[qemu.git] / target-sh4 / helper.c

/*
 *  SH4 emulation
 *
 *  Copyright (c) 2005 Samuel Tardieu
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
 */
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>

#include "cpu.h"
#include "exec-all.h"
#include "hw/sh_intc.h"

#if defined(CONFIG_USER_ONLY)

void do_interrupt (CPUState *env)
{
  env->exception_index = -1;
}

int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
			     int mmu_idx, int is_softmmu)
{
    env->tea = address;
    env->exception_index = 0;
    switch (rw) {
    case 0:
        env->exception_index = 0x0a0;
        break;
    case 1:
        env->exception_index = 0x0c0;
        break;
    case 2:
        env->exception_index = 0x0a0;
        break;
    }
    return 1;
}

target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
{
    return addr;
}

int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
{
    /* For user mode, only U0 area is cachable. */
    return !(addr & 0x80000000);
}

#else /* !CONFIG_USER_ONLY */

#define MMU_OK                   0
#define MMU_ITLB_MISS            (-1)
#define MMU_ITLB_MULTIPLE        (-2)
#define MMU_ITLB_VIOLATION       (-3)
#define MMU_DTLB_MISS_READ       (-4)
#define MMU_DTLB_MISS_WRITE      (-5)
#define MMU_DTLB_INITIAL_WRITE   (-6)
#define MMU_DTLB_VIOLATION_READ  (-7)
#define MMU_DTLB_VIOLATION_WRITE (-8)
#define MMU_DTLB_MULTIPLE        (-9)
#define MMU_DTLB_MISS            (-10)
#define MMU_IADDR_ERROR          (-11)
#define MMU_DADDR_ERROR_READ     (-12)
#define MMU_DADDR_ERROR_WRITE    (-13)

void do_interrupt(CPUState * env)
{
    int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
    int do_exp, irq_vector = env->exception_index;

    /* prioritize exceptions over interrupts */

    do_exp = env->exception_index != -1;
    do_irq = do_irq && (env->exception_index == -1);

    if (env->sr & SR_BL) {
        if (do_exp && env->exception_index != 0x1e0) {
            env->exception_index = 0x000; /* masked exception -> reset */
        }
        if (do_irq && !env->intr_at_halt) {
            return; /* masked */
        }
        env->intr_at_halt = 0;
    }

    if (do_irq) {
        irq_vector = sh_intc_get_pending_vector(env->intc_handle,
						(env->sr >> 4) & 0xf);
        if (irq_vector == -1) {
            return; /* masked */
	}
    }

    if (qemu_loglevel_mask(CPU_LOG_INT)) {
	const char *expname;
	switch (env->exception_index) {
	case 0x0e0:
	    expname = "addr_error";
	    break;
	case 0x040:
	    expname = "tlb_miss";
	    break;
	case 0x0a0:
	    expname = "tlb_violation";
	    break;
	case 0x180:
	    expname = "illegal_instruction";
	    break;
	case 0x1a0:
	    expname = "slot_illegal_instruction";
	    break;
	case 0x800:
	    expname = "fpu_disable";
	    break;
	case 0x820:
	    expname = "slot_fpu";
	    break;
	case 0x100:
	    expname = "data_write";
	    break;
	case 0x060:
	    expname = "dtlb_miss_write";
	    break;
	case 0x0c0:
	    expname = "dtlb_violation_write";
	    break;
	case 0x120:
	    expname = "fpu_exception";
	    break;
	case 0x080:
	    expname = "initial_page_write";
	    break;
	case 0x160:
	    expname = "trapa";
	    break;
	default:
            expname = do_irq ? "interrupt" : "???";
            break;
	}
	qemu_log("exception 0x%03x [%s] raised\n",
		  irq_vector, expname);
	log_cpu_state(env, 0);
    }

    env->ssr = env->sr;
    env->spc = env->pc;
    env->sgr = env->gregs[15];
    env->sr |= SR_BL | SR_MD | SR_RB;

    if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
        /* Branch instruction should be executed again before delay slot. */
	env->spc -= 2;
	/* Clear flags for exception/interrupt routine. */
	env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE);
    }
    if (env->flags & DELAY_SLOT_CLEARME)
        env->flags = 0;

    if (do_exp) {
        env->expevt = env->exception_index;
        switch (env->exception_index) {
        case 0x000:
        case 0x020:
        case 0x140:
            env->sr &= ~SR_FD;
            env->sr |= 0xf << 4; /* IMASK */
            env->pc = 0xa0000000;
            break;
        case 0x040:
        case 0x060:
            env->pc = env->vbr + 0x400;
            break;
        case 0x160:
            env->spc += 2; /* special case for TRAPA */
            /* fall through */
        default:
            env->pc = env->vbr + 0x100;
            break;
        }
        return;
    }

    if (do_irq) {
        env->intevt = irq_vector;
        env->pc = env->vbr + 0x600;
        return;
    }
}

static void update_itlb_use(CPUState * env, int itlbnb)
{
    uint8_t or_mask = 0, and_mask = (uint8_t) - 1;

    switch (itlbnb) {
    case 0:
	and_mask = 0x1f;
	break;
    case 1:
	and_mask = 0xe7;
	or_mask = 0x80;
	break;
    case 2:
	and_mask = 0xfb;
	or_mask = 0x50;
	break;
    case 3:
	or_mask = 0x2c;
	break;
    }

    env->mmucr &= (and_mask << 24) | 0x00ffffff;
    env->mmucr |= (or_mask << 24);
}

static int itlb_replacement(CPUState * env)
{
    if ((env->mmucr & 0xe0000000) == 0xe0000000)
	return 0;
    if ((env->mmucr & 0x98000000) == 0x18000000)
	return 1;
    if ((env->mmucr & 0x54000000) == 0x04000000)
	return 2;
    if ((env->mmucr & 0x2c000000) == 0x00000000)
	return 3;
    assert(0);
}

/* Find the corresponding entry in the right TLB
   Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
*/
static int find_tlb_entry(CPUState * env, target_ulong address,
			  tlb_t * entries, uint8_t nbtlb, int use_asid)
{
    int match = MMU_DTLB_MISS;
    uint32_t start, end;
    uint8_t asid;
    int i;

    asid = env->pteh & 0xff;

    for (i = 0; i < nbtlb; i++) {
	if (!entries[i].v)
	    continue;		/* Invalid entry */
	if (!entries[i].sh && use_asid && entries[i].asid != asid)
	    continue;		/* Bad ASID */
#if 0
	switch (entries[i].sz) {
	case 0:
	    size = 1024;	/* 1kB */
	    break;
	case 1:
	    size = 4 * 1024;	/* 4kB */
	    break;
	case 2:
	    size = 64 * 1024;	/* 64kB */
	    break;
	case 3:
	    size = 1024 * 1024;	/* 1MB */
	    break;
	default:
	    assert(0);
	}
#endif
	start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
	end = start + entries[i].size - 1;
	if (address >= start && address <= end) {	/* Match */
	    if (match != MMU_DTLB_MISS)
		return MMU_DTLB_MULTIPLE;	/* Multiple match */
	    match = i;
	}
    }
    return match;
}

static int same_tlb_entry_exists(const tlb_t * haystack, uint8_t nbtlb,
				 const tlb_t * needle)
{
    int i;
    for (i = 0; i < nbtlb; i++)
        if (!memcmp(&haystack[i], needle, sizeof(tlb_t)))
	    return 1;
    return 0;
}

static void increment_urc(CPUState * env)
{
    uint8_t urb, urc;

    /* Increment URC */
    urb = ((env->mmucr) >> 18) & 0x3f;
    urc = ((env->mmucr) >> 10) & 0x3f;
    urc++;
    if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
	urc = 0;
    env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
}

/* Find itlb entry - update itlb from utlb if necessary and asked for
   Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
   Update the itlb from utlb if update is not 0
*/
static int find_itlb_entry(CPUState * env, target_ulong address,
                           int use_asid, int update)
{
    int e, n;

    e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
    if (e == MMU_DTLB_MULTIPLE)
	e = MMU_ITLB_MULTIPLE;
    else if (e == MMU_DTLB_MISS && update) {
	e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
	if (e >= 0) {
	    tlb_t * ientry;
	    n = itlb_replacement(env);
	    ientry = &env->itlb[n];
	    if (ientry->v) {
		if (!same_tlb_entry_exists(env->utlb, UTLB_SIZE, ientry))
		    tlb_flush_page(env, ientry->vpn << 10);
	    }
	    *ientry = env->utlb[e];
	    e = n;
	} else if (e == MMU_DTLB_MISS)
	    e = MMU_ITLB_MISS;
    } else if (e == MMU_DTLB_MISS)
	e = MMU_ITLB_MISS;
    if (e >= 0)
	update_itlb_use(env, e);
    return e;
}

/* Find utlb entry
   Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
{
    /* per utlb access */
    increment_urc(env);

    /* Return entry */
    return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
}

/* Match address against MMU
   Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
   MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
   MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
   MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
   MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
*/
static int get_mmu_address(CPUState * env, target_ulong * physical,
			   int *prot, target_ulong address,
			   int rw, int access_type)
{
    int use_asid, n;
    tlb_t *matching = NULL;

    use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;

    if (rw == 2) {
	n = find_itlb_entry(env, address, use_asid, 1);
	if (n >= 0) {
	    matching = &env->itlb[n];
	    if ((env->sr & SR_MD) & !(matching->pr & 2))
		n = MMU_ITLB_VIOLATION;
	    else
		*prot = PAGE_READ;
	}
    } else {
	n = find_utlb_entry(env, address, use_asid);
	if (n >= 0) {
	    matching = &env->utlb[n];
	    switch ((matching->pr << 1) | ((env->sr & SR_MD) ? 1 : 0)) {
	    case 0:		/* 000 */
	    case 2:		/* 010 */
		n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
		    MMU_DTLB_VIOLATION_READ;
		break;
	    case 1:		/* 001 */
	    case 4:		/* 100 */
	    case 5:		/* 101 */
		if (rw == 1)
		    n = MMU_DTLB_VIOLATION_WRITE;
		else
		    *prot = PAGE_READ;
		break;
	    case 3:		/* 011 */
	    case 6:		/* 110 */
	    case 7:		/* 111 */
		*prot = (rw == 1)? PAGE_WRITE : PAGE_READ;
		break;
	    }
	} else if (n == MMU_DTLB_MISS) {
	    n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
		MMU_DTLB_MISS_READ;
	}
    }
    if (n >= 0) {
	*physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
	    (address & (matching->size - 1));
	if ((rw == 1) & !matching->d)
	    n = MMU_DTLB_INITIAL_WRITE;
	else
	    n = MMU_OK;
    }
    return n;
}

static int get_physical_address(CPUState * env, target_ulong * physical,
                                int *prot, target_ulong address,
                                int rw, int access_type)
{
    /* P1, P2 and P4 areas do not use translation */
    if ((address >= 0x80000000 && address < 0xc0000000) ||
	address >= 0xe0000000) {
	if (!(env->sr & SR_MD)
	    && (address < 0xe0000000 || address > 0xe4000000)) {
	    /* Unauthorized access in user mode (only store queues are available) */
	    fprintf(stderr, "Unauthorized access\n");
	    if (rw == 0)
		return MMU_DADDR_ERROR_READ;
	    else if (rw == 1)
		return MMU_DADDR_ERROR_WRITE;
	    else
		return MMU_IADDR_ERROR;
	}
	if (address >= 0x80000000 && address < 0xc0000000) {
	    /* Mask upper 3 bits for P1 and P2 areas */
	    *physical = address & 0x1fffffff;
	} else {
	    *physical = address;
	}
	*prot = PAGE_READ | PAGE_WRITE;
	return MMU_OK;
    }

    /* If MMU is disabled, return the corresponding physical page */
    if (!env->mmucr & MMUCR_AT) {
	*physical = address & 0x1FFFFFFF;
	*prot = PAGE_READ | PAGE_WRITE;
	return MMU_OK;
    }

    /* We need to resort to the MMU */
    return get_mmu_address(env, physical, prot, address, rw, access_type);
}

int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
			     int mmu_idx, int is_softmmu)
{
    target_ulong physical, page_offset, page_size;
    int prot, ret, access_type;

    access_type = ACCESS_INT;
    ret =
	get_physical_address(env, &physical, &prot, address, rw,
			     access_type);

    if (ret != MMU_OK) {
	env->tea = address;
	switch (ret) {
	case MMU_ITLB_MISS:
	case MMU_DTLB_MISS_READ:
	    env->exception_index = 0x040;
	    break;
	case MMU_DTLB_MULTIPLE:
	case MMU_ITLB_MULTIPLE:
	    env->exception_index = 0x140;
	    break;
	case MMU_ITLB_VIOLATION:
	    env->exception_index = 0x0a0;
	    break;
	case MMU_DTLB_MISS_WRITE:
	    env->exception_index = 0x060;
	    break;
	case MMU_DTLB_INITIAL_WRITE:
	    env->exception_index = 0x080;
	    break;
	case MMU_DTLB_VIOLATION_READ:
	    env->exception_index = 0x0a0;
	    break;
	case MMU_DTLB_VIOLATION_WRITE:
	    env->exception_index = 0x0c0;
	    break;
	case MMU_IADDR_ERROR:
	case MMU_DADDR_ERROR_READ:
	    env->exception_index = 0x0c0;
	    break;
	case MMU_DADDR_ERROR_WRITE:
	    env->exception_index = 0x100;
	    break;
	default:
	    assert(0);
	}
	return 1;
    }

    page_size = TARGET_PAGE_SIZE;
    page_offset =
	(address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1);
    address = (address & TARGET_PAGE_MASK) + page_offset;
    physical = (physical & TARGET_PAGE_MASK) + page_offset;

    return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu);
}

target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
{
    target_ulong physical;
    int prot;

    get_physical_address(env, &physical, &prot, addr, 0, 0);
    return physical;
}

void cpu_load_tlb(CPUSH4State * env)
{
    int n = cpu_mmucr_urc(env->mmucr);
    tlb_t * entry = &env->utlb[n];

    if (entry->v) {
        /* Overwriting valid entry in utlb. */
        target_ulong address = entry->vpn << 10;
	if (!same_tlb_entry_exists(env->itlb, ITLB_SIZE, entry)) {
	    tlb_flush_page(env, address);
	}
    }

    /* Take values into cpu status from registers. */
    entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
    entry->vpn  = cpu_pteh_vpn(env->pteh);
    entry->v    = (uint8_t)cpu_ptel_v(env->ptel);
    entry->ppn  = cpu_ptel_ppn(env->ptel);
    entry->sz   = (uint8_t)cpu_ptel_sz(env->ptel);
    switch (entry->sz) {
    case 0: /* 00 */
        entry->size = 1024; /* 1K */
        break;
    case 1: /* 01 */
        entry->size = 1024 * 4; /* 4K */
        break;
    case 2: /* 10 */
        entry->size = 1024 * 64; /* 64K */
        break;
    case 3: /* 11 */
        entry->size = 1024 * 1024; /* 1M */
        break;
    default:
        assert(0);
        break;
    }
    entry->sh   = (uint8_t)cpu_ptel_sh(env->ptel);
    entry->c    = (uint8_t)cpu_ptel_c(env->ptel);
    entry->pr   = (uint8_t)cpu_ptel_pr(env->ptel);
    entry->d    = (uint8_t)cpu_ptel_d(env->ptel);
    entry->wt   = (uint8_t)cpu_ptel_wt(env->ptel);
    entry->sa   = (uint8_t)cpu_ptea_sa(env->ptea);
    entry->tc   = (uint8_t)cpu_ptea_tc(env->ptea);
}

void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
				    uint32_t mem_value)
{
    int associate = addr & 0x0000080;
    uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
    uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
    uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
    uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
    int use_asid = (s->mmucr & MMUCR_SV) == 0 || (s->sr & SR_MD) == 0;

    if (associate) {
        int i;
	tlb_t * utlb_match_entry = NULL;
	int needs_tlb_flush = 0;

	/* search UTLB */
	for (i = 0; i < UTLB_SIZE; i++) {
            tlb_t * entry = &s->utlb[i];
            if (!entry->v)
	        continue;

            if (entry->vpn == vpn
                && (!use_asid || entry->asid == asid || entry->sh)) {
	        if (utlb_match_entry) {
		    /* Multiple TLB Exception */
		    s->exception_index = 0x140;
		    s->tea = addr;
		    break;
	        }
		if (entry->v && !v)
		    needs_tlb_flush = 1;
		entry->v = v;
		entry->d = d;
	        utlb_match_entry = entry;
	    }
	    increment_urc(s); /* per utlb access */
	}

	/* search ITLB */
	for (i = 0; i < ITLB_SIZE; i++) {
            tlb_t * entry = &s->itlb[i];
            if (entry->vpn == vpn
                && (!use_asid || entry->asid == asid || entry->sh)) {
	        if (entry->v && !v)
		    needs_tlb_flush = 1;
	        if (utlb_match_entry)
		    *entry = *utlb_match_entry;
	        else
		    entry->v = v;
		break;
	    }
	}

	if (needs_tlb_flush)
	    tlb_flush_page(s, vpn << 10);
        
    } else {
        int index = (addr & 0x00003f00) >> 8;
        tlb_t * entry = &s->utlb[index];
	if (entry->v) {
	    /* Overwriting valid entry in utlb. */
            target_ulong address = entry->vpn << 10;
	    if (!same_tlb_entry_exists(s->itlb, ITLB_SIZE, entry)) {
	        tlb_flush_page(s, address);
	    }
	}
	entry->asid = asid;
	entry->vpn = vpn;
	entry->d = d;
	entry->v = v;
	increment_urc(s);
    }
}

int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
{
    int n;
    int use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;

    /* check area */
    if (env->sr & SR_MD) {
        /* For previledged mode, P2 and P4 area is not cachable. */
        if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
            return 0;
    } else {
        /* For user mode, only U0 area is cachable. */
        if (0x80000000 <= addr)
            return 0;
    }

    /*
     * TODO : Evaluate CCR and check if the cache is on or off.
     *        Now CCR is not in CPUSH4State, but in SH7750State.
     *        When you move the ccr inot CPUSH4State, the code will be
     *        as follows.
     */
#if 0
    /* check if operand cache is enabled or not. */
    if (!(env->ccr & 1))
        return 0;
#endif

    /* if MMU is off, no check for TLB. */
    if (env->mmucr & MMUCR_AT)
        return 1;

    /* check TLB */
    n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
    if (n >= 0)
        return env->itlb[n].c;

    n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
    if (n >= 0)
        return env->utlb[n].c;

    return 0;
}

#endif
Commit	Line	Data
fdf9b3e8 FB	1	/*
fdf9b3e8 FB	2	* SH4 emulation
5fafdf24	3	*
fdf9b3e8 FB	4	* Copyright (c) 2005 Samuel Tardieu
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
fad6cb1a	18	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
fdf9b3e8 FB	19	*/
	20	#include <stdarg.h>
	21	#include <stdlib.h>
	22	#include <stdio.h>
	23	#include <string.h>
	24	#include <inttypes.h>
	25	#include <signal.h>
fdf9b3e8 FB	26
	27	#include "cpu.h"
	28	#include "exec-all.h"
e96e2044	29	#include "hw/sh_intc.h"
fdf9b3e8	30
355fb23d PB	31	#if defined(CONFIG_USER_ONLY)
	32
	33	void do_interrupt (CPUState *env)
	34	{
	35	env->exception_index = -1;
	36	}
	37
	38	int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
6ebbf390	39	int mmu_idx, int is_softmmu)
355fb23d PB	40	{
355fb23d PB	41	env->tea = address;
c3b5bc8a	42	env->exception_index = 0;
355fb23d PB	43	switch (rw) {
	44	case 0:
	45	env->exception_index = 0x0a0;
	46	break;
	47	case 1:
	48	env->exception_index = 0x0c0;
	49	break;
cf7055bd AJ	50	case 2:
	51	env->exception_index = 0x0a0;
	52	break;
355fb23d PB	53	}
	54	return 1;
	55	}
	56
9b3c35e0	57	target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
355fb23d PB	58	{
	59	return addr;
	60	}
	61
3c1adf12 EI	62	int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
	63	{
	64	/* For user mode, only U0 area is cachable. */
679dee3c	65	return !(addr & 0x80000000);
3c1adf12 EI	66	}
3c1adf12 EI	67
355fb23d PB	68	#else /* !CONFIG_USER_ONLY */
355fb23d PB	69
fdf9b3e8 FB	70	#define MMU_OK 0
	71	#define MMU_ITLB_MISS (-1)
	72	#define MMU_ITLB_MULTIPLE (-2)
	73	#define MMU_ITLB_VIOLATION (-3)
	74	#define MMU_DTLB_MISS_READ (-4)
	75	#define MMU_DTLB_MISS_WRITE (-5)
	76	#define MMU_DTLB_INITIAL_WRITE (-6)
	77	#define MMU_DTLB_VIOLATION_READ (-7)
	78	#define MMU_DTLB_VIOLATION_WRITE (-8)
	79	#define MMU_DTLB_MULTIPLE (-9)
	80	#define MMU_DTLB_MISS (-10)
cf7055bd AJ	81	#define MMU_IADDR_ERROR (-11)
	82	#define MMU_DADDR_ERROR_READ (-12)
	83	#define MMU_DADDR_ERROR_WRITE (-13)
fdf9b3e8 FB	84
	85	void do_interrupt(CPUState * env)
	86	{
e96e2044 TS	87	int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
	88	int do_exp, irq_vector = env->exception_index;
	89
	90	/* prioritize exceptions over interrupts */
	91
	92	do_exp = env->exception_index != -1;
	93	do_irq = do_irq && (env->exception_index == -1);
	94
	95	if (env->sr & SR_BL) {
	96	if (do_exp && env->exception_index != 0x1e0) {
	97	env->exception_index = 0x000; /* masked exception -> reset */
	98	}
833ed386	99	if (do_irq && !env->intr_at_halt) {
e96e2044 TS	100	return; /* masked */
e96e2044 TS	101	}
833ed386	102	env->intr_at_halt = 0;
e96e2044 TS	103	}
	104
	105	if (do_irq) {
	106	irq_vector = sh_intc_get_pending_vector(env->intc_handle,
	107	(env->sr >> 4) & 0xf);
	108	if (irq_vector == -1) {
	109	return; /* masked */
	110	}
	111	}
	112
8fec2b8c	113	if (qemu_loglevel_mask(CPU_LOG_INT)) {
fdf9b3e8 FB	114	const char *expname;
	115	switch (env->exception_index) {
	116	case 0x0e0:
	117	expname = "addr_error";
	118	break;
	119	case 0x040:
	120	expname = "tlb_miss";
	121	break;
	122	case 0x0a0:
	123	expname = "tlb_violation";
	124	break;
	125	case 0x180:
	126	expname = "illegal_instruction";
	127	break;
	128	case 0x1a0:
	129	expname = "slot_illegal_instruction";
	130	break;
	131	case 0x800:
	132	expname = "fpu_disable";
	133	break;
	134	case 0x820:
	135	expname = "slot_fpu";
	136	break;
	137	case 0x100:
	138	expname = "data_write";
	139	break;
	140	case 0x060:
	141	expname = "dtlb_miss_write";
	142	break;
	143	case 0x0c0:
	144	expname = "dtlb_violation_write";
	145	break;
	146	case 0x120:
	147	expname = "fpu_exception";
	148	break;
	149	case 0x080:
	150	expname = "initial_page_write";
	151	break;
	152	case 0x160:
	153	expname = "trapa";
	154	break;
	155	default:
e96e2044 TS	156	expname = do_irq ? "interrupt" : "???";
e96e2044 TS	157	break;
fdf9b3e8	158	}
93fcfe39 AL	159	qemu_log("exception 0x%03x [%s] raised\n",
	160	irq_vector, expname);
	161	log_cpu_state(env, 0);
fdf9b3e8 FB	162	}
	163
	164	env->ssr = env->sr;
e96e2044	165	env->spc = env->pc;
fdf9b3e8 FB	166	env->sgr = env->gregs[15];
	167	env->sr \|= SR_BL \| SR_MD \| SR_RB;
	168
274a9e70 AJ	169	if (env->flags & (DELAY_SLOT \| DELAY_SLOT_CONDITIONAL)) {
	170	/* Branch instruction should be executed again before delay slot. */
	171	env->spc -= 2;
	172	/* Clear flags for exception/interrupt routine. */
	173	env->flags &= ~(DELAY_SLOT \| DELAY_SLOT_CONDITIONAL \| DELAY_SLOT_TRUE);
	174	}
	175	if (env->flags & DELAY_SLOT_CLEARME)
	176	env->flags = 0;
	177
e96e2044 TS	178	if (do_exp) {
	179	env->expevt = env->exception_index;
	180	switch (env->exception_index) {
	181	case 0x000:
	182	case 0x020:
	183	case 0x140:
	184	env->sr &= ~SR_FD;
	185	env->sr \|= 0xf << 4; /* IMASK */
	186	env->pc = 0xa0000000;
	187	break;
	188	case 0x040:
	189	case 0x060:
	190	env->pc = env->vbr + 0x400;
	191	break;
	192	case 0x160:
	193	env->spc += 2; /* special case for TRAPA */
	194	/* fall through */
	195	default:
	196	env->pc = env->vbr + 0x100;
	197	break;
	198	}
	199	return;
	200	}
	201
	202	if (do_irq) {
	203	env->intevt = irq_vector;
	204	env->pc = env->vbr + 0x600;
	205	return;
fdf9b3e8 FB	206	}
	207	}
	208
	209	static void update_itlb_use(CPUState * env, int itlbnb)
	210	{
	211	uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
	212
	213	switch (itlbnb) {
	214	case 0:
ea2b542a	215	and_mask = 0x1f;
fdf9b3e8 FB	216	break;
	217	case 1:
	218	and_mask = 0xe7;
	219	or_mask = 0x80;
	220	break;
	221	case 2:
	222	and_mask = 0xfb;
	223	or_mask = 0x50;
	224	break;
	225	case 3:
	226	or_mask = 0x2c;
	227	break;
	228	}
	229
ea2b542a	230	env->mmucr &= (and_mask << 24) \| 0x00ffffff;
fdf9b3e8 FB	231	env->mmucr \|= (or_mask << 24);
	232	}
	233
	234	static int itlb_replacement(CPUState * env)
	235	{
	236	if ((env->mmucr & 0xe0000000) == 0xe0000000)
	237	return 0;
ea2b542a	238	if ((env->mmucr & 0x98000000) == 0x18000000)
fdf9b3e8 FB	239	return 1;
	240	if ((env->mmucr & 0x54000000) == 0x04000000)
	241	return 2;
	242	if ((env->mmucr & 0x2c000000) == 0x00000000)
	243	return 3;
	244	assert(0);
	245	}
	246
	247	/* Find the corresponding entry in the right TLB
	248	Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
	249	*/
	250	static int find_tlb_entry(CPUState * env, target_ulong address,
	251	tlb_t * entries, uint8_t nbtlb, int use_asid)
	252	{
	253	int match = MMU_DTLB_MISS;
	254	uint32_t start, end;
	255	uint8_t asid;
	256	int i;
	257
	258	asid = env->pteh & 0xff;
	259
	260	for (i = 0; i < nbtlb; i++) {
	261	if (!entries[i].v)
	262	continue; /* Invalid entry */
eeda6778	263	if (!entries[i].sh && use_asid && entries[i].asid != asid)
fdf9b3e8 FB	264	continue; /* Bad ASID */
	265	#if 0
	266	switch (entries[i].sz) {
	267	case 0:
	268	size = 1024; /* 1kB */
	269	break;
	270	case 1:
	271	size = 4 * 1024; /* 4kB */
	272	break;
	273	case 2:
	274	size = 64 * 1024; /* 64kB */
	275	break;
	276	case 3:
	277	size = 1024 * 1024; /* 1MB */
	278	break;
	279	default:
	280	assert(0);
	281	}
	282	#endif
	283	start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
	284	end = start + entries[i].size - 1;
	285	if (address >= start && address <= end) { /* Match */
ea2b542a	286	if (match != MMU_DTLB_MISS)
fdf9b3e8 FB	287	return MMU_DTLB_MULTIPLE; /* Multiple match */
	288	match = i;
	289	}
	290	}
	291	return match;
	292	}
	293
29e179bc AJ	294	static int same_tlb_entry_exists(const tlb_t * haystack, uint8_t nbtlb,
	295	const tlb_t * needle)
	296	{
	297	int i;
	298	for (i = 0; i < nbtlb; i++)
	299	if (!memcmp(&haystack[i], needle, sizeof(tlb_t)))
	300	return 1;
	301	return 0;
	302	}
	303
	304	static void increment_urc(CPUState * env)
	305	{
	306	uint8_t urb, urc;
	307
	308	/* Increment URC */
	309	urb = ((env->mmucr) >> 18) & 0x3f;
	310	urc = ((env->mmucr) >> 10) & 0x3f;
	311	urc++;
927e3a4e	312	if ((urb > 0 && urc > urb) \|\| urc > (UTLB_SIZE - 1))
29e179bc AJ	313	urc = 0;
	314	env->mmucr = (env->mmucr & 0xffff03ff) \| (urc << 10);
	315	}
	316
fdf9b3e8 FB	317	/* Find itlb entry - update itlb from utlb if necessary and asked for
	318	Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
	319	Update the itlb from utlb if update is not 0
	320	*/
ef7ec1c1 AJ	321	static int find_itlb_entry(CPUState * env, target_ulong address,
ef7ec1c1 AJ	322	int use_asid, int update)
fdf9b3e8 FB	323	{
	324	int e, n;
	325
	326	e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
	327	if (e == MMU_DTLB_MULTIPLE)
	328	e = MMU_ITLB_MULTIPLE;
	329	else if (e == MMU_DTLB_MISS && update) {
	330	e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
	331	if (e >= 0) {
06afe2c8	332	tlb_t * ientry;
fdf9b3e8	333	n = itlb_replacement(env);
06afe2c8 AJ	334	ientry = &env->itlb[n];
	335	if (ientry->v) {
	336	if (!same_tlb_entry_exists(env->utlb, UTLB_SIZE, ientry))
	337	tlb_flush_page(env, ientry->vpn << 10);
	338	}
	339	*ientry = env->utlb[e];
fdf9b3e8	340	e = n;
ea2b542a AJ	341	} else if (e == MMU_DTLB_MISS)
	342	e = MMU_ITLB_MISS;
	343	} else if (e == MMU_DTLB_MISS)
	344	e = MMU_ITLB_MISS;
fdf9b3e8 FB	345	if (e >= 0)
	346	update_itlb_use(env, e);
	347	return e;
	348	}
	349
	350	/* Find utlb entry
	351	Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
ef7ec1c1	352	static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
fdf9b3e8	353	{
29e179bc AJ	354	/* per utlb access */
29e179bc AJ	355	increment_urc(env);
fdf9b3e8 FB	356
	357	/* Return entry */
	358	return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
	359	}
	360
	361	/* Match address against MMU
	362	Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
	363	MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
	364	MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
cf7055bd AJ	365	MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
cf7055bd AJ	366	MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
fdf9b3e8 FB	367	*/
	368	static int get_mmu_address(CPUState * env, target_ulong * physical,
	369	int *prot, target_ulong address,
	370	int rw, int access_type)
	371	{
cf7055bd	372	int use_asid, n;
fdf9b3e8 FB	373	tlb_t *matching = NULL;
fdf9b3e8 FB	374
06afe2c8	375	use_asid = (env->mmucr & MMUCR_SV) == 0 \|\| (env->sr & SR_MD) == 0;
fdf9b3e8	376
cf7055bd	377	if (rw == 2) {
fdf9b3e8 FB	378	n = find_itlb_entry(env, address, use_asid, 1);
	379	if (n >= 0) {
	380	matching = &env->itlb[n];
	381	if ((env->sr & SR_MD) & !(matching->pr & 2))
	382	n = MMU_ITLB_VIOLATION;
	383	else
	384	*prot = PAGE_READ;
	385	}
	386	} else {
	387	n = find_utlb_entry(env, address, use_asid);
	388	if (n >= 0) {
	389	matching = &env->utlb[n];
	390	switch ((matching->pr << 1) \| ((env->sr & SR_MD) ? 1 : 0)) {
	391	case 0: /* 000 */
	392	case 2: /* 010 */
cf7055bd	393	n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
fdf9b3e8 FB	394	MMU_DTLB_VIOLATION_READ;
	395	break;
	396	case 1: /* 001 */
	397	case 4: /* 100 */
	398	case 5: /* 101 */
cf7055bd	399	if (rw == 1)
fdf9b3e8 FB	400	n = MMU_DTLB_VIOLATION_WRITE;
	401	else
	402	*prot = PAGE_READ;
	403	break;
	404	case 3: /* 011 */
	405	case 6: /* 110 */
	406	case 7: /* 111 */
cf7055bd	407	*prot = (rw == 1)? PAGE_WRITE : PAGE_READ;
fdf9b3e8 FB	408	break;
	409	}
	410	} else if (n == MMU_DTLB_MISS) {
cf7055bd	411	n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
fdf9b3e8 FB	412	MMU_DTLB_MISS_READ;
	413	}
	414	}
	415	if (n >= 0) {
	416	*physical = ((matching->ppn << 10) & ~(matching->size - 1)) \|
	417	(address & (matching->size - 1));
cf7055bd	418	if ((rw == 1) & !matching->d)
fdf9b3e8 FB	419	n = MMU_DTLB_INITIAL_WRITE;
	420	else
	421	n = MMU_OK;
	422	}
	423	return n;
	424	}
	425
ef7ec1c1 AJ	426	static int get_physical_address(CPUState * env, target_ulong * physical,
	427	int *prot, target_ulong address,
	428	int rw, int access_type)
fdf9b3e8 FB	429	{
	430	/* P1, P2 and P4 areas do not use translation */
	431	if ((address >= 0x80000000 && address < 0xc0000000) \|\|
	432	address >= 0xe0000000) {
	433	if (!(env->sr & SR_MD)
	434	&& (address < 0xe0000000 \|\| address > 0xe4000000)) {
	435	/* Unauthorized access in user mode (only store queues are available) */
	436	fprintf(stderr, "Unauthorized access\n");
cf7055bd AJ	437	if (rw == 0)
	438	return MMU_DADDR_ERROR_READ;
	439	else if (rw == 1)
	440	return MMU_DADDR_ERROR_WRITE;
	441	else
	442	return MMU_IADDR_ERROR;
fdf9b3e8	443	}
29e179bc AJ	444	if (address >= 0x80000000 && address < 0xc0000000) {
	445	/* Mask upper 3 bits for P1 and P2 areas */
	446	*physical = address & 0x1fffffff;
29e179bc	447	} else {
29e179bc AJ	448	*physical = address;
29e179bc AJ	449	}
fdf9b3e8 FB	450	*prot = PAGE_READ \| PAGE_WRITE;
	451	return MMU_OK;
	452	}
	453
	454	/* If MMU is disabled, return the corresponding physical page */
	455	if (!env->mmucr & MMUCR_AT) {
	456	*physical = address & 0x1FFFFFFF;
	457	*prot = PAGE_READ \| PAGE_WRITE;
	458	return MMU_OK;
	459	}
	460
	461	/* We need to resort to the MMU */
	462	return get_mmu_address(env, physical, prot, address, rw, access_type);
	463	}
	464
	465	int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
6ebbf390	466	int mmu_idx, int is_softmmu)
fdf9b3e8 FB	467	{
	468	target_ulong physical, page_offset, page_size;
	469	int prot, ret, access_type;
	470
fdf9b3e8 FB	471	access_type = ACCESS_INT;
	472	ret =
	473	get_physical_address(env, &physical, &prot, address, rw,
	474	access_type);
	475
	476	if (ret != MMU_OK) {
	477	env->tea = address;
	478	switch (ret) {
	479	case MMU_ITLB_MISS:
	480	case MMU_DTLB_MISS_READ:
	481	env->exception_index = 0x040;
	482	break;
	483	case MMU_DTLB_MULTIPLE:
	484	case MMU_ITLB_MULTIPLE:
	485	env->exception_index = 0x140;
	486	break;
	487	case MMU_ITLB_VIOLATION:
	488	env->exception_index = 0x0a0;
	489	break;
	490	case MMU_DTLB_MISS_WRITE:
	491	env->exception_index = 0x060;
	492	break;
	493	case MMU_DTLB_INITIAL_WRITE:
	494	env->exception_index = 0x080;
	495	break;
	496	case MMU_DTLB_VIOLATION_READ:
	497	env->exception_index = 0x0a0;
	498	break;
	499	case MMU_DTLB_VIOLATION_WRITE:
	500	env->exception_index = 0x0c0;
	501	break;
cf7055bd AJ	502	case MMU_IADDR_ERROR:
	503	case MMU_DADDR_ERROR_READ:
	504	env->exception_index = 0x0c0;
	505	break;
	506	case MMU_DADDR_ERROR_WRITE:
	507	env->exception_index = 0x100;
	508	break;
fdf9b3e8 FB	509	default:
	510	assert(0);
	511	}
	512	return 1;
	513	}
	514
	515	page_size = TARGET_PAGE_SIZE;
	516	page_offset =
	517	(address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1);
	518	address = (address & TARGET_PAGE_MASK) + page_offset;
	519	physical = (physical & TARGET_PAGE_MASK) + page_offset;
	520
6ebbf390	521	return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu);
fdf9b3e8	522	}
355fb23d	523
9b3c35e0	524	target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
355fb23d PB	525	{
	526	target_ulong physical;
	527	int prot;
	528
cf7055bd	529	get_physical_address(env, &physical, &prot, addr, 0, 0);
355fb23d PB	530	return physical;
	531	}
	532
ef7ec1c1	533	void cpu_load_tlb(CPUSH4State * env)
ea2b542a AJ	534	{
	535	int n = cpu_mmucr_urc(env->mmucr);
	536	tlb_t * entry = &env->utlb[n];
	537
06afe2c8 AJ	538	if (entry->v) {
	539	/* Overwriting valid entry in utlb. */
	540	target_ulong address = entry->vpn << 10;
	541	if (!same_tlb_entry_exists(env->itlb, ITLB_SIZE, entry)) {
	542	tlb_flush_page(env, address);
	543	}
	544	}
	545
ea2b542a AJ	546	/* Take values into cpu status from registers. */
	547	entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
	548	entry->vpn = cpu_pteh_vpn(env->pteh);
	549	entry->v = (uint8_t)cpu_ptel_v(env->ptel);
	550	entry->ppn = cpu_ptel_ppn(env->ptel);
	551	entry->sz = (uint8_t)cpu_ptel_sz(env->ptel);
	552	switch (entry->sz) {
	553	case 0: /* 00 */
	554	entry->size = 1024; /* 1K */
	555	break;
	556	case 1: /* 01 */
	557	entry->size = 1024 * 4; /* 4K */
	558	break;
	559	case 2: /* 10 */
	560	entry->size = 1024 * 64; /* 64K */
	561	break;
	562	case 3: /* 11 */
	563	entry->size = 1024 * 1024; /* 1M */
	564	break;
	565	default:
	566	assert(0);
	567	break;
	568	}
	569	entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
	570	entry->c = (uint8_t)cpu_ptel_c(env->ptel);
	571	entry->pr = (uint8_t)cpu_ptel_pr(env->ptel);
	572	entry->d = (uint8_t)cpu_ptel_d(env->ptel);
	573	entry->wt = (uint8_t)cpu_ptel_wt(env->ptel);
	574	entry->sa = (uint8_t)cpu_ptea_sa(env->ptea);
	575	entry->tc = (uint8_t)cpu_ptea_tc(env->ptea);
	576	}
	577
29e179bc AJ	578	void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
	579	uint32_t mem_value)
	580	{
	581	int associate = addr & 0x0000080;
	582	uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
	583	uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
	584	uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
	585	uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
eeda6778	586	int use_asid = (s->mmucr & MMUCR_SV) == 0 \|\| (s->sr & SR_MD) == 0;
29e179bc AJ	587
	588	if (associate) {
	589	int i;
	590	tlb_t * utlb_match_entry = NULL;
	591	int needs_tlb_flush = 0;
	592
	593	/* search UTLB */
	594	for (i = 0; i < UTLB_SIZE; i++) {
	595	tlb_t * entry = &s->utlb[i];
	596	if (!entry->v)
	597	continue;
	598
eeda6778 AJ	599	if (entry->vpn == vpn
eeda6778 AJ	600	&& (!use_asid \|\| entry->asid == asid \|\| entry->sh)) {
29e179bc AJ	601	if (utlb_match_entry) {
	602	/* Multiple TLB Exception */
	603	s->exception_index = 0x140;
	604	s->tea = addr;
	605	break;
	606	}
	607	if (entry->v && !v)
	608	needs_tlb_flush = 1;
	609	entry->v = v;
	610	entry->d = d;
	611	utlb_match_entry = entry;
	612	}
	613	increment_urc(s); /* per utlb access */
	614	}
	615
	616	/* search ITLB */
	617	for (i = 0; i < ITLB_SIZE; i++) {
	618	tlb_t * entry = &s->itlb[i];
eeda6778 AJ	619	if (entry->vpn == vpn
eeda6778 AJ	620	&& (!use_asid \|\| entry->asid == asid \|\| entry->sh)) {
29e179bc AJ	621	if (entry->v && !v)
	622	needs_tlb_flush = 1;
	623	if (utlb_match_entry)
	624	entry = utlb_match_entry;
	625	else
	626	entry->v = v;
	627	break;
	628	}
	629	}
	630
	631	if (needs_tlb_flush)
	632	tlb_flush_page(s, vpn << 10);
	633
	634	} else {
	635	int index = (addr & 0x00003f00) >> 8;
	636	tlb_t * entry = &s->utlb[index];
	637	if (entry->v) {
	638	/* Overwriting valid entry in utlb. */
	639	target_ulong address = entry->vpn << 10;
	640	if (!same_tlb_entry_exists(s->itlb, ITLB_SIZE, entry)) {
	641	tlb_flush_page(s, address);
	642	}
	643	}
	644	entry->asid = asid;
	645	entry->vpn = vpn;
	646	entry->d = d;
	647	entry->v = v;
	648	increment_urc(s);
	649	}
	650	}
	651
852d481f EI	652	int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
	653	{
	654	int n;
	655	int use_asid = (env->mmucr & MMUCR_SV) == 0 \|\| (env->sr & SR_MD) == 0;
	656
	657	/* check area */
	658	if (env->sr & SR_MD) {
	659	/* For previledged mode, P2 and P4 area is not cachable. */
	660	if ((0xA0000000 <= addr && addr < 0xC0000000) \|\| 0xE0000000 <= addr)
	661	return 0;
	662	} else {
	663	/* For user mode, only U0 area is cachable. */
	664	if (0x80000000 <= addr)
	665	return 0;
	666	}
	667
	668	/*
	669	* TODO : Evaluate CCR and check if the cache is on or off.
	670	* Now CCR is not in CPUSH4State, but in SH7750State.
	671	* When you move the ccr inot CPUSH4State, the code will be
	672	* as follows.
	673	*/
	674	#if 0
	675	/* check if operand cache is enabled or not. */
	676	if (!(env->ccr & 1))
	677	return 0;
	678	#endif
	679
	680	/* if MMU is off, no check for TLB. */
	681	if (env->mmucr & MMUCR_AT)
	682	return 1;
	683
	684	/* check TLB */
	685	n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
	686	if (n >= 0)
	687	return env->itlb[n].c;
	688
	689	n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
	690	if (n >= 0)
	691	return env->utlb[n].c;
	692
	693	return 0;
	694	}
	695
355fb23d	696	#endif