[qemu.git] / target-sh4 / op_helper.c

/*
 *  SH4 emulation
 *
 *  Copyright (c) 2005 Samuel Tardieu
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#include <assert.h>
#include <stdlib.h>
#include "cpu.h"
#include "dyngen-exec.h"
#include "helper.h"

static void cpu_restore_state_from_retaddr(uintptr_t retaddr)
{
    TranslationBlock *tb;

    if (retaddr) {
        tb = tb_find_pc(retaddr);
        if (tb) {
            /* the PC is inside the translated code. It means that we have
               a virtual CPU fault */
            cpu_restore_state(tb, env, retaddr);
        }
    }
}

#ifndef CONFIG_USER_ONLY
#include "softmmu_exec.h"

#define MMUSUFFIX _mmu

#define SHIFT 0
#include "softmmu_template.h"

#define SHIFT 1
#include "softmmu_template.h"

#define SHIFT 2
#include "softmmu_template.h"

#define SHIFT 3
#include "softmmu_template.h"

void tlb_fill(CPUSH4State *env1, target_ulong addr, int is_write, int mmu_idx,
              uintptr_t retaddr)
{
    CPUSH4State *saved_env;
    int ret;

    saved_env = env;
    env = env1;
    ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx);
    if (ret) {
        /* now we have a real cpu fault */
        cpu_restore_state_from_retaddr(retaddr);
        cpu_loop_exit(env);
    }
    env = saved_env;
}

#endif

void helper_ldtlb(void)
{
#ifdef CONFIG_USER_ONLY
    /* XXXXX */
    cpu_abort(env, "Unhandled ldtlb");
#else
    cpu_load_tlb(env);
#endif
}

static inline void raise_exception(int index, uintptr_t retaddr)
{
    env->exception_index = index;
    cpu_restore_state_from_retaddr(retaddr);
    cpu_loop_exit(env);
}

void helper_raise_illegal_instruction(void)
{
    raise_exception(0x180, GETPC());
}

void helper_raise_slot_illegal_instruction(void)
{
    raise_exception(0x1a0, GETPC());
}

void helper_raise_fpu_disable(void)
{
    raise_exception(0x800, GETPC());
}

void helper_raise_slot_fpu_disable(void)
{
    raise_exception(0x820, GETPC());
}

void helper_debug(void)
{
    env->exception_index = EXCP_DEBUG;
    cpu_loop_exit(env);
}

void helper_sleep(uint32_t next_pc)
{
    env->halted = 1;
    env->in_sleep = 1;
    env->exception_index = EXCP_HLT;
    env->pc = next_pc;
    cpu_loop_exit(env);
}

void helper_trapa(uint32_t tra)
{
    env->tra = tra << 2;
    raise_exception(0x160, GETPC());
}

void helper_movcal(uint32_t address, uint32_t value)
{
    if (cpu_sh4_is_cached (env, address))
    {
	memory_content *r = malloc (sizeof(memory_content));
	r->address = address;
	r->value = value;
	r->next = NULL;

	*(env->movcal_backup_tail) = r;
	env->movcal_backup_tail = &(r->next);
    }
}

void helper_discard_movcal_backup(void)
{
    memory_content *current = env->movcal_backup;

    while(current)
    {
	memory_content *next = current->next;
	free (current);
	env->movcal_backup = current = next;
	if (current == NULL)
	    env->movcal_backup_tail = &(env->movcal_backup);
    } 
}

void helper_ocbi(uint32_t address)
{
    memory_content **current = &(env->movcal_backup);
    while (*current)
    {
	uint32_t a = (*current)->address;
	if ((a & ~0x1F) == (address & ~0x1F))
	{
	    memory_content *next = (*current)->next;
	    stl(a, (*current)->value);
	    
	    if (next == NULL)
	    {
		env->movcal_backup_tail = current;
	    }

	    free (*current);
	    *current = next;
	    break;
	}
    }
}

uint32_t helper_addc(uint32_t arg0, uint32_t arg1)
{
    uint32_t tmp0, tmp1;

    tmp1 = arg0 + arg1;
    tmp0 = arg1;
    arg1 = tmp1 + (env->sr & 1);
    if (tmp0 > tmp1)
	env->sr |= SR_T;
    else
	env->sr &= ~SR_T;
    if (tmp1 > arg1)
	env->sr |= SR_T;
    return arg1;
}

uint32_t helper_addv(uint32_t arg0, uint32_t arg1)
{
    uint32_t dest, src, ans;

    if ((int32_t) arg1 >= 0)
	dest = 0;
    else
	dest = 1;
    if ((int32_t) arg0 >= 0)
	src = 0;
    else
	src = 1;
    src += dest;
    arg1 += arg0;
    if ((int32_t) arg1 >= 0)
	ans = 0;
    else
	ans = 1;
    ans += dest;
    if (src == 0 || src == 2) {
	if (ans == 1)
	    env->sr |= SR_T;
	else
	    env->sr &= ~SR_T;
    } else
	env->sr &= ~SR_T;
    return arg1;
}

#define T (env->sr & SR_T)
#define Q (env->sr & SR_Q ? 1 : 0)
#define M (env->sr & SR_M ? 1 : 0)
#define SETT env->sr |= SR_T
#define CLRT env->sr &= ~SR_T
#define SETQ env->sr |= SR_Q
#define CLRQ env->sr &= ~SR_Q
#define SETM env->sr |= SR_M
#define CLRM env->sr &= ~SR_M

uint32_t helper_div1(uint32_t arg0, uint32_t arg1)
{
    uint32_t tmp0, tmp2;
    uint8_t old_q, tmp1 = 0xff;

    //printf("div1 arg0=0x%08x arg1=0x%08x M=%d Q=%d T=%d\n", arg0, arg1, M, Q, T);
    old_q = Q;
    if ((0x80000000 & arg1) != 0)
	SETQ;
    else
	CLRQ;
    tmp2 = arg0;
    arg1 <<= 1;
    arg1 |= T;
    switch (old_q) {
    case 0:
	switch (M) {
	case 0:
	    tmp0 = arg1;
	    arg1 -= tmp2;
	    tmp1 = arg1 > tmp0;
	    switch (Q) {
	    case 0:
		if (tmp1)
		    SETQ;
		else
		    CLRQ;
		break;
	    case 1:
		if (tmp1 == 0)
		    SETQ;
		else
		    CLRQ;
		break;
	    }
	    break;
	case 1:
	    tmp0 = arg1;
	    arg1 += tmp2;
	    tmp1 = arg1 < tmp0;
	    switch (Q) {
	    case 0:
		if (tmp1 == 0)
		    SETQ;
		else
		    CLRQ;
		break;
	    case 1:
		if (tmp1)
		    SETQ;
		else
		    CLRQ;
		break;
	    }
	    break;
	}
	break;
    case 1:
	switch (M) {
	case 0:
	    tmp0 = arg1;
	    arg1 += tmp2;
	    tmp1 = arg1 < tmp0;
	    switch (Q) {
	    case 0:
		if (tmp1)
		    SETQ;
		else
		    CLRQ;
		break;
	    case 1:
		if (tmp1 == 0)
		    SETQ;
		else
		    CLRQ;
		break;
	    }
	    break;
	case 1:
	    tmp0 = arg1;
	    arg1 -= tmp2;
	    tmp1 = arg1 > tmp0;
	    switch (Q) {
	    case 0:
		if (tmp1 == 0)
		    SETQ;
		else
		    CLRQ;
		break;
	    case 1:
		if (tmp1)
		    SETQ;
		else
		    CLRQ;
		break;
	    }
	    break;
	}
	break;
    }
    if (Q == M)
	SETT;
    else
	CLRT;
    //printf("Output: arg1=0x%08x M=%d Q=%d T=%d\n", arg1, M, Q, T);
    return arg1;
}

void helper_macl(uint32_t arg0, uint32_t arg1)
{
    int64_t res;

    res = ((uint64_t) env->mach << 32) | env->macl;
    res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1;
    env->mach = (res >> 32) & 0xffffffff;
    env->macl = res & 0xffffffff;
    if (env->sr & SR_S) {
	if (res < 0)
	    env->mach |= 0xffff0000;
	else
	    env->mach &= 0x00007fff;
    }
}

void helper_macw(uint32_t arg0, uint32_t arg1)
{
    int64_t res;

    res = ((uint64_t) env->mach << 32) | env->macl;
    res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1;
    env->mach = (res >> 32) & 0xffffffff;
    env->macl = res & 0xffffffff;
    if (env->sr & SR_S) {
	if (res < -0x80000000) {
	    env->mach = 1;
	    env->macl = 0x80000000;
	} else if (res > 0x000000007fffffff) {
	    env->mach = 1;
	    env->macl = 0x7fffffff;
	}
    }
}

uint32_t helper_subc(uint32_t arg0, uint32_t arg1)
{
    uint32_t tmp0, tmp1;

    tmp1 = arg1 - arg0;
    tmp0 = arg1;
    arg1 = tmp1 - (env->sr & SR_T);
    if (tmp0 < tmp1)
	env->sr |= SR_T;
    else
	env->sr &= ~SR_T;
    if (tmp1 < arg1)
	env->sr |= SR_T;
    return arg1;
}

uint32_t helper_subv(uint32_t arg0, uint32_t arg1)
{
    int32_t dest, src, ans;

    if ((int32_t) arg1 >= 0)
	dest = 0;
    else
	dest = 1;
    if ((int32_t) arg0 >= 0)
	src = 0;
    else
	src = 1;
    src += dest;
    arg1 -= arg0;
    if ((int32_t) arg1 >= 0)
	ans = 0;
    else
	ans = 1;
    ans += dest;
    if (src == 1) {
	if (ans == 1)
	    env->sr |= SR_T;
	else
	    env->sr &= ~SR_T;
    } else
	env->sr &= ~SR_T;
    return arg1;
}

static inline void set_t(void)
{
    env->sr |= SR_T;
}

static inline void clr_t(void)
{
    env->sr &= ~SR_T;
}

void helper_ld_fpscr(uint32_t val)
{
    env->fpscr = val & FPSCR_MASK;
    if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
	set_float_rounding_mode(float_round_to_zero, &env->fp_status);
    } else {
	set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
    }
    set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
}

static void update_fpscr(uintptr_t retaddr)
{
    int xcpt, cause, enable;

    xcpt = get_float_exception_flags(&env->fp_status);

    /* Clear the flag entries */
    env->fpscr &= ~FPSCR_FLAG_MASK;

    if (unlikely(xcpt)) {
        if (xcpt & float_flag_invalid) {
            env->fpscr |= FPSCR_FLAG_V;
        }
        if (xcpt & float_flag_divbyzero) {
            env->fpscr |= FPSCR_FLAG_Z;
        }
        if (xcpt & float_flag_overflow) {
            env->fpscr |= FPSCR_FLAG_O;
        }
        if (xcpt & float_flag_underflow) {
            env->fpscr |= FPSCR_FLAG_U;
        }
        if (xcpt & float_flag_inexact) {
            env->fpscr |= FPSCR_FLAG_I;
        }

        /* Accumulate in cause entries */
        env->fpscr |= (env->fpscr & FPSCR_FLAG_MASK)
                      << (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT);

        /* Generate an exception if enabled */
        cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
        enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
        if (cause & enable) {
            cpu_restore_state_from_retaddr(retaddr);
            env->exception_index = 0x120;
            cpu_loop_exit(env);
        }
    }
}

float32 helper_fabs_FT(float32 t0)
{
    return float32_abs(t0);
}

float64 helper_fabs_DT(float64 t0)
{
    return float64_abs(t0);
}

float32 helper_fadd_FT(float32 t0, float32 t1)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float32_add(t0, t1, &env->fp_status);
    update_fpscr(GETPC());
    return t0;
}

float64 helper_fadd_DT(float64 t0, float64 t1)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float64_add(t0, t1, &env->fp_status);
    update_fpscr(GETPC());
    return t0;
}

void helper_fcmp_eq_FT(float32 t0, float32 t1)
{
    int relation;

    set_float_exception_flags(0, &env->fp_status);
    relation = float32_compare(t0, t1, &env->fp_status);
    if (unlikely(relation == float_relation_unordered)) {
        update_fpscr(GETPC());
    } else if (relation == float_relation_equal) {
	set_t();
    } else {
	clr_t();
    }
}

void helper_fcmp_eq_DT(float64 t0, float64 t1)
{
    int relation;

    set_float_exception_flags(0, &env->fp_status);
    relation = float64_compare(t0, t1, &env->fp_status);
    if (unlikely(relation == float_relation_unordered)) {
        update_fpscr(GETPC());
    } else if (relation == float_relation_equal) {
	set_t();
    } else {
	clr_t();
    }
}

void helper_fcmp_gt_FT(float32 t0, float32 t1)
{
    int relation;

    set_float_exception_flags(0, &env->fp_status);
    relation = float32_compare(t0, t1, &env->fp_status);
    if (unlikely(relation == float_relation_unordered)) {
        update_fpscr(GETPC());
    } else if (relation == float_relation_greater) {
	set_t();
    } else {
	clr_t();
    }
}

void helper_fcmp_gt_DT(float64 t0, float64 t1)
{
    int relation;

    set_float_exception_flags(0, &env->fp_status);
    relation = float64_compare(t0, t1, &env->fp_status);
    if (unlikely(relation == float_relation_unordered)) {
        update_fpscr(GETPC());
    } else if (relation == float_relation_greater) {
	set_t();
    } else {
	clr_t();
    }
}

float64 helper_fcnvsd_FT_DT(float32 t0)
{
    float64 ret;
    set_float_exception_flags(0, &env->fp_status);
    ret = float32_to_float64(t0, &env->fp_status);
    update_fpscr(GETPC());
    return ret;
}

float32 helper_fcnvds_DT_FT(float64 t0)
{
    float32 ret;
    set_float_exception_flags(0, &env->fp_status);
    ret = float64_to_float32(t0, &env->fp_status);
    update_fpscr(GETPC());
    return ret;
}

float32 helper_fdiv_FT(float32 t0, float32 t1)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float32_div(t0, t1, &env->fp_status);
    update_fpscr(GETPC());
    return t0;
}

float64 helper_fdiv_DT(float64 t0, float64 t1)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float64_div(t0, t1, &env->fp_status);
    update_fpscr(GETPC());
    return t0;
}

float32 helper_float_FT(uint32_t t0)
{
    float32 ret;
    set_float_exception_flags(0, &env->fp_status);
    ret = int32_to_float32(t0, &env->fp_status);
    update_fpscr(GETPC());
    return ret;
}

float64 helper_float_DT(uint32_t t0)
{
    float64 ret;
    set_float_exception_flags(0, &env->fp_status);
    ret = int32_to_float64(t0, &env->fp_status);
    update_fpscr(GETPC());
    return ret;
}

float32 helper_fmac_FT(float32 t0, float32 t1, float32 t2)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float32_mul(t0, t1, &env->fp_status);
    t0 = float32_add(t0, t2, &env->fp_status);
    update_fpscr(GETPC());
    return t0;
}

float32 helper_fmul_FT(float32 t0, float32 t1)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float32_mul(t0, t1, &env->fp_status);
    update_fpscr(GETPC());
    return t0;
}

float64 helper_fmul_DT(float64 t0, float64 t1)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float64_mul(t0, t1, &env->fp_status);
    update_fpscr(GETPC());
    return t0;
}

float32 helper_fneg_T(float32 t0)
{
    return float32_chs(t0);
}

float32 helper_fsqrt_FT(float32 t0)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float32_sqrt(t0, &env->fp_status);
    update_fpscr(GETPC());
    return t0;
}

float64 helper_fsqrt_DT(float64 t0)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float64_sqrt(t0, &env->fp_status);
    update_fpscr(GETPC());
    return t0;
}

float32 helper_fsub_FT(float32 t0, float32 t1)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float32_sub(t0, t1, &env->fp_status);
    update_fpscr(GETPC());
    return t0;
}

float64 helper_fsub_DT(float64 t0, float64 t1)
{
    set_float_exception_flags(0, &env->fp_status);
    t0 = float64_sub(t0, t1, &env->fp_status);
    update_fpscr(GETPC());
    return t0;
}

uint32_t helper_ftrc_FT(float32 t0)
{
    uint32_t ret;
    set_float_exception_flags(0, &env->fp_status);
    ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
    update_fpscr(GETPC());
    return ret;
}

uint32_t helper_ftrc_DT(float64 t0)
{
    uint32_t ret;
    set_float_exception_flags(0, &env->fp_status);
    ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
    update_fpscr(GETPC());
    return ret;
}

void helper_fipr(uint32_t m, uint32_t n)
{
    int bank, i;
    float32 r, p;

    bank = (env->sr & FPSCR_FR) ? 16 : 0;
    r = float32_zero;
    set_float_exception_flags(0, &env->fp_status);

    for (i = 0 ; i < 4 ; i++) {
        p = float32_mul(env->fregs[bank + m + i],
                        env->fregs[bank + n + i],
                        &env->fp_status);
        r = float32_add(r, p, &env->fp_status);
    }
    update_fpscr(GETPC());

    env->fregs[bank + n + 3] = r;
}

void helper_ftrv(uint32_t n)
{
    int bank_matrix, bank_vector;
    int i, j;
    float32 r[4];
    float32 p;

    bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
    bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
    set_float_exception_flags(0, &env->fp_status);
    for (i = 0 ; i < 4 ; i++) {
        r[i] = float32_zero;
        for (j = 0 ; j < 4 ; j++) {
            p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
                            env->fregs[bank_vector + j],
                            &env->fp_status);
            r[i] = float32_add(r[i], p, &env->fp_status);
        }
    }
    update_fpscr(GETPC());

    for (i = 0 ; i < 4 ; i++) {
        env->fregs[bank_vector + i] = r[i];
    }
}
Commit	Line	Data
fdf9b3e8 FB	1	/*
fdf9b3e8 FB	2	* SH4 emulation
5fafdf24	3	*
fdf9b3e8 FB	4	* Copyright (c) 2005 Samuel Tardieu
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
fdf9b3e8 FB	18	*/
fdf9b3e8 FB	19	#include <assert.h>
852d481f	20	#include <stdlib.h>
3e457172 BS	21	#include "cpu.h"
3e457172 BS	22	#include "dyngen-exec.h"
a7812ae4	23	#include "helper.h"
fdf9b3e8	24
20503968	25	static void cpu_restore_state_from_retaddr(uintptr_t retaddr)
21829e9b AJ	26	{
21829e9b AJ	27	TranslationBlock *tb;
21829e9b AJ	28
21829e9b AJ	29	if (retaddr) {
20503968	30	tb = tb_find_pc(retaddr);
21829e9b AJ	31	if (tb) {
	32	/* the PC is inside the translated code. It means that we have
	33	a virtual CPU fault */
20503968	34	cpu_restore_state(tb, env, retaddr);
21829e9b AJ	35	}
	36	}
	37	}
	38
fdf9b3e8	39	#ifndef CONFIG_USER_ONLY
3e457172	40	#include "softmmu_exec.h"
fdf9b3e8 FB	41
fdf9b3e8 FB	42	#define MMUSUFFIX _mmu
fdf9b3e8 FB	43
	44	#define SHIFT 0
	45	#include "softmmu_template.h"
	46
	47	#define SHIFT 1
	48	#include "softmmu_template.h"
	49
	50	#define SHIFT 2
	51	#include "softmmu_template.h"
	52
	53	#define SHIFT 3
	54	#include "softmmu_template.h"
	55
73e5716c	56	void tlb_fill(CPUSH4State *env1, target_ulong addr, int is_write, int mmu_idx,
20503968	57	uintptr_t retaddr)
fdf9b3e8	58	{
73e5716c	59	CPUSH4State *saved_env;
fdf9b3e8 FB	60	int ret;
fdf9b3e8 FB	61
fdf9b3e8	62	saved_env = env;
bccd9ec5	63	env = env1;
97b348e7	64	ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx);
fdf9b3e8	65	if (ret) {
21829e9b AJ	66	/* now we have a real cpu fault */
21829e9b AJ	67	cpu_restore_state_from_retaddr(retaddr);
1162c041	68	cpu_loop_exit(env);
fdf9b3e8 FB	69	}
	70	env = saved_env;
	71	}
	72
	73	#endif
	74
ea2b542a AJ	75	void helper_ldtlb(void)
	76	{
	77	#ifdef CONFIG_USER_ONLY
	78	/* XXXXX */
43dc2a64	79	cpu_abort(env, "Unhandled ldtlb");
ea2b542a AJ	80	#else
	81	cpu_load_tlb(env);
	82	#endif
	83	}
	84
20503968	85	static inline void raise_exception(int index, uintptr_t retaddr)
e6afc2f4	86	{
fd4bab10 AJ	87	env->exception_index = index;
fd4bab10 AJ	88	cpu_restore_state_from_retaddr(retaddr);
1162c041	89	cpu_loop_exit(env);
e6afc2f4 AJ	90	}
e6afc2f4 AJ	91
fd4bab10 AJ	92	void helper_raise_illegal_instruction(void)
	93	{
	94	raise_exception(0x180, GETPC());
	95	}
	96
e6afc2f4 AJ	97	void helper_raise_slot_illegal_instruction(void)
e6afc2f4 AJ	98	{
fd4bab10	99	raise_exception(0x1a0, GETPC());
e6afc2f4 AJ	100	}
e6afc2f4 AJ	101
d8299bcc AJ	102	void helper_raise_fpu_disable(void)
d8299bcc AJ	103	{
fd4bab10	104	raise_exception(0x800, GETPC());
d8299bcc AJ	105	}
	106
	107	void helper_raise_slot_fpu_disable(void)
	108	{
fd4bab10	109	raise_exception(0x820, GETPC());
d8299bcc AJ	110	}
d8299bcc AJ	111
e6afc2f4 AJ	112	void helper_debug(void)
	113	{
	114	env->exception_index = EXCP_DEBUG;
1162c041	115	cpu_loop_exit(env);
e6afc2f4 AJ	116	}
e6afc2f4 AJ	117
f24f381b	118	void helper_sleep(uint32_t next_pc)
e6afc2f4 AJ	119	{
e6afc2f4 AJ	120	env->halted = 1;
efac4154	121	env->in_sleep = 1;
e6afc2f4	122	env->exception_index = EXCP_HLT;
f24f381b	123	env->pc = next_pc;
1162c041	124	cpu_loop_exit(env);
e6afc2f4 AJ	125	}
	126
	127	void helper_trapa(uint32_t tra)
	128	{
	129	env->tra = tra << 2;
fd4bab10	130	raise_exception(0x160, GETPC());
e6afc2f4 AJ	131	}
e6afc2f4 AJ	132
852d481f EI	133	void helper_movcal(uint32_t address, uint32_t value)
	134	{
	135	if (cpu_sh4_is_cached (env, address))
	136	{
	137	memory_content *r = malloc (sizeof(memory_content));
	138	r->address = address;
	139	r->value = value;
	140	r->next = NULL;
	141
	142	*(env->movcal_backup_tail) = r;
	143	env->movcal_backup_tail = &(r->next);
	144	}
	145	}
	146
	147	void helper_discard_movcal_backup(void)
	148	{
	149	memory_content *current = env->movcal_backup;
	150
	151	while(current)
	152	{
	153	memory_content *next = current->next;
	154	free (current);
	155	env->movcal_backup = current = next;
b9d38e95	156	if (current == NULL)
852d481f EI	157	env->movcal_backup_tail = &(env->movcal_backup);
	158	}
	159	}
	160
	161	void helper_ocbi(uint32_t address)
	162	{
	163	memory_content **current = &(env->movcal_backup);
	164	while (*current)
	165	{
	166	uint32_t a = (*current)->address;
	167	if ((a & ~0x1F) == (address & ~0x1F))
	168	{
	169	memory_content next = (current)->next;
	170	stl(a, (*current)->value);
	171
b9d38e95	172	if (next == NULL)
852d481f EI	173	{
	174	env->movcal_backup_tail = current;
	175	}
	176
	177	free (*current);
	178	*current = next;
	179	break;
	180	}
	181	}
	182	}
	183
6f06939b	184	uint32_t helper_addc(uint32_t arg0, uint32_t arg1)
fdf9b3e8 FB	185	{
	186	uint32_t tmp0, tmp1;
	187
6f06939b AJ	188	tmp1 = arg0 + arg1;
	189	tmp0 = arg1;
	190	arg1 = tmp1 + (env->sr & 1);
fdf9b3e8 FB	191	if (tmp0 > tmp1)
	192	env->sr \|= SR_T;
	193	else
	194	env->sr &= ~SR_T;
6f06939b	195	if (tmp1 > arg1)
fdf9b3e8	196	env->sr \|= SR_T;
6f06939b	197	return arg1;
fdf9b3e8 FB	198	}
fdf9b3e8 FB	199
6f06939b	200	uint32_t helper_addv(uint32_t arg0, uint32_t arg1)
fdf9b3e8 FB	201	{
	202	uint32_t dest, src, ans;
	203
6f06939b	204	if ((int32_t) arg1 >= 0)
fdf9b3e8 FB	205	dest = 0;
	206	else
	207	dest = 1;
6f06939b	208	if ((int32_t) arg0 >= 0)
fdf9b3e8 FB	209	src = 0;
	210	else
	211	src = 1;
	212	src += dest;
6f06939b AJ	213	arg1 += arg0;
6f06939b AJ	214	if ((int32_t) arg1 >= 0)
fdf9b3e8 FB	215	ans = 0;
	216	else
	217	ans = 1;
	218	ans += dest;
	219	if (src == 0 \|\| src == 2) {
	220	if (ans == 1)
	221	env->sr \|= SR_T;
	222	else
	223	env->sr &= ~SR_T;
	224	} else
	225	env->sr &= ~SR_T;
6f06939b	226	return arg1;
fdf9b3e8 FB	227	}
	228
	229	#define T (env->sr & SR_T)
	230	#define Q (env->sr & SR_Q ? 1 : 0)
	231	#define M (env->sr & SR_M ? 1 : 0)
	232	#define SETT env->sr \|= SR_T
	233	#define CLRT env->sr &= ~SR_T
	234	#define SETQ env->sr \|= SR_Q
	235	#define CLRQ env->sr &= ~SR_Q
	236	#define SETM env->sr \|= SR_M
	237	#define CLRM env->sr &= ~SR_M
	238
69d6275b	239	uint32_t helper_div1(uint32_t arg0, uint32_t arg1)
fdf9b3e8 FB	240	{
	241	uint32_t tmp0, tmp2;
	242	uint8_t old_q, tmp1 = 0xff;
	243
69d6275b	244	//printf("div1 arg0=0x%08x arg1=0x%08x M=%d Q=%d T=%d\n", arg0, arg1, M, Q, T);
fdf9b3e8	245	old_q = Q;
69d6275b	246	if ((0x80000000 & arg1) != 0)
fdf9b3e8 FB	247	SETQ;
	248	else
	249	CLRQ;
69d6275b AJ	250	tmp2 = arg0;
	251	arg1 <<= 1;
	252	arg1 \|= T;
fdf9b3e8 FB	253	switch (old_q) {
	254	case 0:
	255	switch (M) {
	256	case 0:
69d6275b AJ	257	tmp0 = arg1;
	258	arg1 -= tmp2;
	259	tmp1 = arg1 > tmp0;
fdf9b3e8 FB	260	switch (Q) {
	261	case 0:
	262	if (tmp1)
	263	SETQ;
	264	else
	265	CLRQ;
	266	break;
	267	case 1:
	268	if (tmp1 == 0)
	269	SETQ;
	270	else
	271	CLRQ;
	272	break;
	273	}
	274	break;
	275	case 1:
69d6275b AJ	276	tmp0 = arg1;
	277	arg1 += tmp2;
	278	tmp1 = arg1 < tmp0;
fdf9b3e8 FB	279	switch (Q) {
	280	case 0:
	281	if (tmp1 == 0)
	282	SETQ;
	283	else
	284	CLRQ;
	285	break;
	286	case 1:
	287	if (tmp1)
	288	SETQ;
	289	else
	290	CLRQ;
	291	break;
	292	}
	293	break;
	294	}
	295	break;
	296	case 1:
	297	switch (M) {
	298	case 0:
69d6275b AJ	299	tmp0 = arg1;
	300	arg1 += tmp2;
	301	tmp1 = arg1 < tmp0;
fdf9b3e8 FB	302	switch (Q) {
	303	case 0:
	304	if (tmp1)
	305	SETQ;
	306	else
	307	CLRQ;
	308	break;
	309	case 1:
	310	if (tmp1 == 0)
	311	SETQ;
	312	else
	313	CLRQ;
	314	break;
	315	}
	316	break;
	317	case 1:
69d6275b AJ	318	tmp0 = arg1;
	319	arg1 -= tmp2;
	320	tmp1 = arg1 > tmp0;
fdf9b3e8 FB	321	switch (Q) {
	322	case 0:
	323	if (tmp1 == 0)
	324	SETQ;
	325	else
	326	CLRQ;
	327	break;
	328	case 1:
	329	if (tmp1)
	330	SETQ;
	331	else
	332	CLRQ;
	333	break;
	334	}
	335	break;
	336	}
	337	break;
	338	}
	339	if (Q == M)
	340	SETT;
	341	else
	342	CLRT;
69d6275b AJ	343	//printf("Output: arg1=0x%08x M=%d Q=%d T=%d\n", arg1, M, Q, T);
69d6275b AJ	344	return arg1;
fdf9b3e8 FB	345	}
fdf9b3e8 FB	346
6f06939b	347	void helper_macl(uint32_t arg0, uint32_t arg1)
fdf9b3e8 FB	348	{
	349	int64_t res;
	350
	351	res = ((uint64_t) env->mach << 32) \| env->macl;
6f06939b	352	res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1;
fdf9b3e8 FB	353	env->mach = (res >> 32) & 0xffffffff;
	354	env->macl = res & 0xffffffff;
	355	if (env->sr & SR_S) {
	356	if (res < 0)
	357	env->mach \|= 0xffff0000;
	358	else
	359	env->mach &= 0x00007fff;
	360	}
	361	}
	362
6f06939b	363	void helper_macw(uint32_t arg0, uint32_t arg1)
fdf9b3e8 FB	364	{
	365	int64_t res;
	366
	367	res = ((uint64_t) env->mach << 32) \| env->macl;
6f06939b	368	res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1;
fdf9b3e8 FB	369	env->mach = (res >> 32) & 0xffffffff;
	370	env->macl = res & 0xffffffff;
	371	if (env->sr & SR_S) {
	372	if (res < -0x80000000) {
	373	env->mach = 1;
	374	env->macl = 0x80000000;
	375	} else if (res > 0x000000007fffffff) {
	376	env->mach = 1;
	377	env->macl = 0x7fffffff;
	378	}
	379	}
	380	}
	381
6f06939b	382	uint32_t helper_subc(uint32_t arg0, uint32_t arg1)
fdf9b3e8 FB	383	{
	384	uint32_t tmp0, tmp1;
	385
6f06939b AJ	386	tmp1 = arg1 - arg0;
	387	tmp0 = arg1;
	388	arg1 = tmp1 - (env->sr & SR_T);
fdf9b3e8 FB	389	if (tmp0 < tmp1)
	390	env->sr \|= SR_T;
	391	else
	392	env->sr &= ~SR_T;
6f06939b	393	if (tmp1 < arg1)
fdf9b3e8	394	env->sr \|= SR_T;
6f06939b	395	return arg1;
fdf9b3e8 FB	396	}
fdf9b3e8 FB	397
6f06939b	398	uint32_t helper_subv(uint32_t arg0, uint32_t arg1)
fdf9b3e8 FB	399	{
	400	int32_t dest, src, ans;
	401
6f06939b	402	if ((int32_t) arg1 >= 0)
fdf9b3e8 FB	403	dest = 0;
	404	else
	405	dest = 1;
6f06939b	406	if ((int32_t) arg0 >= 0)
fdf9b3e8 FB	407	src = 0;
	408	else
	409	src = 1;
	410	src += dest;
6f06939b AJ	411	arg1 -= arg0;
6f06939b AJ	412	if ((int32_t) arg1 >= 0)
fdf9b3e8 FB	413	ans = 0;
	414	else
	415	ans = 1;
	416	ans += dest;
	417	if (src == 1) {
	418	if (ans == 1)
	419	env->sr \|= SR_T;
	420	else
	421	env->sr &= ~SR_T;
	422	} else
	423	env->sr &= ~SR_T;
6f06939b	424	return arg1;
fdf9b3e8 FB	425	}
fdf9b3e8 FB	426
cc4ba6a9 AJ	427	static inline void set_t(void)
	428	{
	429	env->sr \|= SR_T;
	430	}
	431
	432	static inline void clr_t(void)
	433	{
	434	env->sr &= ~SR_T;
	435	}
	436
390af821 AJ	437	void helper_ld_fpscr(uint32_t val)
390af821 AJ	438	{
26ac1ea5 AJ	439	env->fpscr = val & FPSCR_MASK;
26ac1ea5 AJ	440	if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
390af821	441	set_float_rounding_mode(float_round_to_zero, &env->fp_status);
26ac1ea5	442	} else {
390af821	443	set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
26ac1ea5	444	}
a0d4ac33	445	set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
390af821	446	}
cc4ba6a9	447
20503968	448	static void update_fpscr(uintptr_t retaddr)
21829e9b AJ	449	{
	450	int xcpt, cause, enable;
	451
	452	xcpt = get_float_exception_flags(&env->fp_status);
	453
	454	/* Clear the flag entries */
	455	env->fpscr &= ~FPSCR_FLAG_MASK;
	456
	457	if (unlikely(xcpt)) {
	458	if (xcpt & float_flag_invalid) {
	459	env->fpscr \|= FPSCR_FLAG_V;
	460	}
	461	if (xcpt & float_flag_divbyzero) {
	462	env->fpscr \|= FPSCR_FLAG_Z;
	463	}
	464	if (xcpt & float_flag_overflow) {
	465	env->fpscr \|= FPSCR_FLAG_O;
	466	}
	467	if (xcpt & float_flag_underflow) {
	468	env->fpscr \|= FPSCR_FLAG_U;
	469	}
	470	if (xcpt & float_flag_inexact) {
	471	env->fpscr \|= FPSCR_FLAG_I;
	472	}
	473
	474	/* Accumulate in cause entries */
	475	env->fpscr \|= (env->fpscr & FPSCR_FLAG_MASK)
	476	<< (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT);
	477
	478	/* Generate an exception if enabled */
	479	cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
	480	enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
	481	if (cause & enable) {
	482	cpu_restore_state_from_retaddr(retaddr);
	483	env->exception_index = 0x120;
1162c041	484	cpu_loop_exit(env);
21829e9b AJ	485	}
	486	}
	487	}
	488
d6c424c5	489	float32 helper_fabs_FT(float32 t0)
cc4ba6a9	490	{
d6c424c5	491	return float32_abs(t0);
cc4ba6a9 AJ	492	}
cc4ba6a9 AJ	493
d6c424c5	494	float64 helper_fabs_DT(float64 t0)
cc4ba6a9	495	{
d6c424c5	496	return float64_abs(t0);
cc4ba6a9 AJ	497	}
cc4ba6a9 AJ	498
d6c424c5	499	float32 helper_fadd_FT(float32 t0, float32 t1)
cc4ba6a9	500	{
21829e9b	501	set_float_exception_flags(0, &env->fp_status);
d6c424c5	502	t0 = float32_add(t0, t1, &env->fp_status);
21829e9b	503	update_fpscr(GETPC());
d6c424c5	504	return t0;
cc4ba6a9 AJ	505	}
cc4ba6a9 AJ	506
d6c424c5	507	float64 helper_fadd_DT(float64 t0, float64 t1)
cc4ba6a9	508	{
21829e9b	509	set_float_exception_flags(0, &env->fp_status);
d6c424c5	510	t0 = float64_add(t0, t1, &env->fp_status);
21829e9b	511	update_fpscr(GETPC());
d6c424c5	512	return t0;
cc4ba6a9 AJ	513	}
cc4ba6a9 AJ	514
d6c424c5	515	void helper_fcmp_eq_FT(float32 t0, float32 t1)
cc4ba6a9	516	{
21829e9b	517	int relation;
9850d1e8	518
21829e9b	519	set_float_exception_flags(0, &env->fp_status);
d6c424c5	520	relation = float32_compare(t0, t1, &env->fp_status);
21829e9b AJ	521	if (unlikely(relation == float_relation_unordered)) {
	522	update_fpscr(GETPC());
	523	} else if (relation == float_relation_equal) {
cc4ba6a9	524	set_t();
21829e9b	525	} else {
cc4ba6a9	526	clr_t();
21829e9b	527	}
cc4ba6a9 AJ	528	}
cc4ba6a9 AJ	529
d6c424c5	530	void helper_fcmp_eq_DT(float64 t0, float64 t1)
cc4ba6a9	531	{
21829e9b	532	int relation;
9850d1e8	533
21829e9b	534	set_float_exception_flags(0, &env->fp_status);
d6c424c5	535	relation = float64_compare(t0, t1, &env->fp_status);
21829e9b AJ	536	if (unlikely(relation == float_relation_unordered)) {
	537	update_fpscr(GETPC());
	538	} else if (relation == float_relation_equal) {
cc4ba6a9	539	set_t();
21829e9b	540	} else {
cc4ba6a9	541	clr_t();
21829e9b	542	}
cc4ba6a9 AJ	543	}
cc4ba6a9 AJ	544
d6c424c5	545	void helper_fcmp_gt_FT(float32 t0, float32 t1)
cc4ba6a9	546	{
21829e9b	547	int relation;
9850d1e8	548
21829e9b	549	set_float_exception_flags(0, &env->fp_status);
d6c424c5	550	relation = float32_compare(t0, t1, &env->fp_status);
21829e9b AJ	551	if (unlikely(relation == float_relation_unordered)) {
	552	update_fpscr(GETPC());
	553	} else if (relation == float_relation_greater) {
cc4ba6a9	554	set_t();
21829e9b	555	} else {
cc4ba6a9	556	clr_t();
21829e9b	557	}
cc4ba6a9 AJ	558	}
cc4ba6a9 AJ	559
d6c424c5	560	void helper_fcmp_gt_DT(float64 t0, float64 t1)
cc4ba6a9	561	{
21829e9b	562	int relation;
9850d1e8	563
21829e9b	564	set_float_exception_flags(0, &env->fp_status);
d6c424c5	565	relation = float64_compare(t0, t1, &env->fp_status);
21829e9b AJ	566	if (unlikely(relation == float_relation_unordered)) {
	567	update_fpscr(GETPC());
	568	} else if (relation == float_relation_greater) {
cc4ba6a9	569	set_t();
21829e9b	570	} else {
cc4ba6a9	571	clr_t();
21829e9b	572	}
cc4ba6a9 AJ	573	}
cc4ba6a9 AJ	574
d6c424c5	575	float64 helper_fcnvsd_FT_DT(float32 t0)
cc4ba6a9	576	{
d6c424c5	577	float64 ret;
21829e9b	578	set_float_exception_flags(0, &env->fp_status);
d6c424c5	579	ret = float32_to_float64(t0, &env->fp_status);
21829e9b	580	update_fpscr(GETPC());
d6c424c5	581	return ret;
cc4ba6a9 AJ	582	}
cc4ba6a9 AJ	583
d6c424c5	584	float32 helper_fcnvds_DT_FT(float64 t0)
cc4ba6a9	585	{
d6c424c5	586	float32 ret;
21829e9b	587	set_float_exception_flags(0, &env->fp_status);
d6c424c5	588	ret = float64_to_float32(t0, &env->fp_status);
21829e9b	589	update_fpscr(GETPC());
d6c424c5	590	return ret;
cc4ba6a9 AJ	591	}
cc4ba6a9 AJ	592
d6c424c5	593	float32 helper_fdiv_FT(float32 t0, float32 t1)
cc4ba6a9	594	{
21829e9b	595	set_float_exception_flags(0, &env->fp_status);
d6c424c5	596	t0 = float32_div(t0, t1, &env->fp_status);
21829e9b	597	update_fpscr(GETPC());
d6c424c5	598	return t0;
cc4ba6a9 AJ	599	}
cc4ba6a9 AJ	600
d6c424c5	601	float64 helper_fdiv_DT(float64 t0, float64 t1)
cc4ba6a9	602	{
21829e9b	603	set_float_exception_flags(0, &env->fp_status);
d6c424c5	604	t0 = float64_div(t0, t1, &env->fp_status);
21829e9b	605	update_fpscr(GETPC());
d6c424c5	606	return t0;
cc4ba6a9 AJ	607	}
cc4ba6a9 AJ	608
d6c424c5	609	float32 helper_float_FT(uint32_t t0)
cc4ba6a9	610	{
d6c424c5	611	float32 ret;
21829e9b	612	set_float_exception_flags(0, &env->fp_status);
d6c424c5	613	ret = int32_to_float32(t0, &env->fp_status);
21829e9b	614	update_fpscr(GETPC());
d6c424c5	615	return ret;
cc4ba6a9 AJ	616	}
cc4ba6a9 AJ	617
d6c424c5	618	float64 helper_float_DT(uint32_t t0)
cc4ba6a9	619	{
d6c424c5	620	float64 ret;
21829e9b	621	set_float_exception_flags(0, &env->fp_status);
d6c424c5	622	ret = int32_to_float64(t0, &env->fp_status);
21829e9b	623	update_fpscr(GETPC());
d6c424c5	624	return ret;
cc4ba6a9 AJ	625	}
cc4ba6a9 AJ	626
d6c424c5	627	float32 helper_fmac_FT(float32 t0, float32 t1, float32 t2)
5b7141a1	628	{
21829e9b	629	set_float_exception_flags(0, &env->fp_status);
d6c424c5 AJ	630	t0 = float32_mul(t0, t1, &env->fp_status);
d6c424c5 AJ	631	t0 = float32_add(t0, t2, &env->fp_status);
21829e9b	632	update_fpscr(GETPC());
d6c424c5	633	return t0;
5b7141a1 AJ	634	}
5b7141a1 AJ	635
d6c424c5	636	float32 helper_fmul_FT(float32 t0, float32 t1)
cc4ba6a9	637	{
21829e9b	638	set_float_exception_flags(0, &env->fp_status);
d6c424c5	639	t0 = float32_mul(t0, t1, &env->fp_status);
21829e9b	640	update_fpscr(GETPC());
d6c424c5	641	return t0;
cc4ba6a9 AJ	642	}
cc4ba6a9 AJ	643
d6c424c5	644	float64 helper_fmul_DT(float64 t0, float64 t1)
cc4ba6a9	645	{
21829e9b	646	set_float_exception_flags(0, &env->fp_status);
d6c424c5	647	t0 = float64_mul(t0, t1, &env->fp_status);
21829e9b	648	update_fpscr(GETPC());
d6c424c5	649	return t0;
cc4ba6a9 AJ	650	}
cc4ba6a9 AJ	651
d6c424c5	652	float32 helper_fneg_T(float32 t0)
7fdf924f	653	{
d6c424c5	654	return float32_chs(t0);
7fdf924f AJ	655	}
7fdf924f AJ	656
d6c424c5	657	float32 helper_fsqrt_FT(float32 t0)
cc4ba6a9	658	{
21829e9b	659	set_float_exception_flags(0, &env->fp_status);
d6c424c5	660	t0 = float32_sqrt(t0, &env->fp_status);
21829e9b	661	update_fpscr(GETPC());
d6c424c5	662	return t0;
cc4ba6a9 AJ	663	}
cc4ba6a9 AJ	664
d6c424c5	665	float64 helper_fsqrt_DT(float64 t0)
cc4ba6a9	666	{
21829e9b	667	set_float_exception_flags(0, &env->fp_status);
d6c424c5	668	t0 = float64_sqrt(t0, &env->fp_status);
21829e9b	669	update_fpscr(GETPC());
d6c424c5	670	return t0;
cc4ba6a9 AJ	671	}
cc4ba6a9 AJ	672
d6c424c5	673	float32 helper_fsub_FT(float32 t0, float32 t1)
cc4ba6a9	674	{
21829e9b	675	set_float_exception_flags(0, &env->fp_status);
d6c424c5	676	t0 = float32_sub(t0, t1, &env->fp_status);
21829e9b	677	update_fpscr(GETPC());
d6c424c5	678	return t0;
cc4ba6a9 AJ	679	}
cc4ba6a9 AJ	680
d6c424c5	681	float64 helper_fsub_DT(float64 t0, float64 t1)
cc4ba6a9	682	{
21829e9b	683	set_float_exception_flags(0, &env->fp_status);
d6c424c5	684	t0 = float64_sub(t0, t1, &env->fp_status);
21829e9b	685	update_fpscr(GETPC());
d6c424c5	686	return t0;
cc4ba6a9 AJ	687	}
cc4ba6a9 AJ	688
d6c424c5	689	uint32_t helper_ftrc_FT(float32 t0)
cc4ba6a9	690	{
21829e9b	691	uint32_t ret;
21829e9b	692	set_float_exception_flags(0, &env->fp_status);
d6c424c5	693	ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
21829e9b AJ	694	update_fpscr(GETPC());
21829e9b AJ	695	return ret;
cc4ba6a9 AJ	696	}
cc4ba6a9 AJ	697
d6c424c5	698	uint32_t helper_ftrc_DT(float64 t0)
cc4ba6a9	699	{
21829e9b	700	uint32_t ret;
21829e9b	701	set_float_exception_flags(0, &env->fp_status);
d6c424c5	702	ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
21829e9b AJ	703	update_fpscr(GETPC());
21829e9b AJ	704	return ret;
cc4ba6a9	705	}
af8c2bde AJ	706
	707	void helper_fipr(uint32_t m, uint32_t n)
	708	{
	709	int bank, i;
	710	float32 r, p;
	711
	712	bank = (env->sr & FPSCR_FR) ? 16 : 0;
	713	r = float32_zero;
	714	set_float_exception_flags(0, &env->fp_status);
	715
	716	for (i = 0 ; i < 4 ; i++) {
	717	p = float32_mul(env->fregs[bank + m + i],
	718	env->fregs[bank + n + i],
	719	&env->fp_status);
	720	r = float32_add(r, p, &env->fp_status);
	721	}
	722	update_fpscr(GETPC());
	723
	724	env->fregs[bank + n + 3] = r;
	725	}
17075f10 AJ	726
	727	void helper_ftrv(uint32_t n)
	728	{
	729	int bank_matrix, bank_vector;
	730	int i, j;
	731	float32 r[4];
	732	float32 p;
	733
	734	bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
	735	bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
	736	set_float_exception_flags(0, &env->fp_status);
	737	for (i = 0 ; i < 4 ; i++) {
	738	r[i] = float32_zero;
	739	for (j = 0 ; j < 4 ; j++) {
	740	p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
	741	env->fregs[bank_vector + j],
	742	&env->fp_status);
	743	r[i] = float32_add(r[i], p, &env->fp_status);
	744	}
	745	}
	746	update_fpscr(GETPC());
	747
	748	for (i = 0 ; i < 4 ; i++) {
	749	env->fregs[bank_vector + i] = r[i];
	750	}
	751	}