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Commit | Line | Data |
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fdf9b3e8 FB |
1 | /* |
2 | * SH4 translation | |
5fafdf24 | 3 | * |
fdf9b3e8 FB |
4 | * Copyright (c) 2005 Samuel Tardieu |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | #include <stdarg.h> | |
21 | #include <stdlib.h> | |
22 | #include <stdio.h> | |
23 | #include <string.h> | |
24 | #include <inttypes.h> | |
25 | #include <assert.h> | |
26 | ||
27 | #define DEBUG_DISAS | |
28 | #define SH4_DEBUG_DISAS | |
29 | //#define SH4_SINGLE_STEP | |
30 | ||
31 | #include "cpu.h" | |
32 | #include "exec-all.h" | |
33 | #include "disas.h" | |
988d7eaa | 34 | #include "helper.h" |
57fec1fe | 35 | #include "tcg-op.h" |
ca10f867 | 36 | #include "qemu-common.h" |
fdf9b3e8 FB |
37 | |
38 | typedef struct DisasContext { | |
39 | struct TranslationBlock *tb; | |
40 | target_ulong pc; | |
41 | uint32_t sr; | |
eda9b09b | 42 | uint32_t fpscr; |
fdf9b3e8 FB |
43 | uint16_t opcode; |
44 | uint32_t flags; | |
823029f9 | 45 | int bstate; |
fdf9b3e8 FB |
46 | int memidx; |
47 | uint32_t delayed_pc; | |
48 | int singlestep_enabled; | |
49 | } DisasContext; | |
50 | ||
fe25591e AJ |
51 | #if defined(CONFIG_USER_ONLY) |
52 | #define IS_USER(ctx) 1 | |
53 | #else | |
54 | #define IS_USER(ctx) (!(ctx->sr & SR_MD)) | |
55 | #endif | |
56 | ||
823029f9 TS |
57 | enum { |
58 | BS_NONE = 0, /* We go out of the TB without reaching a branch or an | |
59 | * exception condition | |
60 | */ | |
61 | BS_STOP = 1, /* We want to stop translation for any reason */ | |
62 | BS_BRANCH = 2, /* We reached a branch condition */ | |
63 | BS_EXCP = 3, /* We reached an exception condition */ | |
64 | }; | |
65 | ||
1e8864f7 AJ |
66 | /* global register indexes */ |
67 | static TCGv cpu_env; | |
68 | static TCGv cpu_gregs[24]; | |
3a8a44c4 AJ |
69 | static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr; |
70 | static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl; | |
1000822b AJ |
71 | static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_flags; |
72 | ||
73 | /* internal register indexes */ | |
74 | static TCGv cpu_flags, cpu_delayed_pc; | |
1e8864f7 | 75 | |
2e70f6ef PB |
76 | #include "gen-icount.h" |
77 | ||
a5f1b965 | 78 | static void sh4_translate_init(void) |
2e70f6ef | 79 | { |
1e8864f7 | 80 | int i; |
2e70f6ef | 81 | static int done_init = 0; |
559dd74d | 82 | static const char * const gregnames[24] = { |
1e8864f7 AJ |
83 | "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0", |
84 | "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0", | |
85 | "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", | |
86 | "R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1", | |
87 | "R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1" | |
88 | }; | |
89 | ||
2e70f6ef PB |
90 | if (done_init) |
91 | return; | |
1e8864f7 | 92 | |
2e70f6ef | 93 | cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env"); |
1e8864f7 AJ |
94 | |
95 | for (i = 0; i < 24; i++) | |
96 | cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, | |
97 | offsetof(CPUState, gregs[i]), | |
98 | gregnames[i]); | |
988d7eaa | 99 | |
3a8a44c4 AJ |
100 | cpu_pc = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
101 | offsetof(CPUState, pc), "PC"); | |
102 | cpu_sr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, | |
103 | offsetof(CPUState, sr), "SR"); | |
104 | cpu_ssr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, | |
105 | offsetof(CPUState, ssr), "SSR"); | |
106 | cpu_spc = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, | |
107 | offsetof(CPUState, spc), "SPC"); | |
108 | cpu_gbr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, | |
109 | offsetof(CPUState, gbr), "GBR"); | |
110 | cpu_vbr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, | |
111 | offsetof(CPUState, vbr), "VBR"); | |
112 | cpu_sgr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, | |
113 | offsetof(CPUState, sgr), "SGR"); | |
114 | cpu_dbr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, | |
115 | offsetof(CPUState, dbr), "DBR"); | |
116 | cpu_mach = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, | |
117 | offsetof(CPUState, mach), "MACH"); | |
118 | cpu_macl = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, | |
119 | offsetof(CPUState, macl), "MACL"); | |
120 | cpu_pr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, | |
121 | offsetof(CPUState, pr), "PR"); | |
122 | cpu_fpscr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, | |
123 | offsetof(CPUState, fpscr), "FPSCR"); | |
124 | cpu_fpul = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, | |
125 | offsetof(CPUState, fpul), "FPUL"); | |
126 | ||
1000822b AJ |
127 | cpu_flags = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
128 | offsetof(CPUState, flags), "_flags_"); | |
129 | cpu_delayed_pc = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, | |
130 | offsetof(CPUState, delayed_pc), | |
131 | "_delayed_pc_"); | |
132 | ||
988d7eaa AJ |
133 | /* register helpers */ |
134 | #undef DEF_HELPER | |
135 | #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); | |
136 | #include "helper.h" | |
137 | ||
2e70f6ef PB |
138 | done_init = 1; |
139 | } | |
140 | ||
fdf9b3e8 FB |
141 | void cpu_dump_state(CPUState * env, FILE * f, |
142 | int (*cpu_fprintf) (FILE * f, const char *fmt, ...), | |
143 | int flags) | |
144 | { | |
145 | int i; | |
eda9b09b FB |
146 | cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n", |
147 | env->pc, env->sr, env->pr, env->fpscr); | |
274a9e70 AJ |
148 | cpu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n", |
149 | env->spc, env->ssr, env->gbr, env->vbr); | |
150 | cpu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n", | |
151 | env->sgr, env->dbr, env->delayed_pc, env->fpul); | |
fdf9b3e8 FB |
152 | for (i = 0; i < 24; i += 4) { |
153 | cpu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n", | |
154 | i, env->gregs[i], i + 1, env->gregs[i + 1], | |
155 | i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]); | |
156 | } | |
157 | if (env->flags & DELAY_SLOT) { | |
158 | cpu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n", | |
159 | env->delayed_pc); | |
160 | } else if (env->flags & DELAY_SLOT_CONDITIONAL) { | |
161 | cpu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n", | |
162 | env->delayed_pc); | |
163 | } | |
164 | } | |
165 | ||
166 | void cpu_sh4_reset(CPUSH4State * env) | |
167 | { | |
9c2a9ea1 | 168 | #if defined(CONFIG_USER_ONLY) |
4c909d14 | 169 | env->sr = SR_FD; /* FD - kernel does lazy fpu context switch */ |
9c2a9ea1 | 170 | #else |
fdf9b3e8 | 171 | env->sr = 0x700000F0; /* MD, RB, BL, I3-I0 */ |
9c2a9ea1 | 172 | #endif |
fdf9b3e8 FB |
173 | env->vbr = 0; |
174 | env->pc = 0xA0000000; | |
ea6cf6be TS |
175 | #if defined(CONFIG_USER_ONLY) |
176 | env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ | |
b0b3de89 | 177 | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ |
ea6cf6be TS |
178 | #else |
179 | env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */ | |
b0b3de89 | 180 | set_float_rounding_mode(float_round_to_zero, &env->fp_status); |
ea6cf6be | 181 | #endif |
fdf9b3e8 FB |
182 | env->mmucr = 0; |
183 | } | |
184 | ||
0fd3ca30 | 185 | typedef struct { |
b55266b5 | 186 | const char *name; |
0fd3ca30 AJ |
187 | int id; |
188 | uint32_t pvr; | |
189 | uint32_t prr; | |
190 | uint32_t cvr; | |
191 | } sh4_def_t; | |
192 | ||
193 | static sh4_def_t sh4_defs[] = { | |
194 | { | |
195 | .name = "SH7750R", | |
196 | .id = SH_CPU_SH7750R, | |
197 | .pvr = 0x00050000, | |
198 | .prr = 0x00000100, | |
199 | .cvr = 0x00110000, | |
200 | }, { | |
201 | .name = "SH7751R", | |
202 | .id = SH_CPU_SH7751R, | |
203 | .pvr = 0x04050005, | |
204 | .prr = 0x00000113, | |
205 | .cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */ | |
206 | }, | |
207 | }; | |
208 | ||
b55266b5 | 209 | static const sh4_def_t *cpu_sh4_find_by_name(const char *name) |
0fd3ca30 AJ |
210 | { |
211 | int i; | |
212 | ||
213 | if (strcasecmp(name, "any") == 0) | |
214 | return &sh4_defs[0]; | |
215 | ||
216 | for (i = 0; i < sizeof(sh4_defs) / sizeof(*sh4_defs); i++) | |
217 | if (strcasecmp(name, sh4_defs[i].name) == 0) | |
218 | return &sh4_defs[i]; | |
219 | ||
220 | return NULL; | |
221 | } | |
222 | ||
223 | void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) | |
224 | { | |
225 | int i; | |
226 | ||
227 | for (i = 0; i < sizeof(sh4_defs) / sizeof(*sh4_defs); i++) | |
228 | (*cpu_fprintf)(f, "%s\n", sh4_defs[i].name); | |
229 | } | |
230 | ||
231 | static int cpu_sh4_register(CPUSH4State *env, const sh4_def_t *def) | |
232 | { | |
233 | env->pvr = def->pvr; | |
234 | env->prr = def->prr; | |
235 | env->cvr = def->cvr; | |
236 | env->id = def->id; | |
237 | } | |
238 | ||
aaed909a | 239 | CPUSH4State *cpu_sh4_init(const char *cpu_model) |
fdf9b3e8 FB |
240 | { |
241 | CPUSH4State *env; | |
0fd3ca30 | 242 | const sh4_def_t *def; |
fdf9b3e8 | 243 | |
0fd3ca30 AJ |
244 | def = cpu_sh4_find_by_name(cpu_model); |
245 | if (!def) | |
246 | return NULL; | |
fdf9b3e8 FB |
247 | env = qemu_mallocz(sizeof(CPUSH4State)); |
248 | if (!env) | |
249 | return NULL; | |
250 | cpu_exec_init(env); | |
2e70f6ef | 251 | sh4_translate_init(); |
7478757e | 252 | env->cpu_model_str = cpu_model; |
fdf9b3e8 | 253 | cpu_sh4_reset(env); |
0fd3ca30 | 254 | cpu_sh4_register(env, def); |
fdf9b3e8 FB |
255 | tlb_flush(env, 1); |
256 | return env; | |
257 | } | |
258 | ||
fdf9b3e8 FB |
259 | static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest) |
260 | { | |
261 | TranslationBlock *tb; | |
262 | tb = ctx->tb; | |
263 | ||
264 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && | |
265 | !ctx->singlestep_enabled) { | |
266 | /* Use a direct jump if in same page and singlestep not enabled */ | |
57fec1fe | 267 | tcg_gen_goto_tb(n); |
3a8a44c4 | 268 | tcg_gen_movi_i32(cpu_pc, dest); |
57fec1fe | 269 | tcg_gen_exit_tb((long) tb + n); |
fdf9b3e8 | 270 | } else { |
3a8a44c4 | 271 | tcg_gen_movi_i32(cpu_pc, dest); |
57fec1fe | 272 | if (ctx->singlestep_enabled) |
e6afc2f4 | 273 | tcg_gen_helper_0_0(helper_debug); |
57fec1fe | 274 | tcg_gen_exit_tb(0); |
fdf9b3e8 | 275 | } |
fdf9b3e8 FB |
276 | } |
277 | ||
fdf9b3e8 FB |
278 | static void gen_jump(DisasContext * ctx) |
279 | { | |
280 | if (ctx->delayed_pc == (uint32_t) - 1) { | |
281 | /* Target is not statically known, it comes necessarily from a | |
282 | delayed jump as immediate jump are conditinal jumps */ | |
1000822b | 283 | tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc); |
fdf9b3e8 | 284 | if (ctx->singlestep_enabled) |
e6afc2f4 | 285 | tcg_gen_helper_0_0(helper_debug); |
57fec1fe | 286 | tcg_gen_exit_tb(0); |
fdf9b3e8 FB |
287 | } else { |
288 | gen_goto_tb(ctx, 0, ctx->delayed_pc); | |
289 | } | |
290 | } | |
291 | ||
1000822b AJ |
292 | static inline void gen_branch_slot(uint32_t delayed_pc, int t) |
293 | { | |
c55497ec | 294 | TCGv sr; |
1000822b AJ |
295 | int label = gen_new_label(); |
296 | tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc); | |
c55497ec AJ |
297 | sr = tcg_temp_new(TCG_TYPE_I32); |
298 | tcg_gen_andi_i32(sr, cpu_sr, SR_T); | |
299 | tcg_gen_brcondi_i32(TCG_COND_NE, sr, t ? SR_T : 0, label); | |
1000822b AJ |
300 | tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE); |
301 | gen_set_label(label); | |
302 | } | |
303 | ||
fdf9b3e8 FB |
304 | /* Immediate conditional jump (bt or bf) */ |
305 | static void gen_conditional_jump(DisasContext * ctx, | |
306 | target_ulong ift, target_ulong ifnott) | |
307 | { | |
308 | int l1; | |
c55497ec | 309 | TCGv sr; |
fdf9b3e8 FB |
310 | |
311 | l1 = gen_new_label(); | |
c55497ec AJ |
312 | sr = tcg_temp_new(TCG_TYPE_I32); |
313 | tcg_gen_andi_i32(sr, cpu_sr, SR_T); | |
314 | tcg_gen_brcondi_i32(TCG_COND_EQ, sr, SR_T, l1); | |
fdf9b3e8 FB |
315 | gen_goto_tb(ctx, 0, ifnott); |
316 | gen_set_label(l1); | |
317 | gen_goto_tb(ctx, 1, ift); | |
318 | } | |
319 | ||
320 | /* Delayed conditional jump (bt or bf) */ | |
321 | static void gen_delayed_conditional_jump(DisasContext * ctx) | |
322 | { | |
323 | int l1; | |
c55497ec | 324 | TCGv ds; |
fdf9b3e8 FB |
325 | |
326 | l1 = gen_new_label(); | |
c55497ec AJ |
327 | ds = tcg_temp_new(TCG_TYPE_I32); |
328 | tcg_gen_andi_i32(ds, cpu_flags, DELAY_SLOT_TRUE); | |
329 | tcg_gen_brcondi_i32(TCG_COND_EQ, ds, DELAY_SLOT_TRUE, l1); | |
823029f9 | 330 | gen_goto_tb(ctx, 1, ctx->pc + 2); |
fdf9b3e8 | 331 | gen_set_label(l1); |
1000822b | 332 | tcg_gen_andi_i32(cpu_flags, cpu_flags, ~DELAY_SLOT_TRUE); |
9c2a9ea1 | 333 | gen_jump(ctx); |
fdf9b3e8 FB |
334 | } |
335 | ||
a4625612 AJ |
336 | static inline void gen_set_t(void) |
337 | { | |
338 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T); | |
339 | } | |
340 | ||
341 | static inline void gen_clr_t(void) | |
342 | { | |
343 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); | |
344 | } | |
345 | ||
346 | static inline void gen_cmp(int cond, TCGv t0, TCGv t1) | |
347 | { | |
348 | int label1 = gen_new_label(); | |
349 | int label2 = gen_new_label(); | |
350 | tcg_gen_brcond_i32(cond, t1, t0, label1); | |
351 | gen_clr_t(); | |
352 | tcg_gen_br(label2); | |
353 | gen_set_label(label1); | |
354 | gen_set_t(); | |
355 | gen_set_label(label2); | |
356 | } | |
357 | ||
358 | static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm) | |
359 | { | |
360 | int label1 = gen_new_label(); | |
361 | int label2 = gen_new_label(); | |
362 | tcg_gen_brcondi_i32(cond, t0, imm, label1); | |
363 | gen_clr_t(); | |
364 | tcg_gen_br(label2); | |
365 | gen_set_label(label1); | |
366 | gen_set_t(); | |
367 | gen_set_label(label2); | |
368 | } | |
369 | ||
1000822b AJ |
370 | static inline void gen_store_flags(uint32_t flags) |
371 | { | |
372 | tcg_gen_andi_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE); | |
373 | tcg_gen_ori_i32(cpu_flags, cpu_flags, flags); | |
374 | } | |
375 | ||
69d6275b AJ |
376 | static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1) |
377 | { | |
378 | TCGv tmp = tcg_temp_new(TCG_TYPE_I32); | |
379 | ||
380 | p0 &= 0x1f; | |
381 | p1 &= 0x1f; | |
382 | ||
383 | tcg_gen_andi_i32(tmp, t1, (1 << p1)); | |
384 | tcg_gen_andi_i32(t0, t0, ~(1 << p0)); | |
385 | if (p0 < p1) | |
386 | tcg_gen_shri_i32(tmp, tmp, p1 - p0); | |
387 | else if (p0 > p1) | |
388 | tcg_gen_shli_i32(tmp, tmp, p0 - p1); | |
389 | tcg_gen_or_i32(t0, t0, tmp); | |
390 | ||
391 | tcg_temp_free(tmp); | |
392 | } | |
393 | ||
cc4ba6a9 AJ |
394 | |
395 | static inline void gen_load_fpr32(TCGv t, int reg) | |
396 | { | |
397 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, fregs[reg])); | |
398 | } | |
399 | ||
400 | static inline void gen_load_fpr64(TCGv t, int reg) | |
401 | { | |
402 | TCGv tmp1 = tcg_temp_new(TCG_TYPE_I32); | |
403 | TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64); | |
404 | ||
405 | tcg_gen_ld_i32(tmp1, cpu_env, offsetof(CPUState, fregs[reg])); | |
406 | tcg_gen_extu_i32_i64(t, tmp1); | |
407 | tcg_gen_shli_i64(t, t, 32); | |
408 | tcg_gen_ld_i32(tmp1, cpu_env, offsetof(CPUState, fregs[reg + 1])); | |
409 | tcg_gen_extu_i32_i64(tmp2, tmp1); | |
410 | tcg_temp_free(tmp1); | |
411 | tcg_gen_or_i64(t, t, tmp2); | |
412 | tcg_temp_free(tmp2); | |
413 | } | |
414 | ||
415 | static inline void gen_store_fpr32(TCGv t, int reg) | |
416 | { | |
417 | tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, fregs[reg])); | |
418 | } | |
419 | ||
420 | static inline void gen_store_fpr64 (TCGv t, int reg) | |
421 | { | |
422 | TCGv tmp = tcg_temp_new(TCG_TYPE_I32); | |
423 | ||
424 | tcg_gen_trunc_i64_i32(tmp, t); | |
425 | tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, fregs[reg + 1])); | |
426 | tcg_gen_shri_i64(t, t, 32); | |
427 | tcg_gen_trunc_i64_i32(tmp, t); | |
428 | tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, fregs[reg])); | |
429 | tcg_temp_free(tmp); | |
430 | } | |
431 | ||
fdf9b3e8 FB |
432 | #define B3_0 (ctx->opcode & 0xf) |
433 | #define B6_4 ((ctx->opcode >> 4) & 0x7) | |
434 | #define B7_4 ((ctx->opcode >> 4) & 0xf) | |
435 | #define B7_0 (ctx->opcode & 0xff) | |
436 | #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff)) | |
437 | #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \ | |
438 | (ctx->opcode & 0xfff)) | |
439 | #define B11_8 ((ctx->opcode >> 8) & 0xf) | |
440 | #define B15_12 ((ctx->opcode >> 12) & 0xf) | |
441 | ||
442 | #define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \ | |
7efbe241 | 443 | (cpu_gregs[x + 16]) : (cpu_gregs[x])) |
fdf9b3e8 FB |
444 | |
445 | #define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \ | |
7efbe241 | 446 | ? (cpu_gregs[x + 16]) : (cpu_gregs[x])) |
fdf9b3e8 | 447 | |
eda9b09b | 448 | #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x)) |
f09111e0 | 449 | #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) |
eda9b09b | 450 | #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x)) |
ea6cf6be | 451 | #define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */ |
eda9b09b | 452 | |
fdf9b3e8 FB |
453 | #define CHECK_NOT_DELAY_SLOT \ |
454 | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \ | |
e6afc2f4 | 455 | {tcg_gen_helper_0_0(helper_raise_slot_illegal_instruction); ctx->bstate = BS_EXCP; \ |
fdf9b3e8 FB |
456 | return;} |
457 | ||
fe25591e AJ |
458 | #define CHECK_PRIVILEGED \ |
459 | if (IS_USER(ctx)) { \ | |
460 | tcg_gen_helper_0_0(helper_raise_illegal_instruction); \ | |
461 | ctx->bstate = BS_EXCP; \ | |
462 | return; \ | |
463 | } | |
464 | ||
823029f9 | 465 | void _decode_opc(DisasContext * ctx) |
fdf9b3e8 FB |
466 | { |
467 | #if 0 | |
468 | fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode); | |
469 | #endif | |
470 | switch (ctx->opcode) { | |
471 | case 0x0019: /* div0u */ | |
3a8a44c4 | 472 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T)); |
fdf9b3e8 FB |
473 | return; |
474 | case 0x000b: /* rts */ | |
1000822b AJ |
475 | CHECK_NOT_DELAY_SLOT |
476 | tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr); | |
fdf9b3e8 FB |
477 | ctx->flags |= DELAY_SLOT; |
478 | ctx->delayed_pc = (uint32_t) - 1; | |
479 | return; | |
480 | case 0x0028: /* clrmac */ | |
3a8a44c4 AJ |
481 | tcg_gen_movi_i32(cpu_mach, 0); |
482 | tcg_gen_movi_i32(cpu_macl, 0); | |
fdf9b3e8 FB |
483 | return; |
484 | case 0x0048: /* clrs */ | |
3a8a44c4 | 485 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S); |
fdf9b3e8 FB |
486 | return; |
487 | case 0x0008: /* clrt */ | |
a4625612 | 488 | gen_clr_t(); |
fdf9b3e8 FB |
489 | return; |
490 | case 0x0038: /* ldtlb */ | |
fe25591e | 491 | CHECK_PRIVILEGED |
e6afc2f4 | 492 | tcg_gen_helper_0_0(helper_ldtlb); |
fdf9b3e8 | 493 | return; |
c5e814b2 | 494 | case 0x002b: /* rte */ |
fe25591e | 495 | CHECK_PRIVILEGED |
1000822b AJ |
496 | CHECK_NOT_DELAY_SLOT |
497 | tcg_gen_mov_i32(cpu_sr, cpu_ssr); | |
498 | tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc); | |
fdf9b3e8 FB |
499 | ctx->flags |= DELAY_SLOT; |
500 | ctx->delayed_pc = (uint32_t) - 1; | |
501 | return; | |
502 | case 0x0058: /* sets */ | |
3a8a44c4 | 503 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S); |
fdf9b3e8 FB |
504 | return; |
505 | case 0x0018: /* sett */ | |
a4625612 | 506 | gen_set_t(); |
fdf9b3e8 | 507 | return; |
24988dc2 | 508 | case 0xfbfd: /* frchg */ |
6f06939b | 509 | tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR); |
823029f9 | 510 | ctx->bstate = BS_STOP; |
fdf9b3e8 | 511 | return; |
24988dc2 | 512 | case 0xf3fd: /* fschg */ |
6f06939b | 513 | tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ); |
823029f9 | 514 | ctx->bstate = BS_STOP; |
fdf9b3e8 FB |
515 | return; |
516 | case 0x0009: /* nop */ | |
517 | return; | |
518 | case 0x001b: /* sleep */ | |
fe25591e AJ |
519 | CHECK_PRIVILEGED |
520 | tcg_gen_helper_0_1(helper_sleep, tcg_const_i32(ctx->pc + 2)); | |
fdf9b3e8 FB |
521 | return; |
522 | } | |
523 | ||
524 | switch (ctx->opcode & 0xf000) { | |
525 | case 0x1000: /* mov.l Rm,@(disp,Rn) */ | |
c55497ec AJ |
526 | { |
527 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
528 | tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4); | |
529 | tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); | |
530 | tcg_temp_free(addr); | |
531 | } | |
fdf9b3e8 FB |
532 | return; |
533 | case 0x5000: /* mov.l @(disp,Rm),Rn */ | |
c55497ec AJ |
534 | { |
535 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
536 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4); | |
537 | tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); | |
538 | tcg_temp_free(addr); | |
539 | } | |
fdf9b3e8 | 540 | return; |
24988dc2 | 541 | case 0xe000: /* mov #imm,Rn */ |
7efbe241 | 542 | tcg_gen_movi_i32(REG(B11_8), B7_0s); |
fdf9b3e8 FB |
543 | return; |
544 | case 0x9000: /* mov.w @(disp,PC),Rn */ | |
c55497ec AJ |
545 | { |
546 | TCGv addr = tcg_const_i32(ctx->pc + 4 + B7_0 * 2); | |
547 | tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx); | |
548 | tcg_temp_free(addr); | |
549 | } | |
fdf9b3e8 FB |
550 | return; |
551 | case 0xd000: /* mov.l @(disp,PC),Rn */ | |
c55497ec AJ |
552 | { |
553 | TCGv addr = tcg_const_i32((ctx->pc + 4 + B7_0 * 4) & ~3); | |
554 | tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); | |
555 | tcg_temp_free(addr); | |
556 | } | |
fdf9b3e8 | 557 | return; |
24988dc2 | 558 | case 0x7000: /* add #imm,Rn */ |
7efbe241 | 559 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), B7_0s); |
fdf9b3e8 FB |
560 | return; |
561 | case 0xa000: /* bra disp */ | |
562 | CHECK_NOT_DELAY_SLOT | |
1000822b AJ |
563 | ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2; |
564 | tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc); | |
fdf9b3e8 FB |
565 | ctx->flags |= DELAY_SLOT; |
566 | return; | |
567 | case 0xb000: /* bsr disp */ | |
568 | CHECK_NOT_DELAY_SLOT | |
1000822b AJ |
569 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4); |
570 | ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2; | |
571 | tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc); | |
fdf9b3e8 FB |
572 | ctx->flags |= DELAY_SLOT; |
573 | return; | |
574 | } | |
575 | ||
576 | switch (ctx->opcode & 0xf00f) { | |
577 | case 0x6003: /* mov Rm,Rn */ | |
7efbe241 | 578 | tcg_gen_mov_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
579 | return; |
580 | case 0x2000: /* mov.b Rm,@Rn */ | |
7efbe241 | 581 | tcg_gen_qemu_st8(REG(B7_4), REG(B11_8), ctx->memidx); |
fdf9b3e8 FB |
582 | return; |
583 | case 0x2001: /* mov.w Rm,@Rn */ | |
7efbe241 | 584 | tcg_gen_qemu_st16(REG(B7_4), REG(B11_8), ctx->memidx); |
fdf9b3e8 FB |
585 | return; |
586 | case 0x2002: /* mov.l Rm,@Rn */ | |
7efbe241 | 587 | tcg_gen_qemu_st32(REG(B7_4), REG(B11_8), ctx->memidx); |
fdf9b3e8 FB |
588 | return; |
589 | case 0x6000: /* mov.b @Rm,Rn */ | |
7efbe241 | 590 | tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx); |
fdf9b3e8 FB |
591 | return; |
592 | case 0x6001: /* mov.w @Rm,Rn */ | |
7efbe241 | 593 | tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx); |
fdf9b3e8 FB |
594 | return; |
595 | case 0x6002: /* mov.l @Rm,Rn */ | |
7efbe241 | 596 | tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx); |
fdf9b3e8 FB |
597 | return; |
598 | case 0x2004: /* mov.b Rm,@-Rn */ | |
c55497ec AJ |
599 | { |
600 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
601 | tcg_gen_subi_i32(addr, REG(B11_8), 1); | |
602 | tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); /* might cause re-execution */ | |
603 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); /* modify register status */ | |
604 | tcg_temp_free(addr); | |
605 | } | |
fdf9b3e8 FB |
606 | return; |
607 | case 0x2005: /* mov.w Rm,@-Rn */ | |
c55497ec AJ |
608 | { |
609 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
610 | tcg_gen_subi_i32(addr, REG(B11_8), 2); | |
611 | tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx); | |
612 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 2); | |
613 | tcg_temp_free(addr); | |
614 | } | |
fdf9b3e8 FB |
615 | return; |
616 | case 0x2006: /* mov.l Rm,@-Rn */ | |
c55497ec AJ |
617 | { |
618 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
619 | tcg_gen_subi_i32(addr, REG(B11_8), 4); | |
620 | tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); | |
621 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); | |
622 | } | |
fdf9b3e8 | 623 | return; |
eda9b09b | 624 | case 0x6004: /* mov.b @Rm+,Rn */ |
7efbe241 | 625 | tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx); |
24988dc2 | 626 | if ( B11_8 != B7_4 ) |
7efbe241 | 627 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1); |
fdf9b3e8 FB |
628 | return; |
629 | case 0x6005: /* mov.w @Rm+,Rn */ | |
7efbe241 | 630 | tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx); |
24988dc2 | 631 | if ( B11_8 != B7_4 ) |
7efbe241 | 632 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); |
fdf9b3e8 FB |
633 | return; |
634 | case 0x6006: /* mov.l @Rm+,Rn */ | |
7efbe241 | 635 | tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx); |
24988dc2 | 636 | if ( B11_8 != B7_4 ) |
7efbe241 | 637 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); |
fdf9b3e8 FB |
638 | return; |
639 | case 0x0004: /* mov.b Rm,@(R0,Rn) */ | |
c55497ec AJ |
640 | { |
641 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
642 | tcg_gen_add_i32(addr, REG(B11_8), REG(0)); | |
643 | tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); | |
644 | tcg_temp_free(addr); | |
645 | } | |
fdf9b3e8 FB |
646 | return; |
647 | case 0x0005: /* mov.w Rm,@(R0,Rn) */ | |
c55497ec AJ |
648 | { |
649 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
650 | tcg_gen_add_i32(addr, REG(B11_8), REG(0)); | |
651 | tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx); | |
652 | tcg_temp_free(addr); | |
653 | } | |
fdf9b3e8 FB |
654 | return; |
655 | case 0x0006: /* mov.l Rm,@(R0,Rn) */ | |
c55497ec AJ |
656 | { |
657 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
658 | tcg_gen_add_i32(addr, REG(B11_8), REG(0)); | |
659 | tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); | |
660 | tcg_temp_free(addr); | |
661 | } | |
fdf9b3e8 FB |
662 | return; |
663 | case 0x000c: /* mov.b @(R0,Rm),Rn */ | |
c55497ec AJ |
664 | { |
665 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
666 | tcg_gen_add_i32(addr, REG(B7_4), REG(0)); | |
667 | tcg_gen_qemu_ld8s(REG(B11_8), addr, ctx->memidx); | |
668 | tcg_temp_free(addr); | |
669 | } | |
fdf9b3e8 FB |
670 | return; |
671 | case 0x000d: /* mov.w @(R0,Rm),Rn */ | |
c55497ec AJ |
672 | { |
673 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
674 | tcg_gen_add_i32(addr, REG(B7_4), REG(0)); | |
675 | tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx); | |
676 | tcg_temp_free(addr); | |
677 | } | |
fdf9b3e8 FB |
678 | return; |
679 | case 0x000e: /* mov.l @(R0,Rm),Rn */ | |
c55497ec AJ |
680 | { |
681 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
682 | tcg_gen_add_i32(addr, REG(B7_4), REG(0)); | |
683 | tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); | |
684 | tcg_temp_free(addr); | |
685 | } | |
fdf9b3e8 FB |
686 | return; |
687 | case 0x6008: /* swap.b Rm,Rn */ | |
c55497ec AJ |
688 | { |
689 | TCGv high, low; | |
690 | high = tcg_temp_new(TCG_TYPE_I32); | |
691 | tcg_gen_ext8u_i32(high, REG(B7_4)); | |
692 | tcg_gen_shli_i32(high, high, 8); | |
693 | low = tcg_temp_new(TCG_TYPE_I32); | |
694 | tcg_gen_shri_i32(low, REG(B7_4), 8); | |
695 | tcg_gen_ext8u_i32(low, low); | |
696 | tcg_gen_or_i32(REG(B11_8), high, low); | |
697 | tcg_temp_free(low); | |
698 | tcg_temp_free(high); | |
699 | } | |
fdf9b3e8 FB |
700 | return; |
701 | case 0x6009: /* swap.w Rm,Rn */ | |
c55497ec AJ |
702 | { |
703 | TCGv high, low; | |
704 | high = tcg_temp_new(TCG_TYPE_I32); | |
705 | tcg_gen_ext16u_i32(high, REG(B7_4)); | |
706 | tcg_gen_shli_i32(high, high, 16); | |
707 | low = tcg_temp_new(TCG_TYPE_I32); | |
708 | tcg_gen_shri_i32(low, REG(B7_4), 16); | |
709 | tcg_gen_ext16u_i32(low, low); | |
710 | tcg_gen_or_i32(REG(B11_8), high, low); | |
711 | tcg_temp_free(low); | |
712 | tcg_temp_free(high); | |
713 | } | |
fdf9b3e8 FB |
714 | return; |
715 | case 0x200d: /* xtrct Rm,Rn */ | |
c55497ec AJ |
716 | { |
717 | TCGv high, low; | |
718 | high = tcg_temp_new(TCG_TYPE_I32); | |
719 | tcg_gen_ext16u_i32(high, REG(B7_4)); | |
720 | tcg_gen_shli_i32(high, high, 16); | |
721 | low = tcg_temp_new(TCG_TYPE_I32); | |
722 | tcg_gen_shri_i32(low, REG(B11_8), 16); | |
723 | tcg_gen_ext16u_i32(low, low); | |
724 | tcg_gen_or_i32(REG(B11_8), high, low); | |
725 | tcg_temp_free(low); | |
726 | tcg_temp_free(high); | |
727 | } | |
fdf9b3e8 FB |
728 | return; |
729 | case 0x300c: /* add Rm,Rn */ | |
7efbe241 | 730 | tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
731 | return; |
732 | case 0x300e: /* addc Rm,Rn */ | |
7efbe241 | 733 | tcg_gen_helper_1_2(helper_addc, REG(B11_8), REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
734 | return; |
735 | case 0x300f: /* addv Rm,Rn */ | |
7efbe241 | 736 | tcg_gen_helper_1_2(helper_addv, REG(B11_8), REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
737 | return; |
738 | case 0x2009: /* and Rm,Rn */ | |
7efbe241 | 739 | tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
740 | return; |
741 | case 0x3000: /* cmp/eq Rm,Rn */ | |
7efbe241 | 742 | gen_cmp(TCG_COND_EQ, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
743 | return; |
744 | case 0x3003: /* cmp/ge Rm,Rn */ | |
7efbe241 | 745 | gen_cmp(TCG_COND_GE, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
746 | return; |
747 | case 0x3007: /* cmp/gt Rm,Rn */ | |
7efbe241 | 748 | gen_cmp(TCG_COND_GT, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
749 | return; |
750 | case 0x3006: /* cmp/hi Rm,Rn */ | |
7efbe241 | 751 | gen_cmp(TCG_COND_GTU, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
752 | return; |
753 | case 0x3002: /* cmp/hs Rm,Rn */ | |
7efbe241 | 754 | gen_cmp(TCG_COND_GEU, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
755 | return; |
756 | case 0x200c: /* cmp/str Rm,Rn */ | |
69d6275b AJ |
757 | { |
758 | int label1 = gen_new_label(); | |
759 | int label2 = gen_new_label(); | |
c55497ec AJ |
760 | TCGv cmp1 = tcg_temp_local_new(TCG_TYPE_I32); |
761 | TCGv cmp2 = tcg_temp_local_new(TCG_TYPE_I32); | |
762 | tcg_gen_xor_i32(cmp1, REG(B7_4), REG(B11_8)); | |
763 | tcg_gen_andi_i32(cmp2, cmp1, 0xff000000); | |
764 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1); | |
765 | tcg_gen_andi_i32(cmp2, cmp1, 0x00ff0000); | |
766 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1); | |
767 | tcg_gen_andi_i32(cmp2, cmp1, 0x0000ff00); | |
768 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1); | |
769 | tcg_gen_andi_i32(cmp2, cmp1, 0x000000ff); | |
770 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1); | |
69d6275b AJ |
771 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); |
772 | tcg_gen_br(label2); | |
773 | gen_set_label(label1); | |
774 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T); | |
775 | gen_set_label(label2); | |
c55497ec AJ |
776 | tcg_temp_free(cmp2); |
777 | tcg_temp_free(cmp1); | |
69d6275b | 778 | } |
fdf9b3e8 FB |
779 | return; |
780 | case 0x2007: /* div0s Rm,Rn */ | |
c55497ec AJ |
781 | { |
782 | gen_copy_bit_i32(cpu_sr, 8, REG(B11_8), 31); /* SR_Q */ | |
783 | gen_copy_bit_i32(cpu_sr, 9, REG(B7_4), 31); /* SR_M */ | |
784 | TCGv val = tcg_temp_new(TCG_TYPE_I32); | |
785 | tcg_gen_xor_i32(val, REG(B7_4), REG(B11_8)); | |
786 | gen_copy_bit_i32(cpu_sr, 0, val, 31); /* SR_T */ | |
787 | tcg_temp_free(val); | |
788 | } | |
fdf9b3e8 FB |
789 | return; |
790 | case 0x3004: /* div1 Rm,Rn */ | |
7efbe241 | 791 | tcg_gen_helper_1_2(helper_div1, REG(B11_8), REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
792 | return; |
793 | case 0x300d: /* dmuls.l Rm,Rn */ | |
6f06939b AJ |
794 | { |
795 | TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64); | |
796 | TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64); | |
797 | ||
7efbe241 AJ |
798 | tcg_gen_ext_i32_i64(tmp1, REG(B7_4)); |
799 | tcg_gen_ext_i32_i64(tmp2, REG(B11_8)); | |
6f06939b AJ |
800 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
801 | tcg_gen_trunc_i64_i32(cpu_macl, tmp1); | |
802 | tcg_gen_shri_i64(tmp1, tmp1, 32); | |
803 | tcg_gen_trunc_i64_i32(cpu_mach, tmp1); | |
804 | ||
6f06939b | 805 | tcg_temp_free(tmp2); |
c55497ec | 806 | tcg_temp_free(tmp1); |
6f06939b | 807 | } |
fdf9b3e8 FB |
808 | return; |
809 | case 0x3005: /* dmulu.l Rm,Rn */ | |
6f06939b AJ |
810 | { |
811 | TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64); | |
812 | TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64); | |
813 | ||
7efbe241 AJ |
814 | tcg_gen_extu_i32_i64(tmp1, REG(B7_4)); |
815 | tcg_gen_extu_i32_i64(tmp2, REG(B11_8)); | |
6f06939b AJ |
816 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
817 | tcg_gen_trunc_i64_i32(cpu_macl, tmp1); | |
818 | tcg_gen_shri_i64(tmp1, tmp1, 32); | |
819 | tcg_gen_trunc_i64_i32(cpu_mach, tmp1); | |
820 | ||
6f06939b | 821 | tcg_temp_free(tmp2); |
c55497ec | 822 | tcg_temp_free(tmp1); |
6f06939b | 823 | } |
fdf9b3e8 FB |
824 | return; |
825 | case 0x600e: /* exts.b Rm,Rn */ | |
7efbe241 | 826 | tcg_gen_ext8s_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
827 | return; |
828 | case 0x600f: /* exts.w Rm,Rn */ | |
7efbe241 | 829 | tcg_gen_ext16s_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
830 | return; |
831 | case 0x600c: /* extu.b Rm,Rn */ | |
7efbe241 | 832 | tcg_gen_ext8u_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
833 | return; |
834 | case 0x600d: /* extu.w Rm,Rn */ | |
7efbe241 | 835 | tcg_gen_ext16u_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 | 836 | return; |
24988dc2 | 837 | case 0x000f: /* mac.l @Rm+,@Rn+ */ |
c55497ec AJ |
838 | { |
839 | TCGv arg0, arg1; | |
840 | arg0 = tcg_temp_new(TCG_TYPE_I32); | |
841 | tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx); | |
842 | arg1 = tcg_temp_new(TCG_TYPE_I32); | |
843 | tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx); | |
844 | tcg_gen_helper_0_2(helper_macl, arg0, arg1); | |
845 | tcg_temp_free(arg1); | |
846 | tcg_temp_free(arg0); | |
847 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); | |
848 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); | |
849 | } | |
fdf9b3e8 FB |
850 | return; |
851 | case 0x400f: /* mac.w @Rm+,@Rn+ */ | |
c55497ec AJ |
852 | { |
853 | TCGv arg0, arg1; | |
854 | arg0 = tcg_temp_new(TCG_TYPE_I32); | |
855 | tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx); | |
856 | arg1 = tcg_temp_new(TCG_TYPE_I32); | |
857 | tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx); | |
858 | tcg_gen_helper_0_2(helper_macw, arg0, arg1); | |
859 | tcg_temp_free(arg1); | |
860 | tcg_temp_free(arg0); | |
861 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2); | |
862 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); | |
863 | } | |
fdf9b3e8 FB |
864 | return; |
865 | case 0x0007: /* mul.l Rm,Rn */ | |
7efbe241 | 866 | tcg_gen_mul_i32(cpu_macl, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
867 | return; |
868 | case 0x200f: /* muls.w Rm,Rn */ | |
c55497ec AJ |
869 | { |
870 | TCGv arg0, arg1; | |
871 | arg0 = tcg_temp_new(TCG_TYPE_I32); | |
872 | tcg_gen_ext16s_i32(arg0, REG(B7_4)); | |
873 | arg1 = tcg_temp_new(TCG_TYPE_I32); | |
874 | tcg_gen_ext16s_i32(arg1, REG(B11_8)); | |
875 | tcg_gen_mul_i32(cpu_macl, arg0, arg1); | |
876 | tcg_temp_free(arg1); | |
877 | tcg_temp_free(arg0); | |
878 | } | |
fdf9b3e8 FB |
879 | return; |
880 | case 0x200e: /* mulu.w Rm,Rn */ | |
c55497ec AJ |
881 | { |
882 | TCGv arg0, arg1; | |
883 | arg0 = tcg_temp_new(TCG_TYPE_I32); | |
884 | tcg_gen_ext16u_i32(arg0, REG(B7_4)); | |
885 | arg1 = tcg_temp_new(TCG_TYPE_I32); | |
886 | tcg_gen_ext16u_i32(arg1, REG(B11_8)); | |
887 | tcg_gen_mul_i32(cpu_macl, arg0, arg1); | |
888 | tcg_temp_free(arg1); | |
889 | tcg_temp_free(arg0); | |
890 | } | |
fdf9b3e8 FB |
891 | return; |
892 | case 0x600b: /* neg Rm,Rn */ | |
7efbe241 | 893 | tcg_gen_neg_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
894 | return; |
895 | case 0x600a: /* negc Rm,Rn */ | |
7efbe241 | 896 | tcg_gen_helper_1_1(helper_negc, REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
897 | return; |
898 | case 0x6007: /* not Rm,Rn */ | |
7efbe241 | 899 | tcg_gen_not_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
900 | return; |
901 | case 0x200b: /* or Rm,Rn */ | |
7efbe241 | 902 | tcg_gen_or_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
903 | return; |
904 | case 0x400c: /* shad Rm,Rn */ | |
69d6275b AJ |
905 | { |
906 | int label1 = gen_new_label(); | |
907 | int label2 = gen_new_label(); | |
908 | int label3 = gen_new_label(); | |
909 | int label4 = gen_new_label(); | |
c55497ec | 910 | TCGv shift = tcg_temp_local_new(TCG_TYPE_I32); |
7efbe241 | 911 | tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1); |
69d6275b | 912 | /* Rm positive, shift to the left */ |
c55497ec AJ |
913 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); |
914 | tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift); | |
69d6275b AJ |
915 | tcg_gen_br(label4); |
916 | /* Rm negative, shift to the right */ | |
917 | gen_set_label(label1); | |
c55497ec AJ |
918 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); |
919 | tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2); | |
920 | tcg_gen_not_i32(shift, REG(B7_4)); | |
921 | tcg_gen_andi_i32(shift, shift, 0x1f); | |
922 | tcg_gen_addi_i32(shift, shift, 1); | |
923 | tcg_gen_sar_i32(REG(B11_8), REG(B11_8), shift); | |
69d6275b AJ |
924 | tcg_gen_br(label4); |
925 | /* Rm = -32 */ | |
926 | gen_set_label(label2); | |
7efbe241 AJ |
927 | tcg_gen_brcondi_i32(TCG_COND_LT, REG(B11_8), 0, label3); |
928 | tcg_gen_movi_i32(REG(B11_8), 0); | |
69d6275b AJ |
929 | tcg_gen_br(label4); |
930 | gen_set_label(label3); | |
7efbe241 | 931 | tcg_gen_movi_i32(REG(B11_8), 0xffffffff); |
69d6275b | 932 | gen_set_label(label4); |
c55497ec | 933 | tcg_temp_free(shift); |
69d6275b | 934 | } |
fdf9b3e8 FB |
935 | return; |
936 | case 0x400d: /* shld Rm,Rn */ | |
69d6275b AJ |
937 | { |
938 | int label1 = gen_new_label(); | |
939 | int label2 = gen_new_label(); | |
940 | int label3 = gen_new_label(); | |
c55497ec | 941 | TCGv shift = tcg_temp_local_new(TCG_TYPE_I32); |
7efbe241 | 942 | tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1); |
69d6275b | 943 | /* Rm positive, shift to the left */ |
c55497ec AJ |
944 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); |
945 | tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift); | |
69d6275b AJ |
946 | tcg_gen_br(label3); |
947 | /* Rm negative, shift to the right */ | |
948 | gen_set_label(label1); | |
c55497ec AJ |
949 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); |
950 | tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2); | |
951 | tcg_gen_not_i32(shift, REG(B7_4)); | |
952 | tcg_gen_andi_i32(shift, shift, 0x1f); | |
953 | tcg_gen_addi_i32(shift, shift, 1); | |
954 | tcg_gen_shr_i32(REG(B11_8), REG(B11_8), shift); | |
69d6275b AJ |
955 | tcg_gen_br(label3); |
956 | /* Rm = -32 */ | |
957 | gen_set_label(label2); | |
7efbe241 | 958 | tcg_gen_movi_i32(REG(B11_8), 0); |
69d6275b | 959 | gen_set_label(label3); |
c55497ec | 960 | tcg_temp_free(shift); |
69d6275b | 961 | } |
fdf9b3e8 FB |
962 | return; |
963 | case 0x3008: /* sub Rm,Rn */ | |
7efbe241 | 964 | tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
965 | return; |
966 | case 0x300a: /* subc Rm,Rn */ | |
7efbe241 | 967 | tcg_gen_helper_1_2(helper_subc, REG(B11_8), REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
968 | return; |
969 | case 0x300b: /* subv Rm,Rn */ | |
7efbe241 | 970 | tcg_gen_helper_1_2(helper_subv, REG(B11_8), REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
971 | return; |
972 | case 0x2008: /* tst Rm,Rn */ | |
c55497ec AJ |
973 | { |
974 | TCGv val = tcg_temp_new(TCG_TYPE_I32); | |
975 | tcg_gen_and_i32(val, REG(B7_4), REG(B11_8)); | |
976 | gen_cmp_imm(TCG_COND_EQ, val, 0); | |
977 | tcg_temp_free(val); | |
978 | } | |
fdf9b3e8 FB |
979 | return; |
980 | case 0x200a: /* xor Rm,Rn */ | |
7efbe241 | 981 | tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
fdf9b3e8 | 982 | return; |
e67888a7 | 983 | case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */ |
022a22c7 | 984 | if (ctx->fpscr & FPSCR_SZ) { |
cc4ba6a9 AJ |
985 | TCGv fp = tcg_temp_new(TCG_TYPE_I64); |
986 | gen_load_fpr64(fp, XREG(B7_4)); | |
987 | gen_store_fpr64(fp, XREG(B11_8)); | |
988 | tcg_temp_free(fp); | |
eda9b09b | 989 | } else { |
cc4ba6a9 AJ |
990 | TCGv fp = tcg_temp_new(TCG_TYPE_I32); |
991 | gen_load_fpr32(fp, FREG(B7_4)); | |
992 | gen_store_fpr32(fp, FREG(B11_8)); | |
993 | tcg_temp_free(fp); | |
eda9b09b FB |
994 | } |
995 | return; | |
e67888a7 | 996 | case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ |
022a22c7 | 997 | if (ctx->fpscr & FPSCR_SZ) { |
cc4ba6a9 AJ |
998 | TCGv fp = tcg_temp_new(TCG_TYPE_I64); |
999 | gen_load_fpr64(fp, XREG(B7_4)); | |
1000 | tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx); | |
1001 | tcg_temp_free(fp); | |
eda9b09b | 1002 | } else { |
cc4ba6a9 AJ |
1003 | TCGv fp = tcg_temp_new(TCG_TYPE_I32); |
1004 | gen_load_fpr32(fp, FREG(B7_4)); | |
1005 | tcg_gen_qemu_st32(fp, REG(B11_8), ctx->memidx); | |
1006 | tcg_temp_free(fp); | |
eda9b09b FB |
1007 | } |
1008 | return; | |
e67888a7 | 1009 | case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ |
022a22c7 | 1010 | if (ctx->fpscr & FPSCR_SZ) { |
cc4ba6a9 AJ |
1011 | TCGv fp = tcg_temp_new(TCG_TYPE_I64); |
1012 | tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx); | |
1013 | gen_store_fpr64(fp, XREG(B11_8)); | |
1014 | tcg_temp_free(fp); | |
eda9b09b | 1015 | } else { |
cc4ba6a9 AJ |
1016 | TCGv fp = tcg_temp_new(TCG_TYPE_I32); |
1017 | tcg_gen_qemu_ld32u(fp, REG(B7_4), ctx->memidx); | |
1018 | gen_store_fpr32(fp, FREG(B11_8)); | |
1019 | tcg_temp_free(fp); | |
eda9b09b FB |
1020 | } |
1021 | return; | |
e67888a7 | 1022 | case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ |
022a22c7 | 1023 | if (ctx->fpscr & FPSCR_SZ) { |
cc4ba6a9 AJ |
1024 | TCGv fp = tcg_temp_new(TCG_TYPE_I64); |
1025 | tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx); | |
1026 | gen_store_fpr64(fp, XREG(B11_8)); | |
1027 | tcg_temp_free(fp); | |
1028 | tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8); | |
eda9b09b | 1029 | } else { |
cc4ba6a9 AJ |
1030 | TCGv fp = tcg_temp_new(TCG_TYPE_I32); |
1031 | tcg_gen_qemu_ld32u(fp, REG(B7_4), ctx->memidx); | |
1032 | gen_store_fpr32(fp, FREG(B11_8)); | |
1033 | tcg_temp_free(fp); | |
1034 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); | |
eda9b09b FB |
1035 | } |
1036 | return; | |
e67888a7 | 1037 | case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ |
022a22c7 | 1038 | if (ctx->fpscr & FPSCR_SZ) { |
cc4ba6a9 AJ |
1039 | TCGv addr, fp; |
1040 | addr = tcg_temp_new(TCG_TYPE_I32); | |
1041 | tcg_gen_subi_i32(addr, REG(B11_8), 8); | |
1042 | fp = tcg_temp_new(TCG_TYPE_I64); | |
1043 | gen_load_fpr64(fp, XREG(B7_4)); | |
1044 | tcg_gen_qemu_st64(fp, addr, ctx->memidx); | |
1045 | tcg_temp_free(fp); | |
1046 | tcg_temp_free(addr); | |
7efbe241 | 1047 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8); |
eda9b09b | 1048 | } else { |
cc4ba6a9 AJ |
1049 | TCGv addr, fp; |
1050 | addr = tcg_temp_new(TCG_TYPE_I32); | |
1051 | tcg_gen_subi_i32(addr, REG(B11_8), 4); | |
1052 | fp = tcg_temp_new(TCG_TYPE_I32); | |
1053 | gen_load_fpr32(fp, FREG(B7_4)); | |
1054 | tcg_gen_qemu_st32(fp, addr, ctx->memidx); | |
1055 | tcg_temp_free(fp); | |
1056 | tcg_temp_free(addr); | |
7efbe241 | 1057 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); |
eda9b09b FB |
1058 | } |
1059 | return; | |
e67888a7 | 1060 | case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ |
cc4ba6a9 AJ |
1061 | { |
1062 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
1063 | tcg_gen_add_i32(addr, REG(B7_4), REG(0)); | |
1064 | if (ctx->fpscr & FPSCR_SZ) { | |
1065 | TCGv fp = tcg_temp_new(TCG_TYPE_I64); | |
1066 | tcg_gen_qemu_ld64(fp, addr, ctx->memidx); | |
1067 | gen_store_fpr64(fp, XREG(B11_8)); | |
1068 | tcg_temp_free(fp); | |
1069 | } else { | |
1070 | TCGv fp = tcg_temp_new(TCG_TYPE_I32); | |
1071 | tcg_gen_qemu_ld32u(fp, addr, ctx->memidx); | |
1072 | gen_store_fpr32(fp, FREG(B11_8)); | |
1073 | tcg_temp_free(fp); | |
1074 | } | |
1075 | tcg_temp_free(addr); | |
eda9b09b FB |
1076 | } |
1077 | return; | |
e67888a7 | 1078 | case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */ |
cc4ba6a9 AJ |
1079 | { |
1080 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
1081 | tcg_gen_add_i32(addr, REG(B11_8), REG(0)); | |
1082 | if (ctx->fpscr & FPSCR_SZ) { | |
1083 | TCGv fp = tcg_temp_new(TCG_TYPE_I64); | |
1084 | gen_load_fpr64(fp, XREG(B7_4)); | |
1085 | tcg_gen_qemu_st64(fp, addr, ctx->memidx); | |
1086 | tcg_temp_free(fp); | |
1087 | } else { | |
1088 | TCGv fp = tcg_temp_new(TCG_TYPE_I32); | |
1089 | gen_load_fpr32(fp, FREG(B7_4)); | |
1090 | tcg_gen_qemu_st32(fp, addr, ctx->memidx); | |
1091 | tcg_temp_free(fp); | |
1092 | } | |
1093 | tcg_temp_free(addr); | |
eda9b09b FB |
1094 | } |
1095 | return; | |
e67888a7 TS |
1096 | case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
1097 | case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ | |
1098 | case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ | |
1099 | case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ | |
1100 | case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ | |
1101 | case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ | |
cc4ba6a9 AJ |
1102 | { |
1103 | TCGv fp0, fp1; | |
1104 | ||
1105 | if (ctx->fpscr & FPSCR_PR) { | |
1106 | if (ctx->opcode & 0x0110) | |
1107 | break; /* illegal instruction */ | |
1108 | fp0 = tcg_temp_new(TCG_TYPE_I64); | |
1109 | fp1 = tcg_temp_new(TCG_TYPE_I64); | |
1110 | gen_load_fpr64(fp0, DREG(B11_8)); | |
1111 | gen_load_fpr64(fp1, DREG(B7_4)); | |
1112 | } | |
1113 | else { | |
1114 | fp0 = tcg_temp_new(TCG_TYPE_I32); | |
1115 | fp1 = tcg_temp_new(TCG_TYPE_I32); | |
1116 | gen_load_fpr32(fp0, FREG(B11_8)); | |
1117 | gen_load_fpr32(fp1, FREG(B7_4)); | |
1118 | } | |
1119 | ||
1120 | switch (ctx->opcode & 0xf00f) { | |
1121 | case 0xf000: /* fadd Rm,Rn */ | |
1122 | if (ctx->fpscr & FPSCR_PR) | |
1123 | tcg_gen_helper_1_2(helper_fadd_DT, fp0, fp0, fp1); | |
1124 | else | |
1125 | tcg_gen_helper_1_2(helper_fadd_FT, fp0, fp0, fp1); | |
1126 | break; | |
1127 | case 0xf001: /* fsub Rm,Rn */ | |
1128 | if (ctx->fpscr & FPSCR_PR) | |
1129 | tcg_gen_helper_1_2(helper_fsub_DT, fp0, fp0, fp1); | |
1130 | else | |
1131 | tcg_gen_helper_1_2(helper_fsub_FT, fp0, fp0, fp1); | |
1132 | break; | |
1133 | case 0xf002: /* fmul Rm,Rn */ | |
1134 | if (ctx->fpscr & FPSCR_PR) | |
1135 | tcg_gen_helper_1_2(helper_fmul_DT, fp0, fp0, fp1); | |
1136 | else | |
1137 | tcg_gen_helper_1_2(helper_fmul_FT, fp0, fp0, fp1); | |
1138 | break; | |
1139 | case 0xf003: /* fdiv Rm,Rn */ | |
1140 | if (ctx->fpscr & FPSCR_PR) | |
1141 | tcg_gen_helper_1_2(helper_fdiv_DT, fp0, fp0, fp1); | |
1142 | else | |
1143 | tcg_gen_helper_1_2(helper_fdiv_FT, fp0, fp0, fp1); | |
1144 | break; | |
1145 | case 0xf004: /* fcmp/eq Rm,Rn */ | |
1146 | if (ctx->fpscr & FPSCR_PR) | |
1147 | tcg_gen_helper_0_2(helper_fcmp_eq_DT, fp0, fp1); | |
1148 | else | |
1149 | tcg_gen_helper_0_2(helper_fcmp_eq_FT, fp0, fp1); | |
1150 | return; | |
1151 | case 0xf005: /* fcmp/gt Rm,Rn */ | |
1152 | if (ctx->fpscr & FPSCR_PR) | |
1153 | tcg_gen_helper_0_2(helper_fcmp_gt_DT, fp0, fp1); | |
1154 | else | |
1155 | tcg_gen_helper_0_2(helper_fcmp_gt_FT, fp0, fp1); | |
1156 | return; | |
1157 | } | |
1158 | ||
1159 | if (ctx->fpscr & FPSCR_PR) { | |
1160 | gen_store_fpr64(fp0, DREG(B11_8)); | |
1161 | } | |
1162 | else { | |
1163 | gen_store_fpr32(fp0, FREG(B11_8)); | |
1164 | } | |
1165 | tcg_temp_free(fp1); | |
1166 | tcg_temp_free(fp0); | |
ea6cf6be TS |
1167 | } |
1168 | return; | |
fdf9b3e8 FB |
1169 | } |
1170 | ||
1171 | switch (ctx->opcode & 0xff00) { | |
1172 | case 0xc900: /* and #imm,R0 */ | |
7efbe241 | 1173 | tcg_gen_andi_i32(REG(0), REG(0), B7_0); |
fdf9b3e8 | 1174 | return; |
24988dc2 | 1175 | case 0xcd00: /* and.b #imm,@(R0,GBR) */ |
c55497ec AJ |
1176 | { |
1177 | TCGv addr, val; | |
1178 | addr = tcg_temp_new(TCG_TYPE_I32); | |
1179 | tcg_gen_add_i32(addr, REG(0), cpu_gbr); | |
1180 | val = tcg_temp_new(TCG_TYPE_I32); | |
1181 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); | |
1182 | tcg_gen_andi_i32(val, val, B7_0); | |
1183 | tcg_gen_qemu_st8(val, addr, ctx->memidx); | |
1184 | tcg_temp_free(val); | |
1185 | tcg_temp_free(addr); | |
1186 | } | |
fdf9b3e8 FB |
1187 | return; |
1188 | case 0x8b00: /* bf label */ | |
1189 | CHECK_NOT_DELAY_SLOT | |
1190 | gen_conditional_jump(ctx, ctx->pc + 2, | |
1191 | ctx->pc + 4 + B7_0s * 2); | |
823029f9 | 1192 | ctx->bstate = BS_BRANCH; |
fdf9b3e8 FB |
1193 | return; |
1194 | case 0x8f00: /* bf/s label */ | |
1195 | CHECK_NOT_DELAY_SLOT | |
1000822b | 1196 | gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 0); |
fdf9b3e8 FB |
1197 | ctx->flags |= DELAY_SLOT_CONDITIONAL; |
1198 | return; | |
1199 | case 0x8900: /* bt label */ | |
1200 | CHECK_NOT_DELAY_SLOT | |
1201 | gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2, | |
1202 | ctx->pc + 2); | |
823029f9 | 1203 | ctx->bstate = BS_BRANCH; |
fdf9b3e8 FB |
1204 | return; |
1205 | case 0x8d00: /* bt/s label */ | |
1206 | CHECK_NOT_DELAY_SLOT | |
1000822b | 1207 | gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 1); |
fdf9b3e8 FB |
1208 | ctx->flags |= DELAY_SLOT_CONDITIONAL; |
1209 | return; | |
1210 | case 0x8800: /* cmp/eq #imm,R0 */ | |
7efbe241 | 1211 | gen_cmp_imm(TCG_COND_EQ, REG(0), B7_0s); |
fdf9b3e8 FB |
1212 | return; |
1213 | case 0xc400: /* mov.b @(disp,GBR),R0 */ | |
c55497ec AJ |
1214 | { |
1215 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
1216 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0); | |
1217 | tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx); | |
1218 | tcg_temp_free(addr); | |
1219 | } | |
fdf9b3e8 FB |
1220 | return; |
1221 | case 0xc500: /* mov.w @(disp,GBR),R0 */ | |
c55497ec AJ |
1222 | { |
1223 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
1224 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2); | |
1225 | tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx); | |
1226 | tcg_temp_free(addr); | |
1227 | } | |
fdf9b3e8 FB |
1228 | return; |
1229 | case 0xc600: /* mov.l @(disp,GBR),R0 */ | |
c55497ec AJ |
1230 | { |
1231 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
1232 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4); | |
1233 | tcg_gen_qemu_ld32s(REG(0), addr, ctx->memidx); | |
1234 | tcg_temp_free(addr); | |
1235 | } | |
fdf9b3e8 FB |
1236 | return; |
1237 | case 0xc000: /* mov.b R0,@(disp,GBR) */ | |
c55497ec AJ |
1238 | { |
1239 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
1240 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0); | |
1241 | tcg_gen_qemu_st8(REG(0), addr, ctx->memidx); | |
1242 | tcg_temp_free(addr); | |
1243 | } | |
fdf9b3e8 FB |
1244 | return; |
1245 | case 0xc100: /* mov.w R0,@(disp,GBR) */ | |
c55497ec AJ |
1246 | { |
1247 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
1248 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2); | |
1249 | tcg_gen_qemu_st16(REG(0), addr, ctx->memidx); | |
1250 | tcg_temp_free(addr); | |
1251 | } | |
fdf9b3e8 FB |
1252 | return; |
1253 | case 0xc200: /* mov.l R0,@(disp,GBR) */ | |
c55497ec AJ |
1254 | { |
1255 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
1256 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4); | |
1257 | tcg_gen_qemu_st32(REG(0), addr, ctx->memidx); | |
1258 | tcg_temp_free(addr); | |
1259 | } | |
fdf9b3e8 FB |
1260 | return; |
1261 | case 0x8000: /* mov.b R0,@(disp,Rn) */ | |
c55497ec AJ |
1262 | { |
1263 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
1264 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0); | |
1265 | tcg_gen_qemu_st8(REG(0), addr, ctx->memidx); | |
1266 | tcg_temp_free(addr); | |
1267 | } | |
fdf9b3e8 FB |
1268 | return; |
1269 | case 0x8100: /* mov.w R0,@(disp,Rn) */ | |
c55497ec AJ |
1270 | { |
1271 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
1272 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); | |
1273 | tcg_gen_qemu_st16(REG(0), addr, ctx->memidx); | |
1274 | tcg_temp_free(addr); | |
1275 | } | |
fdf9b3e8 FB |
1276 | return; |
1277 | case 0x8400: /* mov.b @(disp,Rn),R0 */ | |
c55497ec AJ |
1278 | { |
1279 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
1280 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0); | |
1281 | tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx); | |
1282 | tcg_temp_free(addr); | |
1283 | } | |
fdf9b3e8 FB |
1284 | return; |
1285 | case 0x8500: /* mov.w @(disp,Rn),R0 */ | |
c55497ec AJ |
1286 | { |
1287 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
1288 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); | |
1289 | tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx); | |
1290 | tcg_temp_free(addr); | |
1291 | } | |
fdf9b3e8 FB |
1292 | return; |
1293 | case 0xc700: /* mova @(disp,PC),R0 */ | |
7efbe241 | 1294 | tcg_gen_movi_i32(REG(0), ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3); |
fdf9b3e8 FB |
1295 | return; |
1296 | case 0xcb00: /* or #imm,R0 */ | |
7efbe241 | 1297 | tcg_gen_ori_i32(REG(0), REG(0), B7_0); |
fdf9b3e8 | 1298 | return; |
24988dc2 | 1299 | case 0xcf00: /* or.b #imm,@(R0,GBR) */ |
c55497ec AJ |
1300 | { |
1301 | TCGv addr, val; | |
1302 | addr = tcg_temp_new(TCG_TYPE_I32); | |
1303 | tcg_gen_add_i32(addr, REG(0), cpu_gbr); | |
1304 | val = tcg_temp_new(TCG_TYPE_I32); | |
1305 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); | |
1306 | tcg_gen_ori_i32(val, val, B7_0); | |
1307 | tcg_gen_qemu_st8(val, addr, ctx->memidx); | |
1308 | tcg_temp_free(val); | |
1309 | tcg_temp_free(addr); | |
1310 | } | |
fdf9b3e8 FB |
1311 | return; |
1312 | case 0xc300: /* trapa #imm */ | |
c55497ec AJ |
1313 | { |
1314 | TCGv imm; | |
1315 | CHECK_NOT_DELAY_SLOT | |
1316 | tcg_gen_movi_i32(cpu_pc, ctx->pc); | |
1317 | imm = tcg_const_i32(B7_0); | |
1318 | tcg_gen_helper_0_1(helper_trapa, imm); | |
1319 | tcg_temp_free(imm); | |
1320 | ctx->bstate = BS_BRANCH; | |
1321 | } | |
fdf9b3e8 FB |
1322 | return; |
1323 | case 0xc800: /* tst #imm,R0 */ | |
c55497ec AJ |
1324 | { |
1325 | TCGv val = tcg_temp_new(TCG_TYPE_I32); | |
1326 | tcg_gen_andi_i32(val, REG(0), B7_0); | |
1327 | gen_cmp_imm(TCG_COND_EQ, val, 0); | |
1328 | tcg_temp_free(val); | |
1329 | } | |
fdf9b3e8 | 1330 | return; |
24988dc2 | 1331 | case 0xcc00: /* tst.b #imm,@(R0,GBR) */ |
c55497ec AJ |
1332 | { |
1333 | TCGv val = tcg_temp_new(TCG_TYPE_I32); | |
1334 | tcg_gen_add_i32(val, REG(0), cpu_gbr); | |
1335 | tcg_gen_qemu_ld8u(val, val, ctx->memidx); | |
1336 | tcg_gen_andi_i32(val, val, B7_0); | |
1337 | gen_cmp_imm(TCG_COND_EQ, val, 0); | |
1338 | tcg_temp_free(val); | |
1339 | } | |
fdf9b3e8 FB |
1340 | return; |
1341 | case 0xca00: /* xor #imm,R0 */ | |
7efbe241 | 1342 | tcg_gen_xori_i32(REG(0), REG(0), B7_0); |
fdf9b3e8 | 1343 | return; |
24988dc2 | 1344 | case 0xce00: /* xor.b #imm,@(R0,GBR) */ |
c55497ec AJ |
1345 | { |
1346 | TCGv addr, val; | |
1347 | addr = tcg_temp_new(TCG_TYPE_I32); | |
1348 | tcg_gen_add_i32(addr, REG(0), cpu_gbr); | |
1349 | val = tcg_temp_new(TCG_TYPE_I32); | |
1350 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); | |
1351 | tcg_gen_xori_i32(val, val, B7_0); | |
1352 | tcg_gen_qemu_st8(val, addr, ctx->memidx); | |
1353 | tcg_temp_free(val); | |
1354 | tcg_temp_free(addr); | |
1355 | } | |
fdf9b3e8 FB |
1356 | return; |
1357 | } | |
1358 | ||
1359 | switch (ctx->opcode & 0xf08f) { | |
1360 | case 0x408e: /* ldc Rm,Rn_BANK */ | |
fe25591e | 1361 | CHECK_PRIVILEGED |
7efbe241 | 1362 | tcg_gen_mov_i32(ALTREG(B6_4), REG(B11_8)); |
fdf9b3e8 FB |
1363 | return; |
1364 | case 0x4087: /* ldc.l @Rm+,Rn_BANK */ | |
fe25591e | 1365 | CHECK_PRIVILEGED |
7efbe241 AJ |
1366 | tcg_gen_qemu_ld32s(ALTREG(B6_4), REG(B11_8), ctx->memidx); |
1367 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); | |
fdf9b3e8 FB |
1368 | return; |
1369 | case 0x0082: /* stc Rm_BANK,Rn */ | |
fe25591e | 1370 | CHECK_PRIVILEGED |
7efbe241 | 1371 | tcg_gen_mov_i32(REG(B11_8), ALTREG(B6_4)); |
fdf9b3e8 FB |
1372 | return; |
1373 | case 0x4083: /* stc.l Rm_BANK,@-Rn */ | |
fe25591e | 1374 | CHECK_PRIVILEGED |
c55497ec AJ |
1375 | { |
1376 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
1377 | tcg_gen_subi_i32(addr, REG(B11_8), 4); | |
1378 | tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx); | |
1379 | tcg_temp_free(addr); | |
1380 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); | |
1381 | } | |
fdf9b3e8 FB |
1382 | return; |
1383 | } | |
1384 | ||
1385 | switch (ctx->opcode & 0xf0ff) { | |
1386 | case 0x0023: /* braf Rn */ | |
7efbe241 AJ |
1387 | CHECK_NOT_DELAY_SLOT |
1388 | tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->pc + 4); | |
fdf9b3e8 FB |
1389 | ctx->flags |= DELAY_SLOT; |
1390 | ctx->delayed_pc = (uint32_t) - 1; | |
1391 | return; | |
1392 | case 0x0003: /* bsrf Rn */ | |
7efbe241 | 1393 | CHECK_NOT_DELAY_SLOT |
1000822b | 1394 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4); |
7efbe241 | 1395 | tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr); |
fdf9b3e8 FB |
1396 | ctx->flags |= DELAY_SLOT; |
1397 | ctx->delayed_pc = (uint32_t) - 1; | |
1398 | return; | |
1399 | case 0x4015: /* cmp/pl Rn */ | |
7efbe241 | 1400 | gen_cmp_imm(TCG_COND_GT, REG(B11_8), 0); |
fdf9b3e8 FB |
1401 | return; |
1402 | case 0x4011: /* cmp/pz Rn */ | |
7efbe241 | 1403 | gen_cmp_imm(TCG_COND_GE, REG(B11_8), 0); |
fdf9b3e8 FB |
1404 | return; |
1405 | case 0x4010: /* dt Rn */ | |
7efbe241 AJ |
1406 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); |
1407 | gen_cmp_imm(TCG_COND_EQ, REG(B11_8), 0); | |
fdf9b3e8 FB |
1408 | return; |
1409 | case 0x402b: /* jmp @Rn */ | |
7efbe241 AJ |
1410 | CHECK_NOT_DELAY_SLOT |
1411 | tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); | |
fdf9b3e8 FB |
1412 | ctx->flags |= DELAY_SLOT; |
1413 | ctx->delayed_pc = (uint32_t) - 1; | |
1414 | return; | |
1415 | case 0x400b: /* jsr @Rn */ | |
7efbe241 | 1416 | CHECK_NOT_DELAY_SLOT |
1000822b | 1417 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4); |
7efbe241 | 1418 | tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); |
fdf9b3e8 FB |
1419 | ctx->flags |= DELAY_SLOT; |
1420 | ctx->delayed_pc = (uint32_t) - 1; | |
1421 | return; | |
fe25591e AJ |
1422 | case 0x400e: /* ldc Rm,SR */ |
1423 | CHECK_PRIVILEGED | |
7efbe241 | 1424 | tcg_gen_andi_i32(cpu_sr, REG(B11_8), 0x700083f3); |
390af821 AJ |
1425 | ctx->bstate = BS_STOP; |
1426 | return; | |
fe25591e AJ |
1427 | case 0x4007: /* ldc.l @Rm+,SR */ |
1428 | CHECK_PRIVILEGED | |
c55497ec AJ |
1429 | { |
1430 | TCGv val = tcg_temp_new(TCG_TYPE_I32); | |
1431 | tcg_gen_qemu_ld32s(val, REG(B11_8), ctx->memidx); | |
1432 | tcg_gen_andi_i32(cpu_sr, val, 0x700083f3); | |
1433 | tcg_temp_free(val); | |
1434 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); | |
1435 | ctx->bstate = BS_STOP; | |
1436 | } | |
390af821 | 1437 | return; |
fe25591e AJ |
1438 | case 0x0002: /* stc SR,Rn */ |
1439 | CHECK_PRIVILEGED | |
7efbe241 | 1440 | tcg_gen_mov_i32(REG(B11_8), cpu_sr); |
390af821 | 1441 | return; |
fe25591e AJ |
1442 | case 0x4003: /* stc SR,@-Rn */ |
1443 | CHECK_PRIVILEGED | |
c55497ec AJ |
1444 | { |
1445 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
1446 | tcg_gen_subi_i32(addr, REG(B11_8), 4); | |
1447 | tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx); | |
1448 | tcg_temp_free(addr); | |
1449 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); | |
1450 | } | |
390af821 | 1451 | return; |
fe25591e | 1452 | #define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \ |
fdf9b3e8 | 1453 | case ldnum: \ |
fe25591e | 1454 | prechk \ |
7efbe241 | 1455 | tcg_gen_mov_i32 (cpu_##reg, REG(B11_8)); \ |
fdf9b3e8 FB |
1456 | return; \ |
1457 | case ldpnum: \ | |
fe25591e | 1458 | prechk \ |
7efbe241 AJ |
1459 | tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx); \ |
1460 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); \ | |
fdf9b3e8 FB |
1461 | return; \ |
1462 | case stnum: \ | |
fe25591e | 1463 | prechk \ |
7efbe241 | 1464 | tcg_gen_mov_i32 (REG(B11_8), cpu_##reg); \ |
fdf9b3e8 FB |
1465 | return; \ |
1466 | case stpnum: \ | |
fe25591e | 1467 | prechk \ |
c55497ec AJ |
1468 | { \ |
1469 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); \ | |
1470 | tcg_gen_subi_i32(addr, REG(B11_8), 4); \ | |
1471 | tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx); \ | |
1472 | tcg_temp_free(addr); \ | |
1473 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); \ | |
86e0abc7 | 1474 | } \ |
fdf9b3e8 | 1475 | return; |
fe25591e AJ |
1476 | LDST(gbr, 0x401e, 0x4017, 0x0012, 0x4013, {}) |
1477 | LDST(vbr, 0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED) | |
1478 | LDST(ssr, 0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED) | |
1479 | LDST(spc, 0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED) | |
1480 | LDST(dbr, 0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED) | |
1481 | LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {}) | |
1482 | LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {}) | |
1483 | LDST(pr, 0x402a, 0x4026, 0x002a, 0x4022, {}) | |
1484 | LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {}) | |
390af821 | 1485 | case 0x406a: /* lds Rm,FPSCR */ |
7efbe241 | 1486 | tcg_gen_helper_0_1(helper_ld_fpscr, REG(B11_8)); |
390af821 AJ |
1487 | ctx->bstate = BS_STOP; |
1488 | return; | |
1489 | case 0x4066: /* lds.l @Rm+,FPSCR */ | |
c55497ec AJ |
1490 | { |
1491 | TCGv addr = tcg_temp_new(TCG_TYPE_I32); | |
1492 | tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx); | |
1493 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); | |
1494 | tcg_gen_helper_0_1(helper_ld_fpscr, addr); | |
1495 | tcg_temp_free(addr); | |
1496 | ctx->bstate = BS_STOP; | |
1497 | } | |
390af821 AJ |
1498 | return; |
1499 | case 0x006a: /* sts FPSCR,Rn */ | |
c55497ec | 1500 | tcg_gen_andi_i32(REG(B11_8), cpu_fpscr, 0x003fffff); |
390af821 AJ |
1501 | return; |
1502 | case 0x4062: /* sts FPSCR,@-Rn */ | |
c55497ec AJ |
1503 | { |
1504 | TCGv addr, val; | |
1505 | val = tcg_temp_new(TCG_TYPE_I32); | |
1506 | tcg_gen_andi_i32(val, cpu_fpscr, 0x003fffff); | |
1507 | addr = tcg_temp_new(TCG_TYPE_I32); | |
1508 | tcg_gen_subi_i32(addr, REG(B11_8), 4); | |
1509 | tcg_gen_qemu_st32(val, addr, ctx->memidx); | |
1510 | tcg_temp_free(addr); | |
1511 | tcg_temp_free(val); | |
1512 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); | |
1513 | } | |
390af821 | 1514 | return; |
fdf9b3e8 | 1515 | case 0x00c3: /* movca.l R0,@Rm */ |
7efbe241 | 1516 | tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx); |
fdf9b3e8 FB |
1517 | return; |
1518 | case 0x0029: /* movt Rn */ | |
7efbe241 | 1519 | tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T); |
fdf9b3e8 FB |
1520 | return; |
1521 | case 0x0093: /* ocbi @Rn */ | |
c55497ec AJ |
1522 | { |
1523 | TCGv dummy = tcg_temp_new(TCG_TYPE_I32); | |
1524 | tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); | |
1525 | tcg_temp_free(dummy); | |
1526 | } | |
fdf9b3e8 | 1527 | return; |
24988dc2 | 1528 | case 0x00a3: /* ocbp @Rn */ |
c55497ec AJ |
1529 | { |
1530 | TCGv dummy = tcg_temp_new(TCG_TYPE_I32); | |
1531 | tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); | |
1532 | tcg_temp_free(dummy); | |
1533 | } | |
fdf9b3e8 FB |
1534 | return; |
1535 | case 0x00b3: /* ocbwb @Rn */ | |
c55497ec AJ |
1536 | { |
1537 | TCGv dummy = tcg_temp_new(TCG_TYPE_I32); | |
1538 | tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); | |
1539 | tcg_temp_free(dummy); | |
1540 | } | |
fdf9b3e8 FB |
1541 | return; |
1542 | case 0x0083: /* pref @Rn */ | |
1543 | return; | |
1544 | case 0x4024: /* rotcl Rn */ | |
c55497ec AJ |
1545 | { |
1546 | TCGv tmp = tcg_temp_new(TCG_TYPE_I32); | |
1547 | tcg_gen_mov_i32(tmp, cpu_sr); | |
1548 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); | |
1549 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); | |
1550 | gen_copy_bit_i32(REG(B11_8), 0, tmp, 0); | |
1551 | tcg_temp_free(tmp); | |
1552 | } | |
fdf9b3e8 FB |
1553 | return; |
1554 | case 0x4025: /* rotcr Rn */ | |
c55497ec AJ |
1555 | { |
1556 | TCGv tmp = tcg_temp_new(TCG_TYPE_I32); | |
1557 | tcg_gen_mov_i32(tmp, cpu_sr); | |
1558 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); | |
1559 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1); | |
1560 | gen_copy_bit_i32(REG(B11_8), 31, tmp, 0); | |
1561 | tcg_temp_free(tmp); | |
1562 | } | |
fdf9b3e8 FB |
1563 | return; |
1564 | case 0x4004: /* rotl Rn */ | |
7efbe241 AJ |
1565 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); |
1566 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); | |
1567 | gen_copy_bit_i32(REG(B11_8), 0, cpu_sr, 0); | |
fdf9b3e8 FB |
1568 | return; |
1569 | case 0x4005: /* rotr Rn */ | |
7efbe241 AJ |
1570 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1571 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1); | |
1572 | gen_copy_bit_i32(REG(B11_8), 31, cpu_sr, 0); | |
fdf9b3e8 FB |
1573 | return; |
1574 | case 0x4000: /* shll Rn */ | |
1575 | case 0x4020: /* shal Rn */ | |
7efbe241 AJ |
1576 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); |
1577 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); | |
fdf9b3e8 FB |
1578 | return; |
1579 | case 0x4021: /* shar Rn */ | |
7efbe241 AJ |
1580 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1581 | tcg_gen_sari_i32(REG(B11_8), REG(B11_8), 1); | |
fdf9b3e8 FB |
1582 | return; |
1583 | case 0x4001: /* shlr Rn */ | |
7efbe241 AJ |
1584 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1585 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1); | |
fdf9b3e8 FB |
1586 | return; |
1587 | case 0x4008: /* shll2 Rn */ | |
7efbe241 | 1588 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 2); |
fdf9b3e8 FB |
1589 | return; |
1590 | case 0x4018: /* shll8 Rn */ | |
7efbe241 | 1591 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 8); |
fdf9b3e8 FB |
1592 | return; |
1593 | case 0x4028: /* shll16 Rn */ | |
7efbe241 | 1594 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 16); |
fdf9b3e8 FB |
1595 | return; |
1596 | case 0x4009: /* shlr2 Rn */ | |
7efbe241 | 1597 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 2); |
fdf9b3e8 FB |
1598 | return; |
1599 | case 0x4019: /* shlr8 Rn */ | |
7efbe241 | 1600 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 8); |
fdf9b3e8 FB |
1601 | return; |
1602 | case 0x4029: /* shlr16 Rn */ | |
7efbe241 | 1603 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16); |
fdf9b3e8 FB |
1604 | return; |
1605 | case 0x401b: /* tas.b @Rn */ | |
c55497ec AJ |
1606 | { |
1607 | TCGv addr, val; | |
1608 | addr = tcg_temp_local_new(TCG_TYPE_I32); | |
1609 | tcg_gen_mov_i32(addr, REG(B11_8)); | |
1610 | val = tcg_temp_local_new(TCG_TYPE_I32); | |
1611 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); | |
1612 | gen_cmp_imm(TCG_COND_EQ, val, 0); | |
1613 | tcg_gen_ori_i32(val, val, 0x80); | |
1614 | tcg_gen_qemu_st8(val, addr, ctx->memidx); | |
1615 | tcg_temp_free(val); | |
1616 | tcg_temp_free(addr); | |
1617 | } | |
fdf9b3e8 | 1618 | return; |
e67888a7 | 1619 | case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ |
cc4ba6a9 AJ |
1620 | { |
1621 | TCGv fp = tcg_temp_new(TCG_TYPE_I32); | |
1622 | tcg_gen_mov_i32(fp, cpu_fpul); | |
1623 | gen_store_fpr32(fp, FREG(B11_8)); | |
1624 | tcg_temp_free(fp); | |
1625 | } | |
eda9b09b | 1626 | return; |
e67888a7 | 1627 | case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */ |
cc4ba6a9 AJ |
1628 | { |
1629 | TCGv fp = tcg_temp_new(TCG_TYPE_I32); | |
1630 | gen_load_fpr32(fp, FREG(B11_8)); | |
1631 | tcg_gen_mov_i32(cpu_fpul, fp); | |
1632 | tcg_temp_free(fp); | |
1633 | } | |
eda9b09b | 1634 | return; |
e67888a7 | 1635 | case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */ |
ea6cf6be | 1636 | if (ctx->fpscr & FPSCR_PR) { |
cc4ba6a9 | 1637 | TCGv fp; |
ea6cf6be TS |
1638 | if (ctx->opcode & 0x0100) |
1639 | break; /* illegal instruction */ | |
cc4ba6a9 AJ |
1640 | fp = tcg_temp_new(TCG_TYPE_I64); |
1641 | tcg_gen_helper_1_1(helper_float_DT, fp, cpu_fpul); | |
1642 | gen_store_fpr64(fp, DREG(B11_8)); | |
1643 | tcg_temp_free(fp); | |
ea6cf6be TS |
1644 | } |
1645 | else { | |
cc4ba6a9 AJ |
1646 | TCGv fp = tcg_temp_new(TCG_TYPE_I32); |
1647 | tcg_gen_helper_1_1(helper_float_FT, fp, cpu_fpul); | |
1648 | gen_store_fpr32(fp, FREG(B11_8)); | |
1649 | tcg_temp_free(fp); | |
ea6cf6be TS |
1650 | } |
1651 | return; | |
e67888a7 | 1652 | case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
ea6cf6be | 1653 | if (ctx->fpscr & FPSCR_PR) { |
cc4ba6a9 | 1654 | TCGv fp; |
ea6cf6be TS |
1655 | if (ctx->opcode & 0x0100) |
1656 | break; /* illegal instruction */ | |
cc4ba6a9 AJ |
1657 | fp = tcg_temp_new(TCG_TYPE_I64); |
1658 | gen_load_fpr64(fp, DREG(B11_8)); | |
1659 | tcg_gen_helper_1_1(helper_ftrc_DT, cpu_fpul, fp); | |
1660 | tcg_temp_free(fp); | |
ea6cf6be TS |
1661 | } |
1662 | else { | |
cc4ba6a9 AJ |
1663 | TCGv fp = tcg_temp_new(TCG_TYPE_I32); |
1664 | gen_load_fpr32(fp, FREG(B11_8)); | |
1665 | tcg_gen_helper_1_1(helper_ftrc_FT, cpu_fpul, fp); | |
1666 | tcg_temp_free(fp); | |
ea6cf6be TS |
1667 | } |
1668 | return; | |
24988dc2 | 1669 | case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ |
7fdf924f AJ |
1670 | { |
1671 | TCGv fp = tcg_temp_new(TCG_TYPE_I32); | |
1672 | gen_load_fpr32(fp, FREG(B11_8)); | |
1673 | tcg_gen_helper_1_1(helper_fneg_T, fp, fp); | |
1674 | gen_store_fpr32(fp, FREG(B11_8)); | |
1675 | tcg_temp_free(fp); | |
1676 | } | |
24988dc2 AJ |
1677 | return; |
1678 | case 0xf05d: /* fabs FRn/DRn */ | |
1679 | if (ctx->fpscr & FPSCR_PR) { | |
1680 | if (ctx->opcode & 0x0100) | |
1681 | break; /* illegal instruction */ | |
cc4ba6a9 AJ |
1682 | TCGv fp = tcg_temp_new(TCG_TYPE_I64); |
1683 | gen_load_fpr64(fp, DREG(B11_8)); | |
1684 | tcg_gen_helper_1_1(helper_fabs_DT, fp, fp); | |
1685 | gen_store_fpr64(fp, DREG(B11_8)); | |
1686 | tcg_temp_free(fp); | |
24988dc2 | 1687 | } else { |
cc4ba6a9 AJ |
1688 | TCGv fp = tcg_temp_new(TCG_TYPE_I32); |
1689 | gen_load_fpr32(fp, FREG(B11_8)); | |
1690 | tcg_gen_helper_1_1(helper_fabs_FT, fp, fp); | |
1691 | gen_store_fpr32(fp, FREG(B11_8)); | |
1692 | tcg_temp_free(fp); | |
24988dc2 AJ |
1693 | } |
1694 | return; | |
1695 | case 0xf06d: /* fsqrt FRn */ | |
1696 | if (ctx->fpscr & FPSCR_PR) { | |
1697 | if (ctx->opcode & 0x0100) | |
1698 | break; /* illegal instruction */ | |
cc4ba6a9 AJ |
1699 | TCGv fp = tcg_temp_new(TCG_TYPE_I64); |
1700 | gen_load_fpr64(fp, DREG(B11_8)); | |
1701 | tcg_gen_helper_1_1(helper_fsqrt_DT, fp, fp); | |
1702 | gen_store_fpr64(fp, DREG(B11_8)); | |
1703 | tcg_temp_free(fp); | |
24988dc2 | 1704 | } else { |
cc4ba6a9 AJ |
1705 | TCGv fp = tcg_temp_new(TCG_TYPE_I32); |
1706 | gen_load_fpr32(fp, FREG(B11_8)); | |
1707 | tcg_gen_helper_1_1(helper_fsqrt_FT, fp, fp); | |
1708 | gen_store_fpr32(fp, FREG(B11_8)); | |
1709 | tcg_temp_free(fp); | |
24988dc2 AJ |
1710 | } |
1711 | return; | |
1712 | case 0xf07d: /* fsrra FRn */ | |
1713 | break; | |
e67888a7 | 1714 | case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ |
ea6cf6be | 1715 | if (!(ctx->fpscr & FPSCR_PR)) { |
cc4ba6a9 AJ |
1716 | TCGv val = tcg_const_i32(0); |
1717 | gen_load_fpr32(val, FREG(B11_8)); | |
1718 | tcg_temp_free(val); | |
ea6cf6be TS |
1719 | return; |
1720 | } | |
1721 | break; | |
e67888a7 | 1722 | case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ |
ea6cf6be | 1723 | if (!(ctx->fpscr & FPSCR_PR)) { |
cc4ba6a9 AJ |
1724 | TCGv val = tcg_const_i32(0x3f800000); |
1725 | gen_load_fpr32(val, FREG(B11_8)); | |
1726 | tcg_temp_free(val); | |
ea6cf6be TS |
1727 | return; |
1728 | } | |
1729 | break; | |
24988dc2 | 1730 | case 0xf0ad: /* fcnvsd FPUL,DRn */ |
cc4ba6a9 AJ |
1731 | { |
1732 | TCGv fp = tcg_temp_new(TCG_TYPE_I64); | |
1733 | tcg_gen_helper_1_1(helper_fcnvsd_FT_DT, fp, cpu_fpul); | |
1734 | gen_store_fpr64(fp, DREG(B11_8)); | |
1735 | tcg_temp_free(fp); | |
1736 | } | |
24988dc2 AJ |
1737 | return; |
1738 | case 0xf0bd: /* fcnvds DRn,FPUL */ | |
cc4ba6a9 AJ |
1739 | { |
1740 | TCGv fp = tcg_temp_new(TCG_TYPE_I64); | |
1741 | gen_load_fpr64(fp, DREG(B11_8)); | |
1742 | tcg_gen_helper_1_1(helper_fcnvds_DT_FT, cpu_fpul, fp); | |
1743 | tcg_temp_free(fp); | |
1744 | } | |
24988dc2 | 1745 | return; |
fdf9b3e8 FB |
1746 | } |
1747 | ||
1748 | fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n", | |
1749 | ctx->opcode, ctx->pc); | |
e6afc2f4 | 1750 | tcg_gen_helper_0_0(helper_raise_illegal_instruction); |
823029f9 TS |
1751 | ctx->bstate = BS_EXCP; |
1752 | } | |
1753 | ||
1754 | void decode_opc(DisasContext * ctx) | |
1755 | { | |
1756 | uint32_t old_flags = ctx->flags; | |
1757 | ||
1758 | _decode_opc(ctx); | |
1759 | ||
1760 | if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { | |
1761 | if (ctx->flags & DELAY_SLOT_CLEARME) { | |
1000822b | 1762 | gen_store_flags(0); |
274a9e70 AJ |
1763 | } else { |
1764 | /* go out of the delay slot */ | |
1765 | uint32_t new_flags = ctx->flags; | |
1766 | new_flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); | |
1000822b | 1767 | gen_store_flags(new_flags); |
823029f9 TS |
1768 | } |
1769 | ctx->flags = 0; | |
1770 | ctx->bstate = BS_BRANCH; | |
1771 | if (old_flags & DELAY_SLOT_CONDITIONAL) { | |
1772 | gen_delayed_conditional_jump(ctx); | |
1773 | } else if (old_flags & DELAY_SLOT) { | |
1774 | gen_jump(ctx); | |
1775 | } | |
1776 | ||
1777 | } | |
274a9e70 AJ |
1778 | |
1779 | /* go into a delay slot */ | |
1780 | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) | |
1000822b | 1781 | gen_store_flags(ctx->flags); |
fdf9b3e8 FB |
1782 | } |
1783 | ||
2cfc5f17 | 1784 | static inline void |
820e00f2 TS |
1785 | gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb, |
1786 | int search_pc) | |
fdf9b3e8 FB |
1787 | { |
1788 | DisasContext ctx; | |
1789 | target_ulong pc_start; | |
1790 | static uint16_t *gen_opc_end; | |
355fb23d | 1791 | int i, ii; |
2e70f6ef PB |
1792 | int num_insns; |
1793 | int max_insns; | |
fdf9b3e8 FB |
1794 | |
1795 | pc_start = tb->pc; | |
fdf9b3e8 | 1796 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
fdf9b3e8 | 1797 | ctx.pc = pc_start; |
823029f9 TS |
1798 | ctx.flags = (uint32_t)tb->flags; |
1799 | ctx.bstate = BS_NONE; | |
fdf9b3e8 | 1800 | ctx.sr = env->sr; |
eda9b09b | 1801 | ctx.fpscr = env->fpscr; |
fdf9b3e8 | 1802 | ctx.memidx = (env->sr & SR_MD) ? 1 : 0; |
9854bc46 PB |
1803 | /* We don't know if the delayed pc came from a dynamic or static branch, |
1804 | so assume it is a dynamic branch. */ | |
823029f9 | 1805 | ctx.delayed_pc = -1; /* use delayed pc from env pointer */ |
fdf9b3e8 FB |
1806 | ctx.tb = tb; |
1807 | ctx.singlestep_enabled = env->singlestep_enabled; | |
fdf9b3e8 FB |
1808 | |
1809 | #ifdef DEBUG_DISAS | |
1810 | if (loglevel & CPU_LOG_TB_CPU) { | |
1811 | fprintf(logfile, | |
1812 | "------------------------------------------------\n"); | |
1813 | cpu_dump_state(env, logfile, fprintf, 0); | |
1814 | } | |
1815 | #endif | |
1816 | ||
355fb23d | 1817 | ii = -1; |
2e70f6ef PB |
1818 | num_insns = 0; |
1819 | max_insns = tb->cflags & CF_COUNT_MASK; | |
1820 | if (max_insns == 0) | |
1821 | max_insns = CF_COUNT_MASK; | |
1822 | gen_icount_start(); | |
823029f9 | 1823 | while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) { |
fdf9b3e8 FB |
1824 | if (env->nb_breakpoints > 0) { |
1825 | for (i = 0; i < env->nb_breakpoints; i++) { | |
1826 | if (ctx.pc == env->breakpoints[i]) { | |
1827 | /* We have hit a breakpoint - make sure PC is up-to-date */ | |
3a8a44c4 | 1828 | tcg_gen_movi_i32(cpu_pc, ctx.pc); |
e6afc2f4 | 1829 | tcg_gen_helper_0_0(helper_debug); |
823029f9 | 1830 | ctx.bstate = BS_EXCP; |
fdf9b3e8 FB |
1831 | break; |
1832 | } | |
1833 | } | |
1834 | } | |
355fb23d PB |
1835 | if (search_pc) { |
1836 | i = gen_opc_ptr - gen_opc_buf; | |
1837 | if (ii < i) { | |
1838 | ii++; | |
1839 | while (ii < i) | |
1840 | gen_opc_instr_start[ii++] = 0; | |
1841 | } | |
1842 | gen_opc_pc[ii] = ctx.pc; | |
823029f9 | 1843 | gen_opc_hflags[ii] = ctx.flags; |
355fb23d | 1844 | gen_opc_instr_start[ii] = 1; |
2e70f6ef | 1845 | gen_opc_icount[ii] = num_insns; |
355fb23d | 1846 | } |
2e70f6ef PB |
1847 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
1848 | gen_io_start(); | |
fdf9b3e8 FB |
1849 | #if 0 |
1850 | fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc); | |
1851 | fflush(stderr); | |
1852 | #endif | |
1853 | ctx.opcode = lduw_code(ctx.pc); | |
1854 | decode_opc(&ctx); | |
2e70f6ef | 1855 | num_insns++; |
fdf9b3e8 FB |
1856 | ctx.pc += 2; |
1857 | if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) | |
1858 | break; | |
1859 | if (env->singlestep_enabled) | |
1860 | break; | |
2e70f6ef PB |
1861 | if (num_insns >= max_insns) |
1862 | break; | |
fdf9b3e8 FB |
1863 | #ifdef SH4_SINGLE_STEP |
1864 | break; | |
1865 | #endif | |
1866 | } | |
2e70f6ef PB |
1867 | if (tb->cflags & CF_LAST_IO) |
1868 | gen_io_end(); | |
fdf9b3e8 | 1869 | if (env->singlestep_enabled) { |
e6afc2f4 | 1870 | tcg_gen_helper_0_0(helper_debug); |
823029f9 TS |
1871 | } else { |
1872 | switch (ctx.bstate) { | |
1873 | case BS_STOP: | |
1874 | /* gen_op_interrupt_restart(); */ | |
1875 | /* fall through */ | |
1876 | case BS_NONE: | |
1877 | if (ctx.flags) { | |
1000822b | 1878 | gen_store_flags(ctx.flags | DELAY_SLOT_CLEARME); |
823029f9 TS |
1879 | } |
1880 | gen_goto_tb(&ctx, 0, ctx.pc); | |
1881 | break; | |
1882 | case BS_EXCP: | |
1883 | /* gen_op_interrupt_restart(); */ | |
57fec1fe | 1884 | tcg_gen_exit_tb(0); |
823029f9 TS |
1885 | break; |
1886 | case BS_BRANCH: | |
1887 | default: | |
1888 | break; | |
1889 | } | |
fdf9b3e8 | 1890 | } |
823029f9 | 1891 | |
2e70f6ef | 1892 | gen_icount_end(tb, num_insns); |
fdf9b3e8 | 1893 | *gen_opc_ptr = INDEX_op_end; |
355fb23d PB |
1894 | if (search_pc) { |
1895 | i = gen_opc_ptr - gen_opc_buf; | |
1896 | ii++; | |
1897 | while (ii <= i) | |
1898 | gen_opc_instr_start[ii++] = 0; | |
355fb23d PB |
1899 | } else { |
1900 | tb->size = ctx.pc - pc_start; | |
2e70f6ef | 1901 | tb->icount = num_insns; |
355fb23d | 1902 | } |
fdf9b3e8 FB |
1903 | |
1904 | #ifdef DEBUG_DISAS | |
1905 | #ifdef SH4_DEBUG_DISAS | |
1906 | if (loglevel & CPU_LOG_TB_IN_ASM) | |
1907 | fprintf(logfile, "\n"); | |
1908 | #endif | |
1909 | if (loglevel & CPU_LOG_TB_IN_ASM) { | |
1910 | fprintf(logfile, "IN:\n"); /* , lookup_symbol(pc_start)); */ | |
1911 | target_disas(logfile, pc_start, ctx.pc - pc_start, 0); | |
1912 | fprintf(logfile, "\n"); | |
1913 | } | |
fdf9b3e8 | 1914 | #endif |
fdf9b3e8 FB |
1915 | } |
1916 | ||
2cfc5f17 | 1917 | void gen_intermediate_code(CPUState * env, struct TranslationBlock *tb) |
fdf9b3e8 | 1918 | { |
2cfc5f17 | 1919 | gen_intermediate_code_internal(env, tb, 0); |
fdf9b3e8 FB |
1920 | } |
1921 | ||
2cfc5f17 | 1922 | void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb) |
fdf9b3e8 | 1923 | { |
2cfc5f17 | 1924 | gen_intermediate_code_internal(env, tb, 1); |
fdf9b3e8 | 1925 | } |
d2856f1a AJ |
1926 | |
1927 | void gen_pc_load(CPUState *env, TranslationBlock *tb, | |
1928 | unsigned long searched_pc, int pc_pos, void *puc) | |
1929 | { | |
1930 | env->pc = gen_opc_pc[pc_pos]; | |
1931 | env->flags = gen_opc_hflags[pc_pos]; | |
1932 | } |