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Commit | Line | Data |
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fdf9b3e8 FB |
1 | /* |
2 | * SH4 translation | |
5fafdf24 | 3 | * |
fdf9b3e8 FB |
4 | * Copyright (c) 2005 Samuel Tardieu |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | #include <stdarg.h> | |
21 | #include <stdlib.h> | |
22 | #include <stdio.h> | |
23 | #include <string.h> | |
24 | #include <inttypes.h> | |
25 | #include <assert.h> | |
26 | ||
27 | #define DEBUG_DISAS | |
28 | #define SH4_DEBUG_DISAS | |
29 | //#define SH4_SINGLE_STEP | |
30 | ||
31 | #include "cpu.h" | |
32 | #include "exec-all.h" | |
33 | #include "disas.h" | |
57fec1fe | 34 | #include "tcg-op.h" |
ca10f867 | 35 | #include "qemu-common.h" |
fdf9b3e8 | 36 | |
a7812ae4 PB |
37 | #include "helper.h" |
38 | #define GEN_HELPER 1 | |
39 | #include "helper.h" | |
40 | ||
fdf9b3e8 FB |
41 | typedef struct DisasContext { |
42 | struct TranslationBlock *tb; | |
43 | target_ulong pc; | |
44 | uint32_t sr; | |
eda9b09b | 45 | uint32_t fpscr; |
fdf9b3e8 FB |
46 | uint16_t opcode; |
47 | uint32_t flags; | |
823029f9 | 48 | int bstate; |
fdf9b3e8 FB |
49 | int memidx; |
50 | uint32_t delayed_pc; | |
51 | int singlestep_enabled; | |
52 | } DisasContext; | |
53 | ||
fe25591e AJ |
54 | #if defined(CONFIG_USER_ONLY) |
55 | #define IS_USER(ctx) 1 | |
56 | #else | |
57 | #define IS_USER(ctx) (!(ctx->sr & SR_MD)) | |
58 | #endif | |
59 | ||
823029f9 TS |
60 | enum { |
61 | BS_NONE = 0, /* We go out of the TB without reaching a branch or an | |
62 | * exception condition | |
63 | */ | |
64 | BS_STOP = 1, /* We want to stop translation for any reason */ | |
65 | BS_BRANCH = 2, /* We reached a branch condition */ | |
66 | BS_EXCP = 3, /* We reached an exception condition */ | |
67 | }; | |
68 | ||
1e8864f7 | 69 | /* global register indexes */ |
a7812ae4 | 70 | static TCGv_ptr cpu_env; |
1e8864f7 | 71 | static TCGv cpu_gregs[24]; |
3a8a44c4 AJ |
72 | static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr; |
73 | static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl; | |
1000822b | 74 | static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_flags; |
66ba317c | 75 | static TCGv cpu_fregs[32]; |
1000822b AJ |
76 | |
77 | /* internal register indexes */ | |
78 | static TCGv cpu_flags, cpu_delayed_pc; | |
1e8864f7 | 79 | |
2e70f6ef PB |
80 | #include "gen-icount.h" |
81 | ||
a5f1b965 | 82 | static void sh4_translate_init(void) |
2e70f6ef | 83 | { |
1e8864f7 | 84 | int i; |
2e70f6ef | 85 | static int done_init = 0; |
559dd74d | 86 | static const char * const gregnames[24] = { |
1e8864f7 AJ |
87 | "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0", |
88 | "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0", | |
89 | "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", | |
90 | "R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1", | |
91 | "R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1" | |
92 | }; | |
66ba317c AJ |
93 | static const char * const fregnames[32] = { |
94 | "FPR0_BANK0", "FPR1_BANK0", "FPR2_BANK0", "FPR3_BANK0", | |
95 | "FPR4_BANK0", "FPR5_BANK0", "FPR6_BANK0", "FPR7_BANK0", | |
96 | "FPR8_BANK0", "FPR9_BANK0", "FPR10_BANK0", "FPR11_BANK0", | |
97 | "FPR12_BANK0", "FPR13_BANK0", "FPR14_BANK0", "FPR15_BANK0", | |
98 | "FPR0_BANK1", "FPR1_BANK1", "FPR2_BANK1", "FPR3_BANK1", | |
99 | "FPR4_BANK1", "FPR5_BANK1", "FPR6_BANK1", "FPR7_BANK1", | |
100 | "FPR8_BANK1", "FPR9_BANK1", "FPR10_BANK1", "FPR11_BANK1", | |
101 | "FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1", | |
102 | }; | |
1e8864f7 | 103 | |
2e70f6ef PB |
104 | if (done_init) |
105 | return; | |
1e8864f7 | 106 | |
a7812ae4 | 107 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
1e8864f7 AJ |
108 | |
109 | for (i = 0; i < 24; i++) | |
a7812ae4 | 110 | cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0, |
66ba317c AJ |
111 | offsetof(CPUState, gregs[i]), |
112 | gregnames[i]); | |
988d7eaa | 113 | |
a7812ae4 PB |
114 | cpu_pc = tcg_global_mem_new_i32(TCG_AREG0, |
115 | offsetof(CPUState, pc), "PC"); | |
116 | cpu_sr = tcg_global_mem_new_i32(TCG_AREG0, | |
117 | offsetof(CPUState, sr), "SR"); | |
118 | cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0, | |
119 | offsetof(CPUState, ssr), "SSR"); | |
120 | cpu_spc = tcg_global_mem_new_i32(TCG_AREG0, | |
121 | offsetof(CPUState, spc), "SPC"); | |
122 | cpu_gbr = tcg_global_mem_new_i32(TCG_AREG0, | |
123 | offsetof(CPUState, gbr), "GBR"); | |
124 | cpu_vbr = tcg_global_mem_new_i32(TCG_AREG0, | |
125 | offsetof(CPUState, vbr), "VBR"); | |
126 | cpu_sgr = tcg_global_mem_new_i32(TCG_AREG0, | |
127 | offsetof(CPUState, sgr), "SGR"); | |
128 | cpu_dbr = tcg_global_mem_new_i32(TCG_AREG0, | |
129 | offsetof(CPUState, dbr), "DBR"); | |
130 | cpu_mach = tcg_global_mem_new_i32(TCG_AREG0, | |
131 | offsetof(CPUState, mach), "MACH"); | |
132 | cpu_macl = tcg_global_mem_new_i32(TCG_AREG0, | |
133 | offsetof(CPUState, macl), "MACL"); | |
134 | cpu_pr = tcg_global_mem_new_i32(TCG_AREG0, | |
135 | offsetof(CPUState, pr), "PR"); | |
136 | cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, | |
137 | offsetof(CPUState, fpscr), "FPSCR"); | |
138 | cpu_fpul = tcg_global_mem_new_i32(TCG_AREG0, | |
139 | offsetof(CPUState, fpul), "FPUL"); | |
140 | ||
141 | cpu_flags = tcg_global_mem_new_i32(TCG_AREG0, | |
142 | offsetof(CPUState, flags), "_flags_"); | |
143 | cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0, | |
144 | offsetof(CPUState, delayed_pc), | |
145 | "_delayed_pc_"); | |
1000822b | 146 | |
66ba317c AJ |
147 | for (i = 0; i < 32; i++) |
148 | cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0, | |
149 | offsetof(CPUState, fregs[i]), | |
150 | fregnames[i]); | |
151 | ||
988d7eaa | 152 | /* register helpers */ |
a7812ae4 | 153 | #define GEN_HELPER 2 |
988d7eaa AJ |
154 | #include "helper.h" |
155 | ||
2e70f6ef PB |
156 | done_init = 1; |
157 | } | |
158 | ||
fdf9b3e8 FB |
159 | void cpu_dump_state(CPUState * env, FILE * f, |
160 | int (*cpu_fprintf) (FILE * f, const char *fmt, ...), | |
161 | int flags) | |
162 | { | |
163 | int i; | |
eda9b09b FB |
164 | cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n", |
165 | env->pc, env->sr, env->pr, env->fpscr); | |
274a9e70 AJ |
166 | cpu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n", |
167 | env->spc, env->ssr, env->gbr, env->vbr); | |
168 | cpu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n", | |
169 | env->sgr, env->dbr, env->delayed_pc, env->fpul); | |
fdf9b3e8 FB |
170 | for (i = 0; i < 24; i += 4) { |
171 | cpu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n", | |
172 | i, env->gregs[i], i + 1, env->gregs[i + 1], | |
173 | i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]); | |
174 | } | |
175 | if (env->flags & DELAY_SLOT) { | |
176 | cpu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n", | |
177 | env->delayed_pc); | |
178 | } else if (env->flags & DELAY_SLOT_CONDITIONAL) { | |
179 | cpu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n", | |
180 | env->delayed_pc); | |
181 | } | |
182 | } | |
183 | ||
184 | void cpu_sh4_reset(CPUSH4State * env) | |
185 | { | |
9c2a9ea1 | 186 | #if defined(CONFIG_USER_ONLY) |
4c909d14 | 187 | env->sr = SR_FD; /* FD - kernel does lazy fpu context switch */ |
9c2a9ea1 | 188 | #else |
fdf9b3e8 | 189 | env->sr = 0x700000F0; /* MD, RB, BL, I3-I0 */ |
9c2a9ea1 | 190 | #endif |
fdf9b3e8 FB |
191 | env->vbr = 0; |
192 | env->pc = 0xA0000000; | |
ea6cf6be TS |
193 | #if defined(CONFIG_USER_ONLY) |
194 | env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ | |
b0b3de89 | 195 | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ |
ea6cf6be TS |
196 | #else |
197 | env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */ | |
b0b3de89 | 198 | set_float_rounding_mode(float_round_to_zero, &env->fp_status); |
ea6cf6be | 199 | #endif |
fdf9b3e8 FB |
200 | env->mmucr = 0; |
201 | } | |
202 | ||
0fd3ca30 | 203 | typedef struct { |
b55266b5 | 204 | const char *name; |
0fd3ca30 AJ |
205 | int id; |
206 | uint32_t pvr; | |
207 | uint32_t prr; | |
208 | uint32_t cvr; | |
209 | } sh4_def_t; | |
210 | ||
211 | static sh4_def_t sh4_defs[] = { | |
212 | { | |
213 | .name = "SH7750R", | |
214 | .id = SH_CPU_SH7750R, | |
215 | .pvr = 0x00050000, | |
216 | .prr = 0x00000100, | |
217 | .cvr = 0x00110000, | |
218 | }, { | |
219 | .name = "SH7751R", | |
220 | .id = SH_CPU_SH7751R, | |
221 | .pvr = 0x04050005, | |
222 | .prr = 0x00000113, | |
223 | .cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */ | |
224 | }, | |
225 | }; | |
226 | ||
b55266b5 | 227 | static const sh4_def_t *cpu_sh4_find_by_name(const char *name) |
0fd3ca30 AJ |
228 | { |
229 | int i; | |
230 | ||
231 | if (strcasecmp(name, "any") == 0) | |
232 | return &sh4_defs[0]; | |
233 | ||
234 | for (i = 0; i < sizeof(sh4_defs) / sizeof(*sh4_defs); i++) | |
235 | if (strcasecmp(name, sh4_defs[i].name) == 0) | |
236 | return &sh4_defs[i]; | |
237 | ||
238 | return NULL; | |
239 | } | |
240 | ||
241 | void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) | |
242 | { | |
243 | int i; | |
244 | ||
245 | for (i = 0; i < sizeof(sh4_defs) / sizeof(*sh4_defs); i++) | |
246 | (*cpu_fprintf)(f, "%s\n", sh4_defs[i].name); | |
247 | } | |
248 | ||
1ed1a787 | 249 | static void cpu_sh4_register(CPUSH4State *env, const sh4_def_t *def) |
0fd3ca30 AJ |
250 | { |
251 | env->pvr = def->pvr; | |
252 | env->prr = def->prr; | |
253 | env->cvr = def->cvr; | |
254 | env->id = def->id; | |
255 | } | |
256 | ||
aaed909a | 257 | CPUSH4State *cpu_sh4_init(const char *cpu_model) |
fdf9b3e8 FB |
258 | { |
259 | CPUSH4State *env; | |
0fd3ca30 | 260 | const sh4_def_t *def; |
fdf9b3e8 | 261 | |
0fd3ca30 AJ |
262 | def = cpu_sh4_find_by_name(cpu_model); |
263 | if (!def) | |
264 | return NULL; | |
fdf9b3e8 FB |
265 | env = qemu_mallocz(sizeof(CPUSH4State)); |
266 | if (!env) | |
267 | return NULL; | |
268 | cpu_exec_init(env); | |
2e70f6ef | 269 | sh4_translate_init(); |
7478757e | 270 | env->cpu_model_str = cpu_model; |
fdf9b3e8 | 271 | cpu_sh4_reset(env); |
0fd3ca30 | 272 | cpu_sh4_register(env, def); |
fdf9b3e8 FB |
273 | tlb_flush(env, 1); |
274 | return env; | |
275 | } | |
276 | ||
fdf9b3e8 FB |
277 | static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest) |
278 | { | |
279 | TranslationBlock *tb; | |
280 | tb = ctx->tb; | |
281 | ||
282 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && | |
283 | !ctx->singlestep_enabled) { | |
284 | /* Use a direct jump if in same page and singlestep not enabled */ | |
57fec1fe | 285 | tcg_gen_goto_tb(n); |
3a8a44c4 | 286 | tcg_gen_movi_i32(cpu_pc, dest); |
57fec1fe | 287 | tcg_gen_exit_tb((long) tb + n); |
fdf9b3e8 | 288 | } else { |
3a8a44c4 | 289 | tcg_gen_movi_i32(cpu_pc, dest); |
57fec1fe | 290 | if (ctx->singlestep_enabled) |
a7812ae4 | 291 | gen_helper_debug(); |
57fec1fe | 292 | tcg_gen_exit_tb(0); |
fdf9b3e8 | 293 | } |
fdf9b3e8 FB |
294 | } |
295 | ||
fdf9b3e8 FB |
296 | static void gen_jump(DisasContext * ctx) |
297 | { | |
298 | if (ctx->delayed_pc == (uint32_t) - 1) { | |
299 | /* Target is not statically known, it comes necessarily from a | |
300 | delayed jump as immediate jump are conditinal jumps */ | |
1000822b | 301 | tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc); |
fdf9b3e8 | 302 | if (ctx->singlestep_enabled) |
a7812ae4 | 303 | gen_helper_debug(); |
57fec1fe | 304 | tcg_gen_exit_tb(0); |
fdf9b3e8 FB |
305 | } else { |
306 | gen_goto_tb(ctx, 0, ctx->delayed_pc); | |
307 | } | |
308 | } | |
309 | ||
1000822b AJ |
310 | static inline void gen_branch_slot(uint32_t delayed_pc, int t) |
311 | { | |
c55497ec | 312 | TCGv sr; |
1000822b AJ |
313 | int label = gen_new_label(); |
314 | tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc); | |
a7812ae4 | 315 | sr = tcg_temp_new(); |
c55497ec AJ |
316 | tcg_gen_andi_i32(sr, cpu_sr, SR_T); |
317 | tcg_gen_brcondi_i32(TCG_COND_NE, sr, t ? SR_T : 0, label); | |
1000822b AJ |
318 | tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE); |
319 | gen_set_label(label); | |
320 | } | |
321 | ||
fdf9b3e8 FB |
322 | /* Immediate conditional jump (bt or bf) */ |
323 | static void gen_conditional_jump(DisasContext * ctx, | |
324 | target_ulong ift, target_ulong ifnott) | |
325 | { | |
326 | int l1; | |
c55497ec | 327 | TCGv sr; |
fdf9b3e8 FB |
328 | |
329 | l1 = gen_new_label(); | |
a7812ae4 | 330 | sr = tcg_temp_new(); |
c55497ec AJ |
331 | tcg_gen_andi_i32(sr, cpu_sr, SR_T); |
332 | tcg_gen_brcondi_i32(TCG_COND_EQ, sr, SR_T, l1); | |
fdf9b3e8 FB |
333 | gen_goto_tb(ctx, 0, ifnott); |
334 | gen_set_label(l1); | |
335 | gen_goto_tb(ctx, 1, ift); | |
336 | } | |
337 | ||
338 | /* Delayed conditional jump (bt or bf) */ | |
339 | static void gen_delayed_conditional_jump(DisasContext * ctx) | |
340 | { | |
341 | int l1; | |
c55497ec | 342 | TCGv ds; |
fdf9b3e8 FB |
343 | |
344 | l1 = gen_new_label(); | |
a7812ae4 | 345 | ds = tcg_temp_new(); |
c55497ec AJ |
346 | tcg_gen_andi_i32(ds, cpu_flags, DELAY_SLOT_TRUE); |
347 | tcg_gen_brcondi_i32(TCG_COND_EQ, ds, DELAY_SLOT_TRUE, l1); | |
823029f9 | 348 | gen_goto_tb(ctx, 1, ctx->pc + 2); |
fdf9b3e8 | 349 | gen_set_label(l1); |
1000822b | 350 | tcg_gen_andi_i32(cpu_flags, cpu_flags, ~DELAY_SLOT_TRUE); |
9c2a9ea1 | 351 | gen_jump(ctx); |
fdf9b3e8 FB |
352 | } |
353 | ||
a4625612 AJ |
354 | static inline void gen_set_t(void) |
355 | { | |
356 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T); | |
357 | } | |
358 | ||
359 | static inline void gen_clr_t(void) | |
360 | { | |
361 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); | |
362 | } | |
363 | ||
364 | static inline void gen_cmp(int cond, TCGv t0, TCGv t1) | |
365 | { | |
366 | int label1 = gen_new_label(); | |
367 | int label2 = gen_new_label(); | |
368 | tcg_gen_brcond_i32(cond, t1, t0, label1); | |
369 | gen_clr_t(); | |
370 | tcg_gen_br(label2); | |
371 | gen_set_label(label1); | |
372 | gen_set_t(); | |
373 | gen_set_label(label2); | |
374 | } | |
375 | ||
376 | static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm) | |
377 | { | |
378 | int label1 = gen_new_label(); | |
379 | int label2 = gen_new_label(); | |
380 | tcg_gen_brcondi_i32(cond, t0, imm, label1); | |
381 | gen_clr_t(); | |
382 | tcg_gen_br(label2); | |
383 | gen_set_label(label1); | |
384 | gen_set_t(); | |
385 | gen_set_label(label2); | |
386 | } | |
387 | ||
1000822b AJ |
388 | static inline void gen_store_flags(uint32_t flags) |
389 | { | |
390 | tcg_gen_andi_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE); | |
391 | tcg_gen_ori_i32(cpu_flags, cpu_flags, flags); | |
392 | } | |
393 | ||
69d6275b AJ |
394 | static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1) |
395 | { | |
a7812ae4 | 396 | TCGv tmp = tcg_temp_new(); |
69d6275b AJ |
397 | |
398 | p0 &= 0x1f; | |
399 | p1 &= 0x1f; | |
400 | ||
401 | tcg_gen_andi_i32(tmp, t1, (1 << p1)); | |
402 | tcg_gen_andi_i32(t0, t0, ~(1 << p0)); | |
403 | if (p0 < p1) | |
404 | tcg_gen_shri_i32(tmp, tmp, p1 - p0); | |
405 | else if (p0 > p1) | |
406 | tcg_gen_shli_i32(tmp, tmp, p0 - p1); | |
407 | tcg_gen_or_i32(t0, t0, tmp); | |
408 | ||
409 | tcg_temp_free(tmp); | |
410 | } | |
411 | ||
a7812ae4 | 412 | static inline void gen_load_fpr64(TCGv_i64 t, int reg) |
cc4ba6a9 | 413 | { |
66ba317c | 414 | tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]); |
cc4ba6a9 AJ |
415 | } |
416 | ||
a7812ae4 | 417 | static inline void gen_store_fpr64 (TCGv_i64 t, int reg) |
cc4ba6a9 | 418 | { |
a7812ae4 | 419 | TCGv_i32 tmp = tcg_temp_new_i32(); |
cc4ba6a9 | 420 | tcg_gen_trunc_i64_i32(tmp, t); |
66ba317c | 421 | tcg_gen_mov_i32(cpu_fregs[reg + 1], tmp); |
cc4ba6a9 AJ |
422 | tcg_gen_shri_i64(t, t, 32); |
423 | tcg_gen_trunc_i64_i32(tmp, t); | |
66ba317c | 424 | tcg_gen_mov_i32(cpu_fregs[reg], tmp); |
a7812ae4 | 425 | tcg_temp_free_i32(tmp); |
cc4ba6a9 AJ |
426 | } |
427 | ||
fdf9b3e8 FB |
428 | #define B3_0 (ctx->opcode & 0xf) |
429 | #define B6_4 ((ctx->opcode >> 4) & 0x7) | |
430 | #define B7_4 ((ctx->opcode >> 4) & 0xf) | |
431 | #define B7_0 (ctx->opcode & 0xff) | |
432 | #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff)) | |
433 | #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \ | |
434 | (ctx->opcode & 0xfff)) | |
435 | #define B11_8 ((ctx->opcode >> 8) & 0xf) | |
436 | #define B15_12 ((ctx->opcode >> 12) & 0xf) | |
437 | ||
438 | #define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \ | |
7efbe241 | 439 | (cpu_gregs[x + 16]) : (cpu_gregs[x])) |
fdf9b3e8 FB |
440 | |
441 | #define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \ | |
7efbe241 | 442 | ? (cpu_gregs[x + 16]) : (cpu_gregs[x])) |
fdf9b3e8 | 443 | |
eda9b09b | 444 | #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x)) |
f09111e0 | 445 | #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) |
eda9b09b | 446 | #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x)) |
ea6cf6be | 447 | #define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */ |
eda9b09b | 448 | |
fdf9b3e8 FB |
449 | #define CHECK_NOT_DELAY_SLOT \ |
450 | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \ | |
a7812ae4 | 451 | {gen_helper_raise_slot_illegal_instruction(); ctx->bstate = BS_EXCP; \ |
fdf9b3e8 FB |
452 | return;} |
453 | ||
fe25591e AJ |
454 | #define CHECK_PRIVILEGED \ |
455 | if (IS_USER(ctx)) { \ | |
a7812ae4 | 456 | gen_helper_raise_illegal_instruction(); \ |
fe25591e AJ |
457 | ctx->bstate = BS_EXCP; \ |
458 | return; \ | |
459 | } | |
460 | ||
b1d8e52e | 461 | static void _decode_opc(DisasContext * ctx) |
fdf9b3e8 FB |
462 | { |
463 | #if 0 | |
464 | fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode); | |
465 | #endif | |
466 | switch (ctx->opcode) { | |
467 | case 0x0019: /* div0u */ | |
3a8a44c4 | 468 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T)); |
fdf9b3e8 FB |
469 | return; |
470 | case 0x000b: /* rts */ | |
1000822b AJ |
471 | CHECK_NOT_DELAY_SLOT |
472 | tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr); | |
fdf9b3e8 FB |
473 | ctx->flags |= DELAY_SLOT; |
474 | ctx->delayed_pc = (uint32_t) - 1; | |
475 | return; | |
476 | case 0x0028: /* clrmac */ | |
3a8a44c4 AJ |
477 | tcg_gen_movi_i32(cpu_mach, 0); |
478 | tcg_gen_movi_i32(cpu_macl, 0); | |
fdf9b3e8 FB |
479 | return; |
480 | case 0x0048: /* clrs */ | |
3a8a44c4 | 481 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S); |
fdf9b3e8 FB |
482 | return; |
483 | case 0x0008: /* clrt */ | |
a4625612 | 484 | gen_clr_t(); |
fdf9b3e8 FB |
485 | return; |
486 | case 0x0038: /* ldtlb */ | |
fe25591e | 487 | CHECK_PRIVILEGED |
a7812ae4 | 488 | gen_helper_ldtlb(); |
fdf9b3e8 | 489 | return; |
c5e814b2 | 490 | case 0x002b: /* rte */ |
fe25591e | 491 | CHECK_PRIVILEGED |
1000822b AJ |
492 | CHECK_NOT_DELAY_SLOT |
493 | tcg_gen_mov_i32(cpu_sr, cpu_ssr); | |
494 | tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc); | |
fdf9b3e8 FB |
495 | ctx->flags |= DELAY_SLOT; |
496 | ctx->delayed_pc = (uint32_t) - 1; | |
497 | return; | |
498 | case 0x0058: /* sets */ | |
3a8a44c4 | 499 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S); |
fdf9b3e8 FB |
500 | return; |
501 | case 0x0018: /* sett */ | |
a4625612 | 502 | gen_set_t(); |
fdf9b3e8 | 503 | return; |
24988dc2 | 504 | case 0xfbfd: /* frchg */ |
6f06939b | 505 | tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR); |
823029f9 | 506 | ctx->bstate = BS_STOP; |
fdf9b3e8 | 507 | return; |
24988dc2 | 508 | case 0xf3fd: /* fschg */ |
6f06939b | 509 | tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ); |
823029f9 | 510 | ctx->bstate = BS_STOP; |
fdf9b3e8 FB |
511 | return; |
512 | case 0x0009: /* nop */ | |
513 | return; | |
514 | case 0x001b: /* sleep */ | |
fe25591e | 515 | CHECK_PRIVILEGED |
a7812ae4 | 516 | gen_helper_sleep(tcg_const_i32(ctx->pc + 2)); |
fdf9b3e8 FB |
517 | return; |
518 | } | |
519 | ||
520 | switch (ctx->opcode & 0xf000) { | |
521 | case 0x1000: /* mov.l Rm,@(disp,Rn) */ | |
c55497ec | 522 | { |
a7812ae4 | 523 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
524 | tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4); |
525 | tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); | |
526 | tcg_temp_free(addr); | |
527 | } | |
fdf9b3e8 FB |
528 | return; |
529 | case 0x5000: /* mov.l @(disp,Rm),Rn */ | |
c55497ec | 530 | { |
a7812ae4 | 531 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
532 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4); |
533 | tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); | |
534 | tcg_temp_free(addr); | |
535 | } | |
fdf9b3e8 | 536 | return; |
24988dc2 | 537 | case 0xe000: /* mov #imm,Rn */ |
7efbe241 | 538 | tcg_gen_movi_i32(REG(B11_8), B7_0s); |
fdf9b3e8 FB |
539 | return; |
540 | case 0x9000: /* mov.w @(disp,PC),Rn */ | |
c55497ec AJ |
541 | { |
542 | TCGv addr = tcg_const_i32(ctx->pc + 4 + B7_0 * 2); | |
543 | tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx); | |
544 | tcg_temp_free(addr); | |
545 | } | |
fdf9b3e8 FB |
546 | return; |
547 | case 0xd000: /* mov.l @(disp,PC),Rn */ | |
c55497ec AJ |
548 | { |
549 | TCGv addr = tcg_const_i32((ctx->pc + 4 + B7_0 * 4) & ~3); | |
550 | tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); | |
551 | tcg_temp_free(addr); | |
552 | } | |
fdf9b3e8 | 553 | return; |
24988dc2 | 554 | case 0x7000: /* add #imm,Rn */ |
7efbe241 | 555 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), B7_0s); |
fdf9b3e8 FB |
556 | return; |
557 | case 0xa000: /* bra disp */ | |
558 | CHECK_NOT_DELAY_SLOT | |
1000822b AJ |
559 | ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2; |
560 | tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc); | |
fdf9b3e8 FB |
561 | ctx->flags |= DELAY_SLOT; |
562 | return; | |
563 | case 0xb000: /* bsr disp */ | |
564 | CHECK_NOT_DELAY_SLOT | |
1000822b AJ |
565 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4); |
566 | ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2; | |
567 | tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc); | |
fdf9b3e8 FB |
568 | ctx->flags |= DELAY_SLOT; |
569 | return; | |
570 | } | |
571 | ||
572 | switch (ctx->opcode & 0xf00f) { | |
573 | case 0x6003: /* mov Rm,Rn */ | |
7efbe241 | 574 | tcg_gen_mov_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
575 | return; |
576 | case 0x2000: /* mov.b Rm,@Rn */ | |
7efbe241 | 577 | tcg_gen_qemu_st8(REG(B7_4), REG(B11_8), ctx->memidx); |
fdf9b3e8 FB |
578 | return; |
579 | case 0x2001: /* mov.w Rm,@Rn */ | |
7efbe241 | 580 | tcg_gen_qemu_st16(REG(B7_4), REG(B11_8), ctx->memidx); |
fdf9b3e8 FB |
581 | return; |
582 | case 0x2002: /* mov.l Rm,@Rn */ | |
7efbe241 | 583 | tcg_gen_qemu_st32(REG(B7_4), REG(B11_8), ctx->memidx); |
fdf9b3e8 FB |
584 | return; |
585 | case 0x6000: /* mov.b @Rm,Rn */ | |
7efbe241 | 586 | tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx); |
fdf9b3e8 FB |
587 | return; |
588 | case 0x6001: /* mov.w @Rm,Rn */ | |
7efbe241 | 589 | tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx); |
fdf9b3e8 FB |
590 | return; |
591 | case 0x6002: /* mov.l @Rm,Rn */ | |
7efbe241 | 592 | tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx); |
fdf9b3e8 FB |
593 | return; |
594 | case 0x2004: /* mov.b Rm,@-Rn */ | |
c55497ec | 595 | { |
a7812ae4 | 596 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
597 | tcg_gen_subi_i32(addr, REG(B11_8), 1); |
598 | tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); /* might cause re-execution */ | |
599 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); /* modify register status */ | |
600 | tcg_temp_free(addr); | |
601 | } | |
fdf9b3e8 FB |
602 | return; |
603 | case 0x2005: /* mov.w Rm,@-Rn */ | |
c55497ec | 604 | { |
a7812ae4 | 605 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
606 | tcg_gen_subi_i32(addr, REG(B11_8), 2); |
607 | tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx); | |
608 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 2); | |
609 | tcg_temp_free(addr); | |
610 | } | |
fdf9b3e8 FB |
611 | return; |
612 | case 0x2006: /* mov.l Rm,@-Rn */ | |
c55497ec | 613 | { |
a7812ae4 | 614 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
615 | tcg_gen_subi_i32(addr, REG(B11_8), 4); |
616 | tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); | |
617 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); | |
618 | } | |
fdf9b3e8 | 619 | return; |
eda9b09b | 620 | case 0x6004: /* mov.b @Rm+,Rn */ |
7efbe241 | 621 | tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx); |
24988dc2 | 622 | if ( B11_8 != B7_4 ) |
7efbe241 | 623 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1); |
fdf9b3e8 FB |
624 | return; |
625 | case 0x6005: /* mov.w @Rm+,Rn */ | |
7efbe241 | 626 | tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx); |
24988dc2 | 627 | if ( B11_8 != B7_4 ) |
7efbe241 | 628 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); |
fdf9b3e8 FB |
629 | return; |
630 | case 0x6006: /* mov.l @Rm+,Rn */ | |
7efbe241 | 631 | tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx); |
24988dc2 | 632 | if ( B11_8 != B7_4 ) |
7efbe241 | 633 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); |
fdf9b3e8 FB |
634 | return; |
635 | case 0x0004: /* mov.b Rm,@(R0,Rn) */ | |
c55497ec | 636 | { |
a7812ae4 | 637 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
638 | tcg_gen_add_i32(addr, REG(B11_8), REG(0)); |
639 | tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); | |
640 | tcg_temp_free(addr); | |
641 | } | |
fdf9b3e8 FB |
642 | return; |
643 | case 0x0005: /* mov.w Rm,@(R0,Rn) */ | |
c55497ec | 644 | { |
a7812ae4 | 645 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
646 | tcg_gen_add_i32(addr, REG(B11_8), REG(0)); |
647 | tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx); | |
648 | tcg_temp_free(addr); | |
649 | } | |
fdf9b3e8 FB |
650 | return; |
651 | case 0x0006: /* mov.l Rm,@(R0,Rn) */ | |
c55497ec | 652 | { |
a7812ae4 | 653 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
654 | tcg_gen_add_i32(addr, REG(B11_8), REG(0)); |
655 | tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); | |
656 | tcg_temp_free(addr); | |
657 | } | |
fdf9b3e8 FB |
658 | return; |
659 | case 0x000c: /* mov.b @(R0,Rm),Rn */ | |
c55497ec | 660 | { |
a7812ae4 | 661 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
662 | tcg_gen_add_i32(addr, REG(B7_4), REG(0)); |
663 | tcg_gen_qemu_ld8s(REG(B11_8), addr, ctx->memidx); | |
664 | tcg_temp_free(addr); | |
665 | } | |
fdf9b3e8 FB |
666 | return; |
667 | case 0x000d: /* mov.w @(R0,Rm),Rn */ | |
c55497ec | 668 | { |
a7812ae4 | 669 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
670 | tcg_gen_add_i32(addr, REG(B7_4), REG(0)); |
671 | tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx); | |
672 | tcg_temp_free(addr); | |
673 | } | |
fdf9b3e8 FB |
674 | return; |
675 | case 0x000e: /* mov.l @(R0,Rm),Rn */ | |
c55497ec | 676 | { |
a7812ae4 | 677 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
678 | tcg_gen_add_i32(addr, REG(B7_4), REG(0)); |
679 | tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); | |
680 | tcg_temp_free(addr); | |
681 | } | |
fdf9b3e8 FB |
682 | return; |
683 | case 0x6008: /* swap.b Rm,Rn */ | |
c55497ec | 684 | { |
c69e3264 | 685 | TCGv highw, high, low; |
a7812ae4 | 686 | highw = tcg_temp_new(); |
c69e3264 | 687 | tcg_gen_andi_i32(highw, REG(B7_4), 0xffff0000); |
a7812ae4 | 688 | high = tcg_temp_new(); |
c55497ec AJ |
689 | tcg_gen_ext8u_i32(high, REG(B7_4)); |
690 | tcg_gen_shli_i32(high, high, 8); | |
a7812ae4 | 691 | low = tcg_temp_new(); |
c55497ec AJ |
692 | tcg_gen_shri_i32(low, REG(B7_4), 8); |
693 | tcg_gen_ext8u_i32(low, low); | |
694 | tcg_gen_or_i32(REG(B11_8), high, low); | |
c69e3264 | 695 | tcg_gen_or_i32(REG(B11_8), REG(B11_8), highw); |
c55497ec AJ |
696 | tcg_temp_free(low); |
697 | tcg_temp_free(high); | |
698 | } | |
fdf9b3e8 FB |
699 | return; |
700 | case 0x6009: /* swap.w Rm,Rn */ | |
c55497ec AJ |
701 | { |
702 | TCGv high, low; | |
a7812ae4 | 703 | high = tcg_temp_new(); |
c55497ec AJ |
704 | tcg_gen_ext16u_i32(high, REG(B7_4)); |
705 | tcg_gen_shli_i32(high, high, 16); | |
a7812ae4 | 706 | low = tcg_temp_new(); |
c55497ec AJ |
707 | tcg_gen_shri_i32(low, REG(B7_4), 16); |
708 | tcg_gen_ext16u_i32(low, low); | |
709 | tcg_gen_or_i32(REG(B11_8), high, low); | |
710 | tcg_temp_free(low); | |
711 | tcg_temp_free(high); | |
712 | } | |
fdf9b3e8 FB |
713 | return; |
714 | case 0x200d: /* xtrct Rm,Rn */ | |
c55497ec AJ |
715 | { |
716 | TCGv high, low; | |
a7812ae4 | 717 | high = tcg_temp_new(); |
c55497ec AJ |
718 | tcg_gen_ext16u_i32(high, REG(B7_4)); |
719 | tcg_gen_shli_i32(high, high, 16); | |
a7812ae4 | 720 | low = tcg_temp_new(); |
c55497ec AJ |
721 | tcg_gen_shri_i32(low, REG(B11_8), 16); |
722 | tcg_gen_ext16u_i32(low, low); | |
723 | tcg_gen_or_i32(REG(B11_8), high, low); | |
724 | tcg_temp_free(low); | |
725 | tcg_temp_free(high); | |
726 | } | |
fdf9b3e8 FB |
727 | return; |
728 | case 0x300c: /* add Rm,Rn */ | |
7efbe241 | 729 | tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
730 | return; |
731 | case 0x300e: /* addc Rm,Rn */ | |
a7812ae4 | 732 | gen_helper_addc(REG(B11_8), REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
733 | return; |
734 | case 0x300f: /* addv Rm,Rn */ | |
a7812ae4 | 735 | gen_helper_addv(REG(B11_8), REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
736 | return; |
737 | case 0x2009: /* and Rm,Rn */ | |
7efbe241 | 738 | tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
739 | return; |
740 | case 0x3000: /* cmp/eq Rm,Rn */ | |
7efbe241 | 741 | gen_cmp(TCG_COND_EQ, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
742 | return; |
743 | case 0x3003: /* cmp/ge Rm,Rn */ | |
7efbe241 | 744 | gen_cmp(TCG_COND_GE, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
745 | return; |
746 | case 0x3007: /* cmp/gt Rm,Rn */ | |
7efbe241 | 747 | gen_cmp(TCG_COND_GT, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
748 | return; |
749 | case 0x3006: /* cmp/hi Rm,Rn */ | |
7efbe241 | 750 | gen_cmp(TCG_COND_GTU, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
751 | return; |
752 | case 0x3002: /* cmp/hs Rm,Rn */ | |
7efbe241 | 753 | gen_cmp(TCG_COND_GEU, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
754 | return; |
755 | case 0x200c: /* cmp/str Rm,Rn */ | |
69d6275b AJ |
756 | { |
757 | int label1 = gen_new_label(); | |
758 | int label2 = gen_new_label(); | |
c55497ec AJ |
759 | TCGv cmp1 = tcg_temp_local_new(TCG_TYPE_I32); |
760 | TCGv cmp2 = tcg_temp_local_new(TCG_TYPE_I32); | |
761 | tcg_gen_xor_i32(cmp1, REG(B7_4), REG(B11_8)); | |
762 | tcg_gen_andi_i32(cmp2, cmp1, 0xff000000); | |
763 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1); | |
764 | tcg_gen_andi_i32(cmp2, cmp1, 0x00ff0000); | |
765 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1); | |
766 | tcg_gen_andi_i32(cmp2, cmp1, 0x0000ff00); | |
767 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1); | |
768 | tcg_gen_andi_i32(cmp2, cmp1, 0x000000ff); | |
769 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1); | |
69d6275b AJ |
770 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); |
771 | tcg_gen_br(label2); | |
772 | gen_set_label(label1); | |
773 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T); | |
774 | gen_set_label(label2); | |
c55497ec AJ |
775 | tcg_temp_free(cmp2); |
776 | tcg_temp_free(cmp1); | |
69d6275b | 777 | } |
fdf9b3e8 FB |
778 | return; |
779 | case 0x2007: /* div0s Rm,Rn */ | |
c55497ec AJ |
780 | { |
781 | gen_copy_bit_i32(cpu_sr, 8, REG(B11_8), 31); /* SR_Q */ | |
782 | gen_copy_bit_i32(cpu_sr, 9, REG(B7_4), 31); /* SR_M */ | |
a7812ae4 | 783 | TCGv val = tcg_temp_new(); |
c55497ec AJ |
784 | tcg_gen_xor_i32(val, REG(B7_4), REG(B11_8)); |
785 | gen_copy_bit_i32(cpu_sr, 0, val, 31); /* SR_T */ | |
786 | tcg_temp_free(val); | |
787 | } | |
fdf9b3e8 FB |
788 | return; |
789 | case 0x3004: /* div1 Rm,Rn */ | |
a7812ae4 | 790 | gen_helper_div1(REG(B11_8), REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
791 | return; |
792 | case 0x300d: /* dmuls.l Rm,Rn */ | |
6f06939b | 793 | { |
a7812ae4 PB |
794 | TCGv_i64 tmp1 = tcg_temp_new_i64(); |
795 | TCGv_i64 tmp2 = tcg_temp_new_i64(); | |
6f06939b | 796 | |
7efbe241 AJ |
797 | tcg_gen_ext_i32_i64(tmp1, REG(B7_4)); |
798 | tcg_gen_ext_i32_i64(tmp2, REG(B11_8)); | |
6f06939b AJ |
799 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
800 | tcg_gen_trunc_i64_i32(cpu_macl, tmp1); | |
801 | tcg_gen_shri_i64(tmp1, tmp1, 32); | |
802 | tcg_gen_trunc_i64_i32(cpu_mach, tmp1); | |
803 | ||
a7812ae4 PB |
804 | tcg_temp_free_i64(tmp2); |
805 | tcg_temp_free_i64(tmp1); | |
6f06939b | 806 | } |
fdf9b3e8 FB |
807 | return; |
808 | case 0x3005: /* dmulu.l Rm,Rn */ | |
6f06939b | 809 | { |
a7812ae4 PB |
810 | TCGv_i64 tmp1 = tcg_temp_new_i64(); |
811 | TCGv_i64 tmp2 = tcg_temp_new_i64(); | |
6f06939b | 812 | |
7efbe241 AJ |
813 | tcg_gen_extu_i32_i64(tmp1, REG(B7_4)); |
814 | tcg_gen_extu_i32_i64(tmp2, REG(B11_8)); | |
6f06939b AJ |
815 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
816 | tcg_gen_trunc_i64_i32(cpu_macl, tmp1); | |
817 | tcg_gen_shri_i64(tmp1, tmp1, 32); | |
818 | tcg_gen_trunc_i64_i32(cpu_mach, tmp1); | |
819 | ||
a7812ae4 PB |
820 | tcg_temp_free_i64(tmp2); |
821 | tcg_temp_free_i64(tmp1); | |
6f06939b | 822 | } |
fdf9b3e8 FB |
823 | return; |
824 | case 0x600e: /* exts.b Rm,Rn */ | |
7efbe241 | 825 | tcg_gen_ext8s_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
826 | return; |
827 | case 0x600f: /* exts.w Rm,Rn */ | |
7efbe241 | 828 | tcg_gen_ext16s_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
829 | return; |
830 | case 0x600c: /* extu.b Rm,Rn */ | |
7efbe241 | 831 | tcg_gen_ext8u_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
832 | return; |
833 | case 0x600d: /* extu.w Rm,Rn */ | |
7efbe241 | 834 | tcg_gen_ext16u_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 | 835 | return; |
24988dc2 | 836 | case 0x000f: /* mac.l @Rm+,@Rn+ */ |
c55497ec AJ |
837 | { |
838 | TCGv arg0, arg1; | |
a7812ae4 | 839 | arg0 = tcg_temp_new(); |
c55497ec | 840 | tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx); |
a7812ae4 | 841 | arg1 = tcg_temp_new(); |
c55497ec | 842 | tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx); |
a7812ae4 | 843 | gen_helper_macl(arg0, arg1); |
c55497ec AJ |
844 | tcg_temp_free(arg1); |
845 | tcg_temp_free(arg0); | |
846 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); | |
847 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); | |
848 | } | |
fdf9b3e8 FB |
849 | return; |
850 | case 0x400f: /* mac.w @Rm+,@Rn+ */ | |
c55497ec AJ |
851 | { |
852 | TCGv arg0, arg1; | |
a7812ae4 | 853 | arg0 = tcg_temp_new(); |
c55497ec | 854 | tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx); |
a7812ae4 | 855 | arg1 = tcg_temp_new(); |
c55497ec | 856 | tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx); |
a7812ae4 | 857 | gen_helper_macw(arg0, arg1); |
c55497ec AJ |
858 | tcg_temp_free(arg1); |
859 | tcg_temp_free(arg0); | |
860 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2); | |
861 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); | |
862 | } | |
fdf9b3e8 FB |
863 | return; |
864 | case 0x0007: /* mul.l Rm,Rn */ | |
7efbe241 | 865 | tcg_gen_mul_i32(cpu_macl, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
866 | return; |
867 | case 0x200f: /* muls.w Rm,Rn */ | |
c55497ec AJ |
868 | { |
869 | TCGv arg0, arg1; | |
a7812ae4 | 870 | arg0 = tcg_temp_new(); |
c55497ec | 871 | tcg_gen_ext16s_i32(arg0, REG(B7_4)); |
a7812ae4 | 872 | arg1 = tcg_temp_new(); |
c55497ec AJ |
873 | tcg_gen_ext16s_i32(arg1, REG(B11_8)); |
874 | tcg_gen_mul_i32(cpu_macl, arg0, arg1); | |
875 | tcg_temp_free(arg1); | |
876 | tcg_temp_free(arg0); | |
877 | } | |
fdf9b3e8 FB |
878 | return; |
879 | case 0x200e: /* mulu.w Rm,Rn */ | |
c55497ec AJ |
880 | { |
881 | TCGv arg0, arg1; | |
a7812ae4 | 882 | arg0 = tcg_temp_new(); |
c55497ec | 883 | tcg_gen_ext16u_i32(arg0, REG(B7_4)); |
a7812ae4 | 884 | arg1 = tcg_temp_new(); |
c55497ec AJ |
885 | tcg_gen_ext16u_i32(arg1, REG(B11_8)); |
886 | tcg_gen_mul_i32(cpu_macl, arg0, arg1); | |
887 | tcg_temp_free(arg1); | |
888 | tcg_temp_free(arg0); | |
889 | } | |
fdf9b3e8 FB |
890 | return; |
891 | case 0x600b: /* neg Rm,Rn */ | |
7efbe241 | 892 | tcg_gen_neg_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
893 | return; |
894 | case 0x600a: /* negc Rm,Rn */ | |
a7812ae4 | 895 | gen_helper_negc(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
896 | return; |
897 | case 0x6007: /* not Rm,Rn */ | |
7efbe241 | 898 | tcg_gen_not_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
899 | return; |
900 | case 0x200b: /* or Rm,Rn */ | |
7efbe241 | 901 | tcg_gen_or_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
902 | return; |
903 | case 0x400c: /* shad Rm,Rn */ | |
69d6275b AJ |
904 | { |
905 | int label1 = gen_new_label(); | |
906 | int label2 = gen_new_label(); | |
907 | int label3 = gen_new_label(); | |
908 | int label4 = gen_new_label(); | |
c55497ec | 909 | TCGv shift = tcg_temp_local_new(TCG_TYPE_I32); |
7efbe241 | 910 | tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1); |
69d6275b | 911 | /* Rm positive, shift to the left */ |
c55497ec AJ |
912 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); |
913 | tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift); | |
69d6275b AJ |
914 | tcg_gen_br(label4); |
915 | /* Rm negative, shift to the right */ | |
916 | gen_set_label(label1); | |
c55497ec AJ |
917 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); |
918 | tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2); | |
919 | tcg_gen_not_i32(shift, REG(B7_4)); | |
920 | tcg_gen_andi_i32(shift, shift, 0x1f); | |
921 | tcg_gen_addi_i32(shift, shift, 1); | |
922 | tcg_gen_sar_i32(REG(B11_8), REG(B11_8), shift); | |
69d6275b AJ |
923 | tcg_gen_br(label4); |
924 | /* Rm = -32 */ | |
925 | gen_set_label(label2); | |
7efbe241 AJ |
926 | tcg_gen_brcondi_i32(TCG_COND_LT, REG(B11_8), 0, label3); |
927 | tcg_gen_movi_i32(REG(B11_8), 0); | |
69d6275b AJ |
928 | tcg_gen_br(label4); |
929 | gen_set_label(label3); | |
7efbe241 | 930 | tcg_gen_movi_i32(REG(B11_8), 0xffffffff); |
69d6275b | 931 | gen_set_label(label4); |
c55497ec | 932 | tcg_temp_free(shift); |
69d6275b | 933 | } |
fdf9b3e8 FB |
934 | return; |
935 | case 0x400d: /* shld Rm,Rn */ | |
69d6275b AJ |
936 | { |
937 | int label1 = gen_new_label(); | |
938 | int label2 = gen_new_label(); | |
939 | int label3 = gen_new_label(); | |
c55497ec | 940 | TCGv shift = tcg_temp_local_new(TCG_TYPE_I32); |
7efbe241 | 941 | tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1); |
69d6275b | 942 | /* Rm positive, shift to the left */ |
c55497ec AJ |
943 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); |
944 | tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift); | |
69d6275b AJ |
945 | tcg_gen_br(label3); |
946 | /* Rm negative, shift to the right */ | |
947 | gen_set_label(label1); | |
c55497ec AJ |
948 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); |
949 | tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2); | |
950 | tcg_gen_not_i32(shift, REG(B7_4)); | |
951 | tcg_gen_andi_i32(shift, shift, 0x1f); | |
952 | tcg_gen_addi_i32(shift, shift, 1); | |
953 | tcg_gen_shr_i32(REG(B11_8), REG(B11_8), shift); | |
69d6275b AJ |
954 | tcg_gen_br(label3); |
955 | /* Rm = -32 */ | |
956 | gen_set_label(label2); | |
7efbe241 | 957 | tcg_gen_movi_i32(REG(B11_8), 0); |
69d6275b | 958 | gen_set_label(label3); |
c55497ec | 959 | tcg_temp_free(shift); |
69d6275b | 960 | } |
fdf9b3e8 FB |
961 | return; |
962 | case 0x3008: /* sub Rm,Rn */ | |
7efbe241 | 963 | tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
964 | return; |
965 | case 0x300a: /* subc Rm,Rn */ | |
a7812ae4 | 966 | gen_helper_subc(REG(B11_8), REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
967 | return; |
968 | case 0x300b: /* subv Rm,Rn */ | |
a7812ae4 | 969 | gen_helper_subv(REG(B11_8), REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
970 | return; |
971 | case 0x2008: /* tst Rm,Rn */ | |
c55497ec | 972 | { |
a7812ae4 | 973 | TCGv val = tcg_temp_new(); |
c55497ec AJ |
974 | tcg_gen_and_i32(val, REG(B7_4), REG(B11_8)); |
975 | gen_cmp_imm(TCG_COND_EQ, val, 0); | |
976 | tcg_temp_free(val); | |
977 | } | |
fdf9b3e8 FB |
978 | return; |
979 | case 0x200a: /* xor Rm,Rn */ | |
7efbe241 | 980 | tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
fdf9b3e8 | 981 | return; |
e67888a7 | 982 | case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */ |
022a22c7 | 983 | if (ctx->fpscr & FPSCR_SZ) { |
a7812ae4 | 984 | TCGv_i64 fp = tcg_temp_new_i64(); |
cc4ba6a9 AJ |
985 | gen_load_fpr64(fp, XREG(B7_4)); |
986 | gen_store_fpr64(fp, XREG(B11_8)); | |
a7812ae4 | 987 | tcg_temp_free_i64(fp); |
eda9b09b | 988 | } else { |
66ba317c | 989 | tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
eda9b09b FB |
990 | } |
991 | return; | |
e67888a7 | 992 | case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ |
022a22c7 | 993 | if (ctx->fpscr & FPSCR_SZ) { |
11bb09f1 AJ |
994 | TCGv addr_hi = tcg_temp_new(); |
995 | int fr = XREG(B7_4); | |
996 | tcg_gen_addi_i32(addr_hi, REG(B11_8), 4); | |
997 | tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx); | |
998 | tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx); | |
999 | tcg_temp_free(addr_hi); | |
eda9b09b | 1000 | } else { |
66ba317c | 1001 | tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx); |
eda9b09b FB |
1002 | } |
1003 | return; | |
e67888a7 | 1004 | case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ |
022a22c7 | 1005 | if (ctx->fpscr & FPSCR_SZ) { |
11bb09f1 AJ |
1006 | TCGv addr_hi = tcg_temp_new(); |
1007 | int fr = XREG(B11_8); | |
1008 | tcg_gen_addi_i32(addr_hi, REG(B7_4), 4); | |
1009 | tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx); | |
1010 | tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx); | |
1011 | tcg_temp_free(addr_hi); | |
eda9b09b | 1012 | } else { |
66ba317c | 1013 | tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx); |
eda9b09b FB |
1014 | } |
1015 | return; | |
e67888a7 | 1016 | case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ |
022a22c7 | 1017 | if (ctx->fpscr & FPSCR_SZ) { |
11bb09f1 AJ |
1018 | TCGv addr_hi = tcg_temp_new(); |
1019 | int fr = XREG(B11_8); | |
1020 | tcg_gen_addi_i32(addr_hi, REG(B7_4), 4); | |
1021 | tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx); | |
1022 | tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx); | |
1023 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8); | |
1024 | tcg_temp_free(addr_hi); | |
eda9b09b | 1025 | } else { |
66ba317c | 1026 | tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx); |
cc4ba6a9 | 1027 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); |
eda9b09b FB |
1028 | } |
1029 | return; | |
e67888a7 | 1030 | case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ |
022a22c7 | 1031 | if (ctx->fpscr & FPSCR_SZ) { |
11bb09f1 AJ |
1032 | TCGv addr = tcg_temp_new_i32(); |
1033 | int fr = XREG(B7_4); | |
1034 | tcg_gen_subi_i32(addr, REG(B11_8), 4); | |
1035 | tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx); | |
cc4ba6a9 | 1036 | tcg_gen_subi_i32(addr, REG(B11_8), 8); |
11bb09f1 AJ |
1037 | tcg_gen_qemu_st32(cpu_fregs[fr ], addr, ctx->memidx); |
1038 | tcg_gen_mov_i32(REG(B11_8), addr); | |
cc4ba6a9 | 1039 | tcg_temp_free(addr); |
eda9b09b | 1040 | } else { |
a7812ae4 | 1041 | TCGv addr; |
a7812ae4 | 1042 | addr = tcg_temp_new_i32(); |
cc4ba6a9 | 1043 | tcg_gen_subi_i32(addr, REG(B11_8), 4); |
66ba317c | 1044 | tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx); |
cc4ba6a9 | 1045 | tcg_temp_free(addr); |
7efbe241 | 1046 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); |
eda9b09b FB |
1047 | } |
1048 | return; | |
e67888a7 | 1049 | case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ |
cc4ba6a9 | 1050 | { |
a7812ae4 | 1051 | TCGv addr = tcg_temp_new_i32(); |
cc4ba6a9 AJ |
1052 | tcg_gen_add_i32(addr, REG(B7_4), REG(0)); |
1053 | if (ctx->fpscr & FPSCR_SZ) { | |
11bb09f1 AJ |
1054 | int fr = XREG(B11_8); |
1055 | tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx); | |
1056 | tcg_gen_addi_i32(addr, addr, 4); | |
1057 | tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx); | |
cc4ba6a9 | 1058 | } else { |
66ba317c | 1059 | tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx); |
cc4ba6a9 AJ |
1060 | } |
1061 | tcg_temp_free(addr); | |
eda9b09b FB |
1062 | } |
1063 | return; | |
e67888a7 | 1064 | case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */ |
cc4ba6a9 | 1065 | { |
a7812ae4 | 1066 | TCGv addr = tcg_temp_new(); |
cc4ba6a9 AJ |
1067 | tcg_gen_add_i32(addr, REG(B11_8), REG(0)); |
1068 | if (ctx->fpscr & FPSCR_SZ) { | |
11bb09f1 AJ |
1069 | int fr = XREG(B7_4); |
1070 | tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx); | |
1071 | tcg_gen_addi_i32(addr, addr, 4); | |
1072 | tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx); | |
cc4ba6a9 | 1073 | } else { |
66ba317c | 1074 | tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx); |
cc4ba6a9 AJ |
1075 | } |
1076 | tcg_temp_free(addr); | |
eda9b09b FB |
1077 | } |
1078 | return; | |
e67888a7 TS |
1079 | case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
1080 | case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ | |
1081 | case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ | |
1082 | case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ | |
1083 | case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ | |
1084 | case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ | |
cc4ba6a9 | 1085 | { |
cc4ba6a9 | 1086 | if (ctx->fpscr & FPSCR_PR) { |
a7812ae4 PB |
1087 | TCGv_i64 fp0, fp1; |
1088 | ||
cc4ba6a9 AJ |
1089 | if (ctx->opcode & 0x0110) |
1090 | break; /* illegal instruction */ | |
a7812ae4 PB |
1091 | fp0 = tcg_temp_new_i64(); |
1092 | fp1 = tcg_temp_new_i64(); | |
cc4ba6a9 AJ |
1093 | gen_load_fpr64(fp0, DREG(B11_8)); |
1094 | gen_load_fpr64(fp1, DREG(B7_4)); | |
a7812ae4 PB |
1095 | switch (ctx->opcode & 0xf00f) { |
1096 | case 0xf000: /* fadd Rm,Rn */ | |
1097 | gen_helper_fadd_DT(fp0, fp0, fp1); | |
1098 | break; | |
1099 | case 0xf001: /* fsub Rm,Rn */ | |
1100 | gen_helper_fsub_DT(fp0, fp0, fp1); | |
1101 | break; | |
1102 | case 0xf002: /* fmul Rm,Rn */ | |
1103 | gen_helper_fmul_DT(fp0, fp0, fp1); | |
1104 | break; | |
1105 | case 0xf003: /* fdiv Rm,Rn */ | |
1106 | gen_helper_fdiv_DT(fp0, fp0, fp1); | |
1107 | break; | |
1108 | case 0xf004: /* fcmp/eq Rm,Rn */ | |
1109 | gen_helper_fcmp_eq_DT(fp0, fp1); | |
1110 | return; | |
1111 | case 0xf005: /* fcmp/gt Rm,Rn */ | |
1112 | gen_helper_fcmp_gt_DT(fp0, fp1); | |
1113 | return; | |
1114 | } | |
1115 | gen_store_fpr64(fp0, DREG(B11_8)); | |
1116 | tcg_temp_free_i64(fp0); | |
1117 | tcg_temp_free_i64(fp1); | |
1118 | } else { | |
a7812ae4 PB |
1119 | switch (ctx->opcode & 0xf00f) { |
1120 | case 0xf000: /* fadd Rm,Rn */ | |
66ba317c | 1121 | gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
a7812ae4 PB |
1122 | break; |
1123 | case 0xf001: /* fsub Rm,Rn */ | |
66ba317c | 1124 | gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
a7812ae4 PB |
1125 | break; |
1126 | case 0xf002: /* fmul Rm,Rn */ | |
66ba317c | 1127 | gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
a7812ae4 PB |
1128 | break; |
1129 | case 0xf003: /* fdiv Rm,Rn */ | |
66ba317c | 1130 | gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
a7812ae4 PB |
1131 | break; |
1132 | case 0xf004: /* fcmp/eq Rm,Rn */ | |
66ba317c | 1133 | gen_helper_fcmp_eq_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
a7812ae4 PB |
1134 | return; |
1135 | case 0xf005: /* fcmp/gt Rm,Rn */ | |
66ba317c | 1136 | gen_helper_fcmp_gt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
a7812ae4 PB |
1137 | return; |
1138 | } | |
cc4ba6a9 | 1139 | } |
ea6cf6be TS |
1140 | } |
1141 | return; | |
fdf9b3e8 FB |
1142 | } |
1143 | ||
1144 | switch (ctx->opcode & 0xff00) { | |
1145 | case 0xc900: /* and #imm,R0 */ | |
7efbe241 | 1146 | tcg_gen_andi_i32(REG(0), REG(0), B7_0); |
fdf9b3e8 | 1147 | return; |
24988dc2 | 1148 | case 0xcd00: /* and.b #imm,@(R0,GBR) */ |
c55497ec AJ |
1149 | { |
1150 | TCGv addr, val; | |
a7812ae4 | 1151 | addr = tcg_temp_new(); |
c55497ec | 1152 | tcg_gen_add_i32(addr, REG(0), cpu_gbr); |
a7812ae4 | 1153 | val = tcg_temp_new(); |
c55497ec AJ |
1154 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
1155 | tcg_gen_andi_i32(val, val, B7_0); | |
1156 | tcg_gen_qemu_st8(val, addr, ctx->memidx); | |
1157 | tcg_temp_free(val); | |
1158 | tcg_temp_free(addr); | |
1159 | } | |
fdf9b3e8 FB |
1160 | return; |
1161 | case 0x8b00: /* bf label */ | |
1162 | CHECK_NOT_DELAY_SLOT | |
1163 | gen_conditional_jump(ctx, ctx->pc + 2, | |
1164 | ctx->pc + 4 + B7_0s * 2); | |
823029f9 | 1165 | ctx->bstate = BS_BRANCH; |
fdf9b3e8 FB |
1166 | return; |
1167 | case 0x8f00: /* bf/s label */ | |
1168 | CHECK_NOT_DELAY_SLOT | |
1000822b | 1169 | gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 0); |
fdf9b3e8 FB |
1170 | ctx->flags |= DELAY_SLOT_CONDITIONAL; |
1171 | return; | |
1172 | case 0x8900: /* bt label */ | |
1173 | CHECK_NOT_DELAY_SLOT | |
1174 | gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2, | |
1175 | ctx->pc + 2); | |
823029f9 | 1176 | ctx->bstate = BS_BRANCH; |
fdf9b3e8 FB |
1177 | return; |
1178 | case 0x8d00: /* bt/s label */ | |
1179 | CHECK_NOT_DELAY_SLOT | |
1000822b | 1180 | gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 1); |
fdf9b3e8 FB |
1181 | ctx->flags |= DELAY_SLOT_CONDITIONAL; |
1182 | return; | |
1183 | case 0x8800: /* cmp/eq #imm,R0 */ | |
7efbe241 | 1184 | gen_cmp_imm(TCG_COND_EQ, REG(0), B7_0s); |
fdf9b3e8 FB |
1185 | return; |
1186 | case 0xc400: /* mov.b @(disp,GBR),R0 */ | |
c55497ec | 1187 | { |
a7812ae4 | 1188 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1189 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0); |
1190 | tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx); | |
1191 | tcg_temp_free(addr); | |
1192 | } | |
fdf9b3e8 FB |
1193 | return; |
1194 | case 0xc500: /* mov.w @(disp,GBR),R0 */ | |
c55497ec | 1195 | { |
a7812ae4 | 1196 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1197 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2); |
1198 | tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx); | |
1199 | tcg_temp_free(addr); | |
1200 | } | |
fdf9b3e8 FB |
1201 | return; |
1202 | case 0xc600: /* mov.l @(disp,GBR),R0 */ | |
c55497ec | 1203 | { |
a7812ae4 | 1204 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1205 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4); |
1206 | tcg_gen_qemu_ld32s(REG(0), addr, ctx->memidx); | |
1207 | tcg_temp_free(addr); | |
1208 | } | |
fdf9b3e8 FB |
1209 | return; |
1210 | case 0xc000: /* mov.b R0,@(disp,GBR) */ | |
c55497ec | 1211 | { |
a7812ae4 | 1212 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1213 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0); |
1214 | tcg_gen_qemu_st8(REG(0), addr, ctx->memidx); | |
1215 | tcg_temp_free(addr); | |
1216 | } | |
fdf9b3e8 FB |
1217 | return; |
1218 | case 0xc100: /* mov.w R0,@(disp,GBR) */ | |
c55497ec | 1219 | { |
a7812ae4 | 1220 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1221 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2); |
1222 | tcg_gen_qemu_st16(REG(0), addr, ctx->memidx); | |
1223 | tcg_temp_free(addr); | |
1224 | } | |
fdf9b3e8 FB |
1225 | return; |
1226 | case 0xc200: /* mov.l R0,@(disp,GBR) */ | |
c55497ec | 1227 | { |
a7812ae4 | 1228 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1229 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4); |
1230 | tcg_gen_qemu_st32(REG(0), addr, ctx->memidx); | |
1231 | tcg_temp_free(addr); | |
1232 | } | |
fdf9b3e8 FB |
1233 | return; |
1234 | case 0x8000: /* mov.b R0,@(disp,Rn) */ | |
c55497ec | 1235 | { |
a7812ae4 | 1236 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1237 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0); |
1238 | tcg_gen_qemu_st8(REG(0), addr, ctx->memidx); | |
1239 | tcg_temp_free(addr); | |
1240 | } | |
fdf9b3e8 FB |
1241 | return; |
1242 | case 0x8100: /* mov.w R0,@(disp,Rn) */ | |
c55497ec | 1243 | { |
a7812ae4 | 1244 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1245 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); |
1246 | tcg_gen_qemu_st16(REG(0), addr, ctx->memidx); | |
1247 | tcg_temp_free(addr); | |
1248 | } | |
fdf9b3e8 FB |
1249 | return; |
1250 | case 0x8400: /* mov.b @(disp,Rn),R0 */ | |
c55497ec | 1251 | { |
a7812ae4 | 1252 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1253 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0); |
1254 | tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx); | |
1255 | tcg_temp_free(addr); | |
1256 | } | |
fdf9b3e8 FB |
1257 | return; |
1258 | case 0x8500: /* mov.w @(disp,Rn),R0 */ | |
c55497ec | 1259 | { |
a7812ae4 | 1260 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1261 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); |
1262 | tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx); | |
1263 | tcg_temp_free(addr); | |
1264 | } | |
fdf9b3e8 FB |
1265 | return; |
1266 | case 0xc700: /* mova @(disp,PC),R0 */ | |
7efbe241 | 1267 | tcg_gen_movi_i32(REG(0), ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3); |
fdf9b3e8 FB |
1268 | return; |
1269 | case 0xcb00: /* or #imm,R0 */ | |
7efbe241 | 1270 | tcg_gen_ori_i32(REG(0), REG(0), B7_0); |
fdf9b3e8 | 1271 | return; |
24988dc2 | 1272 | case 0xcf00: /* or.b #imm,@(R0,GBR) */ |
c55497ec AJ |
1273 | { |
1274 | TCGv addr, val; | |
a7812ae4 | 1275 | addr = tcg_temp_new(); |
c55497ec | 1276 | tcg_gen_add_i32(addr, REG(0), cpu_gbr); |
a7812ae4 | 1277 | val = tcg_temp_new(); |
c55497ec AJ |
1278 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
1279 | tcg_gen_ori_i32(val, val, B7_0); | |
1280 | tcg_gen_qemu_st8(val, addr, ctx->memidx); | |
1281 | tcg_temp_free(val); | |
1282 | tcg_temp_free(addr); | |
1283 | } | |
fdf9b3e8 FB |
1284 | return; |
1285 | case 0xc300: /* trapa #imm */ | |
c55497ec AJ |
1286 | { |
1287 | TCGv imm; | |
1288 | CHECK_NOT_DELAY_SLOT | |
1289 | tcg_gen_movi_i32(cpu_pc, ctx->pc); | |
1290 | imm = tcg_const_i32(B7_0); | |
a7812ae4 | 1291 | gen_helper_trapa(imm); |
c55497ec AJ |
1292 | tcg_temp_free(imm); |
1293 | ctx->bstate = BS_BRANCH; | |
1294 | } | |
fdf9b3e8 FB |
1295 | return; |
1296 | case 0xc800: /* tst #imm,R0 */ | |
c55497ec | 1297 | { |
a7812ae4 | 1298 | TCGv val = tcg_temp_new(); |
c55497ec AJ |
1299 | tcg_gen_andi_i32(val, REG(0), B7_0); |
1300 | gen_cmp_imm(TCG_COND_EQ, val, 0); | |
1301 | tcg_temp_free(val); | |
1302 | } | |
fdf9b3e8 | 1303 | return; |
24988dc2 | 1304 | case 0xcc00: /* tst.b #imm,@(R0,GBR) */ |
c55497ec | 1305 | { |
a7812ae4 | 1306 | TCGv val = tcg_temp_new(); |
c55497ec AJ |
1307 | tcg_gen_add_i32(val, REG(0), cpu_gbr); |
1308 | tcg_gen_qemu_ld8u(val, val, ctx->memidx); | |
1309 | tcg_gen_andi_i32(val, val, B7_0); | |
1310 | gen_cmp_imm(TCG_COND_EQ, val, 0); | |
1311 | tcg_temp_free(val); | |
1312 | } | |
fdf9b3e8 FB |
1313 | return; |
1314 | case 0xca00: /* xor #imm,R0 */ | |
7efbe241 | 1315 | tcg_gen_xori_i32(REG(0), REG(0), B7_0); |
fdf9b3e8 | 1316 | return; |
24988dc2 | 1317 | case 0xce00: /* xor.b #imm,@(R0,GBR) */ |
c55497ec AJ |
1318 | { |
1319 | TCGv addr, val; | |
a7812ae4 | 1320 | addr = tcg_temp_new(); |
c55497ec | 1321 | tcg_gen_add_i32(addr, REG(0), cpu_gbr); |
a7812ae4 | 1322 | val = tcg_temp_new(); |
c55497ec AJ |
1323 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
1324 | tcg_gen_xori_i32(val, val, B7_0); | |
1325 | tcg_gen_qemu_st8(val, addr, ctx->memidx); | |
1326 | tcg_temp_free(val); | |
1327 | tcg_temp_free(addr); | |
1328 | } | |
fdf9b3e8 FB |
1329 | return; |
1330 | } | |
1331 | ||
1332 | switch (ctx->opcode & 0xf08f) { | |
1333 | case 0x408e: /* ldc Rm,Rn_BANK */ | |
fe25591e | 1334 | CHECK_PRIVILEGED |
7efbe241 | 1335 | tcg_gen_mov_i32(ALTREG(B6_4), REG(B11_8)); |
fdf9b3e8 FB |
1336 | return; |
1337 | case 0x4087: /* ldc.l @Rm+,Rn_BANK */ | |
fe25591e | 1338 | CHECK_PRIVILEGED |
7efbe241 AJ |
1339 | tcg_gen_qemu_ld32s(ALTREG(B6_4), REG(B11_8), ctx->memidx); |
1340 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); | |
fdf9b3e8 FB |
1341 | return; |
1342 | case 0x0082: /* stc Rm_BANK,Rn */ | |
fe25591e | 1343 | CHECK_PRIVILEGED |
7efbe241 | 1344 | tcg_gen_mov_i32(REG(B11_8), ALTREG(B6_4)); |
fdf9b3e8 FB |
1345 | return; |
1346 | case 0x4083: /* stc.l Rm_BANK,@-Rn */ | |
fe25591e | 1347 | CHECK_PRIVILEGED |
c55497ec | 1348 | { |
a7812ae4 | 1349 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1350 | tcg_gen_subi_i32(addr, REG(B11_8), 4); |
1351 | tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx); | |
1352 | tcg_temp_free(addr); | |
1353 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); | |
1354 | } | |
fdf9b3e8 FB |
1355 | return; |
1356 | } | |
1357 | ||
1358 | switch (ctx->opcode & 0xf0ff) { | |
1359 | case 0x0023: /* braf Rn */ | |
7efbe241 AJ |
1360 | CHECK_NOT_DELAY_SLOT |
1361 | tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->pc + 4); | |
fdf9b3e8 FB |
1362 | ctx->flags |= DELAY_SLOT; |
1363 | ctx->delayed_pc = (uint32_t) - 1; | |
1364 | return; | |
1365 | case 0x0003: /* bsrf Rn */ | |
7efbe241 | 1366 | CHECK_NOT_DELAY_SLOT |
1000822b | 1367 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4); |
7efbe241 | 1368 | tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr); |
fdf9b3e8 FB |
1369 | ctx->flags |= DELAY_SLOT; |
1370 | ctx->delayed_pc = (uint32_t) - 1; | |
1371 | return; | |
1372 | case 0x4015: /* cmp/pl Rn */ | |
7efbe241 | 1373 | gen_cmp_imm(TCG_COND_GT, REG(B11_8), 0); |
fdf9b3e8 FB |
1374 | return; |
1375 | case 0x4011: /* cmp/pz Rn */ | |
7efbe241 | 1376 | gen_cmp_imm(TCG_COND_GE, REG(B11_8), 0); |
fdf9b3e8 FB |
1377 | return; |
1378 | case 0x4010: /* dt Rn */ | |
7efbe241 AJ |
1379 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); |
1380 | gen_cmp_imm(TCG_COND_EQ, REG(B11_8), 0); | |
fdf9b3e8 FB |
1381 | return; |
1382 | case 0x402b: /* jmp @Rn */ | |
7efbe241 AJ |
1383 | CHECK_NOT_DELAY_SLOT |
1384 | tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); | |
fdf9b3e8 FB |
1385 | ctx->flags |= DELAY_SLOT; |
1386 | ctx->delayed_pc = (uint32_t) - 1; | |
1387 | return; | |
1388 | case 0x400b: /* jsr @Rn */ | |
7efbe241 | 1389 | CHECK_NOT_DELAY_SLOT |
1000822b | 1390 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4); |
7efbe241 | 1391 | tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); |
fdf9b3e8 FB |
1392 | ctx->flags |= DELAY_SLOT; |
1393 | ctx->delayed_pc = (uint32_t) - 1; | |
1394 | return; | |
fe25591e AJ |
1395 | case 0x400e: /* ldc Rm,SR */ |
1396 | CHECK_PRIVILEGED | |
7efbe241 | 1397 | tcg_gen_andi_i32(cpu_sr, REG(B11_8), 0x700083f3); |
390af821 AJ |
1398 | ctx->bstate = BS_STOP; |
1399 | return; | |
fe25591e AJ |
1400 | case 0x4007: /* ldc.l @Rm+,SR */ |
1401 | CHECK_PRIVILEGED | |
c55497ec | 1402 | { |
a7812ae4 | 1403 | TCGv val = tcg_temp_new(); |
c55497ec AJ |
1404 | tcg_gen_qemu_ld32s(val, REG(B11_8), ctx->memidx); |
1405 | tcg_gen_andi_i32(cpu_sr, val, 0x700083f3); | |
1406 | tcg_temp_free(val); | |
1407 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); | |
1408 | ctx->bstate = BS_STOP; | |
1409 | } | |
390af821 | 1410 | return; |
fe25591e AJ |
1411 | case 0x0002: /* stc SR,Rn */ |
1412 | CHECK_PRIVILEGED | |
7efbe241 | 1413 | tcg_gen_mov_i32(REG(B11_8), cpu_sr); |
390af821 | 1414 | return; |
fe25591e AJ |
1415 | case 0x4003: /* stc SR,@-Rn */ |
1416 | CHECK_PRIVILEGED | |
c55497ec | 1417 | { |
a7812ae4 | 1418 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1419 | tcg_gen_subi_i32(addr, REG(B11_8), 4); |
1420 | tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx); | |
1421 | tcg_temp_free(addr); | |
1422 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); | |
1423 | } | |
390af821 | 1424 | return; |
fe25591e | 1425 | #define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \ |
fdf9b3e8 | 1426 | case ldnum: \ |
fe25591e | 1427 | prechk \ |
7efbe241 | 1428 | tcg_gen_mov_i32 (cpu_##reg, REG(B11_8)); \ |
fdf9b3e8 FB |
1429 | return; \ |
1430 | case ldpnum: \ | |
fe25591e | 1431 | prechk \ |
7efbe241 AJ |
1432 | tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx); \ |
1433 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); \ | |
fdf9b3e8 FB |
1434 | return; \ |
1435 | case stnum: \ | |
fe25591e | 1436 | prechk \ |
7efbe241 | 1437 | tcg_gen_mov_i32 (REG(B11_8), cpu_##reg); \ |
fdf9b3e8 FB |
1438 | return; \ |
1439 | case stpnum: \ | |
fe25591e | 1440 | prechk \ |
c55497ec | 1441 | { \ |
a7812ae4 | 1442 | TCGv addr = tcg_temp_new(); \ |
c55497ec AJ |
1443 | tcg_gen_subi_i32(addr, REG(B11_8), 4); \ |
1444 | tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx); \ | |
1445 | tcg_temp_free(addr); \ | |
1446 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); \ | |
86e0abc7 | 1447 | } \ |
fdf9b3e8 | 1448 | return; |
fe25591e AJ |
1449 | LDST(gbr, 0x401e, 0x4017, 0x0012, 0x4013, {}) |
1450 | LDST(vbr, 0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED) | |
1451 | LDST(ssr, 0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED) | |
1452 | LDST(spc, 0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED) | |
1453 | LDST(dbr, 0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED) | |
1454 | LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {}) | |
1455 | LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {}) | |
1456 | LDST(pr, 0x402a, 0x4026, 0x002a, 0x4022, {}) | |
1457 | LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {}) | |
390af821 | 1458 | case 0x406a: /* lds Rm,FPSCR */ |
a7812ae4 | 1459 | gen_helper_ld_fpscr(REG(B11_8)); |
390af821 AJ |
1460 | ctx->bstate = BS_STOP; |
1461 | return; | |
1462 | case 0x4066: /* lds.l @Rm+,FPSCR */ | |
c55497ec | 1463 | { |
a7812ae4 | 1464 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1465 | tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx); |
1466 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); | |
a7812ae4 | 1467 | gen_helper_ld_fpscr(addr); |
c55497ec AJ |
1468 | tcg_temp_free(addr); |
1469 | ctx->bstate = BS_STOP; | |
1470 | } | |
390af821 AJ |
1471 | return; |
1472 | case 0x006a: /* sts FPSCR,Rn */ | |
c55497ec | 1473 | tcg_gen_andi_i32(REG(B11_8), cpu_fpscr, 0x003fffff); |
390af821 AJ |
1474 | return; |
1475 | case 0x4062: /* sts FPSCR,@-Rn */ | |
c55497ec AJ |
1476 | { |
1477 | TCGv addr, val; | |
a7812ae4 | 1478 | val = tcg_temp_new(); |
c55497ec | 1479 | tcg_gen_andi_i32(val, cpu_fpscr, 0x003fffff); |
a7812ae4 | 1480 | addr = tcg_temp_new(); |
c55497ec AJ |
1481 | tcg_gen_subi_i32(addr, REG(B11_8), 4); |
1482 | tcg_gen_qemu_st32(val, addr, ctx->memidx); | |
1483 | tcg_temp_free(addr); | |
1484 | tcg_temp_free(val); | |
1485 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); | |
1486 | } | |
390af821 | 1487 | return; |
fdf9b3e8 | 1488 | case 0x00c3: /* movca.l R0,@Rm */ |
7efbe241 | 1489 | tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx); |
fdf9b3e8 | 1490 | return; |
7526aa2d AJ |
1491 | case 0x40a9: |
1492 | /* MOVUA.L @Rm,R0 (Rm) -> R0 | |
1493 | Load non-boundary-aligned data */ | |
1494 | tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx); | |
1495 | return; | |
1496 | case 0x40e9: | |
1497 | /* MOVUA.L @Rm+,R0 (Rm) -> R0, Rm + 4 -> Rm | |
1498 | Load non-boundary-aligned data */ | |
1499 | tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx); | |
1500 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); | |
1501 | return; | |
fdf9b3e8 | 1502 | case 0x0029: /* movt Rn */ |
7efbe241 | 1503 | tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T); |
fdf9b3e8 FB |
1504 | return; |
1505 | case 0x0093: /* ocbi @Rn */ | |
c55497ec | 1506 | { |
a7812ae4 | 1507 | TCGv dummy = tcg_temp_new(); |
c55497ec AJ |
1508 | tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); |
1509 | tcg_temp_free(dummy); | |
1510 | } | |
fdf9b3e8 | 1511 | return; |
24988dc2 | 1512 | case 0x00a3: /* ocbp @Rn */ |
c55497ec | 1513 | { |
a7812ae4 | 1514 | TCGv dummy = tcg_temp_new(); |
c55497ec AJ |
1515 | tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); |
1516 | tcg_temp_free(dummy); | |
1517 | } | |
fdf9b3e8 FB |
1518 | return; |
1519 | case 0x00b3: /* ocbwb @Rn */ | |
c55497ec | 1520 | { |
a7812ae4 | 1521 | TCGv dummy = tcg_temp_new(); |
c55497ec AJ |
1522 | tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); |
1523 | tcg_temp_free(dummy); | |
1524 | } | |
fdf9b3e8 FB |
1525 | return; |
1526 | case 0x0083: /* pref @Rn */ | |
1527 | return; | |
1528 | case 0x4024: /* rotcl Rn */ | |
c55497ec | 1529 | { |
a7812ae4 | 1530 | TCGv tmp = tcg_temp_new(); |
c55497ec AJ |
1531 | tcg_gen_mov_i32(tmp, cpu_sr); |
1532 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); | |
1533 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); | |
1534 | gen_copy_bit_i32(REG(B11_8), 0, tmp, 0); | |
1535 | tcg_temp_free(tmp); | |
1536 | } | |
fdf9b3e8 FB |
1537 | return; |
1538 | case 0x4025: /* rotcr Rn */ | |
c55497ec | 1539 | { |
a7812ae4 | 1540 | TCGv tmp = tcg_temp_new(); |
c55497ec AJ |
1541 | tcg_gen_mov_i32(tmp, cpu_sr); |
1542 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); | |
1543 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1); | |
1544 | gen_copy_bit_i32(REG(B11_8), 31, tmp, 0); | |
1545 | tcg_temp_free(tmp); | |
1546 | } | |
fdf9b3e8 FB |
1547 | return; |
1548 | case 0x4004: /* rotl Rn */ | |
7efbe241 AJ |
1549 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); |
1550 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); | |
1551 | gen_copy_bit_i32(REG(B11_8), 0, cpu_sr, 0); | |
fdf9b3e8 FB |
1552 | return; |
1553 | case 0x4005: /* rotr Rn */ | |
7efbe241 AJ |
1554 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1555 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1); | |
1556 | gen_copy_bit_i32(REG(B11_8), 31, cpu_sr, 0); | |
fdf9b3e8 FB |
1557 | return; |
1558 | case 0x4000: /* shll Rn */ | |
1559 | case 0x4020: /* shal Rn */ | |
7efbe241 AJ |
1560 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); |
1561 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); | |
fdf9b3e8 FB |
1562 | return; |
1563 | case 0x4021: /* shar Rn */ | |
7efbe241 AJ |
1564 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1565 | tcg_gen_sari_i32(REG(B11_8), REG(B11_8), 1); | |
fdf9b3e8 FB |
1566 | return; |
1567 | case 0x4001: /* shlr Rn */ | |
7efbe241 AJ |
1568 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1569 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1); | |
fdf9b3e8 FB |
1570 | return; |
1571 | case 0x4008: /* shll2 Rn */ | |
7efbe241 | 1572 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 2); |
fdf9b3e8 FB |
1573 | return; |
1574 | case 0x4018: /* shll8 Rn */ | |
7efbe241 | 1575 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 8); |
fdf9b3e8 FB |
1576 | return; |
1577 | case 0x4028: /* shll16 Rn */ | |
7efbe241 | 1578 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 16); |
fdf9b3e8 FB |
1579 | return; |
1580 | case 0x4009: /* shlr2 Rn */ | |
7efbe241 | 1581 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 2); |
fdf9b3e8 FB |
1582 | return; |
1583 | case 0x4019: /* shlr8 Rn */ | |
7efbe241 | 1584 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 8); |
fdf9b3e8 FB |
1585 | return; |
1586 | case 0x4029: /* shlr16 Rn */ | |
7efbe241 | 1587 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16); |
fdf9b3e8 FB |
1588 | return; |
1589 | case 0x401b: /* tas.b @Rn */ | |
c55497ec AJ |
1590 | { |
1591 | TCGv addr, val; | |
1592 | addr = tcg_temp_local_new(TCG_TYPE_I32); | |
1593 | tcg_gen_mov_i32(addr, REG(B11_8)); | |
1594 | val = tcg_temp_local_new(TCG_TYPE_I32); | |
1595 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); | |
1596 | gen_cmp_imm(TCG_COND_EQ, val, 0); | |
1597 | tcg_gen_ori_i32(val, val, 0x80); | |
1598 | tcg_gen_qemu_st8(val, addr, ctx->memidx); | |
1599 | tcg_temp_free(val); | |
1600 | tcg_temp_free(addr); | |
1601 | } | |
fdf9b3e8 | 1602 | return; |
e67888a7 | 1603 | case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ |
cc4ba6a9 | 1604 | { |
66ba317c | 1605 | tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fpul); |
cc4ba6a9 | 1606 | } |
eda9b09b | 1607 | return; |
e67888a7 | 1608 | case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */ |
cc4ba6a9 | 1609 | { |
66ba317c | 1610 | tcg_gen_mov_i32(cpu_fpul, cpu_fregs[FREG(B11_8)]); |
cc4ba6a9 | 1611 | } |
eda9b09b | 1612 | return; |
e67888a7 | 1613 | case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */ |
ea6cf6be | 1614 | if (ctx->fpscr & FPSCR_PR) { |
a7812ae4 | 1615 | TCGv_i64 fp; |
ea6cf6be TS |
1616 | if (ctx->opcode & 0x0100) |
1617 | break; /* illegal instruction */ | |
a7812ae4 PB |
1618 | fp = tcg_temp_new_i64(); |
1619 | gen_helper_float_DT(fp, cpu_fpul); | |
cc4ba6a9 | 1620 | gen_store_fpr64(fp, DREG(B11_8)); |
a7812ae4 | 1621 | tcg_temp_free_i64(fp); |
ea6cf6be TS |
1622 | } |
1623 | else { | |
66ba317c | 1624 | gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_fpul); |
ea6cf6be TS |
1625 | } |
1626 | return; | |
e67888a7 | 1627 | case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
ea6cf6be | 1628 | if (ctx->fpscr & FPSCR_PR) { |
a7812ae4 | 1629 | TCGv_i64 fp; |
ea6cf6be TS |
1630 | if (ctx->opcode & 0x0100) |
1631 | break; /* illegal instruction */ | |
a7812ae4 | 1632 | fp = tcg_temp_new_i64(); |
cc4ba6a9 | 1633 | gen_load_fpr64(fp, DREG(B11_8)); |
a7812ae4 PB |
1634 | gen_helper_ftrc_DT(cpu_fpul, fp); |
1635 | tcg_temp_free_i64(fp); | |
ea6cf6be TS |
1636 | } |
1637 | else { | |
66ba317c | 1638 | gen_helper_ftrc_FT(cpu_fpul, cpu_fregs[FREG(B11_8)]); |
ea6cf6be TS |
1639 | } |
1640 | return; | |
24988dc2 | 1641 | case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ |
7fdf924f | 1642 | { |
66ba317c | 1643 | gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); |
7fdf924f | 1644 | } |
24988dc2 AJ |
1645 | return; |
1646 | case 0xf05d: /* fabs FRn/DRn */ | |
1647 | if (ctx->fpscr & FPSCR_PR) { | |
1648 | if (ctx->opcode & 0x0100) | |
1649 | break; /* illegal instruction */ | |
a7812ae4 | 1650 | TCGv_i64 fp = tcg_temp_new_i64(); |
cc4ba6a9 | 1651 | gen_load_fpr64(fp, DREG(B11_8)); |
a7812ae4 | 1652 | gen_helper_fabs_DT(fp, fp); |
cc4ba6a9 | 1653 | gen_store_fpr64(fp, DREG(B11_8)); |
a7812ae4 | 1654 | tcg_temp_free_i64(fp); |
24988dc2 | 1655 | } else { |
66ba317c | 1656 | gen_helper_fabs_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); |
24988dc2 AJ |
1657 | } |
1658 | return; | |
1659 | case 0xf06d: /* fsqrt FRn */ | |
1660 | if (ctx->fpscr & FPSCR_PR) { | |
1661 | if (ctx->opcode & 0x0100) | |
1662 | break; /* illegal instruction */ | |
a7812ae4 | 1663 | TCGv_i64 fp = tcg_temp_new_i64(); |
cc4ba6a9 | 1664 | gen_load_fpr64(fp, DREG(B11_8)); |
a7812ae4 | 1665 | gen_helper_fsqrt_DT(fp, fp); |
cc4ba6a9 | 1666 | gen_store_fpr64(fp, DREG(B11_8)); |
a7812ae4 | 1667 | tcg_temp_free_i64(fp); |
24988dc2 | 1668 | } else { |
66ba317c | 1669 | gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); |
24988dc2 AJ |
1670 | } |
1671 | return; | |
1672 | case 0xf07d: /* fsrra FRn */ | |
1673 | break; | |
e67888a7 | 1674 | case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ |
ea6cf6be | 1675 | if (!(ctx->fpscr & FPSCR_PR)) { |
66ba317c | 1676 | tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0); |
ea6cf6be | 1677 | } |
12d96138 | 1678 | return; |
e67888a7 | 1679 | case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ |
ea6cf6be | 1680 | if (!(ctx->fpscr & FPSCR_PR)) { |
66ba317c | 1681 | tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000); |
ea6cf6be | 1682 | } |
12d96138 | 1683 | return; |
24988dc2 | 1684 | case 0xf0ad: /* fcnvsd FPUL,DRn */ |
cc4ba6a9 | 1685 | { |
a7812ae4 PB |
1686 | TCGv_i64 fp = tcg_temp_new_i64(); |
1687 | gen_helper_fcnvsd_FT_DT(fp, cpu_fpul); | |
cc4ba6a9 | 1688 | gen_store_fpr64(fp, DREG(B11_8)); |
a7812ae4 | 1689 | tcg_temp_free_i64(fp); |
cc4ba6a9 | 1690 | } |
24988dc2 AJ |
1691 | return; |
1692 | case 0xf0bd: /* fcnvds DRn,FPUL */ | |
cc4ba6a9 | 1693 | { |
a7812ae4 | 1694 | TCGv_i64 fp = tcg_temp_new_i64(); |
cc4ba6a9 | 1695 | gen_load_fpr64(fp, DREG(B11_8)); |
a7812ae4 PB |
1696 | gen_helper_fcnvds_DT_FT(cpu_fpul, fp); |
1697 | tcg_temp_free_i64(fp); | |
cc4ba6a9 | 1698 | } |
24988dc2 | 1699 | return; |
fdf9b3e8 FB |
1700 | } |
1701 | ||
1702 | fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n", | |
1703 | ctx->opcode, ctx->pc); | |
a7812ae4 | 1704 | gen_helper_raise_illegal_instruction(); |
823029f9 TS |
1705 | ctx->bstate = BS_EXCP; |
1706 | } | |
1707 | ||
b1d8e52e | 1708 | static void decode_opc(DisasContext * ctx) |
823029f9 TS |
1709 | { |
1710 | uint32_t old_flags = ctx->flags; | |
1711 | ||
1712 | _decode_opc(ctx); | |
1713 | ||
1714 | if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { | |
1715 | if (ctx->flags & DELAY_SLOT_CLEARME) { | |
1000822b | 1716 | gen_store_flags(0); |
274a9e70 AJ |
1717 | } else { |
1718 | /* go out of the delay slot */ | |
1719 | uint32_t new_flags = ctx->flags; | |
1720 | new_flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); | |
1000822b | 1721 | gen_store_flags(new_flags); |
823029f9 TS |
1722 | } |
1723 | ctx->flags = 0; | |
1724 | ctx->bstate = BS_BRANCH; | |
1725 | if (old_flags & DELAY_SLOT_CONDITIONAL) { | |
1726 | gen_delayed_conditional_jump(ctx); | |
1727 | } else if (old_flags & DELAY_SLOT) { | |
1728 | gen_jump(ctx); | |
1729 | } | |
1730 | ||
1731 | } | |
274a9e70 AJ |
1732 | |
1733 | /* go into a delay slot */ | |
1734 | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) | |
1000822b | 1735 | gen_store_flags(ctx->flags); |
fdf9b3e8 FB |
1736 | } |
1737 | ||
2cfc5f17 | 1738 | static inline void |
820e00f2 TS |
1739 | gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb, |
1740 | int search_pc) | |
fdf9b3e8 FB |
1741 | { |
1742 | DisasContext ctx; | |
1743 | target_ulong pc_start; | |
1744 | static uint16_t *gen_opc_end; | |
a1d1bb31 | 1745 | CPUBreakpoint *bp; |
355fb23d | 1746 | int i, ii; |
2e70f6ef PB |
1747 | int num_insns; |
1748 | int max_insns; | |
fdf9b3e8 FB |
1749 | |
1750 | pc_start = tb->pc; | |
fdf9b3e8 | 1751 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
fdf9b3e8 | 1752 | ctx.pc = pc_start; |
823029f9 TS |
1753 | ctx.flags = (uint32_t)tb->flags; |
1754 | ctx.bstate = BS_NONE; | |
fdf9b3e8 | 1755 | ctx.sr = env->sr; |
eda9b09b | 1756 | ctx.fpscr = env->fpscr; |
fdf9b3e8 | 1757 | ctx.memidx = (env->sr & SR_MD) ? 1 : 0; |
9854bc46 PB |
1758 | /* We don't know if the delayed pc came from a dynamic or static branch, |
1759 | so assume it is a dynamic branch. */ | |
823029f9 | 1760 | ctx.delayed_pc = -1; /* use delayed pc from env pointer */ |
fdf9b3e8 FB |
1761 | ctx.tb = tb; |
1762 | ctx.singlestep_enabled = env->singlestep_enabled; | |
fdf9b3e8 FB |
1763 | |
1764 | #ifdef DEBUG_DISAS | |
1765 | if (loglevel & CPU_LOG_TB_CPU) { | |
1766 | fprintf(logfile, | |
1767 | "------------------------------------------------\n"); | |
1768 | cpu_dump_state(env, logfile, fprintf, 0); | |
1769 | } | |
1770 | #endif | |
1771 | ||
355fb23d | 1772 | ii = -1; |
2e70f6ef PB |
1773 | num_insns = 0; |
1774 | max_insns = tb->cflags & CF_COUNT_MASK; | |
1775 | if (max_insns == 0) | |
1776 | max_insns = CF_COUNT_MASK; | |
1777 | gen_icount_start(); | |
823029f9 | 1778 | while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) { |
c0ce998e AL |
1779 | if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) { |
1780 | TAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a1d1bb31 | 1781 | if (ctx.pc == bp->pc) { |
fdf9b3e8 | 1782 | /* We have hit a breakpoint - make sure PC is up-to-date */ |
3a8a44c4 | 1783 | tcg_gen_movi_i32(cpu_pc, ctx.pc); |
a7812ae4 | 1784 | gen_helper_debug(); |
823029f9 | 1785 | ctx.bstate = BS_EXCP; |
fdf9b3e8 FB |
1786 | break; |
1787 | } | |
1788 | } | |
1789 | } | |
355fb23d PB |
1790 | if (search_pc) { |
1791 | i = gen_opc_ptr - gen_opc_buf; | |
1792 | if (ii < i) { | |
1793 | ii++; | |
1794 | while (ii < i) | |
1795 | gen_opc_instr_start[ii++] = 0; | |
1796 | } | |
1797 | gen_opc_pc[ii] = ctx.pc; | |
823029f9 | 1798 | gen_opc_hflags[ii] = ctx.flags; |
355fb23d | 1799 | gen_opc_instr_start[ii] = 1; |
2e70f6ef | 1800 | gen_opc_icount[ii] = num_insns; |
355fb23d | 1801 | } |
2e70f6ef PB |
1802 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
1803 | gen_io_start(); | |
fdf9b3e8 FB |
1804 | #if 0 |
1805 | fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc); | |
1806 | fflush(stderr); | |
1807 | #endif | |
1808 | ctx.opcode = lduw_code(ctx.pc); | |
1809 | decode_opc(&ctx); | |
2e70f6ef | 1810 | num_insns++; |
fdf9b3e8 FB |
1811 | ctx.pc += 2; |
1812 | if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) | |
1813 | break; | |
1814 | if (env->singlestep_enabled) | |
1815 | break; | |
2e70f6ef PB |
1816 | if (num_insns >= max_insns) |
1817 | break; | |
fdf9b3e8 FB |
1818 | #ifdef SH4_SINGLE_STEP |
1819 | break; | |
1820 | #endif | |
1821 | } | |
2e70f6ef PB |
1822 | if (tb->cflags & CF_LAST_IO) |
1823 | gen_io_end(); | |
fdf9b3e8 | 1824 | if (env->singlestep_enabled) { |
bdbf22e6 | 1825 | tcg_gen_movi_i32(cpu_pc, ctx.pc); |
a7812ae4 | 1826 | gen_helper_debug(); |
823029f9 TS |
1827 | } else { |
1828 | switch (ctx.bstate) { | |
1829 | case BS_STOP: | |
1830 | /* gen_op_interrupt_restart(); */ | |
1831 | /* fall through */ | |
1832 | case BS_NONE: | |
1833 | if (ctx.flags) { | |
1000822b | 1834 | gen_store_flags(ctx.flags | DELAY_SLOT_CLEARME); |
823029f9 TS |
1835 | } |
1836 | gen_goto_tb(&ctx, 0, ctx.pc); | |
1837 | break; | |
1838 | case BS_EXCP: | |
1839 | /* gen_op_interrupt_restart(); */ | |
57fec1fe | 1840 | tcg_gen_exit_tb(0); |
823029f9 TS |
1841 | break; |
1842 | case BS_BRANCH: | |
1843 | default: | |
1844 | break; | |
1845 | } | |
fdf9b3e8 | 1846 | } |
823029f9 | 1847 | |
2e70f6ef | 1848 | gen_icount_end(tb, num_insns); |
fdf9b3e8 | 1849 | *gen_opc_ptr = INDEX_op_end; |
355fb23d PB |
1850 | if (search_pc) { |
1851 | i = gen_opc_ptr - gen_opc_buf; | |
1852 | ii++; | |
1853 | while (ii <= i) | |
1854 | gen_opc_instr_start[ii++] = 0; | |
355fb23d PB |
1855 | } else { |
1856 | tb->size = ctx.pc - pc_start; | |
2e70f6ef | 1857 | tb->icount = num_insns; |
355fb23d | 1858 | } |
fdf9b3e8 FB |
1859 | |
1860 | #ifdef DEBUG_DISAS | |
1861 | #ifdef SH4_DEBUG_DISAS | |
1862 | if (loglevel & CPU_LOG_TB_IN_ASM) | |
1863 | fprintf(logfile, "\n"); | |
1864 | #endif | |
1865 | if (loglevel & CPU_LOG_TB_IN_ASM) { | |
1866 | fprintf(logfile, "IN:\n"); /* , lookup_symbol(pc_start)); */ | |
1867 | target_disas(logfile, pc_start, ctx.pc - pc_start, 0); | |
1868 | fprintf(logfile, "\n"); | |
1869 | } | |
fdf9b3e8 | 1870 | #endif |
fdf9b3e8 FB |
1871 | } |
1872 | ||
2cfc5f17 | 1873 | void gen_intermediate_code(CPUState * env, struct TranslationBlock *tb) |
fdf9b3e8 | 1874 | { |
2cfc5f17 | 1875 | gen_intermediate_code_internal(env, tb, 0); |
fdf9b3e8 FB |
1876 | } |
1877 | ||
2cfc5f17 | 1878 | void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb) |
fdf9b3e8 | 1879 | { |
2cfc5f17 | 1880 | gen_intermediate_code_internal(env, tb, 1); |
fdf9b3e8 | 1881 | } |
d2856f1a AJ |
1882 | |
1883 | void gen_pc_load(CPUState *env, TranslationBlock *tb, | |
1884 | unsigned long searched_pc, int pc_pos, void *puc) | |
1885 | { | |
1886 | env->pc = gen_opc_pc[pc_pos]; | |
1887 | env->flags = gen_opc_hflags[pc_pos]; | |
1888 | } |