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Commit | Line | Data |
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fdf9b3e8 FB |
1 | /* |
2 | * SH4 translation | |
5fafdf24 | 3 | * |
fdf9b3e8 FB |
4 | * Copyright (c) 2005 Samuel Tardieu |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | #include <stdarg.h> | |
21 | #include <stdlib.h> | |
22 | #include <stdio.h> | |
23 | #include <string.h> | |
24 | #include <inttypes.h> | |
25 | #include <assert.h> | |
26 | ||
27 | #define DEBUG_DISAS | |
28 | #define SH4_DEBUG_DISAS | |
29 | //#define SH4_SINGLE_STEP | |
30 | ||
31 | #include "cpu.h" | |
32 | #include "exec-all.h" | |
33 | #include "disas.h" | |
57fec1fe | 34 | #include "tcg-op.h" |
ca10f867 | 35 | #include "qemu-common.h" |
fdf9b3e8 | 36 | |
a7812ae4 PB |
37 | #include "helper.h" |
38 | #define GEN_HELPER 1 | |
39 | #include "helper.h" | |
40 | ||
fdf9b3e8 FB |
41 | typedef struct DisasContext { |
42 | struct TranslationBlock *tb; | |
43 | target_ulong pc; | |
44 | uint32_t sr; | |
eda9b09b | 45 | uint32_t fpscr; |
fdf9b3e8 FB |
46 | uint16_t opcode; |
47 | uint32_t flags; | |
823029f9 | 48 | int bstate; |
fdf9b3e8 FB |
49 | int memidx; |
50 | uint32_t delayed_pc; | |
51 | int singlestep_enabled; | |
71968fa6 | 52 | uint32_t features; |
fdf9b3e8 FB |
53 | } DisasContext; |
54 | ||
fe25591e AJ |
55 | #if defined(CONFIG_USER_ONLY) |
56 | #define IS_USER(ctx) 1 | |
57 | #else | |
58 | #define IS_USER(ctx) (!(ctx->sr & SR_MD)) | |
59 | #endif | |
60 | ||
823029f9 TS |
61 | enum { |
62 | BS_NONE = 0, /* We go out of the TB without reaching a branch or an | |
63 | * exception condition | |
64 | */ | |
65 | BS_STOP = 1, /* We want to stop translation for any reason */ | |
66 | BS_BRANCH = 2, /* We reached a branch condition */ | |
67 | BS_EXCP = 3, /* We reached an exception condition */ | |
68 | }; | |
69 | ||
1e8864f7 | 70 | /* global register indexes */ |
a7812ae4 | 71 | static TCGv_ptr cpu_env; |
1e8864f7 | 72 | static TCGv cpu_gregs[24]; |
3a8a44c4 AJ |
73 | static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr; |
74 | static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl; | |
b79e1752 | 75 | static TCGv cpu_pr, cpu_fpscr, cpu_fpul; |
66ba317c | 76 | static TCGv cpu_fregs[32]; |
1000822b AJ |
77 | |
78 | /* internal register indexes */ | |
79 | static TCGv cpu_flags, cpu_delayed_pc; | |
1e8864f7 | 80 | |
2e70f6ef PB |
81 | #include "gen-icount.h" |
82 | ||
a5f1b965 | 83 | static void sh4_translate_init(void) |
2e70f6ef | 84 | { |
1e8864f7 | 85 | int i; |
2e70f6ef | 86 | static int done_init = 0; |
559dd74d | 87 | static const char * const gregnames[24] = { |
1e8864f7 AJ |
88 | "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0", |
89 | "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0", | |
90 | "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", | |
91 | "R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1", | |
92 | "R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1" | |
93 | }; | |
66ba317c AJ |
94 | static const char * const fregnames[32] = { |
95 | "FPR0_BANK0", "FPR1_BANK0", "FPR2_BANK0", "FPR3_BANK0", | |
96 | "FPR4_BANK0", "FPR5_BANK0", "FPR6_BANK0", "FPR7_BANK0", | |
97 | "FPR8_BANK0", "FPR9_BANK0", "FPR10_BANK0", "FPR11_BANK0", | |
98 | "FPR12_BANK0", "FPR13_BANK0", "FPR14_BANK0", "FPR15_BANK0", | |
99 | "FPR0_BANK1", "FPR1_BANK1", "FPR2_BANK1", "FPR3_BANK1", | |
100 | "FPR4_BANK1", "FPR5_BANK1", "FPR6_BANK1", "FPR7_BANK1", | |
101 | "FPR8_BANK1", "FPR9_BANK1", "FPR10_BANK1", "FPR11_BANK1", | |
102 | "FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1", | |
103 | }; | |
1e8864f7 | 104 | |
2e70f6ef PB |
105 | if (done_init) |
106 | return; | |
1e8864f7 | 107 | |
a7812ae4 | 108 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
1e8864f7 AJ |
109 | |
110 | for (i = 0; i < 24; i++) | |
a7812ae4 | 111 | cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0, |
66ba317c AJ |
112 | offsetof(CPUState, gregs[i]), |
113 | gregnames[i]); | |
988d7eaa | 114 | |
a7812ae4 PB |
115 | cpu_pc = tcg_global_mem_new_i32(TCG_AREG0, |
116 | offsetof(CPUState, pc), "PC"); | |
117 | cpu_sr = tcg_global_mem_new_i32(TCG_AREG0, | |
118 | offsetof(CPUState, sr), "SR"); | |
119 | cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0, | |
120 | offsetof(CPUState, ssr), "SSR"); | |
121 | cpu_spc = tcg_global_mem_new_i32(TCG_AREG0, | |
122 | offsetof(CPUState, spc), "SPC"); | |
123 | cpu_gbr = tcg_global_mem_new_i32(TCG_AREG0, | |
124 | offsetof(CPUState, gbr), "GBR"); | |
125 | cpu_vbr = tcg_global_mem_new_i32(TCG_AREG0, | |
126 | offsetof(CPUState, vbr), "VBR"); | |
127 | cpu_sgr = tcg_global_mem_new_i32(TCG_AREG0, | |
128 | offsetof(CPUState, sgr), "SGR"); | |
129 | cpu_dbr = tcg_global_mem_new_i32(TCG_AREG0, | |
130 | offsetof(CPUState, dbr), "DBR"); | |
131 | cpu_mach = tcg_global_mem_new_i32(TCG_AREG0, | |
132 | offsetof(CPUState, mach), "MACH"); | |
133 | cpu_macl = tcg_global_mem_new_i32(TCG_AREG0, | |
134 | offsetof(CPUState, macl), "MACL"); | |
135 | cpu_pr = tcg_global_mem_new_i32(TCG_AREG0, | |
136 | offsetof(CPUState, pr), "PR"); | |
137 | cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, | |
138 | offsetof(CPUState, fpscr), "FPSCR"); | |
139 | cpu_fpul = tcg_global_mem_new_i32(TCG_AREG0, | |
140 | offsetof(CPUState, fpul), "FPUL"); | |
141 | ||
142 | cpu_flags = tcg_global_mem_new_i32(TCG_AREG0, | |
143 | offsetof(CPUState, flags), "_flags_"); | |
144 | cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0, | |
145 | offsetof(CPUState, delayed_pc), | |
146 | "_delayed_pc_"); | |
1000822b | 147 | |
66ba317c AJ |
148 | for (i = 0; i < 32; i++) |
149 | cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0, | |
150 | offsetof(CPUState, fregs[i]), | |
151 | fregnames[i]); | |
152 | ||
988d7eaa | 153 | /* register helpers */ |
a7812ae4 | 154 | #define GEN_HELPER 2 |
988d7eaa AJ |
155 | #include "helper.h" |
156 | ||
2e70f6ef PB |
157 | done_init = 1; |
158 | } | |
159 | ||
fdf9b3e8 FB |
160 | void cpu_dump_state(CPUState * env, FILE * f, |
161 | int (*cpu_fprintf) (FILE * f, const char *fmt, ...), | |
162 | int flags) | |
163 | { | |
164 | int i; | |
eda9b09b FB |
165 | cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n", |
166 | env->pc, env->sr, env->pr, env->fpscr); | |
274a9e70 AJ |
167 | cpu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n", |
168 | env->spc, env->ssr, env->gbr, env->vbr); | |
169 | cpu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n", | |
170 | env->sgr, env->dbr, env->delayed_pc, env->fpul); | |
fdf9b3e8 FB |
171 | for (i = 0; i < 24; i += 4) { |
172 | cpu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n", | |
173 | i, env->gregs[i], i + 1, env->gregs[i + 1], | |
174 | i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]); | |
175 | } | |
176 | if (env->flags & DELAY_SLOT) { | |
177 | cpu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n", | |
178 | env->delayed_pc); | |
179 | } else if (env->flags & DELAY_SLOT_CONDITIONAL) { | |
180 | cpu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n", | |
181 | env->delayed_pc); | |
182 | } | |
183 | } | |
184 | ||
b79e1752 | 185 | static void cpu_sh4_reset(CPUSH4State * env) |
fdf9b3e8 | 186 | { |
9c2a9ea1 | 187 | #if defined(CONFIG_USER_ONLY) |
f3ff7fac | 188 | env->sr = 0; |
9c2a9ea1 | 189 | #else |
56cd2b96 | 190 | env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0; |
9c2a9ea1 | 191 | #endif |
fdf9b3e8 FB |
192 | env->vbr = 0; |
193 | env->pc = 0xA0000000; | |
ea6cf6be TS |
194 | #if defined(CONFIG_USER_ONLY) |
195 | env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ | |
b0b3de89 | 196 | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ |
ea6cf6be TS |
197 | #else |
198 | env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */ | |
b0b3de89 | 199 | set_float_rounding_mode(float_round_to_zero, &env->fp_status); |
ea6cf6be | 200 | #endif |
fdf9b3e8 FB |
201 | env->mmucr = 0; |
202 | } | |
203 | ||
0fd3ca30 | 204 | typedef struct { |
b55266b5 | 205 | const char *name; |
0fd3ca30 AJ |
206 | int id; |
207 | uint32_t pvr; | |
208 | uint32_t prr; | |
209 | uint32_t cvr; | |
71968fa6 | 210 | uint32_t features; |
0fd3ca30 AJ |
211 | } sh4_def_t; |
212 | ||
213 | static sh4_def_t sh4_defs[] = { | |
214 | { | |
215 | .name = "SH7750R", | |
216 | .id = SH_CPU_SH7750R, | |
217 | .pvr = 0x00050000, | |
218 | .prr = 0x00000100, | |
219 | .cvr = 0x00110000, | |
220 | }, { | |
221 | .name = "SH7751R", | |
222 | .id = SH_CPU_SH7751R, | |
223 | .pvr = 0x04050005, | |
224 | .prr = 0x00000113, | |
225 | .cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */ | |
a9c43f8e AJ |
226 | }, { |
227 | .name = "SH7785", | |
228 | .id = SH_CPU_SH7785, | |
229 | .pvr = 0x10300700, | |
230 | .prr = 0x00000200, | |
231 | .cvr = 0x71440211, | |
71968fa6 | 232 | .features = SH_FEATURE_SH4A, |
a9c43f8e | 233 | }, |
0fd3ca30 AJ |
234 | }; |
235 | ||
b55266b5 | 236 | static const sh4_def_t *cpu_sh4_find_by_name(const char *name) |
0fd3ca30 AJ |
237 | { |
238 | int i; | |
239 | ||
240 | if (strcasecmp(name, "any") == 0) | |
241 | return &sh4_defs[0]; | |
242 | ||
b1503cda | 243 | for (i = 0; i < ARRAY_SIZE(sh4_defs); i++) |
0fd3ca30 AJ |
244 | if (strcasecmp(name, sh4_defs[i].name) == 0) |
245 | return &sh4_defs[i]; | |
246 | ||
247 | return NULL; | |
248 | } | |
249 | ||
250 | void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) | |
251 | { | |
252 | int i; | |
253 | ||
b1503cda | 254 | for (i = 0; i < ARRAY_SIZE(sh4_defs); i++) |
0fd3ca30 AJ |
255 | (*cpu_fprintf)(f, "%s\n", sh4_defs[i].name); |
256 | } | |
257 | ||
1ed1a787 | 258 | static void cpu_sh4_register(CPUSH4State *env, const sh4_def_t *def) |
0fd3ca30 AJ |
259 | { |
260 | env->pvr = def->pvr; | |
261 | env->prr = def->prr; | |
262 | env->cvr = def->cvr; | |
263 | env->id = def->id; | |
264 | } | |
265 | ||
aaed909a | 266 | CPUSH4State *cpu_sh4_init(const char *cpu_model) |
fdf9b3e8 FB |
267 | { |
268 | CPUSH4State *env; | |
0fd3ca30 | 269 | const sh4_def_t *def; |
fdf9b3e8 | 270 | |
0fd3ca30 AJ |
271 | def = cpu_sh4_find_by_name(cpu_model); |
272 | if (!def) | |
273 | return NULL; | |
fdf9b3e8 FB |
274 | env = qemu_mallocz(sizeof(CPUSH4State)); |
275 | if (!env) | |
276 | return NULL; | |
71968fa6 | 277 | env->features = def->features; |
fdf9b3e8 | 278 | cpu_exec_init(env); |
2e70f6ef | 279 | sh4_translate_init(); |
7478757e | 280 | env->cpu_model_str = cpu_model; |
fdf9b3e8 | 281 | cpu_sh4_reset(env); |
0fd3ca30 | 282 | cpu_sh4_register(env, def); |
fdf9b3e8 FB |
283 | tlb_flush(env, 1); |
284 | return env; | |
285 | } | |
286 | ||
fdf9b3e8 FB |
287 | static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest) |
288 | { | |
289 | TranslationBlock *tb; | |
290 | tb = ctx->tb; | |
291 | ||
292 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && | |
293 | !ctx->singlestep_enabled) { | |
294 | /* Use a direct jump if in same page and singlestep not enabled */ | |
57fec1fe | 295 | tcg_gen_goto_tb(n); |
3a8a44c4 | 296 | tcg_gen_movi_i32(cpu_pc, dest); |
57fec1fe | 297 | tcg_gen_exit_tb((long) tb + n); |
fdf9b3e8 | 298 | } else { |
3a8a44c4 | 299 | tcg_gen_movi_i32(cpu_pc, dest); |
57fec1fe | 300 | if (ctx->singlestep_enabled) |
a7812ae4 | 301 | gen_helper_debug(); |
57fec1fe | 302 | tcg_gen_exit_tb(0); |
fdf9b3e8 | 303 | } |
fdf9b3e8 FB |
304 | } |
305 | ||
fdf9b3e8 FB |
306 | static void gen_jump(DisasContext * ctx) |
307 | { | |
308 | if (ctx->delayed_pc == (uint32_t) - 1) { | |
309 | /* Target is not statically known, it comes necessarily from a | |
310 | delayed jump as immediate jump are conditinal jumps */ | |
1000822b | 311 | tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc); |
fdf9b3e8 | 312 | if (ctx->singlestep_enabled) |
a7812ae4 | 313 | gen_helper_debug(); |
57fec1fe | 314 | tcg_gen_exit_tb(0); |
fdf9b3e8 FB |
315 | } else { |
316 | gen_goto_tb(ctx, 0, ctx->delayed_pc); | |
317 | } | |
318 | } | |
319 | ||
1000822b AJ |
320 | static inline void gen_branch_slot(uint32_t delayed_pc, int t) |
321 | { | |
c55497ec | 322 | TCGv sr; |
1000822b AJ |
323 | int label = gen_new_label(); |
324 | tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc); | |
a7812ae4 | 325 | sr = tcg_temp_new(); |
c55497ec AJ |
326 | tcg_gen_andi_i32(sr, cpu_sr, SR_T); |
327 | tcg_gen_brcondi_i32(TCG_COND_NE, sr, t ? SR_T : 0, label); | |
1000822b AJ |
328 | tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE); |
329 | gen_set_label(label); | |
330 | } | |
331 | ||
fdf9b3e8 FB |
332 | /* Immediate conditional jump (bt or bf) */ |
333 | static void gen_conditional_jump(DisasContext * ctx, | |
334 | target_ulong ift, target_ulong ifnott) | |
335 | { | |
336 | int l1; | |
c55497ec | 337 | TCGv sr; |
fdf9b3e8 FB |
338 | |
339 | l1 = gen_new_label(); | |
a7812ae4 | 340 | sr = tcg_temp_new(); |
c55497ec AJ |
341 | tcg_gen_andi_i32(sr, cpu_sr, SR_T); |
342 | tcg_gen_brcondi_i32(TCG_COND_EQ, sr, SR_T, l1); | |
fdf9b3e8 FB |
343 | gen_goto_tb(ctx, 0, ifnott); |
344 | gen_set_label(l1); | |
345 | gen_goto_tb(ctx, 1, ift); | |
346 | } | |
347 | ||
348 | /* Delayed conditional jump (bt or bf) */ | |
349 | static void gen_delayed_conditional_jump(DisasContext * ctx) | |
350 | { | |
351 | int l1; | |
c55497ec | 352 | TCGv ds; |
fdf9b3e8 FB |
353 | |
354 | l1 = gen_new_label(); | |
a7812ae4 | 355 | ds = tcg_temp_new(); |
c55497ec AJ |
356 | tcg_gen_andi_i32(ds, cpu_flags, DELAY_SLOT_TRUE); |
357 | tcg_gen_brcondi_i32(TCG_COND_EQ, ds, DELAY_SLOT_TRUE, l1); | |
823029f9 | 358 | gen_goto_tb(ctx, 1, ctx->pc + 2); |
fdf9b3e8 | 359 | gen_set_label(l1); |
1000822b | 360 | tcg_gen_andi_i32(cpu_flags, cpu_flags, ~DELAY_SLOT_TRUE); |
9c2a9ea1 | 361 | gen_jump(ctx); |
fdf9b3e8 FB |
362 | } |
363 | ||
a4625612 AJ |
364 | static inline void gen_set_t(void) |
365 | { | |
366 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T); | |
367 | } | |
368 | ||
369 | static inline void gen_clr_t(void) | |
370 | { | |
371 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); | |
372 | } | |
373 | ||
374 | static inline void gen_cmp(int cond, TCGv t0, TCGv t1) | |
375 | { | |
376 | int label1 = gen_new_label(); | |
377 | int label2 = gen_new_label(); | |
378 | tcg_gen_brcond_i32(cond, t1, t0, label1); | |
379 | gen_clr_t(); | |
380 | tcg_gen_br(label2); | |
381 | gen_set_label(label1); | |
382 | gen_set_t(); | |
383 | gen_set_label(label2); | |
384 | } | |
385 | ||
386 | static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm) | |
387 | { | |
388 | int label1 = gen_new_label(); | |
389 | int label2 = gen_new_label(); | |
390 | tcg_gen_brcondi_i32(cond, t0, imm, label1); | |
391 | gen_clr_t(); | |
392 | tcg_gen_br(label2); | |
393 | gen_set_label(label1); | |
394 | gen_set_t(); | |
395 | gen_set_label(label2); | |
396 | } | |
397 | ||
1000822b AJ |
398 | static inline void gen_store_flags(uint32_t flags) |
399 | { | |
400 | tcg_gen_andi_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE); | |
401 | tcg_gen_ori_i32(cpu_flags, cpu_flags, flags); | |
402 | } | |
403 | ||
69d6275b AJ |
404 | static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1) |
405 | { | |
a7812ae4 | 406 | TCGv tmp = tcg_temp_new(); |
69d6275b AJ |
407 | |
408 | p0 &= 0x1f; | |
409 | p1 &= 0x1f; | |
410 | ||
411 | tcg_gen_andi_i32(tmp, t1, (1 << p1)); | |
412 | tcg_gen_andi_i32(t0, t0, ~(1 << p0)); | |
413 | if (p0 < p1) | |
414 | tcg_gen_shri_i32(tmp, tmp, p1 - p0); | |
415 | else if (p0 > p1) | |
416 | tcg_gen_shli_i32(tmp, tmp, p0 - p1); | |
417 | tcg_gen_or_i32(t0, t0, tmp); | |
418 | ||
419 | tcg_temp_free(tmp); | |
420 | } | |
421 | ||
a7812ae4 | 422 | static inline void gen_load_fpr64(TCGv_i64 t, int reg) |
cc4ba6a9 | 423 | { |
66ba317c | 424 | tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]); |
cc4ba6a9 AJ |
425 | } |
426 | ||
a7812ae4 | 427 | static inline void gen_store_fpr64 (TCGv_i64 t, int reg) |
cc4ba6a9 | 428 | { |
a7812ae4 | 429 | TCGv_i32 tmp = tcg_temp_new_i32(); |
cc4ba6a9 | 430 | tcg_gen_trunc_i64_i32(tmp, t); |
66ba317c | 431 | tcg_gen_mov_i32(cpu_fregs[reg + 1], tmp); |
cc4ba6a9 AJ |
432 | tcg_gen_shri_i64(t, t, 32); |
433 | tcg_gen_trunc_i64_i32(tmp, t); | |
66ba317c | 434 | tcg_gen_mov_i32(cpu_fregs[reg], tmp); |
a7812ae4 | 435 | tcg_temp_free_i32(tmp); |
cc4ba6a9 AJ |
436 | } |
437 | ||
fdf9b3e8 FB |
438 | #define B3_0 (ctx->opcode & 0xf) |
439 | #define B6_4 ((ctx->opcode >> 4) & 0x7) | |
440 | #define B7_4 ((ctx->opcode >> 4) & 0xf) | |
441 | #define B7_0 (ctx->opcode & 0xff) | |
442 | #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff)) | |
443 | #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \ | |
444 | (ctx->opcode & 0xfff)) | |
445 | #define B11_8 ((ctx->opcode >> 8) & 0xf) | |
446 | #define B15_12 ((ctx->opcode >> 12) & 0xf) | |
447 | ||
448 | #define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \ | |
7efbe241 | 449 | (cpu_gregs[x + 16]) : (cpu_gregs[x])) |
fdf9b3e8 FB |
450 | |
451 | #define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \ | |
7efbe241 | 452 | ? (cpu_gregs[x + 16]) : (cpu_gregs[x])) |
fdf9b3e8 | 453 | |
eda9b09b | 454 | #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x)) |
f09111e0 | 455 | #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) |
eda9b09b | 456 | #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x)) |
ea6cf6be | 457 | #define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */ |
eda9b09b | 458 | |
fdf9b3e8 | 459 | #define CHECK_NOT_DELAY_SLOT \ |
d8299bcc AJ |
460 | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \ |
461 | { \ | |
462 | tcg_gen_movi_i32(cpu_pc, ctx->pc-2); \ | |
463 | gen_helper_raise_slot_illegal_instruction(); \ | |
464 | ctx->bstate = BS_EXCP; \ | |
465 | return; \ | |
466 | } | |
fdf9b3e8 | 467 | |
fe25591e AJ |
468 | #define CHECK_PRIVILEGED \ |
469 | if (IS_USER(ctx)) { \ | |
d8299bcc | 470 | tcg_gen_movi_i32(cpu_pc, ctx->pc); \ |
a7812ae4 | 471 | gen_helper_raise_illegal_instruction(); \ |
fe25591e AJ |
472 | ctx->bstate = BS_EXCP; \ |
473 | return; \ | |
474 | } | |
475 | ||
d8299bcc AJ |
476 | #define CHECK_FPU_ENABLED \ |
477 | if (ctx->flags & SR_FD) { \ | |
478 | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \ | |
479 | tcg_gen_movi_i32(cpu_pc, ctx->pc-2); \ | |
480 | gen_helper_raise_slot_fpu_disable(); \ | |
481 | } else { \ | |
482 | tcg_gen_movi_i32(cpu_pc, ctx->pc); \ | |
483 | gen_helper_raise_fpu_disable(); \ | |
484 | } \ | |
485 | ctx->bstate = BS_EXCP; \ | |
486 | return; \ | |
487 | } | |
488 | ||
b1d8e52e | 489 | static void _decode_opc(DisasContext * ctx) |
fdf9b3e8 FB |
490 | { |
491 | #if 0 | |
492 | fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode); | |
493 | #endif | |
f6198371 | 494 | |
fdf9b3e8 FB |
495 | switch (ctx->opcode) { |
496 | case 0x0019: /* div0u */ | |
3a8a44c4 | 497 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T)); |
fdf9b3e8 FB |
498 | return; |
499 | case 0x000b: /* rts */ | |
1000822b AJ |
500 | CHECK_NOT_DELAY_SLOT |
501 | tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr); | |
fdf9b3e8 FB |
502 | ctx->flags |= DELAY_SLOT; |
503 | ctx->delayed_pc = (uint32_t) - 1; | |
504 | return; | |
505 | case 0x0028: /* clrmac */ | |
3a8a44c4 AJ |
506 | tcg_gen_movi_i32(cpu_mach, 0); |
507 | tcg_gen_movi_i32(cpu_macl, 0); | |
fdf9b3e8 FB |
508 | return; |
509 | case 0x0048: /* clrs */ | |
3a8a44c4 | 510 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S); |
fdf9b3e8 FB |
511 | return; |
512 | case 0x0008: /* clrt */ | |
a4625612 | 513 | gen_clr_t(); |
fdf9b3e8 FB |
514 | return; |
515 | case 0x0038: /* ldtlb */ | |
fe25591e | 516 | CHECK_PRIVILEGED |
a7812ae4 | 517 | gen_helper_ldtlb(); |
fdf9b3e8 | 518 | return; |
c5e814b2 | 519 | case 0x002b: /* rte */ |
fe25591e | 520 | CHECK_PRIVILEGED |
1000822b AJ |
521 | CHECK_NOT_DELAY_SLOT |
522 | tcg_gen_mov_i32(cpu_sr, cpu_ssr); | |
523 | tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc); | |
fdf9b3e8 FB |
524 | ctx->flags |= DELAY_SLOT; |
525 | ctx->delayed_pc = (uint32_t) - 1; | |
526 | return; | |
527 | case 0x0058: /* sets */ | |
3a8a44c4 | 528 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S); |
fdf9b3e8 FB |
529 | return; |
530 | case 0x0018: /* sett */ | |
a4625612 | 531 | gen_set_t(); |
fdf9b3e8 | 532 | return; |
24988dc2 | 533 | case 0xfbfd: /* frchg */ |
6f06939b | 534 | tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR); |
823029f9 | 535 | ctx->bstate = BS_STOP; |
fdf9b3e8 | 536 | return; |
24988dc2 | 537 | case 0xf3fd: /* fschg */ |
6f06939b | 538 | tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ); |
823029f9 | 539 | ctx->bstate = BS_STOP; |
fdf9b3e8 FB |
540 | return; |
541 | case 0x0009: /* nop */ | |
542 | return; | |
543 | case 0x001b: /* sleep */ | |
fe25591e | 544 | CHECK_PRIVILEGED |
a7812ae4 | 545 | gen_helper_sleep(tcg_const_i32(ctx->pc + 2)); |
fdf9b3e8 FB |
546 | return; |
547 | } | |
548 | ||
549 | switch (ctx->opcode & 0xf000) { | |
550 | case 0x1000: /* mov.l Rm,@(disp,Rn) */ | |
c55497ec | 551 | { |
a7812ae4 | 552 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
553 | tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4); |
554 | tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); | |
555 | tcg_temp_free(addr); | |
556 | } | |
fdf9b3e8 FB |
557 | return; |
558 | case 0x5000: /* mov.l @(disp,Rm),Rn */ | |
c55497ec | 559 | { |
a7812ae4 | 560 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
561 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4); |
562 | tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); | |
563 | tcg_temp_free(addr); | |
564 | } | |
fdf9b3e8 | 565 | return; |
24988dc2 | 566 | case 0xe000: /* mov #imm,Rn */ |
7efbe241 | 567 | tcg_gen_movi_i32(REG(B11_8), B7_0s); |
fdf9b3e8 FB |
568 | return; |
569 | case 0x9000: /* mov.w @(disp,PC),Rn */ | |
c55497ec AJ |
570 | { |
571 | TCGv addr = tcg_const_i32(ctx->pc + 4 + B7_0 * 2); | |
572 | tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx); | |
573 | tcg_temp_free(addr); | |
574 | } | |
fdf9b3e8 FB |
575 | return; |
576 | case 0xd000: /* mov.l @(disp,PC),Rn */ | |
c55497ec AJ |
577 | { |
578 | TCGv addr = tcg_const_i32((ctx->pc + 4 + B7_0 * 4) & ~3); | |
579 | tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); | |
580 | tcg_temp_free(addr); | |
581 | } | |
fdf9b3e8 | 582 | return; |
24988dc2 | 583 | case 0x7000: /* add #imm,Rn */ |
7efbe241 | 584 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), B7_0s); |
fdf9b3e8 FB |
585 | return; |
586 | case 0xa000: /* bra disp */ | |
587 | CHECK_NOT_DELAY_SLOT | |
1000822b AJ |
588 | ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2; |
589 | tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc); | |
fdf9b3e8 FB |
590 | ctx->flags |= DELAY_SLOT; |
591 | return; | |
592 | case 0xb000: /* bsr disp */ | |
593 | CHECK_NOT_DELAY_SLOT | |
1000822b AJ |
594 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4); |
595 | ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2; | |
596 | tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc); | |
fdf9b3e8 FB |
597 | ctx->flags |= DELAY_SLOT; |
598 | return; | |
599 | } | |
600 | ||
601 | switch (ctx->opcode & 0xf00f) { | |
602 | case 0x6003: /* mov Rm,Rn */ | |
7efbe241 | 603 | tcg_gen_mov_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
604 | return; |
605 | case 0x2000: /* mov.b Rm,@Rn */ | |
7efbe241 | 606 | tcg_gen_qemu_st8(REG(B7_4), REG(B11_8), ctx->memidx); |
fdf9b3e8 FB |
607 | return; |
608 | case 0x2001: /* mov.w Rm,@Rn */ | |
7efbe241 | 609 | tcg_gen_qemu_st16(REG(B7_4), REG(B11_8), ctx->memidx); |
fdf9b3e8 FB |
610 | return; |
611 | case 0x2002: /* mov.l Rm,@Rn */ | |
7efbe241 | 612 | tcg_gen_qemu_st32(REG(B7_4), REG(B11_8), ctx->memidx); |
fdf9b3e8 FB |
613 | return; |
614 | case 0x6000: /* mov.b @Rm,Rn */ | |
7efbe241 | 615 | tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx); |
fdf9b3e8 FB |
616 | return; |
617 | case 0x6001: /* mov.w @Rm,Rn */ | |
7efbe241 | 618 | tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx); |
fdf9b3e8 FB |
619 | return; |
620 | case 0x6002: /* mov.l @Rm,Rn */ | |
7efbe241 | 621 | tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx); |
fdf9b3e8 FB |
622 | return; |
623 | case 0x2004: /* mov.b Rm,@-Rn */ | |
c55497ec | 624 | { |
a7812ae4 | 625 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
626 | tcg_gen_subi_i32(addr, REG(B11_8), 1); |
627 | tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); /* might cause re-execution */ | |
628 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); /* modify register status */ | |
629 | tcg_temp_free(addr); | |
630 | } | |
fdf9b3e8 FB |
631 | return; |
632 | case 0x2005: /* mov.w Rm,@-Rn */ | |
c55497ec | 633 | { |
a7812ae4 | 634 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
635 | tcg_gen_subi_i32(addr, REG(B11_8), 2); |
636 | tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx); | |
637 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 2); | |
638 | tcg_temp_free(addr); | |
639 | } | |
fdf9b3e8 FB |
640 | return; |
641 | case 0x2006: /* mov.l Rm,@-Rn */ | |
c55497ec | 642 | { |
a7812ae4 | 643 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
644 | tcg_gen_subi_i32(addr, REG(B11_8), 4); |
645 | tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); | |
646 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); | |
647 | } | |
fdf9b3e8 | 648 | return; |
eda9b09b | 649 | case 0x6004: /* mov.b @Rm+,Rn */ |
7efbe241 | 650 | tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx); |
24988dc2 | 651 | if ( B11_8 != B7_4 ) |
7efbe241 | 652 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1); |
fdf9b3e8 FB |
653 | return; |
654 | case 0x6005: /* mov.w @Rm+,Rn */ | |
7efbe241 | 655 | tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx); |
24988dc2 | 656 | if ( B11_8 != B7_4 ) |
7efbe241 | 657 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); |
fdf9b3e8 FB |
658 | return; |
659 | case 0x6006: /* mov.l @Rm+,Rn */ | |
7efbe241 | 660 | tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx); |
24988dc2 | 661 | if ( B11_8 != B7_4 ) |
7efbe241 | 662 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); |
fdf9b3e8 FB |
663 | return; |
664 | case 0x0004: /* mov.b Rm,@(R0,Rn) */ | |
c55497ec | 665 | { |
a7812ae4 | 666 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
667 | tcg_gen_add_i32(addr, REG(B11_8), REG(0)); |
668 | tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); | |
669 | tcg_temp_free(addr); | |
670 | } | |
fdf9b3e8 FB |
671 | return; |
672 | case 0x0005: /* mov.w Rm,@(R0,Rn) */ | |
c55497ec | 673 | { |
a7812ae4 | 674 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
675 | tcg_gen_add_i32(addr, REG(B11_8), REG(0)); |
676 | tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx); | |
677 | tcg_temp_free(addr); | |
678 | } | |
fdf9b3e8 FB |
679 | return; |
680 | case 0x0006: /* mov.l Rm,@(R0,Rn) */ | |
c55497ec | 681 | { |
a7812ae4 | 682 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
683 | tcg_gen_add_i32(addr, REG(B11_8), REG(0)); |
684 | tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); | |
685 | tcg_temp_free(addr); | |
686 | } | |
fdf9b3e8 FB |
687 | return; |
688 | case 0x000c: /* mov.b @(R0,Rm),Rn */ | |
c55497ec | 689 | { |
a7812ae4 | 690 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
691 | tcg_gen_add_i32(addr, REG(B7_4), REG(0)); |
692 | tcg_gen_qemu_ld8s(REG(B11_8), addr, ctx->memidx); | |
693 | tcg_temp_free(addr); | |
694 | } | |
fdf9b3e8 FB |
695 | return; |
696 | case 0x000d: /* mov.w @(R0,Rm),Rn */ | |
c55497ec | 697 | { |
a7812ae4 | 698 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
699 | tcg_gen_add_i32(addr, REG(B7_4), REG(0)); |
700 | tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx); | |
701 | tcg_temp_free(addr); | |
702 | } | |
fdf9b3e8 FB |
703 | return; |
704 | case 0x000e: /* mov.l @(R0,Rm),Rn */ | |
c55497ec | 705 | { |
a7812ae4 | 706 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
707 | tcg_gen_add_i32(addr, REG(B7_4), REG(0)); |
708 | tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); | |
709 | tcg_temp_free(addr); | |
710 | } | |
fdf9b3e8 FB |
711 | return; |
712 | case 0x6008: /* swap.b Rm,Rn */ | |
c55497ec | 713 | { |
c69e3264 | 714 | TCGv highw, high, low; |
a7812ae4 | 715 | highw = tcg_temp_new(); |
c69e3264 | 716 | tcg_gen_andi_i32(highw, REG(B7_4), 0xffff0000); |
a7812ae4 | 717 | high = tcg_temp_new(); |
c55497ec AJ |
718 | tcg_gen_ext8u_i32(high, REG(B7_4)); |
719 | tcg_gen_shli_i32(high, high, 8); | |
a7812ae4 | 720 | low = tcg_temp_new(); |
c55497ec AJ |
721 | tcg_gen_shri_i32(low, REG(B7_4), 8); |
722 | tcg_gen_ext8u_i32(low, low); | |
723 | tcg_gen_or_i32(REG(B11_8), high, low); | |
c69e3264 | 724 | tcg_gen_or_i32(REG(B11_8), REG(B11_8), highw); |
c55497ec AJ |
725 | tcg_temp_free(low); |
726 | tcg_temp_free(high); | |
727 | } | |
fdf9b3e8 FB |
728 | return; |
729 | case 0x6009: /* swap.w Rm,Rn */ | |
c55497ec AJ |
730 | { |
731 | TCGv high, low; | |
a7812ae4 | 732 | high = tcg_temp_new(); |
c55497ec AJ |
733 | tcg_gen_ext16u_i32(high, REG(B7_4)); |
734 | tcg_gen_shli_i32(high, high, 16); | |
a7812ae4 | 735 | low = tcg_temp_new(); |
c55497ec AJ |
736 | tcg_gen_shri_i32(low, REG(B7_4), 16); |
737 | tcg_gen_ext16u_i32(low, low); | |
738 | tcg_gen_or_i32(REG(B11_8), high, low); | |
739 | tcg_temp_free(low); | |
740 | tcg_temp_free(high); | |
741 | } | |
fdf9b3e8 FB |
742 | return; |
743 | case 0x200d: /* xtrct Rm,Rn */ | |
c55497ec AJ |
744 | { |
745 | TCGv high, low; | |
a7812ae4 | 746 | high = tcg_temp_new(); |
c55497ec AJ |
747 | tcg_gen_ext16u_i32(high, REG(B7_4)); |
748 | tcg_gen_shli_i32(high, high, 16); | |
a7812ae4 | 749 | low = tcg_temp_new(); |
c55497ec AJ |
750 | tcg_gen_shri_i32(low, REG(B11_8), 16); |
751 | tcg_gen_ext16u_i32(low, low); | |
752 | tcg_gen_or_i32(REG(B11_8), high, low); | |
753 | tcg_temp_free(low); | |
754 | tcg_temp_free(high); | |
755 | } | |
fdf9b3e8 FB |
756 | return; |
757 | case 0x300c: /* add Rm,Rn */ | |
7efbe241 | 758 | tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
759 | return; |
760 | case 0x300e: /* addc Rm,Rn */ | |
a7812ae4 | 761 | gen_helper_addc(REG(B11_8), REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
762 | return; |
763 | case 0x300f: /* addv Rm,Rn */ | |
a7812ae4 | 764 | gen_helper_addv(REG(B11_8), REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
765 | return; |
766 | case 0x2009: /* and Rm,Rn */ | |
7efbe241 | 767 | tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
768 | return; |
769 | case 0x3000: /* cmp/eq Rm,Rn */ | |
7efbe241 | 770 | gen_cmp(TCG_COND_EQ, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
771 | return; |
772 | case 0x3003: /* cmp/ge Rm,Rn */ | |
7efbe241 | 773 | gen_cmp(TCG_COND_GE, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
774 | return; |
775 | case 0x3007: /* cmp/gt Rm,Rn */ | |
7efbe241 | 776 | gen_cmp(TCG_COND_GT, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
777 | return; |
778 | case 0x3006: /* cmp/hi Rm,Rn */ | |
7efbe241 | 779 | gen_cmp(TCG_COND_GTU, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
780 | return; |
781 | case 0x3002: /* cmp/hs Rm,Rn */ | |
7efbe241 | 782 | gen_cmp(TCG_COND_GEU, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
783 | return; |
784 | case 0x200c: /* cmp/str Rm,Rn */ | |
69d6275b AJ |
785 | { |
786 | int label1 = gen_new_label(); | |
787 | int label2 = gen_new_label(); | |
c55497ec AJ |
788 | TCGv cmp1 = tcg_temp_local_new(TCG_TYPE_I32); |
789 | TCGv cmp2 = tcg_temp_local_new(TCG_TYPE_I32); | |
790 | tcg_gen_xor_i32(cmp1, REG(B7_4), REG(B11_8)); | |
791 | tcg_gen_andi_i32(cmp2, cmp1, 0xff000000); | |
792 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1); | |
793 | tcg_gen_andi_i32(cmp2, cmp1, 0x00ff0000); | |
794 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1); | |
795 | tcg_gen_andi_i32(cmp2, cmp1, 0x0000ff00); | |
796 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1); | |
797 | tcg_gen_andi_i32(cmp2, cmp1, 0x000000ff); | |
798 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1); | |
69d6275b AJ |
799 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); |
800 | tcg_gen_br(label2); | |
801 | gen_set_label(label1); | |
802 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T); | |
803 | gen_set_label(label2); | |
c55497ec AJ |
804 | tcg_temp_free(cmp2); |
805 | tcg_temp_free(cmp1); | |
69d6275b | 806 | } |
fdf9b3e8 FB |
807 | return; |
808 | case 0x2007: /* div0s Rm,Rn */ | |
c55497ec AJ |
809 | { |
810 | gen_copy_bit_i32(cpu_sr, 8, REG(B11_8), 31); /* SR_Q */ | |
811 | gen_copy_bit_i32(cpu_sr, 9, REG(B7_4), 31); /* SR_M */ | |
a7812ae4 | 812 | TCGv val = tcg_temp_new(); |
c55497ec AJ |
813 | tcg_gen_xor_i32(val, REG(B7_4), REG(B11_8)); |
814 | gen_copy_bit_i32(cpu_sr, 0, val, 31); /* SR_T */ | |
815 | tcg_temp_free(val); | |
816 | } | |
fdf9b3e8 FB |
817 | return; |
818 | case 0x3004: /* div1 Rm,Rn */ | |
a7812ae4 | 819 | gen_helper_div1(REG(B11_8), REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
820 | return; |
821 | case 0x300d: /* dmuls.l Rm,Rn */ | |
6f06939b | 822 | { |
a7812ae4 PB |
823 | TCGv_i64 tmp1 = tcg_temp_new_i64(); |
824 | TCGv_i64 tmp2 = tcg_temp_new_i64(); | |
6f06939b | 825 | |
7efbe241 AJ |
826 | tcg_gen_ext_i32_i64(tmp1, REG(B7_4)); |
827 | tcg_gen_ext_i32_i64(tmp2, REG(B11_8)); | |
6f06939b AJ |
828 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
829 | tcg_gen_trunc_i64_i32(cpu_macl, tmp1); | |
830 | tcg_gen_shri_i64(tmp1, tmp1, 32); | |
831 | tcg_gen_trunc_i64_i32(cpu_mach, tmp1); | |
832 | ||
a7812ae4 PB |
833 | tcg_temp_free_i64(tmp2); |
834 | tcg_temp_free_i64(tmp1); | |
6f06939b | 835 | } |
fdf9b3e8 FB |
836 | return; |
837 | case 0x3005: /* dmulu.l Rm,Rn */ | |
6f06939b | 838 | { |
a7812ae4 PB |
839 | TCGv_i64 tmp1 = tcg_temp_new_i64(); |
840 | TCGv_i64 tmp2 = tcg_temp_new_i64(); | |
6f06939b | 841 | |
7efbe241 AJ |
842 | tcg_gen_extu_i32_i64(tmp1, REG(B7_4)); |
843 | tcg_gen_extu_i32_i64(tmp2, REG(B11_8)); | |
6f06939b AJ |
844 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
845 | tcg_gen_trunc_i64_i32(cpu_macl, tmp1); | |
846 | tcg_gen_shri_i64(tmp1, tmp1, 32); | |
847 | tcg_gen_trunc_i64_i32(cpu_mach, tmp1); | |
848 | ||
a7812ae4 PB |
849 | tcg_temp_free_i64(tmp2); |
850 | tcg_temp_free_i64(tmp1); | |
6f06939b | 851 | } |
fdf9b3e8 FB |
852 | return; |
853 | case 0x600e: /* exts.b Rm,Rn */ | |
7efbe241 | 854 | tcg_gen_ext8s_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
855 | return; |
856 | case 0x600f: /* exts.w Rm,Rn */ | |
7efbe241 | 857 | tcg_gen_ext16s_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
858 | return; |
859 | case 0x600c: /* extu.b Rm,Rn */ | |
7efbe241 | 860 | tcg_gen_ext8u_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
861 | return; |
862 | case 0x600d: /* extu.w Rm,Rn */ | |
7efbe241 | 863 | tcg_gen_ext16u_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 | 864 | return; |
24988dc2 | 865 | case 0x000f: /* mac.l @Rm+,@Rn+ */ |
c55497ec AJ |
866 | { |
867 | TCGv arg0, arg1; | |
a7812ae4 | 868 | arg0 = tcg_temp_new(); |
c55497ec | 869 | tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx); |
a7812ae4 | 870 | arg1 = tcg_temp_new(); |
c55497ec | 871 | tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx); |
a7812ae4 | 872 | gen_helper_macl(arg0, arg1); |
c55497ec AJ |
873 | tcg_temp_free(arg1); |
874 | tcg_temp_free(arg0); | |
875 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); | |
876 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); | |
877 | } | |
fdf9b3e8 FB |
878 | return; |
879 | case 0x400f: /* mac.w @Rm+,@Rn+ */ | |
c55497ec AJ |
880 | { |
881 | TCGv arg0, arg1; | |
a7812ae4 | 882 | arg0 = tcg_temp_new(); |
c55497ec | 883 | tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx); |
a7812ae4 | 884 | arg1 = tcg_temp_new(); |
c55497ec | 885 | tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx); |
a7812ae4 | 886 | gen_helper_macw(arg0, arg1); |
c55497ec AJ |
887 | tcg_temp_free(arg1); |
888 | tcg_temp_free(arg0); | |
889 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2); | |
890 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); | |
891 | } | |
fdf9b3e8 FB |
892 | return; |
893 | case 0x0007: /* mul.l Rm,Rn */ | |
7efbe241 | 894 | tcg_gen_mul_i32(cpu_macl, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
895 | return; |
896 | case 0x200f: /* muls.w Rm,Rn */ | |
c55497ec AJ |
897 | { |
898 | TCGv arg0, arg1; | |
a7812ae4 | 899 | arg0 = tcg_temp_new(); |
c55497ec | 900 | tcg_gen_ext16s_i32(arg0, REG(B7_4)); |
a7812ae4 | 901 | arg1 = tcg_temp_new(); |
c55497ec AJ |
902 | tcg_gen_ext16s_i32(arg1, REG(B11_8)); |
903 | tcg_gen_mul_i32(cpu_macl, arg0, arg1); | |
904 | tcg_temp_free(arg1); | |
905 | tcg_temp_free(arg0); | |
906 | } | |
fdf9b3e8 FB |
907 | return; |
908 | case 0x200e: /* mulu.w Rm,Rn */ | |
c55497ec AJ |
909 | { |
910 | TCGv arg0, arg1; | |
a7812ae4 | 911 | arg0 = tcg_temp_new(); |
c55497ec | 912 | tcg_gen_ext16u_i32(arg0, REG(B7_4)); |
a7812ae4 | 913 | arg1 = tcg_temp_new(); |
c55497ec AJ |
914 | tcg_gen_ext16u_i32(arg1, REG(B11_8)); |
915 | tcg_gen_mul_i32(cpu_macl, arg0, arg1); | |
916 | tcg_temp_free(arg1); | |
917 | tcg_temp_free(arg0); | |
918 | } | |
fdf9b3e8 FB |
919 | return; |
920 | case 0x600b: /* neg Rm,Rn */ | |
7efbe241 | 921 | tcg_gen_neg_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
922 | return; |
923 | case 0x600a: /* negc Rm,Rn */ | |
a7812ae4 | 924 | gen_helper_negc(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
925 | return; |
926 | case 0x6007: /* not Rm,Rn */ | |
7efbe241 | 927 | tcg_gen_not_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
928 | return; |
929 | case 0x200b: /* or Rm,Rn */ | |
7efbe241 | 930 | tcg_gen_or_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
931 | return; |
932 | case 0x400c: /* shad Rm,Rn */ | |
69d6275b AJ |
933 | { |
934 | int label1 = gen_new_label(); | |
935 | int label2 = gen_new_label(); | |
936 | int label3 = gen_new_label(); | |
937 | int label4 = gen_new_label(); | |
c55497ec | 938 | TCGv shift = tcg_temp_local_new(TCG_TYPE_I32); |
7efbe241 | 939 | tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1); |
69d6275b | 940 | /* Rm positive, shift to the left */ |
c55497ec AJ |
941 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); |
942 | tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift); | |
69d6275b AJ |
943 | tcg_gen_br(label4); |
944 | /* Rm negative, shift to the right */ | |
945 | gen_set_label(label1); | |
c55497ec AJ |
946 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); |
947 | tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2); | |
948 | tcg_gen_not_i32(shift, REG(B7_4)); | |
949 | tcg_gen_andi_i32(shift, shift, 0x1f); | |
950 | tcg_gen_addi_i32(shift, shift, 1); | |
951 | tcg_gen_sar_i32(REG(B11_8), REG(B11_8), shift); | |
69d6275b AJ |
952 | tcg_gen_br(label4); |
953 | /* Rm = -32 */ | |
954 | gen_set_label(label2); | |
7efbe241 AJ |
955 | tcg_gen_brcondi_i32(TCG_COND_LT, REG(B11_8), 0, label3); |
956 | tcg_gen_movi_i32(REG(B11_8), 0); | |
69d6275b AJ |
957 | tcg_gen_br(label4); |
958 | gen_set_label(label3); | |
7efbe241 | 959 | tcg_gen_movi_i32(REG(B11_8), 0xffffffff); |
69d6275b | 960 | gen_set_label(label4); |
c55497ec | 961 | tcg_temp_free(shift); |
69d6275b | 962 | } |
fdf9b3e8 FB |
963 | return; |
964 | case 0x400d: /* shld Rm,Rn */ | |
69d6275b AJ |
965 | { |
966 | int label1 = gen_new_label(); | |
967 | int label2 = gen_new_label(); | |
968 | int label3 = gen_new_label(); | |
c55497ec | 969 | TCGv shift = tcg_temp_local_new(TCG_TYPE_I32); |
7efbe241 | 970 | tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1); |
69d6275b | 971 | /* Rm positive, shift to the left */ |
c55497ec AJ |
972 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); |
973 | tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift); | |
69d6275b AJ |
974 | tcg_gen_br(label3); |
975 | /* Rm negative, shift to the right */ | |
976 | gen_set_label(label1); | |
c55497ec AJ |
977 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); |
978 | tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2); | |
979 | tcg_gen_not_i32(shift, REG(B7_4)); | |
980 | tcg_gen_andi_i32(shift, shift, 0x1f); | |
981 | tcg_gen_addi_i32(shift, shift, 1); | |
982 | tcg_gen_shr_i32(REG(B11_8), REG(B11_8), shift); | |
69d6275b AJ |
983 | tcg_gen_br(label3); |
984 | /* Rm = -32 */ | |
985 | gen_set_label(label2); | |
7efbe241 | 986 | tcg_gen_movi_i32(REG(B11_8), 0); |
69d6275b | 987 | gen_set_label(label3); |
c55497ec | 988 | tcg_temp_free(shift); |
69d6275b | 989 | } |
fdf9b3e8 FB |
990 | return; |
991 | case 0x3008: /* sub Rm,Rn */ | |
7efbe241 | 992 | tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
993 | return; |
994 | case 0x300a: /* subc Rm,Rn */ | |
a7812ae4 | 995 | gen_helper_subc(REG(B11_8), REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
996 | return; |
997 | case 0x300b: /* subv Rm,Rn */ | |
a7812ae4 | 998 | gen_helper_subv(REG(B11_8), REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
999 | return; |
1000 | case 0x2008: /* tst Rm,Rn */ | |
c55497ec | 1001 | { |
a7812ae4 | 1002 | TCGv val = tcg_temp_new(); |
c55497ec AJ |
1003 | tcg_gen_and_i32(val, REG(B7_4), REG(B11_8)); |
1004 | gen_cmp_imm(TCG_COND_EQ, val, 0); | |
1005 | tcg_temp_free(val); | |
1006 | } | |
fdf9b3e8 FB |
1007 | return; |
1008 | case 0x200a: /* xor Rm,Rn */ | |
7efbe241 | 1009 | tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
fdf9b3e8 | 1010 | return; |
e67888a7 | 1011 | case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */ |
f6198371 | 1012 | CHECK_FPU_ENABLED |
022a22c7 | 1013 | if (ctx->fpscr & FPSCR_SZ) { |
a7812ae4 | 1014 | TCGv_i64 fp = tcg_temp_new_i64(); |
cc4ba6a9 AJ |
1015 | gen_load_fpr64(fp, XREG(B7_4)); |
1016 | gen_store_fpr64(fp, XREG(B11_8)); | |
a7812ae4 | 1017 | tcg_temp_free_i64(fp); |
eda9b09b | 1018 | } else { |
66ba317c | 1019 | tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
eda9b09b FB |
1020 | } |
1021 | return; | |
e67888a7 | 1022 | case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ |
f6198371 | 1023 | CHECK_FPU_ENABLED |
022a22c7 | 1024 | if (ctx->fpscr & FPSCR_SZ) { |
11bb09f1 AJ |
1025 | TCGv addr_hi = tcg_temp_new(); |
1026 | int fr = XREG(B7_4); | |
1027 | tcg_gen_addi_i32(addr_hi, REG(B11_8), 4); | |
1028 | tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx); | |
1029 | tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx); | |
1030 | tcg_temp_free(addr_hi); | |
eda9b09b | 1031 | } else { |
66ba317c | 1032 | tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx); |
eda9b09b FB |
1033 | } |
1034 | return; | |
e67888a7 | 1035 | case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ |
f6198371 | 1036 | CHECK_FPU_ENABLED |
022a22c7 | 1037 | if (ctx->fpscr & FPSCR_SZ) { |
11bb09f1 AJ |
1038 | TCGv addr_hi = tcg_temp_new(); |
1039 | int fr = XREG(B11_8); | |
1040 | tcg_gen_addi_i32(addr_hi, REG(B7_4), 4); | |
1041 | tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx); | |
1042 | tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx); | |
1043 | tcg_temp_free(addr_hi); | |
eda9b09b | 1044 | } else { |
66ba317c | 1045 | tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx); |
eda9b09b FB |
1046 | } |
1047 | return; | |
e67888a7 | 1048 | case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ |
f6198371 | 1049 | CHECK_FPU_ENABLED |
022a22c7 | 1050 | if (ctx->fpscr & FPSCR_SZ) { |
11bb09f1 AJ |
1051 | TCGv addr_hi = tcg_temp_new(); |
1052 | int fr = XREG(B11_8); | |
1053 | tcg_gen_addi_i32(addr_hi, REG(B7_4), 4); | |
1054 | tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx); | |
1055 | tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx); | |
1056 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8); | |
1057 | tcg_temp_free(addr_hi); | |
eda9b09b | 1058 | } else { |
66ba317c | 1059 | tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx); |
cc4ba6a9 | 1060 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); |
eda9b09b FB |
1061 | } |
1062 | return; | |
e67888a7 | 1063 | case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ |
f6198371 | 1064 | CHECK_FPU_ENABLED |
022a22c7 | 1065 | if (ctx->fpscr & FPSCR_SZ) { |
11bb09f1 AJ |
1066 | TCGv addr = tcg_temp_new_i32(); |
1067 | int fr = XREG(B7_4); | |
1068 | tcg_gen_subi_i32(addr, REG(B11_8), 4); | |
1069 | tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx); | |
cc4ba6a9 | 1070 | tcg_gen_subi_i32(addr, REG(B11_8), 8); |
11bb09f1 AJ |
1071 | tcg_gen_qemu_st32(cpu_fregs[fr ], addr, ctx->memidx); |
1072 | tcg_gen_mov_i32(REG(B11_8), addr); | |
cc4ba6a9 | 1073 | tcg_temp_free(addr); |
eda9b09b | 1074 | } else { |
a7812ae4 | 1075 | TCGv addr; |
a7812ae4 | 1076 | addr = tcg_temp_new_i32(); |
cc4ba6a9 | 1077 | tcg_gen_subi_i32(addr, REG(B11_8), 4); |
66ba317c | 1078 | tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx); |
cc4ba6a9 | 1079 | tcg_temp_free(addr); |
7efbe241 | 1080 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); |
eda9b09b FB |
1081 | } |
1082 | return; | |
e67888a7 | 1083 | case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ |
f6198371 | 1084 | CHECK_FPU_ENABLED |
cc4ba6a9 | 1085 | { |
a7812ae4 | 1086 | TCGv addr = tcg_temp_new_i32(); |
cc4ba6a9 AJ |
1087 | tcg_gen_add_i32(addr, REG(B7_4), REG(0)); |
1088 | if (ctx->fpscr & FPSCR_SZ) { | |
11bb09f1 AJ |
1089 | int fr = XREG(B11_8); |
1090 | tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx); | |
1091 | tcg_gen_addi_i32(addr, addr, 4); | |
1092 | tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx); | |
cc4ba6a9 | 1093 | } else { |
66ba317c | 1094 | tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx); |
cc4ba6a9 AJ |
1095 | } |
1096 | tcg_temp_free(addr); | |
eda9b09b FB |
1097 | } |
1098 | return; | |
e67888a7 | 1099 | case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */ |
f6198371 | 1100 | CHECK_FPU_ENABLED |
cc4ba6a9 | 1101 | { |
a7812ae4 | 1102 | TCGv addr = tcg_temp_new(); |
cc4ba6a9 AJ |
1103 | tcg_gen_add_i32(addr, REG(B11_8), REG(0)); |
1104 | if (ctx->fpscr & FPSCR_SZ) { | |
11bb09f1 AJ |
1105 | int fr = XREG(B7_4); |
1106 | tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx); | |
1107 | tcg_gen_addi_i32(addr, addr, 4); | |
1108 | tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx); | |
cc4ba6a9 | 1109 | } else { |
66ba317c | 1110 | tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx); |
cc4ba6a9 AJ |
1111 | } |
1112 | tcg_temp_free(addr); | |
eda9b09b FB |
1113 | } |
1114 | return; | |
e67888a7 TS |
1115 | case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
1116 | case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ | |
1117 | case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ | |
1118 | case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ | |
1119 | case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ | |
1120 | case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ | |
cc4ba6a9 | 1121 | { |
f6198371 | 1122 | CHECK_FPU_ENABLED |
cc4ba6a9 | 1123 | if (ctx->fpscr & FPSCR_PR) { |
a7812ae4 PB |
1124 | TCGv_i64 fp0, fp1; |
1125 | ||
cc4ba6a9 AJ |
1126 | if (ctx->opcode & 0x0110) |
1127 | break; /* illegal instruction */ | |
a7812ae4 PB |
1128 | fp0 = tcg_temp_new_i64(); |
1129 | fp1 = tcg_temp_new_i64(); | |
cc4ba6a9 AJ |
1130 | gen_load_fpr64(fp0, DREG(B11_8)); |
1131 | gen_load_fpr64(fp1, DREG(B7_4)); | |
a7812ae4 PB |
1132 | switch (ctx->opcode & 0xf00f) { |
1133 | case 0xf000: /* fadd Rm,Rn */ | |
1134 | gen_helper_fadd_DT(fp0, fp0, fp1); | |
1135 | break; | |
1136 | case 0xf001: /* fsub Rm,Rn */ | |
1137 | gen_helper_fsub_DT(fp0, fp0, fp1); | |
1138 | break; | |
1139 | case 0xf002: /* fmul Rm,Rn */ | |
1140 | gen_helper_fmul_DT(fp0, fp0, fp1); | |
1141 | break; | |
1142 | case 0xf003: /* fdiv Rm,Rn */ | |
1143 | gen_helper_fdiv_DT(fp0, fp0, fp1); | |
1144 | break; | |
1145 | case 0xf004: /* fcmp/eq Rm,Rn */ | |
1146 | gen_helper_fcmp_eq_DT(fp0, fp1); | |
1147 | return; | |
1148 | case 0xf005: /* fcmp/gt Rm,Rn */ | |
1149 | gen_helper_fcmp_gt_DT(fp0, fp1); | |
1150 | return; | |
1151 | } | |
1152 | gen_store_fpr64(fp0, DREG(B11_8)); | |
1153 | tcg_temp_free_i64(fp0); | |
1154 | tcg_temp_free_i64(fp1); | |
1155 | } else { | |
a7812ae4 PB |
1156 | switch (ctx->opcode & 0xf00f) { |
1157 | case 0xf000: /* fadd Rm,Rn */ | |
66ba317c | 1158 | gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
a7812ae4 PB |
1159 | break; |
1160 | case 0xf001: /* fsub Rm,Rn */ | |
66ba317c | 1161 | gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
a7812ae4 PB |
1162 | break; |
1163 | case 0xf002: /* fmul Rm,Rn */ | |
66ba317c | 1164 | gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
a7812ae4 PB |
1165 | break; |
1166 | case 0xf003: /* fdiv Rm,Rn */ | |
66ba317c | 1167 | gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
a7812ae4 PB |
1168 | break; |
1169 | case 0xf004: /* fcmp/eq Rm,Rn */ | |
66ba317c | 1170 | gen_helper_fcmp_eq_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
a7812ae4 PB |
1171 | return; |
1172 | case 0xf005: /* fcmp/gt Rm,Rn */ | |
66ba317c | 1173 | gen_helper_fcmp_gt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
a7812ae4 PB |
1174 | return; |
1175 | } | |
cc4ba6a9 | 1176 | } |
ea6cf6be TS |
1177 | } |
1178 | return; | |
fdf9b3e8 FB |
1179 | } |
1180 | ||
1181 | switch (ctx->opcode & 0xff00) { | |
1182 | case 0xc900: /* and #imm,R0 */ | |
7efbe241 | 1183 | tcg_gen_andi_i32(REG(0), REG(0), B7_0); |
fdf9b3e8 | 1184 | return; |
24988dc2 | 1185 | case 0xcd00: /* and.b #imm,@(R0,GBR) */ |
c55497ec AJ |
1186 | { |
1187 | TCGv addr, val; | |
a7812ae4 | 1188 | addr = tcg_temp_new(); |
c55497ec | 1189 | tcg_gen_add_i32(addr, REG(0), cpu_gbr); |
a7812ae4 | 1190 | val = tcg_temp_new(); |
c55497ec AJ |
1191 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
1192 | tcg_gen_andi_i32(val, val, B7_0); | |
1193 | tcg_gen_qemu_st8(val, addr, ctx->memidx); | |
1194 | tcg_temp_free(val); | |
1195 | tcg_temp_free(addr); | |
1196 | } | |
fdf9b3e8 FB |
1197 | return; |
1198 | case 0x8b00: /* bf label */ | |
1199 | CHECK_NOT_DELAY_SLOT | |
1200 | gen_conditional_jump(ctx, ctx->pc + 2, | |
1201 | ctx->pc + 4 + B7_0s * 2); | |
823029f9 | 1202 | ctx->bstate = BS_BRANCH; |
fdf9b3e8 FB |
1203 | return; |
1204 | case 0x8f00: /* bf/s label */ | |
1205 | CHECK_NOT_DELAY_SLOT | |
1000822b | 1206 | gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 0); |
fdf9b3e8 FB |
1207 | ctx->flags |= DELAY_SLOT_CONDITIONAL; |
1208 | return; | |
1209 | case 0x8900: /* bt label */ | |
1210 | CHECK_NOT_DELAY_SLOT | |
1211 | gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2, | |
1212 | ctx->pc + 2); | |
823029f9 | 1213 | ctx->bstate = BS_BRANCH; |
fdf9b3e8 FB |
1214 | return; |
1215 | case 0x8d00: /* bt/s label */ | |
1216 | CHECK_NOT_DELAY_SLOT | |
1000822b | 1217 | gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 1); |
fdf9b3e8 FB |
1218 | ctx->flags |= DELAY_SLOT_CONDITIONAL; |
1219 | return; | |
1220 | case 0x8800: /* cmp/eq #imm,R0 */ | |
7efbe241 | 1221 | gen_cmp_imm(TCG_COND_EQ, REG(0), B7_0s); |
fdf9b3e8 FB |
1222 | return; |
1223 | case 0xc400: /* mov.b @(disp,GBR),R0 */ | |
c55497ec | 1224 | { |
a7812ae4 | 1225 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1226 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0); |
1227 | tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx); | |
1228 | tcg_temp_free(addr); | |
1229 | } | |
fdf9b3e8 FB |
1230 | return; |
1231 | case 0xc500: /* mov.w @(disp,GBR),R0 */ | |
c55497ec | 1232 | { |
a7812ae4 | 1233 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1234 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2); |
1235 | tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx); | |
1236 | tcg_temp_free(addr); | |
1237 | } | |
fdf9b3e8 FB |
1238 | return; |
1239 | case 0xc600: /* mov.l @(disp,GBR),R0 */ | |
c55497ec | 1240 | { |
a7812ae4 | 1241 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1242 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4); |
1243 | tcg_gen_qemu_ld32s(REG(0), addr, ctx->memidx); | |
1244 | tcg_temp_free(addr); | |
1245 | } | |
fdf9b3e8 FB |
1246 | return; |
1247 | case 0xc000: /* mov.b R0,@(disp,GBR) */ | |
c55497ec | 1248 | { |
a7812ae4 | 1249 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1250 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0); |
1251 | tcg_gen_qemu_st8(REG(0), addr, ctx->memidx); | |
1252 | tcg_temp_free(addr); | |
1253 | } | |
fdf9b3e8 FB |
1254 | return; |
1255 | case 0xc100: /* mov.w R0,@(disp,GBR) */ | |
c55497ec | 1256 | { |
a7812ae4 | 1257 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1258 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2); |
1259 | tcg_gen_qemu_st16(REG(0), addr, ctx->memidx); | |
1260 | tcg_temp_free(addr); | |
1261 | } | |
fdf9b3e8 FB |
1262 | return; |
1263 | case 0xc200: /* mov.l R0,@(disp,GBR) */ | |
c55497ec | 1264 | { |
a7812ae4 | 1265 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1266 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4); |
1267 | tcg_gen_qemu_st32(REG(0), addr, ctx->memidx); | |
1268 | tcg_temp_free(addr); | |
1269 | } | |
fdf9b3e8 FB |
1270 | return; |
1271 | case 0x8000: /* mov.b R0,@(disp,Rn) */ | |
c55497ec | 1272 | { |
a7812ae4 | 1273 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1274 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0); |
1275 | tcg_gen_qemu_st8(REG(0), addr, ctx->memidx); | |
1276 | tcg_temp_free(addr); | |
1277 | } | |
fdf9b3e8 FB |
1278 | return; |
1279 | case 0x8100: /* mov.w R0,@(disp,Rn) */ | |
c55497ec | 1280 | { |
a7812ae4 | 1281 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1282 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); |
1283 | tcg_gen_qemu_st16(REG(0), addr, ctx->memidx); | |
1284 | tcg_temp_free(addr); | |
1285 | } | |
fdf9b3e8 FB |
1286 | return; |
1287 | case 0x8400: /* mov.b @(disp,Rn),R0 */ | |
c55497ec | 1288 | { |
a7812ae4 | 1289 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1290 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0); |
1291 | tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx); | |
1292 | tcg_temp_free(addr); | |
1293 | } | |
fdf9b3e8 FB |
1294 | return; |
1295 | case 0x8500: /* mov.w @(disp,Rn),R0 */ | |
c55497ec | 1296 | { |
a7812ae4 | 1297 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1298 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); |
1299 | tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx); | |
1300 | tcg_temp_free(addr); | |
1301 | } | |
fdf9b3e8 FB |
1302 | return; |
1303 | case 0xc700: /* mova @(disp,PC),R0 */ | |
7efbe241 | 1304 | tcg_gen_movi_i32(REG(0), ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3); |
fdf9b3e8 FB |
1305 | return; |
1306 | case 0xcb00: /* or #imm,R0 */ | |
7efbe241 | 1307 | tcg_gen_ori_i32(REG(0), REG(0), B7_0); |
fdf9b3e8 | 1308 | return; |
24988dc2 | 1309 | case 0xcf00: /* or.b #imm,@(R0,GBR) */ |
c55497ec AJ |
1310 | { |
1311 | TCGv addr, val; | |
a7812ae4 | 1312 | addr = tcg_temp_new(); |
c55497ec | 1313 | tcg_gen_add_i32(addr, REG(0), cpu_gbr); |
a7812ae4 | 1314 | val = tcg_temp_new(); |
c55497ec AJ |
1315 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
1316 | tcg_gen_ori_i32(val, val, B7_0); | |
1317 | tcg_gen_qemu_st8(val, addr, ctx->memidx); | |
1318 | tcg_temp_free(val); | |
1319 | tcg_temp_free(addr); | |
1320 | } | |
fdf9b3e8 FB |
1321 | return; |
1322 | case 0xc300: /* trapa #imm */ | |
c55497ec AJ |
1323 | { |
1324 | TCGv imm; | |
1325 | CHECK_NOT_DELAY_SLOT | |
1326 | tcg_gen_movi_i32(cpu_pc, ctx->pc); | |
1327 | imm = tcg_const_i32(B7_0); | |
a7812ae4 | 1328 | gen_helper_trapa(imm); |
c55497ec AJ |
1329 | tcg_temp_free(imm); |
1330 | ctx->bstate = BS_BRANCH; | |
1331 | } | |
fdf9b3e8 FB |
1332 | return; |
1333 | case 0xc800: /* tst #imm,R0 */ | |
c55497ec | 1334 | { |
a7812ae4 | 1335 | TCGv val = tcg_temp_new(); |
c55497ec AJ |
1336 | tcg_gen_andi_i32(val, REG(0), B7_0); |
1337 | gen_cmp_imm(TCG_COND_EQ, val, 0); | |
1338 | tcg_temp_free(val); | |
1339 | } | |
fdf9b3e8 | 1340 | return; |
24988dc2 | 1341 | case 0xcc00: /* tst.b #imm,@(R0,GBR) */ |
c55497ec | 1342 | { |
a7812ae4 | 1343 | TCGv val = tcg_temp_new(); |
c55497ec AJ |
1344 | tcg_gen_add_i32(val, REG(0), cpu_gbr); |
1345 | tcg_gen_qemu_ld8u(val, val, ctx->memidx); | |
1346 | tcg_gen_andi_i32(val, val, B7_0); | |
1347 | gen_cmp_imm(TCG_COND_EQ, val, 0); | |
1348 | tcg_temp_free(val); | |
1349 | } | |
fdf9b3e8 FB |
1350 | return; |
1351 | case 0xca00: /* xor #imm,R0 */ | |
7efbe241 | 1352 | tcg_gen_xori_i32(REG(0), REG(0), B7_0); |
fdf9b3e8 | 1353 | return; |
24988dc2 | 1354 | case 0xce00: /* xor.b #imm,@(R0,GBR) */ |
c55497ec AJ |
1355 | { |
1356 | TCGv addr, val; | |
a7812ae4 | 1357 | addr = tcg_temp_new(); |
c55497ec | 1358 | tcg_gen_add_i32(addr, REG(0), cpu_gbr); |
a7812ae4 | 1359 | val = tcg_temp_new(); |
c55497ec AJ |
1360 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
1361 | tcg_gen_xori_i32(val, val, B7_0); | |
1362 | tcg_gen_qemu_st8(val, addr, ctx->memidx); | |
1363 | tcg_temp_free(val); | |
1364 | tcg_temp_free(addr); | |
1365 | } | |
fdf9b3e8 FB |
1366 | return; |
1367 | } | |
1368 | ||
1369 | switch (ctx->opcode & 0xf08f) { | |
1370 | case 0x408e: /* ldc Rm,Rn_BANK */ | |
fe25591e | 1371 | CHECK_PRIVILEGED |
7efbe241 | 1372 | tcg_gen_mov_i32(ALTREG(B6_4), REG(B11_8)); |
fdf9b3e8 FB |
1373 | return; |
1374 | case 0x4087: /* ldc.l @Rm+,Rn_BANK */ | |
fe25591e | 1375 | CHECK_PRIVILEGED |
7efbe241 AJ |
1376 | tcg_gen_qemu_ld32s(ALTREG(B6_4), REG(B11_8), ctx->memidx); |
1377 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); | |
fdf9b3e8 FB |
1378 | return; |
1379 | case 0x0082: /* stc Rm_BANK,Rn */ | |
fe25591e | 1380 | CHECK_PRIVILEGED |
7efbe241 | 1381 | tcg_gen_mov_i32(REG(B11_8), ALTREG(B6_4)); |
fdf9b3e8 FB |
1382 | return; |
1383 | case 0x4083: /* stc.l Rm_BANK,@-Rn */ | |
fe25591e | 1384 | CHECK_PRIVILEGED |
c55497ec | 1385 | { |
a7812ae4 | 1386 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1387 | tcg_gen_subi_i32(addr, REG(B11_8), 4); |
1388 | tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx); | |
1389 | tcg_temp_free(addr); | |
1390 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); | |
1391 | } | |
fdf9b3e8 FB |
1392 | return; |
1393 | } | |
1394 | ||
1395 | switch (ctx->opcode & 0xf0ff) { | |
1396 | case 0x0023: /* braf Rn */ | |
7efbe241 AJ |
1397 | CHECK_NOT_DELAY_SLOT |
1398 | tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->pc + 4); | |
fdf9b3e8 FB |
1399 | ctx->flags |= DELAY_SLOT; |
1400 | ctx->delayed_pc = (uint32_t) - 1; | |
1401 | return; | |
1402 | case 0x0003: /* bsrf Rn */ | |
7efbe241 | 1403 | CHECK_NOT_DELAY_SLOT |
1000822b | 1404 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4); |
7efbe241 | 1405 | tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr); |
fdf9b3e8 FB |
1406 | ctx->flags |= DELAY_SLOT; |
1407 | ctx->delayed_pc = (uint32_t) - 1; | |
1408 | return; | |
1409 | case 0x4015: /* cmp/pl Rn */ | |
7efbe241 | 1410 | gen_cmp_imm(TCG_COND_GT, REG(B11_8), 0); |
fdf9b3e8 FB |
1411 | return; |
1412 | case 0x4011: /* cmp/pz Rn */ | |
7efbe241 | 1413 | gen_cmp_imm(TCG_COND_GE, REG(B11_8), 0); |
fdf9b3e8 FB |
1414 | return; |
1415 | case 0x4010: /* dt Rn */ | |
7efbe241 AJ |
1416 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); |
1417 | gen_cmp_imm(TCG_COND_EQ, REG(B11_8), 0); | |
fdf9b3e8 FB |
1418 | return; |
1419 | case 0x402b: /* jmp @Rn */ | |
7efbe241 AJ |
1420 | CHECK_NOT_DELAY_SLOT |
1421 | tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); | |
fdf9b3e8 FB |
1422 | ctx->flags |= DELAY_SLOT; |
1423 | ctx->delayed_pc = (uint32_t) - 1; | |
1424 | return; | |
1425 | case 0x400b: /* jsr @Rn */ | |
7efbe241 | 1426 | CHECK_NOT_DELAY_SLOT |
1000822b | 1427 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4); |
7efbe241 | 1428 | tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); |
fdf9b3e8 FB |
1429 | ctx->flags |= DELAY_SLOT; |
1430 | ctx->delayed_pc = (uint32_t) - 1; | |
1431 | return; | |
fe25591e AJ |
1432 | case 0x400e: /* ldc Rm,SR */ |
1433 | CHECK_PRIVILEGED | |
7efbe241 | 1434 | tcg_gen_andi_i32(cpu_sr, REG(B11_8), 0x700083f3); |
390af821 AJ |
1435 | ctx->bstate = BS_STOP; |
1436 | return; | |
fe25591e AJ |
1437 | case 0x4007: /* ldc.l @Rm+,SR */ |
1438 | CHECK_PRIVILEGED | |
c55497ec | 1439 | { |
a7812ae4 | 1440 | TCGv val = tcg_temp_new(); |
c55497ec AJ |
1441 | tcg_gen_qemu_ld32s(val, REG(B11_8), ctx->memidx); |
1442 | tcg_gen_andi_i32(cpu_sr, val, 0x700083f3); | |
1443 | tcg_temp_free(val); | |
1444 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); | |
1445 | ctx->bstate = BS_STOP; | |
1446 | } | |
390af821 | 1447 | return; |
fe25591e AJ |
1448 | case 0x0002: /* stc SR,Rn */ |
1449 | CHECK_PRIVILEGED | |
7efbe241 | 1450 | tcg_gen_mov_i32(REG(B11_8), cpu_sr); |
390af821 | 1451 | return; |
fe25591e AJ |
1452 | case 0x4003: /* stc SR,@-Rn */ |
1453 | CHECK_PRIVILEGED | |
c55497ec | 1454 | { |
a7812ae4 | 1455 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1456 | tcg_gen_subi_i32(addr, REG(B11_8), 4); |
1457 | tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx); | |
1458 | tcg_temp_free(addr); | |
1459 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); | |
1460 | } | |
390af821 | 1461 | return; |
fe25591e | 1462 | #define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \ |
fdf9b3e8 | 1463 | case ldnum: \ |
fe25591e | 1464 | prechk \ |
7efbe241 | 1465 | tcg_gen_mov_i32 (cpu_##reg, REG(B11_8)); \ |
fdf9b3e8 FB |
1466 | return; \ |
1467 | case ldpnum: \ | |
fe25591e | 1468 | prechk \ |
7efbe241 AJ |
1469 | tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx); \ |
1470 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); \ | |
fdf9b3e8 FB |
1471 | return; \ |
1472 | case stnum: \ | |
fe25591e | 1473 | prechk \ |
7efbe241 | 1474 | tcg_gen_mov_i32 (REG(B11_8), cpu_##reg); \ |
fdf9b3e8 FB |
1475 | return; \ |
1476 | case stpnum: \ | |
fe25591e | 1477 | prechk \ |
c55497ec | 1478 | { \ |
a7812ae4 | 1479 | TCGv addr = tcg_temp_new(); \ |
c55497ec AJ |
1480 | tcg_gen_subi_i32(addr, REG(B11_8), 4); \ |
1481 | tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx); \ | |
1482 | tcg_temp_free(addr); \ | |
1483 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); \ | |
86e0abc7 | 1484 | } \ |
fdf9b3e8 | 1485 | return; |
fe25591e AJ |
1486 | LDST(gbr, 0x401e, 0x4017, 0x0012, 0x4013, {}) |
1487 | LDST(vbr, 0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED) | |
1488 | LDST(ssr, 0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED) | |
1489 | LDST(spc, 0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED) | |
1490 | LDST(dbr, 0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED) | |
1491 | LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {}) | |
1492 | LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {}) | |
1493 | LDST(pr, 0x402a, 0x4026, 0x002a, 0x4022, {}) | |
d8299bcc | 1494 | LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {CHECK_FPU_ENABLED}) |
390af821 | 1495 | case 0x406a: /* lds Rm,FPSCR */ |
d8299bcc | 1496 | CHECK_FPU_ENABLED |
a7812ae4 | 1497 | gen_helper_ld_fpscr(REG(B11_8)); |
390af821 AJ |
1498 | ctx->bstate = BS_STOP; |
1499 | return; | |
1500 | case 0x4066: /* lds.l @Rm+,FPSCR */ | |
d8299bcc | 1501 | CHECK_FPU_ENABLED |
c55497ec | 1502 | { |
a7812ae4 | 1503 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1504 | tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx); |
1505 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); | |
a7812ae4 | 1506 | gen_helper_ld_fpscr(addr); |
c55497ec AJ |
1507 | tcg_temp_free(addr); |
1508 | ctx->bstate = BS_STOP; | |
1509 | } | |
390af821 AJ |
1510 | return; |
1511 | case 0x006a: /* sts FPSCR,Rn */ | |
d8299bcc | 1512 | CHECK_FPU_ENABLED |
c55497ec | 1513 | tcg_gen_andi_i32(REG(B11_8), cpu_fpscr, 0x003fffff); |
390af821 AJ |
1514 | return; |
1515 | case 0x4062: /* sts FPSCR,@-Rn */ | |
d8299bcc | 1516 | CHECK_FPU_ENABLED |
c55497ec AJ |
1517 | { |
1518 | TCGv addr, val; | |
a7812ae4 | 1519 | val = tcg_temp_new(); |
c55497ec | 1520 | tcg_gen_andi_i32(val, cpu_fpscr, 0x003fffff); |
a7812ae4 | 1521 | addr = tcg_temp_new(); |
c55497ec AJ |
1522 | tcg_gen_subi_i32(addr, REG(B11_8), 4); |
1523 | tcg_gen_qemu_st32(val, addr, ctx->memidx); | |
1524 | tcg_temp_free(addr); | |
1525 | tcg_temp_free(val); | |
1526 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); | |
1527 | } | |
390af821 | 1528 | return; |
fdf9b3e8 | 1529 | case 0x00c3: /* movca.l R0,@Rm */ |
7efbe241 | 1530 | tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx); |
fdf9b3e8 | 1531 | return; |
7526aa2d AJ |
1532 | case 0x40a9: |
1533 | /* MOVUA.L @Rm,R0 (Rm) -> R0 | |
1534 | Load non-boundary-aligned data */ | |
1535 | tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx); | |
1536 | return; | |
1537 | case 0x40e9: | |
1538 | /* MOVUA.L @Rm+,R0 (Rm) -> R0, Rm + 4 -> Rm | |
1539 | Load non-boundary-aligned data */ | |
1540 | tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx); | |
1541 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); | |
1542 | return; | |
fdf9b3e8 | 1543 | case 0x0029: /* movt Rn */ |
7efbe241 | 1544 | tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T); |
fdf9b3e8 FB |
1545 | return; |
1546 | case 0x0093: /* ocbi @Rn */ | |
c55497ec | 1547 | { |
a7812ae4 | 1548 | TCGv dummy = tcg_temp_new(); |
c55497ec AJ |
1549 | tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); |
1550 | tcg_temp_free(dummy); | |
1551 | } | |
fdf9b3e8 | 1552 | return; |
24988dc2 | 1553 | case 0x00a3: /* ocbp @Rn */ |
c55497ec | 1554 | { |
a7812ae4 | 1555 | TCGv dummy = tcg_temp_new(); |
c55497ec AJ |
1556 | tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); |
1557 | tcg_temp_free(dummy); | |
1558 | } | |
fdf9b3e8 FB |
1559 | return; |
1560 | case 0x00b3: /* ocbwb @Rn */ | |
c55497ec | 1561 | { |
a7812ae4 | 1562 | TCGv dummy = tcg_temp_new(); |
c55497ec AJ |
1563 | tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); |
1564 | tcg_temp_free(dummy); | |
1565 | } | |
fdf9b3e8 FB |
1566 | return; |
1567 | case 0x0083: /* pref @Rn */ | |
1568 | return; | |
71968fa6 AJ |
1569 | case 0x00d3: /* prefi @Rn */ |
1570 | if (ctx->features & SH_FEATURE_SH4A) | |
1571 | return; | |
1572 | else | |
1573 | break; | |
1574 | case 0x00e3: /* icbi @Rn */ | |
1575 | if (ctx->features & SH_FEATURE_SH4A) | |
1576 | return; | |
1577 | else | |
1578 | break; | |
1579 | case 0x00ab: /* synco */ | |
1580 | if (ctx->features & SH_FEATURE_SH4A) | |
1581 | return; | |
1582 | else | |
1583 | break; | |
fdf9b3e8 | 1584 | case 0x4024: /* rotcl Rn */ |
c55497ec | 1585 | { |
a7812ae4 | 1586 | TCGv tmp = tcg_temp_new(); |
c55497ec AJ |
1587 | tcg_gen_mov_i32(tmp, cpu_sr); |
1588 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); | |
1589 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); | |
1590 | gen_copy_bit_i32(REG(B11_8), 0, tmp, 0); | |
1591 | tcg_temp_free(tmp); | |
1592 | } | |
fdf9b3e8 FB |
1593 | return; |
1594 | case 0x4025: /* rotcr Rn */ | |
c55497ec | 1595 | { |
a7812ae4 | 1596 | TCGv tmp = tcg_temp_new(); |
c55497ec AJ |
1597 | tcg_gen_mov_i32(tmp, cpu_sr); |
1598 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); | |
1599 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1); | |
1600 | gen_copy_bit_i32(REG(B11_8), 31, tmp, 0); | |
1601 | tcg_temp_free(tmp); | |
1602 | } | |
fdf9b3e8 FB |
1603 | return; |
1604 | case 0x4004: /* rotl Rn */ | |
7efbe241 AJ |
1605 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); |
1606 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); | |
1607 | gen_copy_bit_i32(REG(B11_8), 0, cpu_sr, 0); | |
fdf9b3e8 FB |
1608 | return; |
1609 | case 0x4005: /* rotr Rn */ | |
7efbe241 AJ |
1610 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1611 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1); | |
1612 | gen_copy_bit_i32(REG(B11_8), 31, cpu_sr, 0); | |
fdf9b3e8 FB |
1613 | return; |
1614 | case 0x4000: /* shll Rn */ | |
1615 | case 0x4020: /* shal Rn */ | |
7efbe241 AJ |
1616 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); |
1617 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); | |
fdf9b3e8 FB |
1618 | return; |
1619 | case 0x4021: /* shar Rn */ | |
7efbe241 AJ |
1620 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1621 | tcg_gen_sari_i32(REG(B11_8), REG(B11_8), 1); | |
fdf9b3e8 FB |
1622 | return; |
1623 | case 0x4001: /* shlr Rn */ | |
7efbe241 AJ |
1624 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1625 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1); | |
fdf9b3e8 FB |
1626 | return; |
1627 | case 0x4008: /* shll2 Rn */ | |
7efbe241 | 1628 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 2); |
fdf9b3e8 FB |
1629 | return; |
1630 | case 0x4018: /* shll8 Rn */ | |
7efbe241 | 1631 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 8); |
fdf9b3e8 FB |
1632 | return; |
1633 | case 0x4028: /* shll16 Rn */ | |
7efbe241 | 1634 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 16); |
fdf9b3e8 FB |
1635 | return; |
1636 | case 0x4009: /* shlr2 Rn */ | |
7efbe241 | 1637 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 2); |
fdf9b3e8 FB |
1638 | return; |
1639 | case 0x4019: /* shlr8 Rn */ | |
7efbe241 | 1640 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 8); |
fdf9b3e8 FB |
1641 | return; |
1642 | case 0x4029: /* shlr16 Rn */ | |
7efbe241 | 1643 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16); |
fdf9b3e8 FB |
1644 | return; |
1645 | case 0x401b: /* tas.b @Rn */ | |
c55497ec AJ |
1646 | { |
1647 | TCGv addr, val; | |
1648 | addr = tcg_temp_local_new(TCG_TYPE_I32); | |
1649 | tcg_gen_mov_i32(addr, REG(B11_8)); | |
1650 | val = tcg_temp_local_new(TCG_TYPE_I32); | |
1651 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); | |
1652 | gen_cmp_imm(TCG_COND_EQ, val, 0); | |
1653 | tcg_gen_ori_i32(val, val, 0x80); | |
1654 | tcg_gen_qemu_st8(val, addr, ctx->memidx); | |
1655 | tcg_temp_free(val); | |
1656 | tcg_temp_free(addr); | |
1657 | } | |
fdf9b3e8 | 1658 | return; |
e67888a7 | 1659 | case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ |
f6198371 AJ |
1660 | CHECK_FPU_ENABLED |
1661 | tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fpul); | |
eda9b09b | 1662 | return; |
e67888a7 | 1663 | case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */ |
f6198371 AJ |
1664 | CHECK_FPU_ENABLED |
1665 | tcg_gen_mov_i32(cpu_fpul, cpu_fregs[FREG(B11_8)]); | |
eda9b09b | 1666 | return; |
e67888a7 | 1667 | case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */ |
f6198371 | 1668 | CHECK_FPU_ENABLED |
ea6cf6be | 1669 | if (ctx->fpscr & FPSCR_PR) { |
a7812ae4 | 1670 | TCGv_i64 fp; |
ea6cf6be TS |
1671 | if (ctx->opcode & 0x0100) |
1672 | break; /* illegal instruction */ | |
a7812ae4 PB |
1673 | fp = tcg_temp_new_i64(); |
1674 | gen_helper_float_DT(fp, cpu_fpul); | |
cc4ba6a9 | 1675 | gen_store_fpr64(fp, DREG(B11_8)); |
a7812ae4 | 1676 | tcg_temp_free_i64(fp); |
ea6cf6be TS |
1677 | } |
1678 | else { | |
66ba317c | 1679 | gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_fpul); |
ea6cf6be TS |
1680 | } |
1681 | return; | |
e67888a7 | 1682 | case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
f6198371 | 1683 | CHECK_FPU_ENABLED |
ea6cf6be | 1684 | if (ctx->fpscr & FPSCR_PR) { |
a7812ae4 | 1685 | TCGv_i64 fp; |
ea6cf6be TS |
1686 | if (ctx->opcode & 0x0100) |
1687 | break; /* illegal instruction */ | |
a7812ae4 | 1688 | fp = tcg_temp_new_i64(); |
cc4ba6a9 | 1689 | gen_load_fpr64(fp, DREG(B11_8)); |
a7812ae4 PB |
1690 | gen_helper_ftrc_DT(cpu_fpul, fp); |
1691 | tcg_temp_free_i64(fp); | |
ea6cf6be TS |
1692 | } |
1693 | else { | |
66ba317c | 1694 | gen_helper_ftrc_FT(cpu_fpul, cpu_fregs[FREG(B11_8)]); |
ea6cf6be TS |
1695 | } |
1696 | return; | |
24988dc2 | 1697 | case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ |
f6198371 | 1698 | CHECK_FPU_ENABLED |
7fdf924f | 1699 | { |
66ba317c | 1700 | gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); |
7fdf924f | 1701 | } |
24988dc2 AJ |
1702 | return; |
1703 | case 0xf05d: /* fabs FRn/DRn */ | |
f6198371 | 1704 | CHECK_FPU_ENABLED |
24988dc2 AJ |
1705 | if (ctx->fpscr & FPSCR_PR) { |
1706 | if (ctx->opcode & 0x0100) | |
1707 | break; /* illegal instruction */ | |
a7812ae4 | 1708 | TCGv_i64 fp = tcg_temp_new_i64(); |
cc4ba6a9 | 1709 | gen_load_fpr64(fp, DREG(B11_8)); |
a7812ae4 | 1710 | gen_helper_fabs_DT(fp, fp); |
cc4ba6a9 | 1711 | gen_store_fpr64(fp, DREG(B11_8)); |
a7812ae4 | 1712 | tcg_temp_free_i64(fp); |
24988dc2 | 1713 | } else { |
66ba317c | 1714 | gen_helper_fabs_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); |
24988dc2 AJ |
1715 | } |
1716 | return; | |
1717 | case 0xf06d: /* fsqrt FRn */ | |
f6198371 | 1718 | CHECK_FPU_ENABLED |
24988dc2 AJ |
1719 | if (ctx->fpscr & FPSCR_PR) { |
1720 | if (ctx->opcode & 0x0100) | |
1721 | break; /* illegal instruction */ | |
a7812ae4 | 1722 | TCGv_i64 fp = tcg_temp_new_i64(); |
cc4ba6a9 | 1723 | gen_load_fpr64(fp, DREG(B11_8)); |
a7812ae4 | 1724 | gen_helper_fsqrt_DT(fp, fp); |
cc4ba6a9 | 1725 | gen_store_fpr64(fp, DREG(B11_8)); |
a7812ae4 | 1726 | tcg_temp_free_i64(fp); |
24988dc2 | 1727 | } else { |
66ba317c | 1728 | gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); |
24988dc2 AJ |
1729 | } |
1730 | return; | |
1731 | case 0xf07d: /* fsrra FRn */ | |
f6198371 | 1732 | CHECK_FPU_ENABLED |
24988dc2 | 1733 | break; |
e67888a7 | 1734 | case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ |
f6198371 | 1735 | CHECK_FPU_ENABLED |
ea6cf6be | 1736 | if (!(ctx->fpscr & FPSCR_PR)) { |
66ba317c | 1737 | tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0); |
ea6cf6be | 1738 | } |
12d96138 | 1739 | return; |
e67888a7 | 1740 | case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ |
f6198371 | 1741 | CHECK_FPU_ENABLED |
ea6cf6be | 1742 | if (!(ctx->fpscr & FPSCR_PR)) { |
66ba317c | 1743 | tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000); |
ea6cf6be | 1744 | } |
12d96138 | 1745 | return; |
24988dc2 | 1746 | case 0xf0ad: /* fcnvsd FPUL,DRn */ |
f6198371 | 1747 | CHECK_FPU_ENABLED |
cc4ba6a9 | 1748 | { |
a7812ae4 PB |
1749 | TCGv_i64 fp = tcg_temp_new_i64(); |
1750 | gen_helper_fcnvsd_FT_DT(fp, cpu_fpul); | |
cc4ba6a9 | 1751 | gen_store_fpr64(fp, DREG(B11_8)); |
a7812ae4 | 1752 | tcg_temp_free_i64(fp); |
cc4ba6a9 | 1753 | } |
24988dc2 AJ |
1754 | return; |
1755 | case 0xf0bd: /* fcnvds DRn,FPUL */ | |
f6198371 | 1756 | CHECK_FPU_ENABLED |
cc4ba6a9 | 1757 | { |
a7812ae4 | 1758 | TCGv_i64 fp = tcg_temp_new_i64(); |
cc4ba6a9 | 1759 | gen_load_fpr64(fp, DREG(B11_8)); |
a7812ae4 PB |
1760 | gen_helper_fcnvds_DT_FT(cpu_fpul, fp); |
1761 | tcg_temp_free_i64(fp); | |
cc4ba6a9 | 1762 | } |
24988dc2 | 1763 | return; |
fdf9b3e8 | 1764 | } |
bacc637a | 1765 | #if 0 |
fdf9b3e8 FB |
1766 | fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n", |
1767 | ctx->opcode, ctx->pc); | |
bacc637a AJ |
1768 | fflush(stderr); |
1769 | #endif | |
a7812ae4 | 1770 | gen_helper_raise_illegal_instruction(); |
823029f9 TS |
1771 | ctx->bstate = BS_EXCP; |
1772 | } | |
1773 | ||
b1d8e52e | 1774 | static void decode_opc(DisasContext * ctx) |
823029f9 TS |
1775 | { |
1776 | uint32_t old_flags = ctx->flags; | |
1777 | ||
1778 | _decode_opc(ctx); | |
1779 | ||
1780 | if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { | |
1781 | if (ctx->flags & DELAY_SLOT_CLEARME) { | |
1000822b | 1782 | gen_store_flags(0); |
274a9e70 AJ |
1783 | } else { |
1784 | /* go out of the delay slot */ | |
1785 | uint32_t new_flags = ctx->flags; | |
1786 | new_flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); | |
1000822b | 1787 | gen_store_flags(new_flags); |
823029f9 TS |
1788 | } |
1789 | ctx->flags = 0; | |
1790 | ctx->bstate = BS_BRANCH; | |
1791 | if (old_flags & DELAY_SLOT_CONDITIONAL) { | |
1792 | gen_delayed_conditional_jump(ctx); | |
1793 | } else if (old_flags & DELAY_SLOT) { | |
1794 | gen_jump(ctx); | |
1795 | } | |
1796 | ||
1797 | } | |
274a9e70 AJ |
1798 | |
1799 | /* go into a delay slot */ | |
1800 | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) | |
1000822b | 1801 | gen_store_flags(ctx->flags); |
fdf9b3e8 FB |
1802 | } |
1803 | ||
2cfc5f17 | 1804 | static inline void |
820e00f2 TS |
1805 | gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb, |
1806 | int search_pc) | |
fdf9b3e8 FB |
1807 | { |
1808 | DisasContext ctx; | |
1809 | target_ulong pc_start; | |
1810 | static uint16_t *gen_opc_end; | |
a1d1bb31 | 1811 | CPUBreakpoint *bp; |
355fb23d | 1812 | int i, ii; |
2e70f6ef PB |
1813 | int num_insns; |
1814 | int max_insns; | |
fdf9b3e8 FB |
1815 | |
1816 | pc_start = tb->pc; | |
fdf9b3e8 | 1817 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
fdf9b3e8 | 1818 | ctx.pc = pc_start; |
823029f9 TS |
1819 | ctx.flags = (uint32_t)tb->flags; |
1820 | ctx.bstate = BS_NONE; | |
fdf9b3e8 | 1821 | ctx.sr = env->sr; |
eda9b09b | 1822 | ctx.fpscr = env->fpscr; |
fdf9b3e8 | 1823 | ctx.memidx = (env->sr & SR_MD) ? 1 : 0; |
9854bc46 PB |
1824 | /* We don't know if the delayed pc came from a dynamic or static branch, |
1825 | so assume it is a dynamic branch. */ | |
823029f9 | 1826 | ctx.delayed_pc = -1; /* use delayed pc from env pointer */ |
fdf9b3e8 FB |
1827 | ctx.tb = tb; |
1828 | ctx.singlestep_enabled = env->singlestep_enabled; | |
71968fa6 | 1829 | ctx.features = env->features; |
fdf9b3e8 FB |
1830 | |
1831 | #ifdef DEBUG_DISAS | |
1832 | if (loglevel & CPU_LOG_TB_CPU) { | |
1833 | fprintf(logfile, | |
1834 | "------------------------------------------------\n"); | |
1835 | cpu_dump_state(env, logfile, fprintf, 0); | |
1836 | } | |
1837 | #endif | |
1838 | ||
355fb23d | 1839 | ii = -1; |
2e70f6ef PB |
1840 | num_insns = 0; |
1841 | max_insns = tb->cflags & CF_COUNT_MASK; | |
1842 | if (max_insns == 0) | |
1843 | max_insns = CF_COUNT_MASK; | |
1844 | gen_icount_start(); | |
823029f9 | 1845 | while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) { |
c0ce998e AL |
1846 | if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) { |
1847 | TAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a1d1bb31 | 1848 | if (ctx.pc == bp->pc) { |
fdf9b3e8 | 1849 | /* We have hit a breakpoint - make sure PC is up-to-date */ |
3a8a44c4 | 1850 | tcg_gen_movi_i32(cpu_pc, ctx.pc); |
a7812ae4 | 1851 | gen_helper_debug(); |
823029f9 | 1852 | ctx.bstate = BS_EXCP; |
fdf9b3e8 FB |
1853 | break; |
1854 | } | |
1855 | } | |
1856 | } | |
355fb23d PB |
1857 | if (search_pc) { |
1858 | i = gen_opc_ptr - gen_opc_buf; | |
1859 | if (ii < i) { | |
1860 | ii++; | |
1861 | while (ii < i) | |
1862 | gen_opc_instr_start[ii++] = 0; | |
1863 | } | |
1864 | gen_opc_pc[ii] = ctx.pc; | |
823029f9 | 1865 | gen_opc_hflags[ii] = ctx.flags; |
355fb23d | 1866 | gen_opc_instr_start[ii] = 1; |
2e70f6ef | 1867 | gen_opc_icount[ii] = num_insns; |
355fb23d | 1868 | } |
2e70f6ef PB |
1869 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
1870 | gen_io_start(); | |
fdf9b3e8 FB |
1871 | #if 0 |
1872 | fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc); | |
1873 | fflush(stderr); | |
1874 | #endif | |
1875 | ctx.opcode = lduw_code(ctx.pc); | |
1876 | decode_opc(&ctx); | |
2e70f6ef | 1877 | num_insns++; |
fdf9b3e8 FB |
1878 | ctx.pc += 2; |
1879 | if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) | |
1880 | break; | |
1881 | if (env->singlestep_enabled) | |
1882 | break; | |
2e70f6ef PB |
1883 | if (num_insns >= max_insns) |
1884 | break; | |
fdf9b3e8 FB |
1885 | #ifdef SH4_SINGLE_STEP |
1886 | break; | |
1887 | #endif | |
1888 | } | |
2e70f6ef PB |
1889 | if (tb->cflags & CF_LAST_IO) |
1890 | gen_io_end(); | |
fdf9b3e8 | 1891 | if (env->singlestep_enabled) { |
bdbf22e6 | 1892 | tcg_gen_movi_i32(cpu_pc, ctx.pc); |
a7812ae4 | 1893 | gen_helper_debug(); |
823029f9 TS |
1894 | } else { |
1895 | switch (ctx.bstate) { | |
1896 | case BS_STOP: | |
1897 | /* gen_op_interrupt_restart(); */ | |
1898 | /* fall through */ | |
1899 | case BS_NONE: | |
1900 | if (ctx.flags) { | |
1000822b | 1901 | gen_store_flags(ctx.flags | DELAY_SLOT_CLEARME); |
823029f9 TS |
1902 | } |
1903 | gen_goto_tb(&ctx, 0, ctx.pc); | |
1904 | break; | |
1905 | case BS_EXCP: | |
1906 | /* gen_op_interrupt_restart(); */ | |
57fec1fe | 1907 | tcg_gen_exit_tb(0); |
823029f9 TS |
1908 | break; |
1909 | case BS_BRANCH: | |
1910 | default: | |
1911 | break; | |
1912 | } | |
fdf9b3e8 | 1913 | } |
823029f9 | 1914 | |
2e70f6ef | 1915 | gen_icount_end(tb, num_insns); |
fdf9b3e8 | 1916 | *gen_opc_ptr = INDEX_op_end; |
355fb23d PB |
1917 | if (search_pc) { |
1918 | i = gen_opc_ptr - gen_opc_buf; | |
1919 | ii++; | |
1920 | while (ii <= i) | |
1921 | gen_opc_instr_start[ii++] = 0; | |
355fb23d PB |
1922 | } else { |
1923 | tb->size = ctx.pc - pc_start; | |
2e70f6ef | 1924 | tb->icount = num_insns; |
355fb23d | 1925 | } |
fdf9b3e8 FB |
1926 | |
1927 | #ifdef DEBUG_DISAS | |
1928 | #ifdef SH4_DEBUG_DISAS | |
1929 | if (loglevel & CPU_LOG_TB_IN_ASM) | |
1930 | fprintf(logfile, "\n"); | |
1931 | #endif | |
1932 | if (loglevel & CPU_LOG_TB_IN_ASM) { | |
1933 | fprintf(logfile, "IN:\n"); /* , lookup_symbol(pc_start)); */ | |
1934 | target_disas(logfile, pc_start, ctx.pc - pc_start, 0); | |
1935 | fprintf(logfile, "\n"); | |
1936 | } | |
fdf9b3e8 | 1937 | #endif |
fdf9b3e8 FB |
1938 | } |
1939 | ||
2cfc5f17 | 1940 | void gen_intermediate_code(CPUState * env, struct TranslationBlock *tb) |
fdf9b3e8 | 1941 | { |
2cfc5f17 | 1942 | gen_intermediate_code_internal(env, tb, 0); |
fdf9b3e8 FB |
1943 | } |
1944 | ||
2cfc5f17 | 1945 | void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb) |
fdf9b3e8 | 1946 | { |
2cfc5f17 | 1947 | gen_intermediate_code_internal(env, tb, 1); |
fdf9b3e8 | 1948 | } |
d2856f1a AJ |
1949 | |
1950 | void gen_pc_load(CPUState *env, TranslationBlock *tb, | |
1951 | unsigned long searched_pc, int pc_pos, void *puc) | |
1952 | { | |
1953 | env->pc = gen_opc_pc[pc_pos]; | |
1954 | env->flags = gen_opc_hflags[pc_pos]; | |
1955 | } |