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Merge branch 'spice.v23.pull' of git://anongit.freedesktop.org/spice/qemu
[qemu.git] / target-sparc / cpu.h
CommitLineData
7a3f1944
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1#ifndef CPU_SPARC_H
2#define CPU_SPARC_H
3
af7bf89b 4#include "config.h"
047b39e4 5#include "qemu-common.h"
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6
7#if !defined(TARGET_SPARC64)
3cf1e035 8#define TARGET_LONG_BITS 32
af7bf89b 9#define TARGET_FPREGS 32
83469015 10#define TARGET_PAGE_BITS 12 /* 4k */
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11#define TARGET_PHYS_ADDR_SPACE_BITS 36
12#define TARGET_VIRT_ADDR_SPACE_BITS 32
13#else
14#define TARGET_LONG_BITS 64
15#define TARGET_FPREGS 64
16#define TARGET_PAGE_BITS 13 /* 8k */
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17#define TARGET_PHYS_ADDR_SPACE_BITS 41
18# ifdef TARGET_ABI32
19# define TARGET_VIRT_ADDR_SPACE_BITS 32
20# else
21# define TARGET_VIRT_ADDR_SPACE_BITS 44
22# endif
af7bf89b 23#endif
3cf1e035 24
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25#define CPUState struct CPUSPARCState
26
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27#include "cpu-defs.h"
28
7a0e1f41
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29#include "softfloat.h"
30
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31#define TARGET_HAS_ICE 1
32
9042c0e2 33#if !defined(TARGET_SPARC64)
0f8a249a 34#define ELF_MACHINE EM_SPARC
9042c0e2 35#else
0f8a249a 36#define ELF_MACHINE EM_SPARCV9
9042c0e2
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37#endif
38
7a3f1944
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39/*#define EXCP_INTERRUPT 0x100*/
40
cf495bcf 41/* trap definitions */
3475187d 42#ifndef TARGET_SPARC64
878d3096 43#define TT_TFAULT 0x01
cf495bcf 44#define TT_ILL_INSN 0x02
e8af50a3 45#define TT_PRIV_INSN 0x03
e80cfcfc 46#define TT_NFPU_INSN 0x04
cf495bcf 47#define TT_WIN_OVF 0x05
5fafdf24 48#define TT_WIN_UNF 0x06
d2889a3e 49#define TT_UNALIGNED 0x07
e8af50a3 50#define TT_FP_EXCP 0x08
878d3096 51#define TT_DFAULT 0x09
e32f879d 52#define TT_TOVF 0x0a
878d3096 53#define TT_EXTINT 0x10
1b2e93c1 54#define TT_CODE_ACCESS 0x21
64a88d5d 55#define TT_UNIMP_FLUSH 0x25
b4f0a316 56#define TT_DATA_ACCESS 0x29
cf495bcf 57#define TT_DIV_ZERO 0x2a
fcc72045 58#define TT_NCP_INSN 0x24
cf495bcf 59#define TT_TRAP 0x80
3475187d 60#else
8194f35a 61#define TT_POWER_ON_RESET 0x01
3475187d 62#define TT_TFAULT 0x08
1b2e93c1 63#define TT_CODE_ACCESS 0x0a
3475187d 64#define TT_ILL_INSN 0x10
64a88d5d 65#define TT_UNIMP_FLUSH TT_ILL_INSN
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66#define TT_PRIV_INSN 0x11
67#define TT_NFPU_INSN 0x20
68#define TT_FP_EXCP 0x21
e32f879d 69#define TT_TOVF 0x23
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70#define TT_CLRWIN 0x24
71#define TT_DIV_ZERO 0x28
72#define TT_DFAULT 0x30
b4f0a316 73#define TT_DATA_ACCESS 0x32
d2889a3e 74#define TT_UNALIGNED 0x34
83469015 75#define TT_PRIV_ACT 0x37
3475187d 76#define TT_EXTINT 0x40
74b9decc 77#define TT_IVEC 0x60
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78#define TT_TMISS 0x64
79#define TT_DMISS 0x68
74b9decc 80#define TT_DPROT 0x6c
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81#define TT_SPILL 0x80
82#define TT_FILL 0xc0
88c8e03f 83#define TT_WOTHER (1 << 5)
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84#define TT_TRAP 0x100
85#endif
7a3f1944 86
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87#define PSR_NEG_SHIFT 23
88#define PSR_NEG (1 << PSR_NEG_SHIFT)
89#define PSR_ZERO_SHIFT 22
90#define PSR_ZERO (1 << PSR_ZERO_SHIFT)
91#define PSR_OVF_SHIFT 21
92#define PSR_OVF (1 << PSR_OVF_SHIFT)
93#define PSR_CARRY_SHIFT 20
94#define PSR_CARRY (1 << PSR_CARRY_SHIFT)
e8af50a3 95#define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
2aae2b8e 96#if !defined(TARGET_SPARC64)
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97#define PSR_EF (1<<12)
98#define PSR_PIL 0xf00
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99#define PSR_S (1<<7)
100#define PSR_PS (1<<6)
101#define PSR_ET (1<<5)
102#define PSR_CWP 0x1f
2aae2b8e 103#endif
e8af50a3 104
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105#define CC_SRC (env->cc_src)
106#define CC_SRC2 (env->cc_src2)
107#define CC_DST (env->cc_dst)
108#define CC_OP (env->cc_op)
109
110enum {
111 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
112 CC_OP_FLAGS, /* all cc are back in status register */
113 CC_OP_DIV, /* modify N, Z and V, C = 0*/
114 CC_OP_ADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
115 CC_OP_ADDX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
116 CC_OP_TADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
117 CC_OP_TADDTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
118 CC_OP_SUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
119 CC_OP_SUBX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
120 CC_OP_TSUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
121 CC_OP_TSUBTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
122 CC_OP_LOGIC, /* modify N and Z, C = V = 0, CC_DST = res */
123 CC_OP_NB,
124};
125
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126/* Trap base register */
127#define TBR_BASE_MASK 0xfffff000
128
3475187d 129#if defined(TARGET_SPARC64)
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130#define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */
131#define PS_IG (1<<11) /* v9, zero on UA2007 */
132#define PS_MG (1<<10) /* v9, zero on UA2007 */
133#define PS_CLE (1<<9) /* UA2007 */
134#define PS_TLE (1<<8) /* UA2007 */
6ef905f6 135#define PS_RMO (1<<7)
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136#define PS_RED (1<<5) /* v9, zero on UA2007 */
137#define PS_PEF (1<<4) /* enable fpu */
138#define PS_AM (1<<3) /* address mask */
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139#define PS_PRIV (1<<2)
140#define PS_IE (1<<1)
5210977a 141#define PS_AG (1<<0) /* v9, zero on UA2007 */
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142
143#define FPRS_FEF (1<<2)
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144
145#define HS_PRIV (1<<2)
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146#endif
147
e8af50a3 148/* Fcc */
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149#define FSR_RD1 (1ULL << 31)
150#define FSR_RD0 (1ULL << 30)
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151#define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
152#define FSR_RD_NEAREST 0
153#define FSR_RD_ZERO FSR_RD0
154#define FSR_RD_POS FSR_RD1
155#define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
156
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157#define FSR_NVM (1ULL << 27)
158#define FSR_OFM (1ULL << 26)
159#define FSR_UFM (1ULL << 25)
160#define FSR_DZM (1ULL << 24)
161#define FSR_NXM (1ULL << 23)
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162#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
163
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164#define FSR_NVA (1ULL << 9)
165#define FSR_OFA (1ULL << 8)
166#define FSR_UFA (1ULL << 7)
167#define FSR_DZA (1ULL << 6)
168#define FSR_NXA (1ULL << 5)
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169#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
170
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171#define FSR_NVC (1ULL << 4)
172#define FSR_OFC (1ULL << 3)
173#define FSR_UFC (1ULL << 2)
174#define FSR_DZC (1ULL << 1)
175#define FSR_NXC (1ULL << 0)
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176#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
177
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178#define FSR_FTT2 (1ULL << 16)
179#define FSR_FTT1 (1ULL << 15)
180#define FSR_FTT0 (1ULL << 14)
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181//gcc warns about constant overflow for ~FSR_FTT_MASK
182//#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
183#ifdef TARGET_SPARC64
184#define FSR_FTT_NMASK 0xfffffffffffe3fffULL
185#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
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186#define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL
187#define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL
188#define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
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189#else
190#define FSR_FTT_NMASK 0xfffe3fffULL
191#define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
3a3b925d 192#define FSR_LDFSR_OLDMASK 0x000fc000ULL
47ad35f1 193#endif
3a3b925d 194#define FSR_LDFSR_MASK 0xcfc00fffULL
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195#define FSR_FTT_IEEE_EXCP (1ULL << 14)
196#define FSR_FTT_UNIMPFPOP (3ULL << 14)
197#define FSR_FTT_SEQ_ERROR (4ULL << 14)
198#define FSR_FTT_INVAL_FPR (6ULL << 14)
e8af50a3 199
4b8b8b76 200#define FSR_FCC1_SHIFT 11
ba6a9d8c 201#define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT)
4b8b8b76 202#define FSR_FCC0_SHIFT 10
ba6a9d8c 203#define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT)
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204
205/* MMU */
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206#define MMU_E (1<<0)
207#define MMU_NF (1<<1)
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208
209#define PTE_ENTRYTYPE_MASK 3
210#define PTE_ACCESS_MASK 0x1c
211#define PTE_ACCESS_SHIFT 2
8d5f07fa 212#define PTE_PPN_SHIFT 7
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213#define PTE_ADDR_MASK 0xffffff00
214
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215#define PG_ACCESSED_BIT 5
216#define PG_MODIFIED_BIT 6
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217#define PG_CACHE_BIT 7
218
219#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
220#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
221#define PG_CACHE_MASK (1 << PG_CACHE_BIT)
222
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223/* 3 <= NWINDOWS <= 32. */
224#define MIN_NWINDOWS 3
225#define MAX_NWINDOWS 32
cf495bcf 226
6f27aba6 227#if !defined(TARGET_SPARC64)
6ebbf390 228#define NB_MMU_MODES 2
6f27aba6 229#else
2065061e 230#define NB_MMU_MODES 6
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231typedef struct trap_state {
232 uint64_t tpc;
233 uint64_t tnpc;
234 uint64_t tstate;
235 uint32_t tt;
236} trap_state;
6f27aba6 237#endif
6ebbf390 238
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239typedef struct sparc_def_t {
240 const char *name;
241 target_ulong iu_version;
242 uint32_t fpu_version;
243 uint32_t mmu_version;
244 uint32_t mmu_bm;
245 uint32_t mmu_ctpr_mask;
246 uint32_t mmu_cxr_mask;
247 uint32_t mmu_sfsr_mask;
248 uint32_t mmu_trcr_mask;
963262de 249 uint32_t mxcc_version;
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250 uint32_t features;
251 uint32_t nwindows;
252 uint32_t maxtl;
253} sparc_def_t;
254
255#define CPU_FEATURE_FLOAT (1 << 0)
256#define CPU_FEATURE_FLOAT128 (1 << 1)
257#define CPU_FEATURE_SWAP (1 << 2)
258#define CPU_FEATURE_MUL (1 << 3)
259#define CPU_FEATURE_DIV (1 << 4)
260#define CPU_FEATURE_FLUSH (1 << 5)
261#define CPU_FEATURE_FSQRT (1 << 6)
262#define CPU_FEATURE_FMUL (1 << 7)
263#define CPU_FEATURE_VIS1 (1 << 8)
264#define CPU_FEATURE_VIS2 (1 << 9)
265#define CPU_FEATURE_FSMULD (1 << 10)
266#define CPU_FEATURE_HYPV (1 << 11)
267#define CPU_FEATURE_CMT (1 << 12)
268#define CPU_FEATURE_GL (1 << 13)
269#ifndef TARGET_SPARC64
270#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
271 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
272 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
273 CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
274#else
275#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
276 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
277 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
278 CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \
279 CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD)
280enum {
281 mmu_us_12, // Ultrasparc < III (64 entry TLB)
282 mmu_us_3, // Ultrasparc III (512 entry TLB)
283 mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages)
284 mmu_sun4v, // T1, T2
285};
286#endif
287
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288#define TTE_VALID_BIT (1ULL << 63)
289#define TTE_USED_BIT (1ULL << 41)
290#define TTE_LOCKED_BIT (1ULL << 6)
2a90358f 291#define TTE_GLOBAL_BIT (1ULL << 0)
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292
293#define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT)
294#define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT)
295#define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT)
2a90358f 296#define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT)
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297
298#define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT)
299#define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
300
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301typedef struct SparcTLBEntry {
302 uint64_t tag;
303 uint64_t tte;
304} SparcTLBEntry;
305
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306struct CPUTimer
307{
308 const char *name;
309 uint32_t frequency;
310 uint32_t disabled;
311 uint64_t disabled_mask;
312 int64_t clock_offset;
313 struct QEMUTimer *qtimer;
314};
315
316typedef struct CPUTimer CPUTimer;
317
318struct QEMUFile;
319void cpu_put_timer(struct QEMUFile *f, CPUTimer *s);
320void cpu_get_timer(struct QEMUFile *f, CPUTimer *s);
321
7a3f1944 322typedef struct CPUSPARCState {
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323 target_ulong gregs[8]; /* general registers */
324 target_ulong *regwptr; /* pointer to current register window */
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325 target_ulong pc; /* program counter */
326 target_ulong npc; /* next program counter */
327 target_ulong y; /* multiply/divide register */
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328
329 /* emulator internal flags handling */
d9bdab86 330 target_ulong cc_src, cc_src2;
dc99a3f2 331 target_ulong cc_dst;
8393617c 332 uint32_t cc_op;
dc99a3f2 333
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334 target_ulong t0, t1; /* temporaries live across basic blocks */
335 target_ulong cond; /* conditional branch result (XXX: save it in a
336 temporary register when possible) */
337
cf495bcf 338 uint32_t psr; /* processor state register */
3475187d 339 target_ulong fsr; /* FPU state register */
7c60cc4b 340 float32 fpr[TARGET_FPREGS]; /* floating point registers */
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341 uint32_t cwp; /* index of current register window (extracted
342 from PSR) */
5210977a 343#if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
cf495bcf 344 uint32_t wim; /* window invalid mask */
5210977a 345#endif
3475187d 346 target_ulong tbr; /* trap base register */
2aae2b8e 347#if !defined(TARGET_SPARC64)
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348 int psrs; /* supervisor mode (extracted from PSR) */
349 int psrps; /* previous supervisor mode */
350 int psret; /* enable traps */
5210977a 351#endif
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352 uint32_t psrpil; /* interrupt blocking level */
353 uint32_t pil_in; /* incoming interrupt level bitmap */
2aae2b8e 354#if !defined(TARGET_SPARC64)
e80cfcfc 355 int psref; /* enable fpu */
2aae2b8e 356#endif
62724a37 357 target_ulong version;
cf495bcf 358 int interrupt_index;
1a14026e 359 uint32_t nwindows;
cf495bcf 360 /* NOTE: we allow 8 more registers to handle wrapping */
1a14026e 361 target_ulong regbase[MAX_NWINDOWS * 16 + 8];
d720b93d 362
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363 CPU_COMMON
364
e8af50a3 365 /* MMU regs */
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366#if defined(TARGET_SPARC64)
367 uint64_t lsu;
368#define DMMU_E 0x8
369#define IMMU_E 0x4
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370 //typedef struct SparcMMU
371 union {
372 uint64_t immuregs[16];
373 struct {
374 uint64_t tsb_tag_target;
375 uint64_t unused_mmu_primary_context; // use DMMU
376 uint64_t unused_mmu_secondary_context; // use DMMU
377 uint64_t sfsr;
378 uint64_t sfar;
379 uint64_t tsb;
380 uint64_t tag_access;
381 } immu;
382 };
383 union {
384 uint64_t dmmuregs[16];
385 struct {
386 uint64_t tsb_tag_target;
387 uint64_t mmu_primary_context;
388 uint64_t mmu_secondary_context;
389 uint64_t sfsr;
390 uint64_t sfar;
391 uint64_t tsb;
392 uint64_t tag_access;
393 } dmmu;
394 };
395 SparcTLBEntry itlb[64];
396 SparcTLBEntry dtlb[64];
fb79ceb9 397 uint32_t mmu_version;
3475187d 398#else
3dd9a152 399 uint32_t mmuregs[32];
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400 uint64_t mxccdata[4];
401 uint64_t mxccregs[8];
4017190e 402 uint64_t mmubpregs[4];
3ebf5aaf 403 uint64_t prom_addr;
3475187d 404#endif
e8af50a3 405 /* temporary float registers */
65ce8c2f 406 float64 dt0, dt1;
1f587329 407 float128 qt0, qt1;
7a0e1f41 408 float_status fp_status;
af7bf89b 409#if defined(TARGET_SPARC64)
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410#define MAXTL_MAX 8
411#define MAXTL_MASK (MAXTL_MAX - 1)
c19148bd 412 trap_state ts[MAXTL_MAX];
0f8a249a 413 uint32_t xcc; /* Extended integer condition codes */
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414 uint32_t asi;
415 uint32_t pstate;
416 uint32_t tl;
c19148bd 417 uint32_t maxtl;
3475187d 418 uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
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419 uint64_t agregs[8]; /* alternate general registers */
420 uint64_t bgregs[8]; /* backup for normal global registers */
421 uint64_t igregs[8]; /* interrupt general registers */
422 uint64_t mgregs[8]; /* mmu general registers */
3475187d 423 uint64_t fprs;
83469015 424 uint64_t tick_cmpr, stick_cmpr;
8f4efc55 425 CPUTimer *tick, *stick;
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426#define TICK_NPT_MASK 0x8000000000000000ULL
427#define TICK_INT_DIS 0x8000000000000000ULL
725cb90b 428 uint64_t gsr;
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429 uint32_t gl; // UA2005
430 /* UA 2005 hyperprivileged registers */
c19148bd 431 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
8f4efc55 432 CPUTimer *hstick; // UA 2005
9d926598 433 uint32_t softint;
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434#define SOFTINT_TIMER 1
435#define SOFTINT_STIMER (1 << 16)
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436#define SOFTINT_INTRMASK (0xFFFE)
437#define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
3475187d 438#endif
5578ceab 439 sparc_def_t *def;
7a3f1944 440} CPUSPARCState;
64a88d5d 441
5a834bb4 442#ifndef NO_CPU_IO_DEFS
91736d37 443/* helper.c */
aaed909a 444CPUSPARCState *cpu_sparc_init(const char *cpu_model);
91736d37 445void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
047b39e4 446void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf);
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447int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
448 int mmu_idx, int is_softmmu);
0b5c1ce8 449#define cpu_handle_mmu_fault cpu_sparc_handle_mmu_fault
48585ec5 450target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
d41160a3 451void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env);
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452
453/* translate.c */
454void gen_intermediate_code_init(CPUSPARCState *env);
455
456/* cpu-exec.c */
457int cpu_sparc_exec(CPUSPARCState *s);
7a3f1944 458
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459/* op_helper.c */
460target_ulong cpu_get_psr(CPUState *env1);
461void cpu_put_psr(CPUState *env1, target_ulong val);
462#ifdef TARGET_SPARC64
463target_ulong cpu_get_ccr(CPUState *env1);
464void cpu_put_ccr(CPUState *env1, target_ulong val);
465target_ulong cpu_get_cwp64(CPUState *env1);
466void cpu_put_cwp64(CPUState *env1, int cwp);
4c6aa085 467#endif
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468int cpu_cwp_inc(CPUState *env1, int cwp);
469int cpu_cwp_dec(CPUState *env1, int cwp);
470void cpu_set_cwp(CPUState *env1, int new_cwp);
1a14026e 471
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472/* sun4m.c, sun4u.c */
473void cpu_check_irqs(CPUSPARCState *env);
1a14026e 474
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475#if defined (TARGET_SPARC64)
476
477static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
478{
479 return (x & mask) == (y & mask);
480}
481
482#define MMU_CONTEXT_BITS 13
483#define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1)
484
485static inline int tlb_compare_context(const SparcTLBEntry *tlb,
486 uint64_t context)
487{
488 return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK);
489}
490
0bbd4a0d 491#endif
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492#endif
493
91736d37 494/* cpu-exec.c */
3c7b48b7 495#if !defined(CONFIG_USER_ONLY)
c227f099 496void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
e18231a3 497 int is_asi, int size);
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498target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
499 int mmu_idx);
500
3c7b48b7 501#endif
f0d5e471 502int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
7a3f1944 503
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504#define cpu_init cpu_sparc_init
505#define cpu_exec cpu_sparc_exec
506#define cpu_gen_code cpu_sparc_gen_code
507#define cpu_signal_handler cpu_sparc_signal_handler
c732abe2 508#define cpu_list sparc_cpu_list
9467d44c 509
8f4efc55 510#define CPU_SAVE_VERSION 6
b3c7724c 511
6ebbf390 512/* MMU modes definitions */
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513#if defined (TARGET_SPARC64)
514#define MMU_USER_IDX 0
6f27aba6 515#define MMU_MODE0_SUFFIX _user
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516#define MMU_USER_SECONDARY_IDX 1
517#define MMU_MODE1_SUFFIX _user_secondary
518#define MMU_KERNEL_IDX 2
519#define MMU_MODE2_SUFFIX _kernel
520#define MMU_KERNEL_SECONDARY_IDX 3
521#define MMU_MODE3_SUFFIX _kernel_secondary
522#define MMU_NUCLEUS_IDX 4
523#define MMU_MODE4_SUFFIX _nucleus
524#define MMU_HYPV_IDX 5
525#define MMU_MODE5_SUFFIX _hypv
526#else
9e31b9e2 527#define MMU_USER_IDX 0
2aae2b8e 528#define MMU_MODE0_SUFFIX _user
9e31b9e2 529#define MMU_KERNEL_IDX 1
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530#define MMU_MODE1_SUFFIX _kernel
531#endif
532
533#if defined (TARGET_SPARC64)
534static inline int cpu_has_hypervisor(CPUState *env1)
535{
536 return env1->def->features & CPU_FEATURE_HYPV;
537}
538
539static inline int cpu_hypervisor_mode(CPUState *env1)
540{
541 return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
542}
543
544static inline int cpu_supervisor_mode(CPUState *env1)
545{
546 return env1->pstate & PS_PRIV;
547}
2065061e 548#endif
9e31b9e2 549
22548760 550static inline int cpu_mmu_index(CPUState *env1)
6ebbf390 551{
6f27aba6 552#if defined(CONFIG_USER_ONLY)
9e31b9e2 553 return MMU_USER_IDX;
6f27aba6 554#elif !defined(TARGET_SPARC64)
22548760 555 return env1->psrs;
6f27aba6 556#else
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557 if (env1->tl > 0) {
558 return MMU_NUCLEUS_IDX;
559 } else if (cpu_hypervisor_mode(env1)) {
9e31b9e2 560 return MMU_HYPV_IDX;
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561 } else if (cpu_supervisor_mode(env1)) {
562 return MMU_KERNEL_IDX;
563 } else {
564 return MMU_USER_IDX;
565 }
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566#endif
567}
568
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569static inline int cpu_interrupts_enabled(CPUState *env1)
570{
571#if !defined (TARGET_SPARC64)
572 if (env1->psret != 0)
573 return 1;
574#else
575 if (env1->pstate & PS_IE)
576 return 1;
577#endif
578
579 return 0;
580}
581
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582static inline int cpu_pil_allowed(CPUState *env1, int pil)
583{
584#if !defined(TARGET_SPARC64)
585 /* level 15 is non-maskable on sparc v8 */
586 return pil == 15 || pil > env1->psrpil;
587#else
588 return pil > env1->psrpil;
589#endif
590}
591
22548760 592static inline int cpu_fpu_enabled(CPUState *env1)
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593{
594#if defined(CONFIG_USER_ONLY)
595 return 1;
596#elif !defined(TARGET_SPARC64)
22548760 597 return env1->psref;
6f27aba6 598#else
22548760 599 return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0);
6f27aba6 600#endif
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601}
602
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603#if defined(CONFIG_USER_ONLY)
604static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
605{
f8ed7070 606 if (newsp)
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607 env->regwptr[22] = newsp;
608 env->regwptr[0] = 0;
609 /* FIXME: Do we also need to clear CF? */
610 /* XXXXX */
611 printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
612}
613#endif
614
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615#include "cpu-all.h"
616
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617#ifdef TARGET_SPARC64
618/* sun4u.c */
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619void cpu_tick_set_count(CPUTimer *timer, uint64_t count);
620uint64_t cpu_tick_get_count(CPUTimer *timer);
621void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
8194f35a 622trap_state* cpu_tsptr(CPUState* env);
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623#endif
624
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625static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
626 target_ulong *cs_base, int *flags)
627{
628 *pc = env->pc;
629 *cs_base = env->npc;
630#ifdef TARGET_SPARC64
631 // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
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632 *flags = ((env->pstate & PS_AM) << 2) /* 5 */
633 | (((env->pstate & PS_PEF) >> 1) /* 3 */
634 | ((env->fprs & FPRS_FEF) << 2)) /* 4 */
635 | (env->pstate & PS_PRIV) /* 2 */
636 | ((env->lsu & (DMMU_E | IMMU_E)) >> 2) /* 1, 0 */
637 | ((env->tl & 0xff) << 8)
638 | (env->dmmu.mmu_primary_context << 16); /* 16... */
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639#else
640 // FPU enable . Supervisor
641 *flags = (env->psref << 4) | env->psrs;
642#endif
643}
644
7a3f1944 645#endif