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Commit | Line | Data |
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7a3f1944 FB |
1 | #ifndef CPU_SPARC_H |
2 | #define CPU_SPARC_H | |
3 | ||
af7bf89b FB |
4 | #include "config.h" |
5 | ||
6 | #if !defined(TARGET_SPARC64) | |
3cf1e035 | 7 | #define TARGET_LONG_BITS 32 |
af7bf89b | 8 | #define TARGET_FPREGS 32 |
83469015 | 9 | #define TARGET_PAGE_BITS 12 /* 4k */ |
af7bf89b FB |
10 | #else |
11 | #define TARGET_LONG_BITS 64 | |
12 | #define TARGET_FPREGS 64 | |
33b37802 | 13 | #define TARGET_PAGE_BITS 13 /* 8k */ |
af7bf89b | 14 | #endif |
3cf1e035 | 15 | |
92b72cbc BS |
16 | #define TARGET_PHYS_ADDR_BITS 64 |
17 | ||
7a3f1944 FB |
18 | #include "cpu-defs.h" |
19 | ||
7a0e1f41 FB |
20 | #include "softfloat.h" |
21 | ||
1fddef4b FB |
22 | #define TARGET_HAS_ICE 1 |
23 | ||
9042c0e2 | 24 | #if !defined(TARGET_SPARC64) |
0f8a249a | 25 | #define ELF_MACHINE EM_SPARC |
9042c0e2 | 26 | #else |
0f8a249a | 27 | #define ELF_MACHINE EM_SPARCV9 |
9042c0e2 TS |
28 | #endif |
29 | ||
7a3f1944 FB |
30 | /*#define EXCP_INTERRUPT 0x100*/ |
31 | ||
cf495bcf | 32 | /* trap definitions */ |
3475187d | 33 | #ifndef TARGET_SPARC64 |
878d3096 | 34 | #define TT_TFAULT 0x01 |
cf495bcf | 35 | #define TT_ILL_INSN 0x02 |
e8af50a3 | 36 | #define TT_PRIV_INSN 0x03 |
e80cfcfc | 37 | #define TT_NFPU_INSN 0x04 |
cf495bcf | 38 | #define TT_WIN_OVF 0x05 |
5fafdf24 | 39 | #define TT_WIN_UNF 0x06 |
d2889a3e | 40 | #define TT_UNALIGNED 0x07 |
e8af50a3 | 41 | #define TT_FP_EXCP 0x08 |
878d3096 | 42 | #define TT_DFAULT 0x09 |
e32f879d | 43 | #define TT_TOVF 0x0a |
878d3096 | 44 | #define TT_EXTINT 0x10 |
1b2e93c1 | 45 | #define TT_CODE_ACCESS 0x21 |
b4f0a316 | 46 | #define TT_DATA_ACCESS 0x29 |
cf495bcf | 47 | #define TT_DIV_ZERO 0x2a |
fcc72045 | 48 | #define TT_NCP_INSN 0x24 |
cf495bcf | 49 | #define TT_TRAP 0x80 |
3475187d FB |
50 | #else |
51 | #define TT_TFAULT 0x08 | |
83469015 | 52 | #define TT_TMISS 0x09 |
1b2e93c1 | 53 | #define TT_CODE_ACCESS 0x0a |
3475187d FB |
54 | #define TT_ILL_INSN 0x10 |
55 | #define TT_PRIV_INSN 0x11 | |
56 | #define TT_NFPU_INSN 0x20 | |
57 | #define TT_FP_EXCP 0x21 | |
e32f879d | 58 | #define TT_TOVF 0x23 |
3475187d FB |
59 | #define TT_CLRWIN 0x24 |
60 | #define TT_DIV_ZERO 0x28 | |
61 | #define TT_DFAULT 0x30 | |
83469015 | 62 | #define TT_DMISS 0x31 |
b4f0a316 BS |
63 | #define TT_DATA_ACCESS 0x32 |
64 | #define TT_DPROT 0x33 | |
d2889a3e | 65 | #define TT_UNALIGNED 0x34 |
83469015 | 66 | #define TT_PRIV_ACT 0x37 |
3475187d FB |
67 | #define TT_EXTINT 0x40 |
68 | #define TT_SPILL 0x80 | |
69 | #define TT_FILL 0xc0 | |
70 | #define TT_WOTHER 0x10 | |
71 | #define TT_TRAP 0x100 | |
72 | #endif | |
7a3f1944 | 73 | |
4b8b8b76 BS |
74 | #define PSR_NEG_SHIFT 23 |
75 | #define PSR_NEG (1 << PSR_NEG_SHIFT) | |
76 | #define PSR_ZERO_SHIFT 22 | |
77 | #define PSR_ZERO (1 << PSR_ZERO_SHIFT) | |
78 | #define PSR_OVF_SHIFT 21 | |
79 | #define PSR_OVF (1 << PSR_OVF_SHIFT) | |
80 | #define PSR_CARRY_SHIFT 20 | |
81 | #define PSR_CARRY (1 << PSR_CARRY_SHIFT) | |
e8af50a3 | 82 | #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) |
e80cfcfc FB |
83 | #define PSR_EF (1<<12) |
84 | #define PSR_PIL 0xf00 | |
e8af50a3 FB |
85 | #define PSR_S (1<<7) |
86 | #define PSR_PS (1<<6) | |
87 | #define PSR_ET (1<<5) | |
88 | #define PSR_CWP 0x1f | |
e8af50a3 FB |
89 | |
90 | /* Trap base register */ | |
91 | #define TBR_BASE_MASK 0xfffff000 | |
92 | ||
3475187d | 93 | #if defined(TARGET_SPARC64) |
83469015 FB |
94 | #define PS_IG (1<<11) |
95 | #define PS_MG (1<<10) | |
6ef905f6 | 96 | #define PS_RMO (1<<7) |
83469015 | 97 | #define PS_RED (1<<5) |
3475187d FB |
98 | #define PS_PEF (1<<4) |
99 | #define PS_AM (1<<3) | |
100 | #define PS_PRIV (1<<2) | |
101 | #define PS_IE (1<<1) | |
83469015 | 102 | #define PS_AG (1<<0) |
a80dde08 FB |
103 | |
104 | #define FPRS_FEF (1<<2) | |
6f27aba6 BS |
105 | |
106 | #define HS_PRIV (1<<2) | |
3475187d FB |
107 | #endif |
108 | ||
e8af50a3 FB |
109 | /* Fcc */ |
110 | #define FSR_RD1 (1<<31) | |
111 | #define FSR_RD0 (1<<30) | |
112 | #define FSR_RD_MASK (FSR_RD1 | FSR_RD0) | |
113 | #define FSR_RD_NEAREST 0 | |
114 | #define FSR_RD_ZERO FSR_RD0 | |
115 | #define FSR_RD_POS FSR_RD1 | |
116 | #define FSR_RD_NEG (FSR_RD1 | FSR_RD0) | |
117 | ||
118 | #define FSR_NVM (1<<27) | |
119 | #define FSR_OFM (1<<26) | |
120 | #define FSR_UFM (1<<25) | |
121 | #define FSR_DZM (1<<24) | |
122 | #define FSR_NXM (1<<23) | |
123 | #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) | |
124 | ||
125 | #define FSR_NVA (1<<9) | |
126 | #define FSR_OFA (1<<8) | |
127 | #define FSR_UFA (1<<7) | |
128 | #define FSR_DZA (1<<6) | |
129 | #define FSR_NXA (1<<5) | |
130 | #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) | |
131 | ||
132 | #define FSR_NVC (1<<4) | |
133 | #define FSR_OFC (1<<3) | |
134 | #define FSR_UFC (1<<2) | |
135 | #define FSR_DZC (1<<1) | |
136 | #define FSR_NXC (1<<0) | |
137 | #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) | |
138 | ||
139 | #define FSR_FTT2 (1<<16) | |
140 | #define FSR_FTT1 (1<<15) | |
141 | #define FSR_FTT0 (1<<14) | |
142 | #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) | |
e80cfcfc FB |
143 | #define FSR_FTT_IEEE_EXCP (1 << 14) |
144 | #define FSR_FTT_UNIMPFPOP (3 << 14) | |
9143e598 | 145 | #define FSR_FTT_SEQ_ERROR (4 << 14) |
e80cfcfc | 146 | #define FSR_FTT_INVAL_FPR (6 << 14) |
e8af50a3 | 147 | |
4b8b8b76 BS |
148 | #define FSR_FCC1_SHIFT 11 |
149 | #define FSR_FCC1 (1 << FSR_FCC1_SHIFT) | |
150 | #define FSR_FCC0_SHIFT 10 | |
151 | #define FSR_FCC0 (1 << FSR_FCC0_SHIFT) | |
e8af50a3 FB |
152 | |
153 | /* MMU */ | |
0f8a249a BS |
154 | #define MMU_E (1<<0) |
155 | #define MMU_NF (1<<1) | |
e8af50a3 FB |
156 | |
157 | #define PTE_ENTRYTYPE_MASK 3 | |
158 | #define PTE_ACCESS_MASK 0x1c | |
159 | #define PTE_ACCESS_SHIFT 2 | |
8d5f07fa | 160 | #define PTE_PPN_SHIFT 7 |
e8af50a3 FB |
161 | #define PTE_ADDR_MASK 0xffffff00 |
162 | ||
0f8a249a BS |
163 | #define PG_ACCESSED_BIT 5 |
164 | #define PG_MODIFIED_BIT 6 | |
e8af50a3 FB |
165 | #define PG_CACHE_BIT 7 |
166 | ||
167 | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) | |
168 | #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) | |
169 | #define PG_CACHE_MASK (1 << PG_CACHE_BIT) | |
170 | ||
1d6e34fd FB |
171 | /* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */ |
172 | #define NWINDOWS 8 | |
cf495bcf | 173 | |
6f27aba6 | 174 | #if !defined(TARGET_SPARC64) |
6ebbf390 | 175 | #define NB_MMU_MODES 2 |
6f27aba6 BS |
176 | #else |
177 | #define NB_MMU_MODES 3 | |
375ee38b BS |
178 | typedef struct trap_state { |
179 | uint64_t tpc; | |
180 | uint64_t tnpc; | |
181 | uint64_t tstate; | |
182 | uint32_t tt; | |
183 | } trap_state; | |
6f27aba6 | 184 | #endif |
6ebbf390 | 185 | |
7a3f1944 | 186 | typedef struct CPUSPARCState { |
af7bf89b FB |
187 | target_ulong gregs[8]; /* general registers */ |
188 | target_ulong *regwptr; /* pointer to current register window */ | |
65ce8c2f | 189 | float32 fpr[TARGET_FPREGS]; /* floating point registers */ |
af7bf89b FB |
190 | target_ulong pc; /* program counter */ |
191 | target_ulong npc; /* next program counter */ | |
192 | target_ulong y; /* multiply/divide register */ | |
dc99a3f2 BS |
193 | |
194 | /* emulator internal flags handling */ | |
d9bdab86 | 195 | target_ulong cc_src, cc_src2; |
dc99a3f2 BS |
196 | target_ulong cc_dst; |
197 | ||
cf495bcf | 198 | uint32_t psr; /* processor state register */ |
3475187d | 199 | target_ulong fsr; /* FPU state register */ |
cf495bcf FB |
200 | uint32_t cwp; /* index of current register window (extracted |
201 | from PSR) */ | |
202 | uint32_t wim; /* window invalid mask */ | |
3475187d | 203 | target_ulong tbr; /* trap base register */ |
e8af50a3 FB |
204 | int psrs; /* supervisor mode (extracted from PSR) */ |
205 | int psrps; /* previous supervisor mode */ | |
206 | int psret; /* enable traps */ | |
327ac2e7 BS |
207 | uint32_t psrpil; /* interrupt blocking level */ |
208 | uint32_t pil_in; /* incoming interrupt level bitmap */ | |
e80cfcfc | 209 | int psref; /* enable fpu */ |
62724a37 | 210 | target_ulong version; |
cf495bcf FB |
211 | jmp_buf jmp_env; |
212 | int user_mode_only; | |
213 | int exception_index; | |
214 | int interrupt_index; | |
215 | int interrupt_request; | |
ba3c64fb | 216 | int halted; |
6d5f237a | 217 | uint32_t mmu_bm; |
3deaeab7 BS |
218 | uint32_t mmu_ctpr_mask; |
219 | uint32_t mmu_cxr_mask; | |
220 | uint32_t mmu_sfsr_mask; | |
221 | uint32_t mmu_trcr_mask; | |
cf495bcf | 222 | /* NOTE: we allow 8 more registers to handle wrapping */ |
af7bf89b | 223 | target_ulong regbase[NWINDOWS * 16 + 8]; |
d720b93d | 224 | |
a316d335 FB |
225 | CPU_COMMON |
226 | ||
e8af50a3 | 227 | /* MMU regs */ |
3475187d FB |
228 | #if defined(TARGET_SPARC64) |
229 | uint64_t lsu; | |
230 | #define DMMU_E 0x8 | |
231 | #define IMMU_E 0x4 | |
232 | uint64_t immuregs[16]; | |
233 | uint64_t dmmuregs[16]; | |
234 | uint64_t itlb_tag[64]; | |
235 | uint64_t itlb_tte[64]; | |
236 | uint64_t dtlb_tag[64]; | |
237 | uint64_t dtlb_tte[64]; | |
238 | #else | |
3dd9a152 | 239 | uint32_t mmuregs[32]; |
952a328f BS |
240 | uint64_t mxccdata[4]; |
241 | uint64_t mxccregs[8]; | |
3ebf5aaf | 242 | uint64_t prom_addr; |
3475187d | 243 | #endif |
e8af50a3 | 244 | /* temporary float registers */ |
65ce8c2f FB |
245 | float32 ft0, ft1; |
246 | float64 dt0, dt1; | |
1f587329 BS |
247 | #if defined(CONFIG_USER_ONLY) |
248 | float128 qt0, qt1; | |
249 | #endif | |
7a0e1f41 | 250 | float_status fp_status; |
af7bf89b | 251 | #if defined(TARGET_SPARC64) |
3475187d | 252 | #define MAXTL 4 |
7fa76c0b | 253 | uint64_t t0; |
375ee38b BS |
254 | trap_state *tsptr; |
255 | trap_state ts[MAXTL]; | |
0f8a249a | 256 | uint32_t xcc; /* Extended integer condition codes */ |
3475187d FB |
257 | uint32_t asi; |
258 | uint32_t pstate; | |
259 | uint32_t tl; | |
260 | uint32_t cansave, canrestore, otherwin, wstate, cleanwin; | |
83469015 FB |
261 | uint64_t agregs[8]; /* alternate general registers */ |
262 | uint64_t bgregs[8]; /* backup for normal global registers */ | |
263 | uint64_t igregs[8]; /* interrupt general registers */ | |
264 | uint64_t mgregs[8]; /* mmu general registers */ | |
3475187d | 265 | uint64_t fprs; |
83469015 | 266 | uint64_t tick_cmpr, stick_cmpr; |
20c9f095 | 267 | void *tick, *stick; |
725cb90b | 268 | uint64_t gsr; |
e9ebed4d BS |
269 | uint32_t gl; // UA2005 |
270 | /* UA 2005 hyperprivileged registers */ | |
271 | uint64_t hpstate, htstate[MAXTL], hintp, htba, hver, hstick_cmpr, ssr; | |
20c9f095 | 272 | void *hstick; // UA 2005 |
3475187d | 273 | #endif |
7fa76c0b | 274 | target_ulong t1, t2; |
7a3f1944 | 275 | } CPUSPARCState; |
3475187d FB |
276 | #if defined(TARGET_SPARC64) |
277 | #define GET_FSR32(env) (env->fsr & 0xcfc1ffff) | |
0f8a249a BS |
278 | #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \ |
279 | env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \ | |
3475187d FB |
280 | } while (0) |
281 | #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL) | |
0f8a249a BS |
282 | #define PUT_FSR64(env, val) do { uint64_t _tmp = val; \ |
283 | env->fsr = _tmp & 0x3fcfc1c3ffULL; \ | |
3475187d | 284 | } while (0) |
3475187d FB |
285 | #else |
286 | #define GET_FSR32(env) (env->fsr) | |
3e736bf4 | 287 | #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \ |
9143e598 | 288 | env->fsr = (_tmp & 0xcfc1dfff) | (env->fsr & 0x000e0000); \ |
3475187d FB |
289 | } while (0) |
290 | #endif | |
7a3f1944 | 291 | |
aaed909a | 292 | CPUSPARCState *cpu_sparc_init(const char *cpu_model); |
c48fcb47 | 293 | void gen_intermediate_code_init(CPUSPARCState *env); |
7a3f1944 FB |
294 | int cpu_sparc_exec(CPUSPARCState *s); |
295 | int cpu_sparc_close(CPUSPARCState *s); | |
62724a37 BS |
296 | void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, |
297 | ...)); | |
aaed909a | 298 | void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); |
7a3f1944 | 299 | |
62724a37 | 300 | #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \ |
0f8a249a BS |
301 | (env->psref? PSR_EF : 0) | \ |
302 | (env->psrpil << 8) | \ | |
303 | (env->psrs? PSR_S : 0) | \ | |
304 | (env->psrps? PSR_PS : 0) | \ | |
305 | (env->psret? PSR_ET : 0) | env->cwp) | |
b4ff5987 FB |
306 | |
307 | #ifndef NO_CPU_IO_DEFS | |
308 | void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); | |
309 | #endif | |
310 | ||
0f8a249a BS |
311 | #define PUT_PSR(env, val) do { int _tmp = val; \ |
312 | env->psr = _tmp & PSR_ICC; \ | |
313 | env->psref = (_tmp & PSR_EF)? 1 : 0; \ | |
314 | env->psrpil = (_tmp & PSR_PIL) >> 8; \ | |
315 | env->psrs = (_tmp & PSR_S)? 1 : 0; \ | |
316 | env->psrps = (_tmp & PSR_PS)? 1 : 0; \ | |
317 | env->psret = (_tmp & PSR_ET)? 1 : 0; \ | |
d4218d99 | 318 | cpu_set_cwp(env, _tmp & PSR_CWP); \ |
b4ff5987 FB |
319 | } while (0) |
320 | ||
3475187d | 321 | #ifdef TARGET_SPARC64 |
17d996e1 | 322 | #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20)) |
0f8a249a BS |
323 | #define PUT_CCR(env, val) do { int _tmp = val; \ |
324 | env->xcc = (_tmp >> 4) << 20; \ | |
325 | env->psr = (_tmp & 0xf) << 20; \ | |
3475187d | 326 | } while (0) |
17d996e1 | 327 | #define GET_CWP64(env) (NWINDOWS - 1 - (env)->cwp) |
8f1f22f6 BS |
328 | #define PUT_CWP64(env, val) \ |
329 | cpu_set_cwp(env, NWINDOWS - 1 - ((val) & (NWINDOWS - 1))) | |
17d996e1 | 330 | |
3475187d FB |
331 | #endif |
332 | ||
5a7b542b | 333 | int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); |
5dcb6b91 | 334 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
6c36d3fa | 335 | int is_asi); |
327ac2e7 | 336 | void cpu_check_irqs(CPUSPARCState *env); |
7a3f1944 | 337 | |
9467d44c TS |
338 | #define CPUState CPUSPARCState |
339 | #define cpu_init cpu_sparc_init | |
340 | #define cpu_exec cpu_sparc_exec | |
341 | #define cpu_gen_code cpu_sparc_gen_code | |
342 | #define cpu_signal_handler cpu_sparc_signal_handler | |
c732abe2 | 343 | #define cpu_list sparc_cpu_list |
9467d44c | 344 | |
6ebbf390 | 345 | /* MMU modes definitions */ |
6f27aba6 BS |
346 | #define MMU_MODE0_SUFFIX _user |
347 | #define MMU_MODE1_SUFFIX _kernel | |
348 | #ifdef TARGET_SPARC64 | |
349 | #define MMU_MODE2_SUFFIX _hypv | |
350 | #endif | |
9e31b9e2 BS |
351 | #define MMU_USER_IDX 0 |
352 | #define MMU_KERNEL_IDX 1 | |
353 | #define MMU_HYPV_IDX 2 | |
354 | ||
6ebbf390 JM |
355 | static inline int cpu_mmu_index (CPUState *env) |
356 | { | |
6f27aba6 | 357 | #if defined(CONFIG_USER_ONLY) |
9e31b9e2 | 358 | return MMU_USER_IDX; |
6f27aba6 BS |
359 | #elif !defined(TARGET_SPARC64) |
360 | return env->psrs; | |
361 | #else | |
362 | if (!env->psrs) | |
9e31b9e2 | 363 | return MMU_USER_IDX; |
6f27aba6 | 364 | else if ((env->hpstate & HS_PRIV) == 0) |
9e31b9e2 | 365 | return MMU_KERNEL_IDX; |
6f27aba6 | 366 | else |
9e31b9e2 | 367 | return MMU_HYPV_IDX; |
6f27aba6 BS |
368 | #endif |
369 | } | |
370 | ||
371 | static inline int cpu_fpu_enabled(CPUState *env) | |
372 | { | |
373 | #if defined(CONFIG_USER_ONLY) | |
374 | return 1; | |
375 | #elif !defined(TARGET_SPARC64) | |
376 | return env->psref; | |
377 | #else | |
378 | return ((env->pstate & PS_PEF) != 0) && ((env->fprs & FPRS_FEF) != 0); | |
379 | #endif | |
6ebbf390 JM |
380 | } |
381 | ||
7a3f1944 FB |
382 | #include "cpu-all.h" |
383 | ||
384 | #endif |