[qemu.git] / target-sparc / cpu.h

#ifndef CPU_SPARC_H
#define CPU_SPARC_H

#include "config.h"

#if !defined(TARGET_SPARC64)
#define TARGET_LONG_BITS 32
#define TARGET_FPREGS 32
#define TARGET_PAGE_BITS 12 /* 4k */
#else
#define TARGET_LONG_BITS 64
#define TARGET_FPREGS 64
#define TARGET_PAGE_BITS 13 /* 8k */
#endif

#define CPUState struct CPUSPARCState

#include "cpu-defs.h"

#include "softfloat.h"

#define TARGET_HAS_ICE 1

#if !defined(TARGET_SPARC64)
#define ELF_MACHINE     EM_SPARC
#else
#define ELF_MACHINE     EM_SPARCV9
#endif

/*#define EXCP_INTERRUPT 0x100*/

/* trap definitions */
#ifndef TARGET_SPARC64
#define TT_TFAULT   0x01
#define TT_ILL_INSN 0x02
#define TT_PRIV_INSN 0x03
#define TT_NFPU_INSN 0x04
#define TT_WIN_OVF  0x05
#define TT_WIN_UNF  0x06
#define TT_UNALIGNED 0x07
#define TT_FP_EXCP  0x08
#define TT_DFAULT   0x09
#define TT_TOVF     0x0a
#define TT_EXTINT   0x10
#define TT_CODE_ACCESS 0x21
#define TT_UNIMP_FLUSH 0x25
#define TT_DATA_ACCESS 0x29
#define TT_DIV_ZERO 0x2a
#define TT_NCP_INSN 0x24
#define TT_TRAP     0x80
#else
#define TT_TFAULT   0x08
#define TT_CODE_ACCESS 0x0a
#define TT_ILL_INSN 0x10
#define TT_UNIMP_FLUSH TT_ILL_INSN
#define TT_PRIV_INSN 0x11
#define TT_NFPU_INSN 0x20
#define TT_FP_EXCP  0x21
#define TT_TOVF     0x23
#define TT_CLRWIN   0x24
#define TT_DIV_ZERO 0x28
#define TT_DFAULT   0x30
#define TT_DATA_ACCESS 0x32
#define TT_UNALIGNED 0x34
#define TT_PRIV_ACT 0x37
#define TT_EXTINT   0x40
#define TT_IVEC     0x60
#define TT_TMISS    0x64
#define TT_DMISS    0x68
#define TT_DPROT    0x6c
#define TT_SPILL    0x80
#define TT_FILL     0xc0
#define TT_WOTHER   0x10
#define TT_TRAP     0x100
#endif

#define PSR_NEG_SHIFT 23
#define PSR_NEG   (1 << PSR_NEG_SHIFT)
#define PSR_ZERO_SHIFT 22
#define PSR_ZERO  (1 << PSR_ZERO_SHIFT)
#define PSR_OVF_SHIFT 21
#define PSR_OVF   (1 << PSR_OVF_SHIFT)
#define PSR_CARRY_SHIFT 20
#define PSR_CARRY (1 << PSR_CARRY_SHIFT)
#define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
#define PSR_EF    (1<<12)
#define PSR_PIL   0xf00
#define PSR_S     (1<<7)
#define PSR_PS    (1<<6)
#define PSR_ET    (1<<5)
#define PSR_CWP   0x1f

#define CC_SRC (env->cc_src)
#define CC_SRC2 (env->cc_src2)
#define CC_DST (env->cc_dst)
#define CC_OP  (env->cc_op)

enum {
    CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
    CC_OP_FLAGS,   /* all cc are back in status register */
    CC_OP_DIV,     /* modify N, Z and V, C = 0*/
    CC_OP_ADD,     /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_ADDX,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_TADD,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_TADDTV,  /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
    CC_OP_SUB,     /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_SUBX,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_TSUB,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_TSUBTV,  /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
    CC_OP_LOGIC,   /* modify N and Z, C = V = 0, CC_DST = res */
    CC_OP_NB,
};

/* Trap base register */
#define TBR_BASE_MASK 0xfffff000

#if defined(TARGET_SPARC64)
#define PS_TCT   (1<<12) /* UA2007, impl.dep. trap on control transfer */
#define PS_IG    (1<<11) /* v9, zero on UA2007 */
#define PS_MG    (1<<10) /* v9, zero on UA2007 */
#define PS_CLE   (1<<9) /* UA2007 */
#define PS_TLE   (1<<8) /* UA2007 */
#define PS_RMO   (1<<7)
#define PS_RED   (1<<5) /* v9, zero on UA2007 */
#define PS_PEF   (1<<4) /* enable fpu */
#define PS_AM    (1<<3) /* address mask */
#define PS_PRIV  (1<<2)
#define PS_IE    (1<<1)
#define PS_AG    (1<<0) /* v9, zero on UA2007 */

#define FPRS_FEF (1<<2)

#define HS_PRIV  (1<<2)
#endif

/* Fcc */
#define FSR_RD1        (1ULL << 31)
#define FSR_RD0        (1ULL << 30)
#define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
#define FSR_RD_NEAREST 0
#define FSR_RD_ZERO    FSR_RD0
#define FSR_RD_POS     FSR_RD1
#define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)

#define FSR_NVM   (1ULL << 27)
#define FSR_OFM   (1ULL << 26)
#define FSR_UFM   (1ULL << 25)
#define FSR_DZM   (1ULL << 24)
#define FSR_NXM   (1ULL << 23)
#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)

#define FSR_NVA   (1ULL << 9)
#define FSR_OFA   (1ULL << 8)
#define FSR_UFA   (1ULL << 7)
#define FSR_DZA   (1ULL << 6)
#define FSR_NXA   (1ULL << 5)
#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)

#define FSR_NVC   (1ULL << 4)
#define FSR_OFC   (1ULL << 3)
#define FSR_UFC   (1ULL << 2)
#define FSR_DZC   (1ULL << 1)
#define FSR_NXC   (1ULL << 0)
#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)

#define FSR_FTT2   (1ULL << 16)
#define FSR_FTT1   (1ULL << 15)
#define FSR_FTT0   (1ULL << 14)
//gcc warns about constant overflow for ~FSR_FTT_MASK
//#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
#ifdef TARGET_SPARC64
#define FSR_FTT_NMASK      0xfffffffffffe3fffULL
#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
#define FSR_LDFSR_OLDMASK  0x0000003f000fc000ULL
#define FSR_LDXFSR_MASK    0x0000003fcfc00fffULL
#define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
#else
#define FSR_FTT_NMASK      0xfffe3fffULL
#define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
#define FSR_LDFSR_OLDMASK  0x000fc000ULL
#endif
#define FSR_LDFSR_MASK     0xcfc00fffULL
#define FSR_FTT_IEEE_EXCP (1ULL << 14)
#define FSR_FTT_UNIMPFPOP (3ULL << 14)
#define FSR_FTT_SEQ_ERROR (4ULL << 14)
#define FSR_FTT_INVAL_FPR (6ULL << 14)

#define FSR_FCC1_SHIFT 11
#define FSR_FCC1  (1ULL << FSR_FCC1_SHIFT)
#define FSR_FCC0_SHIFT 10
#define FSR_FCC0  (1ULL << FSR_FCC0_SHIFT)

/* MMU */
#define MMU_E     (1<<0)
#define MMU_NF    (1<<1)

#define PTE_ENTRYTYPE_MASK 3
#define PTE_ACCESS_MASK    0x1c
#define PTE_ACCESS_SHIFT   2
#define PTE_PPN_SHIFT      7
#define PTE_ADDR_MASK      0xffffff00

#define PG_ACCESSED_BIT 5
#define PG_MODIFIED_BIT 6
#define PG_CACHE_BIT    7

#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
#define PG_CACHE_MASK    (1 << PG_CACHE_BIT)

/* 3 <= NWINDOWS <= 32. */
#define MIN_NWINDOWS 3
#define MAX_NWINDOWS 32

#if !defined(TARGET_SPARC64)
#define NB_MMU_MODES 2
#else
#define NB_MMU_MODES 3
typedef struct trap_state {
    uint64_t tpc;
    uint64_t tnpc;
    uint64_t tstate;
    uint32_t tt;
} trap_state;
#endif

typedef struct sparc_def_t {
    const char *name;
    target_ulong iu_version;
    uint32_t fpu_version;
    uint32_t mmu_version;
    uint32_t mmu_bm;
    uint32_t mmu_ctpr_mask;
    uint32_t mmu_cxr_mask;
    uint32_t mmu_sfsr_mask;
    uint32_t mmu_trcr_mask;
    uint32_t mxcc_version;
    uint32_t features;
    uint32_t nwindows;
    uint32_t maxtl;
} sparc_def_t;

#define CPU_FEATURE_FLOAT    (1 << 0)
#define CPU_FEATURE_FLOAT128 (1 << 1)
#define CPU_FEATURE_SWAP     (1 << 2)
#define CPU_FEATURE_MUL      (1 << 3)
#define CPU_FEATURE_DIV      (1 << 4)
#define CPU_FEATURE_FLUSH    (1 << 5)
#define CPU_FEATURE_FSQRT    (1 << 6)
#define CPU_FEATURE_FMUL     (1 << 7)
#define CPU_FEATURE_VIS1     (1 << 8)
#define CPU_FEATURE_VIS2     (1 << 9)
#define CPU_FEATURE_FSMULD   (1 << 10)
#define CPU_FEATURE_HYPV     (1 << 11)
#define CPU_FEATURE_CMT      (1 << 12)
#define CPU_FEATURE_GL       (1 << 13)
#ifndef TARGET_SPARC64
#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
                              CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
                              CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
                              CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
#else
#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
                              CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
                              CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
                              CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 |   \
                              CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD)
enum {
    mmu_us_12, // Ultrasparc < III (64 entry TLB)
    mmu_us_3,  // Ultrasparc III (512 entry TLB)
    mmu_us_4,  // Ultrasparc IV (several TLBs, 32 and 256MB pages)
    mmu_sun4v, // T1, T2
};
#endif

typedef struct CPUSPARCState {
    target_ulong gregs[8]; /* general registers */
    target_ulong *regwptr; /* pointer to current register window */
    target_ulong pc;       /* program counter */
    target_ulong npc;      /* next program counter */
    target_ulong y;        /* multiply/divide register */

    /* emulator internal flags handling */
    target_ulong cc_src, cc_src2;
    target_ulong cc_dst;
    uint32_t cc_op;

    target_ulong t0, t1; /* temporaries live across basic blocks */
    target_ulong cond; /* conditional branch result (XXX: save it in a
                          temporary register when possible) */

    uint32_t psr;      /* processor state register */
    target_ulong fsr;      /* FPU state register */
    float32 fpr[TARGET_FPREGS];  /* floating point registers */
    uint32_t cwp;      /* index of current register window (extracted
                          from PSR) */
#if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
    uint32_t wim;      /* window invalid mask */
#endif
    target_ulong tbr;  /* trap base register */
    int      psrs;     /* supervisor mode (extracted from PSR) */
    int      psrps;    /* previous supervisor mode */
#if !defined(TARGET_SPARC64)
    int      psret;    /* enable traps */
#endif
    uint32_t psrpil;   /* interrupt blocking level */
    uint32_t pil_in;   /* incoming interrupt level bitmap */
    int      psref;    /* enable fpu */
    target_ulong version;
    int interrupt_index;
    uint32_t nwindows;
    /* NOTE: we allow 8 more registers to handle wrapping */
    target_ulong regbase[MAX_NWINDOWS * 16 + 8];

    CPU_COMMON

    /* MMU regs */
#if defined(TARGET_SPARC64)
    uint64_t lsu;
#define DMMU_E 0x8
#define IMMU_E 0x4
    uint64_t immuregs[16];
    uint64_t dmmuregs[16];
    uint64_t itlb_tag[64];
    uint64_t itlb_tte[64];
    uint64_t dtlb_tag[64];
    uint64_t dtlb_tte[64];
    uint32_t mmu_version;
#else
    uint32_t mmuregs[32];
    uint64_t mxccdata[4];
    uint64_t mxccregs[8];
    uint64_t mmubpregs[4];
    uint64_t prom_addr;
#endif
    /* temporary float registers */
    float64 dt0, dt1;
    float128 qt0, qt1;
    float_status fp_status;
#if defined(TARGET_SPARC64)
#define MAXTL_MAX 8
#define MAXTL_MASK (MAXTL_MAX - 1)
    trap_state *tsptr;
    trap_state ts[MAXTL_MAX];
    uint32_t xcc;               /* Extended integer condition codes */
    uint32_t asi;
    uint32_t pstate;
    uint32_t tl;
    uint32_t maxtl;
    uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
    uint64_t agregs[8]; /* alternate general registers */
    uint64_t bgregs[8]; /* backup for normal global registers */
    uint64_t igregs[8]; /* interrupt general registers */
    uint64_t mgregs[8]; /* mmu general registers */
    uint64_t fprs;
    uint64_t tick_cmpr, stick_cmpr;
    void *tick, *stick;
    uint64_t gsr;
    uint32_t gl; // UA2005
    /* UA 2005 hyperprivileged registers */
    uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
    void *hstick; // UA 2005
    uint32_t softint;
#define SOFTINT_TIMER   1
#define SOFTINT_STIMER  (1 << 16)
#endif
    sparc_def_t *def;
} CPUSPARCState;

/* helper.c */
CPUSPARCState *cpu_sparc_init(const char *cpu_model);
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
                                                 ...));
void cpu_lock(void);
void cpu_unlock(void);
int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
                               int mmu_idx, int is_softmmu);
target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
void dump_mmu(CPUSPARCState *env);

/* translate.c */
void gen_intermediate_code_init(CPUSPARCState *env);

/* cpu-exec.c */
int cpu_sparc_exec(CPUSPARCState *s);

#if !defined (TARGET_SPARC64)
#define GET_PSR(env) (env->version | (env->psr & PSR_ICC) |             \
                      (env->psref? PSR_EF : 0) |                        \
                      (env->psrpil << 8) |                              \
                      (env->psrs? PSR_S : 0) |                          \
                      (env->psrps? PSR_PS : 0) |                        \
                      (env->psret? PSR_ET : 0) | env->cwp)
#else
#define GET_PSR(env) (env->version | (env->psr & PSR_ICC) |             \
                      (env->psref? PSR_EF : 0) |                        \
                      (env->psrpil << 8) |                              \
                      (env->psrs? PSR_S : 0) |                          \
                      (env->psrps? PSR_PS : 0) |                        \
                      env->cwp)
#endif

#ifndef NO_CPU_IO_DEFS
static inline void memcpy32(target_ulong *dst, const target_ulong *src)
{
    dst[0] = src[0];
    dst[1] = src[1];
    dst[2] = src[2];
    dst[3] = src[3];
    dst[4] = src[4];
    dst[5] = src[5];
    dst[6] = src[6];
    dst[7] = src[7];
}

static inline void cpu_set_cwp(CPUSPARCState *env1, int new_cwp)
{
    /* put the modified wrap registers at their proper location */
    if (env1->cwp == env1->nwindows - 1)
        memcpy32(env1->regbase, env1->regbase + env1->nwindows * 16);
    env1->cwp = new_cwp;
    /* put the wrap registers at their temporary location */
    if (new_cwp == env1->nwindows - 1)
        memcpy32(env1->regbase + env1->nwindows * 16, env1->regbase);
    env1->regwptr = env1->regbase + (new_cwp * 16);
}

static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp)
{
    if (unlikely(cwp >= env1->nwindows))
        cwp -= env1->nwindows;
    return cwp;
}

static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
{
    if (unlikely(cwp < 0))
        cwp += env1->nwindows;
    return cwp;
}
#endif

#if !defined (TARGET_SPARC64)
#define PUT_PSR(env, val) do { int _tmp = val;                          \
        env->psr = _tmp & PSR_ICC;                                      \
        env->psref = (_tmp & PSR_EF)? 1 : 0;                            \
        env->psrpil = (_tmp & PSR_PIL) >> 8;                            \
        env->psrs = (_tmp & PSR_S)? 1 : 0;                              \
        env->psrps = (_tmp & PSR_PS)? 1 : 0;                            \
        env->psret = (_tmp & PSR_ET)? 1 : 0;                            \
        cpu_set_cwp(env, _tmp & PSR_CWP);                               \
        CC_OP = CC_OP_FLAGS;                                            \
    } while (0)
#else
#define PUT_PSR(env, val) do { int _tmp = val;                          \
        env->psr = _tmp & PSR_ICC;                                      \
        env->psref = (_tmp & PSR_EF)? 1 : 0;                            \
        env->psrpil = (_tmp & PSR_PIL) >> 8;                            \
        env->psrs = (_tmp & PSR_S)? 1 : 0;                              \
        env->psrps = (_tmp & PSR_PS)? 1 : 0;                            \
        cpu_set_cwp(env, _tmp & PSR_CWP);                               \
        CC_OP = CC_OP_FLAGS;                                            \
    } while (0)
#endif

#ifdef TARGET_SPARC64
#define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
#define PUT_CCR(env, val) do { int _tmp = val;                          \
        env->xcc = (_tmp >> 4) << 20;                                   \
        env->psr = (_tmp & 0xf) << 20;                                  \
        CC_OP = CC_OP_FLAGS;                                            \
    } while (0)
#define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp)

#ifndef NO_CPU_IO_DEFS
static inline void PUT_CWP64(CPUSPARCState *env1, int cwp)
{
    if (unlikely(cwp >= env1->nwindows || cwp < 0))
        cwp = 0;
    cpu_set_cwp(env1, env1->nwindows - 1 - cwp);
}
#endif
#endif

/* cpu-exec.c */
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
                          int is_asi, int size);
int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);

#define cpu_init cpu_sparc_init
#define cpu_exec cpu_sparc_exec
#define cpu_gen_code cpu_sparc_gen_code
#define cpu_signal_handler cpu_sparc_signal_handler
#define cpu_list sparc_cpu_list

#define CPU_SAVE_VERSION 5

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _user
#define MMU_MODE1_SUFFIX _kernel
#ifdef TARGET_SPARC64
#define MMU_MODE2_SUFFIX _hypv
#endif
#define MMU_USER_IDX   0
#define MMU_KERNEL_IDX 1
#define MMU_HYPV_IDX   2

static inline int cpu_mmu_index(CPUState *env1)
{
#if defined(CONFIG_USER_ONLY)
    return MMU_USER_IDX;
#elif !defined(TARGET_SPARC64)
    return env1->psrs;
#else
    if (!env1->psrs)
        return MMU_USER_IDX;
    else if ((env1->hpstate & HS_PRIV) == 0)
        return MMU_KERNEL_IDX;
    else
        return MMU_HYPV_IDX;
#endif
}

static inline int cpu_fpu_enabled(CPUState *env1)
{
#if defined(CONFIG_USER_ONLY)
    return 1;
#elif !defined(TARGET_SPARC64)
    return env1->psref;
#else
    return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0);
#endif
}

#if defined(CONFIG_USER_ONLY)
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
{
    if (newsp)
        env->regwptr[22] = newsp;
    env->regwptr[0] = 0;
    /* FIXME: Do we also need to clear CF?  */
    /* XXXXX */
    printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
}
#endif

#include "cpu-all.h"
#include "exec-all.h"

/* sum4m.c, sun4u.c */
void cpu_check_irqs(CPUSPARCState *env);

#ifdef TARGET_SPARC64
/* sun4u.c */
void cpu_tick_set_count(void *opaque, uint64_t count);
uint64_t cpu_tick_get_count(void *opaque);
void cpu_tick_set_limit(void *opaque, uint64_t limit);
#endif

static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
    env->pc = tb->pc;
    env->npc = tb->cs_base;
}

static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
                                        target_ulong *cs_base, int *flags)
{
    *pc = env->pc;
    *cs_base = env->npc;
#ifdef TARGET_SPARC64
    // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
    *flags = ((env->pstate & PS_AM) << 2)
        | (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
        | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
#else
    // FPU enable . Supervisor
    *flags = (env->psref << 4) | env->psrs;
#endif
}

#endif
Commit	Line	Data
7a3f1944 FB	1	#ifndef CPU_SPARC_H
	2	#define CPU_SPARC_H
	3
af7bf89b FB	4	#include "config.h"
	5
	6	#if !defined(TARGET_SPARC64)
3cf1e035	7	#define TARGET_LONG_BITS 32
af7bf89b	8	#define TARGET_FPREGS 32
83469015	9	#define TARGET_PAGE_BITS 12 /* 4k */
af7bf89b FB	10	#else
	11	#define TARGET_LONG_BITS 64
	12	#define TARGET_FPREGS 64
33b37802	13	#define TARGET_PAGE_BITS 13 /* 8k */
af7bf89b	14	#endif
3cf1e035	15
c2764719 PB	16	#define CPUState struct CPUSPARCState
c2764719 PB	17
7a3f1944 FB	18	#include "cpu-defs.h"
7a3f1944 FB	19
7a0e1f41 FB	20	#include "softfloat.h"
7a0e1f41 FB	21
1fddef4b FB	22	#define TARGET_HAS_ICE 1
1fddef4b FB	23
9042c0e2	24	#if !defined(TARGET_SPARC64)
0f8a249a	25	#define ELF_MACHINE EM_SPARC
9042c0e2	26	#else
0f8a249a	27	#define ELF_MACHINE EM_SPARCV9
9042c0e2 TS	28	#endif
9042c0e2 TS	29
7a3f1944 FB	30	/#define EXCP_INTERRUPT 0x100/
7a3f1944 FB	31
cf495bcf	32	/* trap definitions */
3475187d	33	#ifndef TARGET_SPARC64
878d3096	34	#define TT_TFAULT 0x01
cf495bcf	35	#define TT_ILL_INSN 0x02
e8af50a3	36	#define TT_PRIV_INSN 0x03
e80cfcfc	37	#define TT_NFPU_INSN 0x04
cf495bcf	38	#define TT_WIN_OVF 0x05
5fafdf24	39	#define TT_WIN_UNF 0x06
d2889a3e	40	#define TT_UNALIGNED 0x07
e8af50a3	41	#define TT_FP_EXCP 0x08
878d3096	42	#define TT_DFAULT 0x09
e32f879d	43	#define TT_TOVF 0x0a
878d3096	44	#define TT_EXTINT 0x10
1b2e93c1	45	#define TT_CODE_ACCESS 0x21
64a88d5d	46	#define TT_UNIMP_FLUSH 0x25
b4f0a316	47	#define TT_DATA_ACCESS 0x29
cf495bcf	48	#define TT_DIV_ZERO 0x2a
fcc72045	49	#define TT_NCP_INSN 0x24
cf495bcf	50	#define TT_TRAP 0x80
3475187d FB	51	#else
3475187d FB	52	#define TT_TFAULT 0x08
1b2e93c1	53	#define TT_CODE_ACCESS 0x0a
3475187d	54	#define TT_ILL_INSN 0x10
64a88d5d	55	#define TT_UNIMP_FLUSH TT_ILL_INSN
3475187d FB	56	#define TT_PRIV_INSN 0x11
	57	#define TT_NFPU_INSN 0x20
	58	#define TT_FP_EXCP 0x21
e32f879d	59	#define TT_TOVF 0x23
3475187d FB	60	#define TT_CLRWIN 0x24
	61	#define TT_DIV_ZERO 0x28
	62	#define TT_DFAULT 0x30
b4f0a316	63	#define TT_DATA_ACCESS 0x32
d2889a3e	64	#define TT_UNALIGNED 0x34
83469015	65	#define TT_PRIV_ACT 0x37
3475187d	66	#define TT_EXTINT 0x40
74b9decc	67	#define TT_IVEC 0x60
e19e4efe BS	68	#define TT_TMISS 0x64
e19e4efe BS	69	#define TT_DMISS 0x68
74b9decc	70	#define TT_DPROT 0x6c
3475187d FB	71	#define TT_SPILL 0x80
	72	#define TT_FILL 0xc0
	73	#define TT_WOTHER 0x10
	74	#define TT_TRAP 0x100
	75	#endif
7a3f1944	76
4b8b8b76 BS	77	#define PSR_NEG_SHIFT 23
	78	#define PSR_NEG (1 << PSR_NEG_SHIFT)
	79	#define PSR_ZERO_SHIFT 22
	80	#define PSR_ZERO (1 << PSR_ZERO_SHIFT)
	81	#define PSR_OVF_SHIFT 21
	82	#define PSR_OVF (1 << PSR_OVF_SHIFT)
	83	#define PSR_CARRY_SHIFT 20
	84	#define PSR_CARRY (1 << PSR_CARRY_SHIFT)
e8af50a3	85	#define PSR_ICC (PSR_NEG\|PSR_ZERO\|PSR_OVF\|PSR_CARRY)
e80cfcfc FB	86	#define PSR_EF (1<<12)
e80cfcfc FB	87	#define PSR_PIL 0xf00
e8af50a3 FB	88	#define PSR_S (1<<7)
	89	#define PSR_PS (1<<6)
	90	#define PSR_ET (1<<5)
	91	#define PSR_CWP 0x1f
e8af50a3	92
8393617c BS	93	#define CC_SRC (env->cc_src)
	94	#define CC_SRC2 (env->cc_src2)
	95	#define CC_DST (env->cc_dst)
	96	#define CC_OP (env->cc_op)
	97
	98	enum {
	99	CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
	100	CC_OP_FLAGS, /* all cc are back in status register */
	101	CC_OP_DIV, /* modify N, Z and V, C = 0*/
	102	CC_OP_ADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	103	CC_OP_ADDX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	104	CC_OP_TADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	105	CC_OP_TADDTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
	106	CC_OP_SUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	107	CC_OP_SUBX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	108	CC_OP_TSUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	109	CC_OP_TSUBTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
	110	CC_OP_LOGIC, /* modify N and Z, C = V = 0, CC_DST = res */
	111	CC_OP_NB,
	112	};
	113
e8af50a3 FB	114	/* Trap base register */
	115	#define TBR_BASE_MASK 0xfffff000
	116
3475187d	117	#if defined(TARGET_SPARC64)
5210977a IK	118	#define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */
	119	#define PS_IG (1<<11) /* v9, zero on UA2007 */
	120	#define PS_MG (1<<10) /* v9, zero on UA2007 */
	121	#define PS_CLE (1<<9) /* UA2007 */
	122	#define PS_TLE (1<<8) /* UA2007 */
6ef905f6	123	#define PS_RMO (1<<7)
5210977a IK	124	#define PS_RED (1<<5) /* v9, zero on UA2007 */
	125	#define PS_PEF (1<<4) /* enable fpu */
	126	#define PS_AM (1<<3) /* address mask */
3475187d FB	127	#define PS_PRIV (1<<2)
3475187d FB	128	#define PS_IE (1<<1)
5210977a	129	#define PS_AG (1<<0) /* v9, zero on UA2007 */
a80dde08 FB	130
a80dde08 FB	131	#define FPRS_FEF (1<<2)
6f27aba6 BS	132
6f27aba6 BS	133	#define HS_PRIV (1<<2)
3475187d FB	134	#endif
3475187d FB	135
e8af50a3	136	/* Fcc */
ba6a9d8c BS	137	#define FSR_RD1 (1ULL << 31)
ba6a9d8c BS	138	#define FSR_RD0 (1ULL << 30)
e8af50a3 FB	139	#define FSR_RD_MASK (FSR_RD1 \| FSR_RD0)
	140	#define FSR_RD_NEAREST 0
	141	#define FSR_RD_ZERO FSR_RD0
	142	#define FSR_RD_POS FSR_RD1
	143	#define FSR_RD_NEG (FSR_RD1 \| FSR_RD0)
	144
ba6a9d8c BS	145	#define FSR_NVM (1ULL << 27)
	146	#define FSR_OFM (1ULL << 26)
	147	#define FSR_UFM (1ULL << 25)
	148	#define FSR_DZM (1ULL << 24)
	149	#define FSR_NXM (1ULL << 23)
e8af50a3 FB	150	#define FSR_TEM_MASK (FSR_NVM \| FSR_OFM \| FSR_UFM \| FSR_DZM \| FSR_NXM)
e8af50a3 FB	151
ba6a9d8c BS	152	#define FSR_NVA (1ULL << 9)
	153	#define FSR_OFA (1ULL << 8)
	154	#define FSR_UFA (1ULL << 7)
	155	#define FSR_DZA (1ULL << 6)
	156	#define FSR_NXA (1ULL << 5)
e8af50a3 FB	157	#define FSR_AEXC_MASK (FSR_NVA \| FSR_OFA \| FSR_UFA \| FSR_DZA \| FSR_NXA)
e8af50a3 FB	158
ba6a9d8c BS	159	#define FSR_NVC (1ULL << 4)
	160	#define FSR_OFC (1ULL << 3)
	161	#define FSR_UFC (1ULL << 2)
	162	#define FSR_DZC (1ULL << 1)
	163	#define FSR_NXC (1ULL << 0)
e8af50a3 FB	164	#define FSR_CEXC_MASK (FSR_NVC \| FSR_OFC \| FSR_UFC \| FSR_DZC \| FSR_NXC)
e8af50a3 FB	165
ba6a9d8c BS	166	#define FSR_FTT2 (1ULL << 16)
	167	#define FSR_FTT1 (1ULL << 15)
	168	#define FSR_FTT0 (1ULL << 14)
47ad35f1 BS	169	//gcc warns about constant overflow for ~FSR_FTT_MASK
	170	//#define FSR_FTT_MASK (FSR_FTT2 \| FSR_FTT1 \| FSR_FTT0)
	171	#ifdef TARGET_SPARC64
	172	#define FSR_FTT_NMASK 0xfffffffffffe3fffULL
	173	#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
3a3b925d BS	174	#define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL
	175	#define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL
	176	#define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
47ad35f1 BS	177	#else
	178	#define FSR_FTT_NMASK 0xfffe3fffULL
	179	#define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
3a3b925d	180	#define FSR_LDFSR_OLDMASK 0x000fc000ULL
47ad35f1	181	#endif
3a3b925d	182	#define FSR_LDFSR_MASK 0xcfc00fffULL
ba6a9d8c BS	183	#define FSR_FTT_IEEE_EXCP (1ULL << 14)
	184	#define FSR_FTT_UNIMPFPOP (3ULL << 14)
	185	#define FSR_FTT_SEQ_ERROR (4ULL << 14)
	186	#define FSR_FTT_INVAL_FPR (6ULL << 14)
e8af50a3	187
4b8b8b76	188	#define FSR_FCC1_SHIFT 11
ba6a9d8c	189	#define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT)
4b8b8b76	190	#define FSR_FCC0_SHIFT 10
ba6a9d8c	191	#define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT)
e8af50a3 FB	192
e8af50a3 FB	193	/* MMU */
0f8a249a BS	194	#define MMU_E (1<<0)
0f8a249a BS	195	#define MMU_NF (1<<1)
e8af50a3 FB	196
	197	#define PTE_ENTRYTYPE_MASK 3
	198	#define PTE_ACCESS_MASK 0x1c
	199	#define PTE_ACCESS_SHIFT 2
8d5f07fa	200	#define PTE_PPN_SHIFT 7
e8af50a3 FB	201	#define PTE_ADDR_MASK 0xffffff00
e8af50a3 FB	202
0f8a249a BS	203	#define PG_ACCESSED_BIT 5
0f8a249a BS	204	#define PG_MODIFIED_BIT 6
e8af50a3 FB	205	#define PG_CACHE_BIT 7
	206
	207	#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
	208	#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
	209	#define PG_CACHE_MASK (1 << PG_CACHE_BIT)
	210
1a14026e BS	211	/* 3 <= NWINDOWS <= 32. */
	212	#define MIN_NWINDOWS 3
	213	#define MAX_NWINDOWS 32
cf495bcf	214
6f27aba6	215	#if !defined(TARGET_SPARC64)
6ebbf390	216	#define NB_MMU_MODES 2
6f27aba6 BS	217	#else
6f27aba6 BS	218	#define NB_MMU_MODES 3
375ee38b BS	219	typedef struct trap_state {
	220	uint64_t tpc;
	221	uint64_t tnpc;
	222	uint64_t tstate;
	223	uint32_t tt;
	224	} trap_state;
6f27aba6	225	#endif
6ebbf390	226
5578ceab BS	227	typedef struct sparc_def_t {
	228	const char *name;
	229	target_ulong iu_version;
	230	uint32_t fpu_version;
	231	uint32_t mmu_version;
	232	uint32_t mmu_bm;
	233	uint32_t mmu_ctpr_mask;
	234	uint32_t mmu_cxr_mask;
	235	uint32_t mmu_sfsr_mask;
	236	uint32_t mmu_trcr_mask;
963262de	237	uint32_t mxcc_version;
5578ceab BS	238	uint32_t features;
	239	uint32_t nwindows;
	240	uint32_t maxtl;
	241	} sparc_def_t;
	242
	243	#define CPU_FEATURE_FLOAT (1 << 0)
	244	#define CPU_FEATURE_FLOAT128 (1 << 1)
	245	#define CPU_FEATURE_SWAP (1 << 2)
	246	#define CPU_FEATURE_MUL (1 << 3)
	247	#define CPU_FEATURE_DIV (1 << 4)
	248	#define CPU_FEATURE_FLUSH (1 << 5)
	249	#define CPU_FEATURE_FSQRT (1 << 6)
	250	#define CPU_FEATURE_FMUL (1 << 7)
	251	#define CPU_FEATURE_VIS1 (1 << 8)
	252	#define CPU_FEATURE_VIS2 (1 << 9)
	253	#define CPU_FEATURE_FSMULD (1 << 10)
	254	#define CPU_FEATURE_HYPV (1 << 11)
	255	#define CPU_FEATURE_CMT (1 << 12)
	256	#define CPU_FEATURE_GL (1 << 13)
	257	#ifndef TARGET_SPARC64
	258	#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT \| CPU_FEATURE_SWAP \| \
	259	CPU_FEATURE_MUL \| CPU_FEATURE_DIV \| \
	260	CPU_FEATURE_FLUSH \| CPU_FEATURE_FSQRT \| \
	261	CPU_FEATURE_FMUL \| CPU_FEATURE_FSMULD)
	262	#else
	263	#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT \| CPU_FEATURE_SWAP \| \
	264	CPU_FEATURE_MUL \| CPU_FEATURE_DIV \| \
	265	CPU_FEATURE_FLUSH \| CPU_FEATURE_FSQRT \| \
	266	CPU_FEATURE_FMUL \| CPU_FEATURE_VIS1 \| \
	267	CPU_FEATURE_VIS2 \| CPU_FEATURE_FSMULD)
	268	enum {
	269	mmu_us_12, // Ultrasparc < III (64 entry TLB)
	270	mmu_us_3, // Ultrasparc III (512 entry TLB)
	271	mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages)
	272	mmu_sun4v, // T1, T2
	273	};
	274	#endif
	275
7a3f1944	276	typedef struct CPUSPARCState {
af7bf89b FB	277	target_ulong gregs[8]; /* general registers */
af7bf89b FB	278	target_ulong regwptr; / pointer to current register window */
af7bf89b FB	279	target_ulong pc; /* program counter */
	280	target_ulong npc; /* next program counter */
	281	target_ulong y; /* multiply/divide register */
dc99a3f2 BS	282
dc99a3f2 BS	283	/* emulator internal flags handling */
d9bdab86	284	target_ulong cc_src, cc_src2;
dc99a3f2	285	target_ulong cc_dst;
8393617c	286	uint32_t cc_op;
dc99a3f2	287
7c60cc4b FB	288	target_ulong t0, t1; /* temporaries live across basic blocks */
	289	target_ulong cond; /* conditional branch result (XXX: save it in a
	290	temporary register when possible) */
	291
cf495bcf	292	uint32_t psr; /* processor state register */
3475187d	293	target_ulong fsr; /* FPU state register */
7c60cc4b	294	float32 fpr[TARGET_FPREGS]; /* floating point registers */
cf495bcf FB	295	uint32_t cwp; /* index of current register window (extracted
cf495bcf FB	296	from PSR) */
5210977a	297	#if !defined(TARGET_SPARC64) \|\| defined(TARGET_ABI32)
cf495bcf	298	uint32_t wim; /* window invalid mask */
5210977a	299	#endif
3475187d	300	target_ulong tbr; /* trap base register */
e8af50a3 FB	301	int psrs; /* supervisor mode (extracted from PSR) */
e8af50a3 FB	302	int psrps; /* previous supervisor mode */
5210977a	303	#if !defined(TARGET_SPARC64)
e8af50a3	304	int psret; /* enable traps */
5210977a	305	#endif
327ac2e7 BS	306	uint32_t psrpil; /* interrupt blocking level */
327ac2e7 BS	307	uint32_t pil_in; /* incoming interrupt level bitmap */
e80cfcfc	308	int psref; /* enable fpu */
62724a37	309	target_ulong version;
cf495bcf	310	int interrupt_index;
1a14026e	311	uint32_t nwindows;
cf495bcf	312	/* NOTE: we allow 8 more registers to handle wrapping */
1a14026e	313	target_ulong regbase[MAX_NWINDOWS * 16 + 8];
d720b93d	314
a316d335 FB	315	CPU_COMMON
a316d335 FB	316
e8af50a3	317	/* MMU regs */
3475187d FB	318	#if defined(TARGET_SPARC64)
	319	uint64_t lsu;
	320	#define DMMU_E 0x8
	321	#define IMMU_E 0x4
	322	uint64_t immuregs[16];
	323	uint64_t dmmuregs[16];
	324	uint64_t itlb_tag[64];
	325	uint64_t itlb_tte[64];
	326	uint64_t dtlb_tag[64];
	327	uint64_t dtlb_tte[64];
fb79ceb9	328	uint32_t mmu_version;
3475187d	329	#else
3dd9a152	330	uint32_t mmuregs[32];
952a328f BS	331	uint64_t mxccdata[4];
952a328f BS	332	uint64_t mxccregs[8];
4017190e	333	uint64_t mmubpregs[4];
3ebf5aaf	334	uint64_t prom_addr;
3475187d	335	#endif
e8af50a3	336	/* temporary float registers */
65ce8c2f	337	float64 dt0, dt1;
1f587329	338	float128 qt0, qt1;
7a0e1f41	339	float_status fp_status;
af7bf89b	340	#if defined(TARGET_SPARC64)
c19148bd BS	341	#define MAXTL_MAX 8
c19148bd BS	342	#define MAXTL_MASK (MAXTL_MAX - 1)
375ee38b	343	trap_state *tsptr;
c19148bd	344	trap_state ts[MAXTL_MAX];
0f8a249a	345	uint32_t xcc; /* Extended integer condition codes */
3475187d FB	346	uint32_t asi;
	347	uint32_t pstate;
	348	uint32_t tl;
c19148bd	349	uint32_t maxtl;
3475187d	350	uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
83469015 FB	351	uint64_t agregs[8]; /* alternate general registers */
	352	uint64_t bgregs[8]; /* backup for normal global registers */
	353	uint64_t igregs[8]; /* interrupt general registers */
	354	uint64_t mgregs[8]; /* mmu general registers */
3475187d	355	uint64_t fprs;
83469015	356	uint64_t tick_cmpr, stick_cmpr;
20c9f095	357	void tick, stick;
725cb90b	358	uint64_t gsr;
e9ebed4d BS	359	uint32_t gl; // UA2005
e9ebed4d BS	360	/* UA 2005 hyperprivileged registers */
c19148bd	361	uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
20c9f095	362	void *hstick; // UA 2005
9d926598	363	uint32_t softint;
8fa211e8 BS	364	#define SOFTINT_TIMER 1
8fa211e8 BS	365	#define SOFTINT_STIMER (1 << 16)
3475187d	366	#endif
5578ceab	367	sparc_def_t *def;
7a3f1944	368	} CPUSPARCState;
64a88d5d	369
91736d37	370	/* helper.c */
aaed909a	371	CPUSPARCState cpu_sparc_init(const char cpu_model);
91736d37	372	void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
62724a37 BS	373	void sparc_cpu_list (FILE f, int (cpu_fprintf)(FILE f, const char fmt,
62724a37 BS	374	...));
48585ec5 BS	375	void cpu_lock(void);
	376	void cpu_unlock(void);
	377	int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
	378	int mmu_idx, int is_softmmu);
	379	target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
	380	void dump_mmu(CPUSPARCState *env);
91736d37 BS	381
	382	/* translate.c */
	383	void gen_intermediate_code_init(CPUSPARCState *env);
	384
	385	/* cpu-exec.c */
	386	int cpu_sparc_exec(CPUSPARCState *s);
7a3f1944	387
5210977a	388	#if !defined (TARGET_SPARC64)
62724a37	389	#define GET_PSR(env) (env->version \| (env->psr & PSR_ICC) \| \
0f8a249a BS	390	(env->psref? PSR_EF : 0) \| \
	391	(env->psrpil << 8) \| \
	392	(env->psrs? PSR_S : 0) \| \
	393	(env->psrps? PSR_PS : 0) \| \
	394	(env->psret? PSR_ET : 0) \| env->cwp)
5210977a IK	395	#else
	396	#define GET_PSR(env) (env->version \| (env->psr & PSR_ICC) \| \
	397	(env->psref? PSR_EF : 0) \| \
	398	(env->psrpil << 8) \| \
	399	(env->psrs? PSR_S : 0) \| \
	400	(env->psrps? PSR_PS : 0) \| \
	401	env->cwp)
	402	#endif
b4ff5987 FB	403
b4ff5987 FB	404	#ifndef NO_CPU_IO_DEFS
91736d37 BS	405	static inline void memcpy32(target_ulong dst, const target_ulong src)
	406	{
	407	dst[0] = src[0];
	408	dst[1] = src[1];
	409	dst[2] = src[2];
	410	dst[3] = src[3];
	411	dst[4] = src[4];
	412	dst[5] = src[5];
	413	dst[6] = src[6];
	414	dst[7] = src[7];
	415	}
	416
	417	static inline void cpu_set_cwp(CPUSPARCState *env1, int new_cwp)
	418	{
	419	/* put the modified wrap registers at their proper location */
	420	if (env1->cwp == env1->nwindows - 1)
	421	memcpy32(env1->regbase, env1->regbase + env1->nwindows * 16);
	422	env1->cwp = new_cwp;
	423	/* put the wrap registers at their temporary location */
	424	if (new_cwp == env1->nwindows - 1)
	425	memcpy32(env1->regbase + env1->nwindows * 16, env1->regbase);
	426	env1->regwptr = env1->regbase + (new_cwp * 16);
	427	}
1a14026e BS	428
	429	static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp)
	430	{
	431	if (unlikely(cwp >= env1->nwindows))
	432	cwp -= env1->nwindows;
	433	return cwp;
	434	}
	435
	436	static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
	437	{
	438	if (unlikely(cwp < 0))
	439	cwp += env1->nwindows;
	440	return cwp;
	441	}
b4ff5987 FB	442	#endif
b4ff5987 FB	443
5210977a	444	#if !defined (TARGET_SPARC64)
0f8a249a BS	445	#define PUT_PSR(env, val) do { int _tmp = val; \
	446	env->psr = _tmp & PSR_ICC; \
	447	env->psref = (_tmp & PSR_EF)? 1 : 0; \
	448	env->psrpil = (_tmp & PSR_PIL) >> 8; \
	449	env->psrs = (_tmp & PSR_S)? 1 : 0; \
	450	env->psrps = (_tmp & PSR_PS)? 1 : 0; \
	451	env->psret = (_tmp & PSR_ET)? 1 : 0; \
d4218d99	452	cpu_set_cwp(env, _tmp & PSR_CWP); \
8393617c	453	CC_OP = CC_OP_FLAGS; \
b4ff5987	454	} while (0)
5210977a IK	455	#else
	456	#define PUT_PSR(env, val) do { int _tmp = val; \
	457	env->psr = _tmp & PSR_ICC; \
	458	env->psref = (_tmp & PSR_EF)? 1 : 0; \
	459	env->psrpil = (_tmp & PSR_PIL) >> 8; \
	460	env->psrs = (_tmp & PSR_S)? 1 : 0; \
	461	env->psrps = (_tmp & PSR_PS)? 1 : 0; \
	462	cpu_set_cwp(env, _tmp & PSR_CWP); \
	463	CC_OP = CC_OP_FLAGS; \
	464	} while (0)
	465	#endif
b4ff5987	466
3475187d	467	#ifdef TARGET_SPARC64
17d996e1	468	#define GET_CCR(env) (((env->xcc >> 20) << 4) \| ((env->psr & PSR_ICC) >> 20))
0f8a249a	469	#define PUT_CCR(env, val) do { int _tmp = val; \
77f193da	470	env->xcc = (_tmp >> 4) << 20; \
0f8a249a	471	env->psr = (_tmp & 0xf) << 20; \
8393617c	472	CC_OP = CC_OP_FLAGS; \
3475187d	473	} while (0)
1a14026e BS	474	#define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp)
1a14026e BS	475
0bbd4a0d	476	#ifndef NO_CPU_IO_DEFS
1a14026e BS	477	static inline void PUT_CWP64(CPUSPARCState *env1, int cwp)
	478	{
	479	if (unlikely(cwp >= env1->nwindows \|\| cwp < 0))
	480	cwp = 0;
	481	cpu_set_cwp(env1, env1->nwindows - 1 - cwp);
	482	}
0bbd4a0d	483	#endif
3475187d FB	484	#endif
3475187d FB	485
91736d37	486	/* cpu-exec.c */
5dcb6b91	487	void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
e18231a3	488	int is_asi, int size);
f0d5e471	489	int cpu_sparc_signal_handler(int host_signum, void pinfo, void puc);
7a3f1944	490
9467d44c TS	491	#define cpu_init cpu_sparc_init
	492	#define cpu_exec cpu_sparc_exec
	493	#define cpu_gen_code cpu_sparc_gen_code
	494	#define cpu_signal_handler cpu_sparc_signal_handler
c732abe2	495	#define cpu_list sparc_cpu_list
9467d44c	496
0b8f1b10	497	#define CPU_SAVE_VERSION 5
b3c7724c	498
6ebbf390	499	/* MMU modes definitions */
6f27aba6 BS	500	#define MMU_MODE0_SUFFIX _user
	501	#define MMU_MODE1_SUFFIX _kernel
	502	#ifdef TARGET_SPARC64
	503	#define MMU_MODE2_SUFFIX _hypv
	504	#endif
9e31b9e2 BS	505	#define MMU_USER_IDX 0
	506	#define MMU_KERNEL_IDX 1
	507	#define MMU_HYPV_IDX 2
	508
22548760	509	static inline int cpu_mmu_index(CPUState *env1)
6ebbf390	510	{
6f27aba6	511	#if defined(CONFIG_USER_ONLY)
9e31b9e2	512	return MMU_USER_IDX;
6f27aba6	513	#elif !defined(TARGET_SPARC64)
22548760	514	return env1->psrs;
6f27aba6	515	#else
22548760	516	if (!env1->psrs)
9e31b9e2	517	return MMU_USER_IDX;
22548760	518	else if ((env1->hpstate & HS_PRIV) == 0)
9e31b9e2	519	return MMU_KERNEL_IDX;
6f27aba6	520	else
9e31b9e2	521	return MMU_HYPV_IDX;
6f27aba6 BS	522	#endif
	523	}
	524
22548760	525	static inline int cpu_fpu_enabled(CPUState *env1)
6f27aba6 BS	526	{
	527	#if defined(CONFIG_USER_ONLY)
	528	return 1;
	529	#elif !defined(TARGET_SPARC64)
22548760	530	return env1->psref;
6f27aba6	531	#else
22548760	532	return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0);
6f27aba6	533	#endif
6ebbf390 JM	534	}
6ebbf390 JM	535
6e68e076 PB	536	#if defined(CONFIG_USER_ONLY)
	537	static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
	538	{
f8ed7070	539	if (newsp)
6e68e076 PB	540	env->regwptr[22] = newsp;
	541	env->regwptr[0] = 0;
	542	/* FIXME: Do we also need to clear CF? */
	543	/* XXXXX */
	544	printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
	545	}
	546	#endif
	547
7a3f1944	548	#include "cpu-all.h"
622ed360	549	#include "exec-all.h"
7a3f1944	550
48585ec5 BS	551	/* sum4m.c, sun4u.c */
	552	void cpu_check_irqs(CPUSPARCState *env);
	553
f4b1a842 BS	554	#ifdef TARGET_SPARC64
	555	/* sun4u.c */
	556	void cpu_tick_set_count(void *opaque, uint64_t count);
	557	uint64_t cpu_tick_get_count(void *opaque);
	558	void cpu_tick_set_limit(void *opaque, uint64_t limit);
	559	#endif
	560
622ed360 AL	561	static inline void cpu_pc_from_tb(CPUState env, TranslationBlock tb)
	562	{
	563	env->pc = tb->pc;
	564	env->npc = tb->cs_base;
	565	}
	566
6b917547 AL	567	static inline void cpu_get_tb_cpu_state(CPUState env, target_ulong pc,
	568	target_ulong cs_base, int flags)
	569	{
	570	*pc = env->pc;
	571	*cs_base = env->npc;
	572	#ifdef TARGET_SPARC64
	573	// AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
	574	*flags = ((env->pstate & PS_AM) << 2)
	575	\| (((env->pstate & PS_PEF) >> 1) \| ((env->fprs & FPRS_FEF) << 2))
	576	\| (env->pstate & PS_PRIV) \| ((env->lsu & (DMMU_E \| IMMU_E)) >> 2);
	577	#else
	578	// FPU enable . Supervisor
	579	*flags = (env->psref << 4) \| env->psrs;
	580	#endif
	581	}
	582
7a3f1944	583	#endif