[qemu.git] / target-sparc / cpu.h

#ifndef CPU_SPARC_H
#define CPU_SPARC_H

#include "config.h"

#if !defined(TARGET_SPARC64)
#define TARGET_LONG_BITS 32
#define TARGET_FPREGS 32
#define TARGET_PAGE_BITS 12 /* 4k */
#else
#define TARGET_LONG_BITS 64
#define TARGET_FPREGS 64
#define TARGET_PAGE_BITS 13 /* 8k */
#endif

#define TARGET_PHYS_ADDR_BITS 64

#include "cpu-defs.h"

#include "softfloat.h"

#define TARGET_HAS_ICE 1

#if !defined(TARGET_SPARC64)
#define ELF_MACHINE     EM_SPARC
#else
#define ELF_MACHINE     EM_SPARCV9
#endif

/*#define EXCP_INTERRUPT 0x100*/

/* trap definitions */
#ifndef TARGET_SPARC64
#define TT_TFAULT   0x01
#define TT_ILL_INSN 0x02
#define TT_PRIV_INSN 0x03
#define TT_NFPU_INSN 0x04
#define TT_WIN_OVF  0x05
#define TT_WIN_UNF  0x06
#define TT_UNALIGNED 0x07
#define TT_FP_EXCP  0x08
#define TT_DFAULT   0x09
#define TT_TOVF     0x0a
#define TT_EXTINT   0x10
#define TT_CODE_ACCESS 0x21
#define TT_DATA_ACCESS 0x29
#define TT_DIV_ZERO 0x2a
#define TT_NCP_INSN 0x24
#define TT_TRAP     0x80
#else
#define TT_TFAULT   0x08
#define TT_TMISS    0x09
#define TT_CODE_ACCESS 0x0a
#define TT_ILL_INSN 0x10
#define TT_PRIV_INSN 0x11
#define TT_NFPU_INSN 0x20
#define TT_FP_EXCP  0x21
#define TT_TOVF     0x23
#define TT_CLRWIN   0x24
#define TT_DIV_ZERO 0x28
#define TT_DFAULT   0x30
#define TT_DMISS    0x31
#define TT_DATA_ACCESS 0x32
#define TT_DPROT    0x33
#define TT_UNALIGNED 0x34
#define TT_PRIV_ACT 0x37
#define TT_EXTINT   0x40
#define TT_SPILL    0x80
#define TT_FILL     0xc0
#define TT_WOTHER   0x10
#define TT_TRAP     0x100
#endif

#define PSR_NEG   (1<<23)
#define PSR_ZERO  (1<<22)
#define PSR_OVF   (1<<21)
#define PSR_CARRY (1<<20)
#define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
#define PSR_EF    (1<<12)
#define PSR_PIL   0xf00
#define PSR_S     (1<<7)
#define PSR_PS    (1<<6)
#define PSR_ET    (1<<5)
#define PSR_CWP   0x1f

/* Trap base register */
#define TBR_BASE_MASK 0xfffff000

#if defined(TARGET_SPARC64)
#define PS_IG    (1<<11)
#define PS_MG    (1<<10)
#define PS_RMO   (1<<7)
#define PS_RED   (1<<5)
#define PS_PEF   (1<<4)
#define PS_AM    (1<<3)
#define PS_PRIV  (1<<2)
#define PS_IE    (1<<1)
#define PS_AG    (1<<0)

#define FPRS_FEF (1<<2)

#define HS_PRIV  (1<<2)
#endif

/* Fcc */
#define FSR_RD1        (1<<31)
#define FSR_RD0        (1<<30)
#define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
#define FSR_RD_NEAREST 0
#define FSR_RD_ZERO    FSR_RD0
#define FSR_RD_POS     FSR_RD1
#define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)

#define FSR_NVM   (1<<27)
#define FSR_OFM   (1<<26)
#define FSR_UFM   (1<<25)
#define FSR_DZM   (1<<24)
#define FSR_NXM   (1<<23)
#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)

#define FSR_NVA   (1<<9)
#define FSR_OFA   (1<<8)
#define FSR_UFA   (1<<7)
#define FSR_DZA   (1<<6)
#define FSR_NXA   (1<<5)
#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)

#define FSR_NVC   (1<<4)
#define FSR_OFC   (1<<3)
#define FSR_UFC   (1<<2)
#define FSR_DZC   (1<<1)
#define FSR_NXC   (1<<0)
#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)

#define FSR_FTT2   (1<<16)
#define FSR_FTT1   (1<<15)
#define FSR_FTT0   (1<<14)
#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
#define FSR_FTT_IEEE_EXCP (1 << 14)
#define FSR_FTT_UNIMPFPOP (3 << 14)
#define FSR_FTT_SEQ_ERROR (4 << 14)
#define FSR_FTT_INVAL_FPR (6 << 14)

#define FSR_FCC1  (1<<11)
#define FSR_FCC0  (1<<10)

/* MMU */
#define MMU_E     (1<<0)
#define MMU_NF    (1<<1)

#define PTE_ENTRYTYPE_MASK 3
#define PTE_ACCESS_MASK    0x1c
#define PTE_ACCESS_SHIFT   2
#define PTE_PPN_SHIFT      7
#define PTE_ADDR_MASK      0xffffff00

#define PG_ACCESSED_BIT 5
#define PG_MODIFIED_BIT 6
#define PG_CACHE_BIT    7

#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
#define PG_CACHE_MASK    (1 << PG_CACHE_BIT)

/* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
#define NWINDOWS  8

#if !defined(TARGET_SPARC64)
#define NB_MMU_MODES 2
#else
#define NB_MMU_MODES 3
#endif

typedef struct CPUSPARCState {
    target_ulong gregs[8]; /* general registers */
    target_ulong *regwptr; /* pointer to current register window */
    float32 fpr[TARGET_FPREGS];  /* floating point registers */
    target_ulong pc;       /* program counter */
    target_ulong npc;      /* next program counter */
    target_ulong y;        /* multiply/divide register */
    uint32_t psr;      /* processor state register */
    target_ulong fsr;      /* FPU state register */
    uint32_t cwp;      /* index of current register window (extracted
                          from PSR) */
    uint32_t wim;      /* window invalid mask */
    target_ulong tbr;  /* trap base register */
    int      psrs;     /* supervisor mode (extracted from PSR) */
    int      psrps;    /* previous supervisor mode */
    int      psret;    /* enable traps */
    uint32_t psrpil;   /* interrupt blocking level */
    uint32_t pil_in;   /* incoming interrupt level bitmap */
    int      psref;    /* enable fpu */
    target_ulong version;
    jmp_buf  jmp_env;
    int user_mode_only;
    int exception_index;
    int interrupt_index;
    int interrupt_request;
    int halted;
    uint32_t mmu_bm;
    /* NOTE: we allow 8 more registers to handle wrapping */
    target_ulong regbase[NWINDOWS * 16 + 8];

    CPU_COMMON

    /* MMU regs */
#if defined(TARGET_SPARC64)
    uint64_t lsu;
#define DMMU_E 0x8
#define IMMU_E 0x4
    uint64_t immuregs[16];
    uint64_t dmmuregs[16];
    uint64_t itlb_tag[64];
    uint64_t itlb_tte[64];
    uint64_t dtlb_tag[64];
    uint64_t dtlb_tte[64];
#else
    uint32_t mmuregs[16];
    uint64_t mxccdata[4];
    uint64_t mxccregs[8];
#endif
    /* temporary float registers */
    float32 ft0, ft1;
    float64 dt0, dt1;
    float_status fp_status;
#if defined(TARGET_SPARC64)
#define MAXTL 4
    uint64_t t0, t1, t2;
    uint64_t tpc[MAXTL];
    uint64_t tnpc[MAXTL];
    uint64_t tstate[MAXTL];
    uint32_t tt[MAXTL];
    uint32_t xcc;               /* Extended integer condition codes */
    uint32_t asi;
    uint32_t pstate;
    uint32_t tl;
    uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
    uint64_t agregs[8]; /* alternate general registers */
    uint64_t bgregs[8]; /* backup for normal global registers */
    uint64_t igregs[8]; /* interrupt general registers */
    uint64_t mgregs[8]; /* mmu general registers */
    uint64_t fprs;
    uint64_t tick_cmpr, stick_cmpr;
    void *tick, *stick;
    uint64_t gsr;
    uint32_t gl; // UA2005
    /* UA 2005 hyperprivileged registers */
    uint64_t hpstate, htstate[MAXTL], hintp, htba, hver, hstick_cmpr, ssr;
    void *hstick; // UA 2005
#endif
#if !defined(TARGET_SPARC64) && !defined(reg_T2)
    target_ulong t2;
#endif
} CPUSPARCState;
#if defined(TARGET_SPARC64)
#define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
#define PUT_FSR32(env, val) do { uint32_t _tmp = val;                   \
        env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL);  \
    } while (0)
#define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
#define PUT_FSR64(env, val) do { uint64_t _tmp = val;   \
        env->fsr = _tmp & 0x3fcfc1c3ffULL;              \
    } while (0)
#else
#define GET_FSR32(env) (env->fsr)
#define PUT_FSR32(env, val) do { uint32_t _tmp = val;                   \
        env->fsr = (_tmp & 0xcfc1dfff) | (env->fsr & 0x000e0000);       \
    } while (0)
#endif

CPUSPARCState *cpu_sparc_init(const char *cpu_model);
int cpu_sparc_exec(CPUSPARCState *s);
int cpu_sparc_close(CPUSPARCState *s);
void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
                                                 ...));
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);

#define GET_PSR(env) (env->version | (env->psr & PSR_ICC) |             \
                      (env->psref? PSR_EF : 0) |                        \
                      (env->psrpil << 8) |                              \
                      (env->psrs? PSR_S : 0) |                          \
                      (env->psrps? PSR_PS : 0) |                        \
                      (env->psret? PSR_ET : 0) | env->cwp)

#ifndef NO_CPU_IO_DEFS
void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
#endif

#define PUT_PSR(env, val) do { int _tmp = val;                          \
        env->psr = _tmp & PSR_ICC;                                      \
        env->psref = (_tmp & PSR_EF)? 1 : 0;                            \
        env->psrpil = (_tmp & PSR_PIL) >> 8;                            \
        env->psrs = (_tmp & PSR_S)? 1 : 0;                              \
        env->psrps = (_tmp & PSR_PS)? 1 : 0;                            \
        env->psret = (_tmp & PSR_ET)? 1 : 0;                            \
        cpu_set_cwp(env, _tmp & PSR_CWP);                               \
    } while (0)

#ifdef TARGET_SPARC64
#define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
#define PUT_CCR(env, val) do { int _tmp = val;                          \
        env->xcc = (_tmp >> 4) << 20;                                           \
        env->psr = (_tmp & 0xf) << 20;                                  \
    } while (0)
#define GET_CWP64(env) (NWINDOWS - 1 - (env)->cwp)
#define PUT_CWP64(env, val) \
    cpu_set_cwp(env, NWINDOWS - 1 - ((val) & (NWINDOWS - 1)))

#endif

int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
void raise_exception(int tt);
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
                          int is_asi);
void do_tick_set_count(void *opaque, uint64_t count);
uint64_t do_tick_get_count(void *opaque);
void do_tick_set_limit(void *opaque, uint64_t limit);
void cpu_check_irqs(CPUSPARCState *env);

#define CPUState CPUSPARCState
#define cpu_init cpu_sparc_init
#define cpu_exec cpu_sparc_exec
#define cpu_gen_code cpu_sparc_gen_code
#define cpu_signal_handler cpu_sparc_signal_handler
#define cpu_list sparc_cpu_list

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _user
#define MMU_MODE1_SUFFIX _kernel
#ifdef TARGET_SPARC64
#define MMU_MODE2_SUFFIX _hypv
#endif
#define MMU_USER_IDX 0
static inline int cpu_mmu_index (CPUState *env)
{
#if defined(CONFIG_USER_ONLY)
    return 0;
#elif !defined(TARGET_SPARC64)
    return env->psrs;
#else
    if (!env->psrs)
        return 0;
    else if ((env->hpstate & HS_PRIV) == 0)
        return 1;
    else
        return 2;
#endif
}

static inline int cpu_fpu_enabled(CPUState *env)
{
#if defined(CONFIG_USER_ONLY)
    return 1;
#elif !defined(TARGET_SPARC64)
    return env->psref;
#else
    return ((env->pstate & PS_PEF) != 0) && ((env->fprs & FPRS_FEF) != 0);
#endif
}

#include "cpu-all.h"

#endif
Commit	Line	Data
7a3f1944 FB	1	#ifndef CPU_SPARC_H
	2	#define CPU_SPARC_H
	3
af7bf89b FB	4	#include "config.h"
	5
	6	#if !defined(TARGET_SPARC64)
3cf1e035	7	#define TARGET_LONG_BITS 32
af7bf89b	8	#define TARGET_FPREGS 32
83469015	9	#define TARGET_PAGE_BITS 12 /* 4k */
af7bf89b FB	10	#else
	11	#define TARGET_LONG_BITS 64
	12	#define TARGET_FPREGS 64
33b37802	13	#define TARGET_PAGE_BITS 13 /* 8k */
af7bf89b	14	#endif
3cf1e035	15
92b72cbc BS	16	#define TARGET_PHYS_ADDR_BITS 64
92b72cbc BS	17
7a3f1944 FB	18	#include "cpu-defs.h"
7a3f1944 FB	19
7a0e1f41 FB	20	#include "softfloat.h"
7a0e1f41 FB	21
1fddef4b FB	22	#define TARGET_HAS_ICE 1
1fddef4b FB	23
9042c0e2	24	#if !defined(TARGET_SPARC64)
0f8a249a	25	#define ELF_MACHINE EM_SPARC
9042c0e2	26	#else
0f8a249a	27	#define ELF_MACHINE EM_SPARCV9
9042c0e2 TS	28	#endif
9042c0e2 TS	29
7a3f1944 FB	30	/#define EXCP_INTERRUPT 0x100/
7a3f1944 FB	31
cf495bcf	32	/* trap definitions */
3475187d	33	#ifndef TARGET_SPARC64
878d3096	34	#define TT_TFAULT 0x01
cf495bcf	35	#define TT_ILL_INSN 0x02
e8af50a3	36	#define TT_PRIV_INSN 0x03
e80cfcfc	37	#define TT_NFPU_INSN 0x04
cf495bcf	38	#define TT_WIN_OVF 0x05
5fafdf24	39	#define TT_WIN_UNF 0x06
d2889a3e	40	#define TT_UNALIGNED 0x07
e8af50a3	41	#define TT_FP_EXCP 0x08
878d3096	42	#define TT_DFAULT 0x09
e32f879d	43	#define TT_TOVF 0x0a
878d3096	44	#define TT_EXTINT 0x10
1b2e93c1	45	#define TT_CODE_ACCESS 0x21
b4f0a316	46	#define TT_DATA_ACCESS 0x29
cf495bcf	47	#define TT_DIV_ZERO 0x2a
fcc72045	48	#define TT_NCP_INSN 0x24
cf495bcf	49	#define TT_TRAP 0x80
3475187d FB	50	#else
3475187d FB	51	#define TT_TFAULT 0x08
83469015	52	#define TT_TMISS 0x09
1b2e93c1	53	#define TT_CODE_ACCESS 0x0a
3475187d FB	54	#define TT_ILL_INSN 0x10
	55	#define TT_PRIV_INSN 0x11
	56	#define TT_NFPU_INSN 0x20
	57	#define TT_FP_EXCP 0x21
e32f879d	58	#define TT_TOVF 0x23
3475187d FB	59	#define TT_CLRWIN 0x24
	60	#define TT_DIV_ZERO 0x28
	61	#define TT_DFAULT 0x30
83469015	62	#define TT_DMISS 0x31
b4f0a316 BS	63	#define TT_DATA_ACCESS 0x32
b4f0a316 BS	64	#define TT_DPROT 0x33
d2889a3e	65	#define TT_UNALIGNED 0x34
83469015	66	#define TT_PRIV_ACT 0x37
3475187d FB	67	#define TT_EXTINT 0x40
	68	#define TT_SPILL 0x80
	69	#define TT_FILL 0xc0
	70	#define TT_WOTHER 0x10
	71	#define TT_TRAP 0x100
	72	#endif
7a3f1944 FB	73
	74	#define PSR_NEG (1<<23)
	75	#define PSR_ZERO (1<<22)
	76	#define PSR_OVF (1<<21)
	77	#define PSR_CARRY (1<<20)
e8af50a3	78	#define PSR_ICC (PSR_NEG\|PSR_ZERO\|PSR_OVF\|PSR_CARRY)
e80cfcfc FB	79	#define PSR_EF (1<<12)
e80cfcfc FB	80	#define PSR_PIL 0xf00
e8af50a3 FB	81	#define PSR_S (1<<7)
	82	#define PSR_PS (1<<6)
	83	#define PSR_ET (1<<5)
	84	#define PSR_CWP 0x1f
e8af50a3 FB	85
	86	/* Trap base register */
	87	#define TBR_BASE_MASK 0xfffff000
	88
3475187d	89	#if defined(TARGET_SPARC64)
83469015 FB	90	#define PS_IG (1<<11)
83469015 FB	91	#define PS_MG (1<<10)
6ef905f6	92	#define PS_RMO (1<<7)
83469015	93	#define PS_RED (1<<5)
3475187d FB	94	#define PS_PEF (1<<4)
	95	#define PS_AM (1<<3)
	96	#define PS_PRIV (1<<2)
	97	#define PS_IE (1<<1)
83469015	98	#define PS_AG (1<<0)
a80dde08 FB	99
a80dde08 FB	100	#define FPRS_FEF (1<<2)
6f27aba6 BS	101
6f27aba6 BS	102	#define HS_PRIV (1<<2)
3475187d FB	103	#endif
3475187d FB	104
e8af50a3 FB	105	/* Fcc */
	106	#define FSR_RD1 (1<<31)
	107	#define FSR_RD0 (1<<30)
	108	#define FSR_RD_MASK (FSR_RD1 \| FSR_RD0)
	109	#define FSR_RD_NEAREST 0
	110	#define FSR_RD_ZERO FSR_RD0
	111	#define FSR_RD_POS FSR_RD1
	112	#define FSR_RD_NEG (FSR_RD1 \| FSR_RD0)
	113
	114	#define FSR_NVM (1<<27)
	115	#define FSR_OFM (1<<26)
	116	#define FSR_UFM (1<<25)
	117	#define FSR_DZM (1<<24)
	118	#define FSR_NXM (1<<23)
	119	#define FSR_TEM_MASK (FSR_NVM \| FSR_OFM \| FSR_UFM \| FSR_DZM \| FSR_NXM)
	120
	121	#define FSR_NVA (1<<9)
	122	#define FSR_OFA (1<<8)
	123	#define FSR_UFA (1<<7)
	124	#define FSR_DZA (1<<6)
	125	#define FSR_NXA (1<<5)
	126	#define FSR_AEXC_MASK (FSR_NVA \| FSR_OFA \| FSR_UFA \| FSR_DZA \| FSR_NXA)
	127
	128	#define FSR_NVC (1<<4)
	129	#define FSR_OFC (1<<3)
	130	#define FSR_UFC (1<<2)
	131	#define FSR_DZC (1<<1)
	132	#define FSR_NXC (1<<0)
	133	#define FSR_CEXC_MASK (FSR_NVC \| FSR_OFC \| FSR_UFC \| FSR_DZC \| FSR_NXC)
	134
	135	#define FSR_FTT2 (1<<16)
	136	#define FSR_FTT1 (1<<15)
	137	#define FSR_FTT0 (1<<14)
	138	#define FSR_FTT_MASK (FSR_FTT2 \| FSR_FTT1 \| FSR_FTT0)
e80cfcfc FB	139	#define FSR_FTT_IEEE_EXCP (1 << 14)
e80cfcfc FB	140	#define FSR_FTT_UNIMPFPOP (3 << 14)
9143e598	141	#define FSR_FTT_SEQ_ERROR (4 << 14)
e80cfcfc	142	#define FSR_FTT_INVAL_FPR (6 << 14)
e8af50a3 FB	143
	144	#define FSR_FCC1 (1<<11)
	145	#define FSR_FCC0 (1<<10)
	146
	147	/* MMU */
0f8a249a BS	148	#define MMU_E (1<<0)
0f8a249a BS	149	#define MMU_NF (1<<1)
e8af50a3 FB	150
	151	#define PTE_ENTRYTYPE_MASK 3
	152	#define PTE_ACCESS_MASK 0x1c
	153	#define PTE_ACCESS_SHIFT 2
8d5f07fa	154	#define PTE_PPN_SHIFT 7
e8af50a3 FB	155	#define PTE_ADDR_MASK 0xffffff00
e8af50a3 FB	156
0f8a249a BS	157	#define PG_ACCESSED_BIT 5
0f8a249a BS	158	#define PG_MODIFIED_BIT 6
e8af50a3 FB	159	#define PG_CACHE_BIT 7
	160
	161	#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
	162	#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
	163	#define PG_CACHE_MASK (1 << PG_CACHE_BIT)
	164
1d6e34fd FB	165	/* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
1d6e34fd FB	166	#define NWINDOWS 8
cf495bcf	167
6f27aba6	168	#if !defined(TARGET_SPARC64)
6ebbf390	169	#define NB_MMU_MODES 2
6f27aba6 BS	170	#else
	171	#define NB_MMU_MODES 3
	172	#endif
6ebbf390	173
7a3f1944	174	typedef struct CPUSPARCState {
af7bf89b FB	175	target_ulong gregs[8]; /* general registers */
af7bf89b FB	176	target_ulong regwptr; / pointer to current register window */
65ce8c2f	177	float32 fpr[TARGET_FPREGS]; /* floating point registers */
af7bf89b FB	178	target_ulong pc; /* program counter */
	179	target_ulong npc; /* next program counter */
	180	target_ulong y; /* multiply/divide register */
cf495bcf	181	uint32_t psr; /* processor state register */
3475187d	182	target_ulong fsr; /* FPU state register */
cf495bcf FB	183	uint32_t cwp; /* index of current register window (extracted
	184	from PSR) */
	185	uint32_t wim; /* window invalid mask */
3475187d	186	target_ulong tbr; /* trap base register */
e8af50a3 FB	187	int psrs; /* supervisor mode (extracted from PSR) */
	188	int psrps; /* previous supervisor mode */
	189	int psret; /* enable traps */
327ac2e7 BS	190	uint32_t psrpil; /* interrupt blocking level */
327ac2e7 BS	191	uint32_t pil_in; /* incoming interrupt level bitmap */
e80cfcfc	192	int psref; /* enable fpu */
62724a37	193	target_ulong version;
cf495bcf FB	194	jmp_buf jmp_env;
	195	int user_mode_only;
	196	int exception_index;
	197	int interrupt_index;
	198	int interrupt_request;
ba3c64fb	199	int halted;
6d5f237a	200	uint32_t mmu_bm;
cf495bcf	201	/* NOTE: we allow 8 more registers to handle wrapping */
af7bf89b	202	target_ulong regbase[NWINDOWS * 16 + 8];
d720b93d	203
a316d335 FB	204	CPU_COMMON
a316d335 FB	205
e8af50a3	206	/* MMU regs */
3475187d FB	207	#if defined(TARGET_SPARC64)
	208	uint64_t lsu;
	209	#define DMMU_E 0x8
	210	#define IMMU_E 0x4
	211	uint64_t immuregs[16];
	212	uint64_t dmmuregs[16];
	213	uint64_t itlb_tag[64];
	214	uint64_t itlb_tte[64];
	215	uint64_t dtlb_tag[64];
	216	uint64_t dtlb_tte[64];
	217	#else
e8af50a3	218	uint32_t mmuregs[16];
952a328f BS	219	uint64_t mxccdata[4];
952a328f BS	220	uint64_t mxccregs[8];
3475187d	221	#endif
e8af50a3	222	/* temporary float registers */
65ce8c2f FB	223	float32 ft0, ft1;
65ce8c2f FB	224	float64 dt0, dt1;
7a0e1f41	225	float_status fp_status;
af7bf89b	226	#if defined(TARGET_SPARC64)
3475187d FB	227	#define MAXTL 4
	228	uint64_t t0, t1, t2;
	229	uint64_t tpc[MAXTL];
	230	uint64_t tnpc[MAXTL];
	231	uint64_t tstate[MAXTL];
	232	uint32_t tt[MAXTL];
0f8a249a	233	uint32_t xcc; /* Extended integer condition codes */
3475187d FB	234	uint32_t asi;
	235	uint32_t pstate;
	236	uint32_t tl;
	237	uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
83469015 FB	238	uint64_t agregs[8]; /* alternate general registers */
	239	uint64_t bgregs[8]; /* backup for normal global registers */
	240	uint64_t igregs[8]; /* interrupt general registers */
	241	uint64_t mgregs[8]; /* mmu general registers */
3475187d	242	uint64_t fprs;
83469015	243	uint64_t tick_cmpr, stick_cmpr;
20c9f095	244	void tick, stick;
725cb90b	245	uint64_t gsr;
e9ebed4d BS	246	uint32_t gl; // UA2005
	247	/* UA 2005 hyperprivileged registers */
	248	uint64_t hpstate, htstate[MAXTL], hintp, htba, hver, hstick_cmpr, ssr;
20c9f095	249	void *hstick; // UA 2005
3475187d FB	250	#endif
	251	#if !defined(TARGET_SPARC64) && !defined(reg_T2)
	252	target_ulong t2;
af7bf89b	253	#endif
7a3f1944	254	} CPUSPARCState;
3475187d FB	255	#if defined(TARGET_SPARC64)
3475187d FB	256	#define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
0f8a249a BS	257	#define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
0f8a249a BS	258	env->fsr = (_tmp & 0xcfc1c3ff) \| (env->fsr & 0x3f00000000ULL); \
3475187d FB	259	} while (0)
3475187d FB	260	#define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
0f8a249a BS	261	#define PUT_FSR64(env, val) do { uint64_t _tmp = val; \
0f8a249a BS	262	env->fsr = _tmp & 0x3fcfc1c3ffULL; \
3475187d	263	} while (0)
3475187d FB	264	#else
3475187d FB	265	#define GET_FSR32(env) (env->fsr)
3e736bf4	266	#define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
9143e598	267	env->fsr = (_tmp & 0xcfc1dfff) \| (env->fsr & 0x000e0000); \
3475187d FB	268	} while (0)
3475187d FB	269	#endif
7a3f1944	270
aaed909a	271	CPUSPARCState cpu_sparc_init(const char cpu_model);
7a3f1944 FB	272	int cpu_sparc_exec(CPUSPARCState *s);
7a3f1944 FB	273	int cpu_sparc_close(CPUSPARCState *s);
62724a37 BS	274	void sparc_cpu_list (FILE f, int (cpu_fprintf)(FILE f, const char fmt,
62724a37 BS	275	...));
aaed909a	276	void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
7a3f1944	277
62724a37	278	#define GET_PSR(env) (env->version \| (env->psr & PSR_ICC) \| \
0f8a249a BS	279	(env->psref? PSR_EF : 0) \| \
	280	(env->psrpil << 8) \| \
	281	(env->psrs? PSR_S : 0) \| \
	282	(env->psrps? PSR_PS : 0) \| \
	283	(env->psret? PSR_ET : 0) \| env->cwp)
b4ff5987 FB	284
	285	#ifndef NO_CPU_IO_DEFS
	286	void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
	287	#endif
	288
0f8a249a BS	289	#define PUT_PSR(env, val) do { int _tmp = val; \
	290	env->psr = _tmp & PSR_ICC; \
	291	env->psref = (_tmp & PSR_EF)? 1 : 0; \
	292	env->psrpil = (_tmp & PSR_PIL) >> 8; \
	293	env->psrs = (_tmp & PSR_S)? 1 : 0; \
	294	env->psrps = (_tmp & PSR_PS)? 1 : 0; \
	295	env->psret = (_tmp & PSR_ET)? 1 : 0; \
d4218d99	296	cpu_set_cwp(env, _tmp & PSR_CWP); \
b4ff5987 FB	297	} while (0)
b4ff5987 FB	298
3475187d	299	#ifdef TARGET_SPARC64
17d996e1	300	#define GET_CCR(env) (((env->xcc >> 20) << 4) \| ((env->psr & PSR_ICC) >> 20))
0f8a249a BS	301	#define PUT_CCR(env, val) do { int _tmp = val; \
	302	env->xcc = (_tmp >> 4) << 20; \
	303	env->psr = (_tmp & 0xf) << 20; \
3475187d	304	} while (0)
17d996e1	305	#define GET_CWP64(env) (NWINDOWS - 1 - (env)->cwp)
8f1f22f6 BS	306	#define PUT_CWP64(env, val) \
8f1f22f6 BS	307	cpu_set_cwp(env, NWINDOWS - 1 - ((val) & (NWINDOWS - 1)))
17d996e1	308
3475187d FB	309	#endif
3475187d FB	310
5a7b542b	311	int cpu_sparc_signal_handler(int host_signum, void pinfo, void puc);
b4f0a316	312	void raise_exception(int tt);
5dcb6b91	313	void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
6c36d3fa	314	int is_asi);
20c9f095 BS	315	void do_tick_set_count(void *opaque, uint64_t count);
	316	uint64_t do_tick_get_count(void *opaque);
	317	void do_tick_set_limit(void *opaque, uint64_t limit);
327ac2e7	318	void cpu_check_irqs(CPUSPARCState *env);
7a3f1944	319
9467d44c TS	320	#define CPUState CPUSPARCState
	321	#define cpu_init cpu_sparc_init
	322	#define cpu_exec cpu_sparc_exec
	323	#define cpu_gen_code cpu_sparc_gen_code
	324	#define cpu_signal_handler cpu_sparc_signal_handler
c732abe2	325	#define cpu_list sparc_cpu_list
9467d44c	326
6ebbf390	327	/* MMU modes definitions */
6f27aba6 BS	328	#define MMU_MODE0_SUFFIX _user
	329	#define MMU_MODE1_SUFFIX _kernel
	330	#ifdef TARGET_SPARC64
	331	#define MMU_MODE2_SUFFIX _hypv
	332	#endif
	333	#define MMU_USER_IDX 0
6ebbf390 JM	334	static inline int cpu_mmu_index (CPUState *env)
6ebbf390 JM	335	{
6f27aba6 BS	336	#if defined(CONFIG_USER_ONLY)
	337	return 0;
	338	#elif !defined(TARGET_SPARC64)
	339	return env->psrs;
	340	#else
	341	if (!env->psrs)
	342	return 0;
	343	else if ((env->hpstate & HS_PRIV) == 0)
	344	return 1;
	345	else
	346	return 2;
	347	#endif
	348	}
	349
	350	static inline int cpu_fpu_enabled(CPUState *env)
	351	{
	352	#if defined(CONFIG_USER_ONLY)
	353	return 1;
	354	#elif !defined(TARGET_SPARC64)
	355	return env->psref;
	356	#else
	357	return ((env->pstate & PS_PEF) != 0) && ((env->fprs & FPRS_FEF) != 0);
	358	#endif
6ebbf390 JM	359	}
6ebbf390 JM	360
7a3f1944 FB	361	#include "cpu-all.h"
	362
	363	#endif