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7a3f1944 FB |
1 | #ifndef CPU_SPARC_H |
2 | #define CPU_SPARC_H | |
3 | ||
af7bf89b FB |
4 | #include "config.h" |
5 | ||
6 | #if !defined(TARGET_SPARC64) | |
3cf1e035 | 7 | #define TARGET_LONG_BITS 32 |
af7bf89b | 8 | #define TARGET_FPREGS 32 |
83469015 | 9 | #define TARGET_PAGE_BITS 12 /* 4k */ |
af7bf89b FB |
10 | #else |
11 | #define TARGET_LONG_BITS 64 | |
12 | #define TARGET_FPREGS 64 | |
33b37802 | 13 | #define TARGET_PAGE_BITS 13 /* 8k */ |
af7bf89b | 14 | #endif |
3cf1e035 | 15 | |
92b72cbc BS |
16 | #define TARGET_PHYS_ADDR_BITS 64 |
17 | ||
7a3f1944 FB |
18 | #include "cpu-defs.h" |
19 | ||
7a0e1f41 FB |
20 | #include "softfloat.h" |
21 | ||
1fddef4b FB |
22 | #define TARGET_HAS_ICE 1 |
23 | ||
9042c0e2 | 24 | #if !defined(TARGET_SPARC64) |
0f8a249a | 25 | #define ELF_MACHINE EM_SPARC |
9042c0e2 | 26 | #else |
0f8a249a | 27 | #define ELF_MACHINE EM_SPARCV9 |
9042c0e2 TS |
28 | #endif |
29 | ||
7a3f1944 FB |
30 | /*#define EXCP_INTERRUPT 0x100*/ |
31 | ||
cf495bcf | 32 | /* trap definitions */ |
3475187d | 33 | #ifndef TARGET_SPARC64 |
878d3096 | 34 | #define TT_TFAULT 0x01 |
cf495bcf | 35 | #define TT_ILL_INSN 0x02 |
e8af50a3 | 36 | #define TT_PRIV_INSN 0x03 |
e80cfcfc | 37 | #define TT_NFPU_INSN 0x04 |
cf495bcf | 38 | #define TT_WIN_OVF 0x05 |
5fafdf24 | 39 | #define TT_WIN_UNF 0x06 |
d2889a3e | 40 | #define TT_UNALIGNED 0x07 |
e8af50a3 | 41 | #define TT_FP_EXCP 0x08 |
878d3096 | 42 | #define TT_DFAULT 0x09 |
e32f879d | 43 | #define TT_TOVF 0x0a |
878d3096 | 44 | #define TT_EXTINT 0x10 |
1b2e93c1 | 45 | #define TT_CODE_ACCESS 0x21 |
64a88d5d | 46 | #define TT_UNIMP_FLUSH 0x25 |
b4f0a316 | 47 | #define TT_DATA_ACCESS 0x29 |
cf495bcf | 48 | #define TT_DIV_ZERO 0x2a |
fcc72045 | 49 | #define TT_NCP_INSN 0x24 |
cf495bcf | 50 | #define TT_TRAP 0x80 |
3475187d FB |
51 | #else |
52 | #define TT_TFAULT 0x08 | |
1b2e93c1 | 53 | #define TT_CODE_ACCESS 0x0a |
3475187d | 54 | #define TT_ILL_INSN 0x10 |
64a88d5d | 55 | #define TT_UNIMP_FLUSH TT_ILL_INSN |
3475187d FB |
56 | #define TT_PRIV_INSN 0x11 |
57 | #define TT_NFPU_INSN 0x20 | |
58 | #define TT_FP_EXCP 0x21 | |
e32f879d | 59 | #define TT_TOVF 0x23 |
3475187d FB |
60 | #define TT_CLRWIN 0x24 |
61 | #define TT_DIV_ZERO 0x28 | |
62 | #define TT_DFAULT 0x30 | |
b4f0a316 BS |
63 | #define TT_DATA_ACCESS 0x32 |
64 | #define TT_DPROT 0x33 | |
d2889a3e | 65 | #define TT_UNALIGNED 0x34 |
83469015 | 66 | #define TT_PRIV_ACT 0x37 |
3475187d | 67 | #define TT_EXTINT 0x40 |
e19e4efe BS |
68 | #define TT_TMISS 0x64 |
69 | #define TT_DMISS 0x68 | |
3475187d FB |
70 | #define TT_SPILL 0x80 |
71 | #define TT_FILL 0xc0 | |
72 | #define TT_WOTHER 0x10 | |
73 | #define TT_TRAP 0x100 | |
74 | #endif | |
7a3f1944 | 75 | |
4b8b8b76 BS |
76 | #define PSR_NEG_SHIFT 23 |
77 | #define PSR_NEG (1 << PSR_NEG_SHIFT) | |
78 | #define PSR_ZERO_SHIFT 22 | |
79 | #define PSR_ZERO (1 << PSR_ZERO_SHIFT) | |
80 | #define PSR_OVF_SHIFT 21 | |
81 | #define PSR_OVF (1 << PSR_OVF_SHIFT) | |
82 | #define PSR_CARRY_SHIFT 20 | |
83 | #define PSR_CARRY (1 << PSR_CARRY_SHIFT) | |
e8af50a3 | 84 | #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) |
e80cfcfc FB |
85 | #define PSR_EF (1<<12) |
86 | #define PSR_PIL 0xf00 | |
e8af50a3 FB |
87 | #define PSR_S (1<<7) |
88 | #define PSR_PS (1<<6) | |
89 | #define PSR_ET (1<<5) | |
90 | #define PSR_CWP 0x1f | |
e8af50a3 FB |
91 | |
92 | /* Trap base register */ | |
93 | #define TBR_BASE_MASK 0xfffff000 | |
94 | ||
3475187d | 95 | #if defined(TARGET_SPARC64) |
83469015 FB |
96 | #define PS_IG (1<<11) |
97 | #define PS_MG (1<<10) | |
6ef905f6 | 98 | #define PS_RMO (1<<7) |
83469015 | 99 | #define PS_RED (1<<5) |
3475187d FB |
100 | #define PS_PEF (1<<4) |
101 | #define PS_AM (1<<3) | |
102 | #define PS_PRIV (1<<2) | |
103 | #define PS_IE (1<<1) | |
83469015 | 104 | #define PS_AG (1<<0) |
a80dde08 FB |
105 | |
106 | #define FPRS_FEF (1<<2) | |
6f27aba6 BS |
107 | |
108 | #define HS_PRIV (1<<2) | |
3475187d FB |
109 | #endif |
110 | ||
e8af50a3 FB |
111 | /* Fcc */ |
112 | #define FSR_RD1 (1<<31) | |
113 | #define FSR_RD0 (1<<30) | |
114 | #define FSR_RD_MASK (FSR_RD1 | FSR_RD0) | |
115 | #define FSR_RD_NEAREST 0 | |
116 | #define FSR_RD_ZERO FSR_RD0 | |
117 | #define FSR_RD_POS FSR_RD1 | |
118 | #define FSR_RD_NEG (FSR_RD1 | FSR_RD0) | |
119 | ||
120 | #define FSR_NVM (1<<27) | |
121 | #define FSR_OFM (1<<26) | |
122 | #define FSR_UFM (1<<25) | |
123 | #define FSR_DZM (1<<24) | |
124 | #define FSR_NXM (1<<23) | |
125 | #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) | |
126 | ||
127 | #define FSR_NVA (1<<9) | |
128 | #define FSR_OFA (1<<8) | |
129 | #define FSR_UFA (1<<7) | |
130 | #define FSR_DZA (1<<6) | |
131 | #define FSR_NXA (1<<5) | |
132 | #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) | |
133 | ||
134 | #define FSR_NVC (1<<4) | |
135 | #define FSR_OFC (1<<3) | |
136 | #define FSR_UFC (1<<2) | |
137 | #define FSR_DZC (1<<1) | |
138 | #define FSR_NXC (1<<0) | |
139 | #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) | |
140 | ||
141 | #define FSR_FTT2 (1<<16) | |
142 | #define FSR_FTT1 (1<<15) | |
143 | #define FSR_FTT0 (1<<14) | |
144 | #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) | |
e80cfcfc FB |
145 | #define FSR_FTT_IEEE_EXCP (1 << 14) |
146 | #define FSR_FTT_UNIMPFPOP (3 << 14) | |
9143e598 | 147 | #define FSR_FTT_SEQ_ERROR (4 << 14) |
e80cfcfc | 148 | #define FSR_FTT_INVAL_FPR (6 << 14) |
e8af50a3 | 149 | |
4b8b8b76 BS |
150 | #define FSR_FCC1_SHIFT 11 |
151 | #define FSR_FCC1 (1 << FSR_FCC1_SHIFT) | |
152 | #define FSR_FCC0_SHIFT 10 | |
153 | #define FSR_FCC0 (1 << FSR_FCC0_SHIFT) | |
e8af50a3 FB |
154 | |
155 | /* MMU */ | |
0f8a249a BS |
156 | #define MMU_E (1<<0) |
157 | #define MMU_NF (1<<1) | |
e8af50a3 FB |
158 | |
159 | #define PTE_ENTRYTYPE_MASK 3 | |
160 | #define PTE_ACCESS_MASK 0x1c | |
161 | #define PTE_ACCESS_SHIFT 2 | |
8d5f07fa | 162 | #define PTE_PPN_SHIFT 7 |
e8af50a3 FB |
163 | #define PTE_ADDR_MASK 0xffffff00 |
164 | ||
0f8a249a BS |
165 | #define PG_ACCESSED_BIT 5 |
166 | #define PG_MODIFIED_BIT 6 | |
e8af50a3 FB |
167 | #define PG_CACHE_BIT 7 |
168 | ||
169 | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) | |
170 | #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) | |
171 | #define PG_CACHE_MASK (1 << PG_CACHE_BIT) | |
172 | ||
1a14026e BS |
173 | /* 3 <= NWINDOWS <= 32. */ |
174 | #define MIN_NWINDOWS 3 | |
175 | #define MAX_NWINDOWS 32 | |
cf495bcf | 176 | |
6f27aba6 | 177 | #if !defined(TARGET_SPARC64) |
6ebbf390 | 178 | #define NB_MMU_MODES 2 |
6f27aba6 BS |
179 | #else |
180 | #define NB_MMU_MODES 3 | |
375ee38b BS |
181 | typedef struct trap_state { |
182 | uint64_t tpc; | |
183 | uint64_t tnpc; | |
184 | uint64_t tstate; | |
185 | uint32_t tt; | |
186 | } trap_state; | |
6f27aba6 | 187 | #endif |
6ebbf390 | 188 | |
7a3f1944 | 189 | typedef struct CPUSPARCState { |
af7bf89b FB |
190 | target_ulong gregs[8]; /* general registers */ |
191 | target_ulong *regwptr; /* pointer to current register window */ | |
af7bf89b FB |
192 | target_ulong pc; /* program counter */ |
193 | target_ulong npc; /* next program counter */ | |
194 | target_ulong y; /* multiply/divide register */ | |
dc99a3f2 BS |
195 | |
196 | /* emulator internal flags handling */ | |
d9bdab86 | 197 | target_ulong cc_src, cc_src2; |
dc99a3f2 BS |
198 | target_ulong cc_dst; |
199 | ||
7c60cc4b FB |
200 | target_ulong t0, t1; /* temporaries live across basic blocks */ |
201 | target_ulong cond; /* conditional branch result (XXX: save it in a | |
202 | temporary register when possible) */ | |
203 | ||
cf495bcf | 204 | uint32_t psr; /* processor state register */ |
3475187d | 205 | target_ulong fsr; /* FPU state register */ |
7c60cc4b | 206 | float32 fpr[TARGET_FPREGS]; /* floating point registers */ |
cf495bcf FB |
207 | uint32_t cwp; /* index of current register window (extracted |
208 | from PSR) */ | |
209 | uint32_t wim; /* window invalid mask */ | |
3475187d | 210 | target_ulong tbr; /* trap base register */ |
e8af50a3 FB |
211 | int psrs; /* supervisor mode (extracted from PSR) */ |
212 | int psrps; /* previous supervisor mode */ | |
213 | int psret; /* enable traps */ | |
327ac2e7 BS |
214 | uint32_t psrpil; /* interrupt blocking level */ |
215 | uint32_t pil_in; /* incoming interrupt level bitmap */ | |
e80cfcfc | 216 | int psref; /* enable fpu */ |
62724a37 | 217 | target_ulong version; |
cf495bcf | 218 | int interrupt_index; |
6d5f237a | 219 | uint32_t mmu_bm; |
3deaeab7 BS |
220 | uint32_t mmu_ctpr_mask; |
221 | uint32_t mmu_cxr_mask; | |
222 | uint32_t mmu_sfsr_mask; | |
223 | uint32_t mmu_trcr_mask; | |
1a14026e | 224 | uint32_t nwindows; |
cf495bcf | 225 | /* NOTE: we allow 8 more registers to handle wrapping */ |
1a14026e | 226 | target_ulong regbase[MAX_NWINDOWS * 16 + 8]; |
d720b93d | 227 | |
a316d335 FB |
228 | CPU_COMMON |
229 | ||
e8af50a3 | 230 | /* MMU regs */ |
3475187d FB |
231 | #if defined(TARGET_SPARC64) |
232 | uint64_t lsu; | |
233 | #define DMMU_E 0x8 | |
234 | #define IMMU_E 0x4 | |
235 | uint64_t immuregs[16]; | |
236 | uint64_t dmmuregs[16]; | |
237 | uint64_t itlb_tag[64]; | |
238 | uint64_t itlb_tte[64]; | |
239 | uint64_t dtlb_tag[64]; | |
240 | uint64_t dtlb_tte[64]; | |
fb79ceb9 | 241 | uint32_t mmu_version; |
3475187d | 242 | #else |
3dd9a152 | 243 | uint32_t mmuregs[32]; |
952a328f BS |
244 | uint64_t mxccdata[4]; |
245 | uint64_t mxccregs[8]; | |
3ebf5aaf | 246 | uint64_t prom_addr; |
3475187d | 247 | #endif |
e8af50a3 | 248 | /* temporary float registers */ |
65ce8c2f FB |
249 | float32 ft0, ft1; |
250 | float64 dt0, dt1; | |
1f587329 | 251 | float128 qt0, qt1; |
7a0e1f41 | 252 | float_status fp_status; |
af7bf89b | 253 | #if defined(TARGET_SPARC64) |
3475187d | 254 | #define MAXTL 4 |
375ee38b BS |
255 | trap_state *tsptr; |
256 | trap_state ts[MAXTL]; | |
0f8a249a | 257 | uint32_t xcc; /* Extended integer condition codes */ |
3475187d FB |
258 | uint32_t asi; |
259 | uint32_t pstate; | |
260 | uint32_t tl; | |
261 | uint32_t cansave, canrestore, otherwin, wstate, cleanwin; | |
83469015 FB |
262 | uint64_t agregs[8]; /* alternate general registers */ |
263 | uint64_t bgregs[8]; /* backup for normal global registers */ | |
264 | uint64_t igregs[8]; /* interrupt general registers */ | |
265 | uint64_t mgregs[8]; /* mmu general registers */ | |
3475187d | 266 | uint64_t fprs; |
83469015 | 267 | uint64_t tick_cmpr, stick_cmpr; |
20c9f095 | 268 | void *tick, *stick; |
725cb90b | 269 | uint64_t gsr; |
e9ebed4d BS |
270 | uint32_t gl; // UA2005 |
271 | /* UA 2005 hyperprivileged registers */ | |
272 | uint64_t hpstate, htstate[MAXTL], hintp, htba, hver, hstick_cmpr, ssr; | |
20c9f095 | 273 | void *hstick; // UA 2005 |
3475187d | 274 | #endif |
64a88d5d | 275 | uint32_t features; |
7a3f1944 | 276 | } CPUSPARCState; |
64a88d5d BS |
277 | |
278 | #define CPU_FEATURE_FLOAT (1 << 0) | |
279 | #define CPU_FEATURE_FLOAT128 (1 << 1) | |
280 | #define CPU_FEATURE_SWAP (1 << 2) | |
281 | #define CPU_FEATURE_MUL (1 << 3) | |
282 | #define CPU_FEATURE_DIV (1 << 4) | |
283 | #define CPU_FEATURE_FLUSH (1 << 5) | |
284 | #define CPU_FEATURE_FSQRT (1 << 6) | |
285 | #define CPU_FEATURE_FMUL (1 << 7) | |
286 | #define CPU_FEATURE_VIS1 (1 << 8) | |
287 | #define CPU_FEATURE_VIS2 (1 << 9) | |
e30b4678 | 288 | #define CPU_FEATURE_FSMULD (1 << 10) |
fb79ceb9 BS |
289 | #define CPU_FEATURE_HYPV (1 << 11) |
290 | #define CPU_FEATURE_CMT (1 << 12) | |
291 | #define CPU_FEATURE_GL (1 << 13) | |
64a88d5d BS |
292 | #ifndef TARGET_SPARC64 |
293 | #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ | |
294 | CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ | |
295 | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ | |
e30b4678 | 296 | CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD) |
64a88d5d BS |
297 | #else |
298 | #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ | |
299 | CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ | |
300 | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ | |
301 | CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \ | |
e30b4678 | 302 | CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD) |
fb79ceb9 BS |
303 | enum { |
304 | mmu_us_12, // Ultrasparc < III (64 entry TLB) | |
305 | mmu_us_3, // Ultrasparc III (512 entry TLB) | |
306 | mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages) | |
307 | mmu_sun4v, // T1, T2 | |
308 | }; | |
64a88d5d BS |
309 | #endif |
310 | ||
3475187d FB |
311 | #if defined(TARGET_SPARC64) |
312 | #define GET_FSR32(env) (env->fsr & 0xcfc1ffff) | |
0f8a249a BS |
313 | #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \ |
314 | env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \ | |
3475187d FB |
315 | } while (0) |
316 | #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL) | |
0f8a249a BS |
317 | #define PUT_FSR64(env, val) do { uint64_t _tmp = val; \ |
318 | env->fsr = _tmp & 0x3fcfc1c3ffULL; \ | |
3475187d | 319 | } while (0) |
3475187d FB |
320 | #else |
321 | #define GET_FSR32(env) (env->fsr) | |
3e736bf4 | 322 | #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \ |
9143e598 | 323 | env->fsr = (_tmp & 0xcfc1dfff) | (env->fsr & 0x000e0000); \ |
3475187d FB |
324 | } while (0) |
325 | #endif | |
7a3f1944 | 326 | |
aaed909a | 327 | CPUSPARCState *cpu_sparc_init(const char *cpu_model); |
c48fcb47 | 328 | void gen_intermediate_code_init(CPUSPARCState *env); |
7a3f1944 | 329 | int cpu_sparc_exec(CPUSPARCState *s); |
62724a37 BS |
330 | void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, |
331 | ...)); | |
aaed909a | 332 | void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); |
7a3f1944 | 333 | |
62724a37 | 334 | #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \ |
0f8a249a BS |
335 | (env->psref? PSR_EF : 0) | \ |
336 | (env->psrpil << 8) | \ | |
337 | (env->psrs? PSR_S : 0) | \ | |
338 | (env->psrps? PSR_PS : 0) | \ | |
339 | (env->psret? PSR_ET : 0) | env->cwp) | |
b4ff5987 FB |
340 | |
341 | #ifndef NO_CPU_IO_DEFS | |
342 | void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); | |
1a14026e BS |
343 | |
344 | static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp) | |
345 | { | |
346 | if (unlikely(cwp >= env1->nwindows)) | |
347 | cwp -= env1->nwindows; | |
348 | return cwp; | |
349 | } | |
350 | ||
351 | static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp) | |
352 | { | |
353 | if (unlikely(cwp < 0)) | |
354 | cwp += env1->nwindows; | |
355 | return cwp; | |
356 | } | |
b4ff5987 FB |
357 | #endif |
358 | ||
0f8a249a BS |
359 | #define PUT_PSR(env, val) do { int _tmp = val; \ |
360 | env->psr = _tmp & PSR_ICC; \ | |
361 | env->psref = (_tmp & PSR_EF)? 1 : 0; \ | |
362 | env->psrpil = (_tmp & PSR_PIL) >> 8; \ | |
363 | env->psrs = (_tmp & PSR_S)? 1 : 0; \ | |
364 | env->psrps = (_tmp & PSR_PS)? 1 : 0; \ | |
365 | env->psret = (_tmp & PSR_ET)? 1 : 0; \ | |
d4218d99 | 366 | cpu_set_cwp(env, _tmp & PSR_CWP); \ |
b4ff5987 FB |
367 | } while (0) |
368 | ||
3475187d | 369 | #ifdef TARGET_SPARC64 |
17d996e1 | 370 | #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20)) |
0f8a249a | 371 | #define PUT_CCR(env, val) do { int _tmp = val; \ |
77f193da | 372 | env->xcc = (_tmp >> 4) << 20; \ |
0f8a249a | 373 | env->psr = (_tmp & 0xf) << 20; \ |
3475187d | 374 | } while (0) |
1a14026e BS |
375 | #define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp) |
376 | ||
0bbd4a0d | 377 | #ifndef NO_CPU_IO_DEFS |
1a14026e BS |
378 | static inline void PUT_CWP64(CPUSPARCState *env1, int cwp) |
379 | { | |
380 | if (unlikely(cwp >= env1->nwindows || cwp < 0)) | |
381 | cwp = 0; | |
382 | cpu_set_cwp(env1, env1->nwindows - 1 - cwp); | |
383 | } | |
0bbd4a0d | 384 | #endif |
3475187d FB |
385 | #endif |
386 | ||
5a7b542b | 387 | int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); |
5dcb6b91 | 388 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
6c36d3fa | 389 | int is_asi); |
327ac2e7 | 390 | void cpu_check_irqs(CPUSPARCState *env); |
7a3f1944 | 391 | |
9467d44c TS |
392 | #define CPUState CPUSPARCState |
393 | #define cpu_init cpu_sparc_init | |
394 | #define cpu_exec cpu_sparc_exec | |
395 | #define cpu_gen_code cpu_sparc_gen_code | |
396 | #define cpu_signal_handler cpu_sparc_signal_handler | |
c732abe2 | 397 | #define cpu_list sparc_cpu_list |
9467d44c | 398 | |
b3c7724c PB |
399 | #define CPU_SAVE_VERSION 4 |
400 | ||
6ebbf390 | 401 | /* MMU modes definitions */ |
6f27aba6 BS |
402 | #define MMU_MODE0_SUFFIX _user |
403 | #define MMU_MODE1_SUFFIX _kernel | |
404 | #ifdef TARGET_SPARC64 | |
405 | #define MMU_MODE2_SUFFIX _hypv | |
406 | #endif | |
9e31b9e2 BS |
407 | #define MMU_USER_IDX 0 |
408 | #define MMU_KERNEL_IDX 1 | |
409 | #define MMU_HYPV_IDX 2 | |
410 | ||
22548760 | 411 | static inline int cpu_mmu_index(CPUState *env1) |
6ebbf390 | 412 | { |
6f27aba6 | 413 | #if defined(CONFIG_USER_ONLY) |
9e31b9e2 | 414 | return MMU_USER_IDX; |
6f27aba6 | 415 | #elif !defined(TARGET_SPARC64) |
22548760 | 416 | return env1->psrs; |
6f27aba6 | 417 | #else |
22548760 | 418 | if (!env1->psrs) |
9e31b9e2 | 419 | return MMU_USER_IDX; |
22548760 | 420 | else if ((env1->hpstate & HS_PRIV) == 0) |
9e31b9e2 | 421 | return MMU_KERNEL_IDX; |
6f27aba6 | 422 | else |
9e31b9e2 | 423 | return MMU_HYPV_IDX; |
6f27aba6 BS |
424 | #endif |
425 | } | |
426 | ||
22548760 | 427 | static inline int cpu_fpu_enabled(CPUState *env1) |
6f27aba6 BS |
428 | { |
429 | #if defined(CONFIG_USER_ONLY) | |
430 | return 1; | |
431 | #elif !defined(TARGET_SPARC64) | |
22548760 | 432 | return env1->psref; |
6f27aba6 | 433 | #else |
22548760 | 434 | return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0); |
6f27aba6 | 435 | #endif |
6ebbf390 JM |
436 | } |
437 | ||
6e68e076 PB |
438 | #if defined(CONFIG_USER_ONLY) |
439 | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) | |
440 | { | |
f8ed7070 | 441 | if (newsp) |
6e68e076 PB |
442 | env->regwptr[22] = newsp; |
443 | env->regwptr[0] = 0; | |
444 | /* FIXME: Do we also need to clear CF? */ | |
445 | /* XXXXX */ | |
446 | printf ("HELPME: %s:%d\n", __FILE__, __LINE__); | |
447 | } | |
448 | #endif | |
449 | ||
2e70f6ef PB |
450 | #define CPU_PC_FROM_TB(env, tb) do { \ |
451 | env->pc = tb->pc; \ | |
452 | env->npc = tb->cs_base; \ | |
453 | } while(0) | |
454 | ||
7a3f1944 FB |
455 | #include "cpu-all.h" |
456 | ||
457 | #endif |