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7a3f1944 FB |
1 | #ifndef EXEC_SPARC_H |
2 | #define EXEC_SPARC_H 1 | |
3475187d | 3 | #include "config.h" |
8294eba1 | 4 | #include "dyngen-exec.h" |
7a3f1944 FB |
5 | |
6 | register struct CPUSPARCState *env asm(AREG0); | |
01d6a890 | 7 | |
af7bf89b FB |
8 | #ifdef TARGET_SPARC64 |
9 | #define T0 (env->t0) | |
10 | #define T1 (env->t1) | |
11 | #define T2 (env->t2) | |
3475187d | 12 | #define REGWPTR env->regwptr |
af7bf89b | 13 | #else |
7a3f1944 FB |
14 | register uint32_t T0 asm(AREG1); |
15 | register uint32_t T1 asm(AREG2); | |
3475187d FB |
16 | |
17 | #undef REG_REGWPTR // Broken | |
18 | #ifdef REG_REGWPTR | |
01d6a890 TS |
19 | #if defined(__sparc__) |
20 | register uint32_t *REGWPTR asm(AREG4); | |
21 | #else | |
3475187d | 22 | register uint32_t *REGWPTR asm(AREG3); |
01d6a890 | 23 | #endif |
3475187d FB |
24 | #define reg_REGWPTR |
25 | ||
26 | #ifdef AREG4 | |
27 | register uint32_t T2 asm(AREG4); | |
28 | #define reg_T2 | |
29 | #else | |
30 | #define T2 (env->t2) | |
31 | #endif | |
32 | ||
33 | #else | |
34 | #define REGWPTR env->regwptr | |
7a3f1944 | 35 | register uint32_t T2 asm(AREG3); |
01d6a890 | 36 | #endif |
3475187d FB |
37 | #define reg_T2 |
38 | #endif | |
3475187d | 39 | |
e8af50a3 FB |
40 | #define FT0 (env->ft0) |
41 | #define FT1 (env->ft1) | |
e8af50a3 FB |
42 | #define DT0 (env->dt0) |
43 | #define DT1 (env->dt1) | |
1f587329 BS |
44 | #if defined(CONFIG_USER_ONLY) |
45 | #define QT0 (env->qt0) | |
46 | #define QT1 (env->qt1) | |
47 | #endif | |
7a3f1944 FB |
48 | |
49 | #include "cpu.h" | |
50 | #include "exec-all.h" | |
51 | ||
52 | void cpu_lock(void); | |
53 | void cpu_unlock(void); | |
54 | void cpu_loop_exit(void); | |
658138bc | 55 | void helper_flush(target_ulong addr); |
e8af50a3 | 56 | void helper_ld_asi(int asi, int size, int sign); |
81ad8ba2 | 57 | void helper_st_asi(int asi, int size); |
3391c818 BS |
58 | void helper_ldf_asi(int asi, int size, int rd); |
59 | void helper_stf_asi(int asi, int size, int rd); | |
e8af50a3 | 60 | void helper_rett(void); |
8d5f07fa | 61 | void helper_ldfsr(void); |
e8af50a3 | 62 | void set_cwp(int new_cwp); |
a0c4cb4a FB |
63 | void do_fitos(void); |
64 | void do_fitod(void); | |
e8af50a3 FB |
65 | void do_fabss(void); |
66 | void do_fsqrts(void); | |
67 | void do_fsqrtd(void); | |
68 | void do_fcmps(void); | |
69 | void do_fcmpd(void); | |
417454b0 BS |
70 | void do_fcmpes(void); |
71 | void do_fcmped(void); | |
1f587329 BS |
72 | #if defined(CONFIG_USER_ONLY) |
73 | void do_fitoq(void); | |
74 | void do_fabsq(void); | |
75 | void do_fsqrtq(void); | |
76 | void do_fcmpq(void); | |
77 | void do_fcmpeq(void); | |
78 | #endif | |
3475187d FB |
79 | #ifdef TARGET_SPARC64 |
80 | void do_fabsd(void); | |
81 | void do_fcmps_fcc1(void); | |
82 | void do_fcmpd_fcc1(void); | |
83 | void do_fcmps_fcc2(void); | |
84 | void do_fcmpd_fcc2(void); | |
85 | void do_fcmps_fcc3(void); | |
86 | void do_fcmpd_fcc3(void); | |
417454b0 BS |
87 | void do_fcmpes_fcc1(void); |
88 | void do_fcmped_fcc1(void); | |
89 | void do_fcmpes_fcc2(void); | |
90 | void do_fcmped_fcc2(void); | |
91 | void do_fcmpes_fcc3(void); | |
92 | void do_fcmped_fcc3(void); | |
1f587329 BS |
93 | #if defined(CONFIG_USER_ONLY) |
94 | void do_fcmpq_fcc1(void); | |
95 | void do_fcmpq_fcc2(void); | |
96 | void do_fcmpq_fcc3(void); | |
97 | void do_fcmpeq_fcc1(void); | |
98 | void do_fcmpeq_fcc2(void); | |
99 | void do_fcmpeq_fcc3(void); | |
100 | #endif | |
3475187d | 101 | void do_popc(); |
83469015 FB |
102 | void do_wrpstate(); |
103 | void do_done(); | |
104 | void do_retry(); | |
3475187d | 105 | #endif |
af7bf89b FB |
106 | void do_ldd_kernel(target_ulong addr); |
107 | void do_ldd_user(target_ulong addr); | |
108 | void do_ldd_raw(target_ulong addr); | |
878d3096 | 109 | void do_interrupt(int intno); |
e8af50a3 | 110 | void raise_exception(int tt); |
417454b0 | 111 | void check_ieee_exceptions(); |
af7bf89b | 112 | void memcpy32(target_ulong *dst, const target_ulong *src); |
ee5bbe38 FB |
113 | target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev); |
114 | void dump_mmu(CPUState *env); | |
e80cfcfc | 115 | void helper_debug(); |
af7bf89b FB |
116 | void do_wrpsr(); |
117 | void do_rdpsr(); | |
e8af50a3 FB |
118 | |
119 | /* XXX: move that to a generic header */ | |
120 | #if !defined(CONFIG_USER_ONLY) | |
a9049a07 | 121 | #include "softmmu_exec.h" |
e8af50a3 | 122 | #endif /* !defined(CONFIG_USER_ONLY) */ |
0d1a29f9 FB |
123 | |
124 | static inline void env_to_regs(void) | |
125 | { | |
aea3ce4c FB |
126 | #if defined(reg_REGWPTR) |
127 | REGWPTR = env->regbase + (env->cwp * 16); | |
128 | env->regwptr = REGWPTR; | |
129 | #endif | |
0d1a29f9 FB |
130 | } |
131 | ||
132 | static inline void regs_to_env(void) | |
133 | { | |
134 | } | |
135 | ||
9d893301 | 136 | int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw, |
6ebbf390 | 137 | int mmu_idx, int is_softmmu); |
9d893301 | 138 | |
bfed01fc TS |
139 | static inline int cpu_halted(CPUState *env) { |
140 | if (!env->halted) | |
141 | return 0; | |
142 | if ((env->interrupt_request & CPU_INTERRUPT_HARD) && (env->psret != 0)) { | |
143 | env->halted = 0; | |
144 | return 0; | |
145 | } | |
146 | return EXCP_HALTED; | |
147 | } | |
148 | ||
7a3f1944 | 149 | #endif |