[qemu.git] / target-sparc / helper.c

/*
 *  sparc helpers
 * 
 *  Copyright (c) 2003-2005 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>
#include <assert.h>

#include "cpu.h"
#include "exec-all.h"

//#define DEBUG_MMU

/* Sparc MMU emulation */

/* thread support */

spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;

void cpu_lock(void)
{
    spin_lock(&global_cpu_lock);
}

void cpu_unlock(void)
{
    spin_unlock(&global_cpu_lock);
}

#if defined(CONFIG_USER_ONLY) 

int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
                               int is_user, int is_softmmu)
{
    if (rw & 2)
        env->exception_index = TT_TFAULT;
    else
        env->exception_index = TT_DFAULT;
    return 1;
}

#else

#ifndef TARGET_SPARC64
/*
 * Sparc V8 Reference MMU (SRMMU)
 */
static const int access_table[8][8] = {
    { 0, 0, 0, 0, 2, 0, 3, 3 },
    { 0, 0, 0, 0, 2, 0, 0, 0 },
    { 2, 2, 0, 0, 0, 2, 3, 3 },
    { 2, 2, 0, 0, 0, 2, 0, 0 },
    { 2, 0, 2, 0, 2, 2, 3, 3 },
    { 2, 0, 2, 0, 2, 0, 2, 0 },
    { 2, 2, 2, 0, 2, 2, 3, 3 },
    { 2, 2, 2, 0, 2, 2, 2, 0 }
};

static const int perm_table[2][8] = {
    {
        PAGE_READ,
        PAGE_READ | PAGE_WRITE,
        PAGE_READ | PAGE_EXEC,
        PAGE_READ | PAGE_WRITE | PAGE_EXEC,
        PAGE_EXEC,
        PAGE_READ | PAGE_WRITE,
        PAGE_READ | PAGE_EXEC,
        PAGE_READ | PAGE_WRITE | PAGE_EXEC
    },
    {
        PAGE_READ,
        PAGE_READ | PAGE_WRITE,
        PAGE_READ | PAGE_EXEC,
        PAGE_READ | PAGE_WRITE | PAGE_EXEC,
        PAGE_EXEC,
        PAGE_READ,
        0,
        0,
    }
};

int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
			  int *access_index, target_ulong address, int rw,
			  int is_user)
{
    int access_perms = 0;
    target_phys_addr_t pde_ptr;
    uint32_t pde;
    target_ulong virt_addr;
    int error_code = 0, is_dirty;
    unsigned long page_offset;

    virt_addr = address & TARGET_PAGE_MASK;
    if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
	*physical = address;
        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
        return 0;
    }

    *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
    *physical = 0xfffff000;

    /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
    /* Context base + context number */
    pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
    pde = ldl_phys(pde_ptr);

    /* Ctx pde */
    switch (pde & PTE_ENTRYTYPE_MASK) {
    default:
    case 0: /* Invalid */
	return 1 << 2;
    case 2: /* L0 PTE, maybe should not happen? */
    case 3: /* Reserved */
        return 4 << 2;
    case 1: /* L0 PDE */
	pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
        pde = ldl_phys(pde_ptr);

	switch (pde & PTE_ENTRYTYPE_MASK) {
	default:
	case 0: /* Invalid */
	    return (1 << 8) | (1 << 2);
	case 3: /* Reserved */
	    return (1 << 8) | (4 << 2);
	case 1: /* L1 PDE */
	    pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
            pde = ldl_phys(pde_ptr);

	    switch (pde & PTE_ENTRYTYPE_MASK) {
	    default:
	    case 0: /* Invalid */
		return (2 << 8) | (1 << 2);
	    case 3: /* Reserved */
		return (2 << 8) | (4 << 2);
	    case 1: /* L2 PDE */
		pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
                pde = ldl_phys(pde_ptr);

		switch (pde & PTE_ENTRYTYPE_MASK) {
		default:
		case 0: /* Invalid */
		    return (3 << 8) | (1 << 2);
		case 1: /* PDE, should not happen */
		case 3: /* Reserved */
		    return (3 << 8) | (4 << 2);
		case 2: /* L3 PTE */
		    virt_addr = address & TARGET_PAGE_MASK;
		    page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
		}
		break;
	    case 2: /* L2 PTE */
		virt_addr = address & ~0x3ffff;
		page_offset = address & 0x3ffff;
	    }
	    break;
	case 2: /* L1 PTE */
	    virt_addr = address & ~0xffffff;
	    page_offset = address & 0xffffff;
	}
    }

    /* update page modified and dirty bits */
    is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
    if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
	pde |= PG_ACCESSED_MASK;
	if (is_dirty)
	    pde |= PG_MODIFIED_MASK;
        stl_phys_notdirty(pde_ptr, pde);
    }
    /* check access */
    access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
    error_code = access_table[*access_index][access_perms];
    if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
	return error_code;

    /* the page can be put in the TLB */
    *prot = perm_table[is_user][access_perms];
    if (!(pde & PG_MODIFIED_MASK)) {
        /* only set write access if already dirty... otherwise wait
           for dirty access */
        *prot &= ~PAGE_WRITE;
    }

    /* Even if large ptes, we map only one 4KB page in the cache to
       avoid filling it too fast */
    *physical = ((pde & PTE_ADDR_MASK) << 4) + page_offset;
    return error_code;
}

/* Perform address translation */
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                              int is_user, int is_softmmu)
{
    target_phys_addr_t paddr;
    unsigned long vaddr;
    int error_code = 0, prot, ret = 0, access_index;

    error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
    if (error_code == 0) {
	vaddr = address & TARGET_PAGE_MASK;
	paddr &= TARGET_PAGE_MASK;
#ifdef DEBUG_MMU
	printf("Translate at 0x%lx -> 0x%lx, vaddr 0x%lx\n", (long)address, (long)paddr, (long)vaddr);
#endif
	ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
	return ret;
    }

    if (env->mmuregs[3]) /* Fault status register */
	env->mmuregs[3] = 1; /* overflow (not read before another fault) */
    env->mmuregs[3] |= (access_index << 5) | error_code | 2;
    env->mmuregs[4] = address; /* Fault address register */

    if ((env->mmuregs[0] & MMU_NF) || env->psret == 0)  {
        // No fault mode: if a mapping is available, just override
        // permissions. If no mapping is available, redirect accesses to
        // neverland. Fake/overridden mappings will be flushed when
        // switching to normal mode.
	vaddr = address & TARGET_PAGE_MASK;
        prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
        ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
	return ret;
    } else {
        if (rw & 2)
            env->exception_index = TT_TFAULT;
        else
            env->exception_index = TT_DFAULT;
        return 1;
    }
}

target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
{
    target_phys_addr_t pde_ptr;
    uint32_t pde;

    /* Context base + context number */
    pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
    pde = ldl_phys(pde_ptr);

    switch (pde & PTE_ENTRYTYPE_MASK) {
    default:
    case 0: /* Invalid */
    case 2: /* PTE, maybe should not happen? */
    case 3: /* Reserved */
	return 0;
    case 1: /* L1 PDE */
	if (mmulev == 3)
	    return pde;
	pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
        pde = ldl_phys(pde_ptr);

	switch (pde & PTE_ENTRYTYPE_MASK) {
	default:
	case 0: /* Invalid */
	case 3: /* Reserved */
	    return 0;
	case 2: /* L1 PTE */
	    return pde;
	case 1: /* L2 PDE */
	    if (mmulev == 2)
		return pde;
	    pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
            pde = ldl_phys(pde_ptr);

	    switch (pde & PTE_ENTRYTYPE_MASK) {
	    default:
	    case 0: /* Invalid */
	    case 3: /* Reserved */
		return 0;
	    case 2: /* L2 PTE */
		return pde;
	    case 1: /* L3 PDE */
		if (mmulev == 1)
		    return pde;
		pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
                pde = ldl_phys(pde_ptr);

		switch (pde & PTE_ENTRYTYPE_MASK) {
		default:
		case 0: /* Invalid */
		case 1: /* PDE, should not happen */
		case 3: /* Reserved */
		    return 0;
		case 2: /* L3 PTE */
		    return pde;
		}
	    }
	}
    }
    return 0;
}

#ifdef DEBUG_MMU
void dump_mmu(CPUState *env)
{
     target_ulong va, va1, va2;
     unsigned int n, m, o;
     target_phys_addr_t pde_ptr, pa;
    uint32_t pde;

    printf("MMU dump:\n");
    pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
    pde = ldl_phys(pde_ptr);
    printf("Root ptr: " TARGET_FMT_lx ", ctx: %d\n", env->mmuregs[1] << 4, env->mmuregs[2]);
    for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
	pde_ptr = mmu_probe(env, va, 2);
	if (pde_ptr) {
	    pa = cpu_get_phys_page_debug(env, va);
 	    printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va, pa, pde_ptr);
	    for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
		pde_ptr = mmu_probe(env, va1, 1);
		if (pde_ptr) {
		    pa = cpu_get_phys_page_debug(env, va1);
 		    printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde_ptr);
		    for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
			pde_ptr = mmu_probe(env, va2, 0);
			if (pde_ptr) {
			    pa = cpu_get_phys_page_debug(env, va2);
 			    printf("  VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PTE: " TARGET_FMT_lx "\n", va2, pa, pde_ptr);
			}
		    }
		}
	    }
	}
    }
    printf("MMU dump ends\n");
}
#endif /* DEBUG_MMU */

#else /* !TARGET_SPARC64 */
/*
 * UltraSparc IIi I/DMMUs
 */
static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot,
			  int *access_index, target_ulong address, int rw,
			  int is_user)
{
    target_ulong mask;
    unsigned int i;

    if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
	*physical = address;
	*prot = PAGE_READ | PAGE_WRITE;
        return 0;
    }

    for (i = 0; i < 64; i++) {
	switch ((env->dtlb_tte[i] >> 61) & 3) {
	default:
	case 0x0: // 8k
	    mask = 0xffffffffffffe000ULL;
	    break;
	case 0x1: // 64k
	    mask = 0xffffffffffff0000ULL;
	    break;
	case 0x2: // 512k
	    mask = 0xfffffffffff80000ULL;
	    break;
	case 0x3: // 4M
	    mask = 0xffffffffffc00000ULL;
	    break;
	}
	// ctx match, vaddr match?
	if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
	    (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
	    // valid, access ok?
	    if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
		((env->dtlb_tte[i] & 0x4) && is_user) ||
		(!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
		if (env->dmmuregs[3]) /* Fault status register */
		    env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
		env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
		env->dmmuregs[4] = address; /* Fault address register */
		env->exception_index = TT_DFAULT;
#ifdef DEBUG_MMU
		printf("DFAULT at 0x%llx\n", address);
#endif
		return 1;
	    }
	    *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
	    *prot = PAGE_READ;
	    if (env->dtlb_tte[i] & 0x2)
		*prot |= PAGE_WRITE;
	    return 0;
	}
    }
#ifdef DEBUG_MMU
    printf("DMISS at 0x%llx\n", address);
#endif
    env->exception_index = TT_DMISS;
    return 1;
}

static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot,
			  int *access_index, target_ulong address, int rw,
			  int is_user)
{
    target_ulong mask;
    unsigned int i;

    if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
	*physical = address;
	*prot = PAGE_EXEC;
        return 0;
    }

    for (i = 0; i < 64; i++) {
	switch ((env->itlb_tte[i] >> 61) & 3) {
	default:
	case 0x0: // 8k
	    mask = 0xffffffffffffe000ULL;
	    break;
	case 0x1: // 64k
	    mask = 0xffffffffffff0000ULL;
	    break;
	case 0x2: // 512k
	    mask = 0xfffffffffff80000ULL;
	    break;
	case 0x3: // 4M
	    mask = 0xffffffffffc00000ULL;
		break;
	}
	// ctx match, vaddr match?
	if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
	    (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
	    // valid, access ok?
	    if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
		((env->itlb_tte[i] & 0x4) && is_user)) {
		if (env->immuregs[3]) /* Fault status register */
		    env->immuregs[3] = 2; /* overflow (not read before another fault) */
		env->immuregs[3] |= (is_user << 3) | 1;
		env->exception_index = TT_TFAULT;
#ifdef DEBUG_MMU
		printf("TFAULT at 0x%llx\n", address);
#endif
		return 1;
	    }
	    *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
	    *prot = PAGE_EXEC;
	    return 0;
	}
    }
#ifdef DEBUG_MMU
    printf("TMISS at 0x%llx\n", address);
#endif
    env->exception_index = TT_TMISS;
    return 1;
}

int get_physical_address(CPUState *env, target_phys_addr_t *physical, int *prot,
			  int *access_index, target_ulong address, int rw,
			  int is_user)
{
    if (rw == 2)
	return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
    else
	return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
}

/* Perform address translation */
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                              int is_user, int is_softmmu)
{
    target_ulong virt_addr, vaddr;
    target_phys_addr_t paddr;
    int error_code = 0, prot, ret = 0, access_index;

    error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
    if (error_code == 0) {
	virt_addr = address & TARGET_PAGE_MASK;
	vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
#ifdef DEBUG_MMU
	printf("Translate at 0x%llx -> 0x%llx, vaddr 0x%llx\n", address, paddr, vaddr);
#endif
	ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
	return ret;
    }
    // XXX
    return 1;
}

#ifdef DEBUG_MMU
void dump_mmu(CPUState *env)
{
    unsigned int i;
    const char *mask;

    printf("MMU contexts: Primary: %lld, Secondary: %lld\n", env->dmmuregs[1], env->dmmuregs[2]);
    if ((env->lsu & DMMU_E) == 0) {
	printf("DMMU disabled\n");
    } else {
	printf("DMMU dump:\n");
	for (i = 0; i < 64; i++) {
	    switch ((env->dtlb_tte[i] >> 61) & 3) {
	    default:
	    case 0x0:
		mask = "  8k";
		break;
	    case 0x1:
		mask = " 64k";
		break;
	    case 0x2:
		mask = "512k";
		break;
	    case 0x3:
		mask = "  4M";
		break;
	    }
	    if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
		printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %lld\n",
		       env->dtlb_tag[i] & ~0x1fffULL,
		       env->dtlb_tte[i] & 0x1ffffffe000ULL,
		       mask,
		       env->dtlb_tte[i] & 0x4? "priv": "user",
		       env->dtlb_tte[i] & 0x2? "RW": "RO",
		       env->dtlb_tte[i] & 0x40? "locked": "unlocked",
		       env->dtlb_tag[i] & 0x1fffULL);
	    }
	}
    }
    if ((env->lsu & IMMU_E) == 0) {
	printf("IMMU disabled\n");
    } else {
	printf("IMMU dump:\n");
	for (i = 0; i < 64; i++) {
	    switch ((env->itlb_tte[i] >> 61) & 3) {
	    default:
	    case 0x0:
		mask = "  8k";
		break;
	    case 0x1:
		mask = " 64k";
		break;
	    case 0x2:
		mask = "512k";
		break;
	    case 0x3:
		mask = "  4M";
		break;
	    }
	    if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
		printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %lld\n",
		       env->itlb_tag[i] & ~0x1fffULL,
		       env->itlb_tte[i] & 0x1ffffffe000ULL,
		       mask,
		       env->itlb_tte[i] & 0x4? "priv": "user",
		       env->itlb_tte[i] & 0x40? "locked": "unlocked",
		       env->itlb_tag[i] & 0x1fffULL);
	    }
	}
    }
}
#endif /* DEBUG_MMU */

#endif /* TARGET_SPARC64 */
#endif /* !CONFIG_USER_ONLY */

void memcpy32(target_ulong *dst, const target_ulong *src)
{
    dst[0] = src[0];
    dst[1] = src[1];
    dst[2] = src[2];
    dst[3] = src[3];
    dst[4] = src[4];
    dst[5] = src[5];
    dst[6] = src[6];
    dst[7] = src[7];
}
Commit	Line	Data
e8af50a3 FB	1	/*
	2	* sparc helpers
	3	*
83469015	4	* Copyright (c) 2003-2005 Fabrice Bellard
e8af50a3 FB	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
ee5bbe38 FB	20	#include <stdarg.h>
	21	#include <stdlib.h>
	22	#include <stdio.h>
	23	#include <string.h>
	24	#include <inttypes.h>
	25	#include <signal.h>
	26	#include <assert.h>
	27
	28	#include "cpu.h"
	29	#include "exec-all.h"
e8af50a3	30
e80cfcfc	31	//#define DEBUG_MMU
e8af50a3	32
e8af50a3	33	/* Sparc MMU emulation */
e8af50a3	34
e8af50a3 FB	35	/* thread support */
	36
	37	spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
	38
	39	void cpu_lock(void)
	40	{
	41	spin_lock(&global_cpu_lock);
	42	}
	43
	44	void cpu_unlock(void)
	45	{
	46	spin_unlock(&global_cpu_lock);
	47	}
	48
9d893301 FB	49	#if defined(CONFIG_USER_ONLY)
	50
	51	int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
	52	int is_user, int is_softmmu)
	53	{
878d3096 FB	54	if (rw & 2)
	55	env->exception_index = TT_TFAULT;
	56	else
	57	env->exception_index = TT_DFAULT;
9d893301 FB	58	return 1;
	59	}
	60
	61	#else
e8af50a3	62
3475187d	63	#ifndef TARGET_SPARC64
83469015 FB	64	/*
	65	* Sparc V8 Reference MMU (SRMMU)
	66	*/
e8af50a3 FB	67	static const int access_table[8][8] = {
	68	{ 0, 0, 0, 0, 2, 0, 3, 3 },
	69	{ 0, 0, 0, 0, 2, 0, 0, 0 },
	70	{ 2, 2, 0, 0, 0, 2, 3, 3 },
	71	{ 2, 2, 0, 0, 0, 2, 0, 0 },
	72	{ 2, 0, 2, 0, 2, 2, 3, 3 },
	73	{ 2, 0, 2, 0, 2, 0, 2, 0 },
	74	{ 2, 2, 2, 0, 2, 2, 3, 3 },
	75	{ 2, 2, 2, 0, 2, 2, 2, 0 }
	76	};
	77
227671c9 FB	78	static const int perm_table[2][8] = {
	79	{
	80	PAGE_READ,
	81	PAGE_READ \| PAGE_WRITE,
	82	PAGE_READ \| PAGE_EXEC,
	83	PAGE_READ \| PAGE_WRITE \| PAGE_EXEC,
	84	PAGE_EXEC,
	85	PAGE_READ \| PAGE_WRITE,
	86	PAGE_READ \| PAGE_EXEC,
	87	PAGE_READ \| PAGE_WRITE \| PAGE_EXEC
	88	},
	89	{
	90	PAGE_READ,
	91	PAGE_READ \| PAGE_WRITE,
	92	PAGE_READ \| PAGE_EXEC,
	93	PAGE_READ \| PAGE_WRITE \| PAGE_EXEC,
	94	PAGE_EXEC,
	95	PAGE_READ,
	96	0,
	97	0,
	98	}
e8af50a3 FB	99	};
e8af50a3 FB	100
af7bf89b FB	101	int get_physical_address (CPUState env, target_phys_addr_t physical, int *prot,
af7bf89b FB	102	int *access_index, target_ulong address, int rw,
e80cfcfc	103	int is_user)
e8af50a3	104	{
e80cfcfc FB	105	int access_perms = 0;
e80cfcfc FB	106	target_phys_addr_t pde_ptr;
af7bf89b FB	107	uint32_t pde;
af7bf89b FB	108	target_ulong virt_addr;
e80cfcfc FB	109	int error_code = 0, is_dirty;
e80cfcfc FB	110	unsigned long page_offset;
e8af50a3 FB	111
	112	virt_addr = address & TARGET_PAGE_MASK;
	113	if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
e80cfcfc	114	*physical = address;
227671c9	115	*prot = PAGE_READ \| PAGE_WRITE \| PAGE_EXEC;
e80cfcfc	116	return 0;
e8af50a3 FB	117	}
e8af50a3 FB	118
7483750d	119	*access_index = ((rw & 1) << 2) \| (rw & 2) \| (is_user? 0 : 1);
6f7e9aec	120	*physical = 0xfffff000;
7483750d	121
e8af50a3 FB	122	/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
e8af50a3 FB	123	/* Context base + context number */
b3180cdc	124	pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
49be8030	125	pde = ldl_phys(pde_ptr);
e8af50a3 FB	126
	127	/* Ctx pde */
	128	switch (pde & PTE_ENTRYTYPE_MASK) {
e80cfcfc	129	default:
e8af50a3	130	case 0: /* Invalid */
7483750d	131	return 1 << 2;
e80cfcfc	132	case 2: /* L0 PTE, maybe should not happen? */
e8af50a3	133	case 3: /* Reserved */
7483750d	134	return 4 << 2;
e80cfcfc FB	135	case 1: /* L0 PDE */
e80cfcfc FB	136	pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
49be8030	137	pde = ldl_phys(pde_ptr);
e8af50a3 FB	138
e8af50a3 FB	139	switch (pde & PTE_ENTRYTYPE_MASK) {
e80cfcfc	140	default:
e8af50a3	141	case 0: /* Invalid */
7483750d	142	return (1 << 8) \| (1 << 2);
e8af50a3	143	case 3: /* Reserved */
7483750d	144	return (1 << 8) \| (4 << 2);
e80cfcfc FB	145	case 1: /* L1 PDE */
e80cfcfc FB	146	pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
49be8030	147	pde = ldl_phys(pde_ptr);
e8af50a3 FB	148
e8af50a3 FB	149	switch (pde & PTE_ENTRYTYPE_MASK) {
e80cfcfc	150	default:
e8af50a3	151	case 0: /* Invalid */
7483750d	152	return (2 << 8) \| (1 << 2);
e8af50a3	153	case 3: /* Reserved */
7483750d	154	return (2 << 8) \| (4 << 2);
e80cfcfc FB	155	case 1: /* L2 PDE */
e80cfcfc FB	156	pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
49be8030	157	pde = ldl_phys(pde_ptr);
e8af50a3 FB	158
e8af50a3 FB	159	switch (pde & PTE_ENTRYTYPE_MASK) {
e80cfcfc	160	default:
e8af50a3	161	case 0: /* Invalid */
7483750d	162	return (3 << 8) \| (1 << 2);
e8af50a3 FB	163	case 1: /* PDE, should not happen */
e8af50a3 FB	164	case 3: /* Reserved */
7483750d	165	return (3 << 8) \| (4 << 2);
e8af50a3 FB	166	case 2: /* L3 PTE */
	167	virt_addr = address & TARGET_PAGE_MASK;
	168	page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
	169	}
	170	break;
	171	case 2: /* L2 PTE */
	172	virt_addr = address & ~0x3ffff;
	173	page_offset = address & 0x3ffff;
	174	}
	175	break;
	176	case 2: /* L1 PTE */
	177	virt_addr = address & ~0xffffff;
	178	page_offset = address & 0xffffff;
	179	}
	180	}
	181
	182	/* update page modified and dirty bits */
b769d8fe	183	is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
e8af50a3 FB	184	if (!(pde & PG_ACCESSED_MASK) \|\| is_dirty) {
	185	pde \|= PG_ACCESSED_MASK;
	186	if (is_dirty)
	187	pde \|= PG_MODIFIED_MASK;
49be8030	188	stl_phys_notdirty(pde_ptr, pde);
e8af50a3	189	}
e8af50a3	190	/* check access */
e8af50a3	191	access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
e80cfcfc	192	error_code = access_table[*access_index][access_perms];
d8e3326c	193	if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
e80cfcfc	194	return error_code;
e8af50a3 FB	195
e8af50a3 FB	196	/* the page can be put in the TLB */
227671c9 FB	197	*prot = perm_table[is_user][access_perms];
227671c9 FB	198	if (!(pde & PG_MODIFIED_MASK)) {
e8af50a3 FB	199	/* only set write access if already dirty... otherwise wait
e8af50a3 FB	200	for dirty access */
227671c9	201	*prot &= ~PAGE_WRITE;
e8af50a3 FB	202	}
	203
	204	/* Even if large ptes, we map only one 4KB page in the cache to
	205	avoid filling it too fast */
e80cfcfc	206	*physical = ((pde & PTE_ADDR_MASK) << 4) + page_offset;
6f7e9aec	207	return error_code;
e80cfcfc FB	208	}
	209
	210	/* Perform address translation */
af7bf89b	211	int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
e80cfcfc FB	212	int is_user, int is_softmmu)
e80cfcfc FB	213	{
af7bf89b	214	target_phys_addr_t paddr;
e80cfcfc FB	215	unsigned long vaddr;
e80cfcfc FB	216	int error_code = 0, prot, ret = 0, access_index;
e8af50a3	217
e80cfcfc FB	218	error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
e80cfcfc FB	219	if (error_code == 0) {
9e61bde5 FB	220	vaddr = address & TARGET_PAGE_MASK;
	221	paddr &= TARGET_PAGE_MASK;
	222	#ifdef DEBUG_MMU
	223	printf("Translate at 0x%lx -> 0x%lx, vaddr 0x%lx\n", (long)address, (long)paddr, (long)vaddr);
	224	#endif
227671c9	225	ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
e80cfcfc FB	226	return ret;
e80cfcfc FB	227	}
e8af50a3	228
e8af50a3 FB	229	if (env->mmuregs[3]) /* Fault status register */
e8af50a3 FB	230	env->mmuregs[3] = 1; /* overflow (not read before another fault) */
7483750d	231	env->mmuregs[3] \|= (access_index << 5) \| error_code \| 2;
e8af50a3 FB	232	env->mmuregs[4] = address; /* Fault address register */
e8af50a3 FB	233
878d3096	234	if ((env->mmuregs[0] & MMU_NF) \|\| env->psret == 0) {
6f7e9aec FB	235	// No fault mode: if a mapping is available, just override
	236	// permissions. If no mapping is available, redirect accesses to
	237	// neverland. Fake/overridden mappings will be flushed when
	238	// switching to normal mode.
7483750d	239	vaddr = address & TARGET_PAGE_MASK;
227671c9 FB	240	prot = PAGE_READ \| PAGE_WRITE \| PAGE_EXEC;
227671c9 FB	241	ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
7483750d	242	return ret;
7483750d FB	243	} else {
	244	if (rw & 2)
	245	env->exception_index = TT_TFAULT;
	246	else
	247	env->exception_index = TT_DFAULT;
	248	return 1;
878d3096	249	}
e8af50a3	250	}
24741ef3 FB	251
	252	target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
	253	{
	254	target_phys_addr_t pde_ptr;
	255	uint32_t pde;
	256
	257	/* Context base + context number */
	258	pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
	259	pde = ldl_phys(pde_ptr);
	260
	261	switch (pde & PTE_ENTRYTYPE_MASK) {
	262	default:
	263	case 0: /* Invalid */
	264	case 2: /* PTE, maybe should not happen? */
	265	case 3: /* Reserved */
	266	return 0;
	267	case 1: /* L1 PDE */
	268	if (mmulev == 3)
	269	return pde;
	270	pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
	271	pde = ldl_phys(pde_ptr);
	272
	273	switch (pde & PTE_ENTRYTYPE_MASK) {
	274	default:
	275	case 0: /* Invalid */
	276	case 3: /* Reserved */
	277	return 0;
	278	case 2: /* L1 PTE */
	279	return pde;
	280	case 1: /* L2 PDE */
	281	if (mmulev == 2)
	282	return pde;
	283	pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
	284	pde = ldl_phys(pde_ptr);
	285
	286	switch (pde & PTE_ENTRYTYPE_MASK) {
	287	default:
	288	case 0: /* Invalid */
	289	case 3: /* Reserved */
	290	return 0;
	291	case 2: /* L2 PTE */
	292	return pde;
	293	case 1: /* L3 PDE */
	294	if (mmulev == 1)
	295	return pde;
	296	pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
	297	pde = ldl_phys(pde_ptr);
	298
	299	switch (pde & PTE_ENTRYTYPE_MASK) {
	300	default:
	301	case 0: /* Invalid */
	302	case 1: /* PDE, should not happen */
	303	case 3: /* Reserved */
	304	return 0;
	305	case 2: /* L3 PTE */
	306	return pde;
	307	}
	308	}
	309	}
	310	}
	311	return 0;
	312	}
	313
	314	#ifdef DEBUG_MMU
315	void dump_mmu(CPUState *env)
316	{
317	target_ulong va, va1, va2;
318	unsigned int n, m, o;
319	target_phys_addr_t pde_ptr, pa;
320	uint32_t pde;
321
322	printf("MMU dump:\n");
323	pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
324	pde = ldl_phys(pde_ptr);
325	printf("Root ptr: " TARGET_FMT_lx ", ctx: %d\n", env->mmuregs[1] << 4, env->mmuregs[2]);
326	for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
327	pde_ptr = mmu_probe(env, va, 2);
328	if (pde_ptr) {
329	pa = cpu_get_phys_page_debug(env, va);
330	printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va, pa, pde_ptr);
331	for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
332	pde_ptr = mmu_probe(env, va1, 1);
333	if (pde_ptr) {
334	pa = cpu_get_phys_page_debug(env, va1);
335	printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde_ptr);
336	for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
337	pde_ptr = mmu_probe(env, va2, 0);
338	if (pde_ptr) {
339	pa = cpu_get_phys_page_debug(env, va2);
340	printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PTE: " TARGET_FMT_lx "\n", va2, pa, pde_ptr);
341	}
342	}
343	}
344	}
345	}
346	}
347	printf("MMU dump ends\n");
348	}
349	#endif /* DEBUG_MMU */
350
351	#else /* !TARGET_SPARC64 */
83469015 FB	352	/*
	353	* UltraSparc IIi I/DMMUs
	354	*/
3475187d FB	355	static int get_physical_address_data(CPUState env, target_phys_addr_t physical, int *prot,
	356	int *access_index, target_ulong address, int rw,
	357	int is_user)
	358	{
	359	target_ulong mask;
	360	unsigned int i;
	361
	362	if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
83469015	363	*physical = address;
3475187d FB	364	*prot = PAGE_READ \| PAGE_WRITE;
	365	return 0;
	366	}
	367
	368	for (i = 0; i < 64; i++) {
83469015 FB	369	switch ((env->dtlb_tte[i] >> 61) & 3) {
	370	default:
	371	case 0x0: // 8k
	372	mask = 0xffffffffffffe000ULL;
	373	break;
	374	case 0x1: // 64k
	375	mask = 0xffffffffffff0000ULL;
	376	break;
	377	case 0x2: // 512k
	378	mask = 0xfffffffffff80000ULL;
	379	break;
	380	case 0x3: // 4M
	381	mask = 0xffffffffffc00000ULL;
	382	break;
	383	}
	384	// ctx match, vaddr match?
	385	if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
	386	(address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
	387	// valid, access ok?
	388	if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 \|\|
	389	((env->dtlb_tte[i] & 0x4) && is_user) \|\|
	390	(!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
	391	if (env->dmmuregs[3]) /* Fault status register */
	392	env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
	393	env->dmmuregs[3] \|= (is_user << 3) \| ((rw == 1) << 2) \| 1;
	394	env->dmmuregs[4] = address; /* Fault address register */
	395	env->exception_index = TT_DFAULT;
	396	#ifdef DEBUG_MMU
	397	printf("DFAULT at 0x%llx\n", address);
	398	#endif
	399	return 1;
3475187d	400	}
83469015 FB	401	*physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
	402	*prot = PAGE_READ;
	403	if (env->dtlb_tte[i] & 0x2)
	404	*prot \|= PAGE_WRITE;
	405	return 0;
3475187d FB	406	}
3475187d FB	407	}
83469015 FB	408	#ifdef DEBUG_MMU
	409	printf("DMISS at 0x%llx\n", address);
	410	#endif
	411	env->exception_index = TT_DMISS;
3475187d FB	412	return 1;
	413	}
	414
	415	static int get_physical_address_code(CPUState env, target_phys_addr_t physical, int *prot,
	416	int *access_index, target_ulong address, int rw,
	417	int is_user)
	418	{
	419	target_ulong mask;
	420	unsigned int i;
	421
	422	if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
83469015	423	*physical = address;
227671c9	424	*prot = PAGE_EXEC;
3475187d FB	425	return 0;
3475187d FB	426	}
83469015	427
3475187d	428	for (i = 0; i < 64; i++) {
83469015 FB	429	switch ((env->itlb_tte[i] >> 61) & 3) {
	430	default:
	431	case 0x0: // 8k
	432	mask = 0xffffffffffffe000ULL;
	433	break;
	434	case 0x1: // 64k
	435	mask = 0xffffffffffff0000ULL;
	436	break;
	437	case 0x2: // 512k
	438	mask = 0xfffffffffff80000ULL;
	439	break;
	440	case 0x3: // 4M
	441	mask = 0xffffffffffc00000ULL;
3475187d	442	break;
83469015 FB	443	}
	444	// ctx match, vaddr match?
	445	if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
	446	(address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
	447	// valid, access ok?
	448	if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 \|\|
	449	((env->itlb_tte[i] & 0x4) && is_user)) {
	450	if (env->immuregs[3]) /* Fault status register */
	451	env->immuregs[3] = 2; /* overflow (not read before another fault) */
	452	env->immuregs[3] \|= (is_user << 3) \| 1;
	453	env->exception_index = TT_TFAULT;
	454	#ifdef DEBUG_MMU
	455	printf("TFAULT at 0x%llx\n", address);
	456	#endif
	457	return 1;
3475187d	458	}
83469015	459	*physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
227671c9	460	*prot = PAGE_EXEC;
83469015	461	return 0;
3475187d FB	462	}
3475187d FB	463	}
83469015 FB	464	#ifdef DEBUG_MMU
	465	printf("TMISS at 0x%llx\n", address);
	466	#endif
	467	env->exception_index = TT_TMISS;
3475187d FB	468	return 1;
	469	}
	470
	471	int get_physical_address(CPUState env, target_phys_addr_t physical, int *prot,
	472	int *access_index, target_ulong address, int rw,
	473	int is_user)
	474	{
	475	if (rw == 2)
	476	return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
	477	else
	478	return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
	479	}
	480
	481	/* Perform address translation */
	482	int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
	483	int is_user, int is_softmmu)
	484	{
83469015	485	target_ulong virt_addr, vaddr;
3475187d	486	target_phys_addr_t paddr;
3475187d FB	487	int error_code = 0, prot, ret = 0, access_index;
	488
	489	error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
	490	if (error_code == 0) {
	491	virt_addr = address & TARGET_PAGE_MASK;
	492	vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
83469015 FB	493	#ifdef DEBUG_MMU
	494	printf("Translate at 0x%llx -> 0x%llx, vaddr 0x%llx\n", address, paddr, vaddr);
	495	#endif
227671c9	496	ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
3475187d FB	497	return ret;
	498	}
	499	// XXX
	500	return 1;
	501	}
	502
83469015 FB	503	#ifdef DEBUG_MMU
	504	void dump_mmu(CPUState *env)
	505	{
	506	unsigned int i;
	507	const char *mask;
	508
	509	printf("MMU contexts: Primary: %lld, Secondary: %lld\n", env->dmmuregs[1], env->dmmuregs[2]);
	510	if ((env->lsu & DMMU_E) == 0) {
	511	printf("DMMU disabled\n");
	512	} else {
	513	printf("DMMU dump:\n");
	514	for (i = 0; i < 64; i++) {
	515	switch ((env->dtlb_tte[i] >> 61) & 3) {
	516	default:
	517	case 0x0:
	518	mask = " 8k";
	519	break;
	520	case 0x1:
	521	mask = " 64k";
	522	break;
	523	case 0x2:
	524	mask = "512k";
	525	break;
	526	case 0x3:
	527	mask = " 4M";
	528	break;
	529	}
	530	if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
	531	printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %lld\n",
	532	env->dtlb_tag[i] & ~0x1fffULL,
	533	env->dtlb_tte[i] & 0x1ffffffe000ULL,
	534	mask,
	535	env->dtlb_tte[i] & 0x4? "priv": "user",
	536	env->dtlb_tte[i] & 0x2? "RW": "RO",
	537	env->dtlb_tte[i] & 0x40? "locked": "unlocked",
	538	env->dtlb_tag[i] & 0x1fffULL);
	539	}
	540	}
	541	}
	542	if ((env->lsu & IMMU_E) == 0) {
	543	printf("IMMU disabled\n");
	544	} else {
	545	printf("IMMU dump:\n");
	546	for (i = 0; i < 64; i++) {
	547	switch ((env->itlb_tte[i] >> 61) & 3) {
	548	default:
	549	case 0x0:
	550	mask = " 8k";
	551	break;
	552	case 0x1:
	553	mask = " 64k";
	554	break;
	555	case 0x2:
	556	mask = "512k";
	557	break;
	558	case 0x3:
	559	mask = " 4M";
	560	break;
	561	}
	562	if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
	563	printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %lld\n",
	564	env->itlb_tag[i] & ~0x1fffULL,
	565	env->itlb_tte[i] & 0x1ffffffe000ULL,
	566	mask,
567	env->itlb_tte[i] & 0x4? "priv": "user",
568	env->itlb_tte[i] & 0x40? "locked": "unlocked",
569	env->itlb_tag[i] & 0x1fffULL);
570	}
571	}
572	}
573	}
24741ef3 FB	574	#endif /* DEBUG_MMU */
	575
	576	#endif /* TARGET_SPARC64 */
	577	#endif /* !CONFIG_USER_ONLY */
	578
	579	void memcpy32(target_ulong dst, const target_ulong src)
	580	{
	581	dst[0] = src[0];
	582	dst[1] = src[1];
	583	dst[2] = src[2];
	584	dst[3] = src[3];
	585	dst[4] = src[4];
	586	dst[5] = src[5];
	587	dst[6] = src[6];
	588	dst[7] = src[7];
	589	}