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Commit | Line | Data |
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e8af50a3 FB |
1 | /* |
2 | * sparc helpers | |
5fafdf24 | 3 | * |
83469015 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
e8af50a3 FB |
5 | * |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
ee5bbe38 FB |
20 | #include <stdarg.h> |
21 | #include <stdlib.h> | |
22 | #include <stdio.h> | |
23 | #include <string.h> | |
24 | #include <inttypes.h> | |
25 | #include <signal.h> | |
26 | #include <assert.h> | |
27 | ||
28 | #include "cpu.h" | |
29 | #include "exec-all.h" | |
ca10f867 | 30 | #include "qemu-common.h" |
22548760 | 31 | #include "helper.h" |
e8af50a3 | 32 | |
e80cfcfc | 33 | //#define DEBUG_MMU |
64a88d5d | 34 | //#define DEBUG_FEATURES |
f2bc7e7f | 35 | //#define DEBUG_PCALL |
e8af50a3 | 36 | |
c48fcb47 BS |
37 | typedef struct sparc_def_t sparc_def_t; |
38 | ||
39 | struct sparc_def_t { | |
22548760 | 40 | const char *name; |
c48fcb47 BS |
41 | target_ulong iu_version; |
42 | uint32_t fpu_version; | |
43 | uint32_t mmu_version; | |
44 | uint32_t mmu_bm; | |
45 | uint32_t mmu_ctpr_mask; | |
46 | uint32_t mmu_cxr_mask; | |
47 | uint32_t mmu_sfsr_mask; | |
48 | uint32_t mmu_trcr_mask; | |
64a88d5d | 49 | uint32_t features; |
1a14026e | 50 | uint32_t nwindows; |
c48fcb47 BS |
51 | }; |
52 | ||
22548760 | 53 | static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model); |
c48fcb47 | 54 | |
e8af50a3 | 55 | /* Sparc MMU emulation */ |
e8af50a3 | 56 | |
e8af50a3 FB |
57 | /* thread support */ |
58 | ||
59 | spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED; | |
60 | ||
61 | void cpu_lock(void) | |
62 | { | |
63 | spin_lock(&global_cpu_lock); | |
64 | } | |
65 | ||
66 | void cpu_unlock(void) | |
67 | { | |
68 | spin_unlock(&global_cpu_lock); | |
69 | } | |
70 | ||
5fafdf24 | 71 | #if defined(CONFIG_USER_ONLY) |
9d893301 | 72 | |
22548760 | 73 | int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw, |
6ebbf390 | 74 | int mmu_idx, int is_softmmu) |
9d893301 | 75 | { |
878d3096 | 76 | if (rw & 2) |
22548760 | 77 | env1->exception_index = TT_TFAULT; |
878d3096 | 78 | else |
22548760 | 79 | env1->exception_index = TT_DFAULT; |
9d893301 FB |
80 | return 1; |
81 | } | |
82 | ||
83 | #else | |
e8af50a3 | 84 | |
3475187d | 85 | #ifndef TARGET_SPARC64 |
83469015 FB |
86 | /* |
87 | * Sparc V8 Reference MMU (SRMMU) | |
88 | */ | |
e8af50a3 | 89 | static const int access_table[8][8] = { |
a764a566 BS |
90 | { 0, 0, 0, 0, 8, 0, 12, 12 }, |
91 | { 0, 0, 0, 0, 8, 0, 0, 0 }, | |
92 | { 8, 8, 0, 0, 0, 8, 12, 12 }, | |
93 | { 8, 8, 0, 0, 0, 8, 0, 0 }, | |
94 | { 8, 0, 8, 0, 8, 8, 12, 12 }, | |
95 | { 8, 0, 8, 0, 8, 0, 8, 0 }, | |
96 | { 8, 8, 8, 0, 8, 8, 12, 12 }, | |
97 | { 8, 8, 8, 0, 8, 8, 8, 0 } | |
e8af50a3 FB |
98 | }; |
99 | ||
227671c9 FB |
100 | static const int perm_table[2][8] = { |
101 | { | |
102 | PAGE_READ, | |
103 | PAGE_READ | PAGE_WRITE, | |
104 | PAGE_READ | PAGE_EXEC, | |
105 | PAGE_READ | PAGE_WRITE | PAGE_EXEC, | |
106 | PAGE_EXEC, | |
107 | PAGE_READ | PAGE_WRITE, | |
108 | PAGE_READ | PAGE_EXEC, | |
109 | PAGE_READ | PAGE_WRITE | PAGE_EXEC | |
110 | }, | |
111 | { | |
112 | PAGE_READ, | |
113 | PAGE_READ | PAGE_WRITE, | |
114 | PAGE_READ | PAGE_EXEC, | |
115 | PAGE_READ | PAGE_WRITE | PAGE_EXEC, | |
116 | PAGE_EXEC, | |
117 | PAGE_READ, | |
118 | 0, | |
119 | 0, | |
120 | } | |
e8af50a3 FB |
121 | }; |
122 | ||
c48fcb47 BS |
123 | static int get_physical_address(CPUState *env, target_phys_addr_t *physical, |
124 | int *prot, int *access_index, | |
125 | target_ulong address, int rw, int mmu_idx) | |
e8af50a3 | 126 | { |
e80cfcfc FB |
127 | int access_perms = 0; |
128 | target_phys_addr_t pde_ptr; | |
af7bf89b FB |
129 | uint32_t pde; |
130 | target_ulong virt_addr; | |
6ebbf390 | 131 | int error_code = 0, is_dirty, is_user; |
e80cfcfc | 132 | unsigned long page_offset; |
e8af50a3 | 133 | |
6ebbf390 | 134 | is_user = mmu_idx == MMU_USER_IDX; |
e8af50a3 | 135 | virt_addr = address & TARGET_PAGE_MASK; |
40ce0a9a | 136 | |
e8af50a3 | 137 | if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ |
40ce0a9a | 138 | // Boot mode: instruction fetches are taken from PROM |
6d5f237a | 139 | if (rw == 2 && (env->mmuregs[0] & env->mmu_bm)) { |
58a770f3 | 140 | *physical = env->prom_addr | (address & 0x7ffffULL); |
40ce0a9a BS |
141 | *prot = PAGE_READ | PAGE_EXEC; |
142 | return 0; | |
143 | } | |
0f8a249a | 144 | *physical = address; |
227671c9 | 145 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
e80cfcfc | 146 | return 0; |
e8af50a3 FB |
147 | } |
148 | ||
7483750d | 149 | *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1); |
5dcb6b91 | 150 | *physical = 0xffffffffffff0000ULL; |
7483750d | 151 | |
e8af50a3 FB |
152 | /* SPARC reference MMU table walk: Context table->L1->L2->PTE */ |
153 | /* Context base + context number */ | |
3deaeab7 | 154 | pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
49be8030 | 155 | pde = ldl_phys(pde_ptr); |
e8af50a3 FB |
156 | |
157 | /* Ctx pde */ | |
158 | switch (pde & PTE_ENTRYTYPE_MASK) { | |
e80cfcfc | 159 | default: |
e8af50a3 | 160 | case 0: /* Invalid */ |
0f8a249a | 161 | return 1 << 2; |
e80cfcfc | 162 | case 2: /* L0 PTE, maybe should not happen? */ |
e8af50a3 | 163 | case 3: /* Reserved */ |
7483750d | 164 | return 4 << 2; |
e80cfcfc | 165 | case 1: /* L0 PDE */ |
0f8a249a | 166 | pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
49be8030 | 167 | pde = ldl_phys(pde_ptr); |
e8af50a3 | 168 | |
0f8a249a BS |
169 | switch (pde & PTE_ENTRYTYPE_MASK) { |
170 | default: | |
171 | case 0: /* Invalid */ | |
172 | return (1 << 8) | (1 << 2); | |
173 | case 3: /* Reserved */ | |
174 | return (1 << 8) | (4 << 2); | |
175 | case 1: /* L1 PDE */ | |
176 | pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); | |
49be8030 | 177 | pde = ldl_phys(pde_ptr); |
e8af50a3 | 178 | |
0f8a249a BS |
179 | switch (pde & PTE_ENTRYTYPE_MASK) { |
180 | default: | |
181 | case 0: /* Invalid */ | |
182 | return (2 << 8) | (1 << 2); | |
183 | case 3: /* Reserved */ | |
184 | return (2 << 8) | (4 << 2); | |
185 | case 1: /* L2 PDE */ | |
186 | pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); | |
49be8030 | 187 | pde = ldl_phys(pde_ptr); |
e8af50a3 | 188 | |
0f8a249a BS |
189 | switch (pde & PTE_ENTRYTYPE_MASK) { |
190 | default: | |
191 | case 0: /* Invalid */ | |
192 | return (3 << 8) | (1 << 2); | |
193 | case 1: /* PDE, should not happen */ | |
194 | case 3: /* Reserved */ | |
195 | return (3 << 8) | (4 << 2); | |
196 | case 2: /* L3 PTE */ | |
197 | virt_addr = address & TARGET_PAGE_MASK; | |
77f193da BS |
198 | page_offset = (address & TARGET_PAGE_MASK) & |
199 | (TARGET_PAGE_SIZE - 1); | |
0f8a249a BS |
200 | } |
201 | break; | |
202 | case 2: /* L2 PTE */ | |
203 | virt_addr = address & ~0x3ffff; | |
204 | page_offset = address & 0x3ffff; | |
205 | } | |
206 | break; | |
207 | case 2: /* L1 PTE */ | |
208 | virt_addr = address & ~0xffffff; | |
209 | page_offset = address & 0xffffff; | |
210 | } | |
e8af50a3 FB |
211 | } |
212 | ||
213 | /* update page modified and dirty bits */ | |
b769d8fe | 214 | is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK); |
e8af50a3 | 215 | if (!(pde & PG_ACCESSED_MASK) || is_dirty) { |
0f8a249a BS |
216 | pde |= PG_ACCESSED_MASK; |
217 | if (is_dirty) | |
218 | pde |= PG_MODIFIED_MASK; | |
49be8030 | 219 | stl_phys_notdirty(pde_ptr, pde); |
e8af50a3 | 220 | } |
e8af50a3 | 221 | /* check access */ |
e8af50a3 | 222 | access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT; |
e80cfcfc | 223 | error_code = access_table[*access_index][access_perms]; |
d8e3326c | 224 | if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user)) |
0f8a249a | 225 | return error_code; |
e8af50a3 FB |
226 | |
227 | /* the page can be put in the TLB */ | |
227671c9 FB |
228 | *prot = perm_table[is_user][access_perms]; |
229 | if (!(pde & PG_MODIFIED_MASK)) { | |
e8af50a3 FB |
230 | /* only set write access if already dirty... otherwise wait |
231 | for dirty access */ | |
227671c9 | 232 | *prot &= ~PAGE_WRITE; |
e8af50a3 FB |
233 | } |
234 | ||
235 | /* Even if large ptes, we map only one 4KB page in the cache to | |
236 | avoid filling it too fast */ | |
5dcb6b91 | 237 | *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset; |
6f7e9aec | 238 | return error_code; |
e80cfcfc FB |
239 | } |
240 | ||
241 | /* Perform address translation */ | |
af7bf89b | 242 | int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
6ebbf390 | 243 | int mmu_idx, int is_softmmu) |
e80cfcfc | 244 | { |
af7bf89b | 245 | target_phys_addr_t paddr; |
5dcb6b91 | 246 | target_ulong vaddr; |
e80cfcfc | 247 | int error_code = 0, prot, ret = 0, access_index; |
e8af50a3 | 248 | |
77f193da BS |
249 | error_code = get_physical_address(env, &paddr, &prot, &access_index, |
250 | address, rw, mmu_idx); | |
e80cfcfc | 251 | if (error_code == 0) { |
0f8a249a BS |
252 | vaddr = address & TARGET_PAGE_MASK; |
253 | paddr &= TARGET_PAGE_MASK; | |
9e61bde5 | 254 | #ifdef DEBUG_MMU |
0f8a249a | 255 | printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr " |
5dcb6b91 | 256 | TARGET_FMT_lx "\n", address, paddr, vaddr); |
9e61bde5 | 257 | #endif |
6ebbf390 | 258 | ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
0f8a249a | 259 | return ret; |
e80cfcfc | 260 | } |
e8af50a3 | 261 | |
e8af50a3 | 262 | if (env->mmuregs[3]) /* Fault status register */ |
0f8a249a | 263 | env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
7483750d | 264 | env->mmuregs[3] |= (access_index << 5) | error_code | 2; |
e8af50a3 FB |
265 | env->mmuregs[4] = address; /* Fault address register */ |
266 | ||
878d3096 | 267 | if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { |
6f7e9aec FB |
268 | // No fault mode: if a mapping is available, just override |
269 | // permissions. If no mapping is available, redirect accesses to | |
270 | // neverland. Fake/overridden mappings will be flushed when | |
271 | // switching to normal mode. | |
0f8a249a | 272 | vaddr = address & TARGET_PAGE_MASK; |
227671c9 | 273 | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
6ebbf390 | 274 | ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
0f8a249a | 275 | return ret; |
7483750d FB |
276 | } else { |
277 | if (rw & 2) | |
278 | env->exception_index = TT_TFAULT; | |
279 | else | |
280 | env->exception_index = TT_DFAULT; | |
281 | return 1; | |
878d3096 | 282 | } |
e8af50a3 | 283 | } |
24741ef3 FB |
284 | |
285 | target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev) | |
286 | { | |
287 | target_phys_addr_t pde_ptr; | |
288 | uint32_t pde; | |
289 | ||
290 | /* Context base + context number */ | |
5dcb6b91 BS |
291 | pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) + |
292 | (env->mmuregs[2] << 2); | |
24741ef3 FB |
293 | pde = ldl_phys(pde_ptr); |
294 | ||
295 | switch (pde & PTE_ENTRYTYPE_MASK) { | |
296 | default: | |
297 | case 0: /* Invalid */ | |
298 | case 2: /* PTE, maybe should not happen? */ | |
299 | case 3: /* Reserved */ | |
0f8a249a | 300 | return 0; |
24741ef3 | 301 | case 1: /* L1 PDE */ |
0f8a249a BS |
302 | if (mmulev == 3) |
303 | return pde; | |
304 | pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); | |
24741ef3 FB |
305 | pde = ldl_phys(pde_ptr); |
306 | ||
0f8a249a BS |
307 | switch (pde & PTE_ENTRYTYPE_MASK) { |
308 | default: | |
309 | case 0: /* Invalid */ | |
310 | case 3: /* Reserved */ | |
311 | return 0; | |
312 | case 2: /* L1 PTE */ | |
313 | return pde; | |
314 | case 1: /* L2 PDE */ | |
315 | if (mmulev == 2) | |
316 | return pde; | |
317 | pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); | |
24741ef3 FB |
318 | pde = ldl_phys(pde_ptr); |
319 | ||
0f8a249a BS |
320 | switch (pde & PTE_ENTRYTYPE_MASK) { |
321 | default: | |
322 | case 0: /* Invalid */ | |
323 | case 3: /* Reserved */ | |
324 | return 0; | |
325 | case 2: /* L2 PTE */ | |
326 | return pde; | |
327 | case 1: /* L3 PDE */ | |
328 | if (mmulev == 1) | |
329 | return pde; | |
330 | pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); | |
24741ef3 FB |
331 | pde = ldl_phys(pde_ptr); |
332 | ||
0f8a249a BS |
333 | switch (pde & PTE_ENTRYTYPE_MASK) { |
334 | default: | |
335 | case 0: /* Invalid */ | |
336 | case 1: /* PDE, should not happen */ | |
337 | case 3: /* Reserved */ | |
338 | return 0; | |
339 | case 2: /* L3 PTE */ | |
340 | return pde; | |
341 | } | |
342 | } | |
343 | } | |
24741ef3 FB |
344 | } |
345 | return 0; | |
346 | } | |
347 | ||
348 | #ifdef DEBUG_MMU | |
349 | void dump_mmu(CPUState *env) | |
350 | { | |
5dcb6b91 BS |
351 | target_ulong va, va1, va2; |
352 | unsigned int n, m, o; | |
353 | target_phys_addr_t pde_ptr, pa; | |
24741ef3 FB |
354 | uint32_t pde; |
355 | ||
356 | printf("MMU dump:\n"); | |
357 | pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); | |
358 | pde = ldl_phys(pde_ptr); | |
5dcb6b91 BS |
359 | printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n", |
360 | (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]); | |
24741ef3 | 361 | for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { |
0f8a249a BS |
362 | pde = mmu_probe(env, va, 2); |
363 | if (pde) { | |
364 | pa = cpu_get_phys_page_debug(env, va); | |
365 | printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx | |
5dcb6b91 | 366 | " PDE: " TARGET_FMT_lx "\n", va, pa, pde); |
0f8a249a BS |
367 | for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) { |
368 | pde = mmu_probe(env, va1, 1); | |
369 | if (pde) { | |
370 | pa = cpu_get_phys_page_debug(env, va1); | |
371 | printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx | |
5dcb6b91 | 372 | " PDE: " TARGET_FMT_lx "\n", va1, pa, pde); |
0f8a249a BS |
373 | for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { |
374 | pde = mmu_probe(env, va2, 0); | |
375 | if (pde) { | |
376 | pa = cpu_get_phys_page_debug(env, va2); | |
377 | printf(" VA: " TARGET_FMT_lx ", PA: " | |
5dcb6b91 BS |
378 | TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n", |
379 | va2, pa, pde); | |
0f8a249a BS |
380 | } |
381 | } | |
382 | } | |
383 | } | |
384 | } | |
24741ef3 FB |
385 | } |
386 | printf("MMU dump ends\n"); | |
387 | } | |
388 | #endif /* DEBUG_MMU */ | |
389 | ||
390 | #else /* !TARGET_SPARC64 */ | |
83469015 FB |
391 | /* |
392 | * UltraSparc IIi I/DMMUs | |
393 | */ | |
77f193da BS |
394 | static int get_physical_address_data(CPUState *env, |
395 | target_phys_addr_t *physical, int *prot, | |
22548760 | 396 | target_ulong address, int rw, int is_user) |
3475187d FB |
397 | { |
398 | target_ulong mask; | |
399 | unsigned int i; | |
400 | ||
401 | if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */ | |
0f8a249a BS |
402 | *physical = address; |
403 | *prot = PAGE_READ | PAGE_WRITE; | |
3475187d FB |
404 | return 0; |
405 | } | |
406 | ||
407 | for (i = 0; i < 64; i++) { | |
0f8a249a BS |
408 | switch ((env->dtlb_tte[i] >> 61) & 3) { |
409 | default: | |
410 | case 0x0: // 8k | |
411 | mask = 0xffffffffffffe000ULL; | |
412 | break; | |
413 | case 0x1: // 64k | |
414 | mask = 0xffffffffffff0000ULL; | |
415 | break; | |
416 | case 0x2: // 512k | |
417 | mask = 0xfffffffffff80000ULL; | |
418 | break; | |
419 | case 0x3: // 4M | |
420 | mask = 0xffffffffffc00000ULL; | |
421 | break; | |
422 | } | |
423 | // ctx match, vaddr match? | |
424 | if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) && | |
425 | (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) { | |
426 | // valid, access ok? | |
427 | if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 || | |
428 | ((env->dtlb_tte[i] & 0x4) && is_user) || | |
429 | (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) { | |
430 | if (env->dmmuregs[3]) /* Fault status register */ | |
77f193da BS |
431 | env->dmmuregs[3] = 2; /* overflow (not read before |
432 | another fault) */ | |
0f8a249a BS |
433 | env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1; |
434 | env->dmmuregs[4] = address; /* Fault address register */ | |
435 | env->exception_index = TT_DFAULT; | |
83469015 | 436 | #ifdef DEBUG_MMU |
0f8a249a | 437 | printf("DFAULT at 0x%" PRIx64 "\n", address); |
83469015 | 438 | #endif |
0f8a249a BS |
439 | return 1; |
440 | } | |
77f193da BS |
441 | *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + |
442 | (address & ~mask & 0x1fffffff000ULL); | |
0f8a249a BS |
443 | *prot = PAGE_READ; |
444 | if (env->dtlb_tte[i] & 0x2) | |
445 | *prot |= PAGE_WRITE; | |
446 | return 0; | |
447 | } | |
3475187d | 448 | } |
83469015 | 449 | #ifdef DEBUG_MMU |
26a76461 | 450 | printf("DMISS at 0x%" PRIx64 "\n", address); |
83469015 | 451 | #endif |
f617a9a6 | 452 | env->dmmuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff); |
83469015 | 453 | env->exception_index = TT_DMISS; |
3475187d FB |
454 | return 1; |
455 | } | |
456 | ||
77f193da BS |
457 | static int get_physical_address_code(CPUState *env, |
458 | target_phys_addr_t *physical, int *prot, | |
22548760 | 459 | target_ulong address, int is_user) |
3475187d FB |
460 | { |
461 | target_ulong mask; | |
462 | unsigned int i; | |
463 | ||
464 | if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */ | |
0f8a249a BS |
465 | *physical = address; |
466 | *prot = PAGE_EXEC; | |
3475187d FB |
467 | return 0; |
468 | } | |
83469015 | 469 | |
3475187d | 470 | for (i = 0; i < 64; i++) { |
0f8a249a BS |
471 | switch ((env->itlb_tte[i] >> 61) & 3) { |
472 | default: | |
473 | case 0x0: // 8k | |
474 | mask = 0xffffffffffffe000ULL; | |
475 | break; | |
476 | case 0x1: // 64k | |
477 | mask = 0xffffffffffff0000ULL; | |
478 | break; | |
479 | case 0x2: // 512k | |
480 | mask = 0xfffffffffff80000ULL; | |
481 | break; | |
482 | case 0x3: // 4M | |
483 | mask = 0xffffffffffc00000ULL; | |
484 | break; | |
485 | } | |
486 | // ctx match, vaddr match? | |
487 | if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) && | |
488 | (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) { | |
489 | // valid, access ok? | |
490 | if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 || | |
491 | ((env->itlb_tte[i] & 0x4) && is_user)) { | |
492 | if (env->immuregs[3]) /* Fault status register */ | |
77f193da BS |
493 | env->immuregs[3] = 2; /* overflow (not read before |
494 | another fault) */ | |
0f8a249a BS |
495 | env->immuregs[3] |= (is_user << 3) | 1; |
496 | env->exception_index = TT_TFAULT; | |
83469015 | 497 | #ifdef DEBUG_MMU |
0f8a249a | 498 | printf("TFAULT at 0x%" PRIx64 "\n", address); |
83469015 | 499 | #endif |
0f8a249a BS |
500 | return 1; |
501 | } | |
77f193da BS |
502 | *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + |
503 | (address & ~mask & 0x1fffffff000ULL); | |
0f8a249a BS |
504 | *prot = PAGE_EXEC; |
505 | return 0; | |
506 | } | |
3475187d | 507 | } |
83469015 | 508 | #ifdef DEBUG_MMU |
26a76461 | 509 | printf("TMISS at 0x%" PRIx64 "\n", address); |
83469015 | 510 | #endif |
f617a9a6 | 511 | env->immuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff); |
83469015 | 512 | env->exception_index = TT_TMISS; |
3475187d FB |
513 | return 1; |
514 | } | |
515 | ||
c48fcb47 BS |
516 | static int get_physical_address(CPUState *env, target_phys_addr_t *physical, |
517 | int *prot, int *access_index, | |
518 | target_ulong address, int rw, int mmu_idx) | |
3475187d | 519 | { |
6ebbf390 JM |
520 | int is_user = mmu_idx == MMU_USER_IDX; |
521 | ||
3475187d | 522 | if (rw == 2) |
22548760 BS |
523 | return get_physical_address_code(env, physical, prot, address, |
524 | is_user); | |
3475187d | 525 | else |
22548760 BS |
526 | return get_physical_address_data(env, physical, prot, address, rw, |
527 | is_user); | |
3475187d FB |
528 | } |
529 | ||
530 | /* Perform address translation */ | |
531 | int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, | |
6ebbf390 | 532 | int mmu_idx, int is_softmmu) |
3475187d | 533 | { |
83469015 | 534 | target_ulong virt_addr, vaddr; |
3475187d | 535 | target_phys_addr_t paddr; |
3475187d FB |
536 | int error_code = 0, prot, ret = 0, access_index; |
537 | ||
77f193da BS |
538 | error_code = get_physical_address(env, &paddr, &prot, &access_index, |
539 | address, rw, mmu_idx); | |
3475187d | 540 | if (error_code == 0) { |
0f8a249a | 541 | virt_addr = address & TARGET_PAGE_MASK; |
77f193da BS |
542 | vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & |
543 | (TARGET_PAGE_SIZE - 1)); | |
83469015 | 544 | #ifdef DEBUG_MMU |
77f193da BS |
545 | printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 |
546 | "\n", address, paddr, vaddr); | |
83469015 | 547 | #endif |
6ebbf390 | 548 | ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
0f8a249a | 549 | return ret; |
3475187d FB |
550 | } |
551 | // XXX | |
552 | return 1; | |
553 | } | |
554 | ||
83469015 FB |
555 | #ifdef DEBUG_MMU |
556 | void dump_mmu(CPUState *env) | |
557 | { | |
558 | unsigned int i; | |
559 | const char *mask; | |
560 | ||
77f193da BS |
561 | printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", |
562 | env->dmmuregs[1], env->dmmuregs[2]); | |
83469015 | 563 | if ((env->lsu & DMMU_E) == 0) { |
0f8a249a | 564 | printf("DMMU disabled\n"); |
83469015 | 565 | } else { |
0f8a249a BS |
566 | printf("DMMU dump:\n"); |
567 | for (i = 0; i < 64; i++) { | |
568 | switch ((env->dtlb_tte[i] >> 61) & 3) { | |
569 | default: | |
570 | case 0x0: | |
571 | mask = " 8k"; | |
572 | break; | |
573 | case 0x1: | |
574 | mask = " 64k"; | |
575 | break; | |
576 | case 0x2: | |
577 | mask = "512k"; | |
578 | break; | |
579 | case 0x3: | |
580 | mask = " 4M"; | |
581 | break; | |
582 | } | |
583 | if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) { | |
77f193da BS |
584 | printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx |
585 | ", %s, %s, %s, %s, ctx %" PRId64 "\n", | |
0f8a249a BS |
586 | env->dtlb_tag[i] & ~0x1fffULL, |
587 | env->dtlb_tte[i] & 0x1ffffffe000ULL, | |
588 | mask, | |
589 | env->dtlb_tte[i] & 0x4? "priv": "user", | |
590 | env->dtlb_tte[i] & 0x2? "RW": "RO", | |
591 | env->dtlb_tte[i] & 0x40? "locked": "unlocked", | |
592 | env->dtlb_tag[i] & 0x1fffULL); | |
593 | } | |
594 | } | |
83469015 FB |
595 | } |
596 | if ((env->lsu & IMMU_E) == 0) { | |
0f8a249a | 597 | printf("IMMU disabled\n"); |
83469015 | 598 | } else { |
0f8a249a BS |
599 | printf("IMMU dump:\n"); |
600 | for (i = 0; i < 64; i++) { | |
601 | switch ((env->itlb_tte[i] >> 61) & 3) { | |
602 | default: | |
603 | case 0x0: | |
604 | mask = " 8k"; | |
605 | break; | |
606 | case 0x1: | |
607 | mask = " 64k"; | |
608 | break; | |
609 | case 0x2: | |
610 | mask = "512k"; | |
611 | break; | |
612 | case 0x3: | |
613 | mask = " 4M"; | |
614 | break; | |
615 | } | |
616 | if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) { | |
77f193da BS |
617 | printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx |
618 | ", %s, %s, %s, ctx %" PRId64 "\n", | |
0f8a249a BS |
619 | env->itlb_tag[i] & ~0x1fffULL, |
620 | env->itlb_tte[i] & 0x1ffffffe000ULL, | |
621 | mask, | |
622 | env->itlb_tte[i] & 0x4? "priv": "user", | |
623 | env->itlb_tte[i] & 0x40? "locked": "unlocked", | |
624 | env->itlb_tag[i] & 0x1fffULL); | |
625 | } | |
626 | } | |
83469015 FB |
627 | } |
628 | } | |
24741ef3 FB |
629 | #endif /* DEBUG_MMU */ |
630 | ||
631 | #endif /* TARGET_SPARC64 */ | |
632 | #endif /* !CONFIG_USER_ONLY */ | |
633 | ||
c48fcb47 BS |
634 | |
635 | #if defined(CONFIG_USER_ONLY) | |
636 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) | |
637 | { | |
638 | return addr; | |
639 | } | |
640 | ||
641 | #else | |
642 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) | |
643 | { | |
644 | target_phys_addr_t phys_addr; | |
645 | int prot, access_index; | |
646 | ||
647 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, | |
648 | MMU_KERNEL_IDX) != 0) | |
649 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, | |
650 | 0, MMU_KERNEL_IDX) != 0) | |
651 | return -1; | |
652 | if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED) | |
653 | return -1; | |
654 | return phys_addr; | |
655 | } | |
656 | #endif | |
657 | ||
f2bc7e7f BS |
658 | #ifdef TARGET_SPARC64 |
659 | #ifdef DEBUG_PCALL | |
e19e4efe | 660 | static const char * const excp_names[0x80] = { |
f2bc7e7f BS |
661 | [TT_TFAULT] = "Instruction Access Fault", |
662 | [TT_TMISS] = "Instruction Access MMU Miss", | |
663 | [TT_CODE_ACCESS] = "Instruction Access Error", | |
664 | [TT_ILL_INSN] = "Illegal Instruction", | |
665 | [TT_PRIV_INSN] = "Privileged Instruction", | |
666 | [TT_NFPU_INSN] = "FPU Disabled", | |
667 | [TT_FP_EXCP] = "FPU Exception", | |
668 | [TT_TOVF] = "Tag Overflow", | |
669 | [TT_CLRWIN] = "Clean Windows", | |
670 | [TT_DIV_ZERO] = "Division By Zero", | |
671 | [TT_DFAULT] = "Data Access Fault", | |
672 | [TT_DMISS] = "Data Access MMU Miss", | |
673 | [TT_DATA_ACCESS] = "Data Access Error", | |
674 | [TT_DPROT] = "Data Protection Error", | |
675 | [TT_UNALIGNED] = "Unaligned Memory Access", | |
676 | [TT_PRIV_ACT] = "Privileged Action", | |
677 | [TT_EXTINT | 0x1] = "External Interrupt 1", | |
678 | [TT_EXTINT | 0x2] = "External Interrupt 2", | |
679 | [TT_EXTINT | 0x3] = "External Interrupt 3", | |
680 | [TT_EXTINT | 0x4] = "External Interrupt 4", | |
681 | [TT_EXTINT | 0x5] = "External Interrupt 5", | |
682 | [TT_EXTINT | 0x6] = "External Interrupt 6", | |
683 | [TT_EXTINT | 0x7] = "External Interrupt 7", | |
684 | [TT_EXTINT | 0x8] = "External Interrupt 8", | |
685 | [TT_EXTINT | 0x9] = "External Interrupt 9", | |
686 | [TT_EXTINT | 0xa] = "External Interrupt 10", | |
687 | [TT_EXTINT | 0xb] = "External Interrupt 11", | |
688 | [TT_EXTINT | 0xc] = "External Interrupt 12", | |
689 | [TT_EXTINT | 0xd] = "External Interrupt 13", | |
690 | [TT_EXTINT | 0xe] = "External Interrupt 14", | |
691 | [TT_EXTINT | 0xf] = "External Interrupt 15", | |
692 | }; | |
693 | #endif | |
694 | ||
695 | void do_interrupt(CPUState *env) | |
696 | { | |
697 | int intno = env->exception_index; | |
698 | ||
699 | #ifdef DEBUG_PCALL | |
700 | if (loglevel & CPU_LOG_INT) { | |
701 | static int count; | |
702 | const char *name; | |
703 | ||
e19e4efe | 704 | if (intno < 0 || intno >= 0x180) |
f2bc7e7f BS |
705 | name = "Unknown"; |
706 | else if (intno >= 0x100) | |
707 | name = "Trap Instruction"; | |
708 | else if (intno >= 0xc0) | |
709 | name = "Window Fill"; | |
710 | else if (intno >= 0x80) | |
711 | name = "Window Spill"; | |
712 | else { | |
713 | name = excp_names[intno]; | |
714 | if (!name) | |
715 | name = "Unknown"; | |
716 | } | |
717 | ||
718 | fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64 | |
719 | " SP=%016" PRIx64 "\n", | |
720 | count, name, intno, | |
721 | env->pc, | |
722 | env->npc, env->regwptr[6]); | |
723 | cpu_dump_state(env, logfile, fprintf, 0); | |
724 | #if 0 | |
725 | { | |
726 | int i; | |
727 | uint8_t *ptr; | |
728 | ||
729 | fprintf(logfile, " code="); | |
730 | ptr = (uint8_t *)env->pc; | |
731 | for(i = 0; i < 16; i++) { | |
732 | fprintf(logfile, " %02x", ldub(ptr + i)); | |
733 | } | |
734 | fprintf(logfile, "\n"); | |
735 | } | |
736 | #endif | |
737 | count++; | |
738 | } | |
739 | #endif | |
740 | #if !defined(CONFIG_USER_ONLY) | |
741 | if (env->tl == MAXTL) { | |
742 | cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", | |
743 | env->exception_index); | |
744 | return; | |
745 | } | |
746 | #endif | |
e6bf7d70 BS |
747 | if (env->tl < MAXTL - 1) { |
748 | env->tl++; | |
749 | } else { | |
750 | env->pstate |= PS_RED; | |
751 | if (env->tl != MAXTL) | |
752 | env->tl++; | |
753 | } | |
754 | env->tsptr = &env->ts[env->tl]; | |
f2bc7e7f BS |
755 | env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) | |
756 | ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | | |
757 | GET_CWP64(env); | |
758 | env->tsptr->tpc = env->pc; | |
759 | env->tsptr->tnpc = env->npc; | |
760 | env->tsptr->tt = intno; | |
761 | change_pstate(PS_PEF | PS_PRIV | PS_AG); | |
762 | ||
763 | if (intno == TT_CLRWIN) | |
1a14026e | 764 | cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1)); |
f2bc7e7f | 765 | else if ((intno & 0x1c0) == TT_SPILL) |
1a14026e | 766 | cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2)); |
f2bc7e7f | 767 | else if ((intno & 0x1c0) == TT_FILL) |
1a14026e | 768 | cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1)); |
f2bc7e7f BS |
769 | env->tbr &= ~0x7fffULL; |
770 | env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); | |
f2bc7e7f BS |
771 | env->pc = env->tbr; |
772 | env->npc = env->pc + 4; | |
773 | env->exception_index = 0; | |
774 | } | |
775 | #else | |
776 | #ifdef DEBUG_PCALL | |
777 | static const char * const excp_names[0x80] = { | |
778 | [TT_TFAULT] = "Instruction Access Fault", | |
779 | [TT_ILL_INSN] = "Illegal Instruction", | |
780 | [TT_PRIV_INSN] = "Privileged Instruction", | |
781 | [TT_NFPU_INSN] = "FPU Disabled", | |
782 | [TT_WIN_OVF] = "Window Overflow", | |
783 | [TT_WIN_UNF] = "Window Underflow", | |
784 | [TT_UNALIGNED] = "Unaligned Memory Access", | |
785 | [TT_FP_EXCP] = "FPU Exception", | |
786 | [TT_DFAULT] = "Data Access Fault", | |
787 | [TT_TOVF] = "Tag Overflow", | |
788 | [TT_EXTINT | 0x1] = "External Interrupt 1", | |
789 | [TT_EXTINT | 0x2] = "External Interrupt 2", | |
790 | [TT_EXTINT | 0x3] = "External Interrupt 3", | |
791 | [TT_EXTINT | 0x4] = "External Interrupt 4", | |
792 | [TT_EXTINT | 0x5] = "External Interrupt 5", | |
793 | [TT_EXTINT | 0x6] = "External Interrupt 6", | |
794 | [TT_EXTINT | 0x7] = "External Interrupt 7", | |
795 | [TT_EXTINT | 0x8] = "External Interrupt 8", | |
796 | [TT_EXTINT | 0x9] = "External Interrupt 9", | |
797 | [TT_EXTINT | 0xa] = "External Interrupt 10", | |
798 | [TT_EXTINT | 0xb] = "External Interrupt 11", | |
799 | [TT_EXTINT | 0xc] = "External Interrupt 12", | |
800 | [TT_EXTINT | 0xd] = "External Interrupt 13", | |
801 | [TT_EXTINT | 0xe] = "External Interrupt 14", | |
802 | [TT_EXTINT | 0xf] = "External Interrupt 15", | |
803 | [TT_TOVF] = "Tag Overflow", | |
804 | [TT_CODE_ACCESS] = "Instruction Access Error", | |
805 | [TT_DATA_ACCESS] = "Data Access Error", | |
806 | [TT_DIV_ZERO] = "Division By Zero", | |
807 | [TT_NCP_INSN] = "Coprocessor Disabled", | |
808 | }; | |
809 | #endif | |
810 | ||
811 | void do_interrupt(CPUState *env) | |
812 | { | |
813 | int cwp, intno = env->exception_index; | |
814 | ||
815 | #ifdef DEBUG_PCALL | |
816 | if (loglevel & CPU_LOG_INT) { | |
817 | static int count; | |
818 | const char *name; | |
819 | ||
820 | if (intno < 0 || intno >= 0x100) | |
821 | name = "Unknown"; | |
822 | else if (intno >= 0x80) | |
823 | name = "Trap Instruction"; | |
824 | else { | |
825 | name = excp_names[intno]; | |
826 | if (!name) | |
827 | name = "Unknown"; | |
828 | } | |
829 | ||
830 | fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n", | |
831 | count, name, intno, | |
832 | env->pc, | |
833 | env->npc, env->regwptr[6]); | |
834 | cpu_dump_state(env, logfile, fprintf, 0); | |
835 | #if 0 | |
836 | { | |
837 | int i; | |
838 | uint8_t *ptr; | |
839 | ||
840 | fprintf(logfile, " code="); | |
841 | ptr = (uint8_t *)env->pc; | |
842 | for(i = 0; i < 16; i++) { | |
843 | fprintf(logfile, " %02x", ldub(ptr + i)); | |
844 | } | |
845 | fprintf(logfile, "\n"); | |
846 | } | |
847 | #endif | |
848 | count++; | |
849 | } | |
850 | #endif | |
851 | #if !defined(CONFIG_USER_ONLY) | |
852 | if (env->psret == 0) { | |
853 | cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", | |
854 | env->exception_index); | |
855 | return; | |
856 | } | |
857 | #endif | |
858 | env->psret = 0; | |
1a14026e | 859 | cwp = cpu_cwp_dec(env, env->cwp - 1); |
f2bc7e7f BS |
860 | cpu_set_cwp(env, cwp); |
861 | env->regwptr[9] = env->pc; | |
862 | env->regwptr[10] = env->npc; | |
863 | env->psrps = env->psrs; | |
864 | env->psrs = 1; | |
865 | env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4); | |
866 | env->pc = env->tbr; | |
867 | env->npc = env->pc + 4; | |
868 | env->exception_index = 0; | |
869 | } | |
870 | #endif | |
871 | ||
24741ef3 FB |
872 | void memcpy32(target_ulong *dst, const target_ulong *src) |
873 | { | |
874 | dst[0] = src[0]; | |
875 | dst[1] = src[1]; | |
876 | dst[2] = src[2]; | |
877 | dst[3] = src[3]; | |
878 | dst[4] = src[4]; | |
879 | dst[5] = src[5]; | |
880 | dst[6] = src[6]; | |
881 | dst[7] = src[7]; | |
882 | } | |
87ecb68b | 883 | |
c48fcb47 BS |
884 | void cpu_reset(CPUSPARCState *env) |
885 | { | |
886 | tlb_flush(env, 1); | |
887 | env->cwp = 0; | |
888 | env->wim = 1; | |
889 | env->regwptr = env->regbase + (env->cwp * 16); | |
890 | #if defined(CONFIG_USER_ONLY) | |
891 | env->user_mode_only = 1; | |
892 | #ifdef TARGET_SPARC64 | |
1a14026e BS |
893 | env->cleanwin = env->nwindows - 2; |
894 | env->cansave = env->nwindows - 2; | |
c48fcb47 BS |
895 | env->pstate = PS_RMO | PS_PEF | PS_IE; |
896 | env->asi = 0x82; // Primary no-fault | |
897 | #endif | |
898 | #else | |
899 | env->psret = 0; | |
900 | env->psrs = 1; | |
901 | env->psrps = 1; | |
902 | #ifdef TARGET_SPARC64 | |
903 | env->pstate = PS_PRIV; | |
904 | env->hpstate = HS_PRIV; | |
905 | env->pc = 0x1fff0000000ULL; | |
906 | env->tsptr = &env->ts[env->tl]; | |
907 | #else | |
908 | env->pc = 0; | |
909 | env->mmuregs[0] &= ~(MMU_E | MMU_NF); | |
910 | env->mmuregs[0] |= env->mmu_bm; | |
911 | #endif | |
912 | env->npc = env->pc + 4; | |
913 | #endif | |
914 | } | |
915 | ||
64a88d5d | 916 | static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model) |
c48fcb47 | 917 | { |
64a88d5d | 918 | sparc_def_t def1, *def = &def1; |
c48fcb47 | 919 | |
64a88d5d BS |
920 | if (cpu_sparc_find_by_name(def, cpu_model) < 0) |
921 | return -1; | |
c48fcb47 | 922 | |
64a88d5d | 923 | env->features = def->features; |
c48fcb47 BS |
924 | env->cpu_model_str = cpu_model; |
925 | env->version = def->iu_version; | |
926 | env->fsr = def->fpu_version; | |
1a14026e | 927 | env->nwindows = def->nwindows; |
c48fcb47 BS |
928 | #if !defined(TARGET_SPARC64) |
929 | env->mmu_bm = def->mmu_bm; | |
930 | env->mmu_ctpr_mask = def->mmu_ctpr_mask; | |
931 | env->mmu_cxr_mask = def->mmu_cxr_mask; | |
932 | env->mmu_sfsr_mask = def->mmu_sfsr_mask; | |
933 | env->mmu_trcr_mask = def->mmu_trcr_mask; | |
934 | env->mmuregs[0] |= def->mmu_version; | |
935 | cpu_sparc_set_id(env, 0); | |
1a14026e BS |
936 | #else |
937 | env->version |= def->nwindows - 1; | |
c48fcb47 | 938 | #endif |
64a88d5d BS |
939 | return 0; |
940 | } | |
941 | ||
942 | static void cpu_sparc_close(CPUSPARCState *env) | |
943 | { | |
944 | free(env); | |
945 | } | |
946 | ||
947 | CPUSPARCState *cpu_sparc_init(const char *cpu_model) | |
948 | { | |
949 | CPUSPARCState *env; | |
950 | ||
951 | env = qemu_mallocz(sizeof(CPUSPARCState)); | |
952 | if (!env) | |
953 | return NULL; | |
954 | cpu_exec_init(env); | |
c48fcb47 BS |
955 | |
956 | gen_intermediate_code_init(env); | |
957 | ||
64a88d5d BS |
958 | if (cpu_sparc_register(env, cpu_model) < 0) { |
959 | cpu_sparc_close(env); | |
960 | return NULL; | |
961 | } | |
c48fcb47 BS |
962 | cpu_reset(env); |
963 | ||
964 | return env; | |
965 | } | |
966 | ||
967 | void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) | |
968 | { | |
969 | #if !defined(TARGET_SPARC64) | |
970 | env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; | |
971 | #endif | |
972 | } | |
973 | ||
974 | static const sparc_def_t sparc_defs[] = { | |
975 | #ifdef TARGET_SPARC64 | |
976 | { | |
977 | .name = "Fujitsu Sparc64", | |
978 | .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24) | |
1a14026e | 979 | | (MAXTL << 8)), |
c48fcb47 BS |
980 | .fpu_version = 0x00000000, |
981 | .mmu_version = 0, | |
1a14026e | 982 | .nwindows = 4, |
64a88d5d | 983 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
984 | }, |
985 | { | |
986 | .name = "Fujitsu Sparc64 III", | |
987 | .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24) | |
1a14026e | 988 | | (MAXTL << 8)), |
c48fcb47 BS |
989 | .fpu_version = 0x00000000, |
990 | .mmu_version = 0, | |
1a14026e | 991 | .nwindows = 5, |
64a88d5d | 992 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
993 | }, |
994 | { | |
995 | .name = "Fujitsu Sparc64 IV", | |
996 | .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24) | |
1a14026e | 997 | | (MAXTL << 8)), |
c48fcb47 BS |
998 | .fpu_version = 0x00000000, |
999 | .mmu_version = 0, | |
1a14026e | 1000 | .nwindows = 8, |
64a88d5d | 1001 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1002 | }, |
1003 | { | |
1004 | .name = "Fujitsu Sparc64 V", | |
1005 | .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24) | |
1a14026e | 1006 | | (MAXTL << 8)), |
c48fcb47 BS |
1007 | .fpu_version = 0x00000000, |
1008 | .mmu_version = 0, | |
1a14026e | 1009 | .nwindows = 8, |
64a88d5d | 1010 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1011 | }, |
1012 | { | |
1013 | .name = "TI UltraSparc I", | |
1014 | .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) | |
1a14026e | 1015 | | (MAXTL << 8)), |
c48fcb47 BS |
1016 | .fpu_version = 0x00000000, |
1017 | .mmu_version = 0, | |
1a14026e | 1018 | .nwindows = 8, |
64a88d5d | 1019 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1020 | }, |
1021 | { | |
1022 | .name = "TI UltraSparc II", | |
1023 | .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24) | |
1a14026e | 1024 | | (MAXTL << 8)), |
c48fcb47 BS |
1025 | .fpu_version = 0x00000000, |
1026 | .mmu_version = 0, | |
1a14026e | 1027 | .nwindows = 8, |
64a88d5d | 1028 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1029 | }, |
1030 | { | |
1031 | .name = "TI UltraSparc IIi", | |
1032 | .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24) | |
1a14026e | 1033 | | (MAXTL << 8)), |
c48fcb47 BS |
1034 | .fpu_version = 0x00000000, |
1035 | .mmu_version = 0, | |
1a14026e | 1036 | .nwindows = 8, |
64a88d5d | 1037 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1038 | }, |
1039 | { | |
1040 | .name = "TI UltraSparc IIe", | |
1041 | .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24) | |
1a14026e | 1042 | | (MAXTL << 8)), |
c48fcb47 BS |
1043 | .fpu_version = 0x00000000, |
1044 | .mmu_version = 0, | |
1a14026e | 1045 | .nwindows = 8, |
64a88d5d | 1046 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1047 | }, |
1048 | { | |
1049 | .name = "Sun UltraSparc III", | |
1050 | .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24) | |
1a14026e | 1051 | | (MAXTL << 8)), |
c48fcb47 BS |
1052 | .fpu_version = 0x00000000, |
1053 | .mmu_version = 0, | |
1a14026e | 1054 | .nwindows = 8, |
64a88d5d | 1055 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1056 | }, |
1057 | { | |
1058 | .name = "Sun UltraSparc III Cu", | |
1059 | .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24) | |
1a14026e | 1060 | | (MAXTL << 8)), |
c48fcb47 BS |
1061 | .fpu_version = 0x00000000, |
1062 | .mmu_version = 0, | |
1a14026e | 1063 | .nwindows = 8, |
64a88d5d | 1064 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1065 | }, |
1066 | { | |
1067 | .name = "Sun UltraSparc IIIi", | |
1068 | .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24) | |
1a14026e | 1069 | | (MAXTL << 8)), |
c48fcb47 BS |
1070 | .fpu_version = 0x00000000, |
1071 | .mmu_version = 0, | |
1a14026e | 1072 | .nwindows = 8, |
64a88d5d | 1073 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1074 | }, |
1075 | { | |
1076 | .name = "Sun UltraSparc IV", | |
1077 | .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24) | |
1a14026e | 1078 | | (MAXTL << 8)), |
c48fcb47 BS |
1079 | .fpu_version = 0x00000000, |
1080 | .mmu_version = 0, | |
1a14026e | 1081 | .nwindows = 8, |
64a88d5d | 1082 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1083 | }, |
1084 | { | |
1085 | .name = "Sun UltraSparc IV+", | |
1086 | .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24) | |
1a14026e | 1087 | | (MAXTL << 8)), |
c48fcb47 BS |
1088 | .fpu_version = 0x00000000, |
1089 | .mmu_version = 0, | |
1a14026e | 1090 | .nwindows = 8, |
64a88d5d | 1091 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1092 | }, |
1093 | { | |
1094 | .name = "Sun UltraSparc IIIi+", | |
1095 | .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24) | |
1a14026e | 1096 | | (MAXTL << 8)), |
c48fcb47 BS |
1097 | .fpu_version = 0x00000000, |
1098 | .mmu_version = 0, | |
1a14026e | 1099 | .nwindows = 8, |
64a88d5d | 1100 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1101 | }, |
1102 | { | |
1103 | .name = "NEC UltraSparc I", | |
1104 | .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) | |
1a14026e | 1105 | | (MAXTL << 8)), |
c48fcb47 BS |
1106 | .fpu_version = 0x00000000, |
1107 | .mmu_version = 0, | |
1a14026e | 1108 | .nwindows = 8, |
64a88d5d | 1109 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1110 | }, |
1111 | #else | |
1112 | { | |
1113 | .name = "Fujitsu MB86900", | |
1114 | .iu_version = 0x00 << 24, /* Impl 0, ver 0 */ | |
1115 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
1116 | .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */ | |
1117 | .mmu_bm = 0x00004000, | |
1118 | .mmu_ctpr_mask = 0x007ffff0, | |
1119 | .mmu_cxr_mask = 0x0000003f, | |
1120 | .mmu_sfsr_mask = 0xffffffff, | |
1121 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1122 | .nwindows = 7, |
e30b4678 | 1123 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD, |
c48fcb47 BS |
1124 | }, |
1125 | { | |
1126 | .name = "Fujitsu MB86904", | |
1127 | .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ | |
1128 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
1129 | .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ | |
1130 | .mmu_bm = 0x00004000, | |
1131 | .mmu_ctpr_mask = 0x00ffffc0, | |
1132 | .mmu_cxr_mask = 0x000000ff, | |
1133 | .mmu_sfsr_mask = 0x00016fff, | |
1134 | .mmu_trcr_mask = 0x00ffffff, | |
1a14026e | 1135 | .nwindows = 8, |
64a88d5d | 1136 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1137 | }, |
1138 | { | |
1139 | .name = "Fujitsu MB86907", | |
1140 | .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ | |
1141 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
1142 | .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ | |
1143 | .mmu_bm = 0x00004000, | |
1144 | .mmu_ctpr_mask = 0xffffffc0, | |
1145 | .mmu_cxr_mask = 0x000000ff, | |
1146 | .mmu_sfsr_mask = 0x00016fff, | |
1147 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1148 | .nwindows = 8, |
64a88d5d | 1149 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1150 | }, |
1151 | { | |
1152 | .name = "LSI L64811", | |
1153 | .iu_version = 0x10 << 24, /* Impl 1, ver 0 */ | |
1154 | .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */ | |
1155 | .mmu_version = 0x10 << 24, | |
1156 | .mmu_bm = 0x00004000, | |
1157 | .mmu_ctpr_mask = 0x007ffff0, | |
1158 | .mmu_cxr_mask = 0x0000003f, | |
1159 | .mmu_sfsr_mask = 0xffffffff, | |
1160 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1161 | .nwindows = 8, |
e30b4678 BS |
1162 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
1163 | CPU_FEATURE_FSMULD, | |
c48fcb47 BS |
1164 | }, |
1165 | { | |
1166 | .name = "Cypress CY7C601", | |
1167 | .iu_version = 0x11 << 24, /* Impl 1, ver 1 */ | |
1168 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ | |
1169 | .mmu_version = 0x10 << 24, | |
1170 | .mmu_bm = 0x00004000, | |
1171 | .mmu_ctpr_mask = 0x007ffff0, | |
1172 | .mmu_cxr_mask = 0x0000003f, | |
1173 | .mmu_sfsr_mask = 0xffffffff, | |
1174 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1175 | .nwindows = 8, |
e30b4678 BS |
1176 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
1177 | CPU_FEATURE_FSMULD, | |
c48fcb47 BS |
1178 | }, |
1179 | { | |
1180 | .name = "Cypress CY7C611", | |
1181 | .iu_version = 0x13 << 24, /* Impl 1, ver 3 */ | |
1182 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ | |
1183 | .mmu_version = 0x10 << 24, | |
1184 | .mmu_bm = 0x00004000, | |
1185 | .mmu_ctpr_mask = 0x007ffff0, | |
1186 | .mmu_cxr_mask = 0x0000003f, | |
1187 | .mmu_sfsr_mask = 0xffffffff, | |
1188 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1189 | .nwindows = 8, |
e30b4678 BS |
1190 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
1191 | CPU_FEATURE_FSMULD, | |
c48fcb47 BS |
1192 | }, |
1193 | { | |
1194 | .name = "TI SuperSparc II", | |
1195 | .iu_version = 0x40000000, | |
1196 | .fpu_version = 0 << 17, | |
1197 | .mmu_version = 0x04000000, | |
1198 | .mmu_bm = 0x00002000, | |
1199 | .mmu_ctpr_mask = 0xffffffc0, | |
1200 | .mmu_cxr_mask = 0x0000ffff, | |
1201 | .mmu_sfsr_mask = 0xffffffff, | |
1202 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1203 | .nwindows = 8, |
64a88d5d | 1204 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1205 | }, |
1206 | { | |
1207 | .name = "TI MicroSparc I", | |
1208 | .iu_version = 0x41000000, | |
1209 | .fpu_version = 4 << 17, | |
1210 | .mmu_version = 0x41000000, | |
1211 | .mmu_bm = 0x00004000, | |
1212 | .mmu_ctpr_mask = 0x007ffff0, | |
1213 | .mmu_cxr_mask = 0x0000003f, | |
1214 | .mmu_sfsr_mask = 0x00016fff, | |
1215 | .mmu_trcr_mask = 0x0000003f, | |
1a14026e | 1216 | .nwindows = 7, |
e30b4678 BS |
1217 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL | |
1218 | CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | | |
1219 | CPU_FEATURE_FMUL, | |
c48fcb47 BS |
1220 | }, |
1221 | { | |
1222 | .name = "TI MicroSparc II", | |
1223 | .iu_version = 0x42000000, | |
1224 | .fpu_version = 4 << 17, | |
1225 | .mmu_version = 0x02000000, | |
1226 | .mmu_bm = 0x00004000, | |
1227 | .mmu_ctpr_mask = 0x00ffffc0, | |
1228 | .mmu_cxr_mask = 0x000000ff, | |
1229 | .mmu_sfsr_mask = 0x00016fff, | |
1230 | .mmu_trcr_mask = 0x00ffffff, | |
1a14026e | 1231 | .nwindows = 8, |
64a88d5d | 1232 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1233 | }, |
1234 | { | |
1235 | .name = "TI MicroSparc IIep", | |
1236 | .iu_version = 0x42000000, | |
1237 | .fpu_version = 4 << 17, | |
1238 | .mmu_version = 0x04000000, | |
1239 | .mmu_bm = 0x00004000, | |
1240 | .mmu_ctpr_mask = 0x00ffffc0, | |
1241 | .mmu_cxr_mask = 0x000000ff, | |
1242 | .mmu_sfsr_mask = 0x00016bff, | |
1243 | .mmu_trcr_mask = 0x00ffffff, | |
1a14026e | 1244 | .nwindows = 8, |
64a88d5d | 1245 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 | 1246 | }, |
b5154bde BS |
1247 | { |
1248 | .name = "TI SuperSparc 40", // STP1020NPGA | |
1249 | .iu_version = 0x41000000, | |
1250 | .fpu_version = 0 << 17, | |
1251 | .mmu_version = 0x00000000, | |
1252 | .mmu_bm = 0x00002000, | |
1253 | .mmu_ctpr_mask = 0xffffffc0, | |
1254 | .mmu_cxr_mask = 0x0000ffff, | |
1255 | .mmu_sfsr_mask = 0xffffffff, | |
1256 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1257 | .nwindows = 8, |
b5154bde BS |
1258 | .features = CPU_DEFAULT_FEATURES, |
1259 | }, | |
1260 | { | |
1261 | .name = "TI SuperSparc 50", // STP1020PGA | |
1262 | .iu_version = 0x40000000, | |
1263 | .fpu_version = 0 << 17, | |
1264 | .mmu_version = 0x04000000, | |
1265 | .mmu_bm = 0x00002000, | |
1266 | .mmu_ctpr_mask = 0xffffffc0, | |
1267 | .mmu_cxr_mask = 0x0000ffff, | |
1268 | .mmu_sfsr_mask = 0xffffffff, | |
1269 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1270 | .nwindows = 8, |
b5154bde BS |
1271 | .features = CPU_DEFAULT_FEATURES, |
1272 | }, | |
c48fcb47 BS |
1273 | { |
1274 | .name = "TI SuperSparc 51", | |
1275 | .iu_version = 0x43000000, | |
1276 | .fpu_version = 0 << 17, | |
1277 | .mmu_version = 0x04000000, | |
1278 | .mmu_bm = 0x00002000, | |
1279 | .mmu_ctpr_mask = 0xffffffc0, | |
1280 | .mmu_cxr_mask = 0x0000ffff, | |
1281 | .mmu_sfsr_mask = 0xffffffff, | |
1282 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1283 | .nwindows = 8, |
64a88d5d | 1284 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 | 1285 | }, |
b5154bde BS |
1286 | { |
1287 | .name = "TI SuperSparc 60", // STP1020APGA | |
1288 | .iu_version = 0x40000000, | |
1289 | .fpu_version = 0 << 17, | |
1290 | .mmu_version = 0x03000000, | |
1291 | .mmu_bm = 0x00002000, | |
1292 | .mmu_ctpr_mask = 0xffffffc0, | |
1293 | .mmu_cxr_mask = 0x0000ffff, | |
1294 | .mmu_sfsr_mask = 0xffffffff, | |
1295 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1296 | .nwindows = 8, |
b5154bde BS |
1297 | .features = CPU_DEFAULT_FEATURES, |
1298 | }, | |
c48fcb47 BS |
1299 | { |
1300 | .name = "TI SuperSparc 61", | |
1301 | .iu_version = 0x44000000, | |
1302 | .fpu_version = 0 << 17, | |
1303 | .mmu_version = 0x04000000, | |
1304 | .mmu_bm = 0x00002000, | |
1305 | .mmu_ctpr_mask = 0xffffffc0, | |
1306 | .mmu_cxr_mask = 0x0000ffff, | |
1307 | .mmu_sfsr_mask = 0xffffffff, | |
1308 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1309 | .nwindows = 8, |
64a88d5d | 1310 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1311 | }, |
1312 | { | |
1313 | .name = "Ross RT625", | |
1314 | .iu_version = 0x1e000000, | |
1315 | .fpu_version = 1 << 17, | |
1316 | .mmu_version = 0x1e000000, | |
1317 | .mmu_bm = 0x00004000, | |
1318 | .mmu_ctpr_mask = 0x007ffff0, | |
1319 | .mmu_cxr_mask = 0x0000003f, | |
1320 | .mmu_sfsr_mask = 0xffffffff, | |
1321 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1322 | .nwindows = 8, |
64a88d5d | 1323 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1324 | }, |
1325 | { | |
1326 | .name = "Ross RT620", | |
1327 | .iu_version = 0x1f000000, | |
1328 | .fpu_version = 1 << 17, | |
1329 | .mmu_version = 0x1f000000, | |
1330 | .mmu_bm = 0x00004000, | |
1331 | .mmu_ctpr_mask = 0x007ffff0, | |
1332 | .mmu_cxr_mask = 0x0000003f, | |
1333 | .mmu_sfsr_mask = 0xffffffff, | |
1334 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1335 | .nwindows = 8, |
64a88d5d | 1336 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1337 | }, |
1338 | { | |
1339 | .name = "BIT B5010", | |
1340 | .iu_version = 0x20000000, | |
1341 | .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */ | |
1342 | .mmu_version = 0x20000000, | |
1343 | .mmu_bm = 0x00004000, | |
1344 | .mmu_ctpr_mask = 0x007ffff0, | |
1345 | .mmu_cxr_mask = 0x0000003f, | |
1346 | .mmu_sfsr_mask = 0xffffffff, | |
1347 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1348 | .nwindows = 8, |
e30b4678 BS |
1349 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
1350 | CPU_FEATURE_FSMULD, | |
c48fcb47 BS |
1351 | }, |
1352 | { | |
1353 | .name = "Matsushita MN10501", | |
1354 | .iu_version = 0x50000000, | |
1355 | .fpu_version = 0 << 17, | |
1356 | .mmu_version = 0x50000000, | |
1357 | .mmu_bm = 0x00004000, | |
1358 | .mmu_ctpr_mask = 0x007ffff0, | |
1359 | .mmu_cxr_mask = 0x0000003f, | |
1360 | .mmu_sfsr_mask = 0xffffffff, | |
1361 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1362 | .nwindows = 8, |
e30b4678 BS |
1363 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT | |
1364 | CPU_FEATURE_FSMULD, | |
c48fcb47 BS |
1365 | }, |
1366 | { | |
1367 | .name = "Weitek W8601", | |
1368 | .iu_version = 0x90 << 24, /* Impl 9, ver 0 */ | |
1369 | .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */ | |
1370 | .mmu_version = 0x10 << 24, | |
1371 | .mmu_bm = 0x00004000, | |
1372 | .mmu_ctpr_mask = 0x007ffff0, | |
1373 | .mmu_cxr_mask = 0x0000003f, | |
1374 | .mmu_sfsr_mask = 0xffffffff, | |
1375 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1376 | .nwindows = 8, |
64a88d5d | 1377 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1378 | }, |
1379 | { | |
1380 | .name = "LEON2", | |
1381 | .iu_version = 0xf2000000, | |
1382 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
1383 | .mmu_version = 0xf2000000, | |
1384 | .mmu_bm = 0x00004000, | |
1385 | .mmu_ctpr_mask = 0x007ffff0, | |
1386 | .mmu_cxr_mask = 0x0000003f, | |
1387 | .mmu_sfsr_mask = 0xffffffff, | |
1388 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1389 | .nwindows = 8, |
64a88d5d | 1390 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1391 | }, |
1392 | { | |
1393 | .name = "LEON3", | |
1394 | .iu_version = 0xf3000000, | |
1395 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
1396 | .mmu_version = 0xf3000000, | |
1397 | .mmu_bm = 0x00004000, | |
1398 | .mmu_ctpr_mask = 0x007ffff0, | |
1399 | .mmu_cxr_mask = 0x0000003f, | |
1400 | .mmu_sfsr_mask = 0xffffffff, | |
1401 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1402 | .nwindows = 8, |
64a88d5d | 1403 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1404 | }, |
1405 | #endif | |
1406 | }; | |
1407 | ||
64a88d5d BS |
1408 | static const char * const feature_name[] = { |
1409 | "float", | |
1410 | "float128", | |
1411 | "swap", | |
1412 | "mul", | |
1413 | "div", | |
1414 | "flush", | |
1415 | "fsqrt", | |
1416 | "fmul", | |
1417 | "vis1", | |
1418 | "vis2", | |
e30b4678 | 1419 | "fsmuld", |
64a88d5d BS |
1420 | }; |
1421 | ||
1422 | static void print_features(FILE *f, | |
1423 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), | |
1424 | uint32_t features, const char *prefix) | |
c48fcb47 BS |
1425 | { |
1426 | unsigned int i; | |
1427 | ||
64a88d5d BS |
1428 | for (i = 0; i < ARRAY_SIZE(feature_name); i++) |
1429 | if (feature_name[i] && (features & (1 << i))) { | |
1430 | if (prefix) | |
1431 | (*cpu_fprintf)(f, "%s", prefix); | |
1432 | (*cpu_fprintf)(f, "%s ", feature_name[i]); | |
1433 | } | |
1434 | } | |
1435 | ||
1436 | static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features) | |
1437 | { | |
1438 | unsigned int i; | |
1439 | ||
1440 | for (i = 0; i < ARRAY_SIZE(feature_name); i++) | |
1441 | if (feature_name[i] && !strcmp(flagname, feature_name[i])) { | |
1442 | *features |= 1 << i; | |
1443 | return; | |
1444 | } | |
1445 | fprintf(stderr, "CPU feature %s not found\n", flagname); | |
1446 | } | |
1447 | ||
22548760 | 1448 | static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model) |
64a88d5d BS |
1449 | { |
1450 | unsigned int i; | |
1451 | const sparc_def_t *def = NULL; | |
1452 | char *s = strdup(cpu_model); | |
1453 | char *featurestr, *name = strtok(s, ","); | |
1454 | uint32_t plus_features = 0; | |
1455 | uint32_t minus_features = 0; | |
1456 | long long iu_version; | |
1a14026e | 1457 | uint32_t fpu_version, mmu_version, nwindows; |
64a88d5d | 1458 | |
c48fcb47 BS |
1459 | for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
1460 | if (strcasecmp(name, sparc_defs[i].name) == 0) { | |
64a88d5d | 1461 | def = &sparc_defs[i]; |
c48fcb47 BS |
1462 | } |
1463 | } | |
64a88d5d BS |
1464 | if (!def) |
1465 | goto error; | |
1466 | memcpy(cpu_def, def, sizeof(*def)); | |
1467 | ||
1468 | featurestr = strtok(NULL, ","); | |
1469 | while (featurestr) { | |
1470 | char *val; | |
1471 | ||
1472 | if (featurestr[0] == '+') { | |
1473 | add_flagname_to_bitmaps(featurestr + 1, &plus_features); | |
1474 | } else if (featurestr[0] == '-') { | |
1475 | add_flagname_to_bitmaps(featurestr + 1, &minus_features); | |
1476 | } else if ((val = strchr(featurestr, '='))) { | |
1477 | *val = 0; val++; | |
1478 | if (!strcmp(featurestr, "iu_version")) { | |
1479 | char *err; | |
1480 | ||
1481 | iu_version = strtoll(val, &err, 0); | |
1482 | if (!*val || *err) { | |
1483 | fprintf(stderr, "bad numerical value %s\n", val); | |
1484 | goto error; | |
1485 | } | |
1486 | cpu_def->iu_version = iu_version; | |
1487 | #ifdef DEBUG_FEATURES | |
1488 | fprintf(stderr, "iu_version %llx\n", iu_version); | |
1489 | #endif | |
1490 | } else if (!strcmp(featurestr, "fpu_version")) { | |
1491 | char *err; | |
1492 | ||
1493 | fpu_version = strtol(val, &err, 0); | |
1494 | if (!*val || *err) { | |
1495 | fprintf(stderr, "bad numerical value %s\n", val); | |
1496 | goto error; | |
1497 | } | |
1498 | cpu_def->fpu_version = fpu_version; | |
1499 | #ifdef DEBUG_FEATURES | |
1500 | fprintf(stderr, "fpu_version %llx\n", fpu_version); | |
1501 | #endif | |
1502 | } else if (!strcmp(featurestr, "mmu_version")) { | |
1503 | char *err; | |
1504 | ||
1505 | mmu_version = strtol(val, &err, 0); | |
1506 | if (!*val || *err) { | |
1507 | fprintf(stderr, "bad numerical value %s\n", val); | |
1508 | goto error; | |
1509 | } | |
1510 | cpu_def->mmu_version = mmu_version; | |
1511 | #ifdef DEBUG_FEATURES | |
1512 | fprintf(stderr, "mmu_version %llx\n", mmu_version); | |
1a14026e BS |
1513 | #endif |
1514 | } else if (!strcmp(featurestr, "nwindows")) { | |
1515 | char *err; | |
1516 | ||
1517 | nwindows = strtol(val, &err, 0); | |
1518 | if (!*val || *err || nwindows > MAX_NWINDOWS || | |
1519 | nwindows < MIN_NWINDOWS) { | |
1520 | fprintf(stderr, "bad numerical value %s\n", val); | |
1521 | goto error; | |
1522 | } | |
1523 | cpu_def->nwindows = nwindows; | |
1524 | #ifdef DEBUG_FEATURES | |
1525 | fprintf(stderr, "nwindows %d\n", nwindows); | |
64a88d5d BS |
1526 | #endif |
1527 | } else { | |
1528 | fprintf(stderr, "unrecognized feature %s\n", featurestr); | |
1529 | goto error; | |
1530 | } | |
1531 | } else { | |
77f193da BS |
1532 | fprintf(stderr, "feature string `%s' not in format " |
1533 | "(+feature|-feature|feature=xyz)\n", featurestr); | |
64a88d5d BS |
1534 | goto error; |
1535 | } | |
1536 | featurestr = strtok(NULL, ","); | |
1537 | } | |
1538 | cpu_def->features |= plus_features; | |
1539 | cpu_def->features &= ~minus_features; | |
1540 | #ifdef DEBUG_FEATURES | |
1541 | print_features(stderr, fprintf, cpu_def->features, NULL); | |
1542 | #endif | |
1543 | free(s); | |
1544 | return 0; | |
1545 | ||
1546 | error: | |
1547 | free(s); | |
1548 | return -1; | |
c48fcb47 BS |
1549 | } |
1550 | ||
77f193da | 1551 | void sparc_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
c48fcb47 BS |
1552 | { |
1553 | unsigned int i; | |
1554 | ||
1555 | for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { | |
1a14026e | 1556 | (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x NWINS %d ", |
c48fcb47 BS |
1557 | sparc_defs[i].name, |
1558 | sparc_defs[i].iu_version, | |
1559 | sparc_defs[i].fpu_version, | |
1a14026e BS |
1560 | sparc_defs[i].mmu_version, |
1561 | sparc_defs[i].nwindows); | |
77f193da BS |
1562 | print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES & |
1563 | ~sparc_defs[i].features, "-"); | |
1564 | print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES & | |
1565 | sparc_defs[i].features, "+"); | |
64a88d5d | 1566 | (*cpu_fprintf)(f, "\n"); |
c48fcb47 | 1567 | } |
64a88d5d BS |
1568 | (*cpu_fprintf)(f, "CPU feature flags (+/-): "); |
1569 | print_features(f, cpu_fprintf, -1, NULL); | |
1570 | (*cpu_fprintf)(f, "\n"); | |
77f193da | 1571 | (*cpu_fprintf)(f, "Numerical features (=): iu_version fpu_version " |
1a14026e | 1572 | "mmu_version nwindows\n"); |
c48fcb47 BS |
1573 | } |
1574 | ||
1575 | #define GET_FLAG(a,b) ((env->psr & a)?b:'-') | |
1576 | ||
1577 | void cpu_dump_state(CPUState *env, FILE *f, | |
1578 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), | |
1579 | int flags) | |
1580 | { | |
1581 | int i, x; | |
1582 | ||
77f193da BS |
1583 | cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, |
1584 | env->npc); | |
c48fcb47 BS |
1585 | cpu_fprintf(f, "General Registers:\n"); |
1586 | for (i = 0; i < 4; i++) | |
1587 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); | |
1588 | cpu_fprintf(f, "\n"); | |
1589 | for (; i < 8; i++) | |
1590 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); | |
1591 | cpu_fprintf(f, "\nCurrent Register Window:\n"); | |
1592 | for (x = 0; x < 3; x++) { | |
1593 | for (i = 0; i < 4; i++) | |
1594 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", | |
1595 | (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i, | |
1596 | env->regwptr[i + x * 8]); | |
1597 | cpu_fprintf(f, "\n"); | |
1598 | for (; i < 8; i++) | |
1599 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", | |
1600 | (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i, | |
1601 | env->regwptr[i + x * 8]); | |
1602 | cpu_fprintf(f, "\n"); | |
1603 | } | |
1604 | cpu_fprintf(f, "\nFloating Point Registers:\n"); | |
1605 | for (i = 0; i < 32; i++) { | |
1606 | if ((i & 3) == 0) | |
1607 | cpu_fprintf(f, "%%f%02d:", i); | |
a37ee56c | 1608 | cpu_fprintf(f, " %016f", *(float *)&env->fpr[i]); |
c48fcb47 BS |
1609 | if ((i & 3) == 3) |
1610 | cpu_fprintf(f, "\n"); | |
1611 | } | |
1612 | #ifdef TARGET_SPARC64 | |
1613 | cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n", | |
1614 | env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs); | |
77f193da BS |
1615 | cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d " |
1616 | "cleanwin %d cwp %d\n", | |
c48fcb47 | 1617 | env->cansave, env->canrestore, env->otherwin, env->wstate, |
1a14026e | 1618 | env->cleanwin, env->nwindows - 1 - env->cwp); |
c48fcb47 | 1619 | #else |
77f193da BS |
1620 | cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", |
1621 | GET_PSR(env), GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), | |
1622 | GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), | |
1623 | env->psrs?'S':'-', env->psrps?'P':'-', | |
1624 | env->psret?'E':'-', env->wim); | |
c48fcb47 BS |
1625 | #endif |
1626 | cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env)); | |
1627 | } | |
1628 | ||
87ecb68b PB |
1629 | #ifdef TARGET_SPARC64 |
1630 | #if !defined(CONFIG_USER_ONLY) | |
1631 | #include "qemu-common.h" | |
1632 | #include "hw/irq.h" | |
1633 | #include "qemu-timer.h" | |
1634 | #endif | |
1635 | ||
ccd4a219 | 1636 | void helper_tick_set_count(void *opaque, uint64_t count) |
87ecb68b PB |
1637 | { |
1638 | #if !defined(CONFIG_USER_ONLY) | |
1639 | ptimer_set_count(opaque, -count); | |
1640 | #endif | |
1641 | } | |
1642 | ||
ccd4a219 | 1643 | uint64_t helper_tick_get_count(void *opaque) |
87ecb68b PB |
1644 | { |
1645 | #if !defined(CONFIG_USER_ONLY) | |
1646 | return -ptimer_get_count(opaque); | |
1647 | #else | |
1648 | return 0; | |
1649 | #endif | |
1650 | } | |
1651 | ||
ccd4a219 | 1652 | void helper_tick_set_limit(void *opaque, uint64_t limit) |
87ecb68b PB |
1653 | { |
1654 | #if !defined(CONFIG_USER_ONLY) | |
1655 | ptimer_set_limit(opaque, -limit, 0); | |
1656 | #endif | |
1657 | } | |
1658 | #endif |