]>
Commit | Line | Data |
---|---|---|
ab3b491f BS |
1 | /* |
2 | * Sparc64 interrupt helpers | |
3 | * | |
4 | * Copyright (c) 2003-2005 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "cpu.h" | |
79227036 | 21 | #include "helper.h" |
11e66bca | 22 | #include "trace.h" |
ab3b491f | 23 | |
b884fc5e | 24 | #define DEBUG_PCALL |
ab3b491f BS |
25 | |
26 | #ifdef DEBUG_PCALL | |
27 | static const char * const excp_names[0x80] = { | |
28 | [TT_TFAULT] = "Instruction Access Fault", | |
29 | [TT_TMISS] = "Instruction Access MMU Miss", | |
30 | [TT_CODE_ACCESS] = "Instruction Access Error", | |
31 | [TT_ILL_INSN] = "Illegal Instruction", | |
32 | [TT_PRIV_INSN] = "Privileged Instruction", | |
33 | [TT_NFPU_INSN] = "FPU Disabled", | |
34 | [TT_FP_EXCP] = "FPU Exception", | |
35 | [TT_TOVF] = "Tag Overflow", | |
36 | [TT_CLRWIN] = "Clean Windows", | |
37 | [TT_DIV_ZERO] = "Division By Zero", | |
38 | [TT_DFAULT] = "Data Access Fault", | |
39 | [TT_DMISS] = "Data Access MMU Miss", | |
40 | [TT_DATA_ACCESS] = "Data Access Error", | |
41 | [TT_DPROT] = "Data Protection Error", | |
42 | [TT_UNALIGNED] = "Unaligned Memory Access", | |
43 | [TT_PRIV_ACT] = "Privileged Action", | |
44 | [TT_EXTINT | 0x1] = "External Interrupt 1", | |
45 | [TT_EXTINT | 0x2] = "External Interrupt 2", | |
46 | [TT_EXTINT | 0x3] = "External Interrupt 3", | |
47 | [TT_EXTINT | 0x4] = "External Interrupt 4", | |
48 | [TT_EXTINT | 0x5] = "External Interrupt 5", | |
49 | [TT_EXTINT | 0x6] = "External Interrupt 6", | |
50 | [TT_EXTINT | 0x7] = "External Interrupt 7", | |
51 | [TT_EXTINT | 0x8] = "External Interrupt 8", | |
52 | [TT_EXTINT | 0x9] = "External Interrupt 9", | |
53 | [TT_EXTINT | 0xa] = "External Interrupt 10", | |
54 | [TT_EXTINT | 0xb] = "External Interrupt 11", | |
55 | [TT_EXTINT | 0xc] = "External Interrupt 12", | |
56 | [TT_EXTINT | 0xd] = "External Interrupt 13", | |
57 | [TT_EXTINT | 0xe] = "External Interrupt 14", | |
58 | [TT_EXTINT | 0xf] = "External Interrupt 15", | |
59 | }; | |
60 | #endif | |
61 | ||
c5f9864e | 62 | void do_interrupt(CPUSPARCState *env) |
ab3b491f BS |
63 | { |
64 | int intno = env->exception_index; | |
65 | trap_state *tsptr; | |
66 | ||
20132b96 RH |
67 | /* Compute PSR before exposing state. */ |
68 | if (env->cc_op != CC_OP_FLAGS) { | |
69 | cpu_get_psr(env); | |
70 | } | |
71 | ||
ab3b491f BS |
72 | #ifdef DEBUG_PCALL |
73 | if (qemu_loglevel_mask(CPU_LOG_INT)) { | |
74 | static int count; | |
75 | const char *name; | |
76 | ||
77 | if (intno < 0 || intno >= 0x180) { | |
78 | name = "Unknown"; | |
79 | } else if (intno >= 0x100) { | |
80 | name = "Trap Instruction"; | |
81 | } else if (intno >= 0xc0) { | |
82 | name = "Window Fill"; | |
83 | } else if (intno >= 0x80) { | |
84 | name = "Window Spill"; | |
85 | } else { | |
86 | name = excp_names[intno]; | |
87 | if (!name) { | |
88 | name = "Unknown"; | |
89 | } | |
90 | } | |
91 | ||
b884fc5e | 92 | qemu_log("%6d: %s (v=%04x)\n", count, name, intno); |
ab3b491f BS |
93 | log_cpu_state(env, 0); |
94 | #if 0 | |
95 | { | |
96 | int i; | |
97 | uint8_t *ptr; | |
98 | ||
99 | qemu_log(" code="); | |
100 | ptr = (uint8_t *)env->pc; | |
101 | for (i = 0; i < 16; i++) { | |
102 | qemu_log(" %02x", ldub(ptr + i)); | |
103 | } | |
104 | qemu_log("\n"); | |
105 | } | |
106 | #endif | |
107 | count++; | |
108 | } | |
109 | #endif | |
110 | #if !defined(CONFIG_USER_ONLY) | |
111 | if (env->tl >= env->maxtl) { | |
112 | cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d)," | |
113 | " Error state", env->exception_index, env->tl, env->maxtl); | |
114 | return; | |
115 | } | |
116 | #endif | |
117 | if (env->tl < env->maxtl - 1) { | |
118 | env->tl++; | |
119 | } else { | |
120 | env->pstate |= PS_RED; | |
121 | if (env->tl < env->maxtl) { | |
122 | env->tl++; | |
123 | } | |
124 | } | |
125 | tsptr = cpu_tsptr(env); | |
126 | ||
127 | tsptr->tstate = (cpu_get_ccr(env) << 32) | | |
128 | ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | | |
129 | cpu_get_cwp64(env); | |
130 | tsptr->tpc = env->pc; | |
131 | tsptr->tnpc = env->npc; | |
132 | tsptr->tt = intno; | |
133 | ||
134 | switch (intno) { | |
135 | case TT_IVEC: | |
136 | cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_IG); | |
137 | break; | |
138 | case TT_TFAULT: | |
139 | case TT_DFAULT: | |
140 | case TT_TMISS ... TT_TMISS + 3: | |
141 | case TT_DMISS ... TT_DMISS + 3: | |
142 | case TT_DPROT ... TT_DPROT + 3: | |
143 | cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_MG); | |
144 | break; | |
145 | default: | |
146 | cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_AG); | |
147 | break; | |
148 | } | |
149 | ||
150 | if (intno == TT_CLRWIN) { | |
151 | cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1)); | |
152 | } else if ((intno & 0x1c0) == TT_SPILL) { | |
153 | cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2)); | |
154 | } else if ((intno & 0x1c0) == TT_FILL) { | |
155 | cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1)); | |
156 | } | |
157 | env->tbr &= ~0x7fffULL; | |
158 | env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); | |
159 | env->pc = env->tbr; | |
160 | env->npc = env->pc + 4; | |
161 | env->exception_index = -1; | |
162 | } | |
2336c1f1 | 163 | |
c5f9864e | 164 | trap_state *cpu_tsptr(CPUSPARCState* env) |
2336c1f1 BS |
165 | { |
166 | return &env->ts[env->tl & MAXTL_MASK]; | |
167 | } | |
79227036 | 168 | |
c5f9864e | 169 | static bool do_modify_softint(CPUSPARCState *env, uint32_t value) |
79227036 BS |
170 | { |
171 | if (env->softint != value) { | |
172 | env->softint = value; | |
79227036 BS |
173 | #if !defined(CONFIG_USER_ONLY) |
174 | if (cpu_interrupts_enabled(env)) { | |
175 | cpu_check_irqs(env); | |
176 | } | |
177 | #endif | |
11e66bca | 178 | return true; |
79227036 | 179 | } |
11e66bca | 180 | return false; |
79227036 BS |
181 | } |
182 | ||
c5f9864e | 183 | void helper_set_softint(CPUSPARCState *env, uint64_t value) |
79227036 | 184 | { |
11e66bca BS |
185 | if (do_modify_softint(env, env->softint | (uint32_t)value)) { |
186 | trace_int_helper_set_softint(env->softint); | |
187 | } | |
79227036 BS |
188 | } |
189 | ||
c5f9864e | 190 | void helper_clear_softint(CPUSPARCState *env, uint64_t value) |
79227036 | 191 | { |
11e66bca BS |
192 | if (do_modify_softint(env, env->softint & (uint32_t)~value)) { |
193 | trace_int_helper_clear_softint(env->softint); | |
194 | } | |
79227036 BS |
195 | } |
196 | ||
c5f9864e | 197 | void helper_write_softint(CPUSPARCState *env, uint64_t value) |
79227036 | 198 | { |
11e66bca BS |
199 | if (do_modify_softint(env, (uint32_t)value)) { |
200 | trace_int_helper_write_softint(env->softint); | |
201 | } | |
79227036 | 202 | } |