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1 | /* |
2 | * Sparc MMU helpers | |
3 | * | |
4 | * Copyright (c) 2003-2005 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "cpu.h" | |
21 | ||
22 | //#define DEBUG_MMU | |
23 | ||
24 | #ifdef DEBUG_MMU | |
25 | #define DPRINTF_MMU(fmt, ...) \ | |
26 | do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0) | |
27 | #else | |
28 | #define DPRINTF_MMU(fmt, ...) do {} while (0) | |
29 | #endif | |
30 | ||
31 | /* Sparc MMU emulation */ | |
32 | ||
33 | #if defined(CONFIG_USER_ONLY) | |
34 | ||
35 | int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw, | |
36 | int mmu_idx) | |
37 | { | |
38 | if (rw & 2) { | |
39 | env1->exception_index = TT_TFAULT; | |
40 | } else { | |
41 | env1->exception_index = TT_DFAULT; | |
42 | } | |
43 | return 1; | |
44 | } | |
45 | ||
46 | #else | |
47 | ||
48 | #ifndef TARGET_SPARC64 | |
49 | /* | |
50 | * Sparc V8 Reference MMU (SRMMU) | |
51 | */ | |
52 | static const int access_table[8][8] = { | |
53 | { 0, 0, 0, 0, 8, 0, 12, 12 }, | |
54 | { 0, 0, 0, 0, 8, 0, 0, 0 }, | |
55 | { 8, 8, 0, 0, 0, 8, 12, 12 }, | |
56 | { 8, 8, 0, 0, 0, 8, 0, 0 }, | |
57 | { 8, 0, 8, 0, 8, 8, 12, 12 }, | |
58 | { 8, 0, 8, 0, 8, 0, 8, 0 }, | |
59 | { 8, 8, 8, 0, 8, 8, 12, 12 }, | |
60 | { 8, 8, 8, 0, 8, 8, 8, 0 } | |
61 | }; | |
62 | ||
63 | static const int perm_table[2][8] = { | |
64 | { | |
65 | PAGE_READ, | |
66 | PAGE_READ | PAGE_WRITE, | |
67 | PAGE_READ | PAGE_EXEC, | |
68 | PAGE_READ | PAGE_WRITE | PAGE_EXEC, | |
69 | PAGE_EXEC, | |
70 | PAGE_READ | PAGE_WRITE, | |
71 | PAGE_READ | PAGE_EXEC, | |
72 | PAGE_READ | PAGE_WRITE | PAGE_EXEC | |
73 | }, | |
74 | { | |
75 | PAGE_READ, | |
76 | PAGE_READ | PAGE_WRITE, | |
77 | PAGE_READ | PAGE_EXEC, | |
78 | PAGE_READ | PAGE_WRITE | PAGE_EXEC, | |
79 | PAGE_EXEC, | |
80 | PAGE_READ, | |
81 | 0, | |
82 | 0, | |
83 | } | |
84 | }; | |
85 | ||
86 | static int get_physical_address(CPUState *env, target_phys_addr_t *physical, | |
87 | int *prot, int *access_index, | |
88 | target_ulong address, int rw, int mmu_idx, | |
89 | target_ulong *page_size) | |
90 | { | |
91 | int access_perms = 0; | |
92 | target_phys_addr_t pde_ptr; | |
93 | uint32_t pde; | |
94 | int error_code = 0, is_dirty, is_user; | |
95 | unsigned long page_offset; | |
96 | ||
97 | is_user = mmu_idx == MMU_USER_IDX; | |
98 | ||
99 | if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ | |
100 | *page_size = TARGET_PAGE_SIZE; | |
101 | /* Boot mode: instruction fetches are taken from PROM */ | |
102 | if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) { | |
103 | *physical = env->prom_addr | (address & 0x7ffffULL); | |
104 | *prot = PAGE_READ | PAGE_EXEC; | |
105 | return 0; | |
106 | } | |
107 | *physical = address; | |
108 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
109 | return 0; | |
110 | } | |
111 | ||
112 | *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user ? 0 : 1); | |
113 | *physical = 0xffffffffffff0000ULL; | |
114 | ||
115 | /* SPARC reference MMU table walk: Context table->L1->L2->PTE */ | |
116 | /* Context base + context number */ | |
117 | pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); | |
118 | pde = ldl_phys(pde_ptr); | |
119 | ||
120 | /* Ctx pde */ | |
121 | switch (pde & PTE_ENTRYTYPE_MASK) { | |
122 | default: | |
123 | case 0: /* Invalid */ | |
124 | return 1 << 2; | |
125 | case 2: /* L0 PTE, maybe should not happen? */ | |
126 | case 3: /* Reserved */ | |
127 | return 4 << 2; | |
128 | case 1: /* L0 PDE */ | |
129 | pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); | |
130 | pde = ldl_phys(pde_ptr); | |
131 | ||
132 | switch (pde & PTE_ENTRYTYPE_MASK) { | |
133 | default: | |
134 | case 0: /* Invalid */ | |
135 | return (1 << 8) | (1 << 2); | |
136 | case 3: /* Reserved */ | |
137 | return (1 << 8) | (4 << 2); | |
138 | case 1: /* L1 PDE */ | |
139 | pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); | |
140 | pde = ldl_phys(pde_ptr); | |
141 | ||
142 | switch (pde & PTE_ENTRYTYPE_MASK) { | |
143 | default: | |
144 | case 0: /* Invalid */ | |
145 | return (2 << 8) | (1 << 2); | |
146 | case 3: /* Reserved */ | |
147 | return (2 << 8) | (4 << 2); | |
148 | case 1: /* L2 PDE */ | |
149 | pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); | |
150 | pde = ldl_phys(pde_ptr); | |
151 | ||
152 | switch (pde & PTE_ENTRYTYPE_MASK) { | |
153 | default: | |
154 | case 0: /* Invalid */ | |
155 | return (3 << 8) | (1 << 2); | |
156 | case 1: /* PDE, should not happen */ | |
157 | case 3: /* Reserved */ | |
158 | return (3 << 8) | (4 << 2); | |
159 | case 2: /* L3 PTE */ | |
160 | page_offset = (address & TARGET_PAGE_MASK) & | |
161 | (TARGET_PAGE_SIZE - 1); | |
162 | } | |
163 | *page_size = TARGET_PAGE_SIZE; | |
164 | break; | |
165 | case 2: /* L2 PTE */ | |
166 | page_offset = address & 0x3ffff; | |
167 | *page_size = 0x40000; | |
168 | } | |
169 | break; | |
170 | case 2: /* L1 PTE */ | |
171 | page_offset = address & 0xffffff; | |
172 | *page_size = 0x1000000; | |
173 | } | |
174 | } | |
175 | ||
176 | /* check access */ | |
177 | access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT; | |
178 | error_code = access_table[*access_index][access_perms]; | |
179 | if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user)) { | |
180 | return error_code; | |
181 | } | |
182 | ||
183 | /* update page modified and dirty bits */ | |
184 | is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK); | |
185 | if (!(pde & PG_ACCESSED_MASK) || is_dirty) { | |
186 | pde |= PG_ACCESSED_MASK; | |
187 | if (is_dirty) { | |
188 | pde |= PG_MODIFIED_MASK; | |
189 | } | |
190 | stl_phys_notdirty(pde_ptr, pde); | |
191 | } | |
192 | ||
193 | /* the page can be put in the TLB */ | |
194 | *prot = perm_table[is_user][access_perms]; | |
195 | if (!(pde & PG_MODIFIED_MASK)) { | |
196 | /* only set write access if already dirty... otherwise wait | |
197 | for dirty access */ | |
198 | *prot &= ~PAGE_WRITE; | |
199 | } | |
200 | ||
201 | /* Even if large ptes, we map only one 4KB page in the cache to | |
202 | avoid filling it too fast */ | |
203 | *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset; | |
204 | return error_code; | |
205 | } | |
206 | ||
207 | /* Perform address translation */ | |
208 | int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw, | |
209 | int mmu_idx) | |
210 | { | |
211 | target_phys_addr_t paddr; | |
212 | target_ulong vaddr; | |
213 | target_ulong page_size; | |
214 | int error_code = 0, prot, access_index; | |
215 | ||
216 | error_code = get_physical_address(env, &paddr, &prot, &access_index, | |
217 | address, rw, mmu_idx, &page_size); | |
218 | if (error_code == 0) { | |
219 | vaddr = address & TARGET_PAGE_MASK; | |
220 | paddr &= TARGET_PAGE_MASK; | |
221 | #ifdef DEBUG_MMU | |
222 | printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr " | |
223 | TARGET_FMT_lx "\n", address, paddr, vaddr); | |
224 | #endif | |
225 | tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size); | |
226 | return 0; | |
227 | } | |
228 | ||
229 | if (env->mmuregs[3]) { /* Fault status register */ | |
230 | env->mmuregs[3] = 1; /* overflow (not read before another fault) */ | |
231 | } | |
232 | env->mmuregs[3] |= (access_index << 5) | error_code | 2; | |
233 | env->mmuregs[4] = address; /* Fault address register */ | |
234 | ||
235 | if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { | |
236 | /* No fault mode: if a mapping is available, just override | |
237 | permissions. If no mapping is available, redirect accesses to | |
238 | neverland. Fake/overridden mappings will be flushed when | |
239 | switching to normal mode. */ | |
240 | vaddr = address & TARGET_PAGE_MASK; | |
241 | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
242 | tlb_set_page(env, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); | |
243 | return 0; | |
244 | } else { | |
245 | if (rw & 2) { | |
246 | env->exception_index = TT_TFAULT; | |
247 | } else { | |
248 | env->exception_index = TT_DFAULT; | |
249 | } | |
250 | return 1; | |
251 | } | |
252 | } | |
253 | ||
254 | target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev) | |
255 | { | |
256 | target_phys_addr_t pde_ptr; | |
257 | uint32_t pde; | |
258 | ||
259 | /* Context base + context number */ | |
260 | pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) + | |
261 | (env->mmuregs[2] << 2); | |
262 | pde = ldl_phys(pde_ptr); | |
263 | ||
264 | switch (pde & PTE_ENTRYTYPE_MASK) { | |
265 | default: | |
266 | case 0: /* Invalid */ | |
267 | case 2: /* PTE, maybe should not happen? */ | |
268 | case 3: /* Reserved */ | |
269 | return 0; | |
270 | case 1: /* L1 PDE */ | |
271 | if (mmulev == 3) { | |
272 | return pde; | |
273 | } | |
274 | pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); | |
275 | pde = ldl_phys(pde_ptr); | |
276 | ||
277 | switch (pde & PTE_ENTRYTYPE_MASK) { | |
278 | default: | |
279 | case 0: /* Invalid */ | |
280 | case 3: /* Reserved */ | |
281 | return 0; | |
282 | case 2: /* L1 PTE */ | |
283 | return pde; | |
284 | case 1: /* L2 PDE */ | |
285 | if (mmulev == 2) { | |
286 | return pde; | |
287 | } | |
288 | pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); | |
289 | pde = ldl_phys(pde_ptr); | |
290 | ||
291 | switch (pde & PTE_ENTRYTYPE_MASK) { | |
292 | default: | |
293 | case 0: /* Invalid */ | |
294 | case 3: /* Reserved */ | |
295 | return 0; | |
296 | case 2: /* L2 PTE */ | |
297 | return pde; | |
298 | case 1: /* L3 PDE */ | |
299 | if (mmulev == 1) { | |
300 | return pde; | |
301 | } | |
302 | pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); | |
303 | pde = ldl_phys(pde_ptr); | |
304 | ||
305 | switch (pde & PTE_ENTRYTYPE_MASK) { | |
306 | default: | |
307 | case 0: /* Invalid */ | |
308 | case 1: /* PDE, should not happen */ | |
309 | case 3: /* Reserved */ | |
310 | return 0; | |
311 | case 2: /* L3 PTE */ | |
312 | return pde; | |
313 | } | |
314 | } | |
315 | } | |
316 | } | |
317 | return 0; | |
318 | } | |
319 | ||
320 | void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env) | |
321 | { | |
322 | target_ulong va, va1, va2; | |
323 | unsigned int n, m, o; | |
324 | target_phys_addr_t pde_ptr, pa; | |
325 | uint32_t pde; | |
326 | ||
327 | pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); | |
328 | pde = ldl_phys(pde_ptr); | |
329 | (*cpu_fprintf)(f, "Root ptr: " TARGET_FMT_plx ", ctx: %d\n", | |
330 | (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]); | |
331 | for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { | |
332 | pde = mmu_probe(env, va, 2); | |
333 | if (pde) { | |
334 | pa = cpu_get_phys_page_debug(env, va); | |
335 | (*cpu_fprintf)(f, "VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx | |
336 | " PDE: " TARGET_FMT_lx "\n", va, pa, pde); | |
337 | for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) { | |
338 | pde = mmu_probe(env, va1, 1); | |
339 | if (pde) { | |
340 | pa = cpu_get_phys_page_debug(env, va1); | |
341 | (*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: " | |
342 | TARGET_FMT_plx " PDE: " TARGET_FMT_lx "\n", | |
343 | va1, pa, pde); | |
344 | for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { | |
345 | pde = mmu_probe(env, va2, 0); | |
346 | if (pde) { | |
347 | pa = cpu_get_phys_page_debug(env, va2); | |
348 | (*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: " | |
349 | TARGET_FMT_plx " PTE: " | |
350 | TARGET_FMT_lx "\n", | |
351 | va2, pa, pde); | |
352 | } | |
353 | } | |
354 | } | |
355 | } | |
356 | } | |
357 | } | |
358 | } | |
359 | ||
360 | /* Gdb expects all registers windows to be flushed in ram. This function handles | |
361 | * reads (and only reads) in stack frames as if windows were flushed. We assume | |
362 | * that the sparc ABI is followed. | |
363 | */ | |
364 | int target_memory_rw_debug(CPUState *env, target_ulong addr, | |
365 | uint8_t *buf, int len, int is_write) | |
366 | { | |
367 | int i; | |
368 | int len1; | |
369 | int cwp = env->cwp; | |
370 | ||
371 | if (!is_write) { | |
372 | for (i = 0; i < env->nwindows; i++) { | |
373 | int off; | |
374 | target_ulong fp = env->regbase[cwp * 16 + 22]; | |
375 | ||
376 | /* Assume fp == 0 means end of frame. */ | |
377 | if (fp == 0) { | |
378 | break; | |
379 | } | |
380 | ||
381 | cwp = cpu_cwp_inc(env, cwp + 1); | |
382 | ||
383 | /* Invalid window ? */ | |
384 | if (env->wim & (1 << cwp)) { | |
385 | break; | |
386 | } | |
387 | ||
388 | /* According to the ABI, the stack is growing downward. */ | |
389 | if (addr + len < fp) { | |
390 | break; | |
391 | } | |
392 | ||
393 | /* Not in this frame. */ | |
394 | if (addr > fp + 64) { | |
395 | continue; | |
396 | } | |
397 | ||
398 | /* Handle access before this window. */ | |
399 | if (addr < fp) { | |
400 | len1 = fp - addr; | |
401 | if (cpu_memory_rw_debug(env, addr, buf, len1, is_write) != 0) { | |
402 | return -1; | |
403 | } | |
404 | addr += len1; | |
405 | len -= len1; | |
406 | buf += len1; | |
407 | } | |
408 | ||
409 | /* Access byte per byte to registers. Not very efficient but speed | |
410 | * is not critical. | |
411 | */ | |
412 | off = addr - fp; | |
413 | len1 = 64 - off; | |
414 | ||
415 | if (len1 > len) { | |
416 | len1 = len; | |
417 | } | |
418 | ||
419 | for (; len1; len1--) { | |
420 | int reg = cwp * 16 + 8 + (off >> 2); | |
421 | union { | |
422 | uint32_t v; | |
423 | uint8_t c[4]; | |
424 | } u; | |
425 | u.v = cpu_to_be32(env->regbase[reg]); | |
426 | *buf++ = u.c[off & 3]; | |
427 | addr++; | |
428 | len--; | |
429 | off++; | |
430 | } | |
431 | ||
432 | if (len == 0) { | |
433 | return 0; | |
434 | } | |
435 | } | |
436 | } | |
437 | return cpu_memory_rw_debug(env, addr, buf, len, is_write); | |
438 | } | |
439 | ||
440 | #else /* !TARGET_SPARC64 */ | |
441 | ||
442 | /* 41 bit physical address space */ | |
443 | static inline target_phys_addr_t ultrasparc_truncate_physical(uint64_t x) | |
444 | { | |
445 | return x & 0x1ffffffffffULL; | |
446 | } | |
447 | ||
448 | /* | |
449 | * UltraSparc IIi I/DMMUs | |
450 | */ | |
451 | ||
452 | /* Returns true if TTE tag is valid and matches virtual address value | |
453 | in context requires virtual address mask value calculated from TTE | |
454 | entry size */ | |
455 | static inline int ultrasparc_tag_match(SparcTLBEntry *tlb, | |
456 | uint64_t address, uint64_t context, | |
457 | target_phys_addr_t *physical) | |
458 | { | |
459 | uint64_t mask; | |
460 | ||
461 | switch (TTE_PGSIZE(tlb->tte)) { | |
462 | default: | |
463 | case 0x0: /* 8k */ | |
464 | mask = 0xffffffffffffe000ULL; | |
465 | break; | |
466 | case 0x1: /* 64k */ | |
467 | mask = 0xffffffffffff0000ULL; | |
468 | break; | |
469 | case 0x2: /* 512k */ | |
470 | mask = 0xfffffffffff80000ULL; | |
471 | break; | |
472 | case 0x3: /* 4M */ | |
473 | mask = 0xffffffffffc00000ULL; | |
474 | break; | |
475 | } | |
476 | ||
477 | /* valid, context match, virtual address match? */ | |
478 | if (TTE_IS_VALID(tlb->tte) && | |
479 | (TTE_IS_GLOBAL(tlb->tte) || tlb_compare_context(tlb, context)) | |
480 | && compare_masked(address, tlb->tag, mask)) { | |
481 | /* decode physical address */ | |
482 | *physical = ((tlb->tte & mask) | (address & ~mask)) & 0x1ffffffe000ULL; | |
483 | return 1; | |
484 | } | |
485 | ||
486 | return 0; | |
487 | } | |
488 | ||
489 | static int get_physical_address_data(CPUState *env, | |
490 | target_phys_addr_t *physical, int *prot, | |
491 | target_ulong address, int rw, int mmu_idx) | |
492 | { | |
493 | unsigned int i; | |
494 | uint64_t context; | |
495 | uint64_t sfsr = 0; | |
496 | ||
497 | int is_user = (mmu_idx == MMU_USER_IDX || | |
498 | mmu_idx == MMU_USER_SECONDARY_IDX); | |
499 | ||
500 | if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */ | |
501 | *physical = ultrasparc_truncate_physical(address); | |
502 | *prot = PAGE_READ | PAGE_WRITE; | |
503 | return 0; | |
504 | } | |
505 | ||
506 | switch (mmu_idx) { | |
507 | case MMU_USER_IDX: | |
508 | case MMU_KERNEL_IDX: | |
509 | context = env->dmmu.mmu_primary_context & 0x1fff; | |
510 | sfsr |= SFSR_CT_PRIMARY; | |
511 | break; | |
512 | case MMU_USER_SECONDARY_IDX: | |
513 | case MMU_KERNEL_SECONDARY_IDX: | |
514 | context = env->dmmu.mmu_secondary_context & 0x1fff; | |
515 | sfsr |= SFSR_CT_SECONDARY; | |
516 | break; | |
517 | case MMU_NUCLEUS_IDX: | |
518 | sfsr |= SFSR_CT_NUCLEUS; | |
519 | /* FALLTHRU */ | |
520 | default: | |
521 | context = 0; | |
522 | break; | |
523 | } | |
524 | ||
525 | if (rw == 1) { | |
526 | sfsr |= SFSR_WRITE_BIT; | |
527 | } else if (rw == 4) { | |
528 | sfsr |= SFSR_NF_BIT; | |
529 | } | |
530 | ||
531 | for (i = 0; i < 64; i++) { | |
532 | /* ctx match, vaddr match, valid? */ | |
533 | if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) { | |
534 | int do_fault = 0; | |
535 | ||
536 | /* access ok? */ | |
537 | /* multiple bits in SFSR.FT may be set on TT_DFAULT */ | |
538 | if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) { | |
539 | do_fault = 1; | |
540 | sfsr |= SFSR_FT_PRIV_BIT; /* privilege violation */ | |
541 | ||
542 | DPRINTF_MMU("DFAULT at %" PRIx64 " context %" PRIx64 | |
543 | " mmu_idx=%d tl=%d\n", | |
544 | address, context, mmu_idx, env->tl); | |
545 | } | |
546 | if (rw == 4) { | |
547 | if (TTE_IS_SIDEEFFECT(env->dtlb[i].tte)) { | |
548 | do_fault = 1; | |
549 | sfsr |= SFSR_FT_NF_E_BIT; | |
550 | } | |
551 | } else { | |
552 | if (TTE_IS_NFO(env->dtlb[i].tte)) { | |
553 | do_fault = 1; | |
554 | sfsr |= SFSR_FT_NFO_BIT; | |
555 | } | |
556 | } | |
557 | ||
558 | if (do_fault) { | |
559 | /* faults above are reported with TT_DFAULT. */ | |
560 | env->exception_index = TT_DFAULT; | |
561 | } else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) { | |
562 | do_fault = 1; | |
563 | env->exception_index = TT_DPROT; | |
564 | ||
565 | DPRINTF_MMU("DPROT at %" PRIx64 " context %" PRIx64 | |
566 | " mmu_idx=%d tl=%d\n", | |
567 | address, context, mmu_idx, env->tl); | |
568 | } | |
569 | ||
570 | if (!do_fault) { | |
571 | *prot = PAGE_READ; | |
572 | if (TTE_IS_W_OK(env->dtlb[i].tte)) { | |
573 | *prot |= PAGE_WRITE; | |
574 | } | |
575 | ||
576 | TTE_SET_USED(env->dtlb[i].tte); | |
577 | ||
578 | return 0; | |
579 | } | |
580 | ||
581 | if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */ | |
582 | sfsr |= SFSR_OW_BIT; /* overflow (not read before | |
583 | another fault) */ | |
584 | } | |
585 | ||
586 | if (env->pstate & PS_PRIV) { | |
587 | sfsr |= SFSR_PR_BIT; | |
588 | } | |
589 | ||
590 | /* FIXME: ASI field in SFSR must be set */ | |
591 | env->dmmu.sfsr = sfsr | SFSR_VALID_BIT; | |
592 | ||
593 | env->dmmu.sfar = address; /* Fault address register */ | |
594 | ||
595 | env->dmmu.tag_access = (address & ~0x1fffULL) | context; | |
596 | ||
597 | return 1; | |
598 | } | |
599 | } | |
600 | ||
601 | DPRINTF_MMU("DMISS at %" PRIx64 " context %" PRIx64 "\n", | |
602 | address, context); | |
603 | ||
604 | /* | |
605 | * On MMU misses: | |
606 | * - UltraSPARC IIi: SFSR and SFAR unmodified | |
607 | * - JPS1: SFAR updated and some fields of SFSR updated | |
608 | */ | |
609 | env->dmmu.tag_access = (address & ~0x1fffULL) | context; | |
610 | env->exception_index = TT_DMISS; | |
611 | return 1; | |
612 | } | |
613 | ||
614 | static int get_physical_address_code(CPUState *env, | |
615 | target_phys_addr_t *physical, int *prot, | |
616 | target_ulong address, int mmu_idx) | |
617 | { | |
618 | unsigned int i; | |
619 | uint64_t context; | |
620 | ||
621 | int is_user = (mmu_idx == MMU_USER_IDX || | |
622 | mmu_idx == MMU_USER_SECONDARY_IDX); | |
623 | ||
624 | if ((env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0) { | |
625 | /* IMMU disabled */ | |
626 | *physical = ultrasparc_truncate_physical(address); | |
627 | *prot = PAGE_EXEC; | |
628 | return 0; | |
629 | } | |
630 | ||
631 | if (env->tl == 0) { | |
632 | /* PRIMARY context */ | |
633 | context = env->dmmu.mmu_primary_context & 0x1fff; | |
634 | } else { | |
635 | /* NUCLEUS context */ | |
636 | context = 0; | |
637 | } | |
638 | ||
639 | for (i = 0; i < 64; i++) { | |
640 | /* ctx match, vaddr match, valid? */ | |
641 | if (ultrasparc_tag_match(&env->itlb[i], | |
642 | address, context, physical)) { | |
643 | /* access ok? */ | |
644 | if (TTE_IS_PRIV(env->itlb[i].tte) && is_user) { | |
645 | /* Fault status register */ | |
646 | if (env->immu.sfsr & SFSR_VALID_BIT) { | |
647 | env->immu.sfsr = SFSR_OW_BIT; /* overflow (not read before | |
648 | another fault) */ | |
649 | } else { | |
650 | env->immu.sfsr = 0; | |
651 | } | |
652 | if (env->pstate & PS_PRIV) { | |
653 | env->immu.sfsr |= SFSR_PR_BIT; | |
654 | } | |
655 | if (env->tl > 0) { | |
656 | env->immu.sfsr |= SFSR_CT_NUCLEUS; | |
657 | } | |
658 | ||
659 | /* FIXME: ASI field in SFSR must be set */ | |
660 | env->immu.sfsr |= SFSR_FT_PRIV_BIT | SFSR_VALID_BIT; | |
661 | env->exception_index = TT_TFAULT; | |
662 | ||
663 | env->immu.tag_access = (address & ~0x1fffULL) | context; | |
664 | ||
665 | DPRINTF_MMU("TFAULT at %" PRIx64 " context %" PRIx64 "\n", | |
666 | address, context); | |
667 | ||
668 | return 1; | |
669 | } | |
670 | *prot = PAGE_EXEC; | |
671 | TTE_SET_USED(env->itlb[i].tte); | |
672 | return 0; | |
673 | } | |
674 | } | |
675 | ||
676 | DPRINTF_MMU("TMISS at %" PRIx64 " context %" PRIx64 "\n", | |
677 | address, context); | |
678 | ||
679 | /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */ | |
680 | env->immu.tag_access = (address & ~0x1fffULL) | context; | |
681 | env->exception_index = TT_TMISS; | |
682 | return 1; | |
683 | } | |
684 | ||
685 | static int get_physical_address(CPUState *env, target_phys_addr_t *physical, | |
686 | int *prot, int *access_index, | |
687 | target_ulong address, int rw, int mmu_idx, | |
688 | target_ulong *page_size) | |
689 | { | |
690 | /* ??? We treat everything as a small page, then explicitly flush | |
691 | everything when an entry is evicted. */ | |
692 | *page_size = TARGET_PAGE_SIZE; | |
693 | ||
694 | #if defined(DEBUG_MMU) | |
695 | /* safety net to catch wrong softmmu index use from dynamic code */ | |
696 | if (env->tl > 0 && mmu_idx != MMU_NUCLEUS_IDX) { | |
697 | DPRINTF_MMU("get_physical_address %s tl=%d mmu_idx=%d" | |
698 | " primary context=%" PRIx64 | |
699 | " secondary context=%" PRIx64 | |
700 | " address=%" PRIx64 | |
701 | "\n", | |
702 | (rw == 2 ? "CODE" : "DATA"), | |
703 | env->tl, mmu_idx, | |
704 | env->dmmu.mmu_primary_context, | |
705 | env->dmmu.mmu_secondary_context, | |
706 | address); | |
707 | } | |
708 | #endif | |
709 | ||
710 | if (rw == 2) { | |
711 | return get_physical_address_code(env, physical, prot, address, | |
712 | mmu_idx); | |
713 | } else { | |
714 | return get_physical_address_data(env, physical, prot, address, rw, | |
715 | mmu_idx); | |
716 | } | |
717 | } | |
718 | ||
719 | /* Perform address translation */ | |
720 | int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw, | |
721 | int mmu_idx) | |
722 | { | |
723 | target_ulong virt_addr, vaddr; | |
724 | target_phys_addr_t paddr; | |
725 | target_ulong page_size; | |
726 | int error_code = 0, prot, access_index; | |
727 | ||
728 | error_code = get_physical_address(env, &paddr, &prot, &access_index, | |
729 | address, rw, mmu_idx, &page_size); | |
730 | if (error_code == 0) { | |
731 | virt_addr = address & TARGET_PAGE_MASK; | |
732 | vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & | |
733 | (TARGET_PAGE_SIZE - 1)); | |
734 | ||
735 | DPRINTF_MMU("Translate at %" PRIx64 " -> %" PRIx64 "," | |
736 | " vaddr %" PRIx64 | |
737 | " mmu_idx=%d" | |
738 | " tl=%d" | |
739 | " primary context=%" PRIx64 | |
740 | " secondary context=%" PRIx64 | |
741 | "\n", | |
742 | address, paddr, vaddr, mmu_idx, env->tl, | |
743 | env->dmmu.mmu_primary_context, | |
744 | env->dmmu.mmu_secondary_context); | |
745 | ||
746 | tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size); | |
747 | return 0; | |
748 | } | |
749 | /* XXX */ | |
750 | return 1; | |
751 | } | |
752 | ||
753 | void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env) | |
754 | { | |
755 | unsigned int i; | |
756 | const char *mask; | |
757 | ||
758 | (*cpu_fprintf)(f, "MMU contexts: Primary: %" PRId64 ", Secondary: %" | |
759 | PRId64 "\n", | |
760 | env->dmmu.mmu_primary_context, | |
761 | env->dmmu.mmu_secondary_context); | |
762 | if ((env->lsu & DMMU_E) == 0) { | |
763 | (*cpu_fprintf)(f, "DMMU disabled\n"); | |
764 | } else { | |
765 | (*cpu_fprintf)(f, "DMMU dump\n"); | |
766 | for (i = 0; i < 64; i++) { | |
767 | switch (TTE_PGSIZE(env->dtlb[i].tte)) { | |
768 | default: | |
769 | case 0x0: | |
770 | mask = " 8k"; | |
771 | break; | |
772 | case 0x1: | |
773 | mask = " 64k"; | |
774 | break; | |
775 | case 0x2: | |
776 | mask = "512k"; | |
777 | break; | |
778 | case 0x3: | |
779 | mask = " 4M"; | |
780 | break; | |
781 | } | |
782 | if (TTE_IS_VALID(env->dtlb[i].tte)) { | |
783 | (*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %llx" | |
784 | ", %s, %s, %s, %s, ctx %" PRId64 " %s\n", | |
785 | i, | |
786 | env->dtlb[i].tag & (uint64_t)~0x1fffULL, | |
787 | TTE_PA(env->dtlb[i].tte), | |
788 | mask, | |
789 | TTE_IS_PRIV(env->dtlb[i].tte) ? "priv" : "user", | |
790 | TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO", | |
791 | TTE_IS_LOCKED(env->dtlb[i].tte) ? | |
792 | "locked" : "unlocked", | |
793 | env->dtlb[i].tag & (uint64_t)0x1fffULL, | |
794 | TTE_IS_GLOBAL(env->dtlb[i].tte) ? | |
795 | "global" : "local"); | |
796 | } | |
797 | } | |
798 | } | |
799 | if ((env->lsu & IMMU_E) == 0) { | |
800 | (*cpu_fprintf)(f, "IMMU disabled\n"); | |
801 | } else { | |
802 | (*cpu_fprintf)(f, "IMMU dump\n"); | |
803 | for (i = 0; i < 64; i++) { | |
804 | switch (TTE_PGSIZE(env->itlb[i].tte)) { | |
805 | default: | |
806 | case 0x0: | |
807 | mask = " 8k"; | |
808 | break; | |
809 | case 0x1: | |
810 | mask = " 64k"; | |
811 | break; | |
812 | case 0x2: | |
813 | mask = "512k"; | |
814 | break; | |
815 | case 0x3: | |
816 | mask = " 4M"; | |
817 | break; | |
818 | } | |
819 | if (TTE_IS_VALID(env->itlb[i].tte)) { | |
820 | (*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %llx" | |
821 | ", %s, %s, %s, ctx %" PRId64 " %s\n", | |
822 | i, | |
823 | env->itlb[i].tag & (uint64_t)~0x1fffULL, | |
824 | TTE_PA(env->itlb[i].tte), | |
825 | mask, | |
826 | TTE_IS_PRIV(env->itlb[i].tte) ? "priv" : "user", | |
827 | TTE_IS_LOCKED(env->itlb[i].tte) ? | |
828 | "locked" : "unlocked", | |
829 | env->itlb[i].tag & (uint64_t)0x1fffULL, | |
830 | TTE_IS_GLOBAL(env->itlb[i].tte) ? | |
831 | "global" : "local"); | |
832 | } | |
833 | } | |
834 | } | |
835 | } | |
836 | ||
837 | #endif /* TARGET_SPARC64 */ | |
838 | ||
839 | static int cpu_sparc_get_phys_page(CPUState *env, target_phys_addr_t *phys, | |
840 | target_ulong addr, int rw, int mmu_idx) | |
841 | { | |
842 | target_ulong page_size; | |
843 | int prot, access_index; | |
844 | ||
845 | return get_physical_address(env, phys, &prot, &access_index, addr, rw, | |
846 | mmu_idx, &page_size); | |
847 | } | |
848 | ||
849 | #if defined(TARGET_SPARC64) | |
850 | target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr, | |
851 | int mmu_idx) | |
852 | { | |
853 | target_phys_addr_t phys_addr; | |
854 | ||
855 | if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 4, mmu_idx) != 0) { | |
856 | return -1; | |
857 | } | |
858 | return phys_addr; | |
859 | } | |
860 | #endif | |
861 | ||
862 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) | |
863 | { | |
864 | target_phys_addr_t phys_addr; | |
865 | int mmu_idx = cpu_mmu_index(env); | |
866 | ||
867 | if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 2, mmu_idx) != 0) { | |
868 | if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != 0) { | |
869 | return -1; | |
870 | } | |
871 | } | |
872 | if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED) { | |
873 | return -1; | |
874 | } | |
875 | return phys_addr; | |
876 | } | |
877 | #endif |