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prep: Remove bogus BIOS size check
[qemu.git] / target-sparc / op_helper.c
CommitLineData
e8af50a3 1#include "exec.h"
eed152bb 2#include "host-utils.h"
1a2fb1c0 3#include "helper.h"
b04d9890 4#include "sysemu.h"
e8af50a3 5
e80cfcfc 6//#define DEBUG_MMU
952a328f 7//#define DEBUG_MXCC
94554550 8//#define DEBUG_UNALIGNED
6c36d3fa 9//#define DEBUG_UNASSIGNED
8543e2cf 10//#define DEBUG_ASI
d81fd722 11//#define DEBUG_PCALL
7e8695ed 12//#define DEBUG_PSTATE
b04d9890 13//#define DEBUG_CACHE_CONTROL
e80cfcfc 14
952a328f 15#ifdef DEBUG_MMU
001faf32
BS		 16#define DPRINTF_MMU(fmt, ...) \
17 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
952a328f 18#else
001faf32 19#define DPRINTF_MMU(fmt, ...) do {} while (0)
952a328f
BS		 20#endif
21
22#ifdef DEBUG_MXCC
001faf32
BS		 23#define DPRINTF_MXCC(fmt, ...) \
24 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
952a328f 25#else
001faf32 26#define DPRINTF_MXCC(fmt, ...) do {} while (0)
952a328f
BS		 27#endif
28
8543e2cf 29#ifdef DEBUG_ASI
001faf32
BS		 30#define DPRINTF_ASI(fmt, ...) \
31 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
8543e2cf
BS		 32#endif
33
7e8695ed
IK		 34#ifdef DEBUG_PSTATE
35#define DPRINTF_PSTATE(fmt, ...) \
36 do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
37#else
38#define DPRINTF_PSTATE(fmt, ...) do {} while (0)
39#endif
40
b04d9890
FC		 41#ifdef DEBUG_CACHE_CONTROL
42#define DPRINTF_CACHE_CONTROL(fmt, ...) \
43 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
44#else
45#define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
46#endif
47
2cade6a3
BS		 48#ifdef TARGET_SPARC64
49#ifndef TARGET_ABI32
50#define AM_CHECK(env1) ((env1)->pstate & PS_AM)
c2bc0e38 51#else
2cade6a3
BS		 52#define AM_CHECK(env1) (1)
53#endif
c2bc0e38
BS		 54#endif
55
21ffd181
BS		 56#define DT0 (env->dt0)
57#define DT1 (env->dt1)
58#define QT0 (env->qt0)
59#define QT1 (env->qt1)
60
b04d9890
FC		 61/* Leon3 cache control */
62
63/* Cache control: emulate the behavior of cache control registers but without
64 any effect on the emulated */
65
66#define CACHE_STATE_MASK 0x3
67#define CACHE_DISABLED 0x0
68#define CACHE_FROZEN 0x1
69#define CACHE_ENABLED 0x3
70
71/* Cache Control register fields */
72
73#define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */
74#define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */
75#define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */
76#define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */
77#define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */
78#define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */
79#define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */
80#define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */
81
3c7b48b7
PB		 82#if defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
83static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
84 int is_asi, int size);
85#endif
86
9c22a623 87#if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
697a77e6
IK		 88// Calculates TSB pointer value for fault page size 8k or 64k
89static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
90 uint64_t tag_access_register,
91 int page_size)
92{
93 uint64_t tsb_base = tsb_register & ~0x1fffULL;
6e8e7d4c
IK		 94 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
95 int tsb_size = tsb_register & 0xf;
697a77e6
IK		 96
97 // discard lower 13 bits which hold tag access context
98 uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
99
100 // now reorder bits
101 uint64_t tsb_base_mask = ~0x1fffULL;
102 uint64_t va = tag_access_va;
103
104 // move va bits to correct position
105 if (page_size == 8*1024) {
106 va >>= 9;
107 } else if (page_size == 64*1024) {
108 va >>= 12;
109 }
110
111 if (tsb_size) {
112 tsb_base_mask <<= tsb_size;
113 }
114
115 // calculate tsb_base mask and adjust va if split is in use
116 if (tsb_split) {
117 if (page_size == 8*1024) {
118 va &= ~(1ULL << (13 + tsb_size));
119 } else if (page_size == 64*1024) {
120 va |= (1ULL << (13 + tsb_size));
121 }
122 tsb_base_mask <<= 1;
123 }
124
125 return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
126}
127
128// Calculates tag target register value by reordering bits
129// in tag access register
130static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
131{
132 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
133}
134
f707726e
IK		 135static void replace_tlb_entry(SparcTLBEntry *tlb,
136 uint64_t tlb_tag, uint64_t tlb_tte,
137 CPUState *env1)
6e8e7d4c
IK		 138{
139 target_ulong mask, size, va, offset;
140
141 // flush page range if translation is valid
f707726e 142 if (TTE_IS_VALID(tlb->tte)) {
6e8e7d4c
IK		 143
144 mask = 0xffffffffffffe000ULL;
145 mask <<= 3 * ((tlb->tte >> 61) & 3);
146 size = ~mask + 1;
147
148 va = tlb->tag & mask;
149
150 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
151 tlb_flush_page(env1, va + offset);
152 }
153 }
154
155 tlb->tag = tlb_tag;
156 tlb->tte = tlb_tte;
157}
158
159static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
f707726e 160 const char* strmmu, CPUState *env1)
6e8e7d4c
IK		 161{
162 unsigned int i;
163 target_ulong mask;
299b520c
IK		 164 uint64_t context;
165
166 int is_demap_context = (demap_addr >> 6) & 1;
167
168 // demap context
169 switch ((demap_addr >> 4) & 3) {
170 case 0: // primary
171 context = env1->dmmu.mmu_primary_context;
172 break;
173 case 1: // secondary
174 context = env1->dmmu.mmu_secondary_context;
175 break;
176 case 2: // nucleus
177 context = 0;
178 break;
179 case 3: // reserved
180 default:
181 return;
182 }
6e8e7d4c
IK		 183
184 for (i = 0; i < 64; i++) {
f707726e 185 if (TTE_IS_VALID(tlb[i].tte)) {
6e8e7d4c 186
299b520c
IK		 187 if (is_demap_context) {
188 // will remove non-global entries matching context value
189 if (TTE_IS_GLOBAL(tlb[i].tte) ||
190 !tlb_compare_context(&tlb[i], context)) {
191 continue;
192 }
193 } else {
194 // demap page
195 // will remove any entry matching VA
196 mask = 0xffffffffffffe000ULL;
197 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
198
199 if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
200 continue;
201 }
202
203 // entry should be global or matching context value
204 if (!TTE_IS_GLOBAL(tlb[i].tte) &&
205 !tlb_compare_context(&tlb[i], context)) {
206 continue;
207 }
208 }
6e8e7d4c 209
299b520c 210 replace_tlb_entry(&tlb[i], 0, 0, env1);
6e8e7d4c 211#ifdef DEBUG_MMU
299b520c 212 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
d41160a3 213 dump_mmu(stdout, fprintf, env1);
6e8e7d4c 214#endif
6e8e7d4c
IK		 215 }
216 }
6e8e7d4c
IK		 217}
218
f707726e
IK		 219static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
220 uint64_t tlb_tag, uint64_t tlb_tte,
221 const char* strmmu, CPUState *env1)
222{
223 unsigned int i, replace_used;
224
225 // Try replacing invalid entry
226 for (i = 0; i < 64; i++) {
227 if (!TTE_IS_VALID(tlb[i].tte)) {
228 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
229#ifdef DEBUG_MMU
230 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
d41160a3 231 dump_mmu(stdout, fprintf, env1);
f707726e
IK		 232#endif
233 return;
234 }
235 }
236
237 // All entries are valid, try replacing unlocked entry
238
239 for (replace_used = 0; replace_used < 2; ++replace_used) {
240
241 // Used entries are not replaced on first pass
242
243 for (i = 0; i < 64; i++) {
244 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
245
246 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
247#ifdef DEBUG_MMU
248 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
249 strmmu, (replace_used?"used":"unused"), i);
d41160a3 250 dump_mmu(stdout, fprintf, env1);
f707726e
IK		 251#endif
252 return;
253 }
254 }
255
256 // Now reset used bit and search for unused entries again
257
258 for (i = 0; i < 64; i++) {
259 TTE_SET_UNUSED(tlb[i].tte);
260 }
261 }
262
263#ifdef DEBUG_MMU
264 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
265#endif
266 // error state?
267}
268
697a77e6
IK		 269#endif
270
41db525e 271static inline target_ulong address_mask(CPUState *env1, target_ulong addr)
2cade6a3
BS		 272{
273#ifdef TARGET_SPARC64
274 if (AM_CHECK(env1))
41db525e 275 addr &= 0xffffffffULL;
2cade6a3 276#endif
41db525e 277 return addr;
2cade6a3
BS		 278}
279
1295001c
IK		 280/* returns true if access using this ASI is to have address translated by MMU
281 otherwise access is to raw physical address */
282static inline int is_translating_asi(int asi)
283{
284#ifdef TARGET_SPARC64
285 /* Ultrasparc IIi translating asi
286 - note this list is defined by cpu implementation
287 */
288 switch (asi) {
289 case 0x04 ... 0x11:
290 case 0x18 ... 0x19:
291 case 0x24 ... 0x2C:
292 case 0x70 ... 0x73:
293 case 0x78 ... 0x79:
294 case 0x80 ... 0xFF:
295 return 1;
296
297 default:
298 return 0;
299 }
300#else
301 /* TODO: check sparc32 bits */
302 return 0;
303#endif
304}
305
306static inline target_ulong asi_address_mask(CPUState *env1,
307 int asi, target_ulong addr)
308{
309 if (is_translating_asi(asi)) {
310 return address_mask(env, addr);
311 } else {
312 return addr;
313 }
314}
315
f4a5a5ba 316static void raise_exception(int tt)
9d893301
FB		 317{
318 env->exception_index = tt;
319 cpu_loop_exit();
3b46e624 320}
9d893301 321
a7812ae4
PB		 322void HELPER(raise_exception)(int tt)
323{
324 raise_exception(tt);
325}
326
b04d9890
FC		 327void helper_shutdown(void)
328{
329#if !defined(CONFIG_USER_ONLY)
330 qemu_system_shutdown_request();
331#endif
332}
333
2b29924f
BS		 334void helper_check_align(target_ulong addr, uint32_t align)
335{
c2bc0e38
BS		 336 if (addr & align) {
337#ifdef DEBUG_UNALIGNED
338 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
339 "\n", addr, env->pc);
340#endif
2b29924f 341 raise_exception(TT_UNALIGNED);
c2bc0e38 342 }
2b29924f
BS		 343}
344
44e7757c
BS		 345#define F_HELPER(name, p) void helper_f##name##p(void)
346
44e7757c 347#define F_BINOP(name) \
714547bb 348 float32 helper_f ## name ## s (float32 src1, float32 src2) \
44e7757c 349 { \
714547bb 350 return float32_ ## name (src1, src2, &env->fp_status); \
44e7757c
BS		 351 } \
352 F_HELPER(name, d) \
353 { \
354 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
4e14008f
BS		 355 } \
356 F_HELPER(name, q) \
357 { \
358 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
44e7757c 359 }
44e7757c
BS		 360
361F_BINOP(add);
362F_BINOP(sub);
363F_BINOP(mul);
364F_BINOP(div);
365#undef F_BINOP
366
d84763bc 367void helper_fsmuld(float32 src1, float32 src2)
1a2fb1c0 368{
d84763bc
BS		 369 DT0 = float64_mul(float32_to_float64(src1, &env->fp_status),
370 float32_to_float64(src2, &env->fp_status),
44e7757c
BS		 371 &env->fp_status);
372}
1a2fb1c0 373
4e14008f
BS		 374void helper_fdmulq(void)
375{
376 QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
377 float64_to_float128(DT1, &env->fp_status),
378 &env->fp_status);
379}
4e14008f 380
714547bb 381float32 helper_fnegs(float32 src)
44e7757c 382{
714547bb 383 return float32_chs(src);
417454b0
BS		 384}
385
44e7757c
BS		 386#ifdef TARGET_SPARC64
387F_HELPER(neg, d)
7e8c2b6c 388{
44e7757c 389 DT0 = float64_chs(DT1);
7e8c2b6c 390}
4e14008f 391
4e14008f
BS		 392F_HELPER(neg, q)
393{
394 QT0 = float128_chs(QT1);
395}
396#endif
44e7757c
BS		 397
398/* Integer to float conversion. */
714547bb 399float32 helper_fitos(int32_t src)
a0c4cb4a 400{
714547bb 401 return int32_to_float32(src, &env->fp_status);
a0c4cb4a
FB		 402}
403
d84763bc 404void helper_fitod(int32_t src)
a0c4cb4a 405{
d84763bc 406 DT0 = int32_to_float64(src, &env->fp_status);
a0c4cb4a 407}
9c2b428e 408
c5d04e99 409void helper_fitoq(int32_t src)
4e14008f 410{
c5d04e99 411 QT0 = int32_to_float128(src, &env->fp_status);
4e14008f 412}
4e14008f 413
1e64e78d 414#ifdef TARGET_SPARC64
d84763bc 415float32 helper_fxtos(void)
1e64e78d 416{
d84763bc 417 return int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
1e64e78d
BS		 418}
419
44e7757c 420F_HELPER(xto, d)
1e64e78d 421{
1e64e78d 422 DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
1e64e78d 423}
64a88d5d 424
4e14008f
BS		 425F_HELPER(xto, q)
426{
427 QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
428}
429#endif
44e7757c
BS		 430#undef F_HELPER
431
432/* floating point conversion */
d84763bc 433float32 helper_fdtos(void)
44e7757c 434{
d84763bc 435 return float64_to_float32(DT1, &env->fp_status);
44e7757c
BS		 436}
437
d84763bc 438void helper_fstod(float32 src)
44e7757c 439{
d84763bc 440 DT0 = float32_to_float64(src, &env->fp_status);
44e7757c 441}
9c2b428e 442
c5d04e99 443float32 helper_fqtos(void)
4e14008f 444{
c5d04e99 445 return float128_to_float32(QT1, &env->fp_status);
4e14008f
BS		 446}
447
c5d04e99 448void helper_fstoq(float32 src)
4e14008f 449{
c5d04e99 450 QT0 = float32_to_float128(src, &env->fp_status);
4e14008f
BS		 451}
452
453void helper_fqtod(void)
454{
455 DT0 = float128_to_float64(QT1, &env->fp_status);
456}
457
458void helper_fdtoq(void)
459{
460 QT0 = float64_to_float128(DT1, &env->fp_status);
461}
4e14008f 462
44e7757c 463/* Float to integer conversion. */
714547bb 464int32_t helper_fstoi(float32 src)
44e7757c 465{
714547bb 466 return float32_to_int32_round_to_zero(src, &env->fp_status);
44e7757c
BS		 467}
468
d84763bc 469int32_t helper_fdtoi(void)
44e7757c 470{
d84763bc 471 return float64_to_int32_round_to_zero(DT1, &env->fp_status);
44e7757c
BS		 472}
473
c5d04e99 474int32_t helper_fqtoi(void)
4e14008f 475{
c5d04e99 476 return float128_to_int32_round_to_zero(QT1, &env->fp_status);
4e14008f 477}
4e14008f 478
44e7757c 479#ifdef TARGET_SPARC64
d84763bc 480void helper_fstox(float32 src)
44e7757c 481{
d84763bc 482 *((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status);
44e7757c
BS		 483}
484
485void helper_fdtox(void)
486{
487 *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
488}
489
4e14008f
BS		 490void helper_fqtox(void)
491{
492 *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);
493}
4e14008f 494
44e7757c
BS		 495void helper_faligndata(void)
496{
497 uint64_t tmp;
498
499 tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
06057e6f
BS		 500 /* on many architectures a shift of 64 does nothing */
501 if ((env->gsr & 7) != 0) {
502 tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
503 }
44e7757c
BS		 504 *((uint64_t *)&DT0) = tmp;
505}
506
e2542fe2 507#ifdef HOST_WORDS_BIGENDIAN
44e7757c
BS		 508#define VIS_B64(n) b[7 - (n)]
509#define VIS_W64(n) w[3 - (n)]
510#define VIS_SW64(n) sw[3 - (n)]
511#define VIS_L64(n) l[1 - (n)]
512#define VIS_B32(n) b[3 - (n)]
513#define VIS_W32(n) w[1 - (n)]
514#else
515#define VIS_B64(n) b[n]
516#define VIS_W64(n) w[n]
517#define VIS_SW64(n) sw[n]
518#define VIS_L64(n) l[n]
519#define VIS_B32(n) b[n]
520#define VIS_W32(n) w[n]
521#endif
522
523typedef union {
524 uint8_t b[8];
525 uint16_t w[4];
526 int16_t sw[4];
527 uint32_t l[2];
528 float64 d;
529} vis64;
530
531typedef union {
532 uint8_t b[4];
533 uint16_t w[2];
534 uint32_t l;
535 float32 f;
536} vis32;
537
538void helper_fpmerge(void)
539{
540 vis64 s, d;
541
542 s.d = DT0;
543 d.d = DT1;
544
545 // Reverse calculation order to handle overlap
546 d.VIS_B64(7) = s.VIS_B64(3);
547 d.VIS_B64(6) = d.VIS_B64(3);
548 d.VIS_B64(5) = s.VIS_B64(2);
549 d.VIS_B64(4) = d.VIS_B64(2);
550 d.VIS_B64(3) = s.VIS_B64(1);
551 d.VIS_B64(2) = d.VIS_B64(1);
552 d.VIS_B64(1) = s.VIS_B64(0);
553 //d.VIS_B64(0) = d.VIS_B64(0);
554
555 DT0 = d.d;
556}
557
558void helper_fmul8x16(void)
559{
560 vis64 s, d;
561 uint32_t tmp;
562
563 s.d = DT0;
564 d.d = DT1;
565
566#define PMUL(r) \
567 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
568 if ((tmp & 0xff) > 0x7f) \
569 tmp += 0x100; \
570 d.VIS_W64(r) = tmp >> 8;
571
572 PMUL(0);
573 PMUL(1);
574 PMUL(2);
575 PMUL(3);
576#undef PMUL
577
578 DT0 = d.d;
579}
580
581void helper_fmul8x16al(void)
582{
583 vis64 s, d;
584 uint32_t tmp;
585
586 s.d = DT0;
587 d.d = DT1;
588
589#define PMUL(r) \
590 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
591 if ((tmp & 0xff) > 0x7f) \
592 tmp += 0x100; \
593 d.VIS_W64(r) = tmp >> 8;
594
595 PMUL(0);
596 PMUL(1);
597 PMUL(2);
598 PMUL(3);
599#undef PMUL
600
601 DT0 = d.d;
602}
603
604void helper_fmul8x16au(void)
605{
606 vis64 s, d;
607 uint32_t tmp;
608
609 s.d = DT0;
610 d.d = DT1;
611
612#define PMUL(r) \
613 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
614 if ((tmp & 0xff) > 0x7f) \
615 tmp += 0x100; \
616 d.VIS_W64(r) = tmp >> 8;
617
618 PMUL(0);
619 PMUL(1);
620 PMUL(2);
621 PMUL(3);
622#undef PMUL
623
624 DT0 = d.d;
625}
626
627void helper_fmul8sux16(void)
628{
629 vis64 s, d;
630 uint32_t tmp;
631
632 s.d = DT0;
633 d.d = DT1;
634
635#define PMUL(r) \
636 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
637 if ((tmp & 0xff) > 0x7f) \
638 tmp += 0x100; \
639 d.VIS_W64(r) = tmp >> 8;
640
641 PMUL(0);
642 PMUL(1);
643 PMUL(2);
644 PMUL(3);
645#undef PMUL
646
647 DT0 = d.d;
648}
649
650void helper_fmul8ulx16(void)
651{
652 vis64 s, d;
653 uint32_t tmp;
654
655 s.d = DT0;
656 d.d = DT1;
657
658#define PMUL(r) \
659 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
660 if ((tmp & 0xff) > 0x7f) \
661 tmp += 0x100; \
662 d.VIS_W64(r) = tmp >> 8;
663
664 PMUL(0);
665 PMUL(1);
666 PMUL(2);
667 PMUL(3);
668#undef PMUL
669
670 DT0 = d.d;
671}
672
673void helper_fmuld8sux16(void)
674{
675 vis64 s, d;
676 uint32_t tmp;
677
678 s.d = DT0;
679 d.d = DT1;
680
681#define PMUL(r) \
682 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
683 if ((tmp & 0xff) > 0x7f) \
684 tmp += 0x100; \
685 d.VIS_L64(r) = tmp;
686
687 // Reverse calculation order to handle overlap
688 PMUL(1);
689 PMUL(0);
690#undef PMUL
691
692 DT0 = d.d;
693}
694
695void helper_fmuld8ulx16(void)
696{
697 vis64 s, d;
698 uint32_t tmp;
699
700 s.d = DT0;
701 d.d = DT1;
702
703#define PMUL(r) \
704 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
705 if ((tmp & 0xff) > 0x7f) \
706 tmp += 0x100; \
707 d.VIS_L64(r) = tmp;
708
709 // Reverse calculation order to handle overlap
710 PMUL(1);
711 PMUL(0);
712#undef PMUL
713
714 DT0 = d.d;
715}
716
717void helper_fexpand(void)
718{
719 vis32 s;
720 vis64 d;
721
722 s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
723 d.d = DT1;
c55bda30
BS		 724 d.VIS_W64(0) = s.VIS_B32(0) << 4;
725 d.VIS_W64(1) = s.VIS_B32(1) << 4;
726 d.VIS_W64(2) = s.VIS_B32(2) << 4;
727 d.VIS_W64(3) = s.VIS_B32(3) << 4;
44e7757c
BS		 728
729 DT0 = d.d;
730}
731
732#define VIS_HELPER(name, F) \
733 void name##16(void) \
734 { \
735 vis64 s, d; \
736 \
737 s.d = DT0; \
738 d.d = DT1; \
739 \
740 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
741 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
742 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
743 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
744 \
745 DT0 = d.d; \
746 } \
747 \
1d01299d 748 uint32_t name##16s(uint32_t src1, uint32_t src2) \
44e7757c
BS		 749 { \
750 vis32 s, d; \
751 \
1d01299d
BS		 752 s.l = src1; \
753 d.l = src2; \
44e7757c
BS		 754 \
755 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
756 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
757 \
1d01299d 758 return d.l; \
44e7757c
BS		 759 } \
760 \
761 void name##32(void) \
762 { \
763 vis64 s, d; \
764 \
765 s.d = DT0; \
766 d.d = DT1; \
767 \
768 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
769 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
770 \
771 DT0 = d.d; \
772 } \
773 \
1d01299d 774 uint32_t name##32s(uint32_t src1, uint32_t src2) \
44e7757c
BS		 775 { \
776 vis32 s, d; \
777 \
1d01299d
BS		 778 s.l = src1; \
779 d.l = src2; \
44e7757c
BS		 780 \
781 d.l = F(d.l, s.l); \
782 \
1d01299d 783 return d.l; \
44e7757c
BS		 784 }
785
786#define FADD(a, b) ((a) + (b))
787#define FSUB(a, b) ((a) - (b))
788VIS_HELPER(helper_fpadd, FADD)
789VIS_HELPER(helper_fpsub, FSUB)
790
791#define VIS_CMPHELPER(name, F) \
792 void name##16(void) \
793 { \
794 vis64 s, d; \
795 \
796 s.d = DT0; \
797 d.d = DT1; \
798 \
799 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
800 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
801 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
802 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
803 \
804 DT0 = d.d; \
805 } \
806 \
807 void name##32(void) \
808 { \
809 vis64 s, d; \
810 \
811 s.d = DT0; \
812 d.d = DT1; \
813 \
814 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
815 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
816 \
817 DT0 = d.d; \
818 }
819
820#define FCMPGT(a, b) ((a) > (b))
821#define FCMPEQ(a, b) ((a) == (b))
822#define FCMPLE(a, b) ((a) <= (b))
823#define FCMPNE(a, b) ((a) != (b))
824
825VIS_CMPHELPER(helper_fcmpgt, FCMPGT)
826VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)
827VIS_CMPHELPER(helper_fcmple, FCMPLE)
828VIS_CMPHELPER(helper_fcmpne, FCMPNE)
829#endif
830
831void helper_check_ieee_exceptions(void)
832{
833 target_ulong status;
834
835 status = get_float_exception_flags(&env->fp_status);
836 if (status) {
837 /* Copy IEEE 754 flags into FSR */
838 if (status & float_flag_invalid)
839 env->fsr |= FSR_NVC;
840 if (status & float_flag_overflow)
841 env->fsr |= FSR_OFC;
842 if (status & float_flag_underflow)
843 env->fsr |= FSR_UFC;
844 if (status & float_flag_divbyzero)
845 env->fsr |= FSR_DZC;
846 if (status & float_flag_inexact)
847 env->fsr |= FSR_NXC;
848
849 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
850 /* Unmasked exception, generate a trap */
851 env->fsr |= FSR_FTT_IEEE_EXCP;
852 raise_exception(TT_FP_EXCP);
853 } else {
854 /* Accumulate exceptions */
855 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
856 }
857 }
858}
859
860void helper_clear_float_exceptions(void)
861{
862 set_float_exception_flags(0, &env->fp_status);
863}
864
714547bb 865float32 helper_fabss(float32 src)
e8af50a3 866{
714547bb 867 return float32_abs(src);
e8af50a3
FB		 868}
869
3475187d 870#ifdef TARGET_SPARC64
7e8c2b6c 871void helper_fabsd(void)
3475187d
FB		 872{
873 DT0 = float64_abs(DT1);
874}
4e14008f 875
4e14008f
BS		 876void helper_fabsq(void)
877{
878 QT0 = float128_abs(QT1);
879}
880#endif
3475187d 881
714547bb 882float32 helper_fsqrts(float32 src)
e8af50a3 883{
714547bb 884 return float32_sqrt(src, &env->fp_status);
e8af50a3
FB		 885}
886
7e8c2b6c 887void helper_fsqrtd(void)
e8af50a3 888{
7a0e1f41 889 DT0 = float64_sqrt(DT1, &env->fp_status);
e8af50a3
FB		 890}
891
4e14008f
BS		 892void helper_fsqrtq(void)
893{
894 QT0 = float128_sqrt(QT1, &env->fp_status);
895}
4e14008f 896
1b5f56b1 897#define GEN_FCMP(name, size, reg1, reg2, FS, E) \
7e8c2b6c 898 void glue(helper_, name) (void) \
65ce8c2f 899 { \
1b5f56b1
BS		 900 env->fsr &= FSR_FTT_NMASK; \
901 if (E && (glue(size, _is_any_nan)(reg1) || \
902 glue(size, _is_any_nan)(reg2)) && \
903 (env->fsr & FSR_NVM)) { \
904 env->fsr |= FSR_NVC; \
905 env->fsr |= FSR_FTT_IEEE_EXCP; \
906 raise_exception(TT_FP_EXCP); \
907 } \
65ce8c2f
FB		 908 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
909 case float_relation_unordered: \
1b5f56b1 910 if ((env->fsr & FSR_NVM)) { \
417454b0
BS		 911 env->fsr |= FSR_NVC; \
912 env->fsr |= FSR_FTT_IEEE_EXCP; \
65ce8c2f
FB		 913 raise_exception(TT_FP_EXCP); \
914 } else { \
1b5f56b1
BS		 915 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
916 env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
65ce8c2f
FB		 917 env->fsr |= FSR_NVA; \
918 } \
919 break; \
920 case float_relation_less: \
1b5f56b1
BS		 921 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
922 env->fsr |= FSR_FCC0 << FS; \
65ce8c2f
FB		 923 break; \
924 case float_relation_greater: \
1b5f56b1
BS		 925 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
926 env->fsr |= FSR_FCC1 << FS; \
65ce8c2f
FB		 927 break; \
928 default: \
1b5f56b1 929 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
65ce8c2f
FB		 930 break; \
931 } \
e8af50a3 932 }
1b5f56b1 933#define GEN_FCMPS(name, size, FS, E) \
714547bb
BS		 934 void glue(helper_, name)(float32 src1, float32 src2) \
935 { \
1b5f56b1
BS		 936 env->fsr &= FSR_FTT_NMASK; \
937 if (E && (glue(size, _is_any_nan)(src1) || \
938 glue(size, _is_any_nan)(src2)) && \
939 (env->fsr & FSR_NVM)) { \
940 env->fsr |= FSR_NVC; \
941 env->fsr |= FSR_FTT_IEEE_EXCP; \
942 raise_exception(TT_FP_EXCP); \
943 } \
714547bb
BS		 944 switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
945 case float_relation_unordered: \
1b5f56b1 946 if ((env->fsr & FSR_NVM)) { \
714547bb
BS		 947 env->fsr |= FSR_NVC; \
948 env->fsr |= FSR_FTT_IEEE_EXCP; \
949 raise_exception(TT_FP_EXCP); \
950 } else { \
1b5f56b1
BS		 951 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
952 env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
714547bb
BS		 953 env->fsr |= FSR_NVA; \
954 } \
955 break; \
956 case float_relation_less: \
1b5f56b1
BS		 957 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
958 env->fsr |= FSR_FCC0 << FS; \
714547bb
BS		 959 break; \
960 case float_relation_greater: \
1b5f56b1
BS		 961 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
962 env->fsr |= FSR_FCC1 << FS; \
714547bb
BS		 963 break; \
964 default: \
1b5f56b1 965 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
714547bb
BS		 966 break; \
967 } \
714547bb 968 }
e8af50a3 969
714547bb 970GEN_FCMPS(fcmps, float32, 0, 0);
417454b0
BS		 971GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
972
714547bb 973GEN_FCMPS(fcmpes, float32, 0, 1);
417454b0 974GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
3475187d 975
4e14008f
BS		 976GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
977GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
4e14008f 978
8393617c
BS		 979static uint32_t compute_all_flags(void)
980{
981 return env->psr & PSR_ICC;
982}
983
984static uint32_t compute_C_flags(void)
985{
986 return env->psr & PSR_CARRY;
987}
988
5a4bb580 989static inline uint32_t get_NZ_icc(int32_t dst)
bdf9f35d
BS		 990{
991 uint32_t ret = 0;
992
5a4bb580
RH		 993 if (dst == 0) {
994 ret = PSR_ZERO;
995 } else if (dst < 0) {
996 ret = PSR_NEG;
997 }
bdf9f35d
BS		 998 return ret;
999}
1000
8393617c
BS		 1001#ifdef TARGET_SPARC64
1002static uint32_t compute_all_flags_xcc(void)
1003{
1004 return env->xcc & PSR_ICC;
1005}
1006
1007static uint32_t compute_C_flags_xcc(void)
1008{
1009 return env->xcc & PSR_CARRY;
1010}
1011
5a4bb580 1012static inline uint32_t get_NZ_xcc(target_long dst)
bdf9f35d
BS		 1013{
1014 uint32_t ret = 0;
1015
5a4bb580
RH		 1016 if (!dst) {
1017 ret = PSR_ZERO;
1018 } else if (dst < 0) {
1019 ret = PSR_NEG;
1020 }
bdf9f35d
BS		 1021 return ret;
1022}
1023#endif
1024
6c78ea32
BS		 1025static inline uint32_t get_V_div_icc(target_ulong src2)
1026{
1027 uint32_t ret = 0;
1028
5a4bb580
RH		 1029 if (src2 != 0) {
1030 ret = PSR_OVF;
1031 }
6c78ea32
BS		 1032 return ret;
1033}
1034
1035static uint32_t compute_all_div(void)
1036{
1037 uint32_t ret;
1038
1039 ret = get_NZ_icc(CC_DST);
1040 ret |= get_V_div_icc(CC_SRC2);
1041 return ret;
1042}
1043
1044static uint32_t compute_C_div(void)
1045{
1046 return 0;
1047}
1048
5a4bb580 1049static inline uint32_t get_C_add_icc(uint32_t dst, uint32_t src1)
bdf9f35d
BS		 1050{
1051 uint32_t ret = 0;
1052
5a4bb580
RH		 1053 if (dst < src1) {
1054 ret = PSR_CARRY;
1055 }
bdf9f35d
BS		 1056 return ret;
1057}
1058
5a4bb580
RH		 1059static inline uint32_t get_C_addx_icc(uint32_t dst, uint32_t src1,
1060 uint32_t src2)
bdf9f35d
BS		 1061{
1062 uint32_t ret = 0;
1063
5a4bb580
RH		 1064 if (((src1 & src2) | (~dst & (src1 | src2))) & (1U << 31)) {
1065 ret = PSR_CARRY;
1066 }
1067 return ret;
1068}
1069
1070static inline uint32_t get_V_add_icc(uint32_t dst, uint32_t src1,
1071 uint32_t src2)
1072{
1073 uint32_t ret = 0;
1074
1075 if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1U << 31)) {
1076 ret = PSR_OVF;
1077 }
bdf9f35d
BS		 1078 return ret;
1079}
1080
bdf9f35d
BS		 1081#ifdef TARGET_SPARC64
1082static inline uint32_t get_C_add_xcc(target_ulong dst, target_ulong src1)
1083{
1084 uint32_t ret = 0;
1085
5a4bb580
RH		 1086 if (dst < src1) {
1087 ret = PSR_CARRY;
1088 }
1089 return ret;
1090}
1091
1092static inline uint32_t get_C_addx_xcc(target_ulong dst, target_ulong src1,
1093 target_ulong src2)
1094{
1095 uint32_t ret = 0;
1096
1097 if (((src1 & src2) | (~dst & (src1 | src2))) & (1ULL << 63)) {
1098 ret = PSR_CARRY;
1099 }
bdf9f35d
BS		 1100 return ret;
1101}
1102
1103static inline uint32_t get_V_add_xcc(target_ulong dst, target_ulong src1,
1104 target_ulong src2)
1105{
1106 uint32_t ret = 0;
1107
5a4bb580
RH		 1108 if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1ULL << 63)) {
1109 ret = PSR_OVF;
1110 }
bdf9f35d
BS		 1111 return ret;
1112}
1113
1114static uint32_t compute_all_add_xcc(void)
1115{
1116 uint32_t ret;
1117
1118 ret = get_NZ_xcc(CC_DST);
1119 ret |= get_C_add_xcc(CC_DST, CC_SRC);
1120 ret |= get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2);
1121 return ret;
1122}
1123
1124static uint32_t compute_C_add_xcc(void)
1125{
1126 return get_C_add_xcc(CC_DST, CC_SRC);
1127}
8393617c
BS		 1128#endif
1129
3e6ba503 1130static uint32_t compute_all_add(void)
789c91ef
BS		 1131{
1132 uint32_t ret;
1133
1134 ret = get_NZ_icc(CC_DST);
5a4bb580 1135 ret |= get_C_add_icc(CC_DST, CC_SRC);
789c91ef
BS		 1136 ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2);
1137 return ret;
1138}
1139
3e6ba503 1140static uint32_t compute_C_add(void)
789c91ef 1141{
5a4bb580 1142 return get_C_add_icc(CC_DST, CC_SRC);
789c91ef
BS		 1143}
1144
1145#ifdef TARGET_SPARC64
1146static uint32_t compute_all_addx_xcc(void)
1147{
1148 uint32_t ret;
1149
1150 ret = get_NZ_xcc(CC_DST);
5a4bb580 1151 ret |= get_C_addx_xcc(CC_DST, CC_SRC, CC_SRC2);
789c91ef
BS		 1152 ret |= get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2);
1153 return ret;
1154}
1155
1156static uint32_t compute_C_addx_xcc(void)
1157{
1158 uint32_t ret;
1159
5a4bb580 1160 ret = get_C_addx_xcc(CC_DST, CC_SRC, CC_SRC2);
789c91ef
BS		 1161 return ret;
1162}
1163#endif
1164
5a4bb580
RH		 1165static uint32_t compute_all_addx(void)
1166{
1167 uint32_t ret;
1168
1169 ret = get_NZ_icc(CC_DST);
1170 ret |= get_C_addx_icc(CC_DST, CC_SRC, CC_SRC2);
1171 ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2);
1172 return ret;
1173}
1174
1175static uint32_t compute_C_addx(void)
1176{
1177 uint32_t ret;
1178
1179 ret = get_C_addx_icc(CC_DST, CC_SRC, CC_SRC2);
1180 return ret;
1181}
1182
3b2d1e92
BS		 1183static inline uint32_t get_V_tag_icc(target_ulong src1, target_ulong src2)
1184{
1185 uint32_t ret = 0;
1186
5a4bb580
RH		 1187 if ((src1 | src2) & 0x3) {
1188 ret = PSR_OVF;
1189 }
3b2d1e92
BS		 1190 return ret;
1191}
1192
1193static uint32_t compute_all_tadd(void)
1194{
1195 uint32_t ret;
1196
1197 ret = get_NZ_icc(CC_DST);
5a4bb580 1198 ret |= get_C_add_icc(CC_DST, CC_SRC);
3b2d1e92
BS		 1199 ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2);
1200 ret |= get_V_tag_icc(CC_SRC, CC_SRC2);
1201 return ret;
1202}
1203
3b2d1e92
BS		 1204static uint32_t compute_all_taddtv(void)
1205{
1206 uint32_t ret;
1207
1208 ret = get_NZ_icc(CC_DST);
5a4bb580 1209 ret |= get_C_add_icc(CC_DST, CC_SRC);
3b2d1e92
BS		 1210 return ret;
1211}
1212
5a4bb580 1213static inline uint32_t get_C_sub_icc(uint32_t src1, uint32_t src2)
3b2d1e92 1214{
5a4bb580
RH		 1215 uint32_t ret = 0;
1216
1217 if (src1 < src2) {
1218 ret = PSR_CARRY;
1219 }
1220 return ret;
3b2d1e92
BS		 1221}
1222
5a4bb580
RH		 1223static inline uint32_t get_C_subx_icc(uint32_t dst, uint32_t src1,
1224 uint32_t src2)
d4b0d468
BS		 1225{
1226 uint32_t ret = 0;
1227
5a4bb580
RH		 1228 if (((~src1 & src2) | (dst & (~src1 | src2))) & (1U << 31)) {
1229 ret = PSR_CARRY;
1230 }
d4b0d468
BS		 1231 return ret;
1232}
1233
5a4bb580
RH		 1234static inline uint32_t get_V_sub_icc(uint32_t dst, uint32_t src1,
1235 uint32_t src2)
d4b0d468
BS		 1236{
1237 uint32_t ret = 0;
1238
5a4bb580
RH		 1239 if (((src1 ^ src2) & (src1 ^ dst)) & (1U << 31)) {
1240 ret = PSR_OVF;
1241 }
d4b0d468
BS		 1242 return ret;
1243}
1244
d4b0d468
BS		 1245
1246#ifdef TARGET_SPARC64
1247static inline uint32_t get_C_sub_xcc(target_ulong src1, target_ulong src2)
1248{
1249 uint32_t ret = 0;
1250
5a4bb580
RH		 1251 if (src1 < src2) {
1252 ret = PSR_CARRY;
1253 }
1254 return ret;
1255}
1256
1257static inline uint32_t get_C_subx_xcc(target_ulong dst, target_ulong src1,
1258 target_ulong src2)
1259{
1260 uint32_t ret = 0;
1261
1262 if (((~src1 & src2) | (dst & (~src1 | src2))) & (1ULL << 63)) {
1263 ret = PSR_CARRY;
1264 }
d4b0d468
BS		 1265 return ret;
1266}
1267
1268static inline uint32_t get_V_sub_xcc(target_ulong dst, target_ulong src1,
1269 target_ulong src2)
1270{
1271 uint32_t ret = 0;
1272
5a4bb580
RH		 1273 if (((src1 ^ src2) & (src1 ^ dst)) & (1ULL << 63)) {
1274 ret = PSR_OVF;
1275 }
d4b0d468
BS		 1276 return ret;
1277}
1278
1279static uint32_t compute_all_sub_xcc(void)
1280{
1281 uint32_t ret;
1282
1283 ret = get_NZ_xcc(CC_DST);
1284 ret |= get_C_sub_xcc(CC_SRC, CC_SRC2);
1285 ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2);
1286 return ret;
1287}
1288
1289static uint32_t compute_C_sub_xcc(void)
1290{
1291 return get_C_sub_xcc(CC_SRC, CC_SRC2);
1292}
1293#endif
1294
3e6ba503 1295static uint32_t compute_all_sub(void)
2ca1d92b
BS		 1296{
1297 uint32_t ret;
1298
1299 ret = get_NZ_icc(CC_DST);
5a4bb580 1300 ret |= get_C_sub_icc(CC_SRC, CC_SRC2);
2ca1d92b
BS		 1301 ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2);
1302 return ret;
1303}
1304
3e6ba503 1305static uint32_t compute_C_sub(void)
2ca1d92b 1306{
5a4bb580 1307 return get_C_sub_icc(CC_SRC, CC_SRC2);
2ca1d92b
BS		 1308}
1309
1310#ifdef TARGET_SPARC64
1311static uint32_t compute_all_subx_xcc(void)
1312{
1313 uint32_t ret;
1314
1315 ret = get_NZ_xcc(CC_DST);
5a4bb580 1316 ret |= get_C_subx_xcc(CC_DST, CC_SRC, CC_SRC2);
2ca1d92b
BS		 1317 ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2);
1318 return ret;
1319}
1320
1321static uint32_t compute_C_subx_xcc(void)
1322{
1323 uint32_t ret;
1324
5a4bb580 1325 ret = get_C_subx_xcc(CC_DST, CC_SRC, CC_SRC2);
2ca1d92b
BS		 1326 return ret;
1327}
1328#endif
1329
5a4bb580 1330static uint32_t compute_all_subx(void)
3b2d1e92
BS		 1331{
1332 uint32_t ret;
1333
1334 ret = get_NZ_icc(CC_DST);
5a4bb580 1335 ret |= get_C_subx_icc(CC_DST, CC_SRC, CC_SRC2);
3b2d1e92 1336 ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2);
3b2d1e92
BS		 1337 return ret;
1338}
1339
5a4bb580 1340static uint32_t compute_C_subx(void)
3b2d1e92 1341{
5a4bb580
RH		 1342 uint32_t ret;
1343
1344 ret = get_C_subx_icc(CC_DST, CC_SRC, CC_SRC2);
1345 return ret;
3b2d1e92
BS		 1346}
1347
5a4bb580 1348static uint32_t compute_all_tsub(void)
3b2d1e92
BS		 1349{
1350 uint32_t ret;
1351
1352 ret = get_NZ_icc(CC_DST);
5a4bb580
RH		 1353 ret |= get_C_sub_icc(CC_SRC, CC_SRC2);
1354 ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2);
1355 ret |= get_V_tag_icc(CC_SRC, CC_SRC2);
3b2d1e92
BS		 1356 return ret;
1357}
1358
5a4bb580 1359static uint32_t compute_all_tsubtv(void)
3b2d1e92 1360{
5a4bb580
RH		 1361 uint32_t ret;
1362
1363 ret = get_NZ_icc(CC_DST);
1364 ret |= get_C_sub_icc(CC_SRC, CC_SRC2);
1365 return ret;
3b2d1e92
BS		 1366}
1367
38482a77
BS		 1368static uint32_t compute_all_logic(void)
1369{
1370 return get_NZ_icc(CC_DST);
1371}
1372
1373static uint32_t compute_C_logic(void)
1374{
1375 return 0;
1376}
1377
1378#ifdef TARGET_SPARC64
1379static uint32_t compute_all_logic_xcc(void)
1380{
1381 return get_NZ_xcc(CC_DST);
1382}
1383#endif
1384
8393617c
BS		 1385typedef struct CCTable {
1386 uint32_t (*compute_all)(void); /* return all the flags */
1387 uint32_t (*compute_c)(void); /* return the C flag */
1388} CCTable;
1389
1390static const CCTable icc_table[CC_OP_NB] = {
1391 /* CC_OP_DYNAMIC should never happen */
1392 [CC_OP_FLAGS] = { compute_all_flags, compute_C_flags },
6c78ea32 1393 [CC_OP_DIV] = { compute_all_div, compute_C_div },
bdf9f35d 1394 [CC_OP_ADD] = { compute_all_add, compute_C_add },
5a4bb580
RH		 1395 [CC_OP_ADDX] = { compute_all_addx, compute_C_addx },
1396 [CC_OP_TADD] = { compute_all_tadd, compute_C_add },
1397 [CC_OP_TADDTV] = { compute_all_taddtv, compute_C_add },
d4b0d468 1398 [CC_OP_SUB] = { compute_all_sub, compute_C_sub },
5a4bb580
RH		 1399 [CC_OP_SUBX] = { compute_all_subx, compute_C_subx },
1400 [CC_OP_TSUB] = { compute_all_tsub, compute_C_sub },
1401 [CC_OP_TSUBTV] = { compute_all_tsubtv, compute_C_sub },
38482a77 1402 [CC_OP_LOGIC] = { compute_all_logic, compute_C_logic },
8393617c
BS		 1403};
1404
1405#ifdef TARGET_SPARC64
1406static const CCTable xcc_table[CC_OP_NB] = {
1407 /* CC_OP_DYNAMIC should never happen */
1408 [CC_OP_FLAGS] = { compute_all_flags_xcc, compute_C_flags_xcc },
6c78ea32 1409 [CC_OP_DIV] = { compute_all_logic_xcc, compute_C_logic },
bdf9f35d 1410 [CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc },
789c91ef 1411 [CC_OP_ADDX] = { compute_all_addx_xcc, compute_C_addx_xcc },
3b2d1e92
BS		 1412 [CC_OP_TADD] = { compute_all_add_xcc, compute_C_add_xcc },
1413 [CC_OP_TADDTV] = { compute_all_add_xcc, compute_C_add_xcc },
d4b0d468 1414 [CC_OP_SUB] = { compute_all_sub_xcc, compute_C_sub_xcc },
2ca1d92b 1415 [CC_OP_SUBX] = { compute_all_subx_xcc, compute_C_subx_xcc },
3b2d1e92
BS		 1416 [CC_OP_TSUB] = { compute_all_sub_xcc, compute_C_sub_xcc },
1417 [CC_OP_TSUBTV] = { compute_all_sub_xcc, compute_C_sub_xcc },
38482a77 1418 [CC_OP_LOGIC] = { compute_all_logic_xcc, compute_C_logic },
8393617c
BS		 1419};
1420#endif
1421
1422void helper_compute_psr(void)
1423{
1424 uint32_t new_psr;
1425
1426 new_psr = icc_table[CC_OP].compute_all();
1427 env->psr = new_psr;
1428#ifdef TARGET_SPARC64
1429 new_psr = xcc_table[CC_OP].compute_all();
1430 env->xcc = new_psr;
1431#endif
1432 CC_OP = CC_OP_FLAGS;
1433}
1434
70c48285 1435uint32_t helper_compute_C_icc(void)
8393617c
BS		 1436{
1437 uint32_t ret;
1438
1439 ret = icc_table[CC_OP].compute_c() >> PSR_CARRY_SHIFT;
1440 return ret;
1441}
1442
5a834bb4
BS		 1443static inline void memcpy32(target_ulong *dst, const target_ulong *src)
1444{
1445 dst[0] = src[0];
1446 dst[1] = src[1];
1447 dst[2] = src[2];
1448 dst[3] = src[3];
1449 dst[4] = src[4];
1450 dst[5] = src[5];
1451 dst[6] = src[6];
1452 dst[7] = src[7];
1453}
1454
1455static void set_cwp(int new_cwp)
1456{
1457 /* put the modified wrap registers at their proper location */
1458 if (env->cwp == env->nwindows - 1) {
1459 memcpy32(env->regbase, env->regbase + env->nwindows * 16);
1460 }
1461 env->cwp = new_cwp;
1462
1463 /* put the wrap registers at their temporary location */
1464 if (new_cwp == env->nwindows - 1) {
1465 memcpy32(env->regbase + env->nwindows * 16, env->regbase);
1466 }
1467 env->regwptr = env->regbase + (new_cwp * 16);
1468}
1469
1470void cpu_set_cwp(CPUState *env1, int new_cwp)
1471{
1472 CPUState *saved_env;
1473
1474 saved_env = env;
1475 env = env1;
1476 set_cwp(new_cwp);
1477 env = saved_env;
1478}
1479
1480static target_ulong get_psr(void)
1481{
1482 helper_compute_psr();
1483
1484#if !defined (TARGET_SPARC64)
1485 return env->version | (env->psr & PSR_ICC) |
1486 (env->psref? PSR_EF : 0) |
1487 (env->psrpil << 8) |
1488 (env->psrs? PSR_S : 0) |
1489 (env->psrps? PSR_PS : 0) |
1490 (env->psret? PSR_ET : 0) | env->cwp;
1491#else
2aae2b8e 1492 return env->psr & PSR_ICC;
5a834bb4
BS		 1493#endif
1494}
1495
1496target_ulong cpu_get_psr(CPUState *env1)
1497{
1498 CPUState *saved_env;
1499 target_ulong ret;
1500
1501 saved_env = env;
1502 env = env1;
1503 ret = get_psr();
1504 env = saved_env;
1505 return ret;
1506}
1507
1508static void put_psr(target_ulong val)
1509{
1510 env->psr = val & PSR_ICC;
2aae2b8e 1511#if !defined (TARGET_SPARC64)
5a834bb4
BS		 1512 env->psref = (val & PSR_EF)? 1 : 0;
1513 env->psrpil = (val & PSR_PIL) >> 8;
2aae2b8e 1514#endif
5a834bb4
BS		 1515#if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
1516 cpu_check_irqs(env);
1517#endif
2aae2b8e 1518#if !defined (TARGET_SPARC64)
5a834bb4
BS		 1519 env->psrs = (val & PSR_S)? 1 : 0;
1520 env->psrps = (val & PSR_PS)? 1 : 0;
5a834bb4 1521 env->psret = (val & PSR_ET)? 1 : 0;
5a834bb4 1522 set_cwp(val & PSR_CWP);
2aae2b8e 1523#endif
5a834bb4
BS		 1524 env->cc_op = CC_OP_FLAGS;
1525}
1526
1527void cpu_put_psr(CPUState *env1, target_ulong val)
1528{
1529 CPUState *saved_env;
1530
1531 saved_env = env;
1532 env = env1;
1533 put_psr(val);
1534 env = saved_env;
1535}
1536
1537static int cwp_inc(int cwp)
1538{
1539 if (unlikely(cwp >= env->nwindows)) {
1540 cwp -= env->nwindows;
1541 }
1542 return cwp;
1543}
1544
1545int cpu_cwp_inc(CPUState *env1, int cwp)
1546{
1547 CPUState *saved_env;
1548 target_ulong ret;
1549
1550 saved_env = env;
1551 env = env1;
1552 ret = cwp_inc(cwp);
1553 env = saved_env;
1554 return ret;
1555}
1556
1557static int cwp_dec(int cwp)
1558{
1559 if (unlikely(cwp < 0)) {
1560 cwp += env->nwindows;
1561 }
1562 return cwp;
1563}
1564
1565int cpu_cwp_dec(CPUState *env1, int cwp)
1566{
1567 CPUState *saved_env;
1568 target_ulong ret;
1569
1570 saved_env = env;
1571 env = env1;
1572 ret = cwp_dec(cwp);
1573 env = saved_env;
1574 return ret;
1575}
1576
3475187d 1577#ifdef TARGET_SPARC64
714547bb 1578GEN_FCMPS(fcmps_fcc1, float32, 22, 0);
417454b0 1579GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
64a88d5d 1580GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
417454b0 1581
714547bb 1582GEN_FCMPS(fcmps_fcc2, float32, 24, 0);
417454b0 1583GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
64a88d5d 1584GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
417454b0 1585
714547bb 1586GEN_FCMPS(fcmps_fcc3, float32, 26, 0);
417454b0 1587GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
64a88d5d 1588GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
417454b0 1589
714547bb 1590GEN_FCMPS(fcmpes_fcc1, float32, 22, 1);
417454b0 1591GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
64a88d5d 1592GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
3475187d 1593
714547bb 1594GEN_FCMPS(fcmpes_fcc2, float32, 24, 1);
417454b0 1595GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
64a88d5d 1596GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
3475187d 1597
714547bb 1598GEN_FCMPS(fcmpes_fcc3, float32, 26, 1);
417454b0 1599GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
4e14008f
BS		 1600GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
1601#endif
714547bb 1602#undef GEN_FCMPS
3475187d 1603
77f193da
BS		 1604#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
1605 defined(DEBUG_MXCC)
952a328f
BS		 1606static void dump_mxcc(CPUState *env)
1607{
0bf9e31a
BS		 1608 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
1609 "\n",
77f193da
BS		 1610 env->mxccdata[0], env->mxccdata[1],
1611 env->mxccdata[2], env->mxccdata[3]);
0bf9e31a
BS		 1612 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
1613 "\n"
1614 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
1615 "\n",
77f193da
BS		 1616 env->mxccregs[0], env->mxccregs[1],
1617 env->mxccregs[2], env->mxccregs[3],
1618 env->mxccregs[4], env->mxccregs[5],
1619 env->mxccregs[6], env->mxccregs[7]);
952a328f
BS		 1620}
1621#endif
1622
1a2fb1c0
BS		 1623#if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
1624 && defined(DEBUG_ASI)
1625static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
1626 uint64_t r1)
8543e2cf
BS		 1627{
1628 switch (size)
1629 {
1630 case 1:
1a2fb1c0
BS		 1631 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
1632 addr, asi, r1 & 0xff);
8543e2cf
BS		 1633 break;
1634 case 2:
1a2fb1c0
BS		 1635 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
1636 addr, asi, r1 & 0xffff);
8543e2cf
BS		 1637 break;
1638 case 4:
1a2fb1c0
BS		 1639 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
1640 addr, asi, r1 & 0xffffffff);
8543e2cf
BS		 1641 break;
1642 case 8:
1a2fb1c0
BS		 1643 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
1644 addr, asi, r1);
8543e2cf
BS		 1645 break;
1646 }
1647}
1648#endif
1649
1a2fb1c0
BS		 1650#ifndef TARGET_SPARC64
1651#ifndef CONFIG_USER_ONLY
b04d9890
FC		 1652
1653
1654/* Leon3 cache control */
1655
1656void leon3_cache_control_int(void)
1657{
1658 uint32_t state = 0;
1659
1660 if (env->cache_control & CACHE_CTRL_IF) {
1661 /* Instruction cache state */
1662 state = env->cache_control & CACHE_STATE_MASK;
1663 if (state == CACHE_ENABLED) {
1664 state = CACHE_FROZEN;
1665 DPRINTF_CACHE_CONTROL("Instruction cache: freeze\n");
1666 }
1667
1668 env->cache_control &= ~CACHE_STATE_MASK;
1669 env->cache_control |= state;
1670 }
1671
1672 if (env->cache_control & CACHE_CTRL_DF) {
1673 /* Data cache state */
1674 state = (env->cache_control >> 2) & CACHE_STATE_MASK;
1675 if (state == CACHE_ENABLED) {
1676 state = CACHE_FROZEN;
1677 DPRINTF_CACHE_CONTROL("Data cache: freeze\n");
1678 }
1679
1680 env->cache_control &= ~(CACHE_STATE_MASK << 2);
1681 env->cache_control |= (state << 2);
1682 }
1683}
1684
1685static void leon3_cache_control_st(target_ulong addr, uint64_t val, int size)
1686{
1687 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
1688 addr, val, size);
1689
1690 if (size != 4) {
1691 DPRINTF_CACHE_CONTROL("32bits only\n");
1692 return;
1693 }
1694
1695 switch (addr) {
1696 case 0x00: /* Cache control */
1697
1698 /* These values must always be read as zeros */
1699 val &= ~CACHE_CTRL_FD;
1700 val &= ~CACHE_CTRL_FI;
1701 val &= ~CACHE_CTRL_IB;
1702 val &= ~CACHE_CTRL_IP;
1703 val &= ~CACHE_CTRL_DP;
1704
1705 env->cache_control = val;
1706 break;
1707 case 0x04: /* Instruction cache configuration */
1708 case 0x08: /* Data cache configuration */
1709 /* Read Only */
1710 break;
1711 default:
1712 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
1713 break;
1714 };
1715}
1716
1717static uint64_t leon3_cache_control_ld(target_ulong addr, int size)
1718{
1719 uint64_t ret = 0;
1720
1721 if (size != 4) {
1722 DPRINTF_CACHE_CONTROL("32bits only\n");
1723 return 0;
1724 }
1725
1726 switch (addr) {
1727 case 0x00: /* Cache control */
1728 ret = env->cache_control;
1729 break;
1730
1731 /* Configuration registers are read and only always keep those
1732 predefined values */
1733
1734 case 0x04: /* Instruction cache configuration */
1735 ret = 0x10220000;
1736 break;
1737 case 0x08: /* Data cache configuration */
1738 ret = 0x18220000;
1739 break;
1740 default:
1741 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
1742 break;
1743 };
1744 DPRINTF_CACHE_CONTROL("st addr:%08x, ret:%" PRIx64 ", size:%d\n",
1745 addr, ret, size);
1746 return ret;
1747}
1748
1a2fb1c0 1749uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
e8af50a3 1750{
1a2fb1c0 1751 uint64_t ret = 0;
8543e2cf 1752#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
1a2fb1c0 1753 uint32_t last_addr = addr;
952a328f 1754#endif
e80cfcfc 1755
c2bc0e38 1756 helper_check_align(addr, size - 1);
e80cfcfc 1757 switch (asi) {
b04d9890 1758 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
1a2fb1c0 1759 switch (addr) {
b04d9890
FC		 1760 case 0x00: /* Leon3 Cache Control */
1761 case 0x08: /* Leon3 Instruction Cache config */
1762 case 0x0C: /* Leon3 Date Cache config */
1763 ret = leon3_cache_control_ld(addr, size);
1764 break;
952a328f 1765 case 0x01c00a00: /* MXCC control register */
1a2fb1c0
BS		 1766 if (size == 8)
1767 ret = env->mxccregs[3];
1768 else
77f193da
BS		 1769 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1770 size);
952a328f
BS		 1771 break;
1772 case 0x01c00a04: /* MXCC control register */
1773 if (size == 4)
1774 ret = env->mxccregs[3];
1775 else
77f193da
BS		 1776 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1777 size);
952a328f 1778 break;
295db113
BS		 1779 case 0x01c00c00: /* Module reset register */
1780 if (size == 8) {
1a2fb1c0 1781 ret = env->mxccregs[5];
295db113
BS		 1782 // should we do something here?
1783 } else
77f193da
BS		 1784 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1785 size);
295db113 1786 break;
952a328f 1787 case 0x01c00f00: /* MBus port address register */
1a2fb1c0
BS		 1788 if (size == 8)
1789 ret = env->mxccregs[7];
1790 else
77f193da
BS		 1791 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1792 size);
952a328f
BS		 1793 break;
1794 default:
77f193da
BS		 1795 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
1796 size);
952a328f
BS		 1797 break;
1798 }
77f193da 1799 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
9827e450 1800 "addr = %08x -> ret = %" PRIx64 ","
1a2fb1c0 1801 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
952a328f
BS		 1802#ifdef DEBUG_MXCC
1803 dump_mxcc(env);
1804#endif
6c36d3fa 1805 break;
e8af50a3 1806 case 3: /* MMU probe */
0f8a249a
BS		 1807 {
1808 int mmulev;
1809
1a2fb1c0 1810 mmulev = (addr >> 8) & 15;
0f8a249a
BS		 1811 if (mmulev > 4)
1812 ret = 0;
1a2fb1c0
BS		 1813 else
1814 ret = mmu_probe(env, addr, mmulev);
1815 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
1816 addr, mmulev, ret);
0f8a249a
BS		 1817 }
1818 break;
e8af50a3 1819 case 4: /* read MMU regs */
0f8a249a 1820 {
1a2fb1c0 1821 int reg = (addr >> 8) & 0x1f;
3b46e624 1822
0f8a249a
BS		 1823 ret = env->mmuregs[reg];
1824 if (reg == 3) /* Fault status cleared on read */
3dd9a152
BS		 1825 env->mmuregs[3] = 0;
1826 else if (reg == 0x13) /* Fault status read */
1827 ret = env->mmuregs[3];
1828 else if (reg == 0x14) /* Fault address read */
1829 ret = env->mmuregs[4];
1a2fb1c0 1830 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
0f8a249a
BS		 1831 }
1832 break;
045380be
BS		 1833 case 5: // Turbosparc ITLB Diagnostic
1834 case 6: // Turbosparc DTLB Diagnostic
1835 case 7: // Turbosparc IOTLB Diagnostic
1836 break;
6c36d3fa
BS		 1837 case 9: /* Supervisor code access */
1838 switch(size) {
1839 case 1:
1a2fb1c0 1840 ret = ldub_code(addr);
6c36d3fa
BS		 1841 break;
1842 case 2:
a4e7dd52 1843 ret = lduw_code(addr);
6c36d3fa
BS		 1844 break;
1845 default:
1846 case 4:
a4e7dd52 1847 ret = ldl_code(addr);
6c36d3fa
BS		 1848 break;
1849 case 8:
a4e7dd52 1850 ret = ldq_code(addr);
6c36d3fa
BS		 1851 break;
1852 }
1853 break;
81ad8ba2
BS		 1854 case 0xa: /* User data access */
1855 switch(size) {
1856 case 1:
1a2fb1c0 1857 ret = ldub_user(addr);
81ad8ba2
BS		 1858 break;
1859 case 2:
a4e7dd52 1860 ret = lduw_user(addr);
81ad8ba2
BS		 1861 break;
1862 default:
1863 case 4:
a4e7dd52 1864 ret = ldl_user(addr);
81ad8ba2
BS		 1865 break;
1866 case 8:
a4e7dd52 1867 ret = ldq_user(addr);
81ad8ba2
BS		 1868 break;
1869 }
1870 break;
1871 case 0xb: /* Supervisor data access */
1872 switch(size) {
1873 case 1:
1a2fb1c0 1874 ret = ldub_kernel(addr);
81ad8ba2
BS		 1875 break;
1876 case 2:
a4e7dd52 1877 ret = lduw_kernel(addr);
81ad8ba2
BS		 1878 break;
1879 default:
1880 case 4:
a4e7dd52 1881 ret = ldl_kernel(addr);
81ad8ba2
BS		 1882 break;
1883 case 8:
a4e7dd52 1884 ret = ldq_kernel(addr);
81ad8ba2
BS		 1885 break;
1886 }
1887 break;
6c36d3fa
BS		 1888 case 0xc: /* I-cache tag */
1889 case 0xd: /* I-cache data */
1890 case 0xe: /* D-cache tag */
1891 case 0xf: /* D-cache data */
1892 break;
1893 case 0x20: /* MMU passthrough */
02aab46a
FB		 1894 switch(size) {
1895 case 1:
1a2fb1c0 1896 ret = ldub_phys(addr);
02aab46a
FB		 1897 break;
1898 case 2:
a4e7dd52 1899 ret = lduw_phys(addr);
02aab46a
FB		 1900 break;
1901 default:
1902 case 4:
a4e7dd52 1903 ret = ldl_phys(addr);
02aab46a 1904 break;
9e61bde5 1905 case 8:
a4e7dd52 1906 ret = ldq_phys(addr);
0f8a249a 1907 break;
02aab46a 1908 }
0f8a249a 1909 break;
7d85892b 1910 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
5dcb6b91
BS		 1911 switch(size) {
1912 case 1:
c227f099
AL		 1913 ret = ldub_phys((target_phys_addr_t)addr
1914 | ((target_phys_addr_t)(asi & 0xf) << 32));
5dcb6b91
BS		 1915 break;
1916 case 2:
c227f099
AL		 1917 ret = lduw_phys((target_phys_addr_t)addr
1918 | ((target_phys_addr_t)(asi & 0xf) << 32));
5dcb6b91
BS		 1919 break;
1920 default:
1921 case 4:
c227f099
AL		 1922 ret = ldl_phys((target_phys_addr_t)addr
1923 | ((target_phys_addr_t)(asi & 0xf) << 32));
5dcb6b91
BS		 1924 break;
1925 case 8:
c227f099
AL		 1926 ret = ldq_phys((target_phys_addr_t)addr
1927 | ((target_phys_addr_t)(asi & 0xf) << 32));
0f8a249a 1928 break;
5dcb6b91 1929 }
0f8a249a 1930 break;
045380be
BS		 1931 case 0x30: // Turbosparc secondary cache diagnostic
1932 case 0x31: // Turbosparc RAM snoop
1933 case 0x32: // Turbosparc page table descriptor diagnostic
666c87aa 1934 case 0x39: /* data cache diagnostic register */
da7ed379 1935 case 0x4c: /* SuperSPARC MMU Breakpoint Action register */
666c87aa
BS		 1936 ret = 0;
1937 break;
4017190e
BS		 1938 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
1939 {
1940 int reg = (addr >> 8) & 3;
1941
1942 switch(reg) {
1943 case 0: /* Breakpoint Value (Addr) */
1944 ret = env->mmubpregs[reg];
1945 break;
1946 case 1: /* Breakpoint Mask */
1947 ret = env->mmubpregs[reg];
1948 break;
1949 case 2: /* Breakpoint Control */
1950 ret = env->mmubpregs[reg];
1951 break;
1952 case 3: /* Breakpoint Status */
1953 ret = env->mmubpregs[reg];
1954 env->mmubpregs[reg] = 0ULL;
1955 break;
1956 }
0bf9e31a
BS		 1957 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
1958 ret);
4017190e
BS		 1959 }
1960 break;
045380be 1961 case 8: /* User code access, XXX */
e8af50a3 1962 default:
e18231a3 1963 do_unassigned_access(addr, 0, 0, asi, size);
0f8a249a
BS		 1964 ret = 0;
1965 break;
e8af50a3 1966 }
81ad8ba2
BS		 1967 if (sign) {
1968 switch(size) {
1969 case 1:
1a2fb1c0 1970 ret = (int8_t) ret;
e32664fb 1971 break;
81ad8ba2 1972 case 2:
1a2fb1c0
BS		 1973 ret = (int16_t) ret;
1974 break;
1975 case 4:
1976 ret = (int32_t) ret;
e32664fb 1977 break;
81ad8ba2 1978 default:
81ad8ba2
BS		 1979 break;
1980 }
1981 }
8543e2cf 1982#ifdef DEBUG_ASI
1a2fb1c0 1983 dump_asi("read ", last_addr, asi, size, ret);
8543e2cf 1984#endif
1a2fb1c0 1985 return ret;
e8af50a3
FB		 1986}
1987
1a2fb1c0 1988void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
e8af50a3 1989{
c2bc0e38 1990 helper_check_align(addr, size - 1);
e8af50a3 1991 switch(asi) {
b04d9890 1992 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
1a2fb1c0 1993 switch (addr) {
b04d9890
FC		 1994 case 0x00: /* Leon3 Cache Control */
1995 case 0x08: /* Leon3 Instruction Cache config */
1996 case 0x0C: /* Leon3 Date Cache config */
1997 leon3_cache_control_st(addr, val, size);
1998 break;
1999
952a328f
BS		 2000 case 0x01c00000: /* MXCC stream data register 0 */
2001 if (size == 8)
1a2fb1c0 2002 env->mxccdata[0] = val;
952a328f 2003 else
77f193da
BS		 2004 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
2005 size);
952a328f
BS		 2006 break;
2007 case 0x01c00008: /* MXCC stream data register 1 */
2008 if (size == 8)
1a2fb1c0 2009 env->mxccdata[1] = val;
952a328f 2010 else
77f193da
BS		 2011 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
2012 size);
952a328f
BS		 2013 break;
2014 case 0x01c00010: /* MXCC stream data register 2 */
2015 if (size == 8)
1a2fb1c0 2016 env->mxccdata[2] = val;
952a328f 2017 else
77f193da
BS		 2018 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
2019 size);
952a328f
BS		 2020 break;
2021 case 0x01c00018: /* MXCC stream data register 3 */
2022 if (size == 8)
1a2fb1c0 2023 env->mxccdata[3] = val;
952a328f 2024 else
77f193da
BS		 2025 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
2026 size);
952a328f
BS		 2027 break;
2028 case 0x01c00100: /* MXCC stream source */
2029 if (size == 8)
1a2fb1c0 2030 env->mxccregs[0] = val;
952a328f 2031 else
77f193da
BS		 2032 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
2033 size);
2034 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
2035 0);
2036 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
2037 8);
2038 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
2039 16);
2040 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
2041 24);
952a328f
BS		 2042 break;
2043 case 0x01c00200: /* MXCC stream destination */
2044 if (size == 8)
1a2fb1c0 2045 env->mxccregs[1] = val;
952a328f 2046 else
77f193da
BS		 2047 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
2048 size);
2049 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0,
2050 env->mxccdata[0]);
2051 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8,
2052 env->mxccdata[1]);
2053 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
2054 env->mxccdata[2]);
2055 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
2056 env->mxccdata[3]);
952a328f
BS		 2057 break;
2058 case 0x01c00a00: /* MXCC control register */
2059 if (size == 8)
1a2fb1c0 2060 env->mxccregs[3] = val;
952a328f 2061 else
77f193da
BS		 2062 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
2063 size);
952a328f
BS		 2064 break;
2065 case 0x01c00a04: /* MXCC control register */
2066 if (size == 4)
9f4576f0 2067 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
77f193da 2068 | val;
952a328f 2069 else
77f193da
BS		 2070 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
2071 size);
952a328f
BS		 2072 break;
2073 case 0x01c00e00: /* MXCC error register */
bbf7d96b 2074 // writing a 1 bit clears the error
952a328f 2075 if (size == 8)
1a2fb1c0 2076 env->mxccregs[6] &= ~val;
952a328f 2077 else
77f193da
BS		 2078 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
2079 size);
952a328f
BS		 2080 break;
2081 case 0x01c00f00: /* MBus port address register */
2082 if (size == 8)
1a2fb1c0 2083 env->mxccregs[7] = val;
952a328f 2084 else
77f193da
BS		 2085 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
2086 size);
952a328f
BS		 2087 break;
2088 default:
77f193da
BS		 2089 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
2090 size);
952a328f
BS		 2091 break;
2092 }
9827e450
BS		 2093 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
2094 asi, size, addr, val);
952a328f
BS		 2095#ifdef DEBUG_MXCC
2096 dump_mxcc(env);
2097#endif
6c36d3fa 2098 break;
e8af50a3 2099 case 3: /* MMU flush */
0f8a249a
BS		 2100 {
2101 int mmulev;
e80cfcfc 2102
1a2fb1c0 2103 mmulev = (addr >> 8) & 15;
952a328f 2104 DPRINTF_MMU("mmu flush level %d\n", mmulev);
0f8a249a
BS		 2105 switch (mmulev) {
2106 case 0: // flush page
1a2fb1c0 2107 tlb_flush_page(env, addr & 0xfffff000);
0f8a249a
BS		 2108 break;
2109 case 1: // flush segment (256k)
2110 case 2: // flush region (16M)
2111 case 3: // flush context (4G)
2112 case 4: // flush entire
2113 tlb_flush(env, 1);
2114 break;
2115 default:
2116 break;
2117 }
55754d9e 2118#ifdef DEBUG_MMU
d41160a3 2119 dump_mmu(stdout, fprintf, env);
55754d9e 2120#endif
0f8a249a 2121 }
8543e2cf 2122 break;
e8af50a3 2123 case 4: /* write MMU regs */
0f8a249a 2124 {
1a2fb1c0 2125 int reg = (addr >> 8) & 0x1f;
0f8a249a 2126 uint32_t oldreg;
3b46e624 2127
0f8a249a 2128 oldreg = env->mmuregs[reg];
55754d9e 2129 switch(reg) {
3deaeab7 2130 case 0: // Control Register
3dd9a152 2131 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
1a2fb1c0 2132 (val & 0x00ffffff);
0f8a249a
BS		 2133 // Mappings generated during no-fault mode or MMU
2134 // disabled mode are invalid in normal mode
5578ceab
BS		 2135 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
2136 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm)))
55754d9e
FB		 2137 tlb_flush(env, 1);
2138 break;
3deaeab7 2139 case 1: // Context Table Pointer Register
5578ceab 2140 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
3deaeab7
BS		 2141 break;
2142 case 2: // Context Register
5578ceab 2143 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
55754d9e
FB		 2144 if (oldreg != env->mmuregs[reg]) {
2145 /* we flush when the MMU context changes because
2146 QEMU has no MMU context support */
2147 tlb_flush(env, 1);
2148 }
2149 break;
3deaeab7
BS		 2150 case 3: // Synchronous Fault Status Register with Clear
2151 case 4: // Synchronous Fault Address Register
2152 break;
2153 case 0x10: // TLB Replacement Control Register
5578ceab 2154 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
55754d9e 2155 break;
3deaeab7 2156 case 0x13: // Synchronous Fault Status Register with Read and Clear
5578ceab 2157 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
3dd9a152 2158 break;
3deaeab7 2159 case 0x14: // Synchronous Fault Address Register
1a2fb1c0 2160 env->mmuregs[4] = val;
3dd9a152 2161 break;
55754d9e 2162 default:
1a2fb1c0 2163 env->mmuregs[reg] = val;
55754d9e
FB		 2164 break;
2165 }
55754d9e 2166 if (oldreg != env->mmuregs[reg]) {
77f193da
BS		 2167 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
2168 reg, oldreg, env->mmuregs[reg]);
55754d9e 2169 }
952a328f 2170#ifdef DEBUG_MMU
d41160a3 2171 dump_mmu(stdout, fprintf, env);
55754d9e 2172#endif
0f8a249a 2173 }
8543e2cf 2174 break;
045380be
BS		 2175 case 5: // Turbosparc ITLB Diagnostic
2176 case 6: // Turbosparc DTLB Diagnostic
2177 case 7: // Turbosparc IOTLB Diagnostic
2178 break;
81ad8ba2
BS		 2179 case 0xa: /* User data access */
2180 switch(size) {
2181 case 1:
1a2fb1c0 2182 stb_user(addr, val);
81ad8ba2
BS		 2183 break;
2184 case 2:
a4e7dd52 2185 stw_user(addr, val);
81ad8ba2
BS		 2186 break;
2187 default:
2188 case 4:
a4e7dd52 2189 stl_user(addr, val);
81ad8ba2
BS		 2190 break;
2191 case 8:
a4e7dd52 2192 stq_user(addr, val);
81ad8ba2
BS		 2193 break;
2194 }
2195 break;
2196 case 0xb: /* Supervisor data access */
2197 switch(size) {
2198 case 1:
1a2fb1c0 2199 stb_kernel(addr, val);
81ad8ba2
BS		 2200 break;
2201 case 2:
a4e7dd52 2202 stw_kernel(addr, val);
81ad8ba2
BS		 2203 break;
2204 default:
2205 case 4:
a4e7dd52 2206 stl_kernel(addr, val);
81ad8ba2
BS		 2207 break;
2208 case 8:
a4e7dd52 2209 stq_kernel(addr, val);
81ad8ba2
BS		 2210 break;
2211 }
2212 break;
6c36d3fa
BS		 2213 case 0xc: /* I-cache tag */
2214 case 0xd: /* I-cache data */
2215 case 0xe: /* D-cache tag */
2216 case 0xf: /* D-cache data */
2217 case 0x10: /* I/D-cache flush page */
2218 case 0x11: /* I/D-cache flush segment */
2219 case 0x12: /* I/D-cache flush region */
2220 case 0x13: /* I/D-cache flush context */
2221 case 0x14: /* I/D-cache flush user */
2222 break;
e80cfcfc 2223 case 0x17: /* Block copy, sta access */
0f8a249a 2224 {
1a2fb1c0
BS		 2225 // val = src
2226 // addr = dst
0f8a249a 2227 // copy 32 bytes
6c36d3fa 2228 unsigned int i;
1a2fb1c0 2229 uint32_t src = val & ~3, dst = addr & ~3, temp;
3b46e624 2230
6c36d3fa
BS		 2231 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
2232 temp = ldl_kernel(src);
2233 stl_kernel(dst, temp);
2234 }
0f8a249a 2235 }
8543e2cf 2236 break;
e80cfcfc 2237 case 0x1f: /* Block fill, stda access */
0f8a249a 2238 {
1a2fb1c0
BS		 2239 // addr = dst
2240 // fill 32 bytes with val
6c36d3fa 2241 unsigned int i;
1a2fb1c0 2242 uint32_t dst = addr & 7;
6c36d3fa
BS		 2243
2244 for (i = 0; i < 32; i += 8, dst += 8)
2245 stq_kernel(dst, val);
0f8a249a 2246 }
8543e2cf 2247 break;
6c36d3fa 2248 case 0x20: /* MMU passthrough */
0f8a249a 2249 {
02aab46a
FB		 2250 switch(size) {
2251 case 1:
1a2fb1c0 2252 stb_phys(addr, val);
02aab46a
FB		 2253 break;
2254 case 2:
a4e7dd52 2255 stw_phys(addr, val);
02aab46a
FB		 2256 break;
2257 case 4:
2258 default:
a4e7dd52 2259 stl_phys(addr, val);
02aab46a 2260 break;
9e61bde5 2261 case 8:
a4e7dd52 2262 stq_phys(addr, val);
9e61bde5 2263 break;
02aab46a 2264 }
0f8a249a 2265 }
8543e2cf 2266 break;
045380be 2267 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
0f8a249a 2268 {
5dcb6b91
BS		 2269 switch(size) {
2270 case 1:
c227f099
AL		 2271 stb_phys((target_phys_addr_t)addr
2272 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 2273 break;
2274 case 2:
c227f099
AL		 2275 stw_phys((target_phys_addr_t)addr
2276 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 2277 break;
2278 case 4:
2279 default:
c227f099
AL		 2280 stl_phys((target_phys_addr_t)addr
2281 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 2282 break;
2283 case 8:
c227f099
AL		 2284 stq_phys((target_phys_addr_t)addr
2285 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 2286 break;
2287 }
0f8a249a 2288 }
8543e2cf 2289 break;
045380be
BS		 2290 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
2291 case 0x31: // store buffer data, Ross RT620 I-cache flush or
2292 // Turbosparc snoop RAM
77f193da
BS		 2293 case 0x32: // store buffer control or Turbosparc page table
2294 // descriptor diagnostic
6c36d3fa
BS		 2295 case 0x36: /* I-cache flash clear */
2296 case 0x37: /* D-cache flash clear */
666c87aa 2297 case 0x4c: /* breakpoint action */
6c36d3fa 2298 break;
4017190e
BS		 2299 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
2300 {
2301 int reg = (addr >> 8) & 3;
2302
2303 switch(reg) {
2304 case 0: /* Breakpoint Value (Addr) */
2305 env->mmubpregs[reg] = (val & 0xfffffffffULL);
2306 break;
2307 case 1: /* Breakpoint Mask */
2308 env->mmubpregs[reg] = (val & 0xfffffffffULL);
2309 break;
2310 case 2: /* Breakpoint Control */
2311 env->mmubpregs[reg] = (val & 0x7fULL);
2312 break;
2313 case 3: /* Breakpoint Status */
2314 env->mmubpregs[reg] = (val & 0xfULL);
2315 break;
2316 }
0bf9e31a 2317 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
4017190e
BS		 2318 env->mmuregs[reg]);
2319 }
2320 break;
045380be 2321 case 8: /* User code access, XXX */
6c36d3fa 2322 case 9: /* Supervisor code access, XXX */
e8af50a3 2323 default:
e18231a3 2324 do_unassigned_access(addr, 1, 0, asi, size);
8543e2cf 2325 break;
e8af50a3 2326 }
8543e2cf 2327#ifdef DEBUG_ASI
1a2fb1c0 2328 dump_asi("write", addr, asi, size, val);
8543e2cf 2329#endif
e8af50a3
FB		 2330}
2331
81ad8ba2
BS		 2332#endif /* CONFIG_USER_ONLY */
2333#else /* TARGET_SPARC64 */
2334
2335#ifdef CONFIG_USER_ONLY
1a2fb1c0 2336uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
81ad8ba2
BS		 2337{
2338 uint64_t ret = 0;
1a2fb1c0
BS		 2339#if defined(DEBUG_ASI)
2340 target_ulong last_addr = addr;
2341#endif
81ad8ba2
BS		 2342
2343 if (asi < 0x80)
2344 raise_exception(TT_PRIV_ACT);
2345
c2bc0e38 2346 helper_check_align(addr, size - 1);
1295001c 2347 addr = asi_address_mask(env, asi, addr);
c2bc0e38 2348
81ad8ba2 2349 switch (asi) {
81ad8ba2 2350 case 0x82: // Primary no-fault
81ad8ba2 2351 case 0x8a: // Primary no-fault LE
e83ce550
BS		 2352 if (page_check_range(addr, size, PAGE_READ) == -1) {
2353#ifdef DEBUG_ASI
2354 dump_asi("read ", last_addr, asi, size, ret);
2355#endif
2356 return 0;
2357 }
2358 // Fall through
2359 case 0x80: // Primary
2360 case 0x88: // Primary LE
81ad8ba2
BS		 2361 {
2362 switch(size) {
2363 case 1:
1a2fb1c0 2364 ret = ldub_raw(addr);
81ad8ba2
BS		 2365 break;
2366 case 2:
a4e7dd52 2367 ret = lduw_raw(addr);
81ad8ba2
BS		 2368 break;
2369 case 4:
a4e7dd52 2370 ret = ldl_raw(addr);
81ad8ba2
BS		 2371 break;
2372 default:
2373 case 8:
a4e7dd52 2374 ret = ldq_raw(addr);
81ad8ba2
BS		 2375 break;
2376 }
2377 }
2378 break;
81ad8ba2 2379 case 0x83: // Secondary no-fault
81ad8ba2 2380 case 0x8b: // Secondary no-fault LE
e83ce550
BS		 2381 if (page_check_range(addr, size, PAGE_READ) == -1) {
2382#ifdef DEBUG_ASI
2383 dump_asi("read ", last_addr, asi, size, ret);
2384#endif
2385 return 0;
2386 }
2387 // Fall through
2388 case 0x81: // Secondary
2389 case 0x89: // Secondary LE
81ad8ba2
BS		 2390 // XXX
2391 break;
2392 default:
2393 break;
2394 }
2395
2396 /* Convert from little endian */
2397 switch (asi) {
2398 case 0x88: // Primary LE
2399 case 0x89: // Secondary LE
2400 case 0x8a: // Primary no-fault LE
2401 case 0x8b: // Secondary no-fault LE
2402 switch(size) {
2403 case 2:
2404 ret = bswap16(ret);
e32664fb 2405 break;
81ad8ba2
BS		 2406 case 4:
2407 ret = bswap32(ret);
e32664fb 2408 break;
81ad8ba2
BS		 2409 case 8:
2410 ret = bswap64(ret);
e32664fb 2411 break;
81ad8ba2
BS		 2412 default:
2413 break;
2414 }
2415 default:
2416 break;
2417 }
2418
2419 /* Convert to signed number */
2420 if (sign) {
2421 switch(size) {
2422 case 1:
2423 ret = (int8_t) ret;
e32664fb 2424 break;
81ad8ba2
BS		 2425 case 2:
2426 ret = (int16_t) ret;
e32664fb 2427 break;
81ad8ba2
BS		 2428 case 4:
2429 ret = (int32_t) ret;
e32664fb 2430 break;
81ad8ba2
BS		 2431 default:
2432 break;
2433 }
2434 }
1a2fb1c0
BS		 2435#ifdef DEBUG_ASI
2436 dump_asi("read ", last_addr, asi, size, ret);
2437#endif
2438 return ret;
81ad8ba2
BS		 2439}
2440
1a2fb1c0 2441void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
81ad8ba2 2442{
1a2fb1c0
BS		 2443#ifdef DEBUG_ASI
2444 dump_asi("write", addr, asi, size, val);
2445#endif
81ad8ba2
BS		 2446 if (asi < 0x80)
2447 raise_exception(TT_PRIV_ACT);
2448
c2bc0e38 2449 helper_check_align(addr, size - 1);
1295001c 2450 addr = asi_address_mask(env, asi, addr);
c2bc0e38 2451
81ad8ba2
BS		 2452 /* Convert to little endian */
2453 switch (asi) {
2454 case 0x88: // Primary LE
2455 case 0x89: // Secondary LE
2456 switch(size) {
2457 case 2:
5b0f0bec 2458 val = bswap16(val);
e32664fb 2459 break;
81ad8ba2 2460 case 4:
5b0f0bec 2461 val = bswap32(val);
e32664fb 2462 break;
81ad8ba2 2463 case 8:
5b0f0bec 2464 val = bswap64(val);
e32664fb 2465 break;
81ad8ba2
BS		 2466 default:
2467 break;
2468 }
2469 default:
2470 break;
2471 }
2472
2473 switch(asi) {
2474 case 0x80: // Primary
2475 case 0x88: // Primary LE
2476 {
2477 switch(size) {
2478 case 1:
1a2fb1c0 2479 stb_raw(addr, val);
81ad8ba2
BS		 2480 break;
2481 case 2:
a4e7dd52 2482 stw_raw(addr, val);
81ad8ba2
BS		 2483 break;
2484 case 4:
a4e7dd52 2485 stl_raw(addr, val);
81ad8ba2
BS		 2486 break;
2487 case 8:
2488 default:
a4e7dd52 2489 stq_raw(addr, val);
81ad8ba2
BS		 2490 break;
2491 }
2492 }
2493 break;
2494 case 0x81: // Secondary
2495 case 0x89: // Secondary LE
2496 // XXX
2497 return;
2498
2499 case 0x82: // Primary no-fault, RO
2500 case 0x83: // Secondary no-fault, RO
2501 case 0x8a: // Primary no-fault LE, RO
2502 case 0x8b: // Secondary no-fault LE, RO
2503 default:
e18231a3 2504 do_unassigned_access(addr, 1, 0, 1, size);
81ad8ba2
BS		 2505 return;
2506 }
2507}
2508
2509#else /* CONFIG_USER_ONLY */
3475187d 2510
1a2fb1c0 2511uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
3475187d 2512{
83469015 2513 uint64_t ret = 0;
1a2fb1c0
BS		 2514#if defined(DEBUG_ASI)
2515 target_ulong last_addr = addr;
2516#endif
3475187d 2517
01b5d4e5
IK		 2518 asi &= 0xff;
2519
6f27aba6 2520 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2aae2b8e 2521 || (cpu_has_hypervisor(env)
5578ceab 2522 && asi >= 0x30 && asi < 0x80
fb79ceb9 2523 && !(env->hpstate & HS_PRIV)))
0f8a249a 2524 raise_exception(TT_PRIV_ACT);
3475187d 2525
c2bc0e38 2526 helper_check_align(addr, size - 1);
1295001c
IK		 2527 addr = asi_address_mask(env, asi, addr);
2528
3475187d 2529 switch (asi) {
e83ce550
BS		 2530 case 0x82: // Primary no-fault
2531 case 0x8a: // Primary no-fault LE
2065061e
IK		 2532 case 0x83: // Secondary no-fault
2533 case 0x8b: // Secondary no-fault LE
2534 {
2535 /* secondary space access has lowest asi bit equal to 1 */
2536 int access_mmu_idx = ( asi & 1 ) ? MMU_KERNEL_IDX
2537 : MMU_KERNEL_SECONDARY_IDX;
2538
2539 if (cpu_get_phys_page_nofault(env, addr, access_mmu_idx) == -1ULL) {
e83ce550 2540#ifdef DEBUG_ASI
2065061e 2541 dump_asi("read ", last_addr, asi, size, ret);
e83ce550 2542#endif
2065061e
IK		 2543 return 0;
2544 }
e83ce550
BS		 2545 }
2546 // Fall through
81ad8ba2 2547 case 0x10: // As if user primary
2065061e 2548 case 0x11: // As if user secondary
81ad8ba2 2549 case 0x18: // As if user primary LE
2065061e 2550 case 0x19: // As if user secondary LE
81ad8ba2 2551 case 0x80: // Primary
2065061e 2552 case 0x81: // Secondary
81ad8ba2 2553 case 0x88: // Primary LE
2065061e 2554 case 0x89: // Secondary LE
c99657d3
BS		 2555 case 0xe2: // UA2007 Primary block init
2556 case 0xe3: // UA2007 Secondary block init
81ad8ba2 2557 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
2aae2b8e 2558 if (cpu_hypervisor_mode(env)) {
6f27aba6
BS		 2559 switch(size) {
2560 case 1:
1a2fb1c0 2561 ret = ldub_hypv(addr);
6f27aba6
BS		 2562 break;
2563 case 2:
a4e7dd52 2564 ret = lduw_hypv(addr);
6f27aba6
BS		 2565 break;
2566 case 4:
a4e7dd52 2567 ret = ldl_hypv(addr);
6f27aba6
BS		 2568 break;
2569 default:
2570 case 8:
a4e7dd52 2571 ret = ldq_hypv(addr);
6f27aba6
BS		 2572 break;
2573 }
2574 } else {
2065061e
IK		 2575 /* secondary space access has lowest asi bit equal to 1 */
2576 if (asi & 1) {
2577 switch(size) {
2578 case 1:
2579 ret = ldub_kernel_secondary(addr);
2580 break;
2581 case 2:
2582 ret = lduw_kernel_secondary(addr);
2583 break;
2584 case 4:
2585 ret = ldl_kernel_secondary(addr);
2586 break;
2587 default:
2588 case 8:
2589 ret = ldq_kernel_secondary(addr);
2590 break;
2591 }
2592 } else {
2593 switch(size) {
2594 case 1:
2595 ret = ldub_kernel(addr);
2596 break;
2597 case 2:
2598 ret = lduw_kernel(addr);
2599 break;
2600 case 4:
2601 ret = ldl_kernel(addr);
2602 break;
2603 default:
2604 case 8:
2605 ret = ldq_kernel(addr);
2606 break;
2607 }
2608 }
2609 }
2610 } else {
2611 /* secondary space access has lowest asi bit equal to 1 */
2612 if (asi & 1) {
6f27aba6
BS		 2613 switch(size) {
2614 case 1:
2065061e 2615 ret = ldub_user_secondary(addr);
6f27aba6
BS		 2616 break;
2617 case 2:
2065061e 2618 ret = lduw_user_secondary(addr);
6f27aba6
BS		 2619 break;
2620 case 4:
2065061e 2621 ret = ldl_user_secondary(addr);
6f27aba6
BS		 2622 break;
2623 default:
2624 case 8:
2065061e
IK		 2625 ret = ldq_user_secondary(addr);
2626 break;
2627 }
2628 } else {
2629 switch(size) {
2630 case 1:
2631 ret = ldub_user(addr);
2632 break;
2633 case 2:
2634 ret = lduw_user(addr);
2635 break;
2636 case 4:
2637 ret = ldl_user(addr);
2638 break;
2639 default:
2640 case 8:
2641 ret = ldq_user(addr);
6f27aba6
BS		 2642 break;
2643 }
81ad8ba2
BS		 2644 }
2645 }
2646 break;
3475187d
FB		 2647 case 0x14: // Bypass
2648 case 0x15: // Bypass, non-cacheable
81ad8ba2
BS		 2649 case 0x1c: // Bypass LE
2650 case 0x1d: // Bypass, non-cacheable LE
0f8a249a 2651 {
02aab46a
FB		 2652 switch(size) {
2653 case 1:
1a2fb1c0 2654 ret = ldub_phys(addr);
02aab46a
FB		 2655 break;
2656 case 2:
a4e7dd52 2657 ret = lduw_phys(addr);
02aab46a
FB		 2658 break;
2659 case 4:
a4e7dd52 2660 ret = ldl_phys(addr);
02aab46a
FB		 2661 break;
2662 default:
2663 case 8:
a4e7dd52 2664 ret = ldq_phys(addr);
02aab46a
FB		 2665 break;
2666 }
0f8a249a
BS		 2667 break;
2668 }
db166940
BS		 2669 case 0x24: // Nucleus quad LDD 128 bit atomic
2670 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2671 // Only ldda allowed
2672 raise_exception(TT_ILL_INSN);
2673 return 0;
83469015
FB		 2674 case 0x04: // Nucleus
2675 case 0x0c: // Nucleus Little Endian (LE)
2065061e
IK		 2676 {
2677 switch(size) {
2678 case 1:
2679 ret = ldub_nucleus(addr);
2680 break;
2681 case 2:
2682 ret = lduw_nucleus(addr);
2683 break;
2684 case 4:
2685 ret = ldl_nucleus(addr);
2686 break;
2687 default:
2688 case 8:
2689 ret = ldq_nucleus(addr);
2690 break;
2691 }
2692 break;
2693 }
83469015 2694 case 0x4a: // UPA config
0f8a249a
BS		 2695 // XXX
2696 break;
3475187d 2697 case 0x45: // LSU
0f8a249a
BS		 2698 ret = env->lsu;
2699 break;
3475187d 2700 case 0x50: // I-MMU regs
0f8a249a 2701 {
1a2fb1c0 2702 int reg = (addr >> 3) & 0xf;
3475187d 2703
697a77e6
IK		 2704 if (reg == 0) {
2705 // I-TSB Tag Target register
6e8e7d4c 2706 ret = ultrasparc_tag_target(env->immu.tag_access);
697a77e6
IK		 2707 } else {
2708 ret = env->immuregs[reg];
2709 }
2710
0f8a249a
BS		 2711 break;
2712 }
3475187d 2713 case 0x51: // I-MMU 8k TSB pointer
697a77e6
IK		 2714 {
2715 // env->immuregs[5] holds I-MMU TSB register value
2716 // env->immuregs[6] holds I-MMU Tag Access register value
6e8e7d4c 2717 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
697a77e6
IK		 2718 8*1024);
2719 break;
2720 }
3475187d 2721 case 0x52: // I-MMU 64k TSB pointer
697a77e6
IK		 2722 {
2723 // env->immuregs[5] holds I-MMU TSB register value
2724 // env->immuregs[6] holds I-MMU Tag Access register value
6e8e7d4c 2725 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
697a77e6
IK		 2726 64*1024);
2727 break;
2728 }
a5a52cf2
BS		 2729 case 0x55: // I-MMU data access
2730 {
2731 int reg = (addr >> 3) & 0x3f;
2732
6e8e7d4c 2733 ret = env->itlb[reg].tte;
a5a52cf2
BS		 2734 break;
2735 }
83469015 2736 case 0x56: // I-MMU tag read
0f8a249a 2737 {
43e9e742 2738 int reg = (addr >> 3) & 0x3f;
0f8a249a 2739
6e8e7d4c 2740 ret = env->itlb[reg].tag;
0f8a249a
BS		 2741 break;
2742 }
3475187d 2743 case 0x58: // D-MMU regs
0f8a249a 2744 {
1a2fb1c0 2745 int reg = (addr >> 3) & 0xf;
3475187d 2746
697a77e6
IK		 2747 if (reg == 0) {
2748 // D-TSB Tag Target register
6e8e7d4c 2749 ret = ultrasparc_tag_target(env->dmmu.tag_access);
697a77e6
IK		 2750 } else {
2751 ret = env->dmmuregs[reg];
2752 }
2753 break;
2754 }
2755 case 0x59: // D-MMU 8k TSB pointer
2756 {
2757 // env->dmmuregs[5] holds D-MMU TSB register value
2758 // env->dmmuregs[6] holds D-MMU Tag Access register value
6e8e7d4c 2759 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
697a77e6
IK		 2760 8*1024);
2761 break;
2762 }
2763 case 0x5a: // D-MMU 64k TSB pointer
2764 {
2765 // env->dmmuregs[5] holds D-MMU TSB register value
2766 // env->dmmuregs[6] holds D-MMU Tag Access register value
6e8e7d4c 2767 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
697a77e6 2768 64*1024);
0f8a249a
BS		 2769 break;
2770 }
a5a52cf2
BS		 2771 case 0x5d: // D-MMU data access
2772 {
2773 int reg = (addr >> 3) & 0x3f;
2774
6e8e7d4c 2775 ret = env->dtlb[reg].tte;
a5a52cf2
BS		 2776 break;
2777 }
83469015 2778 case 0x5e: // D-MMU tag read
0f8a249a 2779 {
43e9e742 2780 int reg = (addr >> 3) & 0x3f;
0f8a249a 2781
6e8e7d4c 2782 ret = env->dtlb[reg].tag;
0f8a249a
BS		 2783 break;
2784 }
f7350b47
BS		 2785 case 0x46: // D-cache data
2786 case 0x47: // D-cache tag access
a5a52cf2
BS		 2787 case 0x4b: // E-cache error enable
2788 case 0x4c: // E-cache asynchronous fault status
2789 case 0x4d: // E-cache asynchronous fault address
f7350b47
BS		 2790 case 0x4e: // E-cache tag data
2791 case 0x66: // I-cache instruction access
2792 case 0x67: // I-cache tag access
2793 case 0x6e: // I-cache predecode
2794 case 0x6f: // I-cache LRU etc.
2795 case 0x76: // E-cache tag
2796 case 0x7e: // E-cache tag
2797 break;
3475187d 2798 case 0x5b: // D-MMU data pointer
83469015
FB		 2799 case 0x48: // Interrupt dispatch, RO
2800 case 0x49: // Interrupt data receive
2801 case 0x7f: // Incoming interrupt vector, RO
0f8a249a
BS		 2802 // XXX
2803 break;
3475187d
FB		 2804 case 0x54: // I-MMU data in, WO
2805 case 0x57: // I-MMU demap, WO
2806 case 0x5c: // D-MMU data in, WO
2807 case 0x5f: // D-MMU demap, WO
83469015 2808 case 0x77: // Interrupt vector, WO
3475187d 2809 default:
e18231a3 2810 do_unassigned_access(addr, 0, 0, 1, size);
0f8a249a
BS		 2811 ret = 0;
2812 break;
3475187d 2813 }
81ad8ba2
BS		 2814
2815 /* Convert from little endian */
2816 switch (asi) {
2817 case 0x0c: // Nucleus Little Endian (LE)
2818 case 0x18: // As if user primary LE
2819 case 0x19: // As if user secondary LE
2820 case 0x1c: // Bypass LE
2821 case 0x1d: // Bypass, non-cacheable LE
2822 case 0x88: // Primary LE
2823 case 0x89: // Secondary LE
2824 case 0x8a: // Primary no-fault LE
2825 case 0x8b: // Secondary no-fault LE
2826 switch(size) {
2827 case 2:
2828 ret = bswap16(ret);
e32664fb 2829 break;
81ad8ba2
BS		 2830 case 4:
2831 ret = bswap32(ret);
e32664fb 2832 break;
81ad8ba2
BS		 2833 case 8:
2834 ret = bswap64(ret);
e32664fb 2835 break;
81ad8ba2
BS		 2836 default:
2837 break;
2838 }
2839 default:
2840 break;
2841 }
2842
2843 /* Convert to signed number */
2844 if (sign) {
2845 switch(size) {
2846 case 1:
2847 ret = (int8_t) ret;
e32664fb 2848 break;
81ad8ba2
BS		 2849 case 2:
2850 ret = (int16_t) ret;
e32664fb 2851 break;
81ad8ba2
BS		 2852 case 4:
2853 ret = (int32_t) ret;
e32664fb 2854 break;
81ad8ba2
BS		 2855 default:
2856 break;
2857 }
2858 }
1a2fb1c0
BS		 2859#ifdef DEBUG_ASI
2860 dump_asi("read ", last_addr, asi, size, ret);
2861#endif
2862 return ret;
3475187d
FB		 2863}
2864
1a2fb1c0 2865void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
3475187d 2866{
1a2fb1c0
BS		 2867#ifdef DEBUG_ASI
2868 dump_asi("write", addr, asi, size, val);
2869#endif
01b5d4e5
IK		 2870
2871 asi &= 0xff;
2872
6f27aba6 2873 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2aae2b8e 2874 || (cpu_has_hypervisor(env)
5578ceab 2875 && asi >= 0x30 && asi < 0x80
fb79ceb9 2876 && !(env->hpstate & HS_PRIV)))
0f8a249a 2877 raise_exception(TT_PRIV_ACT);
3475187d 2878
c2bc0e38 2879 helper_check_align(addr, size - 1);
1295001c
IK		 2880 addr = asi_address_mask(env, asi, addr);
2881
81ad8ba2
BS		 2882 /* Convert to little endian */
2883 switch (asi) {
2884 case 0x0c: // Nucleus Little Endian (LE)
2885 case 0x18: // As if user primary LE
2886 case 0x19: // As if user secondary LE
2887 case 0x1c: // Bypass LE
2888 case 0x1d: // Bypass, non-cacheable LE
81ad8ba2
BS		 2889 case 0x88: // Primary LE
2890 case 0x89: // Secondary LE
2891 switch(size) {
2892 case 2:
5b0f0bec 2893 val = bswap16(val);
e32664fb 2894 break;
81ad8ba2 2895 case 4:
5b0f0bec 2896 val = bswap32(val);
e32664fb 2897 break;
81ad8ba2 2898 case 8:
5b0f0bec 2899 val = bswap64(val);
e32664fb 2900 break;
81ad8ba2
BS		 2901 default:
2902 break;
2903 }
2904 default:
2905 break;
2906 }
2907
3475187d 2908 switch(asi) {
81ad8ba2 2909 case 0x10: // As if user primary
2065061e 2910 case 0x11: // As if user secondary
81ad8ba2 2911 case 0x18: // As if user primary LE
2065061e 2912 case 0x19: // As if user secondary LE
81ad8ba2 2913 case 0x80: // Primary
2065061e 2914 case 0x81: // Secondary
81ad8ba2 2915 case 0x88: // Primary LE
2065061e 2916 case 0x89: // Secondary LE
c99657d3
BS		 2917 case 0xe2: // UA2007 Primary block init
2918 case 0xe3: // UA2007 Secondary block init
81ad8ba2 2919 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
2aae2b8e 2920 if (cpu_hypervisor_mode(env)) {
6f27aba6
BS		 2921 switch(size) {
2922 case 1:
1a2fb1c0 2923 stb_hypv(addr, val);
6f27aba6
BS		 2924 break;
2925 case 2:
a4e7dd52 2926 stw_hypv(addr, val);
6f27aba6
BS		 2927 break;
2928 case 4:
a4e7dd52 2929 stl_hypv(addr, val);
6f27aba6
BS		 2930 break;
2931 case 8:
2932 default:
a4e7dd52 2933 stq_hypv(addr, val);
6f27aba6
BS		 2934 break;
2935 }
2936 } else {
2065061e
IK		 2937 /* secondary space access has lowest asi bit equal to 1 */
2938 if (asi & 1) {
2939 switch(size) {
2940 case 1:
2941 stb_kernel_secondary(addr, val);
2942 break;
2943 case 2:
2944 stw_kernel_secondary(addr, val);
2945 break;
2946 case 4:
2947 stl_kernel_secondary(addr, val);
2948 break;
2949 case 8:
2950 default:
2951 stq_kernel_secondary(addr, val);
2952 break;
2953 }
2954 } else {
2955 switch(size) {
2956 case 1:
2957 stb_kernel(addr, val);
2958 break;
2959 case 2:
2960 stw_kernel(addr, val);
2961 break;
2962 case 4:
2963 stl_kernel(addr, val);
2964 break;
2965 case 8:
2966 default:
2967 stq_kernel(addr, val);
2968 break;
2969 }
2970 }
2971 }
2972 } else {
2973 /* secondary space access has lowest asi bit equal to 1 */
2974 if (asi & 1) {
6f27aba6
BS		 2975 switch(size) {
2976 case 1:
2065061e 2977 stb_user_secondary(addr, val);
6f27aba6
BS		 2978 break;
2979 case 2:
2065061e 2980 stw_user_secondary(addr, val);
6f27aba6
BS		 2981 break;
2982 case 4:
2065061e 2983 stl_user_secondary(addr, val);
6f27aba6
BS		 2984 break;
2985 case 8:
2986 default:
2065061e
IK		 2987 stq_user_secondary(addr, val);
2988 break;
2989 }
2990 } else {
2991 switch(size) {
2992 case 1:
2993 stb_user(addr, val);
2994 break;
2995 case 2:
2996 stw_user(addr, val);
2997 break;
2998 case 4:
2999 stl_user(addr, val);
3000 break;
3001 case 8:
3002 default:
3003 stq_user(addr, val);
6f27aba6
BS		 3004 break;
3005 }
81ad8ba2
BS		 3006 }
3007 }
3008 break;
3475187d
FB		 3009 case 0x14: // Bypass
3010 case 0x15: // Bypass, non-cacheable
81ad8ba2
BS		 3011 case 0x1c: // Bypass LE
3012 case 0x1d: // Bypass, non-cacheable LE
0f8a249a 3013 {
02aab46a
FB		 3014 switch(size) {
3015 case 1:
1a2fb1c0 3016 stb_phys(addr, val);
02aab46a
FB		 3017 break;
3018 case 2:
a4e7dd52 3019 stw_phys(addr, val);
02aab46a
FB		 3020 break;
3021 case 4:
a4e7dd52 3022 stl_phys(addr, val);
02aab46a
FB		 3023 break;
3024 case 8:
3025 default:
a4e7dd52 3026 stq_phys(addr, val);
02aab46a
FB		 3027 break;
3028 }
0f8a249a
BS		 3029 }
3030 return;
db166940
BS		 3031 case 0x24: // Nucleus quad LDD 128 bit atomic
3032 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
3033 // Only ldda allowed
3034 raise_exception(TT_ILL_INSN);
3035 return;
83469015
FB		 3036 case 0x04: // Nucleus
3037 case 0x0c: // Nucleus Little Endian (LE)
2065061e
IK		 3038 {
3039 switch(size) {
3040 case 1:
3041 stb_nucleus(addr, val);
3042 break;
3043 case 2:
3044 stw_nucleus(addr, val);
3045 break;
3046 case 4:
3047 stl_nucleus(addr, val);
3048 break;
3049 default:
3050 case 8:
3051 stq_nucleus(addr, val);
3052 break;
3053 }
3054 break;
3055 }
3056
83469015 3057 case 0x4a: // UPA config
0f8a249a
BS		 3058 // XXX
3059 return;
3475187d 3060 case 0x45: // LSU
0f8a249a
BS		 3061 {
3062 uint64_t oldreg;
3063
3064 oldreg = env->lsu;
1a2fb1c0 3065 env->lsu = val & (DMMU_E | IMMU_E);
0f8a249a
BS		 3066 // Mappings generated during D/I MMU disabled mode are
3067 // invalid in normal mode
3068 if (oldreg != env->lsu) {
77f193da
BS		 3069 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
3070 oldreg, env->lsu);
83469015 3071#ifdef DEBUG_MMU
d41160a3 3072 dump_mmu(stdout, fprintf, env1);
83469015 3073#endif
0f8a249a
BS		 3074 tlb_flush(env, 1);
3075 }
3076 return;
3077 }
3475187d 3078 case 0x50: // I-MMU regs
0f8a249a 3079 {
1a2fb1c0 3080 int reg = (addr >> 3) & 0xf;
0f8a249a 3081 uint64_t oldreg;
3b46e624 3082
0f8a249a 3083 oldreg = env->immuregs[reg];
3475187d
FB		 3084 switch(reg) {
3085 case 0: // RO
3475187d
FB		 3086 return;
3087 case 1: // Not in I-MMU
3088 case 2:
3475187d
FB		 3089 return;
3090 case 3: // SFSR
1a2fb1c0
BS		 3091 if ((val & 1) == 0)
3092 val = 0; // Clear SFSR
6e8e7d4c 3093 env->immu.sfsr = val;
3475187d 3094 break;
6e8e7d4c
IK		 3095 case 4: // RO
3096 return;
3475187d 3097 case 5: // TSB access
6e8e7d4c
IK		 3098 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
3099 PRIx64 "\n", env->immu.tsb, val);
3100 env->immu.tsb = val;
3101 break;
3475187d 3102 case 6: // Tag access
6e8e7d4c
IK		 3103 env->immu.tag_access = val;
3104 break;
3105 case 7:
3106 case 8:
3107 return;
3475187d
FB		 3108 default:
3109 break;
3110 }
6e8e7d4c 3111
3475187d 3112 if (oldreg != env->immuregs[reg]) {
6e8e7d4c 3113 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
77f193da 3114 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
3475187d 3115 }
952a328f 3116#ifdef DEBUG_MMU
d41160a3 3117 dump_mmu(stdout, fprintf, env);
3475187d 3118#endif
0f8a249a
BS		 3119 return;
3120 }
3475187d 3121 case 0x54: // I-MMU data in
f707726e
IK		 3122 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
3123 return;
3475187d 3124 case 0x55: // I-MMU data access
0f8a249a 3125 {
cc6747f4
BS		 3126 // TODO: auto demap
3127
1a2fb1c0 3128 unsigned int i = (addr >> 3) & 0x3f;
3475187d 3129
f707726e 3130 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env);
6e8e7d4c
IK		 3131
3132#ifdef DEBUG_MMU
f707726e 3133 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
d41160a3 3134 dump_mmu(stdout, fprintf, env);
6e8e7d4c 3135#endif
0f8a249a
BS		 3136 return;
3137 }
3475187d 3138 case 0x57: // I-MMU demap
170f4c55 3139 demap_tlb(env->itlb, addr, "immu", env);
0f8a249a 3140 return;
3475187d 3141 case 0x58: // D-MMU regs
0f8a249a 3142 {
1a2fb1c0 3143 int reg = (addr >> 3) & 0xf;
0f8a249a 3144 uint64_t oldreg;
3b46e624 3145
0f8a249a 3146 oldreg = env->dmmuregs[reg];
3475187d
FB		 3147 switch(reg) {
3148 case 0: // RO
3149 case 4:
3150 return;
3151 case 3: // SFSR
1a2fb1c0
BS		 3152 if ((val & 1) == 0) {
3153 val = 0; // Clear SFSR, Fault address
6e8e7d4c 3154 env->dmmu.sfar = 0;
0f8a249a 3155 }
6e8e7d4c 3156 env->dmmu.sfsr = val;
3475187d
FB		 3157 break;
3158 case 1: // Primary context
6e8e7d4c 3159 env->dmmu.mmu_primary_context = val;
664a65b0
IK		 3160 /* can be optimized to only flush MMU_USER_IDX
3161 and MMU_KERNEL_IDX entries */
3162 tlb_flush(env, 1);
6e8e7d4c 3163 break;
3475187d 3164 case 2: // Secondary context
6e8e7d4c 3165 env->dmmu.mmu_secondary_context = val;
664a65b0
IK		 3166 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
3167 and MMU_KERNEL_SECONDARY_IDX entries */
3168 tlb_flush(env, 1);
6e8e7d4c 3169 break;
3475187d 3170 case 5: // TSB access
6e8e7d4c
IK		 3171 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
3172 PRIx64 "\n", env->dmmu.tsb, val);
3173 env->dmmu.tsb = val;
3174 break;
3475187d 3175 case 6: // Tag access
6e8e7d4c
IK		 3176 env->dmmu.tag_access = val;
3177 break;
3475187d
FB		 3178 case 7: // Virtual Watchpoint
3179 case 8: // Physical Watchpoint
3180 default:
6e8e7d4c 3181 env->dmmuregs[reg] = val;
3475187d
FB		 3182 break;
3183 }
6e8e7d4c 3184
3475187d 3185 if (oldreg != env->dmmuregs[reg]) {
6e8e7d4c 3186 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
77f193da 3187 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
3475187d 3188 }
952a328f 3189#ifdef DEBUG_MMU
d41160a3 3190 dump_mmu(stdout, fprintf, env);
3475187d 3191#endif
0f8a249a
BS		 3192 return;
3193 }
3475187d 3194 case 0x5c: // D-MMU data in
f707726e
IK		 3195 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
3196 return;
3475187d 3197 case 0x5d: // D-MMU data access
0f8a249a 3198 {
1a2fb1c0 3199 unsigned int i = (addr >> 3) & 0x3f;
3475187d 3200
f707726e
IK		 3201 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env);
3202
6e8e7d4c 3203#ifdef DEBUG_MMU
f707726e 3204 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
d41160a3 3205 dump_mmu(stdout, fprintf, env);
6e8e7d4c 3206#endif
0f8a249a
BS		 3207 return;
3208 }
3475187d 3209 case 0x5f: // D-MMU demap
170f4c55 3210 demap_tlb(env->dtlb, addr, "dmmu", env);
cc6747f4 3211 return;
83469015 3212 case 0x49: // Interrupt data receive
0f8a249a
BS		 3213 // XXX
3214 return;
f7350b47
BS		 3215 case 0x46: // D-cache data
3216 case 0x47: // D-cache tag access
a5a52cf2
BS		 3217 case 0x4b: // E-cache error enable
3218 case 0x4c: // E-cache asynchronous fault status
3219 case 0x4d: // E-cache asynchronous fault address
f7350b47
BS		 3220 case 0x4e: // E-cache tag data
3221 case 0x66: // I-cache instruction access
3222 case 0x67: // I-cache tag access
3223 case 0x6e: // I-cache predecode
3224 case 0x6f: // I-cache LRU etc.
3225 case 0x76: // E-cache tag
3226 case 0x7e: // E-cache tag
3227 return;
3475187d
FB		 3228 case 0x51: // I-MMU 8k TSB pointer, RO
3229 case 0x52: // I-MMU 64k TSB pointer, RO
3230 case 0x56: // I-MMU tag read, RO
3231 case 0x59: // D-MMU 8k TSB pointer, RO
3232 case 0x5a: // D-MMU 64k TSB pointer, RO
3233 case 0x5b: // D-MMU data pointer, RO
3234 case 0x5e: // D-MMU tag read, RO
83469015
FB		 3235 case 0x48: // Interrupt dispatch, RO
3236 case 0x7f: // Incoming interrupt vector, RO
3237 case 0x82: // Primary no-fault, RO
3238 case 0x83: // Secondary no-fault, RO
3239 case 0x8a: // Primary no-fault LE, RO
3240 case 0x8b: // Secondary no-fault LE, RO
3475187d 3241 default:
e18231a3 3242 do_unassigned_access(addr, 1, 0, 1, size);
0f8a249a 3243 return;
3475187d
FB		 3244 }
3245}
81ad8ba2 3246#endif /* CONFIG_USER_ONLY */
3391c818 3247
db166940
BS		 3248void helper_ldda_asi(target_ulong addr, int asi, int rd)
3249{
db166940 3250 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2aae2b8e 3251 || (cpu_has_hypervisor(env)
5578ceab 3252 && asi >= 0x30 && asi < 0x80
fb79ceb9 3253 && !(env->hpstate & HS_PRIV)))
db166940
BS		 3254 raise_exception(TT_PRIV_ACT);
3255
1295001c
IK		 3256 addr = asi_address_mask(env, asi, addr);
3257
db166940 3258 switch (asi) {
03ae77d6 3259#if !defined(CONFIG_USER_ONLY)
db166940
BS		 3260 case 0x24: // Nucleus quad LDD 128 bit atomic
3261 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
3262 helper_check_align(addr, 0xf);
3263 if (rd == 0) {
54a3c0f0 3264 env->gregs[1] = ldq_nucleus(addr + 8);
db166940
BS		 3265 if (asi == 0x2c)
3266 bswap64s(&env->gregs[1]);
3267 } else if (rd < 8) {
54a3c0f0
IK		 3268 env->gregs[rd] = ldq_nucleus(addr);
3269 env->gregs[rd + 1] = ldq_nucleus(addr + 8);
db166940
BS		 3270 if (asi == 0x2c) {
3271 bswap64s(&env->gregs[rd]);
3272 bswap64s(&env->gregs[rd + 1]);
3273 }
3274 } else {
54a3c0f0
IK		 3275 env->regwptr[rd] = ldq_nucleus(addr);
3276 env->regwptr[rd + 1] = ldq_nucleus(addr + 8);
db166940
BS		 3277 if (asi == 0x2c) {
3278 bswap64s(&env->regwptr[rd]);
3279 bswap64s(&env->regwptr[rd + 1]);
3280 }
3281 }
3282 break;
03ae77d6 3283#endif
db166940
BS		 3284 default:
3285 helper_check_align(addr, 0x3);
3286 if (rd == 0)
3287 env->gregs[1] = helper_ld_asi(addr + 4, asi, 4, 0);
3288 else if (rd < 8) {
3289 env->gregs[rd] = helper_ld_asi(addr, asi, 4, 0);
3290 env->gregs[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
3291 } else {
3292 env->regwptr[rd] = helper_ld_asi(addr, asi, 4, 0);
3293 env->regwptr[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
3294 }
3295 break;
3296 }
3297}
3298
1a2fb1c0 3299void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
3391c818 3300{
3391c818 3301 unsigned int i;
1a2fb1c0 3302 target_ulong val;
3391c818 3303
c2bc0e38 3304 helper_check_align(addr, 3);
1295001c
IK		 3305 addr = asi_address_mask(env, asi, addr);
3306
3391c818
BS		 3307 switch (asi) {
3308 case 0xf0: // Block load primary
3309 case 0xf1: // Block load secondary
3310 case 0xf8: // Block load primary LE
3311 case 0xf9: // Block load secondary LE
51996525
BS		 3312 if (rd & 7) {
3313 raise_exception(TT_ILL_INSN);
3314 return;
3315 }
c2bc0e38 3316 helper_check_align(addr, 0x3f);
51996525 3317 for (i = 0; i < 16; i++) {
77f193da
BS		 3318 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4,
3319 0);
1a2fb1c0 3320 addr += 4;
3391c818 3321 }
3391c818 3322
0e2fa9ca
IK		 3323 return;
3324 case 0x70: // Block load primary, user privilege
3325 case 0x71: // Block load secondary, user privilege
3326 if (rd & 7) {
3327 raise_exception(TT_ILL_INSN);
3328 return;
3329 }
3330 helper_check_align(addr, 0x3f);
3331 for (i = 0; i < 16; i++) {
3332 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x1f, 4,
3333 0);
3334 addr += 4;
3335 }
3336
3391c818
BS		 3337 return;
3338 default:
3339 break;
3340 }
3341
1a2fb1c0 3342 val = helper_ld_asi(addr, asi, size, 0);
3391c818
BS		 3343 switch(size) {
3344 default:
3345 case 4:
714547bb 3346 *((uint32_t *)&env->fpr[rd]) = val;
3391c818
BS		 3347 break;
3348 case 8:
1a2fb1c0 3349 *((int64_t *)&DT0) = val;
3391c818 3350 break;
1f587329
BS		 3351 case 16:
3352 // XXX
3353 break;
3391c818 3354 }
3391c818
BS		 3355}
3356
1a2fb1c0 3357void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
3391c818 3358{
3391c818 3359 unsigned int i;
1a2fb1c0 3360 target_ulong val = 0;
3391c818 3361
c2bc0e38 3362 helper_check_align(addr, 3);
1295001c
IK		 3363 addr = asi_address_mask(env, asi, addr);
3364
3391c818 3365 switch (asi) {
c99657d3
BS		 3366 case 0xe0: // UA2007 Block commit store primary (cache flush)
3367 case 0xe1: // UA2007 Block commit store secondary (cache flush)
3391c818
BS		 3368 case 0xf0: // Block store primary
3369 case 0xf1: // Block store secondary
3370 case 0xf8: // Block store primary LE
3371 case 0xf9: // Block store secondary LE
51996525
BS		 3372 if (rd & 7) {
3373 raise_exception(TT_ILL_INSN);
3374 return;
3375 }
c2bc0e38 3376 helper_check_align(addr, 0x3f);
51996525 3377 for (i = 0; i < 16; i++) {
1a2fb1c0
BS		 3378 val = *(uint32_t *)&env->fpr[rd++];
3379 helper_st_asi(addr, val, asi & 0x8f, 4);
3380 addr += 4;
3391c818 3381 }
3391c818 3382
0e2fa9ca
IK		 3383 return;
3384 case 0x70: // Block store primary, user privilege
3385 case 0x71: // Block store secondary, user privilege
3386 if (rd & 7) {
3387 raise_exception(TT_ILL_INSN);
3388 return;
3389 }
3390 helper_check_align(addr, 0x3f);
3391 for (i = 0; i < 16; i++) {
3392 val = *(uint32_t *)&env->fpr[rd++];
3393 helper_st_asi(addr, val, asi & 0x1f, 4);
3394 addr += 4;
3395 }
3396
3391c818
BS		 3397 return;
3398 default:
3399 break;
3400 }
3401
3402 switch(size) {
3403 default:
3404 case 4:
714547bb 3405 val = *((uint32_t *)&env->fpr[rd]);
3391c818
BS		 3406 break;
3407 case 8:
1a2fb1c0 3408 val = *((int64_t *)&DT0);
3391c818 3409 break;
1f587329
BS		 3410 case 16:
3411 // XXX
3412 break;
3391c818 3413 }
1a2fb1c0
BS		 3414 helper_st_asi(addr, val, asi, size);
3415}
3416
3417target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
3418 target_ulong val2, uint32_t asi)
3419{
3420 target_ulong ret;
3421
1121f879 3422 val2 &= 0xffffffffUL;
1a2fb1c0
BS		 3423 ret = helper_ld_asi(addr, asi, 4, 0);
3424 ret &= 0xffffffffUL;
1121f879
BS		 3425 if (val2 == ret)
3426 helper_st_asi(addr, val1 & 0xffffffffUL, asi, 4);
1a2fb1c0 3427 return ret;
3391c818
BS		 3428}
3429
1a2fb1c0
BS		 3430target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
3431 target_ulong val2, uint32_t asi)
3432{
3433 target_ulong ret;
3434
3435 ret = helper_ld_asi(addr, asi, 8, 0);
1121f879
BS		 3436 if (val2 == ret)
3437 helper_st_asi(addr, val1, asi, 8);
1a2fb1c0
BS		 3438 return ret;
3439}
81ad8ba2 3440#endif /* TARGET_SPARC64 */
3475187d
FB		 3441
3442#ifndef TARGET_SPARC64
1a2fb1c0 3443void helper_rett(void)
e8af50a3 3444{
af7bf89b
FB		 3445 unsigned int cwp;
3446
d4218d99
BS		 3447 if (env->psret == 1)
3448 raise_exception(TT_ILL_INSN);
3449
e8af50a3 3450 env->psret = 1;
5a834bb4 3451 cwp = cwp_inc(env->cwp + 1) ;
e8af50a3
FB		 3452 if (env->wim & (1 << cwp)) {
3453 raise_exception(TT_WIN_UNF);
3454 }
3455 set_cwp(cwp);
3456 env->psrs = env->psrps;
3457}
3475187d 3458#endif
e8af50a3 3459
0fcec41e 3460static target_ulong helper_udiv_common(target_ulong a, target_ulong b, int cc)
3b89f26c 3461{
0fcec41e 3462 int overflow = 0;
3b89f26c
BS		 3463 uint64_t x0;
3464 uint32_t x1;
3465
7621a90d 3466 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
09487205 3467 x1 = (b & 0xffffffff);
3b89f26c
BS		 3468
3469 if (x1 == 0) {
3470 raise_exception(TT_DIV_ZERO);
3471 }
3472
3473 x0 = x0 / x1;
3474 if (x0 > 0xffffffff) {
0fcec41e
AJ		 3475 x0 = 0xffffffff;
3476 overflow = 1;
3477 }
3478
3479 if (cc) {
3480 env->cc_dst = x0;
3481 env->cc_src2 = overflow;
3482 env->cc_op = CC_OP_DIV;
3b89f26c 3483 }
0fcec41e 3484 return x0;
3b89f26c
BS		 3485}
3486
0fcec41e
AJ		 3487target_ulong helper_udiv(target_ulong a, target_ulong b)
3488{
3489 return helper_udiv_common(a, b, 0);
3490}
3491
3492target_ulong helper_udiv_cc(target_ulong a, target_ulong b)
3493{
3494 return helper_udiv_common(a, b, 1);
3495}
3496
3497static target_ulong helper_sdiv_common(target_ulong a, target_ulong b, int cc)
3b89f26c 3498{
0fcec41e 3499 int overflow = 0;
3b89f26c
BS		 3500 int64_t x0;
3501 int32_t x1;
3502
7621a90d 3503 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
09487205 3504 x1 = (b & 0xffffffff);
3b89f26c
BS		 3505
3506 if (x1 == 0) {
3507 raise_exception(TT_DIV_ZERO);
3508 }
3509
3510 x0 = x0 / x1;
3511 if ((int32_t) x0 != x0) {
0fcec41e
AJ		 3512 x0 = x0 < 0 ? 0x80000000: 0x7fffffff;
3513 overflow = 1;
3514 }
3515
3516 if (cc) {
3517 env->cc_dst = x0;
3518 env->cc_src2 = overflow;
3519 env->cc_op = CC_OP_DIV;
3b89f26c 3520 }
0fcec41e
AJ		 3521 return x0;
3522}
3523
3524target_ulong helper_sdiv(target_ulong a, target_ulong b)
3525{
3526 return helper_sdiv_common(a, b, 0);
3527}
3528
3529target_ulong helper_sdiv_cc(target_ulong a, target_ulong b)
3530{
3531 return helper_sdiv_common(a, b, 1);
3b89f26c
BS		 3532}
3533
7fa76c0b
BS		 3534void helper_stdf(target_ulong addr, int mem_idx)
3535{
c2bc0e38 3536 helper_check_align(addr, 7);
7fa76c0b
BS		 3537#if !defined(CONFIG_USER_ONLY)
3538 switch (mem_idx) {
b219094a 3539 case MMU_USER_IDX:
c2bc0e38 3540 stfq_user(addr, DT0);
7fa76c0b 3541 break;
b219094a 3542 case MMU_KERNEL_IDX:
c2bc0e38 3543 stfq_kernel(addr, DT0);
7fa76c0b
BS		 3544 break;
3545#ifdef TARGET_SPARC64
b219094a 3546 case MMU_HYPV_IDX:
c2bc0e38 3547 stfq_hypv(addr, DT0);
7fa76c0b
BS		 3548 break;
3549#endif
3550 default:
b219094a 3551 DPRINTF_MMU("helper_stdf: need to check MMU idx %d\n", mem_idx);
7fa76c0b
BS		 3552 break;
3553 }
3554#else
41db525e 3555 stfq_raw(address_mask(env, addr), DT0);
7fa76c0b
BS		 3556#endif
3557}
3558
3559void helper_lddf(target_ulong addr, int mem_idx)
3560{
c2bc0e38 3561 helper_check_align(addr, 7);
7fa76c0b
BS		 3562#if !defined(CONFIG_USER_ONLY)
3563 switch (mem_idx) {
b219094a 3564 case MMU_USER_IDX:
c2bc0e38 3565 DT0 = ldfq_user(addr);
7fa76c0b 3566 break;
b219094a 3567 case MMU_KERNEL_IDX:
c2bc0e38 3568 DT0 = ldfq_kernel(addr);
7fa76c0b
BS		 3569 break;
3570#ifdef TARGET_SPARC64
b219094a 3571 case MMU_HYPV_IDX:
c2bc0e38 3572 DT0 = ldfq_hypv(addr);
7fa76c0b
BS		 3573 break;
3574#endif
3575 default:
b219094a 3576 DPRINTF_MMU("helper_lddf: need to check MMU idx %d\n", mem_idx);
7fa76c0b
BS		 3577 break;
3578 }
3579#else
41db525e 3580 DT0 = ldfq_raw(address_mask(env, addr));
7fa76c0b
BS		 3581#endif
3582}
3583
64a88d5d 3584void helper_ldqf(target_ulong addr, int mem_idx)
7fa76c0b
BS		 3585{
3586 // XXX add 128 bit load
3587 CPU_QuadU u;
3588
c2bc0e38 3589 helper_check_align(addr, 7);
64a88d5d
BS		 3590#if !defined(CONFIG_USER_ONLY)
3591 switch (mem_idx) {
b219094a 3592 case MMU_USER_IDX:
c2bc0e38
BS		 3593 u.ll.upper = ldq_user(addr);
3594 u.ll.lower = ldq_user(addr + 8);
64a88d5d
BS		 3595 QT0 = u.q;
3596 break;
b219094a 3597 case MMU_KERNEL_IDX:
c2bc0e38
BS		 3598 u.ll.upper = ldq_kernel(addr);
3599 u.ll.lower = ldq_kernel(addr + 8);
64a88d5d
BS		 3600 QT0 = u.q;
3601 break;
3602#ifdef TARGET_SPARC64
b219094a 3603 case MMU_HYPV_IDX:
c2bc0e38
BS		 3604 u.ll.upper = ldq_hypv(addr);
3605 u.ll.lower = ldq_hypv(addr + 8);
64a88d5d
BS		 3606 QT0 = u.q;
3607 break;
3608#endif
3609 default:
b219094a 3610 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx);
64a88d5d
BS		 3611 break;
3612 }
3613#else
41db525e
RH		 3614 u.ll.upper = ldq_raw(address_mask(env, addr));
3615 u.ll.lower = ldq_raw(address_mask(env, addr + 8));
7fa76c0b 3616 QT0 = u.q;
64a88d5d 3617#endif
7fa76c0b
BS		 3618}
3619
64a88d5d 3620void helper_stqf(target_ulong addr, int mem_idx)
7fa76c0b
BS		 3621{
3622 // XXX add 128 bit store
3623 CPU_QuadU u;
3624
c2bc0e38 3625 helper_check_align(addr, 7);
64a88d5d
BS		 3626#if !defined(CONFIG_USER_ONLY)
3627 switch (mem_idx) {
b219094a 3628 case MMU_USER_IDX:
64a88d5d 3629 u.q = QT0;
c2bc0e38
BS		 3630 stq_user(addr, u.ll.upper);
3631 stq_user(addr + 8, u.ll.lower);
64a88d5d 3632 break;
b219094a 3633 case MMU_KERNEL_IDX:
64a88d5d 3634 u.q = QT0;
c2bc0e38
BS		 3635 stq_kernel(addr, u.ll.upper);
3636 stq_kernel(addr + 8, u.ll.lower);
64a88d5d
BS		 3637 break;
3638#ifdef TARGET_SPARC64
b219094a 3639 case MMU_HYPV_IDX:
64a88d5d 3640 u.q = QT0;
c2bc0e38
BS		 3641 stq_hypv(addr, u.ll.upper);
3642 stq_hypv(addr + 8, u.ll.lower);
64a88d5d
BS		 3643 break;
3644#endif
3645 default:
b219094a 3646 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx);
64a88d5d
BS		 3647 break;
3648 }
3649#else
7fa76c0b 3650 u.q = QT0;
41db525e
RH		 3651 stq_raw(address_mask(env, addr), u.ll.upper);
3652 stq_raw(address_mask(env, addr + 8), u.ll.lower);
7fa76c0b 3653#endif
64a88d5d 3654}
7fa76c0b 3655
3a3b925d 3656static inline void set_fsr(void)
e8af50a3 3657{
7a0e1f41 3658 int rnd_mode;
bb5529bb 3659
e8af50a3
FB		 3660 switch (env->fsr & FSR_RD_MASK) {
3661 case FSR_RD_NEAREST:
7a0e1f41 3662 rnd_mode = float_round_nearest_even;
0f8a249a 3663 break;
ed910241 3664 default:
e8af50a3 3665 case FSR_RD_ZERO:
7a0e1f41 3666 rnd_mode = float_round_to_zero;
0f8a249a 3667 break;
e8af50a3 3668 case FSR_RD_POS:
7a0e1f41 3669 rnd_mode = float_round_up;
0f8a249a 3670 break;
e8af50a3 3671 case FSR_RD_NEG:
7a0e1f41 3672 rnd_mode = float_round_down;
0f8a249a 3673 break;
e8af50a3 3674 }
7a0e1f41 3675 set_float_rounding_mode(rnd_mode, &env->fp_status);
e8af50a3 3676}
e80cfcfc 3677
3a3b925d 3678void helper_ldfsr(uint32_t new_fsr)
bb5529bb 3679{
3a3b925d
BS		 3680 env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK);
3681 set_fsr();
bb5529bb
BS		 3682}
3683
3a3b925d
BS		 3684#ifdef TARGET_SPARC64
3685void helper_ldxfsr(uint64_t new_fsr)
3686{
3687 env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK);
3688 set_fsr();
3689}
3690#endif
3691
bb5529bb 3692void helper_debug(void)
e80cfcfc
FB		 3693{
3694 env->exception_index = EXCP_DEBUG;
3695 cpu_loop_exit();
3696}
af7bf89b 3697
3475187d 3698#ifndef TARGET_SPARC64
72a9747b
BS		 3699/* XXX: use another pointer for %iN registers to avoid slow wrapping
3700 handling ? */
3701void helper_save(void)
3702{
3703 uint32_t cwp;
3704
5a834bb4 3705 cwp = cwp_dec(env->cwp - 1);
72a9747b
BS		 3706 if (env->wim & (1 << cwp)) {
3707 raise_exception(TT_WIN_OVF);
3708 }
3709 set_cwp(cwp);
3710}
3711
3712void helper_restore(void)
3713{
3714 uint32_t cwp;
3715
5a834bb4 3716 cwp = cwp_inc(env->cwp + 1);
72a9747b
BS		 3717 if (env->wim & (1 << cwp)) {
3718 raise_exception(TT_WIN_UNF);
3719 }
3720 set_cwp(cwp);
3721}
3722
1a2fb1c0 3723void helper_wrpsr(target_ulong new_psr)
af7bf89b 3724{
5a834bb4 3725 if ((new_psr & PSR_CWP) >= env->nwindows) {
d4218d99 3726 raise_exception(TT_ILL_INSN);
5a834bb4
BS		 3727 } else {
3728 cpu_put_psr(env, new_psr);
3729 }
af7bf89b
FB		 3730}
3731
1a2fb1c0 3732target_ulong helper_rdpsr(void)
af7bf89b 3733{
5a834bb4 3734 return get_psr();
af7bf89b 3735}
3475187d
FB		 3736
3737#else
72a9747b
BS		 3738/* XXX: use another pointer for %iN registers to avoid slow wrapping
3739 handling ? */
3740void helper_save(void)
3741{
3742 uint32_t cwp;
3743
5a834bb4 3744 cwp = cwp_dec(env->cwp - 1);
72a9747b
BS		 3745 if (env->cansave == 0) {
3746 raise_exception(TT_SPILL | (env->otherwin != 0 ?
3747 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
3748 ((env->wstate & 0x7) << 2)));
3749 } else {
3750 if (env->cleanwin - env->canrestore == 0) {
3751 // XXX Clean windows without trap
3752 raise_exception(TT_CLRWIN);
3753 } else {
3754 env->cansave--;
3755 env->canrestore++;
3756 set_cwp(cwp);
3757 }
3758 }
3759}
3760
3761void helper_restore(void)
3762{
3763 uint32_t cwp;
3764
5a834bb4 3765 cwp = cwp_inc(env->cwp + 1);
72a9747b
BS		 3766 if (env->canrestore == 0) {
3767 raise_exception(TT_FILL | (env->otherwin != 0 ?
3768 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
3769 ((env->wstate & 0x7) << 2)));
3770 } else {
3771 env->cansave++;
3772 env->canrestore--;
3773 set_cwp(cwp);
3774 }
3775}
3776
3777void helper_flushw(void)
3778{
1a14026e 3779 if (env->cansave != env->nwindows - 2) {
72a9747b
BS		 3780 raise_exception(TT_SPILL | (env->otherwin != 0 ?
3781 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
3782 ((env->wstate & 0x7) << 2)));
3783 }
3784}
3785
3786void helper_saved(void)
3787{
3788 env->cansave++;
3789 if (env->otherwin == 0)
3790 env->canrestore--;
3791 else
3792 env->otherwin--;
3793}
3794
3795void helper_restored(void)
3796{
3797 env->canrestore++;
1a14026e 3798 if (env->cleanwin < env->nwindows - 1)
72a9747b
BS		 3799 env->cleanwin++;
3800 if (env->otherwin == 0)
3801 env->cansave--;
3802 else
3803 env->otherwin--;
3804}
3805
5a834bb4
BS		 3806static target_ulong get_ccr(void)
3807{
3808 target_ulong psr;
3809
3810 psr = get_psr();
3811
3812 return ((env->xcc >> 20) << 4) | ((psr & PSR_ICC) >> 20);
3813}
3814
3815target_ulong cpu_get_ccr(CPUState *env1)
3816{
3817 CPUState *saved_env;
3818 target_ulong ret;
3819
3820 saved_env = env;
3821 env = env1;
3822 ret = get_ccr();
3823 env = saved_env;
3824 return ret;
3825}
3826
3827static void put_ccr(target_ulong val)
3828{
3829 target_ulong tmp = val;
3830
3831 env->xcc = (tmp >> 4) << 20;
3832 env->psr = (tmp & 0xf) << 20;
3833 CC_OP = CC_OP_FLAGS;
3834}
3835
3836void cpu_put_ccr(CPUState *env1, target_ulong val)
3837{
3838 CPUState *saved_env;
3839
3840 saved_env = env;
3841 env = env1;
3842 put_ccr(val);
3843 env = saved_env;
3844}
3845
3846static target_ulong get_cwp64(void)
3847{
3848 return env->nwindows - 1 - env->cwp;
3849}
3850
3851target_ulong cpu_get_cwp64(CPUState *env1)
3852{
3853 CPUState *saved_env;
3854 target_ulong ret;
3855
3856 saved_env = env;
3857 env = env1;
3858 ret = get_cwp64();
3859 env = saved_env;
3860 return ret;
3861}
3862
3863static void put_cwp64(int cwp)
3864{
3865 if (unlikely(cwp >= env->nwindows || cwp < 0)) {
3866 cwp %= env->nwindows;
3867 }
3868 set_cwp(env->nwindows - 1 - cwp);
3869}
3870
3871void cpu_put_cwp64(CPUState *env1, int cwp)
3872{
3873 CPUState *saved_env;
3874
3875 saved_env = env;
3876 env = env1;
3877 put_cwp64(cwp);
3878 env = saved_env;
3879}
3880
d35527d9
BS		 3881target_ulong helper_rdccr(void)
3882{
5a834bb4 3883 return get_ccr();
d35527d9
BS		 3884}
3885
3886void helper_wrccr(target_ulong new_ccr)
3887{
5a834bb4 3888 put_ccr(new_ccr);
d35527d9
BS		 3889}
3890
3891// CWP handling is reversed in V9, but we still use the V8 register
3892// order.
3893target_ulong helper_rdcwp(void)
3894{
5a834bb4 3895 return get_cwp64();
d35527d9
BS		 3896}
3897
3898void helper_wrcwp(target_ulong new_cwp)
3899{
5a834bb4 3900 put_cwp64(new_cwp);
d35527d9 3901}
3475187d 3902
1f5063fb
BS		 3903// This function uses non-native bit order
3904#define GET_FIELD(X, FROM, TO) \
3905 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
3906
3907// This function uses the order in the manuals, i.e. bit 0 is 2^0
3908#define GET_FIELD_SP(X, FROM, TO) \
3909 GET_FIELD(X, 63 - (TO), 63 - (FROM))
3910
3911target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
3912{
3913 return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
3914 (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
3915 (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) |
3916 (GET_FIELD_SP(pixel_addr, 56, 59) << 13) |
3917 (GET_FIELD_SP(pixel_addr, 35, 38) << 9) |
3918 (GET_FIELD_SP(pixel_addr, 13, 16) << 5) |
3919 (((pixel_addr >> 55) & 1) << 4) |
3920 (GET_FIELD_SP(pixel_addr, 33, 34) << 2) |
3921 GET_FIELD_SP(pixel_addr, 11, 12);
3922}
3923
3924target_ulong helper_alignaddr(target_ulong addr, target_ulong offset)
3925{
3926 uint64_t tmp;
3927
3928 tmp = addr + offset;
3929 env->gsr &= ~7ULL;
3930 env->gsr |= tmp & 7ULL;
3931 return tmp & ~7ULL;
3932}
3933
1a2fb1c0 3934target_ulong helper_popc(target_ulong val)
3475187d 3935{
1a2fb1c0 3936 return ctpop64(val);
3475187d 3937}
83469015 3938
d780a466 3939static inline uint64_t *get_gregset(uint32_t pstate)
83469015
FB		 3940{
3941 switch (pstate) {
3942 default:
7e8695ed
IK		 3943 DPRINTF_PSTATE("ERROR in get_gregset: active pstate bits=%x%s%s%s\n",
3944 pstate,
3945 (pstate & PS_IG) ? " IG" : "",
3946 (pstate & PS_MG) ? " MG" : "",
3947 (pstate & PS_AG) ? " AG" : "");
3948 /* pass through to normal set of global registers */
83469015 3949 case 0:
0f8a249a 3950 return env->bgregs;
83469015 3951 case PS_AG:
0f8a249a 3952 return env->agregs;
83469015 3953 case PS_MG:
0f8a249a 3954 return env->mgregs;
83469015 3955 case PS_IG:
0f8a249a 3956 return env->igregs;
83469015
FB		 3957 }
3958}
3959
d780a466 3960static inline void change_pstate(uint32_t new_pstate)
83469015 3961{
d780a466 3962 uint32_t pstate_regs, new_pstate_regs;
83469015
FB		 3963 uint64_t *src, *dst;
3964
5210977a
IK		 3965 if (env->def->features & CPU_FEATURE_GL) {
3966 // PS_AG is not implemented in this case
3967 new_pstate &= ~PS_AG;
3968 }
3969
83469015
FB		 3970 pstate_regs = env->pstate & 0xc01;
3971 new_pstate_regs = new_pstate & 0xc01;
5210977a 3972
83469015 3973 if (new_pstate_regs != pstate_regs) {
7e8695ed
IK		 3974 DPRINTF_PSTATE("change_pstate: switching regs old=%x new=%x\n",
3975 pstate_regs, new_pstate_regs);
0f8a249a
BS		 3976 // Switch global register bank
3977 src = get_gregset(new_pstate_regs);
3978 dst = get_gregset(pstate_regs);
3979 memcpy32(dst, env->gregs);
3980 memcpy32(env->gregs, src);
83469015 3981 }
7e8695ed
IK		 3982 else {
3983 DPRINTF_PSTATE("change_pstate: regs new=%x (unchanged)\n",
3984 new_pstate_regs);
3985 }
83469015
FB		 3986 env->pstate = new_pstate;
3987}
3988
1a2fb1c0 3989void helper_wrpstate(target_ulong new_state)
8f1f22f6 3990{
5210977a 3991 change_pstate(new_state & 0xf3f);
4dc28134
IK		 3992
3993#if !defined(CONFIG_USER_ONLY)
3994 if (cpu_interrupts_enabled(env)) {
3995 cpu_check_irqs(env);
3996 }
3997#endif
8f1f22f6
BS		 3998}
3999
1fae7b70
IK		 4000void helper_wrpil(target_ulong new_pil)
4001{
4002#if !defined(CONFIG_USER_ONLY)
4003 DPRINTF_PSTATE("helper_wrpil old=%x new=%x\n",
4004 env->psrpil, (uint32_t)new_pil);
4005
4006 env->psrpil = new_pil;
4007
4008 if (cpu_interrupts_enabled(env)) {
4009 cpu_check_irqs(env);
4010 }
4011#endif
4012}
4013
1a2fb1c0 4014void helper_done(void)
83469015 4015{
8194f35a
IK		 4016 trap_state* tsptr = cpu_tsptr(env);
4017
3723cd09 4018 env->pc = tsptr->tnpc;
8194f35a 4019 env->npc = tsptr->tnpc + 4;
5a834bb4 4020 put_ccr(tsptr->tstate >> 32);
8194f35a
IK		 4021 env->asi = (tsptr->tstate >> 24) & 0xff;
4022 change_pstate((tsptr->tstate >> 8) & 0xf3f);
5a834bb4 4023 put_cwp64(tsptr->tstate & 0xff);
e6bf7d70 4024 env->tl--;
4dc28134
IK		 4025
4026 DPRINTF_PSTATE("... helper_done tl=%d\n", env->tl);
4027
4028#if !defined(CONFIG_USER_ONLY)
4029 if (cpu_interrupts_enabled(env)) {
4030 cpu_check_irqs(env);
4031 }
4032#endif
83469015
FB		 4033}
4034
1a2fb1c0 4035void helper_retry(void)
83469015 4036{
8194f35a
IK		 4037 trap_state* tsptr = cpu_tsptr(env);
4038
4039 env->pc = tsptr->tpc;
4040 env->npc = tsptr->tnpc;
5a834bb4 4041 put_ccr(tsptr->tstate >> 32);
8194f35a
IK		 4042 env->asi = (tsptr->tstate >> 24) & 0xff;
4043 change_pstate((tsptr->tstate >> 8) & 0xf3f);
5a834bb4 4044 put_cwp64(tsptr->tstate & 0xff);
e6bf7d70 4045 env->tl--;
4dc28134
IK		 4046
4047 DPRINTF_PSTATE("... helper_retry tl=%d\n", env->tl);
4048
4049#if !defined(CONFIG_USER_ONLY)
4050 if (cpu_interrupts_enabled(env)) {
4051 cpu_check_irqs(env);
4052 }
4053#endif
4054}
4055
4056static void do_modify_softint(const char* operation, uint32_t value)
4057{
4058 if (env->softint != value) {
4059 env->softint = value;
4060 DPRINTF_PSTATE(": %s new %08x\n", operation, env->softint);
4061#if !defined(CONFIG_USER_ONLY)
4062 if (cpu_interrupts_enabled(env)) {
4063 cpu_check_irqs(env);
4064 }
4065#endif
4066 }
83469015 4067}
9d926598
BS		 4068
4069void helper_set_softint(uint64_t value)
4070{
4dc28134 4071 do_modify_softint("helper_set_softint", env->softint | (uint32_t)value);
9d926598
BS		 4072}
4073
4074void helper_clear_softint(uint64_t value)
4075{
4dc28134 4076 do_modify_softint("helper_clear_softint", env->softint & (uint32_t)~value);
9d926598
BS		 4077}
4078
4079void helper_write_softint(uint64_t value)
4080{
4dc28134 4081 do_modify_softint("helper_write_softint", (uint32_t)value);
9d926598 4082}
3475187d 4083#endif
ee5bbe38 4084
91736d37 4085void helper_flush(target_ulong addr)
ee5bbe38 4086{
91736d37
BS		 4087 addr &= ~7;
4088 tb_invalidate_page_range(addr, addr + 8);
ee5bbe38
FB		 4089}
4090
91736d37
BS		 4091#ifdef TARGET_SPARC64
4092#ifdef DEBUG_PCALL
4093static const char * const excp_names[0x80] = {
4094 [TT_TFAULT] = "Instruction Access Fault",
4095 [TT_TMISS] = "Instruction Access MMU Miss",
4096 [TT_CODE_ACCESS] = "Instruction Access Error",
4097 [TT_ILL_INSN] = "Illegal Instruction",
4098 [TT_PRIV_INSN] = "Privileged Instruction",
4099 [TT_NFPU_INSN] = "FPU Disabled",
4100 [TT_FP_EXCP] = "FPU Exception",
4101 [TT_TOVF] = "Tag Overflow",
4102 [TT_CLRWIN] = "Clean Windows",
4103 [TT_DIV_ZERO] = "Division By Zero",
4104 [TT_DFAULT] = "Data Access Fault",
4105 [TT_DMISS] = "Data Access MMU Miss",
4106 [TT_DATA_ACCESS] = "Data Access Error",
4107 [TT_DPROT] = "Data Protection Error",
4108 [TT_UNALIGNED] = "Unaligned Memory Access",
4109 [TT_PRIV_ACT] = "Privileged Action",
4110 [TT_EXTINT | 0x1] = "External Interrupt 1",
4111 [TT_EXTINT | 0x2] = "External Interrupt 2",
4112 [TT_EXTINT | 0x3] = "External Interrupt 3",
4113 [TT_EXTINT | 0x4] = "External Interrupt 4",
4114 [TT_EXTINT | 0x5] = "External Interrupt 5",
4115 [TT_EXTINT | 0x6] = "External Interrupt 6",
4116 [TT_EXTINT | 0x7] = "External Interrupt 7",
4117 [TT_EXTINT | 0x8] = "External Interrupt 8",
4118 [TT_EXTINT | 0x9] = "External Interrupt 9",
4119 [TT_EXTINT | 0xa] = "External Interrupt 10",
4120 [TT_EXTINT | 0xb] = "External Interrupt 11",
4121 [TT_EXTINT | 0xc] = "External Interrupt 12",
4122 [TT_EXTINT | 0xd] = "External Interrupt 13",
4123 [TT_EXTINT | 0xe] = "External Interrupt 14",
4124 [TT_EXTINT | 0xf] = "External Interrupt 15",
4125};
4126#endif
4127
8194f35a
IK		 4128trap_state* cpu_tsptr(CPUState* env)
4129{
4130 return &env->ts[env->tl & MAXTL_MASK];
4131}
4132
91736d37
BS		 4133void do_interrupt(CPUState *env)
4134{
4135 int intno = env->exception_index;
8194f35a 4136 trap_state* tsptr;
91736d37
BS		 4137
4138#ifdef DEBUG_PCALL
8fec2b8c 4139 if (qemu_loglevel_mask(CPU_LOG_INT)) {
91736d37
BS		 4140 static int count;
4141 const char *name;
4142
4143 if (intno < 0 || intno >= 0x180)
4144 name = "Unknown";
4145 else if (intno >= 0x100)
4146 name = "Trap Instruction";
4147 else if (intno >= 0xc0)
4148 name = "Window Fill";
4149 else if (intno >= 0x80)
4150 name = "Window Spill";
4151 else {
4152 name = excp_names[intno];
4153 if (!name)
4154 name = "Unknown";
4155 }
4156
93fcfe39 4157 qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
91736d37
BS		 4158 " SP=%016" PRIx64 "\n",
4159 count, name, intno,
4160 env->pc,
4161 env->npc, env->regwptr[6]);
93fcfe39 4162 log_cpu_state(env, 0);
91736d37
BS		 4163#if 0
4164 {
4165 int i;
4166 uint8_t *ptr;
4167
93fcfe39 4168 qemu_log(" code=");
91736d37
BS		 4169 ptr = (uint8_t *)env->pc;
4170 for(i = 0; i < 16; i++) {
93fcfe39 4171 qemu_log(" %02x", ldub(ptr + i));
91736d37 4172 }
93fcfe39 4173 qemu_log("\n");
91736d37
BS		 4174 }
4175#endif
4176 count++;
4177 }
4178#endif
4179#if !defined(CONFIG_USER_ONLY)
4180 if (env->tl >= env->maxtl) {
4181 cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
4182 " Error state", env->exception_index, env->tl, env->maxtl);
4183 return;
4184 }
4185#endif
4186 if (env->tl < env->maxtl - 1) {
4187 env->tl++;
4188 } else {
4189 env->pstate |= PS_RED;
4190 if (env->tl < env->maxtl)
4191 env->tl++;
4192 }
8194f35a
IK		 4193 tsptr = cpu_tsptr(env);
4194
5a834bb4 4195 tsptr->tstate = (get_ccr() << 32) |
91736d37 4196 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
5a834bb4 4197 get_cwp64();
8194f35a
IK		 4198 tsptr->tpc = env->pc;
4199 tsptr->tnpc = env->npc;
4200 tsptr->tt = intno;
5210977a
IK		 4201
4202 switch (intno) {
4203 case TT_IVEC:
4204 change_pstate(PS_PEF | PS_PRIV | PS_IG);
4205 break;
4206 case TT_TFAULT:
5210977a 4207 case TT_DFAULT:
87f6d3f6
IK		 4208 case TT_TMISS ... TT_TMISS + 3:
4209 case TT_DMISS ... TT_DMISS + 3:
4210 case TT_DPROT ... TT_DPROT + 3:
5210977a
IK		 4211 change_pstate(PS_PEF | PS_PRIV | PS_MG);
4212 break;
4213 default:
4214 change_pstate(PS_PEF | PS_PRIV | PS_AG);
4215 break;
91736d37 4216 }
5210977a 4217
5a834bb4
BS		 4218 if (intno == TT_CLRWIN) {
4219 set_cwp(cwp_dec(env->cwp - 1));
4220 } else if ((intno & 0x1c0) == TT_SPILL) {
4221 set_cwp(cwp_dec(env->cwp - env->cansave - 2));
4222 } else if ((intno & 0x1c0) == TT_FILL) {
4223 set_cwp(cwp_inc(env->cwp + 1));
4224 }
91736d37
BS		 4225 env->tbr &= ~0x7fffULL;
4226 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
4227 env->pc = env->tbr;
4228 env->npc = env->pc + 4;
821b19fe 4229 env->exception_index = -1;
ee5bbe38 4230}
91736d37
BS		 4231#else
4232#ifdef DEBUG_PCALL
4233static const char * const excp_names[0x80] = {
4234 [TT_TFAULT] = "Instruction Access Fault",
4235 [TT_ILL_INSN] = "Illegal Instruction",
4236 [TT_PRIV_INSN] = "Privileged Instruction",
4237 [TT_NFPU_INSN] = "FPU Disabled",
4238 [TT_WIN_OVF] = "Window Overflow",
4239 [TT_WIN_UNF] = "Window Underflow",
4240 [TT_UNALIGNED] = "Unaligned Memory Access",
4241 [TT_FP_EXCP] = "FPU Exception",
4242 [TT_DFAULT] = "Data Access Fault",
4243 [TT_TOVF] = "Tag Overflow",
4244 [TT_EXTINT | 0x1] = "External Interrupt 1",
4245 [TT_EXTINT | 0x2] = "External Interrupt 2",
4246 [TT_EXTINT | 0x3] = "External Interrupt 3",
4247 [TT_EXTINT | 0x4] = "External Interrupt 4",
4248 [TT_EXTINT | 0x5] = "External Interrupt 5",
4249 [TT_EXTINT | 0x6] = "External Interrupt 6",
4250 [TT_EXTINT | 0x7] = "External Interrupt 7",
4251 [TT_EXTINT | 0x8] = "External Interrupt 8",
4252 [TT_EXTINT | 0x9] = "External Interrupt 9",
4253 [TT_EXTINT | 0xa] = "External Interrupt 10",
4254 [TT_EXTINT | 0xb] = "External Interrupt 11",
4255 [TT_EXTINT | 0xc] = "External Interrupt 12",
4256 [TT_EXTINT | 0xd] = "External Interrupt 13",
4257 [TT_EXTINT | 0xe] = "External Interrupt 14",
4258 [TT_EXTINT | 0xf] = "External Interrupt 15",
4259 [TT_TOVF] = "Tag Overflow",
4260 [TT_CODE_ACCESS] = "Instruction Access Error",
4261 [TT_DATA_ACCESS] = "Data Access Error",
4262 [TT_DIV_ZERO] = "Division By Zero",
4263 [TT_NCP_INSN] = "Coprocessor Disabled",
4264};
4265#endif
ee5bbe38 4266
91736d37 4267void do_interrupt(CPUState *env)
ee5bbe38 4268{
91736d37
BS		 4269 int cwp, intno = env->exception_index;
4270
4271#ifdef DEBUG_PCALL
8fec2b8c 4272 if (qemu_loglevel_mask(CPU_LOG_INT)) {
91736d37
BS		 4273 static int count;
4274 const char *name;
4275
4276 if (intno < 0 || intno >= 0x100)
4277 name = "Unknown";
4278 else if (intno >= 0x80)
4279 name = "Trap Instruction";
4280 else {
4281 name = excp_names[intno];
4282 if (!name)
4283 name = "Unknown";
4284 }
4285
93fcfe39 4286 qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
91736d37
BS		 4287 count, name, intno,
4288 env->pc,
4289 env->npc, env->regwptr[6]);
93fcfe39 4290 log_cpu_state(env, 0);
91736d37
BS		 4291#if 0
4292 {
4293 int i;
4294 uint8_t *ptr;
4295
93fcfe39 4296 qemu_log(" code=");
91736d37
BS		 4297 ptr = (uint8_t *)env->pc;
4298 for(i = 0; i < 16; i++) {
93fcfe39 4299 qemu_log(" %02x", ldub(ptr + i));
91736d37 4300 }
93fcfe39 4301 qemu_log("\n");
91736d37
BS		 4302 }
4303#endif
4304 count++;
4305 }
4306#endif
4307#if !defined(CONFIG_USER_ONLY)
4308 if (env->psret == 0) {
4309 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
4310 env->exception_index);
4311 return;
4312 }
4313#endif
4314 env->psret = 0;
5a834bb4
BS		 4315 cwp = cwp_dec(env->cwp - 1);
4316 set_cwp(cwp);
91736d37
BS		 4317 env->regwptr[9] = env->pc;
4318 env->regwptr[10] = env->npc;
4319 env->psrps = env->psrs;
4320 env->psrs = 1;
4321 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
4322 env->pc = env->tbr;
4323 env->npc = env->pc + 4;
95372a39 4324 env->exception_index = -1;
b04d9890
FC		 4325
4326#if !defined(CONFIG_USER_ONLY)
4327 /* IRQ acknowledgment */
4328 if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) {
4329 env->qemu_irq_ack(env->irq_manager, intno);
4330 }
4331#endif
ee5bbe38 4332}
91736d37 4333#endif
ee5bbe38 4334
5fafdf24 4335#if !defined(CONFIG_USER_ONLY)
ee5bbe38 4336
d2889a3e
BS		 4337static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
4338 void *retaddr);
4339
ee5bbe38 4340#define MMUSUFFIX _mmu
d2889a3e 4341#define ALIGNED_ONLY
ee5bbe38
FB		 4342
4343#define SHIFT 0
4344#include "softmmu_template.h"
4345
4346#define SHIFT 1
4347#include "softmmu_template.h"
4348
4349#define SHIFT 2
4350#include "softmmu_template.h"
4351
4352#define SHIFT 3
4353#include "softmmu_template.h"
4354
c2bc0e38
BS		 4355/* XXX: make it generic ? */
4356static void cpu_restore_state2(void *retaddr)
4357{
4358 TranslationBlock *tb;
4359 unsigned long pc;
4360
4361 if (retaddr) {
4362 /* now we have a real cpu fault */
4363 pc = (unsigned long)retaddr;
4364 tb = tb_find_pc(pc);
4365 if (tb) {
4366 /* the PC is inside the translated code. It means that we have
4367 a virtual CPU fault */
4368 cpu_restore_state(tb, env, pc, (void *)(long)env->cond);
4369 }
4370 }
4371}
4372
d2889a3e
BS		 4373static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
4374 void *retaddr)
4375{
94554550 4376#ifdef DEBUG_UNALIGNED
c2bc0e38
BS		 4377 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
4378 "\n", addr, env->pc);
94554550 4379#endif
c2bc0e38 4380 cpu_restore_state2(retaddr);
94554550 4381 raise_exception(TT_UNALIGNED);
d2889a3e 4382}
ee5bbe38
FB		 4383
4384/* try to fill the TLB and return an exception if error. If retaddr is
4385 NULL, it means that the function was called in C code (i.e. not
4386 from generated code or from helper.c) */
4387/* XXX: fix it to restore all registers */
6ebbf390 4388void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
ee5bbe38 4389{
ee5bbe38 4390 int ret;
ee5bbe38
FB		 4391 CPUState *saved_env;
4392
4393 /* XXX: hack to restore env in all cases, even if not called from
4394 generated code */
4395 saved_env = env;
4396 env = cpu_single_env;
4397
6ebbf390 4398 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ee5bbe38 4399 if (ret) {
c2bc0e38 4400 cpu_restore_state2(retaddr);
ee5bbe38
FB		 4401 cpu_loop_exit();
4402 }
4403 env = saved_env;
4404}
4405
3c7b48b7 4406#endif /* !CONFIG_USER_ONLY */
6c36d3fa
BS		 4407
4408#ifndef TARGET_SPARC64
3c7b48b7 4409#if !defined(CONFIG_USER_ONLY)
c227f099 4410void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
e18231a3 4411 int is_asi, int size)
6c36d3fa
BS		 4412{
4413 CPUState *saved_env;
576c2cdc 4414 int fault_type;
6c36d3fa
BS		 4415
4416 /* XXX: hack to restore env in all cases, even if not called from
4417 generated code */
4418 saved_env = env;
4419 env = cpu_single_env;
8543e2cf
BS		 4420#ifdef DEBUG_UNASSIGNED
4421 if (is_asi)
e18231a3 4422 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
77f193da 4423 " asi 0x%02x from " TARGET_FMT_lx "\n",
e18231a3
BS		 4424 is_exec ? "exec" : is_write ? "write" : "read", size,
4425 size == 1 ? "" : "s", addr, is_asi, env->pc);
8543e2cf 4426 else
e18231a3
BS		 4427 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
4428 " from " TARGET_FMT_lx "\n",
4429 is_exec ? "exec" : is_write ? "write" : "read", size,
4430 size == 1 ? "" : "s", addr, env->pc);
8543e2cf 4431#endif
576c2cdc
AT		 4432 /* Don't overwrite translation and access faults */
4433 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
4434 if ((fault_type > 4) || (fault_type == 0)) {
4435 env->mmuregs[3] = 0; /* Fault status register */
4436 if (is_asi)
4437 env->mmuregs[3] |= 1 << 16;
4438 if (env->psrs)
4439 env->mmuregs[3] |= 1 << 5;
4440 if (is_exec)
4441 env->mmuregs[3] |= 1 << 6;
4442 if (is_write)
4443 env->mmuregs[3] |= 1 << 7;
4444 env->mmuregs[3] |= (5 << 2) | 2;
4445 /* SuperSPARC will never place instruction fault addresses in the FAR */
4446 if (!is_exec) {
4447 env->mmuregs[4] = addr; /* Fault address register */
4448 }
4449 }
4450 /* overflow (same type fault was not read before another fault) */
4451 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
4452 env->mmuregs[3] |= 1;
4453 }
4454
6c36d3fa 4455 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
1b2e93c1
BS		 4456 if (is_exec)
4457 raise_exception(TT_CODE_ACCESS);
4458 else
4459 raise_exception(TT_DATA_ACCESS);
6c36d3fa 4460 }
576c2cdc
AT		 4461
4462 /* flush neverland mappings created during no-fault mode,
4463 so the sequential MMU faults report proper fault types */
4464 if (env->mmuregs[0] & MMU_NF) {
4465 tlb_flush(env, 1);
4466 }
15e7c451
AT		 4467
4468 env = saved_env;
6c36d3fa 4469}
3c7b48b7
PB		 4470#endif
4471#else
4472#if defined(CONFIG_USER_ONLY)
4473static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
4474 int is_asi, int size)
6c36d3fa 4475#else
c227f099 4476void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
e18231a3 4477 int is_asi, int size)
3c7b48b7 4478#endif
6c36d3fa 4479{
6c36d3fa
BS		 4480 CPUState *saved_env;
4481
4482 /* XXX: hack to restore env in all cases, even if not called from
4483 generated code */
4484 saved_env = env;
4485 env = cpu_single_env;
dffbe217
IK		 4486
4487#ifdef DEBUG_UNASSIGNED
77f193da
BS		 4488 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
4489 "\n", addr, env->pc);
6c36d3fa 4490#endif
dffbe217 4491
1b2e93c1
BS		 4492 if (is_exec)
4493 raise_exception(TT_CODE_ACCESS);
4494 else
4495 raise_exception(TT_DATA_ACCESS);
dffbe217
IK		 4496
4497 env = saved_env;
6c36d3fa
BS		 4498}
4499#endif
20c9f095 4500
3c7b48b7 4501
f4b1a842
BS		 4502#ifdef TARGET_SPARC64
4503void helper_tick_set_count(void *opaque, uint64_t count)
4504{
4505#if !defined(CONFIG_USER_ONLY)
4506 cpu_tick_set_count(opaque, count);
4507#endif
4508}
4509
4510uint64_t helper_tick_get_count(void *opaque)
4511{
4512#if !defined(CONFIG_USER_ONLY)
4513 return cpu_tick_get_count(opaque);
4514#else
4515 return 0;
4516#endif
4517}
4518
4519void helper_tick_set_limit(void *opaque, uint64_t limit)
4520{
4521#if !defined(CONFIG_USER_ONLY)
4522 cpu_tick_set_limit(opaque, limit);
4523#endif
4524}
4525#endif
Qemu copy for testing