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Sparc32: dummy implementation of MXCC MMU breakpoint registers
[qemu.git] / target-sparc / op_helper.c
CommitLineData
e8af50a3 1#include "exec.h"
eed152bb 2#include "host-utils.h"
1a2fb1c0 3#include "helper.h"
b04d9890 4#include "sysemu.h"
e8af50a3 5
e80cfcfc 6//#define DEBUG_MMU
952a328f 7//#define DEBUG_MXCC
94554550 8//#define DEBUG_UNALIGNED
6c36d3fa 9//#define DEBUG_UNASSIGNED
8543e2cf 10//#define DEBUG_ASI
d81fd722 11//#define DEBUG_PCALL
7e8695ed 12//#define DEBUG_PSTATE
b04d9890 13//#define DEBUG_CACHE_CONTROL
e80cfcfc 14
952a328f 15#ifdef DEBUG_MMU
001faf32
BS		 16#define DPRINTF_MMU(fmt, ...) \
17 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
952a328f 18#else
001faf32 19#define DPRINTF_MMU(fmt, ...) do {} while (0)
952a328f
BS		 20#endif
21
22#ifdef DEBUG_MXCC
001faf32
BS		 23#define DPRINTF_MXCC(fmt, ...) \
24 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
952a328f 25#else
001faf32 26#define DPRINTF_MXCC(fmt, ...) do {} while (0)
952a328f
BS		 27#endif
28
8543e2cf 29#ifdef DEBUG_ASI
001faf32
BS		 30#define DPRINTF_ASI(fmt, ...) \
31 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
8543e2cf
BS		 32#endif
33
7e8695ed
IK		 34#ifdef DEBUG_PSTATE
35#define DPRINTF_PSTATE(fmt, ...) \
36 do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
37#else
38#define DPRINTF_PSTATE(fmt, ...) do {} while (0)
39#endif
40
b04d9890
FC		 41#ifdef DEBUG_CACHE_CONTROL
42#define DPRINTF_CACHE_CONTROL(fmt, ...) \
43 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
44#else
45#define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
46#endif
47
2cade6a3
BS		 48#ifdef TARGET_SPARC64
49#ifndef TARGET_ABI32
50#define AM_CHECK(env1) ((env1)->pstate & PS_AM)
c2bc0e38 51#else
2cade6a3
BS		 52#define AM_CHECK(env1) (1)
53#endif
c2bc0e38
BS		 54#endif
55
21ffd181
BS		 56#define DT0 (env->dt0)
57#define DT1 (env->dt1)
58#define QT0 (env->qt0)
59#define QT1 (env->qt1)
60
b04d9890
FC		 61/* Leon3 cache control */
62
63/* Cache control: emulate the behavior of cache control registers but without
64 any effect on the emulated */
65
66#define CACHE_STATE_MASK 0x3
67#define CACHE_DISABLED 0x0
68#define CACHE_FROZEN 0x1
69#define CACHE_ENABLED 0x3
70
71/* Cache Control register fields */
72
73#define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */
74#define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */
75#define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */
76#define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */
77#define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */
78#define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */
79#define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */
80#define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */
81
3c7b48b7
PB		 82#if defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
83static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
84 int is_asi, int size);
85#endif
86
9c22a623 87#if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
697a77e6
IK		 88// Calculates TSB pointer value for fault page size 8k or 64k
89static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
90 uint64_t tag_access_register,
91 int page_size)
92{
93 uint64_t tsb_base = tsb_register & ~0x1fffULL;
6e8e7d4c
IK		 94 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
95 int tsb_size = tsb_register & 0xf;
697a77e6
IK		 96
97 // discard lower 13 bits which hold tag access context
98 uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
99
100 // now reorder bits
101 uint64_t tsb_base_mask = ~0x1fffULL;
102 uint64_t va = tag_access_va;
103
104 // move va bits to correct position
105 if (page_size == 8*1024) {
106 va >>= 9;
107 } else if (page_size == 64*1024) {
108 va >>= 12;
109 }
110
111 if (tsb_size) {
112 tsb_base_mask <<= tsb_size;
113 }
114
115 // calculate tsb_base mask and adjust va if split is in use
116 if (tsb_split) {
117 if (page_size == 8*1024) {
118 va &= ~(1ULL << (13 + tsb_size));
119 } else if (page_size == 64*1024) {
120 va |= (1ULL << (13 + tsb_size));
121 }
122 tsb_base_mask <<= 1;
123 }
124
125 return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
126}
127
128// Calculates tag target register value by reordering bits
129// in tag access register
130static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
131{
132 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
133}
134
f707726e
IK		 135static void replace_tlb_entry(SparcTLBEntry *tlb,
136 uint64_t tlb_tag, uint64_t tlb_tte,
137 CPUState *env1)
6e8e7d4c
IK		 138{
139 target_ulong mask, size, va, offset;
140
141 // flush page range if translation is valid
f707726e 142 if (TTE_IS_VALID(tlb->tte)) {
6e8e7d4c
IK		 143
144 mask = 0xffffffffffffe000ULL;
145 mask <<= 3 * ((tlb->tte >> 61) & 3);
146 size = ~mask + 1;
147
148 va = tlb->tag & mask;
149
150 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
151 tlb_flush_page(env1, va + offset);
152 }
153 }
154
155 tlb->tag = tlb_tag;
156 tlb->tte = tlb_tte;
157}
158
159static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
f707726e 160 const char* strmmu, CPUState *env1)
6e8e7d4c
IK		 161{
162 unsigned int i;
163 target_ulong mask;
299b520c
IK		 164 uint64_t context;
165
166 int is_demap_context = (demap_addr >> 6) & 1;
167
168 // demap context
169 switch ((demap_addr >> 4) & 3) {
170 case 0: // primary
171 context = env1->dmmu.mmu_primary_context;
172 break;
173 case 1: // secondary
174 context = env1->dmmu.mmu_secondary_context;
175 break;
176 case 2: // nucleus
177 context = 0;
178 break;
179 case 3: // reserved
180 default:
181 return;
182 }
6e8e7d4c
IK		 183
184 for (i = 0; i < 64; i++) {
f707726e 185 if (TTE_IS_VALID(tlb[i].tte)) {
6e8e7d4c 186
299b520c
IK		 187 if (is_demap_context) {
188 // will remove non-global entries matching context value
189 if (TTE_IS_GLOBAL(tlb[i].tte) ||
190 !tlb_compare_context(&tlb[i], context)) {
191 continue;
192 }
193 } else {
194 // demap page
195 // will remove any entry matching VA
196 mask = 0xffffffffffffe000ULL;
197 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
198
199 if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
200 continue;
201 }
202
203 // entry should be global or matching context value
204 if (!TTE_IS_GLOBAL(tlb[i].tte) &&
205 !tlb_compare_context(&tlb[i], context)) {
206 continue;
207 }
208 }
6e8e7d4c 209
299b520c 210 replace_tlb_entry(&tlb[i], 0, 0, env1);
6e8e7d4c 211#ifdef DEBUG_MMU
299b520c 212 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
d41160a3 213 dump_mmu(stdout, fprintf, env1);
6e8e7d4c 214#endif
6e8e7d4c
IK		 215 }
216 }
6e8e7d4c
IK		 217}
218
f707726e
IK		 219static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
220 uint64_t tlb_tag, uint64_t tlb_tte,
221 const char* strmmu, CPUState *env1)
222{
223 unsigned int i, replace_used;
224
225 // Try replacing invalid entry
226 for (i = 0; i < 64; i++) {
227 if (!TTE_IS_VALID(tlb[i].tte)) {
228 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
229#ifdef DEBUG_MMU
230 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
d41160a3 231 dump_mmu(stdout, fprintf, env1);
f707726e
IK		 232#endif
233 return;
234 }
235 }
236
237 // All entries are valid, try replacing unlocked entry
238
239 for (replace_used = 0; replace_used < 2; ++replace_used) {
240
241 // Used entries are not replaced on first pass
242
243 for (i = 0; i < 64; i++) {
244 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
245
246 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
247#ifdef DEBUG_MMU
248 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
249 strmmu, (replace_used?"used":"unused"), i);
d41160a3 250 dump_mmu(stdout, fprintf, env1);
f707726e
IK		 251#endif
252 return;
253 }
254 }
255
256 // Now reset used bit and search for unused entries again
257
258 for (i = 0; i < 64; i++) {
259 TTE_SET_UNUSED(tlb[i].tte);
260 }
261 }
262
263#ifdef DEBUG_MMU
264 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
265#endif
266 // error state?
267}
268
697a77e6
IK		 269#endif
270
41db525e 271static inline target_ulong address_mask(CPUState *env1, target_ulong addr)
2cade6a3
BS		 272{
273#ifdef TARGET_SPARC64
274 if (AM_CHECK(env1))
41db525e 275 addr &= 0xffffffffULL;
2cade6a3 276#endif
41db525e 277 return addr;
2cade6a3
BS		 278}
279
1295001c
IK		 280/* returns true if access using this ASI is to have address translated by MMU
281 otherwise access is to raw physical address */
282static inline int is_translating_asi(int asi)
283{
284#ifdef TARGET_SPARC64
285 /* Ultrasparc IIi translating asi
286 - note this list is defined by cpu implementation
287 */
288 switch (asi) {
289 case 0x04 ... 0x11:
290 case 0x18 ... 0x19:
291 case 0x24 ... 0x2C:
292 case 0x70 ... 0x73:
293 case 0x78 ... 0x79:
294 case 0x80 ... 0xFF:
295 return 1;
296
297 default:
298 return 0;
299 }
300#else
301 /* TODO: check sparc32 bits */
302 return 0;
303#endif
304}
305
306static inline target_ulong asi_address_mask(CPUState *env1,
307 int asi, target_ulong addr)
308{
309 if (is_translating_asi(asi)) {
310 return address_mask(env, addr);
311 } else {
312 return addr;
313 }
314}
315
f4a5a5ba 316static void raise_exception(int tt)
9d893301
FB		 317{
318 env->exception_index = tt;
319 cpu_loop_exit();
3b46e624 320}
9d893301 321
a7812ae4
PB		 322void HELPER(raise_exception)(int tt)
323{
324 raise_exception(tt);
325}
326
b04d9890
FC		 327void helper_shutdown(void)
328{
329#if !defined(CONFIG_USER_ONLY)
330 qemu_system_shutdown_request();
331#endif
332}
333
2b29924f
BS		 334void helper_check_align(target_ulong addr, uint32_t align)
335{
c2bc0e38
BS		 336 if (addr & align) {
337#ifdef DEBUG_UNALIGNED
338 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
339 "\n", addr, env->pc);
340#endif
2b29924f 341 raise_exception(TT_UNALIGNED);
c2bc0e38 342 }
2b29924f
BS		 343}
344
44e7757c
BS		 345#define F_HELPER(name, p) void helper_f##name##p(void)
346
44e7757c 347#define F_BINOP(name) \
714547bb 348 float32 helper_f ## name ## s (float32 src1, float32 src2) \
44e7757c 349 { \
714547bb 350 return float32_ ## name (src1, src2, &env->fp_status); \
44e7757c
BS		 351 } \
352 F_HELPER(name, d) \
353 { \
354 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
4e14008f
BS		 355 } \
356 F_HELPER(name, q) \
357 { \
358 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
44e7757c 359 }
44e7757c
BS		 360
361F_BINOP(add);
362F_BINOP(sub);
363F_BINOP(mul);
364F_BINOP(div);
365#undef F_BINOP
366
d84763bc 367void helper_fsmuld(float32 src1, float32 src2)
1a2fb1c0 368{
d84763bc
BS		 369 DT0 = float64_mul(float32_to_float64(src1, &env->fp_status),
370 float32_to_float64(src2, &env->fp_status),
44e7757c
BS		 371 &env->fp_status);
372}
1a2fb1c0 373
4e14008f
BS		 374void helper_fdmulq(void)
375{
376 QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
377 float64_to_float128(DT1, &env->fp_status),
378 &env->fp_status);
379}
4e14008f 380
714547bb 381float32 helper_fnegs(float32 src)
44e7757c 382{
714547bb 383 return float32_chs(src);
417454b0
BS		 384}
385
44e7757c
BS		 386#ifdef TARGET_SPARC64
387F_HELPER(neg, d)
7e8c2b6c 388{
44e7757c 389 DT0 = float64_chs(DT1);
7e8c2b6c 390}
4e14008f 391
4e14008f
BS		 392F_HELPER(neg, q)
393{
394 QT0 = float128_chs(QT1);
395}
396#endif
44e7757c
BS		 397
398/* Integer to float conversion. */
714547bb 399float32 helper_fitos(int32_t src)
a0c4cb4a 400{
714547bb 401 return int32_to_float32(src, &env->fp_status);
a0c4cb4a
FB		 402}
403
d84763bc 404void helper_fitod(int32_t src)
a0c4cb4a 405{
d84763bc 406 DT0 = int32_to_float64(src, &env->fp_status);
a0c4cb4a 407}
9c2b428e 408
c5d04e99 409void helper_fitoq(int32_t src)
4e14008f 410{
c5d04e99 411 QT0 = int32_to_float128(src, &env->fp_status);
4e14008f 412}
4e14008f 413
1e64e78d 414#ifdef TARGET_SPARC64
d84763bc 415float32 helper_fxtos(void)
1e64e78d 416{
d84763bc 417 return int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
1e64e78d
BS		 418}
419
44e7757c 420F_HELPER(xto, d)
1e64e78d 421{
1e64e78d 422 DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
1e64e78d 423}
64a88d5d 424
4e14008f
BS		 425F_HELPER(xto, q)
426{
427 QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
428}
429#endif
44e7757c
BS		 430#undef F_HELPER
431
432/* floating point conversion */
d84763bc 433float32 helper_fdtos(void)
44e7757c 434{
d84763bc 435 return float64_to_float32(DT1, &env->fp_status);
44e7757c
BS		 436}
437
d84763bc 438void helper_fstod(float32 src)
44e7757c 439{
d84763bc 440 DT0 = float32_to_float64(src, &env->fp_status);
44e7757c 441}
9c2b428e 442
c5d04e99 443float32 helper_fqtos(void)
4e14008f 444{
c5d04e99 445 return float128_to_float32(QT1, &env->fp_status);
4e14008f
BS		 446}
447
c5d04e99 448void helper_fstoq(float32 src)
4e14008f 449{
c5d04e99 450 QT0 = float32_to_float128(src, &env->fp_status);
4e14008f
BS		 451}
452
453void helper_fqtod(void)
454{
455 DT0 = float128_to_float64(QT1, &env->fp_status);
456}
457
458void helper_fdtoq(void)
459{
460 QT0 = float64_to_float128(DT1, &env->fp_status);
461}
4e14008f 462
44e7757c 463/* Float to integer conversion. */
714547bb 464int32_t helper_fstoi(float32 src)
44e7757c 465{
714547bb 466 return float32_to_int32_round_to_zero(src, &env->fp_status);
44e7757c
BS		 467}
468
d84763bc 469int32_t helper_fdtoi(void)
44e7757c 470{
d84763bc 471 return float64_to_int32_round_to_zero(DT1, &env->fp_status);
44e7757c
BS		 472}
473
c5d04e99 474int32_t helper_fqtoi(void)
4e14008f 475{
c5d04e99 476 return float128_to_int32_round_to_zero(QT1, &env->fp_status);
4e14008f 477}
4e14008f 478
44e7757c 479#ifdef TARGET_SPARC64
d84763bc 480void helper_fstox(float32 src)
44e7757c 481{
d84763bc 482 *((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status);
44e7757c
BS		 483}
484
485void helper_fdtox(void)
486{
487 *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
488}
489
4e14008f
BS		 490void helper_fqtox(void)
491{
492 *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);
493}
4e14008f 494
44e7757c
BS		 495void helper_faligndata(void)
496{
497 uint64_t tmp;
498
499 tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
06057e6f
BS		 500 /* on many architectures a shift of 64 does nothing */
501 if ((env->gsr & 7) != 0) {
502 tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
503 }
44e7757c
BS		 504 *((uint64_t *)&DT0) = tmp;
505}
506
e2542fe2 507#ifdef HOST_WORDS_BIGENDIAN
44e7757c
BS		 508#define VIS_B64(n) b[7 - (n)]
509#define VIS_W64(n) w[3 - (n)]
510#define VIS_SW64(n) sw[3 - (n)]
511#define VIS_L64(n) l[1 - (n)]
512#define VIS_B32(n) b[3 - (n)]
513#define VIS_W32(n) w[1 - (n)]
514#else
515#define VIS_B64(n) b[n]
516#define VIS_W64(n) w[n]
517#define VIS_SW64(n) sw[n]
518#define VIS_L64(n) l[n]
519#define VIS_B32(n) b[n]
520#define VIS_W32(n) w[n]
521#endif
522
523typedef union {
524 uint8_t b[8];
525 uint16_t w[4];
526 int16_t sw[4];
527 uint32_t l[2];
528 float64 d;
529} vis64;
530
531typedef union {
532 uint8_t b[4];
533 uint16_t w[2];
534 uint32_t l;
535 float32 f;
536} vis32;
537
538void helper_fpmerge(void)
539{
540 vis64 s, d;
541
542 s.d = DT0;
543 d.d = DT1;
544
545 // Reverse calculation order to handle overlap
546 d.VIS_B64(7) = s.VIS_B64(3);
547 d.VIS_B64(6) = d.VIS_B64(3);
548 d.VIS_B64(5) = s.VIS_B64(2);
549 d.VIS_B64(4) = d.VIS_B64(2);
550 d.VIS_B64(3) = s.VIS_B64(1);
551 d.VIS_B64(2) = d.VIS_B64(1);
552 d.VIS_B64(1) = s.VIS_B64(0);
553 //d.VIS_B64(0) = d.VIS_B64(0);
554
555 DT0 = d.d;
556}
557
558void helper_fmul8x16(void)
559{
560 vis64 s, d;
561 uint32_t tmp;
562
563 s.d = DT0;
564 d.d = DT1;
565
566#define PMUL(r) \
567 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
568 if ((tmp & 0xff) > 0x7f) \
569 tmp += 0x100; \
570 d.VIS_W64(r) = tmp >> 8;
571
572 PMUL(0);
573 PMUL(1);
574 PMUL(2);
575 PMUL(3);
576#undef PMUL
577
578 DT0 = d.d;
579}
580
581void helper_fmul8x16al(void)
582{
583 vis64 s, d;
584 uint32_t tmp;
585
586 s.d = DT0;
587 d.d = DT1;
588
589#define PMUL(r) \
590 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
591 if ((tmp & 0xff) > 0x7f) \
592 tmp += 0x100; \
593 d.VIS_W64(r) = tmp >> 8;
594
595 PMUL(0);
596 PMUL(1);
597 PMUL(2);
598 PMUL(3);
599#undef PMUL
600
601 DT0 = d.d;
602}
603
604void helper_fmul8x16au(void)
605{
606 vis64 s, d;
607 uint32_t tmp;
608
609 s.d = DT0;
610 d.d = DT1;
611
612#define PMUL(r) \
613 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
614 if ((tmp & 0xff) > 0x7f) \
615 tmp += 0x100; \
616 d.VIS_W64(r) = tmp >> 8;
617
618 PMUL(0);
619 PMUL(1);
620 PMUL(2);
621 PMUL(3);
622#undef PMUL
623
624 DT0 = d.d;
625}
626
627void helper_fmul8sux16(void)
628{
629 vis64 s, d;
630 uint32_t tmp;
631
632 s.d = DT0;
633 d.d = DT1;
634
635#define PMUL(r) \
636 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
637 if ((tmp & 0xff) > 0x7f) \
638 tmp += 0x100; \
639 d.VIS_W64(r) = tmp >> 8;
640
641 PMUL(0);
642 PMUL(1);
643 PMUL(2);
644 PMUL(3);
645#undef PMUL
646
647 DT0 = d.d;
648}
649
650void helper_fmul8ulx16(void)
651{
652 vis64 s, d;
653 uint32_t tmp;
654
655 s.d = DT0;
656 d.d = DT1;
657
658#define PMUL(r) \
659 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
660 if ((tmp & 0xff) > 0x7f) \
661 tmp += 0x100; \
662 d.VIS_W64(r) = tmp >> 8;
663
664 PMUL(0);
665 PMUL(1);
666 PMUL(2);
667 PMUL(3);
668#undef PMUL
669
670 DT0 = d.d;
671}
672
673void helper_fmuld8sux16(void)
674{
675 vis64 s, d;
676 uint32_t tmp;
677
678 s.d = DT0;
679 d.d = DT1;
680
681#define PMUL(r) \
682 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
683 if ((tmp & 0xff) > 0x7f) \
684 tmp += 0x100; \
685 d.VIS_L64(r) = tmp;
686
687 // Reverse calculation order to handle overlap
688 PMUL(1);
689 PMUL(0);
690#undef PMUL
691
692 DT0 = d.d;
693}
694
695void helper_fmuld8ulx16(void)
696{
697 vis64 s, d;
698 uint32_t tmp;
699
700 s.d = DT0;
701 d.d = DT1;
702
703#define PMUL(r) \
704 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
705 if ((tmp & 0xff) > 0x7f) \
706 tmp += 0x100; \
707 d.VIS_L64(r) = tmp;
708
709 // Reverse calculation order to handle overlap
710 PMUL(1);
711 PMUL(0);
712#undef PMUL
713
714 DT0 = d.d;
715}
716
717void helper_fexpand(void)
718{
719 vis32 s;
720 vis64 d;
721
722 s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
723 d.d = DT1;
c55bda30
BS		 724 d.VIS_W64(0) = s.VIS_B32(0) << 4;
725 d.VIS_W64(1) = s.VIS_B32(1) << 4;
726 d.VIS_W64(2) = s.VIS_B32(2) << 4;
727 d.VIS_W64(3) = s.VIS_B32(3) << 4;
44e7757c
BS		 728
729 DT0 = d.d;
730}
731
732#define VIS_HELPER(name, F) \
733 void name##16(void) \
734 { \
735 vis64 s, d; \
736 \
737 s.d = DT0; \
738 d.d = DT1; \
739 \
740 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
741 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
742 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
743 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
744 \
745 DT0 = d.d; \
746 } \
747 \
1d01299d 748 uint32_t name##16s(uint32_t src1, uint32_t src2) \
44e7757c
BS		 749 { \
750 vis32 s, d; \
751 \
1d01299d
BS		 752 s.l = src1; \
753 d.l = src2; \
44e7757c
BS		 754 \
755 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
756 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
757 \
1d01299d 758 return d.l; \
44e7757c
BS		 759 } \
760 \
761 void name##32(void) \
762 { \
763 vis64 s, d; \
764 \
765 s.d = DT0; \
766 d.d = DT1; \
767 \
768 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
769 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
770 \
771 DT0 = d.d; \
772 } \
773 \
1d01299d 774 uint32_t name##32s(uint32_t src1, uint32_t src2) \
44e7757c
BS		 775 { \
776 vis32 s, d; \
777 \
1d01299d
BS		 778 s.l = src1; \
779 d.l = src2; \
44e7757c
BS		 780 \
781 d.l = F(d.l, s.l); \
782 \
1d01299d 783 return d.l; \
44e7757c
BS		 784 }
785
786#define FADD(a, b) ((a) + (b))
787#define FSUB(a, b) ((a) - (b))
788VIS_HELPER(helper_fpadd, FADD)
789VIS_HELPER(helper_fpsub, FSUB)
790
791#define VIS_CMPHELPER(name, F) \
792 void name##16(void) \
793 { \
794 vis64 s, d; \
795 \
796 s.d = DT0; \
797 d.d = DT1; \
798 \
799 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
800 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
801 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
802 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
803 \
804 DT0 = d.d; \
805 } \
806 \
807 void name##32(void) \
808 { \
809 vis64 s, d; \
810 \
811 s.d = DT0; \
812 d.d = DT1; \
813 \
814 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
815 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
816 \
817 DT0 = d.d; \
818 }
819
820#define FCMPGT(a, b) ((a) > (b))
821#define FCMPEQ(a, b) ((a) == (b))
822#define FCMPLE(a, b) ((a) <= (b))
823#define FCMPNE(a, b) ((a) != (b))
824
825VIS_CMPHELPER(helper_fcmpgt, FCMPGT)
826VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)
827VIS_CMPHELPER(helper_fcmple, FCMPLE)
828VIS_CMPHELPER(helper_fcmpne, FCMPNE)
829#endif
830
831void helper_check_ieee_exceptions(void)
832{
833 target_ulong status;
834
835 status = get_float_exception_flags(&env->fp_status);
836 if (status) {
837 /* Copy IEEE 754 flags into FSR */
838 if (status & float_flag_invalid)
839 env->fsr |= FSR_NVC;
840 if (status & float_flag_overflow)
841 env->fsr |= FSR_OFC;
842 if (status & float_flag_underflow)
843 env->fsr |= FSR_UFC;
844 if (status & float_flag_divbyzero)
845 env->fsr |= FSR_DZC;
846 if (status & float_flag_inexact)
847 env->fsr |= FSR_NXC;
848
849 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
850 /* Unmasked exception, generate a trap */
851 env->fsr |= FSR_FTT_IEEE_EXCP;
852 raise_exception(TT_FP_EXCP);
853 } else {
854 /* Accumulate exceptions */
855 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
856 }
857 }
858}
859
860void helper_clear_float_exceptions(void)
861{
862 set_float_exception_flags(0, &env->fp_status);
863}
864
714547bb 865float32 helper_fabss(float32 src)
e8af50a3 866{
714547bb 867 return float32_abs(src);
e8af50a3
FB		 868}
869
3475187d 870#ifdef TARGET_SPARC64
7e8c2b6c 871void helper_fabsd(void)
3475187d
FB		 872{
873 DT0 = float64_abs(DT1);
874}
4e14008f 875
4e14008f
BS		 876void helper_fabsq(void)
877{
878 QT0 = float128_abs(QT1);
879}
880#endif
3475187d 881
714547bb 882float32 helper_fsqrts(float32 src)
e8af50a3 883{
714547bb 884 return float32_sqrt(src, &env->fp_status);
e8af50a3
FB		 885}
886
7e8c2b6c 887void helper_fsqrtd(void)
e8af50a3 888{
7a0e1f41 889 DT0 = float64_sqrt(DT1, &env->fp_status);
e8af50a3
FB		 890}
891
4e14008f
BS		 892void helper_fsqrtq(void)
893{
894 QT0 = float128_sqrt(QT1, &env->fp_status);
895}
4e14008f 896
1b5f56b1 897#define GEN_FCMP(name, size, reg1, reg2, FS, E) \
7e8c2b6c 898 void glue(helper_, name) (void) \
65ce8c2f 899 { \
1b5f56b1
BS		 900 env->fsr &= FSR_FTT_NMASK; \
901 if (E && (glue(size, _is_any_nan)(reg1) || \
902 glue(size, _is_any_nan)(reg2)) && \
903 (env->fsr & FSR_NVM)) { \
904 env->fsr |= FSR_NVC; \
905 env->fsr |= FSR_FTT_IEEE_EXCP; \
906 raise_exception(TT_FP_EXCP); \
907 } \
65ce8c2f
FB		 908 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
909 case float_relation_unordered: \
1b5f56b1 910 if ((env->fsr & FSR_NVM)) { \
417454b0
BS		 911 env->fsr |= FSR_NVC; \
912 env->fsr |= FSR_FTT_IEEE_EXCP; \
65ce8c2f
FB		 913 raise_exception(TT_FP_EXCP); \
914 } else { \
1b5f56b1
BS		 915 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
916 env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
65ce8c2f
FB		 917 env->fsr |= FSR_NVA; \
918 } \
919 break; \
920 case float_relation_less: \
1b5f56b1
BS		 921 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
922 env->fsr |= FSR_FCC0 << FS; \
65ce8c2f
FB		 923 break; \
924 case float_relation_greater: \
1b5f56b1
BS		 925 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
926 env->fsr |= FSR_FCC1 << FS; \
65ce8c2f
FB		 927 break; \
928 default: \
1b5f56b1 929 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
65ce8c2f
FB		 930 break; \
931 } \
e8af50a3 932 }
1b5f56b1 933#define GEN_FCMPS(name, size, FS, E) \
714547bb
BS		 934 void glue(helper_, name)(float32 src1, float32 src2) \
935 { \
1b5f56b1
BS		 936 env->fsr &= FSR_FTT_NMASK; \
937 if (E && (glue(size, _is_any_nan)(src1) || \
938 glue(size, _is_any_nan)(src2)) && \
939 (env->fsr & FSR_NVM)) { \
940 env->fsr |= FSR_NVC; \
941 env->fsr |= FSR_FTT_IEEE_EXCP; \
942 raise_exception(TT_FP_EXCP); \
943 } \
714547bb
BS		 944 switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
945 case float_relation_unordered: \
1b5f56b1 946 if ((env->fsr & FSR_NVM)) { \
714547bb
BS		 947 env->fsr |= FSR_NVC; \
948 env->fsr |= FSR_FTT_IEEE_EXCP; \
949 raise_exception(TT_FP_EXCP); \
950 } else { \
1b5f56b1
BS		 951 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
952 env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
714547bb
BS		 953 env->fsr |= FSR_NVA; \
954 } \
955 break; \
956 case float_relation_less: \
1b5f56b1
BS		 957 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
958 env->fsr |= FSR_FCC0 << FS; \
714547bb
BS		 959 break; \
960 case float_relation_greater: \
1b5f56b1
BS		 961 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
962 env->fsr |= FSR_FCC1 << FS; \
714547bb
BS		 963 break; \
964 default: \
1b5f56b1 965 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
714547bb
BS		 966 break; \
967 } \
714547bb 968 }
e8af50a3 969
714547bb 970GEN_FCMPS(fcmps, float32, 0, 0);
417454b0
BS		 971GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
972
714547bb 973GEN_FCMPS(fcmpes, float32, 0, 1);
417454b0 974GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
3475187d 975
4e14008f
BS		 976GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
977GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
4e14008f 978
8393617c
BS		 979static uint32_t compute_all_flags(void)
980{
981 return env->psr & PSR_ICC;
982}
983
984static uint32_t compute_C_flags(void)
985{
986 return env->psr & PSR_CARRY;
987}
988
5a4bb580 989static inline uint32_t get_NZ_icc(int32_t dst)
bdf9f35d
BS		 990{
991 uint32_t ret = 0;
992
5a4bb580
RH		 993 if (dst == 0) {
994 ret = PSR_ZERO;
995 } else if (dst < 0) {
996 ret = PSR_NEG;
997 }
bdf9f35d
BS		 998 return ret;
999}
1000
8393617c
BS		 1001#ifdef TARGET_SPARC64
1002static uint32_t compute_all_flags_xcc(void)
1003{
1004 return env->xcc & PSR_ICC;
1005}
1006
1007static uint32_t compute_C_flags_xcc(void)
1008{
1009 return env->xcc & PSR_CARRY;
1010}
1011
5a4bb580 1012static inline uint32_t get_NZ_xcc(target_long dst)
bdf9f35d
BS		 1013{
1014 uint32_t ret = 0;
1015
5a4bb580
RH		 1016 if (!dst) {
1017 ret = PSR_ZERO;
1018 } else if (dst < 0) {
1019 ret = PSR_NEG;
1020 }
bdf9f35d
BS		 1021 return ret;
1022}
1023#endif
1024
6c78ea32
BS		 1025static inline uint32_t get_V_div_icc(target_ulong src2)
1026{
1027 uint32_t ret = 0;
1028
5a4bb580
RH		 1029 if (src2 != 0) {
1030 ret = PSR_OVF;
1031 }
6c78ea32
BS		 1032 return ret;
1033}
1034
1035static uint32_t compute_all_div(void)
1036{
1037 uint32_t ret;
1038
1039 ret = get_NZ_icc(CC_DST);
1040 ret |= get_V_div_icc(CC_SRC2);
1041 return ret;
1042}
1043
1044static uint32_t compute_C_div(void)
1045{
1046 return 0;
1047}
1048
5a4bb580 1049static inline uint32_t get_C_add_icc(uint32_t dst, uint32_t src1)
bdf9f35d
BS		 1050{
1051 uint32_t ret = 0;
1052
5a4bb580
RH		 1053 if (dst < src1) {
1054 ret = PSR_CARRY;
1055 }
bdf9f35d
BS		 1056 return ret;
1057}
1058
5a4bb580
RH		 1059static inline uint32_t get_C_addx_icc(uint32_t dst, uint32_t src1,
1060 uint32_t src2)
bdf9f35d
BS		 1061{
1062 uint32_t ret = 0;
1063
5a4bb580
RH		 1064 if (((src1 & src2) | (~dst & (src1 | src2))) & (1U << 31)) {
1065 ret = PSR_CARRY;
1066 }
1067 return ret;
1068}
1069
1070static inline uint32_t get_V_add_icc(uint32_t dst, uint32_t src1,
1071 uint32_t src2)
1072{
1073 uint32_t ret = 0;
1074
1075 if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1U << 31)) {
1076 ret = PSR_OVF;
1077 }
bdf9f35d
BS		 1078 return ret;
1079}
1080
bdf9f35d
BS		 1081#ifdef TARGET_SPARC64
1082static inline uint32_t get_C_add_xcc(target_ulong dst, target_ulong src1)
1083{
1084 uint32_t ret = 0;
1085
5a4bb580
RH		 1086 if (dst < src1) {
1087 ret = PSR_CARRY;
1088 }
1089 return ret;
1090}
1091
1092static inline uint32_t get_C_addx_xcc(target_ulong dst, target_ulong src1,
1093 target_ulong src2)
1094{
1095 uint32_t ret = 0;
1096
1097 if (((src1 & src2) | (~dst & (src1 | src2))) & (1ULL << 63)) {
1098 ret = PSR_CARRY;
1099 }
bdf9f35d
BS		 1100 return ret;
1101}
1102
1103static inline uint32_t get_V_add_xcc(target_ulong dst, target_ulong src1,
1104 target_ulong src2)
1105{
1106 uint32_t ret = 0;
1107
5a4bb580
RH		 1108 if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1ULL << 63)) {
1109 ret = PSR_OVF;
1110 }
bdf9f35d
BS		 1111 return ret;
1112}
1113
1114static uint32_t compute_all_add_xcc(void)
1115{
1116 uint32_t ret;
1117
1118 ret = get_NZ_xcc(CC_DST);
1119 ret |= get_C_add_xcc(CC_DST, CC_SRC);
1120 ret |= get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2);
1121 return ret;
1122}
1123
1124static uint32_t compute_C_add_xcc(void)
1125{
1126 return get_C_add_xcc(CC_DST, CC_SRC);
1127}
8393617c
BS		 1128#endif
1129
3e6ba503 1130static uint32_t compute_all_add(void)
789c91ef
BS		 1131{
1132 uint32_t ret;
1133
1134 ret = get_NZ_icc(CC_DST);
5a4bb580 1135 ret |= get_C_add_icc(CC_DST, CC_SRC);
789c91ef
BS		 1136 ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2);
1137 return ret;
1138}
1139
3e6ba503 1140static uint32_t compute_C_add(void)
789c91ef 1141{
5a4bb580 1142 return get_C_add_icc(CC_DST, CC_SRC);
789c91ef
BS		 1143}
1144
1145#ifdef TARGET_SPARC64
1146static uint32_t compute_all_addx_xcc(void)
1147{
1148 uint32_t ret;
1149
1150 ret = get_NZ_xcc(CC_DST);
5a4bb580 1151 ret |= get_C_addx_xcc(CC_DST, CC_SRC, CC_SRC2);
789c91ef
BS		 1152 ret |= get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2);
1153 return ret;
1154}
1155
1156static uint32_t compute_C_addx_xcc(void)
1157{
1158 uint32_t ret;
1159
5a4bb580 1160 ret = get_C_addx_xcc(CC_DST, CC_SRC, CC_SRC2);
789c91ef
BS		 1161 return ret;
1162}
1163#endif
1164
5a4bb580
RH		 1165static uint32_t compute_all_addx(void)
1166{
1167 uint32_t ret;
1168
1169 ret = get_NZ_icc(CC_DST);
1170 ret |= get_C_addx_icc(CC_DST, CC_SRC, CC_SRC2);
1171 ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2);
1172 return ret;
1173}
1174
1175static uint32_t compute_C_addx(void)
1176{
1177 uint32_t ret;
1178
1179 ret = get_C_addx_icc(CC_DST, CC_SRC, CC_SRC2);
1180 return ret;
1181}
1182
3b2d1e92
BS		 1183static inline uint32_t get_V_tag_icc(target_ulong src1, target_ulong src2)
1184{
1185 uint32_t ret = 0;
1186
5a4bb580
RH		 1187 if ((src1 | src2) & 0x3) {
1188 ret = PSR_OVF;
1189 }
3b2d1e92
BS		 1190 return ret;
1191}
1192
1193static uint32_t compute_all_tadd(void)
1194{
1195 uint32_t ret;
1196
1197 ret = get_NZ_icc(CC_DST);
5a4bb580 1198 ret |= get_C_add_icc(CC_DST, CC_SRC);
3b2d1e92
BS		 1199 ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2);
1200 ret |= get_V_tag_icc(CC_SRC, CC_SRC2);
1201 return ret;
1202}
1203
3b2d1e92
BS		 1204static uint32_t compute_all_taddtv(void)
1205{
1206 uint32_t ret;
1207
1208 ret = get_NZ_icc(CC_DST);
5a4bb580 1209 ret |= get_C_add_icc(CC_DST, CC_SRC);
3b2d1e92
BS		 1210 return ret;
1211}
1212
5a4bb580 1213static inline uint32_t get_C_sub_icc(uint32_t src1, uint32_t src2)
3b2d1e92 1214{
5a4bb580
RH		 1215 uint32_t ret = 0;
1216
1217 if (src1 < src2) {
1218 ret = PSR_CARRY;
1219 }
1220 return ret;
3b2d1e92
BS		 1221}
1222
5a4bb580
RH		 1223static inline uint32_t get_C_subx_icc(uint32_t dst, uint32_t src1,
1224 uint32_t src2)
d4b0d468
BS		 1225{
1226 uint32_t ret = 0;
1227
5a4bb580
RH		 1228 if (((~src1 & src2) | (dst & (~src1 | src2))) & (1U << 31)) {
1229 ret = PSR_CARRY;
1230 }
d4b0d468
BS		 1231 return ret;
1232}
1233
5a4bb580
RH		 1234static inline uint32_t get_V_sub_icc(uint32_t dst, uint32_t src1,
1235 uint32_t src2)
d4b0d468
BS		 1236{
1237 uint32_t ret = 0;
1238
5a4bb580
RH		 1239 if (((src1 ^ src2) & (src1 ^ dst)) & (1U << 31)) {
1240 ret = PSR_OVF;
1241 }
d4b0d468
BS		 1242 return ret;
1243}
1244
d4b0d468
BS		 1245
1246#ifdef TARGET_SPARC64
1247static inline uint32_t get_C_sub_xcc(target_ulong src1, target_ulong src2)
1248{
1249 uint32_t ret = 0;
1250
5a4bb580
RH		 1251 if (src1 < src2) {
1252 ret = PSR_CARRY;
1253 }
1254 return ret;
1255}
1256
1257static inline uint32_t get_C_subx_xcc(target_ulong dst, target_ulong src1,
1258 target_ulong src2)
1259{
1260 uint32_t ret = 0;
1261
1262 if (((~src1 & src2) | (dst & (~src1 | src2))) & (1ULL << 63)) {
1263 ret = PSR_CARRY;
1264 }
d4b0d468
BS		 1265 return ret;
1266}
1267
1268static inline uint32_t get_V_sub_xcc(target_ulong dst, target_ulong src1,
1269 target_ulong src2)
1270{
1271 uint32_t ret = 0;
1272
5a4bb580
RH		 1273 if (((src1 ^ src2) & (src1 ^ dst)) & (1ULL << 63)) {
1274 ret = PSR_OVF;
1275 }
d4b0d468
BS		 1276 return ret;
1277}
1278
1279static uint32_t compute_all_sub_xcc(void)
1280{
1281 uint32_t ret;
1282
1283 ret = get_NZ_xcc(CC_DST);
1284 ret |= get_C_sub_xcc(CC_SRC, CC_SRC2);
1285 ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2);
1286 return ret;
1287}
1288
1289static uint32_t compute_C_sub_xcc(void)
1290{
1291 return get_C_sub_xcc(CC_SRC, CC_SRC2);
1292}
1293#endif
1294
3e6ba503 1295static uint32_t compute_all_sub(void)
2ca1d92b
BS		 1296{
1297 uint32_t ret;
1298
1299 ret = get_NZ_icc(CC_DST);
5a4bb580 1300 ret |= get_C_sub_icc(CC_SRC, CC_SRC2);
2ca1d92b
BS		 1301 ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2);
1302 return ret;
1303}
1304
3e6ba503 1305static uint32_t compute_C_sub(void)
2ca1d92b 1306{
5a4bb580 1307 return get_C_sub_icc(CC_SRC, CC_SRC2);
2ca1d92b
BS		 1308}
1309
1310#ifdef TARGET_SPARC64
1311static uint32_t compute_all_subx_xcc(void)
1312{
1313 uint32_t ret;
1314
1315 ret = get_NZ_xcc(CC_DST);
5a4bb580 1316 ret |= get_C_subx_xcc(CC_DST, CC_SRC, CC_SRC2);
2ca1d92b
BS		 1317 ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2);
1318 return ret;
1319}
1320
1321static uint32_t compute_C_subx_xcc(void)
1322{
1323 uint32_t ret;
1324
5a4bb580 1325 ret = get_C_subx_xcc(CC_DST, CC_SRC, CC_SRC2);
2ca1d92b
BS		 1326 return ret;
1327}
1328#endif
1329
5a4bb580 1330static uint32_t compute_all_subx(void)
3b2d1e92
BS		 1331{
1332 uint32_t ret;
1333
1334 ret = get_NZ_icc(CC_DST);
5a4bb580 1335 ret |= get_C_subx_icc(CC_DST, CC_SRC, CC_SRC2);
3b2d1e92 1336 ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2);
3b2d1e92
BS		 1337 return ret;
1338}
1339
5a4bb580 1340static uint32_t compute_C_subx(void)
3b2d1e92 1341{
5a4bb580
RH		 1342 uint32_t ret;
1343
1344 ret = get_C_subx_icc(CC_DST, CC_SRC, CC_SRC2);
1345 return ret;
3b2d1e92
BS		 1346}
1347
5a4bb580 1348static uint32_t compute_all_tsub(void)
3b2d1e92
BS		 1349{
1350 uint32_t ret;
1351
1352 ret = get_NZ_icc(CC_DST);
5a4bb580
RH		 1353 ret |= get_C_sub_icc(CC_SRC, CC_SRC2);
1354 ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2);
1355 ret |= get_V_tag_icc(CC_SRC, CC_SRC2);
3b2d1e92
BS		 1356 return ret;
1357}
1358
5a4bb580 1359static uint32_t compute_all_tsubtv(void)
3b2d1e92 1360{
5a4bb580
RH		 1361 uint32_t ret;
1362
1363 ret = get_NZ_icc(CC_DST);
1364 ret |= get_C_sub_icc(CC_SRC, CC_SRC2);
1365 return ret;
3b2d1e92
BS		 1366}
1367
38482a77
BS		 1368static uint32_t compute_all_logic(void)
1369{
1370 return get_NZ_icc(CC_DST);
1371}
1372
1373static uint32_t compute_C_logic(void)
1374{
1375 return 0;
1376}
1377
1378#ifdef TARGET_SPARC64
1379static uint32_t compute_all_logic_xcc(void)
1380{
1381 return get_NZ_xcc(CC_DST);
1382}
1383#endif
1384
8393617c
BS		 1385typedef struct CCTable {
1386 uint32_t (*compute_all)(void); /* return all the flags */
1387 uint32_t (*compute_c)(void); /* return the C flag */
1388} CCTable;
1389
1390static const CCTable icc_table[CC_OP_NB] = {
1391 /* CC_OP_DYNAMIC should never happen */
1392 [CC_OP_FLAGS] = { compute_all_flags, compute_C_flags },
6c78ea32 1393 [CC_OP_DIV] = { compute_all_div, compute_C_div },
bdf9f35d 1394 [CC_OP_ADD] = { compute_all_add, compute_C_add },
5a4bb580
RH		 1395 [CC_OP_ADDX] = { compute_all_addx, compute_C_addx },
1396 [CC_OP_TADD] = { compute_all_tadd, compute_C_add },
1397 [CC_OP_TADDTV] = { compute_all_taddtv, compute_C_add },
d4b0d468 1398 [CC_OP_SUB] = { compute_all_sub, compute_C_sub },
5a4bb580
RH		 1399 [CC_OP_SUBX] = { compute_all_subx, compute_C_subx },
1400 [CC_OP_TSUB] = { compute_all_tsub, compute_C_sub },
1401 [CC_OP_TSUBTV] = { compute_all_tsubtv, compute_C_sub },
38482a77 1402 [CC_OP_LOGIC] = { compute_all_logic, compute_C_logic },
8393617c
BS		 1403};
1404
1405#ifdef TARGET_SPARC64
1406static const CCTable xcc_table[CC_OP_NB] = {
1407 /* CC_OP_DYNAMIC should never happen */
1408 [CC_OP_FLAGS] = { compute_all_flags_xcc, compute_C_flags_xcc },
6c78ea32 1409 [CC_OP_DIV] = { compute_all_logic_xcc, compute_C_logic },
bdf9f35d 1410 [CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc },
789c91ef 1411 [CC_OP_ADDX] = { compute_all_addx_xcc, compute_C_addx_xcc },
3b2d1e92
BS		 1412 [CC_OP_TADD] = { compute_all_add_xcc, compute_C_add_xcc },
1413 [CC_OP_TADDTV] = { compute_all_add_xcc, compute_C_add_xcc },
d4b0d468 1414 [CC_OP_SUB] = { compute_all_sub_xcc, compute_C_sub_xcc },
2ca1d92b 1415 [CC_OP_SUBX] = { compute_all_subx_xcc, compute_C_subx_xcc },
3b2d1e92
BS		 1416 [CC_OP_TSUB] = { compute_all_sub_xcc, compute_C_sub_xcc },
1417 [CC_OP_TSUBTV] = { compute_all_sub_xcc, compute_C_sub_xcc },
38482a77 1418 [CC_OP_LOGIC] = { compute_all_logic_xcc, compute_C_logic },
8393617c
BS		 1419};
1420#endif
1421
1422void helper_compute_psr(void)
1423{
1424 uint32_t new_psr;
1425
1426 new_psr = icc_table[CC_OP].compute_all();
1427 env->psr = new_psr;
1428#ifdef TARGET_SPARC64
1429 new_psr = xcc_table[CC_OP].compute_all();
1430 env->xcc = new_psr;
1431#endif
1432 CC_OP = CC_OP_FLAGS;
1433}
1434
70c48285 1435uint32_t helper_compute_C_icc(void)
8393617c
BS		 1436{
1437 uint32_t ret;
1438
1439 ret = icc_table[CC_OP].compute_c() >> PSR_CARRY_SHIFT;
1440 return ret;
1441}
1442
5a834bb4
BS		 1443static inline void memcpy32(target_ulong *dst, const target_ulong *src)
1444{
1445 dst[0] = src[0];
1446 dst[1] = src[1];
1447 dst[2] = src[2];
1448 dst[3] = src[3];
1449 dst[4] = src[4];
1450 dst[5] = src[5];
1451 dst[6] = src[6];
1452 dst[7] = src[7];
1453}
1454
1455static void set_cwp(int new_cwp)
1456{
1457 /* put the modified wrap registers at their proper location */
1458 if (env->cwp == env->nwindows - 1) {
1459 memcpy32(env->regbase, env->regbase + env->nwindows * 16);
1460 }
1461 env->cwp = new_cwp;
1462
1463 /* put the wrap registers at their temporary location */
1464 if (new_cwp == env->nwindows - 1) {
1465 memcpy32(env->regbase + env->nwindows * 16, env->regbase);
1466 }
1467 env->regwptr = env->regbase + (new_cwp * 16);
1468}
1469
1470void cpu_set_cwp(CPUState *env1, int new_cwp)
1471{
1472 CPUState *saved_env;
1473
1474 saved_env = env;
1475 env = env1;
1476 set_cwp(new_cwp);
1477 env = saved_env;
1478}
1479
1480static target_ulong get_psr(void)
1481{
1482 helper_compute_psr();
1483
1484#if !defined (TARGET_SPARC64)
1485 return env->version | (env->psr & PSR_ICC) |
1486 (env->psref? PSR_EF : 0) |
1487 (env->psrpil << 8) |
1488 (env->psrs? PSR_S : 0) |
1489 (env->psrps? PSR_PS : 0) |
1490 (env->psret? PSR_ET : 0) | env->cwp;
1491#else
2aae2b8e 1492 return env->psr & PSR_ICC;
5a834bb4
BS		 1493#endif
1494}
1495
1496target_ulong cpu_get_psr(CPUState *env1)
1497{
1498 CPUState *saved_env;
1499 target_ulong ret;
1500
1501 saved_env = env;
1502 env = env1;
1503 ret = get_psr();
1504 env = saved_env;
1505 return ret;
1506}
1507
1508static void put_psr(target_ulong val)
1509{
1510 env->psr = val & PSR_ICC;
2aae2b8e 1511#if !defined (TARGET_SPARC64)
5a834bb4
BS		 1512 env->psref = (val & PSR_EF)? 1 : 0;
1513 env->psrpil = (val & PSR_PIL) >> 8;
2aae2b8e 1514#endif
5a834bb4
BS		 1515#if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
1516 cpu_check_irqs(env);
1517#endif
2aae2b8e 1518#if !defined (TARGET_SPARC64)
5a834bb4
BS		 1519 env->psrs = (val & PSR_S)? 1 : 0;
1520 env->psrps = (val & PSR_PS)? 1 : 0;
5a834bb4 1521 env->psret = (val & PSR_ET)? 1 : 0;
5a834bb4 1522 set_cwp(val & PSR_CWP);
2aae2b8e 1523#endif
5a834bb4
BS		 1524 env->cc_op = CC_OP_FLAGS;
1525}
1526
1527void cpu_put_psr(CPUState *env1, target_ulong val)
1528{
1529 CPUState *saved_env;
1530
1531 saved_env = env;
1532 env = env1;
1533 put_psr(val);
1534 env = saved_env;
1535}
1536
1537static int cwp_inc(int cwp)
1538{
1539 if (unlikely(cwp >= env->nwindows)) {
1540 cwp -= env->nwindows;
1541 }
1542 return cwp;
1543}
1544
1545int cpu_cwp_inc(CPUState *env1, int cwp)
1546{
1547 CPUState *saved_env;
1548 target_ulong ret;
1549
1550 saved_env = env;
1551 env = env1;
1552 ret = cwp_inc(cwp);
1553 env = saved_env;
1554 return ret;
1555}
1556
1557static int cwp_dec(int cwp)
1558{
1559 if (unlikely(cwp < 0)) {
1560 cwp += env->nwindows;
1561 }
1562 return cwp;
1563}
1564
1565int cpu_cwp_dec(CPUState *env1, int cwp)
1566{
1567 CPUState *saved_env;
1568 target_ulong ret;
1569
1570 saved_env = env;
1571 env = env1;
1572 ret = cwp_dec(cwp);
1573 env = saved_env;
1574 return ret;
1575}
1576
3475187d 1577#ifdef TARGET_SPARC64
714547bb 1578GEN_FCMPS(fcmps_fcc1, float32, 22, 0);
417454b0 1579GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
64a88d5d 1580GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
417454b0 1581
714547bb 1582GEN_FCMPS(fcmps_fcc2, float32, 24, 0);
417454b0 1583GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
64a88d5d 1584GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
417454b0 1585
714547bb 1586GEN_FCMPS(fcmps_fcc3, float32, 26, 0);
417454b0 1587GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
64a88d5d 1588GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
417454b0 1589
714547bb 1590GEN_FCMPS(fcmpes_fcc1, float32, 22, 1);
417454b0 1591GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
64a88d5d 1592GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
3475187d 1593
714547bb 1594GEN_FCMPS(fcmpes_fcc2, float32, 24, 1);
417454b0 1595GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
64a88d5d 1596GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
3475187d 1597
714547bb 1598GEN_FCMPS(fcmpes_fcc3, float32, 26, 1);
417454b0 1599GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
4e14008f
BS		 1600GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
1601#endif
714547bb 1602#undef GEN_FCMPS
3475187d 1603
77f193da
BS		 1604#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
1605 defined(DEBUG_MXCC)
952a328f
BS		 1606static void dump_mxcc(CPUState *env)
1607{
0bf9e31a
BS		 1608 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
1609 "\n",
77f193da
BS		 1610 env->mxccdata[0], env->mxccdata[1],
1611 env->mxccdata[2], env->mxccdata[3]);
0bf9e31a
BS		 1612 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
1613 "\n"
1614 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
1615 "\n",
77f193da
BS		 1616 env->mxccregs[0], env->mxccregs[1],
1617 env->mxccregs[2], env->mxccregs[3],
1618 env->mxccregs[4], env->mxccregs[5],
1619 env->mxccregs[6], env->mxccregs[7]);
952a328f
BS		 1620}
1621#endif
1622
1a2fb1c0
BS		 1623#if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
1624 && defined(DEBUG_ASI)
1625static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
1626 uint64_t r1)
8543e2cf
BS		 1627{
1628 switch (size)
1629 {
1630 case 1:
1a2fb1c0
BS		 1631 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
1632 addr, asi, r1 & 0xff);
8543e2cf
BS		 1633 break;
1634 case 2:
1a2fb1c0
BS		 1635 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
1636 addr, asi, r1 & 0xffff);
8543e2cf
BS		 1637 break;
1638 case 4:
1a2fb1c0
BS		 1639 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
1640 addr, asi, r1 & 0xffffffff);
8543e2cf
BS		 1641 break;
1642 case 8:
1a2fb1c0
BS		 1643 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
1644 addr, asi, r1);
8543e2cf
BS		 1645 break;
1646 }
1647}
1648#endif
1649
1a2fb1c0
BS		 1650#ifndef TARGET_SPARC64
1651#ifndef CONFIG_USER_ONLY
b04d9890
FC		 1652
1653
1654/* Leon3 cache control */
1655
60f356e8 1656static void leon3_cache_control_int(void)
b04d9890
FC		 1657{
1658 uint32_t state = 0;
1659
1660 if (env->cache_control & CACHE_CTRL_IF) {
1661 /* Instruction cache state */
1662 state = env->cache_control & CACHE_STATE_MASK;
1663 if (state == CACHE_ENABLED) {
1664 state = CACHE_FROZEN;
1665 DPRINTF_CACHE_CONTROL("Instruction cache: freeze\n");
1666 }
1667
1668 env->cache_control &= ~CACHE_STATE_MASK;
1669 env->cache_control |= state;
1670 }
1671
1672 if (env->cache_control & CACHE_CTRL_DF) {
1673 /* Data cache state */
1674 state = (env->cache_control >> 2) & CACHE_STATE_MASK;
1675 if (state == CACHE_ENABLED) {
1676 state = CACHE_FROZEN;
1677 DPRINTF_CACHE_CONTROL("Data cache: freeze\n");
1678 }
1679
1680 env->cache_control &= ~(CACHE_STATE_MASK << 2);
1681 env->cache_control |= (state << 2);
1682 }
1683}
1684
1685static void leon3_cache_control_st(target_ulong addr, uint64_t val, int size)
1686{
1687 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
1688 addr, val, size);
1689
1690 if (size != 4) {
1691 DPRINTF_CACHE_CONTROL("32bits only\n");
1692 return;
1693 }
1694
1695 switch (addr) {
1696 case 0x00: /* Cache control */
1697
1698 /* These values must always be read as zeros */
1699 val &= ~CACHE_CTRL_FD;
1700 val &= ~CACHE_CTRL_FI;
1701 val &= ~CACHE_CTRL_IB;
1702 val &= ~CACHE_CTRL_IP;
1703 val &= ~CACHE_CTRL_DP;
1704
1705 env->cache_control = val;
1706 break;
1707 case 0x04: /* Instruction cache configuration */
1708 case 0x08: /* Data cache configuration */
1709 /* Read Only */
1710 break;
1711 default:
1712 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
1713 break;
1714 };
1715}
1716
1717static uint64_t leon3_cache_control_ld(target_ulong addr, int size)
1718{
1719 uint64_t ret = 0;
1720
1721 if (size != 4) {
1722 DPRINTF_CACHE_CONTROL("32bits only\n");
1723 return 0;
1724 }
1725
1726 switch (addr) {
1727 case 0x00: /* Cache control */
1728 ret = env->cache_control;
1729 break;
1730
1731 /* Configuration registers are read and only always keep those
1732 predefined values */
1733
1734 case 0x04: /* Instruction cache configuration */
1735 ret = 0x10220000;
1736 break;
1737 case 0x08: /* Data cache configuration */
1738 ret = 0x18220000;
1739 break;
1740 default:
1741 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
1742 break;
1743 };
60f356e8 1744 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",
b04d9890
FC		 1745 addr, ret, size);
1746 return ret;
1747}
1748
60f356e8
FC		 1749void leon3_irq_manager(void *irq_manager, int intno)
1750{
1751 leon3_irq_ack(irq_manager, intno);
1752 leon3_cache_control_int();
1753}
1754
1a2fb1c0 1755uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
e8af50a3 1756{
1a2fb1c0 1757 uint64_t ret = 0;
8543e2cf 1758#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
1a2fb1c0 1759 uint32_t last_addr = addr;
952a328f 1760#endif
e80cfcfc 1761
c2bc0e38 1762 helper_check_align(addr, size - 1);
e80cfcfc 1763 switch (asi) {
b04d9890 1764 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
1a2fb1c0 1765 switch (addr) {
b04d9890
FC		 1766 case 0x00: /* Leon3 Cache Control */
1767 case 0x08: /* Leon3 Instruction Cache config */
1768 case 0x0C: /* Leon3 Date Cache config */
60f356e8
FC		 1769 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
1770 ret = leon3_cache_control_ld(addr, size);
1771 }
b04d9890 1772 break;
952a328f 1773 case 0x01c00a00: /* MXCC control register */
1a2fb1c0
BS		 1774 if (size == 8)
1775 ret = env->mxccregs[3];
1776 else
77f193da
BS		 1777 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1778 size);
952a328f
BS		 1779 break;
1780 case 0x01c00a04: /* MXCC control register */
1781 if (size == 4)
1782 ret = env->mxccregs[3];
1783 else
77f193da
BS		 1784 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1785 size);
952a328f 1786 break;
295db113
BS		 1787 case 0x01c00c00: /* Module reset register */
1788 if (size == 8) {
1a2fb1c0 1789 ret = env->mxccregs[5];
295db113
BS		 1790 // should we do something here?
1791 } else
77f193da
BS		 1792 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1793 size);
295db113 1794 break;
952a328f 1795 case 0x01c00f00: /* MBus port address register */
1a2fb1c0
BS		 1796 if (size == 8)
1797 ret = env->mxccregs[7];
1798 else
77f193da
BS		 1799 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1800 size);
952a328f
BS		 1801 break;
1802 default:
77f193da
BS		 1803 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
1804 size);
952a328f
BS		 1805 break;
1806 }
77f193da 1807 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
9827e450 1808 "addr = %08x -> ret = %" PRIx64 ","
1a2fb1c0 1809 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
952a328f
BS		 1810#ifdef DEBUG_MXCC
1811 dump_mxcc(env);
1812#endif
6c36d3fa 1813 break;
e8af50a3 1814 case 3: /* MMU probe */
0f8a249a
BS		 1815 {
1816 int mmulev;
1817
1a2fb1c0 1818 mmulev = (addr >> 8) & 15;
0f8a249a
BS		 1819 if (mmulev > 4)
1820 ret = 0;
1a2fb1c0
BS		 1821 else
1822 ret = mmu_probe(env, addr, mmulev);
1823 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
1824 addr, mmulev, ret);
0f8a249a
BS		 1825 }
1826 break;
e8af50a3 1827 case 4: /* read MMU regs */
0f8a249a 1828 {
1a2fb1c0 1829 int reg = (addr >> 8) & 0x1f;
3b46e624 1830
0f8a249a
BS		 1831 ret = env->mmuregs[reg];
1832 if (reg == 3) /* Fault status cleared on read */
3dd9a152
BS		 1833 env->mmuregs[3] = 0;
1834 else if (reg == 0x13) /* Fault status read */
1835 ret = env->mmuregs[3];
1836 else if (reg == 0x14) /* Fault address read */
1837 ret = env->mmuregs[4];
1a2fb1c0 1838 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
0f8a249a
BS		 1839 }
1840 break;
045380be
BS		 1841 case 5: // Turbosparc ITLB Diagnostic
1842 case 6: // Turbosparc DTLB Diagnostic
1843 case 7: // Turbosparc IOTLB Diagnostic
1844 break;
6c36d3fa
BS		 1845 case 9: /* Supervisor code access */
1846 switch(size) {
1847 case 1:
1a2fb1c0 1848 ret = ldub_code(addr);
6c36d3fa
BS		 1849 break;
1850 case 2:
a4e7dd52 1851 ret = lduw_code(addr);
6c36d3fa
BS		 1852 break;
1853 default:
1854 case 4:
a4e7dd52 1855 ret = ldl_code(addr);
6c36d3fa
BS		 1856 break;
1857 case 8:
a4e7dd52 1858 ret = ldq_code(addr);
6c36d3fa
BS		 1859 break;
1860 }
1861 break;
81ad8ba2
BS		 1862 case 0xa: /* User data access */
1863 switch(size) {
1864 case 1:
1a2fb1c0 1865 ret = ldub_user(addr);
81ad8ba2
BS		 1866 break;
1867 case 2:
a4e7dd52 1868 ret = lduw_user(addr);
81ad8ba2
BS		 1869 break;
1870 default:
1871 case 4:
a4e7dd52 1872 ret = ldl_user(addr);
81ad8ba2
BS		 1873 break;
1874 case 8:
a4e7dd52 1875 ret = ldq_user(addr);
81ad8ba2
BS		 1876 break;
1877 }
1878 break;
1879 case 0xb: /* Supervisor data access */
1880 switch(size) {
1881 case 1:
1a2fb1c0 1882 ret = ldub_kernel(addr);
81ad8ba2
BS		 1883 break;
1884 case 2:
a4e7dd52 1885 ret = lduw_kernel(addr);
81ad8ba2
BS		 1886 break;
1887 default:
1888 case 4:
a4e7dd52 1889 ret = ldl_kernel(addr);
81ad8ba2
BS		 1890 break;
1891 case 8:
a4e7dd52 1892 ret = ldq_kernel(addr);
81ad8ba2
BS		 1893 break;
1894 }
1895 break;
6c36d3fa
BS		 1896 case 0xc: /* I-cache tag */
1897 case 0xd: /* I-cache data */
1898 case 0xe: /* D-cache tag */
1899 case 0xf: /* D-cache data */
1900 break;
1901 case 0x20: /* MMU passthrough */
02aab46a
FB		 1902 switch(size) {
1903 case 1:
1a2fb1c0 1904 ret = ldub_phys(addr);
02aab46a
FB		 1905 break;
1906 case 2:
a4e7dd52 1907 ret = lduw_phys(addr);
02aab46a
FB		 1908 break;
1909 default:
1910 case 4:
a4e7dd52 1911 ret = ldl_phys(addr);
02aab46a 1912 break;
9e61bde5 1913 case 8:
a4e7dd52 1914 ret = ldq_phys(addr);
0f8a249a 1915 break;
02aab46a 1916 }
0f8a249a 1917 break;
7d85892b 1918 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
5dcb6b91
BS		 1919 switch(size) {
1920 case 1:
c227f099
AL		 1921 ret = ldub_phys((target_phys_addr_t)addr
1922 | ((target_phys_addr_t)(asi & 0xf) << 32));
5dcb6b91
BS		 1923 break;
1924 case 2:
c227f099
AL		 1925 ret = lduw_phys((target_phys_addr_t)addr
1926 | ((target_phys_addr_t)(asi & 0xf) << 32));
5dcb6b91
BS		 1927 break;
1928 default:
1929 case 4:
c227f099
AL		 1930 ret = ldl_phys((target_phys_addr_t)addr
1931 | ((target_phys_addr_t)(asi & 0xf) << 32));
5dcb6b91
BS		 1932 break;
1933 case 8:
c227f099
AL		 1934 ret = ldq_phys((target_phys_addr_t)addr
1935 | ((target_phys_addr_t)(asi & 0xf) << 32));
0f8a249a 1936 break;
5dcb6b91 1937 }
0f8a249a 1938 break;
045380be
BS		 1939 case 0x30: // Turbosparc secondary cache diagnostic
1940 case 0x31: // Turbosparc RAM snoop
1941 case 0x32: // Turbosparc page table descriptor diagnostic
666c87aa
BS		 1942 case 0x39: /* data cache diagnostic register */
1943 ret = 0;
1944 break;
4017190e
BS		 1945 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
1946 {
1947 int reg = (addr >> 8) & 3;
1948
1949 switch(reg) {
1950 case 0: /* Breakpoint Value (Addr) */
1951 ret = env->mmubpregs[reg];
1952 break;
1953 case 1: /* Breakpoint Mask */
1954 ret = env->mmubpregs[reg];
1955 break;
1956 case 2: /* Breakpoint Control */
1957 ret = env->mmubpregs[reg];
1958 break;
1959 case 3: /* Breakpoint Status */
1960 ret = env->mmubpregs[reg];
1961 env->mmubpregs[reg] = 0ULL;
1962 break;
1963 }
0bf9e31a
BS		 1964 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
1965 ret);
4017190e
BS		 1966 }
1967 break;
4d2c2b77
BS		 1968 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1969 ret = env->mmubpctrv;
1970 break;
1971 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1972 ret = env->mmubpctrc;
1973 break;
1974 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1975 ret = env->mmubpctrs;
1976 break;
1977 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1978 ret = env->mmubpaction;
1979 break;
045380be 1980 case 8: /* User code access, XXX */
e8af50a3 1981 default:
e18231a3 1982 do_unassigned_access(addr, 0, 0, asi, size);
0f8a249a
BS		 1983 ret = 0;
1984 break;
e8af50a3 1985 }
81ad8ba2
BS		 1986 if (sign) {
1987 switch(size) {
1988 case 1:
1a2fb1c0 1989 ret = (int8_t) ret;
e32664fb 1990 break;
81ad8ba2 1991 case 2:
1a2fb1c0
BS		 1992 ret = (int16_t) ret;
1993 break;
1994 case 4:
1995 ret = (int32_t) ret;
e32664fb 1996 break;
81ad8ba2 1997 default:
81ad8ba2
BS		 1998 break;
1999 }
2000 }
8543e2cf 2001#ifdef DEBUG_ASI
1a2fb1c0 2002 dump_asi("read ", last_addr, asi, size, ret);
8543e2cf 2003#endif
1a2fb1c0 2004 return ret;
e8af50a3
FB		 2005}
2006
1a2fb1c0 2007void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
e8af50a3 2008{
c2bc0e38 2009 helper_check_align(addr, size - 1);
e8af50a3 2010 switch(asi) {
b04d9890 2011 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
1a2fb1c0 2012 switch (addr) {
b04d9890
FC		 2013 case 0x00: /* Leon3 Cache Control */
2014 case 0x08: /* Leon3 Instruction Cache config */
2015 case 0x0C: /* Leon3 Date Cache config */
60f356e8
FC		 2016 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
2017 leon3_cache_control_st(addr, val, size);
2018 }
b04d9890
FC		 2019 break;
2020
952a328f
BS		 2021 case 0x01c00000: /* MXCC stream data register 0 */
2022 if (size == 8)
1a2fb1c0 2023 env->mxccdata[0] = val;
952a328f 2024 else
77f193da
BS		 2025 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
2026 size);
952a328f
BS		 2027 break;
2028 case 0x01c00008: /* MXCC stream data register 1 */
2029 if (size == 8)
1a2fb1c0 2030 env->mxccdata[1] = val;
952a328f 2031 else
77f193da
BS		 2032 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
2033 size);
952a328f
BS		 2034 break;
2035 case 0x01c00010: /* MXCC stream data register 2 */
2036 if (size == 8)
1a2fb1c0 2037 env->mxccdata[2] = val;
952a328f 2038 else
77f193da
BS		 2039 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
2040 size);
952a328f
BS		 2041 break;
2042 case 0x01c00018: /* MXCC stream data register 3 */
2043 if (size == 8)
1a2fb1c0 2044 env->mxccdata[3] = val;
952a328f 2045 else
77f193da
BS		 2046 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
2047 size);
952a328f
BS		 2048 break;
2049 case 0x01c00100: /* MXCC stream source */
2050 if (size == 8)
1a2fb1c0 2051 env->mxccregs[0] = val;
952a328f 2052 else
77f193da
BS		 2053 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
2054 size);
2055 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
2056 0);
2057 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
2058 8);
2059 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
2060 16);
2061 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
2062 24);
952a328f
BS		 2063 break;
2064 case 0x01c00200: /* MXCC stream destination */
2065 if (size == 8)
1a2fb1c0 2066 env->mxccregs[1] = val;
952a328f 2067 else
77f193da
BS		 2068 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
2069 size);
2070 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0,
2071 env->mxccdata[0]);
2072 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8,
2073 env->mxccdata[1]);
2074 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
2075 env->mxccdata[2]);
2076 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
2077 env->mxccdata[3]);
952a328f
BS		 2078 break;
2079 case 0x01c00a00: /* MXCC control register */
2080 if (size == 8)
1a2fb1c0 2081 env->mxccregs[3] = val;
952a328f 2082 else
77f193da
BS		 2083 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
2084 size);
952a328f
BS		 2085 break;
2086 case 0x01c00a04: /* MXCC control register */
2087 if (size == 4)
9f4576f0 2088 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
77f193da 2089 | val;
952a328f 2090 else
77f193da
BS		 2091 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
2092 size);
952a328f
BS		 2093 break;
2094 case 0x01c00e00: /* MXCC error register */
bbf7d96b 2095 // writing a 1 bit clears the error
952a328f 2096 if (size == 8)
1a2fb1c0 2097 env->mxccregs[6] &= ~val;
952a328f 2098 else
77f193da
BS		 2099 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
2100 size);
952a328f
BS		 2101 break;
2102 case 0x01c00f00: /* MBus port address register */
2103 if (size == 8)
1a2fb1c0 2104 env->mxccregs[7] = val;
952a328f 2105 else
77f193da
BS		 2106 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
2107 size);
952a328f
BS		 2108 break;
2109 default:
77f193da
BS		 2110 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
2111 size);
952a328f
BS		 2112 break;
2113 }
9827e450
BS		 2114 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
2115 asi, size, addr, val);
952a328f
BS		 2116#ifdef DEBUG_MXCC
2117 dump_mxcc(env);
2118#endif
6c36d3fa 2119 break;
e8af50a3 2120 case 3: /* MMU flush */
0f8a249a
BS		 2121 {
2122 int mmulev;
e80cfcfc 2123
1a2fb1c0 2124 mmulev = (addr >> 8) & 15;
952a328f 2125 DPRINTF_MMU("mmu flush level %d\n", mmulev);
0f8a249a
BS		 2126 switch (mmulev) {
2127 case 0: // flush page
1a2fb1c0 2128 tlb_flush_page(env, addr & 0xfffff000);
0f8a249a
BS		 2129 break;
2130 case 1: // flush segment (256k)
2131 case 2: // flush region (16M)
2132 case 3: // flush context (4G)
2133 case 4: // flush entire
2134 tlb_flush(env, 1);
2135 break;
2136 default:
2137 break;
2138 }
55754d9e 2139#ifdef DEBUG_MMU
d41160a3 2140 dump_mmu(stdout, fprintf, env);
55754d9e 2141#endif
0f8a249a 2142 }
8543e2cf 2143 break;
e8af50a3 2144 case 4: /* write MMU regs */
0f8a249a 2145 {
1a2fb1c0 2146 int reg = (addr >> 8) & 0x1f;
0f8a249a 2147 uint32_t oldreg;
3b46e624 2148
0f8a249a 2149 oldreg = env->mmuregs[reg];
55754d9e 2150 switch(reg) {
3deaeab7 2151 case 0: // Control Register
3dd9a152 2152 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
1a2fb1c0 2153 (val & 0x00ffffff);
0f8a249a
BS		 2154 // Mappings generated during no-fault mode or MMU
2155 // disabled mode are invalid in normal mode
5578ceab
BS		 2156 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
2157 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm)))
55754d9e
FB		 2158 tlb_flush(env, 1);
2159 break;
3deaeab7 2160 case 1: // Context Table Pointer Register
5578ceab 2161 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
3deaeab7
BS		 2162 break;
2163 case 2: // Context Register
5578ceab 2164 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
55754d9e
FB		 2165 if (oldreg != env->mmuregs[reg]) {
2166 /* we flush when the MMU context changes because
2167 QEMU has no MMU context support */
2168 tlb_flush(env, 1);
2169 }
2170 break;
3deaeab7
BS		 2171 case 3: // Synchronous Fault Status Register with Clear
2172 case 4: // Synchronous Fault Address Register
2173 break;
2174 case 0x10: // TLB Replacement Control Register
5578ceab 2175 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
55754d9e 2176 break;
3deaeab7 2177 case 0x13: // Synchronous Fault Status Register with Read and Clear
5578ceab 2178 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
3dd9a152 2179 break;
3deaeab7 2180 case 0x14: // Synchronous Fault Address Register
1a2fb1c0 2181 env->mmuregs[4] = val;
3dd9a152 2182 break;
55754d9e 2183 default:
1a2fb1c0 2184 env->mmuregs[reg] = val;
55754d9e
FB		 2185 break;
2186 }
55754d9e 2187 if (oldreg != env->mmuregs[reg]) {
77f193da
BS		 2188 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
2189 reg, oldreg, env->mmuregs[reg]);
55754d9e 2190 }
952a328f 2191#ifdef DEBUG_MMU
d41160a3 2192 dump_mmu(stdout, fprintf, env);
55754d9e 2193#endif
0f8a249a 2194 }
8543e2cf 2195 break;
045380be
BS		 2196 case 5: // Turbosparc ITLB Diagnostic
2197 case 6: // Turbosparc DTLB Diagnostic
2198 case 7: // Turbosparc IOTLB Diagnostic
2199 break;
81ad8ba2
BS		 2200 case 0xa: /* User data access */
2201 switch(size) {
2202 case 1:
1a2fb1c0 2203 stb_user(addr, val);
81ad8ba2
BS		 2204 break;
2205 case 2:
a4e7dd52 2206 stw_user(addr, val);
81ad8ba2
BS		 2207 break;
2208 default:
2209 case 4:
a4e7dd52 2210 stl_user(addr, val);
81ad8ba2
BS		 2211 break;
2212 case 8:
a4e7dd52 2213 stq_user(addr, val);
81ad8ba2
BS		 2214 break;
2215 }
2216 break;
2217 case 0xb: /* Supervisor data access */
2218 switch(size) {
2219 case 1:
1a2fb1c0 2220 stb_kernel(addr, val);
81ad8ba2
BS		 2221 break;
2222 case 2:
a4e7dd52 2223 stw_kernel(addr, val);
81ad8ba2
BS		 2224 break;
2225 default:
2226 case 4:
a4e7dd52 2227 stl_kernel(addr, val);
81ad8ba2
BS		 2228 break;
2229 case 8:
a4e7dd52 2230 stq_kernel(addr, val);
81ad8ba2
BS		 2231 break;
2232 }
2233 break;
6c36d3fa
BS		 2234 case 0xc: /* I-cache tag */
2235 case 0xd: /* I-cache data */
2236 case 0xe: /* D-cache tag */
2237 case 0xf: /* D-cache data */
2238 case 0x10: /* I/D-cache flush page */
2239 case 0x11: /* I/D-cache flush segment */
2240 case 0x12: /* I/D-cache flush region */
2241 case 0x13: /* I/D-cache flush context */
2242 case 0x14: /* I/D-cache flush user */
2243 break;
e80cfcfc 2244 case 0x17: /* Block copy, sta access */
0f8a249a 2245 {
1a2fb1c0
BS		 2246 // val = src
2247 // addr = dst
0f8a249a 2248 // copy 32 bytes
6c36d3fa 2249 unsigned int i;
1a2fb1c0 2250 uint32_t src = val & ~3, dst = addr & ~3, temp;
3b46e624 2251
6c36d3fa
BS		 2252 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
2253 temp = ldl_kernel(src);
2254 stl_kernel(dst, temp);
2255 }
0f8a249a 2256 }
8543e2cf 2257 break;
e80cfcfc 2258 case 0x1f: /* Block fill, stda access */
0f8a249a 2259 {
1a2fb1c0
BS		 2260 // addr = dst
2261 // fill 32 bytes with val
6c36d3fa 2262 unsigned int i;
1a2fb1c0 2263 uint32_t dst = addr & 7;
6c36d3fa
BS		 2264
2265 for (i = 0; i < 32; i += 8, dst += 8)
2266 stq_kernel(dst, val);
0f8a249a 2267 }
8543e2cf 2268 break;
6c36d3fa 2269 case 0x20: /* MMU passthrough */
0f8a249a 2270 {
02aab46a
FB		 2271 switch(size) {
2272 case 1:
1a2fb1c0 2273 stb_phys(addr, val);
02aab46a
FB		 2274 break;
2275 case 2:
a4e7dd52 2276 stw_phys(addr, val);
02aab46a
FB		 2277 break;
2278 case 4:
2279 default:
a4e7dd52 2280 stl_phys(addr, val);
02aab46a 2281 break;
9e61bde5 2282 case 8:
a4e7dd52 2283 stq_phys(addr, val);
9e61bde5 2284 break;
02aab46a 2285 }
0f8a249a 2286 }
8543e2cf 2287 break;
045380be 2288 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
0f8a249a 2289 {
5dcb6b91
BS		 2290 switch(size) {
2291 case 1:
c227f099
AL		 2292 stb_phys((target_phys_addr_t)addr
2293 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 2294 break;
2295 case 2:
c227f099
AL		 2296 stw_phys((target_phys_addr_t)addr
2297 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 2298 break;
2299 case 4:
2300 default:
c227f099
AL		 2301 stl_phys((target_phys_addr_t)addr
2302 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 2303 break;
2304 case 8:
c227f099
AL		 2305 stq_phys((target_phys_addr_t)addr
2306 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 2307 break;
2308 }
0f8a249a 2309 }
8543e2cf 2310 break;
045380be
BS		 2311 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
2312 case 0x31: // store buffer data, Ross RT620 I-cache flush or
2313 // Turbosparc snoop RAM
77f193da
BS		 2314 case 0x32: // store buffer control or Turbosparc page table
2315 // descriptor diagnostic
6c36d3fa
BS		 2316 case 0x36: /* I-cache flash clear */
2317 case 0x37: /* D-cache flash clear */
2318 break;
4017190e
BS		 2319 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
2320 {
2321 int reg = (addr >> 8) & 3;
2322
2323 switch(reg) {
2324 case 0: /* Breakpoint Value (Addr) */
2325 env->mmubpregs[reg] = (val & 0xfffffffffULL);
2326 break;
2327 case 1: /* Breakpoint Mask */
2328 env->mmubpregs[reg] = (val & 0xfffffffffULL);
2329 break;
2330 case 2: /* Breakpoint Control */
2331 env->mmubpregs[reg] = (val & 0x7fULL);
2332 break;
2333 case 3: /* Breakpoint Status */
2334 env->mmubpregs[reg] = (val & 0xfULL);
2335 break;
2336 }
0bf9e31a 2337 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
4017190e
BS		 2338 env->mmuregs[reg]);
2339 }
2340 break;
4d2c2b77
BS		 2341 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
2342 env->mmubpctrv = val & 0xffffffff;
2343 break;
2344 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
2345 env->mmubpctrc = val & 0x3;
2346 break;
2347 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
2348 env->mmubpctrs = val & 0x3;
2349 break;
2350 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
2351 env->mmubpaction = val & 0x1fff;
2352 break;
045380be 2353 case 8: /* User code access, XXX */
6c36d3fa 2354 case 9: /* Supervisor code access, XXX */
e8af50a3 2355 default:
e18231a3 2356 do_unassigned_access(addr, 1, 0, asi, size);
8543e2cf 2357 break;
e8af50a3 2358 }
8543e2cf 2359#ifdef DEBUG_ASI
1a2fb1c0 2360 dump_asi("write", addr, asi, size, val);
8543e2cf 2361#endif
e8af50a3
FB		 2362}
2363
81ad8ba2
BS		 2364#endif /* CONFIG_USER_ONLY */
2365#else /* TARGET_SPARC64 */
2366
2367#ifdef CONFIG_USER_ONLY
1a2fb1c0 2368uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
81ad8ba2
BS		 2369{
2370 uint64_t ret = 0;
1a2fb1c0
BS		 2371#if defined(DEBUG_ASI)
2372 target_ulong last_addr = addr;
2373#endif
81ad8ba2
BS		 2374
2375 if (asi < 0x80)
2376 raise_exception(TT_PRIV_ACT);
2377
c2bc0e38 2378 helper_check_align(addr, size - 1);
1295001c 2379 addr = asi_address_mask(env, asi, addr);
c2bc0e38 2380
81ad8ba2 2381 switch (asi) {
81ad8ba2 2382 case 0x82: // Primary no-fault
81ad8ba2 2383 case 0x8a: // Primary no-fault LE
e83ce550
BS		 2384 if (page_check_range(addr, size, PAGE_READ) == -1) {
2385#ifdef DEBUG_ASI
2386 dump_asi("read ", last_addr, asi, size, ret);
2387#endif
2388 return 0;
2389 }
2390 // Fall through
2391 case 0x80: // Primary
2392 case 0x88: // Primary LE
81ad8ba2
BS		 2393 {
2394 switch(size) {
2395 case 1:
1a2fb1c0 2396 ret = ldub_raw(addr);
81ad8ba2
BS		 2397 break;
2398 case 2:
a4e7dd52 2399 ret = lduw_raw(addr);
81ad8ba2
BS		 2400 break;
2401 case 4:
a4e7dd52 2402 ret = ldl_raw(addr);
81ad8ba2
BS		 2403 break;
2404 default:
2405 case 8:
a4e7dd52 2406 ret = ldq_raw(addr);
81ad8ba2
BS		 2407 break;
2408 }
2409 }
2410 break;
81ad8ba2 2411 case 0x83: // Secondary no-fault
81ad8ba2 2412 case 0x8b: // Secondary no-fault LE
e83ce550
BS		 2413 if (page_check_range(addr, size, PAGE_READ) == -1) {
2414#ifdef DEBUG_ASI
2415 dump_asi("read ", last_addr, asi, size, ret);
2416#endif
2417 return 0;
2418 }
2419 // Fall through
2420 case 0x81: // Secondary
2421 case 0x89: // Secondary LE
81ad8ba2
BS		 2422 // XXX
2423 break;
2424 default:
2425 break;
2426 }
2427
2428 /* Convert from little endian */
2429 switch (asi) {
2430 case 0x88: // Primary LE
2431 case 0x89: // Secondary LE
2432 case 0x8a: // Primary no-fault LE
2433 case 0x8b: // Secondary no-fault LE
2434 switch(size) {
2435 case 2:
2436 ret = bswap16(ret);
e32664fb 2437 break;
81ad8ba2
BS		 2438 case 4:
2439 ret = bswap32(ret);
e32664fb 2440 break;
81ad8ba2
BS		 2441 case 8:
2442 ret = bswap64(ret);
e32664fb 2443 break;
81ad8ba2
BS		 2444 default:
2445 break;
2446 }
2447 default:
2448 break;
2449 }
2450
2451 /* Convert to signed number */
2452 if (sign) {
2453 switch(size) {
2454 case 1:
2455 ret = (int8_t) ret;
e32664fb 2456 break;
81ad8ba2
BS		 2457 case 2:
2458 ret = (int16_t) ret;
e32664fb 2459 break;
81ad8ba2
BS		 2460 case 4:
2461 ret = (int32_t) ret;
e32664fb 2462 break;
81ad8ba2
BS		 2463 default:
2464 break;
2465 }
2466 }
1a2fb1c0
BS		 2467#ifdef DEBUG_ASI
2468 dump_asi("read ", last_addr, asi, size, ret);
2469#endif
2470 return ret;
81ad8ba2
BS		 2471}
2472
1a2fb1c0 2473void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
81ad8ba2 2474{
1a2fb1c0
BS		 2475#ifdef DEBUG_ASI
2476 dump_asi("write", addr, asi, size, val);
2477#endif
81ad8ba2
BS		 2478 if (asi < 0x80)
2479 raise_exception(TT_PRIV_ACT);
2480
c2bc0e38 2481 helper_check_align(addr, size - 1);
1295001c 2482 addr = asi_address_mask(env, asi, addr);
c2bc0e38 2483
81ad8ba2
BS		 2484 /* Convert to little endian */
2485 switch (asi) {
2486 case 0x88: // Primary LE
2487 case 0x89: // Secondary LE
2488 switch(size) {
2489 case 2:
5b0f0bec 2490 val = bswap16(val);
e32664fb 2491 break;
81ad8ba2 2492 case 4:
5b0f0bec 2493 val = bswap32(val);
e32664fb 2494 break;
81ad8ba2 2495 case 8:
5b0f0bec 2496 val = bswap64(val);
e32664fb 2497 break;
81ad8ba2
BS		 2498 default:
2499 break;
2500 }
2501 default:
2502 break;
2503 }
2504
2505 switch(asi) {
2506 case 0x80: // Primary
2507 case 0x88: // Primary LE
2508 {
2509 switch(size) {
2510 case 1:
1a2fb1c0 2511 stb_raw(addr, val);
81ad8ba2
BS		 2512 break;
2513 case 2:
a4e7dd52 2514 stw_raw(addr, val);
81ad8ba2
BS		 2515 break;
2516 case 4:
a4e7dd52 2517 stl_raw(addr, val);
81ad8ba2
BS		 2518 break;
2519 case 8:
2520 default:
a4e7dd52 2521 stq_raw(addr, val);
81ad8ba2
BS		 2522 break;
2523 }
2524 }
2525 break;
2526 case 0x81: // Secondary
2527 case 0x89: // Secondary LE
2528 // XXX
2529 return;
2530
2531 case 0x82: // Primary no-fault, RO
2532 case 0x83: // Secondary no-fault, RO
2533 case 0x8a: // Primary no-fault LE, RO
2534 case 0x8b: // Secondary no-fault LE, RO
2535 default:
e18231a3 2536 do_unassigned_access(addr, 1, 0, 1, size);
81ad8ba2
BS		 2537 return;
2538 }
2539}
2540
2541#else /* CONFIG_USER_ONLY */
3475187d 2542
1a2fb1c0 2543uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
3475187d 2544{
83469015 2545 uint64_t ret = 0;
1a2fb1c0
BS		 2546#if defined(DEBUG_ASI)
2547 target_ulong last_addr = addr;
2548#endif
3475187d 2549
01b5d4e5
IK		 2550 asi &= 0xff;
2551
6f27aba6 2552 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2aae2b8e 2553 || (cpu_has_hypervisor(env)
5578ceab 2554 && asi >= 0x30 && asi < 0x80
fb79ceb9 2555 && !(env->hpstate & HS_PRIV)))
0f8a249a 2556 raise_exception(TT_PRIV_ACT);
3475187d 2557
c2bc0e38 2558 helper_check_align(addr, size - 1);
1295001c
IK		 2559 addr = asi_address_mask(env, asi, addr);
2560
3475187d 2561 switch (asi) {
e83ce550
BS		 2562 case 0x82: // Primary no-fault
2563 case 0x8a: // Primary no-fault LE
2065061e
IK		 2564 case 0x83: // Secondary no-fault
2565 case 0x8b: // Secondary no-fault LE
2566 {
2567 /* secondary space access has lowest asi bit equal to 1 */
2568 int access_mmu_idx = ( asi & 1 ) ? MMU_KERNEL_IDX
2569 : MMU_KERNEL_SECONDARY_IDX;
2570
2571 if (cpu_get_phys_page_nofault(env, addr, access_mmu_idx) == -1ULL) {
e83ce550 2572#ifdef DEBUG_ASI
2065061e 2573 dump_asi("read ", last_addr, asi, size, ret);
e83ce550 2574#endif
2065061e
IK		 2575 return 0;
2576 }
e83ce550
BS		 2577 }
2578 // Fall through
81ad8ba2 2579 case 0x10: // As if user primary
2065061e 2580 case 0x11: // As if user secondary
81ad8ba2 2581 case 0x18: // As if user primary LE
2065061e 2582 case 0x19: // As if user secondary LE
81ad8ba2 2583 case 0x80: // Primary
2065061e 2584 case 0x81: // Secondary
81ad8ba2 2585 case 0x88: // Primary LE
2065061e 2586 case 0x89: // Secondary LE
c99657d3
BS		 2587 case 0xe2: // UA2007 Primary block init
2588 case 0xe3: // UA2007 Secondary block init
81ad8ba2 2589 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
2aae2b8e 2590 if (cpu_hypervisor_mode(env)) {
6f27aba6
BS		 2591 switch(size) {
2592 case 1:
1a2fb1c0 2593 ret = ldub_hypv(addr);
6f27aba6
BS		 2594 break;
2595 case 2:
a4e7dd52 2596 ret = lduw_hypv(addr);
6f27aba6
BS		 2597 break;
2598 case 4:
a4e7dd52 2599 ret = ldl_hypv(addr);
6f27aba6
BS		 2600 break;
2601 default:
2602 case 8:
a4e7dd52 2603 ret = ldq_hypv(addr);
6f27aba6
BS		 2604 break;
2605 }
2606 } else {
2065061e
IK		 2607 /* secondary space access has lowest asi bit equal to 1 */
2608 if (asi & 1) {
2609 switch(size) {
2610 case 1:
2611 ret = ldub_kernel_secondary(addr);
2612 break;
2613 case 2:
2614 ret = lduw_kernel_secondary(addr);
2615 break;
2616 case 4:
2617 ret = ldl_kernel_secondary(addr);
2618 break;
2619 default:
2620 case 8:
2621 ret = ldq_kernel_secondary(addr);
2622 break;
2623 }
2624 } else {
2625 switch(size) {
2626 case 1:
2627 ret = ldub_kernel(addr);
2628 break;
2629 case 2:
2630 ret = lduw_kernel(addr);
2631 break;
2632 case 4:
2633 ret = ldl_kernel(addr);
2634 break;
2635 default:
2636 case 8:
2637 ret = ldq_kernel(addr);
2638 break;
2639 }
2640 }
2641 }
2642 } else {
2643 /* secondary space access has lowest asi bit equal to 1 */
2644 if (asi & 1) {
6f27aba6
BS		 2645 switch(size) {
2646 case 1:
2065061e 2647 ret = ldub_user_secondary(addr);
6f27aba6
BS		 2648 break;
2649 case 2:
2065061e 2650 ret = lduw_user_secondary(addr);
6f27aba6
BS		 2651 break;
2652 case 4:
2065061e 2653 ret = ldl_user_secondary(addr);
6f27aba6
BS		 2654 break;
2655 default:
2656 case 8:
2065061e
IK		 2657 ret = ldq_user_secondary(addr);
2658 break;
2659 }
2660 } else {
2661 switch(size) {
2662 case 1:
2663 ret = ldub_user(addr);
2664 break;
2665 case 2:
2666 ret = lduw_user(addr);
2667 break;
2668 case 4:
2669 ret = ldl_user(addr);
2670 break;
2671 default:
2672 case 8:
2673 ret = ldq_user(addr);
6f27aba6
BS		 2674 break;
2675 }
81ad8ba2
BS		 2676 }
2677 }
2678 break;
3475187d
FB		 2679 case 0x14: // Bypass
2680 case 0x15: // Bypass, non-cacheable
81ad8ba2
BS		 2681 case 0x1c: // Bypass LE
2682 case 0x1d: // Bypass, non-cacheable LE
0f8a249a 2683 {
02aab46a
FB		 2684 switch(size) {
2685 case 1:
1a2fb1c0 2686 ret = ldub_phys(addr);
02aab46a
FB		 2687 break;
2688 case 2:
a4e7dd52 2689 ret = lduw_phys(addr);
02aab46a
FB		 2690 break;
2691 case 4:
a4e7dd52 2692 ret = ldl_phys(addr);
02aab46a
FB		 2693 break;
2694 default:
2695 case 8:
a4e7dd52 2696 ret = ldq_phys(addr);
02aab46a
FB		 2697 break;
2698 }
0f8a249a
BS		 2699 break;
2700 }
db166940
BS		 2701 case 0x24: // Nucleus quad LDD 128 bit atomic
2702 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2703 // Only ldda allowed
2704 raise_exception(TT_ILL_INSN);
2705 return 0;
83469015
FB		 2706 case 0x04: // Nucleus
2707 case 0x0c: // Nucleus Little Endian (LE)
2065061e
IK		 2708 {
2709 switch(size) {
2710 case 1:
2711 ret = ldub_nucleus(addr);
2712 break;
2713 case 2:
2714 ret = lduw_nucleus(addr);
2715 break;
2716 case 4:
2717 ret = ldl_nucleus(addr);
2718 break;
2719 default:
2720 case 8:
2721 ret = ldq_nucleus(addr);
2722 break;
2723 }
2724 break;
2725 }
83469015 2726 case 0x4a: // UPA config
0f8a249a
BS		 2727 // XXX
2728 break;
3475187d 2729 case 0x45: // LSU
0f8a249a
BS		 2730 ret = env->lsu;
2731 break;
3475187d 2732 case 0x50: // I-MMU regs
0f8a249a 2733 {
1a2fb1c0 2734 int reg = (addr >> 3) & 0xf;
3475187d 2735
697a77e6
IK		 2736 if (reg == 0) {
2737 // I-TSB Tag Target register
6e8e7d4c 2738 ret = ultrasparc_tag_target(env->immu.tag_access);
697a77e6
IK		 2739 } else {
2740 ret = env->immuregs[reg];
2741 }
2742
0f8a249a
BS		 2743 break;
2744 }
3475187d 2745 case 0x51: // I-MMU 8k TSB pointer
697a77e6
IK		 2746 {
2747 // env->immuregs[5] holds I-MMU TSB register value
2748 // env->immuregs[6] holds I-MMU Tag Access register value
6e8e7d4c 2749 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
697a77e6
IK		 2750 8*1024);
2751 break;
2752 }
3475187d 2753 case 0x52: // I-MMU 64k TSB pointer
697a77e6
IK		 2754 {
2755 // env->immuregs[5] holds I-MMU TSB register value
2756 // env->immuregs[6] holds I-MMU Tag Access register value
6e8e7d4c 2757 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
697a77e6
IK		 2758 64*1024);
2759 break;
2760 }
a5a52cf2
BS		 2761 case 0x55: // I-MMU data access
2762 {
2763 int reg = (addr >> 3) & 0x3f;
2764
6e8e7d4c 2765 ret = env->itlb[reg].tte;
a5a52cf2
BS		 2766 break;
2767 }
83469015 2768 case 0x56: // I-MMU tag read
0f8a249a 2769 {
43e9e742 2770 int reg = (addr >> 3) & 0x3f;
0f8a249a 2771
6e8e7d4c 2772 ret = env->itlb[reg].tag;
0f8a249a
BS		 2773 break;
2774 }
3475187d 2775 case 0x58: // D-MMU regs
0f8a249a 2776 {
1a2fb1c0 2777 int reg = (addr >> 3) & 0xf;
3475187d 2778
697a77e6
IK		 2779 if (reg == 0) {
2780 // D-TSB Tag Target register
6e8e7d4c 2781 ret = ultrasparc_tag_target(env->dmmu.tag_access);
697a77e6
IK		 2782 } else {
2783 ret = env->dmmuregs[reg];
2784 }
2785 break;
2786 }
2787 case 0x59: // D-MMU 8k TSB pointer
2788 {
2789 // env->dmmuregs[5] holds D-MMU TSB register value
2790 // env->dmmuregs[6] holds D-MMU Tag Access register value
6e8e7d4c 2791 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
697a77e6
IK		 2792 8*1024);
2793 break;
2794 }
2795 case 0x5a: // D-MMU 64k TSB pointer
2796 {
2797 // env->dmmuregs[5] holds D-MMU TSB register value
2798 // env->dmmuregs[6] holds D-MMU Tag Access register value
6e8e7d4c 2799 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
697a77e6 2800 64*1024);
0f8a249a
BS		 2801 break;
2802 }
a5a52cf2
BS		 2803 case 0x5d: // D-MMU data access
2804 {
2805 int reg = (addr >> 3) & 0x3f;
2806
6e8e7d4c 2807 ret = env->dtlb[reg].tte;
a5a52cf2
BS		 2808 break;
2809 }
83469015 2810 case 0x5e: // D-MMU tag read
0f8a249a 2811 {
43e9e742 2812 int reg = (addr >> 3) & 0x3f;
0f8a249a 2813
6e8e7d4c 2814 ret = env->dtlb[reg].tag;
0f8a249a
BS		 2815 break;
2816 }
f7350b47
BS		 2817 case 0x46: // D-cache data
2818 case 0x47: // D-cache tag access
a5a52cf2
BS		 2819 case 0x4b: // E-cache error enable
2820 case 0x4c: // E-cache asynchronous fault status
2821 case 0x4d: // E-cache asynchronous fault address
f7350b47
BS		 2822 case 0x4e: // E-cache tag data
2823 case 0x66: // I-cache instruction access
2824 case 0x67: // I-cache tag access
2825 case 0x6e: // I-cache predecode
2826 case 0x6f: // I-cache LRU etc.
2827 case 0x76: // E-cache tag
2828 case 0x7e: // E-cache tag
2829 break;
3475187d 2830 case 0x5b: // D-MMU data pointer
83469015
FB		 2831 case 0x48: // Interrupt dispatch, RO
2832 case 0x49: // Interrupt data receive
2833 case 0x7f: // Incoming interrupt vector, RO
0f8a249a
BS		 2834 // XXX
2835 break;
3475187d
FB		 2836 case 0x54: // I-MMU data in, WO
2837 case 0x57: // I-MMU demap, WO
2838 case 0x5c: // D-MMU data in, WO
2839 case 0x5f: // D-MMU demap, WO
83469015 2840 case 0x77: // Interrupt vector, WO
3475187d 2841 default:
e18231a3 2842 do_unassigned_access(addr, 0, 0, 1, size);
0f8a249a
BS		 2843 ret = 0;
2844 break;
3475187d 2845 }
81ad8ba2
BS		 2846
2847 /* Convert from little endian */
2848 switch (asi) {
2849 case 0x0c: // Nucleus Little Endian (LE)
2850 case 0x18: // As if user primary LE
2851 case 0x19: // As if user secondary LE
2852 case 0x1c: // Bypass LE
2853 case 0x1d: // Bypass, non-cacheable LE
2854 case 0x88: // Primary LE
2855 case 0x89: // Secondary LE
2856 case 0x8a: // Primary no-fault LE
2857 case 0x8b: // Secondary no-fault LE
2858 switch(size) {
2859 case 2:
2860 ret = bswap16(ret);
e32664fb 2861 break;
81ad8ba2
BS		 2862 case 4:
2863 ret = bswap32(ret);
e32664fb 2864 break;
81ad8ba2
BS		 2865 case 8:
2866 ret = bswap64(ret);
e32664fb 2867 break;
81ad8ba2
BS		 2868 default:
2869 break;
2870 }
2871 default:
2872 break;
2873 }
2874
2875 /* Convert to signed number */
2876 if (sign) {
2877 switch(size) {
2878 case 1:
2879 ret = (int8_t) ret;
e32664fb 2880 break;
81ad8ba2
BS		 2881 case 2:
2882 ret = (int16_t) ret;
e32664fb 2883 break;
81ad8ba2
BS		 2884 case 4:
2885 ret = (int32_t) ret;
e32664fb 2886 break;
81ad8ba2
BS		 2887 default:
2888 break;
2889 }
2890 }
1a2fb1c0
BS		 2891#ifdef DEBUG_ASI
2892 dump_asi("read ", last_addr, asi, size, ret);
2893#endif
2894 return ret;
3475187d
FB		 2895}
2896
1a2fb1c0 2897void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
3475187d 2898{
1a2fb1c0
BS		 2899#ifdef DEBUG_ASI
2900 dump_asi("write", addr, asi, size, val);
2901#endif
01b5d4e5
IK		 2902
2903 asi &= 0xff;
2904
6f27aba6 2905 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2aae2b8e 2906 || (cpu_has_hypervisor(env)
5578ceab 2907 && asi >= 0x30 && asi < 0x80
fb79ceb9 2908 && !(env->hpstate & HS_PRIV)))
0f8a249a 2909 raise_exception(TT_PRIV_ACT);
3475187d 2910
c2bc0e38 2911 helper_check_align(addr, size - 1);
1295001c
IK		 2912 addr = asi_address_mask(env, asi, addr);
2913
81ad8ba2
BS		 2914 /* Convert to little endian */
2915 switch (asi) {
2916 case 0x0c: // Nucleus Little Endian (LE)
2917 case 0x18: // As if user primary LE
2918 case 0x19: // As if user secondary LE
2919 case 0x1c: // Bypass LE
2920 case 0x1d: // Bypass, non-cacheable LE
81ad8ba2
BS		 2921 case 0x88: // Primary LE
2922 case 0x89: // Secondary LE
2923 switch(size) {
2924 case 2:
5b0f0bec 2925 val = bswap16(val);
e32664fb 2926 break;
81ad8ba2 2927 case 4:
5b0f0bec 2928 val = bswap32(val);
e32664fb 2929 break;
81ad8ba2 2930 case 8:
5b0f0bec 2931 val = bswap64(val);
e32664fb 2932 break;
81ad8ba2
BS		 2933 default:
2934 break;
2935 }
2936 default:
2937 break;
2938 }
2939
3475187d 2940 switch(asi) {
81ad8ba2 2941 case 0x10: // As if user primary
2065061e 2942 case 0x11: // As if user secondary
81ad8ba2 2943 case 0x18: // As if user primary LE
2065061e 2944 case 0x19: // As if user secondary LE
81ad8ba2 2945 case 0x80: // Primary
2065061e 2946 case 0x81: // Secondary
81ad8ba2 2947 case 0x88: // Primary LE
2065061e 2948 case 0x89: // Secondary LE
c99657d3
BS		 2949 case 0xe2: // UA2007 Primary block init
2950 case 0xe3: // UA2007 Secondary block init
81ad8ba2 2951 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
2aae2b8e 2952 if (cpu_hypervisor_mode(env)) {
6f27aba6
BS		 2953 switch(size) {
2954 case 1:
1a2fb1c0 2955 stb_hypv(addr, val);
6f27aba6
BS		 2956 break;
2957 case 2:
a4e7dd52 2958 stw_hypv(addr, val);
6f27aba6
BS		 2959 break;
2960 case 4:
a4e7dd52 2961 stl_hypv(addr, val);
6f27aba6
BS		 2962 break;
2963 case 8:
2964 default:
a4e7dd52 2965 stq_hypv(addr, val);
6f27aba6
BS		 2966 break;
2967 }
2968 } else {
2065061e
IK		 2969 /* secondary space access has lowest asi bit equal to 1 */
2970 if (asi & 1) {
2971 switch(size) {
2972 case 1:
2973 stb_kernel_secondary(addr, val);
2974 break;
2975 case 2:
2976 stw_kernel_secondary(addr, val);
2977 break;
2978 case 4:
2979 stl_kernel_secondary(addr, val);
2980 break;
2981 case 8:
2982 default:
2983 stq_kernel_secondary(addr, val);
2984 break;
2985 }
2986 } else {
2987 switch(size) {
2988 case 1:
2989 stb_kernel(addr, val);
2990 break;
2991 case 2:
2992 stw_kernel(addr, val);
2993 break;
2994 case 4:
2995 stl_kernel(addr, val);
2996 break;
2997 case 8:
2998 default:
2999 stq_kernel(addr, val);
3000 break;
3001 }
3002 }
3003 }
3004 } else {
3005 /* secondary space access has lowest asi bit equal to 1 */
3006 if (asi & 1) {
6f27aba6
BS		 3007 switch(size) {
3008 case 1:
2065061e 3009 stb_user_secondary(addr, val);
6f27aba6
BS		 3010 break;
3011 case 2:
2065061e 3012 stw_user_secondary(addr, val);
6f27aba6
BS		 3013 break;
3014 case 4:
2065061e 3015 stl_user_secondary(addr, val);
6f27aba6
BS		 3016 break;
3017 case 8:
3018 default:
2065061e
IK		 3019 stq_user_secondary(addr, val);
3020 break;
3021 }
3022 } else {
3023 switch(size) {
3024 case 1:
3025 stb_user(addr, val);
3026 break;
3027 case 2:
3028 stw_user(addr, val);
3029 break;
3030 case 4:
3031 stl_user(addr, val);
3032 break;
3033 case 8:
3034 default:
3035 stq_user(addr, val);
6f27aba6
BS		 3036 break;
3037 }
81ad8ba2
BS		 3038 }
3039 }
3040 break;
3475187d
FB		 3041 case 0x14: // Bypass
3042 case 0x15: // Bypass, non-cacheable
81ad8ba2
BS		 3043 case 0x1c: // Bypass LE
3044 case 0x1d: // Bypass, non-cacheable LE
0f8a249a 3045 {
02aab46a
FB		 3046 switch(size) {
3047 case 1:
1a2fb1c0 3048 stb_phys(addr, val);
02aab46a
FB		 3049 break;
3050 case 2:
a4e7dd52 3051 stw_phys(addr, val);
02aab46a
FB		 3052 break;
3053 case 4:
a4e7dd52 3054 stl_phys(addr, val);
02aab46a
FB		 3055 break;
3056 case 8:
3057 default:
a4e7dd52 3058 stq_phys(addr, val);
02aab46a
FB		 3059 break;
3060 }
0f8a249a
BS		 3061 }
3062 return;
db166940
BS		 3063 case 0x24: // Nucleus quad LDD 128 bit atomic
3064 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
3065 // Only ldda allowed
3066 raise_exception(TT_ILL_INSN);
3067 return;
83469015
FB		 3068 case 0x04: // Nucleus
3069 case 0x0c: // Nucleus Little Endian (LE)
2065061e
IK		 3070 {
3071 switch(size) {
3072 case 1:
3073 stb_nucleus(addr, val);
3074 break;
3075 case 2:
3076 stw_nucleus(addr, val);
3077 break;
3078 case 4:
3079 stl_nucleus(addr, val);
3080 break;
3081 default:
3082 case 8:
3083 stq_nucleus(addr, val);
3084 break;
3085 }
3086 break;
3087 }
3088
83469015 3089 case 0x4a: // UPA config
0f8a249a
BS		 3090 // XXX
3091 return;
3475187d 3092 case 0x45: // LSU
0f8a249a
BS		 3093 {
3094 uint64_t oldreg;
3095
3096 oldreg = env->lsu;
1a2fb1c0 3097 env->lsu = val & (DMMU_E | IMMU_E);
0f8a249a
BS		 3098 // Mappings generated during D/I MMU disabled mode are
3099 // invalid in normal mode
3100 if (oldreg != env->lsu) {
77f193da
BS		 3101 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
3102 oldreg, env->lsu);
83469015 3103#ifdef DEBUG_MMU
d41160a3 3104 dump_mmu(stdout, fprintf, env1);
83469015 3105#endif
0f8a249a
BS		 3106 tlb_flush(env, 1);
3107 }
3108 return;
3109 }
3475187d 3110 case 0x50: // I-MMU regs
0f8a249a 3111 {
1a2fb1c0 3112 int reg = (addr >> 3) & 0xf;
0f8a249a 3113 uint64_t oldreg;
3b46e624 3114
0f8a249a 3115 oldreg = env->immuregs[reg];
3475187d
FB		 3116 switch(reg) {
3117 case 0: // RO
3475187d
FB		 3118 return;
3119 case 1: // Not in I-MMU
3120 case 2:
3475187d
FB		 3121 return;
3122 case 3: // SFSR
1a2fb1c0
BS		 3123 if ((val & 1) == 0)
3124 val = 0; // Clear SFSR
6e8e7d4c 3125 env->immu.sfsr = val;
3475187d 3126 break;
6e8e7d4c
IK		 3127 case 4: // RO
3128 return;
3475187d 3129 case 5: // TSB access
6e8e7d4c
IK		 3130 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
3131 PRIx64 "\n", env->immu.tsb, val);
3132 env->immu.tsb = val;
3133 break;
3475187d 3134 case 6: // Tag access
6e8e7d4c
IK		 3135 env->immu.tag_access = val;
3136 break;
3137 case 7:
3138 case 8:
3139 return;
3475187d
FB		 3140 default:
3141 break;
3142 }
6e8e7d4c 3143
3475187d 3144 if (oldreg != env->immuregs[reg]) {
6e8e7d4c 3145 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
77f193da 3146 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
3475187d 3147 }
952a328f 3148#ifdef DEBUG_MMU
d41160a3 3149 dump_mmu(stdout, fprintf, env);
3475187d 3150#endif
0f8a249a
BS		 3151 return;
3152 }
3475187d 3153 case 0x54: // I-MMU data in
f707726e
IK		 3154 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
3155 return;
3475187d 3156 case 0x55: // I-MMU data access
0f8a249a 3157 {
cc6747f4
BS		 3158 // TODO: auto demap
3159
1a2fb1c0 3160 unsigned int i = (addr >> 3) & 0x3f;
3475187d 3161
f707726e 3162 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env);
6e8e7d4c
IK		 3163
3164#ifdef DEBUG_MMU
f707726e 3165 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
d41160a3 3166 dump_mmu(stdout, fprintf, env);
6e8e7d4c 3167#endif
0f8a249a
BS		 3168 return;
3169 }
3475187d 3170 case 0x57: // I-MMU demap
170f4c55 3171 demap_tlb(env->itlb, addr, "immu", env);
0f8a249a 3172 return;
3475187d 3173 case 0x58: // D-MMU regs
0f8a249a 3174 {
1a2fb1c0 3175 int reg = (addr >> 3) & 0xf;
0f8a249a 3176 uint64_t oldreg;
3b46e624 3177
0f8a249a 3178 oldreg = env->dmmuregs[reg];
3475187d
FB		 3179 switch(reg) {
3180 case 0: // RO
3181 case 4:
3182 return;
3183 case 3: // SFSR
1a2fb1c0
BS		 3184 if ((val & 1) == 0) {
3185 val = 0; // Clear SFSR, Fault address
6e8e7d4c 3186 env->dmmu.sfar = 0;
0f8a249a 3187 }
6e8e7d4c 3188 env->dmmu.sfsr = val;
3475187d
FB		 3189 break;
3190 case 1: // Primary context
6e8e7d4c 3191 env->dmmu.mmu_primary_context = val;
664a65b0
IK		 3192 /* can be optimized to only flush MMU_USER_IDX
3193 and MMU_KERNEL_IDX entries */
3194 tlb_flush(env, 1);
6e8e7d4c 3195 break;
3475187d 3196 case 2: // Secondary context
6e8e7d4c 3197 env->dmmu.mmu_secondary_context = val;
664a65b0
IK		 3198 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
3199 and MMU_KERNEL_SECONDARY_IDX entries */
3200 tlb_flush(env, 1);
6e8e7d4c 3201 break;
3475187d 3202 case 5: // TSB access
6e8e7d4c
IK		 3203 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
3204 PRIx64 "\n", env->dmmu.tsb, val);
3205 env->dmmu.tsb = val;
3206 break;
3475187d 3207 case 6: // Tag access
6e8e7d4c
IK		 3208 env->dmmu.tag_access = val;
3209 break;
3475187d
FB		 3210 case 7: // Virtual Watchpoint
3211 case 8: // Physical Watchpoint
3212 default:
6e8e7d4c 3213 env->dmmuregs[reg] = val;
3475187d
FB		 3214 break;
3215 }
6e8e7d4c 3216
3475187d 3217 if (oldreg != env->dmmuregs[reg]) {
6e8e7d4c 3218 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
77f193da 3219 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
3475187d 3220 }
952a328f 3221#ifdef DEBUG_MMU
d41160a3 3222 dump_mmu(stdout, fprintf, env);
3475187d 3223#endif
0f8a249a
BS		 3224 return;
3225 }
3475187d 3226 case 0x5c: // D-MMU data in
f707726e
IK		 3227 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
3228 return;
3475187d 3229 case 0x5d: // D-MMU data access
0f8a249a 3230 {
1a2fb1c0 3231 unsigned int i = (addr >> 3) & 0x3f;
3475187d 3232
f707726e
IK		 3233 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env);
3234
6e8e7d4c 3235#ifdef DEBUG_MMU
f707726e 3236 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
d41160a3 3237 dump_mmu(stdout, fprintf, env);
6e8e7d4c 3238#endif
0f8a249a
BS		 3239 return;
3240 }
3475187d 3241 case 0x5f: // D-MMU demap
170f4c55 3242 demap_tlb(env->dtlb, addr, "dmmu", env);
cc6747f4 3243 return;
83469015 3244 case 0x49: // Interrupt data receive
0f8a249a
BS		 3245 // XXX
3246 return;
f7350b47
BS		 3247 case 0x46: // D-cache data
3248 case 0x47: // D-cache tag access
a5a52cf2
BS		 3249 case 0x4b: // E-cache error enable
3250 case 0x4c: // E-cache asynchronous fault status
3251 case 0x4d: // E-cache asynchronous fault address
f7350b47
BS		 3252 case 0x4e: // E-cache tag data
3253 case 0x66: // I-cache instruction access
3254 case 0x67: // I-cache tag access
3255 case 0x6e: // I-cache predecode
3256 case 0x6f: // I-cache LRU etc.
3257 case 0x76: // E-cache tag
3258 case 0x7e: // E-cache tag
3259 return;
3475187d
FB		 3260 case 0x51: // I-MMU 8k TSB pointer, RO
3261 case 0x52: // I-MMU 64k TSB pointer, RO
3262 case 0x56: // I-MMU tag read, RO
3263 case 0x59: // D-MMU 8k TSB pointer, RO
3264 case 0x5a: // D-MMU 64k TSB pointer, RO
3265 case 0x5b: // D-MMU data pointer, RO
3266 case 0x5e: // D-MMU tag read, RO
83469015
FB		 3267 case 0x48: // Interrupt dispatch, RO
3268 case 0x7f: // Incoming interrupt vector, RO
3269 case 0x82: // Primary no-fault, RO
3270 case 0x83: // Secondary no-fault, RO
3271 case 0x8a: // Primary no-fault LE, RO
3272 case 0x8b: // Secondary no-fault LE, RO
3475187d 3273 default:
e18231a3 3274 do_unassigned_access(addr, 1, 0, 1, size);
0f8a249a 3275 return;
3475187d
FB		 3276 }
3277}
81ad8ba2 3278#endif /* CONFIG_USER_ONLY */
3391c818 3279
db166940
BS		 3280void helper_ldda_asi(target_ulong addr, int asi, int rd)
3281{
db166940 3282 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2aae2b8e 3283 || (cpu_has_hypervisor(env)
5578ceab 3284 && asi >= 0x30 && asi < 0x80
fb79ceb9 3285 && !(env->hpstate & HS_PRIV)))
db166940
BS		 3286 raise_exception(TT_PRIV_ACT);
3287
1295001c
IK		 3288 addr = asi_address_mask(env, asi, addr);
3289
db166940 3290 switch (asi) {
03ae77d6 3291#if !defined(CONFIG_USER_ONLY)
db166940
BS		 3292 case 0x24: // Nucleus quad LDD 128 bit atomic
3293 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
3294 helper_check_align(addr, 0xf);
3295 if (rd == 0) {
54a3c0f0 3296 env->gregs[1] = ldq_nucleus(addr + 8);
db166940
BS		 3297 if (asi == 0x2c)
3298 bswap64s(&env->gregs[1]);
3299 } else if (rd < 8) {
54a3c0f0
IK		 3300 env->gregs[rd] = ldq_nucleus(addr);
3301 env->gregs[rd + 1] = ldq_nucleus(addr + 8);
db166940
BS		 3302 if (asi == 0x2c) {
3303 bswap64s(&env->gregs[rd]);
3304 bswap64s(&env->gregs[rd + 1]);
3305 }
3306 } else {
54a3c0f0
IK		 3307 env->regwptr[rd] = ldq_nucleus(addr);
3308 env->regwptr[rd + 1] = ldq_nucleus(addr + 8);
db166940
BS		 3309 if (asi == 0x2c) {
3310 bswap64s(&env->regwptr[rd]);
3311 bswap64s(&env->regwptr[rd + 1]);
3312 }
3313 }
3314 break;
03ae77d6 3315#endif
db166940
BS		 3316 default:
3317 helper_check_align(addr, 0x3);
3318 if (rd == 0)
3319 env->gregs[1] = helper_ld_asi(addr + 4, asi, 4, 0);
3320 else if (rd < 8) {
3321 env->gregs[rd] = helper_ld_asi(addr, asi, 4, 0);
3322 env->gregs[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
3323 } else {
3324 env->regwptr[rd] = helper_ld_asi(addr, asi, 4, 0);
3325 env->regwptr[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
3326 }
3327 break;
3328 }
3329}
3330
1a2fb1c0 3331void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
3391c818 3332{
3391c818 3333 unsigned int i;
1a2fb1c0 3334 target_ulong val;
3391c818 3335
c2bc0e38 3336 helper_check_align(addr, 3);
1295001c
IK		 3337 addr = asi_address_mask(env, asi, addr);
3338
3391c818
BS		 3339 switch (asi) {
3340 case 0xf0: // Block load primary
3341 case 0xf1: // Block load secondary
3342 case 0xf8: // Block load primary LE
3343 case 0xf9: // Block load secondary LE
51996525
BS		 3344 if (rd & 7) {
3345 raise_exception(TT_ILL_INSN);
3346 return;
3347 }
c2bc0e38 3348 helper_check_align(addr, 0x3f);
51996525 3349 for (i = 0; i < 16; i++) {
77f193da
BS		 3350 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4,
3351 0);
1a2fb1c0 3352 addr += 4;
3391c818 3353 }
3391c818 3354
0e2fa9ca
IK		 3355 return;
3356 case 0x70: // Block load primary, user privilege
3357 case 0x71: // Block load secondary, user privilege
3358 if (rd & 7) {
3359 raise_exception(TT_ILL_INSN);
3360 return;
3361 }
3362 helper_check_align(addr, 0x3f);
3363 for (i = 0; i < 16; i++) {
3364 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x1f, 4,
3365 0);
3366 addr += 4;
3367 }
3368
3391c818
BS		 3369 return;
3370 default:
3371 break;
3372 }
3373
1a2fb1c0 3374 val = helper_ld_asi(addr, asi, size, 0);
3391c818
BS		 3375 switch(size) {
3376 default:
3377 case 4:
714547bb 3378 *((uint32_t *)&env->fpr[rd]) = val;
3391c818
BS		 3379 break;
3380 case 8:
1a2fb1c0 3381 *((int64_t *)&DT0) = val;
3391c818 3382 break;
1f587329
BS		 3383 case 16:
3384 // XXX
3385 break;
3391c818 3386 }
3391c818
BS		 3387}
3388
1a2fb1c0 3389void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
3391c818 3390{
3391c818 3391 unsigned int i;
1a2fb1c0 3392 target_ulong val = 0;
3391c818 3393
c2bc0e38 3394 helper_check_align(addr, 3);
1295001c
IK		 3395 addr = asi_address_mask(env, asi, addr);
3396
3391c818 3397 switch (asi) {
c99657d3
BS		 3398 case 0xe0: // UA2007 Block commit store primary (cache flush)
3399 case 0xe1: // UA2007 Block commit store secondary (cache flush)
3391c818
BS		 3400 case 0xf0: // Block store primary
3401 case 0xf1: // Block store secondary
3402 case 0xf8: // Block store primary LE
3403 case 0xf9: // Block store secondary LE
51996525
BS		 3404 if (rd & 7) {
3405 raise_exception(TT_ILL_INSN);
3406 return;
3407 }
c2bc0e38 3408 helper_check_align(addr, 0x3f);
51996525 3409 for (i = 0; i < 16; i++) {
1a2fb1c0
BS		 3410 val = *(uint32_t *)&env->fpr[rd++];
3411 helper_st_asi(addr, val, asi & 0x8f, 4);
3412 addr += 4;
3391c818 3413 }
3391c818 3414
0e2fa9ca
IK		 3415 return;
3416 case 0x70: // Block store primary, user privilege
3417 case 0x71: // Block store secondary, user privilege
3418 if (rd & 7) {
3419 raise_exception(TT_ILL_INSN);
3420 return;
3421 }
3422 helper_check_align(addr, 0x3f);
3423 for (i = 0; i < 16; i++) {
3424 val = *(uint32_t *)&env->fpr[rd++];
3425 helper_st_asi(addr, val, asi & 0x1f, 4);
3426 addr += 4;
3427 }
3428
3391c818
BS		 3429 return;
3430 default:
3431 break;
3432 }
3433
3434 switch(size) {
3435 default:
3436 case 4:
714547bb 3437 val = *((uint32_t *)&env->fpr[rd]);
3391c818
BS		 3438 break;
3439 case 8:
1a2fb1c0 3440 val = *((int64_t *)&DT0);
3391c818 3441 break;
1f587329
BS		 3442 case 16:
3443 // XXX
3444 break;
3391c818 3445 }
1a2fb1c0
BS		 3446 helper_st_asi(addr, val, asi, size);
3447}
3448
3449target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
3450 target_ulong val2, uint32_t asi)
3451{
3452 target_ulong ret;
3453
1121f879 3454 val2 &= 0xffffffffUL;
1a2fb1c0
BS		 3455 ret = helper_ld_asi(addr, asi, 4, 0);
3456 ret &= 0xffffffffUL;
1121f879
BS		 3457 if (val2 == ret)
3458 helper_st_asi(addr, val1 & 0xffffffffUL, asi, 4);
1a2fb1c0 3459 return ret;
3391c818
BS		 3460}
3461
1a2fb1c0
BS		 3462target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
3463 target_ulong val2, uint32_t asi)
3464{
3465 target_ulong ret;
3466
3467 ret = helper_ld_asi(addr, asi, 8, 0);
1121f879
BS		 3468 if (val2 == ret)
3469 helper_st_asi(addr, val1, asi, 8);
1a2fb1c0
BS		 3470 return ret;
3471}
81ad8ba2 3472#endif /* TARGET_SPARC64 */
3475187d
FB		 3473
3474#ifndef TARGET_SPARC64
1a2fb1c0 3475void helper_rett(void)
e8af50a3 3476{
af7bf89b
FB		 3477 unsigned int cwp;
3478
d4218d99
BS		 3479 if (env->psret == 1)
3480 raise_exception(TT_ILL_INSN);
3481
e8af50a3 3482 env->psret = 1;
5a834bb4 3483 cwp = cwp_inc(env->cwp + 1) ;
e8af50a3
FB		 3484 if (env->wim & (1 << cwp)) {
3485 raise_exception(TT_WIN_UNF);
3486 }
3487 set_cwp(cwp);
3488 env->psrs = env->psrps;
3489}
3475187d 3490#endif
e8af50a3 3491
0fcec41e 3492static target_ulong helper_udiv_common(target_ulong a, target_ulong b, int cc)
3b89f26c 3493{
0fcec41e 3494 int overflow = 0;
3b89f26c
BS		 3495 uint64_t x0;
3496 uint32_t x1;
3497
7621a90d 3498 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
09487205 3499 x1 = (b & 0xffffffff);
3b89f26c
BS		 3500
3501 if (x1 == 0) {
3502 raise_exception(TT_DIV_ZERO);
3503 }
3504
3505 x0 = x0 / x1;
3506 if (x0 > 0xffffffff) {
0fcec41e
AJ		 3507 x0 = 0xffffffff;
3508 overflow = 1;
3509 }
3510
3511 if (cc) {
3512 env->cc_dst = x0;
3513 env->cc_src2 = overflow;
3514 env->cc_op = CC_OP_DIV;
3b89f26c 3515 }
0fcec41e 3516 return x0;
3b89f26c
BS		 3517}
3518
0fcec41e
AJ		 3519target_ulong helper_udiv(target_ulong a, target_ulong b)
3520{
3521 return helper_udiv_common(a, b, 0);
3522}
3523
3524target_ulong helper_udiv_cc(target_ulong a, target_ulong b)
3525{
3526 return helper_udiv_common(a, b, 1);
3527}
3528
3529static target_ulong helper_sdiv_common(target_ulong a, target_ulong b, int cc)
3b89f26c 3530{
0fcec41e 3531 int overflow = 0;
3b89f26c
BS		 3532 int64_t x0;
3533 int32_t x1;
3534
7621a90d 3535 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
09487205 3536 x1 = (b & 0xffffffff);
3b89f26c
BS		 3537
3538 if (x1 == 0) {
3539 raise_exception(TT_DIV_ZERO);
3540 }
3541
3542 x0 = x0 / x1;
3543 if ((int32_t) x0 != x0) {
0fcec41e
AJ		 3544 x0 = x0 < 0 ? 0x80000000: 0x7fffffff;
3545 overflow = 1;
3546 }
3547
3548 if (cc) {
3549 env->cc_dst = x0;
3550 env->cc_src2 = overflow;
3551 env->cc_op = CC_OP_DIV;
3b89f26c 3552 }
0fcec41e
AJ		 3553 return x0;
3554}
3555
3556target_ulong helper_sdiv(target_ulong a, target_ulong b)
3557{
3558 return helper_sdiv_common(a, b, 0);
3559}
3560
3561target_ulong helper_sdiv_cc(target_ulong a, target_ulong b)
3562{
3563 return helper_sdiv_common(a, b, 1);
3b89f26c
BS		 3564}
3565
7fa76c0b
BS		 3566void helper_stdf(target_ulong addr, int mem_idx)
3567{
c2bc0e38 3568 helper_check_align(addr, 7);
7fa76c0b
BS		 3569#if !defined(CONFIG_USER_ONLY)
3570 switch (mem_idx) {
b219094a 3571 case MMU_USER_IDX:
c2bc0e38 3572 stfq_user(addr, DT0);
7fa76c0b 3573 break;
b219094a 3574 case MMU_KERNEL_IDX:
c2bc0e38 3575 stfq_kernel(addr, DT0);
7fa76c0b
BS		 3576 break;
3577#ifdef TARGET_SPARC64
b219094a 3578 case MMU_HYPV_IDX:
c2bc0e38 3579 stfq_hypv(addr, DT0);
7fa76c0b
BS		 3580 break;
3581#endif
3582 default:
b219094a 3583 DPRINTF_MMU("helper_stdf: need to check MMU idx %d\n", mem_idx);
7fa76c0b
BS		 3584 break;
3585 }
3586#else
41db525e 3587 stfq_raw(address_mask(env, addr), DT0);
7fa76c0b
BS		 3588#endif
3589}
3590
3591void helper_lddf(target_ulong addr, int mem_idx)
3592{
c2bc0e38 3593 helper_check_align(addr, 7);
7fa76c0b
BS		 3594#if !defined(CONFIG_USER_ONLY)
3595 switch (mem_idx) {
b219094a 3596 case MMU_USER_IDX:
c2bc0e38 3597 DT0 = ldfq_user(addr);
7fa76c0b 3598 break;
b219094a 3599 case MMU_KERNEL_IDX:
c2bc0e38 3600 DT0 = ldfq_kernel(addr);
7fa76c0b
BS		 3601 break;
3602#ifdef TARGET_SPARC64
b219094a 3603 case MMU_HYPV_IDX:
c2bc0e38 3604 DT0 = ldfq_hypv(addr);
7fa76c0b
BS		 3605 break;
3606#endif
3607 default:
b219094a 3608 DPRINTF_MMU("helper_lddf: need to check MMU idx %d\n", mem_idx);
7fa76c0b
BS		 3609 break;
3610 }
3611#else
41db525e 3612 DT0 = ldfq_raw(address_mask(env, addr));
7fa76c0b
BS		 3613#endif
3614}
3615
64a88d5d 3616void helper_ldqf(target_ulong addr, int mem_idx)
7fa76c0b
BS		 3617{
3618 // XXX add 128 bit load
3619 CPU_QuadU u;
3620
c2bc0e38 3621 helper_check_align(addr, 7);
64a88d5d
BS		 3622#if !defined(CONFIG_USER_ONLY)
3623 switch (mem_idx) {
b219094a 3624 case MMU_USER_IDX:
c2bc0e38
BS		 3625 u.ll.upper = ldq_user(addr);
3626 u.ll.lower = ldq_user(addr + 8);
64a88d5d
BS		 3627 QT0 = u.q;
3628 break;
b219094a 3629 case MMU_KERNEL_IDX:
c2bc0e38
BS		 3630 u.ll.upper = ldq_kernel(addr);
3631 u.ll.lower = ldq_kernel(addr + 8);
64a88d5d
BS		 3632 QT0 = u.q;
3633 break;
3634#ifdef TARGET_SPARC64
b219094a 3635 case MMU_HYPV_IDX:
c2bc0e38
BS		 3636 u.ll.upper = ldq_hypv(addr);
3637 u.ll.lower = ldq_hypv(addr + 8);
64a88d5d
BS		 3638 QT0 = u.q;
3639 break;
3640#endif
3641 default:
b219094a 3642 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx);
64a88d5d
BS		 3643 break;
3644 }
3645#else
41db525e
RH		 3646 u.ll.upper = ldq_raw(address_mask(env, addr));
3647 u.ll.lower = ldq_raw(address_mask(env, addr + 8));
7fa76c0b 3648 QT0 = u.q;
64a88d5d 3649#endif
7fa76c0b
BS		 3650}
3651
64a88d5d 3652void helper_stqf(target_ulong addr, int mem_idx)
7fa76c0b
BS		 3653{
3654 // XXX add 128 bit store
3655 CPU_QuadU u;
3656
c2bc0e38 3657 helper_check_align(addr, 7);
64a88d5d
BS		 3658#if !defined(CONFIG_USER_ONLY)
3659 switch (mem_idx) {
b219094a 3660 case MMU_USER_IDX:
64a88d5d 3661 u.q = QT0;
c2bc0e38
BS		 3662 stq_user(addr, u.ll.upper);
3663 stq_user(addr + 8, u.ll.lower);
64a88d5d 3664 break;
b219094a 3665 case MMU_KERNEL_IDX:
64a88d5d 3666 u.q = QT0;
c2bc0e38
BS		 3667 stq_kernel(addr, u.ll.upper);
3668 stq_kernel(addr + 8, u.ll.lower);
64a88d5d
BS		 3669 break;
3670#ifdef TARGET_SPARC64
b219094a 3671 case MMU_HYPV_IDX:
64a88d5d 3672 u.q = QT0;
c2bc0e38
BS		 3673 stq_hypv(addr, u.ll.upper);
3674 stq_hypv(addr + 8, u.ll.lower);
64a88d5d
BS		 3675 break;
3676#endif
3677 default:
b219094a 3678 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx);
64a88d5d
BS		 3679 break;
3680 }
3681#else
7fa76c0b 3682 u.q = QT0;
41db525e
RH		 3683 stq_raw(address_mask(env, addr), u.ll.upper);
3684 stq_raw(address_mask(env, addr + 8), u.ll.lower);
7fa76c0b 3685#endif
64a88d5d 3686}
7fa76c0b 3687
3a3b925d 3688static inline void set_fsr(void)
e8af50a3 3689{
7a0e1f41 3690 int rnd_mode;
bb5529bb 3691
e8af50a3
FB		 3692 switch (env->fsr & FSR_RD_MASK) {
3693 case FSR_RD_NEAREST:
7a0e1f41 3694 rnd_mode = float_round_nearest_even;
0f8a249a 3695 break;
ed910241 3696 default:
e8af50a3 3697 case FSR_RD_ZERO:
7a0e1f41 3698 rnd_mode = float_round_to_zero;
0f8a249a 3699 break;
e8af50a3 3700 case FSR_RD_POS:
7a0e1f41 3701 rnd_mode = float_round_up;
0f8a249a 3702 break;
e8af50a3 3703 case FSR_RD_NEG:
7a0e1f41 3704 rnd_mode = float_round_down;
0f8a249a 3705 break;
e8af50a3 3706 }
7a0e1f41 3707 set_float_rounding_mode(rnd_mode, &env->fp_status);
e8af50a3 3708}
e80cfcfc 3709
3a3b925d 3710void helper_ldfsr(uint32_t new_fsr)
bb5529bb 3711{
3a3b925d
BS		 3712 env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK);
3713 set_fsr();
bb5529bb
BS		 3714}
3715
3a3b925d
BS		 3716#ifdef TARGET_SPARC64
3717void helper_ldxfsr(uint64_t new_fsr)
3718{
3719 env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK);
3720 set_fsr();
3721}
3722#endif
3723
bb5529bb 3724void helper_debug(void)
e80cfcfc
FB		 3725{
3726 env->exception_index = EXCP_DEBUG;
3727 cpu_loop_exit();
3728}
af7bf89b 3729
3475187d 3730#ifndef TARGET_SPARC64
72a9747b
BS		 3731/* XXX: use another pointer for %iN registers to avoid slow wrapping
3732 handling ? */
3733void helper_save(void)
3734{
3735 uint32_t cwp;
3736
5a834bb4 3737 cwp = cwp_dec(env->cwp - 1);
72a9747b
BS		 3738 if (env->wim & (1 << cwp)) {
3739 raise_exception(TT_WIN_OVF);
3740 }
3741 set_cwp(cwp);
3742}
3743
3744void helper_restore(void)
3745{
3746 uint32_t cwp;
3747
5a834bb4 3748 cwp = cwp_inc(env->cwp + 1);
72a9747b
BS		 3749 if (env->wim & (1 << cwp)) {
3750 raise_exception(TT_WIN_UNF);
3751 }
3752 set_cwp(cwp);
3753}
3754
1a2fb1c0 3755void helper_wrpsr(target_ulong new_psr)
af7bf89b 3756{
5a834bb4 3757 if ((new_psr & PSR_CWP) >= env->nwindows) {
d4218d99 3758 raise_exception(TT_ILL_INSN);
5a834bb4
BS		 3759 } else {
3760 cpu_put_psr(env, new_psr);
3761 }
af7bf89b
FB		 3762}
3763
1a2fb1c0 3764target_ulong helper_rdpsr(void)
af7bf89b 3765{
5a834bb4 3766 return get_psr();
af7bf89b 3767}
3475187d
FB		 3768
3769#else
72a9747b
BS		 3770/* XXX: use another pointer for %iN registers to avoid slow wrapping
3771 handling ? */
3772void helper_save(void)
3773{
3774 uint32_t cwp;
3775
5a834bb4 3776 cwp = cwp_dec(env->cwp - 1);
72a9747b
BS		 3777 if (env->cansave == 0) {
3778 raise_exception(TT_SPILL | (env->otherwin != 0 ?
3779 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
3780 ((env->wstate & 0x7) << 2)));
3781 } else {
3782 if (env->cleanwin - env->canrestore == 0) {
3783 // XXX Clean windows without trap
3784 raise_exception(TT_CLRWIN);
3785 } else {
3786 env->cansave--;
3787 env->canrestore++;
3788 set_cwp(cwp);
3789 }
3790 }
3791}
3792
3793void helper_restore(void)
3794{
3795 uint32_t cwp;
3796
5a834bb4 3797 cwp = cwp_inc(env->cwp + 1);
72a9747b
BS		 3798 if (env->canrestore == 0) {
3799 raise_exception(TT_FILL | (env->otherwin != 0 ?
3800 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
3801 ((env->wstate & 0x7) << 2)));
3802 } else {
3803 env->cansave++;
3804 env->canrestore--;
3805 set_cwp(cwp);
3806 }
3807}
3808
3809void helper_flushw(void)
3810{
1a14026e 3811 if (env->cansave != env->nwindows - 2) {
72a9747b
BS		 3812 raise_exception(TT_SPILL | (env->otherwin != 0 ?
3813 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
3814 ((env->wstate & 0x7) << 2)));
3815 }
3816}
3817
3818void helper_saved(void)
3819{
3820 env->cansave++;
3821 if (env->otherwin == 0)
3822 env->canrestore--;
3823 else
3824 env->otherwin--;
3825}
3826
3827void helper_restored(void)
3828{
3829 env->canrestore++;
1a14026e 3830 if (env->cleanwin < env->nwindows - 1)
72a9747b
BS		 3831 env->cleanwin++;
3832 if (env->otherwin == 0)
3833 env->cansave--;
3834 else
3835 env->otherwin--;
3836}
3837
5a834bb4
BS		 3838static target_ulong get_ccr(void)
3839{
3840 target_ulong psr;
3841
3842 psr = get_psr();
3843
3844 return ((env->xcc >> 20) << 4) | ((psr & PSR_ICC) >> 20);
3845}
3846
3847target_ulong cpu_get_ccr(CPUState *env1)
3848{
3849 CPUState *saved_env;
3850 target_ulong ret;
3851
3852 saved_env = env;
3853 env = env1;
3854 ret = get_ccr();
3855 env = saved_env;
3856 return ret;
3857}
3858
3859static void put_ccr(target_ulong val)
3860{
3861 target_ulong tmp = val;
3862
3863 env->xcc = (tmp >> 4) << 20;
3864 env->psr = (tmp & 0xf) << 20;
3865 CC_OP = CC_OP_FLAGS;
3866}
3867
3868void cpu_put_ccr(CPUState *env1, target_ulong val)
3869{
3870 CPUState *saved_env;
3871
3872 saved_env = env;
3873 env = env1;
3874 put_ccr(val);
3875 env = saved_env;
3876}
3877
3878static target_ulong get_cwp64(void)
3879{
3880 return env->nwindows - 1 - env->cwp;
3881}
3882
3883target_ulong cpu_get_cwp64(CPUState *env1)
3884{
3885 CPUState *saved_env;
3886 target_ulong ret;
3887
3888 saved_env = env;
3889 env = env1;
3890 ret = get_cwp64();
3891 env = saved_env;
3892 return ret;
3893}
3894
3895static void put_cwp64(int cwp)
3896{
3897 if (unlikely(cwp >= env->nwindows || cwp < 0)) {
3898 cwp %= env->nwindows;
3899 }
3900 set_cwp(env->nwindows - 1 - cwp);
3901}
3902
3903void cpu_put_cwp64(CPUState *env1, int cwp)
3904{
3905 CPUState *saved_env;
3906
3907 saved_env = env;
3908 env = env1;
3909 put_cwp64(cwp);
3910 env = saved_env;
3911}
3912
d35527d9
BS		 3913target_ulong helper_rdccr(void)
3914{
5a834bb4 3915 return get_ccr();
d35527d9
BS		 3916}
3917
3918void helper_wrccr(target_ulong new_ccr)
3919{
5a834bb4 3920 put_ccr(new_ccr);
d35527d9
BS		 3921}
3922
3923// CWP handling is reversed in V9, but we still use the V8 register
3924// order.
3925target_ulong helper_rdcwp(void)
3926{
5a834bb4 3927 return get_cwp64();
d35527d9
BS		 3928}
3929
3930void helper_wrcwp(target_ulong new_cwp)
3931{
5a834bb4 3932 put_cwp64(new_cwp);
d35527d9 3933}
3475187d 3934
1f5063fb
BS		 3935// This function uses non-native bit order
3936#define GET_FIELD(X, FROM, TO) \
3937 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
3938
3939// This function uses the order in the manuals, i.e. bit 0 is 2^0
3940#define GET_FIELD_SP(X, FROM, TO) \
3941 GET_FIELD(X, 63 - (TO), 63 - (FROM))
3942
3943target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
3944{
3945 return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
3946 (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
3947 (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) |
3948 (GET_FIELD_SP(pixel_addr, 56, 59) << 13) |
3949 (GET_FIELD_SP(pixel_addr, 35, 38) << 9) |
3950 (GET_FIELD_SP(pixel_addr, 13, 16) << 5) |
3951 (((pixel_addr >> 55) & 1) << 4) |
3952 (GET_FIELD_SP(pixel_addr, 33, 34) << 2) |
3953 GET_FIELD_SP(pixel_addr, 11, 12);
3954}
3955
3956target_ulong helper_alignaddr(target_ulong addr, target_ulong offset)
3957{
3958 uint64_t tmp;
3959
3960 tmp = addr + offset;
3961 env->gsr &= ~7ULL;
3962 env->gsr |= tmp & 7ULL;
3963 return tmp & ~7ULL;
3964}
3965
1a2fb1c0 3966target_ulong helper_popc(target_ulong val)
3475187d 3967{
1a2fb1c0 3968 return ctpop64(val);
3475187d 3969}
83469015 3970
d780a466 3971static inline uint64_t *get_gregset(uint32_t pstate)
83469015
FB		 3972{
3973 switch (pstate) {
3974 default:
7e8695ed
IK		 3975 DPRINTF_PSTATE("ERROR in get_gregset: active pstate bits=%x%s%s%s\n",
3976 pstate,
3977 (pstate & PS_IG) ? " IG" : "",
3978 (pstate & PS_MG) ? " MG" : "",
3979 (pstate & PS_AG) ? " AG" : "");
3980 /* pass through to normal set of global registers */
83469015 3981 case 0:
0f8a249a 3982 return env->bgregs;
83469015 3983 case PS_AG:
0f8a249a 3984 return env->agregs;
83469015 3985 case PS_MG:
0f8a249a 3986 return env->mgregs;
83469015 3987 case PS_IG:
0f8a249a 3988 return env->igregs;
83469015
FB		 3989 }
3990}
3991
d780a466 3992static inline void change_pstate(uint32_t new_pstate)
83469015 3993{
d780a466 3994 uint32_t pstate_regs, new_pstate_regs;
83469015
FB		 3995 uint64_t *src, *dst;
3996
5210977a
IK		 3997 if (env->def->features & CPU_FEATURE_GL) {
3998 // PS_AG is not implemented in this case
3999 new_pstate &= ~PS_AG;
4000 }
4001
83469015
FB		 4002 pstate_regs = env->pstate & 0xc01;
4003 new_pstate_regs = new_pstate & 0xc01;
5210977a 4004
83469015 4005 if (new_pstate_regs != pstate_regs) {
7e8695ed
IK		 4006 DPRINTF_PSTATE("change_pstate: switching regs old=%x new=%x\n",
4007 pstate_regs, new_pstate_regs);
0f8a249a
BS		 4008 // Switch global register bank
4009 src = get_gregset(new_pstate_regs);
4010 dst = get_gregset(pstate_regs);
4011 memcpy32(dst, env->gregs);
4012 memcpy32(env->gregs, src);
83469015 4013 }
7e8695ed
IK		 4014 else {
4015 DPRINTF_PSTATE("change_pstate: regs new=%x (unchanged)\n",
4016 new_pstate_regs);
4017 }
83469015
FB		 4018 env->pstate = new_pstate;
4019}
4020
1a2fb1c0 4021void helper_wrpstate(target_ulong new_state)
8f1f22f6 4022{
5210977a 4023 change_pstate(new_state & 0xf3f);
4dc28134
IK		 4024
4025#if !defined(CONFIG_USER_ONLY)
4026 if (cpu_interrupts_enabled(env)) {
4027 cpu_check_irqs(env);
4028 }
4029#endif
8f1f22f6
BS		 4030}
4031
1fae7b70
IK		 4032void helper_wrpil(target_ulong new_pil)
4033{
4034#if !defined(CONFIG_USER_ONLY)
4035 DPRINTF_PSTATE("helper_wrpil old=%x new=%x\n",
4036 env->psrpil, (uint32_t)new_pil);
4037
4038 env->psrpil = new_pil;
4039
4040 if (cpu_interrupts_enabled(env)) {
4041 cpu_check_irqs(env);
4042 }
4043#endif
4044}
4045
1a2fb1c0 4046void helper_done(void)
83469015 4047{
8194f35a
IK		 4048 trap_state* tsptr = cpu_tsptr(env);
4049
3723cd09 4050 env->pc = tsptr->tnpc;
8194f35a 4051 env->npc = tsptr->tnpc + 4;
5a834bb4 4052 put_ccr(tsptr->tstate >> 32);
8194f35a
IK		 4053 env->asi = (tsptr->tstate >> 24) & 0xff;
4054 change_pstate((tsptr->tstate >> 8) & 0xf3f);
5a834bb4 4055 put_cwp64(tsptr->tstate & 0xff);
e6bf7d70 4056 env->tl--;
4dc28134
IK		 4057
4058 DPRINTF_PSTATE("... helper_done tl=%d\n", env->tl);
4059
4060#if !defined(CONFIG_USER_ONLY)
4061 if (cpu_interrupts_enabled(env)) {
4062 cpu_check_irqs(env);
4063 }
4064#endif
83469015
FB		 4065}
4066
1a2fb1c0 4067void helper_retry(void)
83469015 4068{
8194f35a
IK		 4069 trap_state* tsptr = cpu_tsptr(env);
4070
4071 env->pc = tsptr->tpc;
4072 env->npc = tsptr->tnpc;
5a834bb4 4073 put_ccr(tsptr->tstate >> 32);
8194f35a
IK		 4074 env->asi = (tsptr->tstate >> 24) & 0xff;
4075 change_pstate((tsptr->tstate >> 8) & 0xf3f);
5a834bb4 4076 put_cwp64(tsptr->tstate & 0xff);
e6bf7d70 4077 env->tl--;
4dc28134
IK		 4078
4079 DPRINTF_PSTATE("... helper_retry tl=%d\n", env->tl);
4080
4081#if !defined(CONFIG_USER_ONLY)
4082 if (cpu_interrupts_enabled(env)) {
4083 cpu_check_irqs(env);
4084 }
4085#endif
4086}
4087
4088static void do_modify_softint(const char* operation, uint32_t value)
4089{
4090 if (env->softint != value) {
4091 env->softint = value;
4092 DPRINTF_PSTATE(": %s new %08x\n", operation, env->softint);
4093#if !defined(CONFIG_USER_ONLY)
4094 if (cpu_interrupts_enabled(env)) {
4095 cpu_check_irqs(env);
4096 }
4097#endif
4098 }
83469015 4099}
9d926598
BS		 4100
4101void helper_set_softint(uint64_t value)
4102{
4dc28134 4103 do_modify_softint("helper_set_softint", env->softint | (uint32_t)value);
9d926598
BS		 4104}
4105
4106void helper_clear_softint(uint64_t value)
4107{
4dc28134 4108 do_modify_softint("helper_clear_softint", env->softint & (uint32_t)~value);
9d926598
BS		 4109}
4110
4111void helper_write_softint(uint64_t value)
4112{
4dc28134 4113 do_modify_softint("helper_write_softint", (uint32_t)value);
9d926598 4114}
3475187d 4115#endif
ee5bbe38 4116
91736d37
BS		 4117#ifdef TARGET_SPARC64
4118#ifdef DEBUG_PCALL
4119static const char * const excp_names[0x80] = {
4120 [TT_TFAULT] = "Instruction Access Fault",
4121 [TT_TMISS] = "Instruction Access MMU Miss",
4122 [TT_CODE_ACCESS] = "Instruction Access Error",
4123 [TT_ILL_INSN] = "Illegal Instruction",
4124 [TT_PRIV_INSN] = "Privileged Instruction",
4125 [TT_NFPU_INSN] = "FPU Disabled",
4126 [TT_FP_EXCP] = "FPU Exception",
4127 [TT_TOVF] = "Tag Overflow",
4128 [TT_CLRWIN] = "Clean Windows",
4129 [TT_DIV_ZERO] = "Division By Zero",
4130 [TT_DFAULT] = "Data Access Fault",
4131 [TT_DMISS] = "Data Access MMU Miss",
4132 [TT_DATA_ACCESS] = "Data Access Error",
4133 [TT_DPROT] = "Data Protection Error",
4134 [TT_UNALIGNED] = "Unaligned Memory Access",
4135 [TT_PRIV_ACT] = "Privileged Action",
4136 [TT_EXTINT | 0x1] = "External Interrupt 1",
4137 [TT_EXTINT | 0x2] = "External Interrupt 2",
4138 [TT_EXTINT | 0x3] = "External Interrupt 3",
4139 [TT_EXTINT | 0x4] = "External Interrupt 4",
4140 [TT_EXTINT | 0x5] = "External Interrupt 5",
4141 [TT_EXTINT | 0x6] = "External Interrupt 6",
4142 [TT_EXTINT | 0x7] = "External Interrupt 7",
4143 [TT_EXTINT | 0x8] = "External Interrupt 8",
4144 [TT_EXTINT | 0x9] = "External Interrupt 9",
4145 [TT_EXTINT | 0xa] = "External Interrupt 10",
4146 [TT_EXTINT | 0xb] = "External Interrupt 11",
4147 [TT_EXTINT | 0xc] = "External Interrupt 12",
4148 [TT_EXTINT | 0xd] = "External Interrupt 13",
4149 [TT_EXTINT | 0xe] = "External Interrupt 14",
4150 [TT_EXTINT | 0xf] = "External Interrupt 15",
4151};
4152#endif
4153
8194f35a
IK		 4154trap_state* cpu_tsptr(CPUState* env)
4155{
4156 return &env->ts[env->tl & MAXTL_MASK];
4157}
4158
91736d37
BS		 4159void do_interrupt(CPUState *env)
4160{
4161 int intno = env->exception_index;
8194f35a 4162 trap_state* tsptr;
91736d37
BS		 4163
4164#ifdef DEBUG_PCALL
8fec2b8c 4165 if (qemu_loglevel_mask(CPU_LOG_INT)) {
91736d37
BS		 4166 static int count;
4167 const char *name;
4168
4169 if (intno < 0 || intno >= 0x180)
4170 name = "Unknown";
4171 else if (intno >= 0x100)
4172 name = "Trap Instruction";
4173 else if (intno >= 0xc0)
4174 name = "Window Fill";
4175 else if (intno >= 0x80)
4176 name = "Window Spill";
4177 else {
4178 name = excp_names[intno];
4179 if (!name)
4180 name = "Unknown";
4181 }
4182
93fcfe39 4183 qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
91736d37
BS		 4184 " SP=%016" PRIx64 "\n",
4185 count, name, intno,
4186 env->pc,
4187 env->npc, env->regwptr[6]);
93fcfe39 4188 log_cpu_state(env, 0);
91736d37
BS		 4189#if 0
4190 {
4191 int i;
4192 uint8_t *ptr;
4193
93fcfe39 4194 qemu_log(" code=");
91736d37
BS		 4195 ptr = (uint8_t *)env->pc;
4196 for(i = 0; i < 16; i++) {
93fcfe39 4197 qemu_log(" %02x", ldub(ptr + i));
91736d37 4198 }
93fcfe39 4199 qemu_log("\n");
91736d37
BS		 4200 }
4201#endif
4202 count++;
4203 }
4204#endif
4205#if !defined(CONFIG_USER_ONLY)
4206 if (env->tl >= env->maxtl) {
4207 cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
4208 " Error state", env->exception_index, env->tl, env->maxtl);
4209 return;
4210 }
4211#endif
4212 if (env->tl < env->maxtl - 1) {
4213 env->tl++;
4214 } else {
4215 env->pstate |= PS_RED;
4216 if (env->tl < env->maxtl)
4217 env->tl++;
4218 }
8194f35a
IK		 4219 tsptr = cpu_tsptr(env);
4220
5a834bb4 4221 tsptr->tstate = (get_ccr() << 32) |
91736d37 4222 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
5a834bb4 4223 get_cwp64();
8194f35a
IK		 4224 tsptr->tpc = env->pc;
4225 tsptr->tnpc = env->npc;
4226 tsptr->tt = intno;
5210977a
IK		 4227
4228 switch (intno) {
4229 case TT_IVEC:
4230 change_pstate(PS_PEF | PS_PRIV | PS_IG);
4231 break;
4232 case TT_TFAULT:
5210977a 4233 case TT_DFAULT:
87f6d3f6
IK		 4234 case TT_TMISS ... TT_TMISS + 3:
4235 case TT_DMISS ... TT_DMISS + 3:
4236 case TT_DPROT ... TT_DPROT + 3:
5210977a
IK		 4237 change_pstate(PS_PEF | PS_PRIV | PS_MG);
4238 break;
4239 default:
4240 change_pstate(PS_PEF | PS_PRIV | PS_AG);
4241 break;
91736d37 4242 }
5210977a 4243
5a834bb4
BS		 4244 if (intno == TT_CLRWIN) {
4245 set_cwp(cwp_dec(env->cwp - 1));
4246 } else if ((intno & 0x1c0) == TT_SPILL) {
4247 set_cwp(cwp_dec(env->cwp - env->cansave - 2));
4248 } else if ((intno & 0x1c0) == TT_FILL) {
4249 set_cwp(cwp_inc(env->cwp + 1));
4250 }
91736d37
BS		 4251 env->tbr &= ~0x7fffULL;
4252 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
4253 env->pc = env->tbr;
4254 env->npc = env->pc + 4;
821b19fe 4255 env->exception_index = -1;
ee5bbe38 4256}
91736d37
BS		 4257#else
4258#ifdef DEBUG_PCALL
4259static const char * const excp_names[0x80] = {
4260 [TT_TFAULT] = "Instruction Access Fault",
4261 [TT_ILL_INSN] = "Illegal Instruction",
4262 [TT_PRIV_INSN] = "Privileged Instruction",
4263 [TT_NFPU_INSN] = "FPU Disabled",
4264 [TT_WIN_OVF] = "Window Overflow",
4265 [TT_WIN_UNF] = "Window Underflow",
4266 [TT_UNALIGNED] = "Unaligned Memory Access",
4267 [TT_FP_EXCP] = "FPU Exception",
4268 [TT_DFAULT] = "Data Access Fault",
4269 [TT_TOVF] = "Tag Overflow",
4270 [TT_EXTINT | 0x1] = "External Interrupt 1",
4271 [TT_EXTINT | 0x2] = "External Interrupt 2",
4272 [TT_EXTINT | 0x3] = "External Interrupt 3",
4273 [TT_EXTINT | 0x4] = "External Interrupt 4",
4274 [TT_EXTINT | 0x5] = "External Interrupt 5",
4275 [TT_EXTINT | 0x6] = "External Interrupt 6",
4276 [TT_EXTINT | 0x7] = "External Interrupt 7",
4277 [TT_EXTINT | 0x8] = "External Interrupt 8",
4278 [TT_EXTINT | 0x9] = "External Interrupt 9",
4279 [TT_EXTINT | 0xa] = "External Interrupt 10",
4280 [TT_EXTINT | 0xb] = "External Interrupt 11",
4281 [TT_EXTINT | 0xc] = "External Interrupt 12",
4282 [TT_EXTINT | 0xd] = "External Interrupt 13",
4283 [TT_EXTINT | 0xe] = "External Interrupt 14",
4284 [TT_EXTINT | 0xf] = "External Interrupt 15",
4285 [TT_TOVF] = "Tag Overflow",
4286 [TT_CODE_ACCESS] = "Instruction Access Error",
4287 [TT_DATA_ACCESS] = "Data Access Error",
4288 [TT_DIV_ZERO] = "Division By Zero",
4289 [TT_NCP_INSN] = "Coprocessor Disabled",
4290};
4291#endif
ee5bbe38 4292
91736d37 4293void do_interrupt(CPUState *env)
ee5bbe38 4294{
91736d37
BS		 4295 int cwp, intno = env->exception_index;
4296
4297#ifdef DEBUG_PCALL
8fec2b8c 4298 if (qemu_loglevel_mask(CPU_LOG_INT)) {
91736d37
BS		 4299 static int count;
4300 const char *name;
4301
4302 if (intno < 0 || intno >= 0x100)
4303 name = "Unknown";
4304 else if (intno >= 0x80)
4305 name = "Trap Instruction";
4306 else {
4307 name = excp_names[intno];
4308 if (!name)
4309 name = "Unknown";
4310 }
4311
93fcfe39 4312 qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
91736d37
BS		 4313 count, name, intno,
4314 env->pc,
4315 env->npc, env->regwptr[6]);
93fcfe39 4316 log_cpu_state(env, 0);
91736d37
BS		 4317#if 0
4318 {
4319 int i;
4320 uint8_t *ptr;
4321
93fcfe39 4322 qemu_log(" code=");
91736d37
BS		 4323 ptr = (uint8_t *)env->pc;
4324 for(i = 0; i < 16; i++) {
93fcfe39 4325 qemu_log(" %02x", ldub(ptr + i));
91736d37 4326 }
93fcfe39 4327 qemu_log("\n");
91736d37
BS		 4328 }
4329#endif
4330 count++;
4331 }
4332#endif
4333#if !defined(CONFIG_USER_ONLY)
4334 if (env->psret == 0) {
4335 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
4336 env->exception_index);
4337 return;
4338 }
4339#endif
4340 env->psret = 0;
5a834bb4
BS		 4341 cwp = cwp_dec(env->cwp - 1);
4342 set_cwp(cwp);
91736d37
BS		 4343 env->regwptr[9] = env->pc;
4344 env->regwptr[10] = env->npc;
4345 env->psrps = env->psrs;
4346 env->psrs = 1;
4347 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
4348 env->pc = env->tbr;
4349 env->npc = env->pc + 4;
95372a39 4350 env->exception_index = -1;
b04d9890
FC		 4351
4352#if !defined(CONFIG_USER_ONLY)
4353 /* IRQ acknowledgment */
4354 if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) {
4355 env->qemu_irq_ack(env->irq_manager, intno);
4356 }
4357#endif
ee5bbe38 4358}
91736d37 4359#endif
ee5bbe38 4360
5fafdf24 4361#if !defined(CONFIG_USER_ONLY)
ee5bbe38 4362
d2889a3e
BS		 4363static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
4364 void *retaddr);
4365
ee5bbe38 4366#define MMUSUFFIX _mmu
d2889a3e 4367#define ALIGNED_ONLY
ee5bbe38
FB		 4368
4369#define SHIFT 0
4370#include "softmmu_template.h"
4371
4372#define SHIFT 1
4373#include "softmmu_template.h"
4374
4375#define SHIFT 2
4376#include "softmmu_template.h"
4377
4378#define SHIFT 3
4379#include "softmmu_template.h"
4380
c2bc0e38
BS		 4381/* XXX: make it generic ? */
4382static void cpu_restore_state2(void *retaddr)
4383{
4384 TranslationBlock *tb;
4385 unsigned long pc;
4386
4387 if (retaddr) {
4388 /* now we have a real cpu fault */
4389 pc = (unsigned long)retaddr;
4390 tb = tb_find_pc(pc);
4391 if (tb) {
4392 /* the PC is inside the translated code. It means that we have
4393 a virtual CPU fault */
618ba8e6 4394 cpu_restore_state(tb, env, pc);
c2bc0e38
BS		 4395 }
4396 }
4397}
4398
d2889a3e
BS		 4399static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
4400 void *retaddr)
4401{
94554550 4402#ifdef DEBUG_UNALIGNED
c2bc0e38
BS		 4403 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
4404 "\n", addr, env->pc);
94554550 4405#endif
c2bc0e38 4406 cpu_restore_state2(retaddr);
94554550 4407 raise_exception(TT_UNALIGNED);
d2889a3e 4408}
ee5bbe38
FB		 4409
4410/* try to fill the TLB and return an exception if error. If retaddr is
4411 NULL, it means that the function was called in C code (i.e. not
4412 from generated code or from helper.c) */
4413/* XXX: fix it to restore all registers */
6ebbf390 4414void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
ee5bbe38 4415{
ee5bbe38 4416 int ret;
ee5bbe38
FB		 4417 CPUState *saved_env;
4418
4419 /* XXX: hack to restore env in all cases, even if not called from
4420 generated code */
4421 saved_env = env;
4422 env = cpu_single_env;
4423
6ebbf390 4424 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ee5bbe38 4425 if (ret) {
c2bc0e38 4426 cpu_restore_state2(retaddr);
ee5bbe38
FB		 4427 cpu_loop_exit();
4428 }
4429 env = saved_env;
4430}
4431
3c7b48b7 4432#endif /* !CONFIG_USER_ONLY */
6c36d3fa
BS		 4433
4434#ifndef TARGET_SPARC64
3c7b48b7 4435#if !defined(CONFIG_USER_ONLY)
c227f099 4436void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
e18231a3 4437 int is_asi, int size)
6c36d3fa
BS		 4438{
4439 CPUState *saved_env;
576c2cdc 4440 int fault_type;
6c36d3fa
BS		 4441
4442 /* XXX: hack to restore env in all cases, even if not called from
4443 generated code */
4444 saved_env = env;
4445 env = cpu_single_env;
8543e2cf
BS		 4446#ifdef DEBUG_UNASSIGNED
4447 if (is_asi)
e18231a3 4448 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
77f193da 4449 " asi 0x%02x from " TARGET_FMT_lx "\n",
e18231a3
BS		 4450 is_exec ? "exec" : is_write ? "write" : "read", size,
4451 size == 1 ? "" : "s", addr, is_asi, env->pc);
8543e2cf 4452 else
e18231a3
BS		 4453 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
4454 " from " TARGET_FMT_lx "\n",
4455 is_exec ? "exec" : is_write ? "write" : "read", size,
4456 size == 1 ? "" : "s", addr, env->pc);
8543e2cf 4457#endif
576c2cdc
AT		 4458 /* Don't overwrite translation and access faults */
4459 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
4460 if ((fault_type > 4) || (fault_type == 0)) {
4461 env->mmuregs[3] = 0; /* Fault status register */
4462 if (is_asi)
4463 env->mmuregs[3] |= 1 << 16;
4464 if (env->psrs)
4465 env->mmuregs[3] |= 1 << 5;
4466 if (is_exec)
4467 env->mmuregs[3] |= 1 << 6;
4468 if (is_write)
4469 env->mmuregs[3] |= 1 << 7;
4470 env->mmuregs[3] |= (5 << 2) | 2;
4471 /* SuperSPARC will never place instruction fault addresses in the FAR */
4472 if (!is_exec) {
4473 env->mmuregs[4] = addr; /* Fault address register */
4474 }
4475 }
4476 /* overflow (same type fault was not read before another fault) */
4477 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
4478 env->mmuregs[3] |= 1;
4479 }
4480
6c36d3fa 4481 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
1b2e93c1
BS		 4482 if (is_exec)
4483 raise_exception(TT_CODE_ACCESS);
4484 else
4485 raise_exception(TT_DATA_ACCESS);
6c36d3fa 4486 }
576c2cdc
AT		 4487
4488 /* flush neverland mappings created during no-fault mode,
4489 so the sequential MMU faults report proper fault types */
4490 if (env->mmuregs[0] & MMU_NF) {
4491 tlb_flush(env, 1);
4492 }
15e7c451
AT		 4493
4494 env = saved_env;
6c36d3fa 4495}
3c7b48b7
PB		 4496#endif
4497#else
4498#if defined(CONFIG_USER_ONLY)
4499static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
4500 int is_asi, int size)
6c36d3fa 4501#else
c227f099 4502void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
e18231a3 4503 int is_asi, int size)
3c7b48b7 4504#endif
6c36d3fa 4505{
6c36d3fa
BS		 4506 CPUState *saved_env;
4507
4508 /* XXX: hack to restore env in all cases, even if not called from
4509 generated code */
4510 saved_env = env;
4511 env = cpu_single_env;
dffbe217
IK		 4512
4513#ifdef DEBUG_UNASSIGNED
77f193da
BS		 4514 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
4515 "\n", addr, env->pc);
6c36d3fa 4516#endif
dffbe217 4517
1b2e93c1
BS		 4518 if (is_exec)
4519 raise_exception(TT_CODE_ACCESS);
4520 else
4521 raise_exception(TT_DATA_ACCESS);
dffbe217
IK		 4522
4523 env = saved_env;
6c36d3fa
BS		 4524}
4525#endif
20c9f095 4526
3c7b48b7 4527
f4b1a842
BS		 4528#ifdef TARGET_SPARC64
4529void helper_tick_set_count(void *opaque, uint64_t count)
4530{
4531#if !defined(CONFIG_USER_ONLY)
4532 cpu_tick_set_count(opaque, count);
4533#endif
4534}
4535
4536uint64_t helper_tick_get_count(void *opaque)
4537{
4538#if !defined(CONFIG_USER_ONLY)
4539 return cpu_tick_get_count(opaque);
4540#else
4541 return 0;
4542#endif
4543}
4544
4545void helper_tick_set_limit(void *opaque, uint64_t limit)
4546{
4547#if !defined(CONFIG_USER_ONLY)
4548 cpu_tick_set_limit(opaque, limit);
4549#endif
4550}
4551#endif
Qemu copy for testing