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Move #include to speed up compilation
[qemu.git] / target-sparc / op_helper.c
CommitLineData
e8af50a3 1#include "exec.h"
eed152bb 2#include "host-utils.h"
1a2fb1c0 3#include "helper.h"
0828b448
BS		 4#if !defined(CONFIG_USER_ONLY)
5#include "softmmu_exec.h"
6#endif /* !defined(CONFIG_USER_ONLY) */
e8af50a3 7
83469015 8//#define DEBUG_PCALL
e80cfcfc 9//#define DEBUG_MMU
952a328f 10//#define DEBUG_MXCC
94554550 11//#define DEBUG_UNALIGNED
6c36d3fa 12//#define DEBUG_UNASSIGNED
8543e2cf 13//#define DEBUG_ASI
e80cfcfc 14
952a328f
BS		 15#ifdef DEBUG_MMU
16#define DPRINTF_MMU(fmt, args...) \
17do { printf("MMU: " fmt , ##args); } while (0)
18#else
19#define DPRINTF_MMU(fmt, args...)
20#endif
21
22#ifdef DEBUG_MXCC
23#define DPRINTF_MXCC(fmt, args...) \
24do { printf("MXCC: " fmt , ##args); } while (0)
25#else
26#define DPRINTF_MXCC(fmt, args...)
27#endif
28
8543e2cf
BS		 29#ifdef DEBUG_ASI
30#define DPRINTF_ASI(fmt, args...) \
31do { printf("ASI: " fmt , ##args); } while (0)
32#else
33#define DPRINTF_ASI(fmt, args...)
34#endif
35
9d893301
FB		 36void raise_exception(int tt)
37{
38 env->exception_index = tt;
39 cpu_loop_exit();
3b46e624 40}
9d893301 41
1a2fb1c0 42void helper_trap(target_ulong nb_trap)
417454b0 43{
1a2fb1c0
BS		 44 env->exception_index = TT_TRAP + (nb_trap & 0x7f);
45 cpu_loop_exit();
46}
47
48void helper_trapcc(target_ulong nb_trap, target_ulong do_trap)
49{
50 if (do_trap) {
51 env->exception_index = TT_TRAP + (nb_trap & 0x7f);
52 cpu_loop_exit();
53 }
54}
55
2b29924f
BS		 56void helper_check_align(target_ulong addr, uint32_t align)
57{
58 if (addr & align)
59 raise_exception(TT_UNALIGNED);
60}
61
44e7757c
BS		 62#define F_HELPER(name, p) void helper_f##name##p(void)
63
4e14008f 64#if defined(CONFIG_USER_ONLY)
44e7757c
BS		 65#define F_BINOP(name) \
66 F_HELPER(name, s) \
67 { \
68 FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \
69 } \
70 F_HELPER(name, d) \
71 { \
72 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
4e14008f
BS		 73 } \
74 F_HELPER(name, q) \
75 { \
76 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
44e7757c 77 }
4e14008f
BS		 78#else
79#define F_BINOP(name) \
80 F_HELPER(name, s) \
81 { \
82 FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \
83 } \
84 F_HELPER(name, d) \
85 { \
86 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
87 }
88#endif
44e7757c
BS		 89
90F_BINOP(add);
91F_BINOP(sub);
92F_BINOP(mul);
93F_BINOP(div);
94#undef F_BINOP
95
96void helper_fsmuld(void)
1a2fb1c0 97{
44e7757c
BS		 98 DT0 = float64_mul(float32_to_float64(FT0, &env->fp_status),
99 float32_to_float64(FT1, &env->fp_status),
100 &env->fp_status);
101}
1a2fb1c0 102
4e14008f
BS		 103#if defined(CONFIG_USER_ONLY)
104void helper_fdmulq(void)
105{
106 QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
107 float64_to_float128(DT1, &env->fp_status),
108 &env->fp_status);
109}
110#endif
111
44e7757c
BS		 112F_HELPER(neg, s)
113{
114 FT0 = float32_chs(FT1);
417454b0
BS		 115}
116
44e7757c
BS		 117#ifdef TARGET_SPARC64
118F_HELPER(neg, d)
7e8c2b6c 119{
44e7757c 120 DT0 = float64_chs(DT1);
7e8c2b6c 121}
4e14008f
BS		 122
123#if defined(CONFIG_USER_ONLY)
124F_HELPER(neg, q)
125{
126 QT0 = float128_chs(QT1);
127}
128#endif
44e7757c
BS		 129#endif
130
131/* Integer to float conversion. */
132F_HELPER(ito, s)
a0c4cb4a 133{
ec230928 134 FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
a0c4cb4a
FB		 135}
136
44e7757c 137F_HELPER(ito, d)
a0c4cb4a 138{
ec230928 139 DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
a0c4cb4a 140}
9c2b428e 141
4e14008f
BS		 142#if defined(CONFIG_USER_ONLY)
143F_HELPER(ito, q)
144{
145 QT0 = int32_to_float128(*((int32_t *)&FT1), &env->fp_status);
146}
147#endif
148
1e64e78d 149#ifdef TARGET_SPARC64
44e7757c 150F_HELPER(xto, s)
1e64e78d 151{
1e64e78d 152 FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
1e64e78d
BS		 153}
154
44e7757c 155F_HELPER(xto, d)
1e64e78d 156{
1e64e78d 157 DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
1e64e78d 158}
4e14008f
BS		 159#if defined(CONFIG_USER_ONLY)
160F_HELPER(xto, q)
161{
162 QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
163}
164#endif
44e7757c
BS		 165#endif
166#undef F_HELPER
167
168/* floating point conversion */
169void helper_fdtos(void)
170{
171 FT0 = float64_to_float32(DT1, &env->fp_status);
172}
173
174void helper_fstod(void)
175{
176 DT0 = float32_to_float64(FT1, &env->fp_status);
177}
9c2b428e 178
4e14008f
BS		 179#if defined(CONFIG_USER_ONLY)
180void helper_fqtos(void)
181{
182 FT0 = float128_to_float32(QT1, &env->fp_status);
183}
184
185void helper_fstoq(void)
186{
187 QT0 = float32_to_float128(FT1, &env->fp_status);
188}
189
190void helper_fqtod(void)
191{
192 DT0 = float128_to_float64(QT1, &env->fp_status);
193}
194
195void helper_fdtoq(void)
196{
197 QT0 = float64_to_float128(DT1, &env->fp_status);
198}
199#endif
200
44e7757c
BS		 201/* Float to integer conversion. */
202void helper_fstoi(void)
203{
204 *((int32_t *)&FT0) = float32_to_int32_round_to_zero(FT1, &env->fp_status);
205}
206
207void helper_fdtoi(void)
208{
209 *((int32_t *)&FT0) = float64_to_int32_round_to_zero(DT1, &env->fp_status);
210}
211
4e14008f
BS		 212#if defined(CONFIG_USER_ONLY)
213void helper_fqtoi(void)
214{
215 *((int32_t *)&FT0) = float128_to_int32_round_to_zero(QT1, &env->fp_status);
216}
217#endif
218
44e7757c
BS		 219#ifdef TARGET_SPARC64
220void helper_fstox(void)
221{
222 *((int64_t *)&DT0) = float32_to_int64_round_to_zero(FT1, &env->fp_status);
223}
224
225void helper_fdtox(void)
226{
227 *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
228}
229
4e14008f
BS		 230#if defined(CONFIG_USER_ONLY)
231void helper_fqtox(void)
232{
233 *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);
234}
235#endif
236
44e7757c
BS		 237void helper_faligndata(void)
238{
239 uint64_t tmp;
240
241 tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
242 tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
243 *((uint64_t *)&DT0) = tmp;
244}
245
246void helper_movl_FT0_0(void)
247{
248 *((uint32_t *)&FT0) = 0;
249}
250
251void helper_movl_DT0_0(void)
252{
253 *((uint64_t *)&DT0) = 0;
254}
255
256void helper_movl_FT0_1(void)
257{
258 *((uint32_t *)&FT0) = 0xffffffff;
259}
260
261void helper_movl_DT0_1(void)
262{
263 *((uint64_t *)&DT0) = 0xffffffffffffffffULL;
264}
265
266void helper_fnot(void)
267{
268 *(uint64_t *)&DT0 = ~*(uint64_t *)&DT1;
269}
270
271void helper_fnots(void)
272{
273 *(uint32_t *)&FT0 = ~*(uint32_t *)&FT1;
274}
275
276void helper_fnor(void)
277{
278 *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 | *(uint64_t *)&DT1);
279}
280
281void helper_fnors(void)
282{
283 *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 | *(uint32_t *)&FT1);
284}
285
286void helper_for(void)
287{
288 *(uint64_t *)&DT0 |= *(uint64_t *)&DT1;
289}
290
291void helper_fors(void)
292{
293 *(uint32_t *)&FT0 |= *(uint32_t *)&FT1;
294}
295
296void helper_fxor(void)
297{
298 *(uint64_t *)&DT0 ^= *(uint64_t *)&DT1;
299}
300
301void helper_fxors(void)
302{
303 *(uint32_t *)&FT0 ^= *(uint32_t *)&FT1;
304}
305
306void helper_fand(void)
307{
308 *(uint64_t *)&DT0 &= *(uint64_t *)&DT1;
309}
310
311void helper_fands(void)
312{
313 *(uint32_t *)&FT0 &= *(uint32_t *)&FT1;
314}
315
316void helper_fornot(void)
317{
318 *(uint64_t *)&DT0 = *(uint64_t *)&DT0 | ~*(uint64_t *)&DT1;
319}
320
321void helper_fornots(void)
322{
323 *(uint32_t *)&FT0 = *(uint32_t *)&FT0 | ~*(uint32_t *)&FT1;
324}
325
326void helper_fandnot(void)
327{
328 *(uint64_t *)&DT0 = *(uint64_t *)&DT0 & ~*(uint64_t *)&DT1;
329}
330
331void helper_fandnots(void)
332{
333 *(uint32_t *)&FT0 = *(uint32_t *)&FT0 & ~*(uint32_t *)&FT1;
334}
335
336void helper_fnand(void)
337{
338 *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 & *(uint64_t *)&DT1);
339}
340
341void helper_fnands(void)
342{
343 *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 & *(uint32_t *)&FT1);
344}
345
346void helper_fxnor(void)
347{
348 *(uint64_t *)&DT0 ^= ~*(uint64_t *)&DT1;
349}
350
351void helper_fxnors(void)
352{
353 *(uint32_t *)&FT0 ^= ~*(uint32_t *)&FT1;
354}
355
356#ifdef WORDS_BIGENDIAN
357#define VIS_B64(n) b[7 - (n)]
358#define VIS_W64(n) w[3 - (n)]
359#define VIS_SW64(n) sw[3 - (n)]
360#define VIS_L64(n) l[1 - (n)]
361#define VIS_B32(n) b[3 - (n)]
362#define VIS_W32(n) w[1 - (n)]
363#else
364#define VIS_B64(n) b[n]
365#define VIS_W64(n) w[n]
366#define VIS_SW64(n) sw[n]
367#define VIS_L64(n) l[n]
368#define VIS_B32(n) b[n]
369#define VIS_W32(n) w[n]
370#endif
371
372typedef union {
373 uint8_t b[8];
374 uint16_t w[4];
375 int16_t sw[4];
376 uint32_t l[2];
377 float64 d;
378} vis64;
379
380typedef union {
381 uint8_t b[4];
382 uint16_t w[2];
383 uint32_t l;
384 float32 f;
385} vis32;
386
387void helper_fpmerge(void)
388{
389 vis64 s, d;
390
391 s.d = DT0;
392 d.d = DT1;
393
394 // Reverse calculation order to handle overlap
395 d.VIS_B64(7) = s.VIS_B64(3);
396 d.VIS_B64(6) = d.VIS_B64(3);
397 d.VIS_B64(5) = s.VIS_B64(2);
398 d.VIS_B64(4) = d.VIS_B64(2);
399 d.VIS_B64(3) = s.VIS_B64(1);
400 d.VIS_B64(2) = d.VIS_B64(1);
401 d.VIS_B64(1) = s.VIS_B64(0);
402 //d.VIS_B64(0) = d.VIS_B64(0);
403
404 DT0 = d.d;
405}
406
407void helper_fmul8x16(void)
408{
409 vis64 s, d;
410 uint32_t tmp;
411
412 s.d = DT0;
413 d.d = DT1;
414
415#define PMUL(r) \
416 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
417 if ((tmp & 0xff) > 0x7f) \
418 tmp += 0x100; \
419 d.VIS_W64(r) = tmp >> 8;
420
421 PMUL(0);
422 PMUL(1);
423 PMUL(2);
424 PMUL(3);
425#undef PMUL
426
427 DT0 = d.d;
428}
429
430void helper_fmul8x16al(void)
431{
432 vis64 s, d;
433 uint32_t tmp;
434
435 s.d = DT0;
436 d.d = DT1;
437
438#define PMUL(r) \
439 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
440 if ((tmp & 0xff) > 0x7f) \
441 tmp += 0x100; \
442 d.VIS_W64(r) = tmp >> 8;
443
444 PMUL(0);
445 PMUL(1);
446 PMUL(2);
447 PMUL(3);
448#undef PMUL
449
450 DT0 = d.d;
451}
452
453void helper_fmul8x16au(void)
454{
455 vis64 s, d;
456 uint32_t tmp;
457
458 s.d = DT0;
459 d.d = DT1;
460
461#define PMUL(r) \
462 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
463 if ((tmp & 0xff) > 0x7f) \
464 tmp += 0x100; \
465 d.VIS_W64(r) = tmp >> 8;
466
467 PMUL(0);
468 PMUL(1);
469 PMUL(2);
470 PMUL(3);
471#undef PMUL
472
473 DT0 = d.d;
474}
475
476void helper_fmul8sux16(void)
477{
478 vis64 s, d;
479 uint32_t tmp;
480
481 s.d = DT0;
482 d.d = DT1;
483
484#define PMUL(r) \
485 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
486 if ((tmp & 0xff) > 0x7f) \
487 tmp += 0x100; \
488 d.VIS_W64(r) = tmp >> 8;
489
490 PMUL(0);
491 PMUL(1);
492 PMUL(2);
493 PMUL(3);
494#undef PMUL
495
496 DT0 = d.d;
497}
498
499void helper_fmul8ulx16(void)
500{
501 vis64 s, d;
502 uint32_t tmp;
503
504 s.d = DT0;
505 d.d = DT1;
506
507#define PMUL(r) \
508 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
509 if ((tmp & 0xff) > 0x7f) \
510 tmp += 0x100; \
511 d.VIS_W64(r) = tmp >> 8;
512
513 PMUL(0);
514 PMUL(1);
515 PMUL(2);
516 PMUL(3);
517#undef PMUL
518
519 DT0 = d.d;
520}
521
522void helper_fmuld8sux16(void)
523{
524 vis64 s, d;
525 uint32_t tmp;
526
527 s.d = DT0;
528 d.d = DT1;
529
530#define PMUL(r) \
531 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
532 if ((tmp & 0xff) > 0x7f) \
533 tmp += 0x100; \
534 d.VIS_L64(r) = tmp;
535
536 // Reverse calculation order to handle overlap
537 PMUL(1);
538 PMUL(0);
539#undef PMUL
540
541 DT0 = d.d;
542}
543
544void helper_fmuld8ulx16(void)
545{
546 vis64 s, d;
547 uint32_t tmp;
548
549 s.d = DT0;
550 d.d = DT1;
551
552#define PMUL(r) \
553 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
554 if ((tmp & 0xff) > 0x7f) \
555 tmp += 0x100; \
556 d.VIS_L64(r) = tmp;
557
558 // Reverse calculation order to handle overlap
559 PMUL(1);
560 PMUL(0);
561#undef PMUL
562
563 DT0 = d.d;
564}
565
566void helper_fexpand(void)
567{
568 vis32 s;
569 vis64 d;
570
571 s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
572 d.d = DT1;
573 d.VIS_L64(0) = s.VIS_W32(0) << 4;
574 d.VIS_L64(1) = s.VIS_W32(1) << 4;
575 d.VIS_L64(2) = s.VIS_W32(2) << 4;
576 d.VIS_L64(3) = s.VIS_W32(3) << 4;
577
578 DT0 = d.d;
579}
580
581#define VIS_HELPER(name, F) \
582 void name##16(void) \
583 { \
584 vis64 s, d; \
585 \
586 s.d = DT0; \
587 d.d = DT1; \
588 \
589 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
590 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
591 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
592 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
593 \
594 DT0 = d.d; \
595 } \
596 \
597 void name##16s(void) \
598 { \
599 vis32 s, d; \
600 \
601 s.f = FT0; \
602 d.f = FT1; \
603 \
604 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
605 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
606 \
607 FT0 = d.f; \
608 } \
609 \
610 void name##32(void) \
611 { \
612 vis64 s, d; \
613 \
614 s.d = DT0; \
615 d.d = DT1; \
616 \
617 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
618 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
619 \
620 DT0 = d.d; \
621 } \
622 \
623 void name##32s(void) \
624 { \
625 vis32 s, d; \
626 \
627 s.f = FT0; \
628 d.f = FT1; \
629 \
630 d.l = F(d.l, s.l); \
631 \
632 FT0 = d.f; \
633 }
634
635#define FADD(a, b) ((a) + (b))
636#define FSUB(a, b) ((a) - (b))
637VIS_HELPER(helper_fpadd, FADD)
638VIS_HELPER(helper_fpsub, FSUB)
639
640#define VIS_CMPHELPER(name, F) \
641 void name##16(void) \
642 { \
643 vis64 s, d; \
644 \
645 s.d = DT0; \
646 d.d = DT1; \
647 \
648 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
649 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
650 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
651 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
652 \
653 DT0 = d.d; \
654 } \
655 \
656 void name##32(void) \
657 { \
658 vis64 s, d; \
659 \
660 s.d = DT0; \
661 d.d = DT1; \
662 \
663 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
664 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
665 \
666 DT0 = d.d; \
667 }
668
669#define FCMPGT(a, b) ((a) > (b))
670#define FCMPEQ(a, b) ((a) == (b))
671#define FCMPLE(a, b) ((a) <= (b))
672#define FCMPNE(a, b) ((a) != (b))
673
674VIS_CMPHELPER(helper_fcmpgt, FCMPGT)
675VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)
676VIS_CMPHELPER(helper_fcmple, FCMPLE)
677VIS_CMPHELPER(helper_fcmpne, FCMPNE)
678#endif
679
680void helper_check_ieee_exceptions(void)
681{
682 target_ulong status;
683
684 status = get_float_exception_flags(&env->fp_status);
685 if (status) {
686 /* Copy IEEE 754 flags into FSR */
687 if (status & float_flag_invalid)
688 env->fsr |= FSR_NVC;
689 if (status & float_flag_overflow)
690 env->fsr |= FSR_OFC;
691 if (status & float_flag_underflow)
692 env->fsr |= FSR_UFC;
693 if (status & float_flag_divbyzero)
694 env->fsr |= FSR_DZC;
695 if (status & float_flag_inexact)
696 env->fsr |= FSR_NXC;
697
698 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
699 /* Unmasked exception, generate a trap */
700 env->fsr |= FSR_FTT_IEEE_EXCP;
701 raise_exception(TT_FP_EXCP);
702 } else {
703 /* Accumulate exceptions */
704 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
705 }
706 }
707}
708
709void helper_clear_float_exceptions(void)
710{
711 set_float_exception_flags(0, &env->fp_status);
712}
713
7e8c2b6c 714void helper_fabss(void)
e8af50a3 715{
7a0e1f41 716 FT0 = float32_abs(FT1);
e8af50a3
FB		 717}
718
3475187d 719#ifdef TARGET_SPARC64
7e8c2b6c 720void helper_fabsd(void)
3475187d
FB		 721{
722 DT0 = float64_abs(DT1);
723}
4e14008f
BS		 724
725#if defined(CONFIG_USER_ONLY)
726void helper_fabsq(void)
727{
728 QT0 = float128_abs(QT1);
729}
730#endif
3475187d
FB		 731#endif
732
7e8c2b6c 733void helper_fsqrts(void)
e8af50a3 734{
7a0e1f41 735 FT0 = float32_sqrt(FT1, &env->fp_status);
e8af50a3
FB		 736}
737
7e8c2b6c 738void helper_fsqrtd(void)
e8af50a3 739{
7a0e1f41 740 DT0 = float64_sqrt(DT1, &env->fp_status);
e8af50a3
FB		 741}
742
4e14008f
BS		 743#if defined(CONFIG_USER_ONLY)
744void helper_fsqrtq(void)
745{
746 QT0 = float128_sqrt(QT1, &env->fp_status);
747}
748#endif
749
417454b0 750#define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
7e8c2b6c 751 void glue(helper_, name) (void) \
65ce8c2f 752 { \
1a2fb1c0
BS		 753 target_ulong new_fsr; \
754 \
65ce8c2f
FB		 755 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
756 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
757 case float_relation_unordered: \
1a2fb1c0 758 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
417454b0 759 if ((env->fsr & FSR_NVM) || TRAP) { \
1a2fb1c0 760 env->fsr |= new_fsr; \
417454b0
BS		 761 env->fsr |= FSR_NVC; \
762 env->fsr |= FSR_FTT_IEEE_EXCP; \
65ce8c2f
FB		 763 raise_exception(TT_FP_EXCP); \
764 } else { \
765 env->fsr |= FSR_NVA; \
766 } \
767 break; \
768 case float_relation_less: \
1a2fb1c0 769 new_fsr = FSR_FCC0 << FS; \
65ce8c2f
FB		 770 break; \
771 case float_relation_greater: \
1a2fb1c0 772 new_fsr = FSR_FCC1 << FS; \
65ce8c2f
FB		 773 break; \
774 default: \
1a2fb1c0 775 new_fsr = 0; \
65ce8c2f
FB		 776 break; \
777 } \
1a2fb1c0 778 env->fsr |= new_fsr; \
e8af50a3 779 }
e8af50a3 780
417454b0
BS		 781GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0);
782GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
783
784GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1);
785GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
3475187d 786
4e14008f
BS		 787#ifdef CONFIG_USER_ONLY
788GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
789GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
790#endif
791
3475187d 792#ifdef TARGET_SPARC64
417454b0
BS		 793GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0);
794GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
795
796GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0);
797GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
798
799GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0);
800GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
801
802GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1);
803GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
3475187d 804
417454b0
BS		 805GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1);
806GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
3475187d 807
417454b0
BS		 808GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1);
809GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
4e14008f
BS		 810#ifdef CONFIG_USER_ONLY
811GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
812GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
813GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
814GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
815GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
816GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
817#endif
3475187d
FB		 818#endif
819
1a2fb1c0 820#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && defined(DEBUG_MXCC)
952a328f
BS		 821static void dump_mxcc(CPUState *env)
822{
823 printf("mxccdata: %016llx %016llx %016llx %016llx\n",
824 env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]);
825 printf("mxccregs: %016llx %016llx %016llx %016llx\n"
826 " %016llx %016llx %016llx %016llx\n",
827 env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3],
828 env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]);
829}
830#endif
831
1a2fb1c0
BS		 832#if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
833 && defined(DEBUG_ASI)
834static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
835 uint64_t r1)
8543e2cf
BS		 836{
837 switch (size)
838 {
839 case 1:
1a2fb1c0
BS		 840 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
841 addr, asi, r1 & 0xff);
8543e2cf
BS		 842 break;
843 case 2:
1a2fb1c0
BS		 844 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
845 addr, asi, r1 & 0xffff);
8543e2cf
BS		 846 break;
847 case 4:
1a2fb1c0
BS		 848 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
849 addr, asi, r1 & 0xffffffff);
8543e2cf
BS		 850 break;
851 case 8:
1a2fb1c0
BS		 852 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
853 addr, asi, r1);
8543e2cf
BS		 854 break;
855 }
856}
857#endif
858
1a2fb1c0
BS		 859#ifndef TARGET_SPARC64
860#ifndef CONFIG_USER_ONLY
861uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
e8af50a3 862{
1a2fb1c0 863 uint64_t ret = 0;
8543e2cf 864#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
1a2fb1c0 865 uint32_t last_addr = addr;
952a328f 866#endif
e80cfcfc
FB		 867
868 switch (asi) {
6c36d3fa 869 case 2: /* SuperSparc MXCC registers */
1a2fb1c0 870 switch (addr) {
952a328f 871 case 0x01c00a00: /* MXCC control register */
1a2fb1c0
BS		 872 if (size == 8)
873 ret = env->mxccregs[3];
874 else
875 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 876 break;
877 case 0x01c00a04: /* MXCC control register */
878 if (size == 4)
879 ret = env->mxccregs[3];
880 else
1a2fb1c0 881 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f 882 break;
295db113
BS		 883 case 0x01c00c00: /* Module reset register */
884 if (size == 8) {
1a2fb1c0 885 ret = env->mxccregs[5];
295db113
BS		 886 // should we do something here?
887 } else
1a2fb1c0 888 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
295db113 889 break;
952a328f 890 case 0x01c00f00: /* MBus port address register */
1a2fb1c0
BS		 891 if (size == 8)
892 ret = env->mxccregs[7];
893 else
894 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 895 break;
896 default:
1a2fb1c0 897 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
952a328f
BS		 898 break;
899 }
1a2fb1c0
BS		 900 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, addr = %08x -> ret = %08x,"
901 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
952a328f
BS		 902#ifdef DEBUG_MXCC
903 dump_mxcc(env);
904#endif
6c36d3fa 905 break;
e8af50a3 906 case 3: /* MMU probe */
0f8a249a
BS		 907 {
908 int mmulev;
909
1a2fb1c0 910 mmulev = (addr >> 8) & 15;
0f8a249a
BS		 911 if (mmulev > 4)
912 ret = 0;
1a2fb1c0
BS		 913 else
914 ret = mmu_probe(env, addr, mmulev);
915 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
916 addr, mmulev, ret);
0f8a249a
BS		 917 }
918 break;
e8af50a3 919 case 4: /* read MMU regs */
0f8a249a 920 {
1a2fb1c0 921 int reg = (addr >> 8) & 0x1f;
3b46e624 922
0f8a249a
BS		 923 ret = env->mmuregs[reg];
924 if (reg == 3) /* Fault status cleared on read */
3dd9a152
BS		 925 env->mmuregs[3] = 0;
926 else if (reg == 0x13) /* Fault status read */
927 ret = env->mmuregs[3];
928 else if (reg == 0x14) /* Fault address read */
929 ret = env->mmuregs[4];
1a2fb1c0 930 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
0f8a249a
BS		 931 }
932 break;
045380be
BS		 933 case 5: // Turbosparc ITLB Diagnostic
934 case 6: // Turbosparc DTLB Diagnostic
935 case 7: // Turbosparc IOTLB Diagnostic
936 break;
6c36d3fa
BS		 937 case 9: /* Supervisor code access */
938 switch(size) {
939 case 1:
1a2fb1c0 940 ret = ldub_code(addr);
6c36d3fa
BS		 941 break;
942 case 2:
1a2fb1c0 943 ret = lduw_code(addr & ~1);
6c36d3fa
BS		 944 break;
945 default:
946 case 4:
1a2fb1c0 947 ret = ldl_code(addr & ~3);
6c36d3fa
BS		 948 break;
949 case 8:
1a2fb1c0 950 ret = ldq_code(addr & ~7);
6c36d3fa
BS		 951 break;
952 }
953 break;
81ad8ba2
BS		 954 case 0xa: /* User data access */
955 switch(size) {
956 case 1:
1a2fb1c0 957 ret = ldub_user(addr);
81ad8ba2
BS		 958 break;
959 case 2:
1a2fb1c0 960 ret = lduw_user(addr & ~1);
81ad8ba2
BS		 961 break;
962 default:
963 case 4:
1a2fb1c0 964 ret = ldl_user(addr & ~3);
81ad8ba2
BS		 965 break;
966 case 8:
1a2fb1c0 967 ret = ldq_user(addr & ~7);
81ad8ba2
BS		 968 break;
969 }
970 break;
971 case 0xb: /* Supervisor data access */
972 switch(size) {
973 case 1:
1a2fb1c0 974 ret = ldub_kernel(addr);
81ad8ba2
BS		 975 break;
976 case 2:
1a2fb1c0 977 ret = lduw_kernel(addr & ~1);
81ad8ba2
BS		 978 break;
979 default:
980 case 4:
1a2fb1c0 981 ret = ldl_kernel(addr & ~3);
81ad8ba2
BS		 982 break;
983 case 8:
1a2fb1c0 984 ret = ldq_kernel(addr & ~7);
81ad8ba2
BS		 985 break;
986 }
987 break;
6c36d3fa
BS		 988 case 0xc: /* I-cache tag */
989 case 0xd: /* I-cache data */
990 case 0xe: /* D-cache tag */
991 case 0xf: /* D-cache data */
992 break;
993 case 0x20: /* MMU passthrough */
02aab46a
FB		 994 switch(size) {
995 case 1:
1a2fb1c0 996 ret = ldub_phys(addr);
02aab46a
FB		 997 break;
998 case 2:
1a2fb1c0 999 ret = lduw_phys(addr & ~1);
02aab46a
FB		 1000 break;
1001 default:
1002 case 4:
1a2fb1c0 1003 ret = ldl_phys(addr & ~3);
02aab46a 1004 break;
9e61bde5 1005 case 8:
1a2fb1c0 1006 ret = ldq_phys(addr & ~7);
0f8a249a 1007 break;
02aab46a 1008 }
0f8a249a 1009 break;
7d85892b 1010 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
5dcb6b91
BS		 1011 switch(size) {
1012 case 1:
1a2fb1c0 1013 ret = ldub_phys((target_phys_addr_t)addr
5dcb6b91
BS		 1014 | ((target_phys_addr_t)(asi & 0xf) << 32));
1015 break;
1016 case 2:
1a2fb1c0 1017 ret = lduw_phys((target_phys_addr_t)(addr & ~1)
5dcb6b91
BS		 1018 | ((target_phys_addr_t)(asi & 0xf) << 32));
1019 break;
1020 default:
1021 case 4:
1a2fb1c0 1022 ret = ldl_phys((target_phys_addr_t)(addr & ~3)
5dcb6b91
BS		 1023 | ((target_phys_addr_t)(asi & 0xf) << 32));
1024 break;
1025 case 8:
1a2fb1c0 1026 ret = ldq_phys((target_phys_addr_t)(addr & ~7)
5dcb6b91 1027 | ((target_phys_addr_t)(asi & 0xf) << 32));
0f8a249a 1028 break;
5dcb6b91 1029 }
0f8a249a 1030 break;
045380be
BS		 1031 case 0x30: // Turbosparc secondary cache diagnostic
1032 case 0x31: // Turbosparc RAM snoop
1033 case 0x32: // Turbosparc page table descriptor diagnostic
666c87aa
BS		 1034 case 0x39: /* data cache diagnostic register */
1035 ret = 0;
1036 break;
045380be 1037 case 8: /* User code access, XXX */
e8af50a3 1038 default:
1a2fb1c0 1039 do_unassigned_access(addr, 0, 0, asi);
0f8a249a
BS		 1040 ret = 0;
1041 break;
e8af50a3 1042 }
81ad8ba2
BS		 1043 if (sign) {
1044 switch(size) {
1045 case 1:
1a2fb1c0 1046 ret = (int8_t) ret;
e32664fb 1047 break;
81ad8ba2 1048 case 2:
1a2fb1c0
BS		 1049 ret = (int16_t) ret;
1050 break;
1051 case 4:
1052 ret = (int32_t) ret;
e32664fb 1053 break;
81ad8ba2 1054 default:
81ad8ba2
BS		 1055 break;
1056 }
1057 }
8543e2cf 1058#ifdef DEBUG_ASI
1a2fb1c0 1059 dump_asi("read ", last_addr, asi, size, ret);
8543e2cf 1060#endif
1a2fb1c0 1061 return ret;
e8af50a3
FB		 1062}
1063
1a2fb1c0 1064void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
e8af50a3
FB		 1065{
1066 switch(asi) {
6c36d3fa 1067 case 2: /* SuperSparc MXCC registers */
1a2fb1c0 1068 switch (addr) {
952a328f
BS		 1069 case 0x01c00000: /* MXCC stream data register 0 */
1070 if (size == 8)
1a2fb1c0 1071 env->mxccdata[0] = val;
952a328f 1072 else
1a2fb1c0 1073 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1074 break;
1075 case 0x01c00008: /* MXCC stream data register 1 */
1076 if (size == 8)
1a2fb1c0 1077 env->mxccdata[1] = val;
952a328f 1078 else
1a2fb1c0 1079 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1080 break;
1081 case 0x01c00010: /* MXCC stream data register 2 */
1082 if (size == 8)
1a2fb1c0 1083 env->mxccdata[2] = val;
952a328f 1084 else
1a2fb1c0 1085 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1086 break;
1087 case 0x01c00018: /* MXCC stream data register 3 */
1088 if (size == 8)
1a2fb1c0 1089 env->mxccdata[3] = val;
952a328f 1090 else
1a2fb1c0 1091 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1092 break;
1093 case 0x01c00100: /* MXCC stream source */
1094 if (size == 8)
1a2fb1c0 1095 env->mxccregs[0] = val;
952a328f 1096 else
1a2fb1c0 1097 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1098 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0);
1099 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8);
1100 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16);
1101 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 24);
1102 break;
1103 case 0x01c00200: /* MXCC stream destination */
1104 if (size == 8)
1a2fb1c0 1105 env->mxccregs[1] = val;
952a328f 1106 else
1a2fb1c0 1107 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1108 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]);
1109 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]);
1110 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]);
1111 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, env->mxccdata[3]);
1112 break;
1113 case 0x01c00a00: /* MXCC control register */
1114 if (size == 8)
1a2fb1c0 1115 env->mxccregs[3] = val;
952a328f 1116 else
1a2fb1c0 1117 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1118 break;
1119 case 0x01c00a04: /* MXCC control register */
1120 if (size == 4)
1a2fb1c0 1121 env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) | val;
952a328f 1122 else
1a2fb1c0 1123 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1124 break;
1125 case 0x01c00e00: /* MXCC error register */
bbf7d96b 1126 // writing a 1 bit clears the error
952a328f 1127 if (size == 8)
1a2fb1c0 1128 env->mxccregs[6] &= ~val;
952a328f 1129 else
1a2fb1c0 1130 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1131 break;
1132 case 0x01c00f00: /* MBus port address register */
1133 if (size == 8)
1a2fb1c0 1134 env->mxccregs[7] = val;
952a328f 1135 else
1a2fb1c0 1136 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1137 break;
1138 default:
1a2fb1c0 1139 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
952a328f
BS		 1140 break;
1141 }
1a2fb1c0 1142 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi, size, addr, val);
952a328f
BS		 1143#ifdef DEBUG_MXCC
1144 dump_mxcc(env);
1145#endif
6c36d3fa 1146 break;
e8af50a3 1147 case 3: /* MMU flush */
0f8a249a
BS		 1148 {
1149 int mmulev;
e80cfcfc 1150
1a2fb1c0 1151 mmulev = (addr >> 8) & 15;
952a328f 1152 DPRINTF_MMU("mmu flush level %d\n", mmulev);
0f8a249a
BS		 1153 switch (mmulev) {
1154 case 0: // flush page
1a2fb1c0 1155 tlb_flush_page(env, addr & 0xfffff000);
0f8a249a
BS		 1156 break;
1157 case 1: // flush segment (256k)
1158 case 2: // flush region (16M)
1159 case 3: // flush context (4G)
1160 case 4: // flush entire
1161 tlb_flush(env, 1);
1162 break;
1163 default:
1164 break;
1165 }
55754d9e 1166#ifdef DEBUG_MMU
0f8a249a 1167 dump_mmu(env);
55754d9e 1168#endif
0f8a249a 1169 }
8543e2cf 1170 break;
e8af50a3 1171 case 4: /* write MMU regs */
0f8a249a 1172 {
1a2fb1c0 1173 int reg = (addr >> 8) & 0x1f;
0f8a249a 1174 uint32_t oldreg;
3b46e624 1175
0f8a249a 1176 oldreg = env->mmuregs[reg];
55754d9e 1177 switch(reg) {
3deaeab7 1178 case 0: // Control Register
3dd9a152 1179 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
1a2fb1c0 1180 (val & 0x00ffffff);
0f8a249a
BS		 1181 // Mappings generated during no-fault mode or MMU
1182 // disabled mode are invalid in normal mode
3dd9a152
BS		 1183 if ((oldreg & (MMU_E | MMU_NF | env->mmu_bm)) !=
1184 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->mmu_bm)))
55754d9e
FB		 1185 tlb_flush(env, 1);
1186 break;
3deaeab7 1187 case 1: // Context Table Pointer Register
1a2fb1c0 1188 env->mmuregs[reg] = val & env->mmu_ctpr_mask;
3deaeab7
BS		 1189 break;
1190 case 2: // Context Register
1a2fb1c0 1191 env->mmuregs[reg] = val & env->mmu_cxr_mask;
55754d9e
FB		 1192 if (oldreg != env->mmuregs[reg]) {
1193 /* we flush when the MMU context changes because
1194 QEMU has no MMU context support */
1195 tlb_flush(env, 1);
1196 }
1197 break;
3deaeab7
BS		 1198 case 3: // Synchronous Fault Status Register with Clear
1199 case 4: // Synchronous Fault Address Register
1200 break;
1201 case 0x10: // TLB Replacement Control Register
1a2fb1c0 1202 env->mmuregs[reg] = val & env->mmu_trcr_mask;
55754d9e 1203 break;
3deaeab7 1204 case 0x13: // Synchronous Fault Status Register with Read and Clear
1a2fb1c0 1205 env->mmuregs[3] = val & env->mmu_sfsr_mask;
3dd9a152 1206 break;
3deaeab7 1207 case 0x14: // Synchronous Fault Address Register
1a2fb1c0 1208 env->mmuregs[4] = val;
3dd9a152 1209 break;
55754d9e 1210 default:
1a2fb1c0 1211 env->mmuregs[reg] = val;
55754d9e
FB		 1212 break;
1213 }
55754d9e 1214 if (oldreg != env->mmuregs[reg]) {
952a328f 1215 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
55754d9e 1216 }
952a328f 1217#ifdef DEBUG_MMU
0f8a249a 1218 dump_mmu(env);
55754d9e 1219#endif
0f8a249a 1220 }
8543e2cf 1221 break;
045380be
BS		 1222 case 5: // Turbosparc ITLB Diagnostic
1223 case 6: // Turbosparc DTLB Diagnostic
1224 case 7: // Turbosparc IOTLB Diagnostic
1225 break;
81ad8ba2
BS		 1226 case 0xa: /* User data access */
1227 switch(size) {
1228 case 1:
1a2fb1c0 1229 stb_user(addr, val);
81ad8ba2
BS		 1230 break;
1231 case 2:
1a2fb1c0 1232 stw_user(addr & ~1, val);
81ad8ba2
BS		 1233 break;
1234 default:
1235 case 4:
1a2fb1c0 1236 stl_user(addr & ~3, val);
81ad8ba2
BS		 1237 break;
1238 case 8:
1a2fb1c0 1239 stq_user(addr & ~7, val);
81ad8ba2
BS		 1240 break;
1241 }
1242 break;
1243 case 0xb: /* Supervisor data access */
1244 switch(size) {
1245 case 1:
1a2fb1c0 1246 stb_kernel(addr, val);
81ad8ba2
BS		 1247 break;
1248 case 2:
1a2fb1c0 1249 stw_kernel(addr & ~1, val);
81ad8ba2
BS		 1250 break;
1251 default:
1252 case 4:
1a2fb1c0 1253 stl_kernel(addr & ~3, val);
81ad8ba2
BS		 1254 break;
1255 case 8:
1a2fb1c0 1256 stq_kernel(addr & ~7, val);
81ad8ba2
BS		 1257 break;
1258 }
1259 break;
6c36d3fa
BS		 1260 case 0xc: /* I-cache tag */
1261 case 0xd: /* I-cache data */
1262 case 0xe: /* D-cache tag */
1263 case 0xf: /* D-cache data */
1264 case 0x10: /* I/D-cache flush page */
1265 case 0x11: /* I/D-cache flush segment */
1266 case 0x12: /* I/D-cache flush region */
1267 case 0x13: /* I/D-cache flush context */
1268 case 0x14: /* I/D-cache flush user */
1269 break;
e80cfcfc 1270 case 0x17: /* Block copy, sta access */
0f8a249a 1271 {
1a2fb1c0
BS		 1272 // val = src
1273 // addr = dst
0f8a249a 1274 // copy 32 bytes
6c36d3fa 1275 unsigned int i;
1a2fb1c0 1276 uint32_t src = val & ~3, dst = addr & ~3, temp;
3b46e624 1277
6c36d3fa
BS		 1278 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
1279 temp = ldl_kernel(src);
1280 stl_kernel(dst, temp);
1281 }
0f8a249a 1282 }
8543e2cf 1283 break;
e80cfcfc 1284 case 0x1f: /* Block fill, stda access */
0f8a249a 1285 {
1a2fb1c0
BS		 1286 // addr = dst
1287 // fill 32 bytes with val
6c36d3fa 1288 unsigned int i;
1a2fb1c0 1289 uint32_t dst = addr & 7;
6c36d3fa
BS		 1290
1291 for (i = 0; i < 32; i += 8, dst += 8)
1292 stq_kernel(dst, val);
0f8a249a 1293 }
8543e2cf 1294 break;
6c36d3fa 1295 case 0x20: /* MMU passthrough */
0f8a249a 1296 {
02aab46a
FB		 1297 switch(size) {
1298 case 1:
1a2fb1c0 1299 stb_phys(addr, val);
02aab46a
FB		 1300 break;
1301 case 2:
1a2fb1c0 1302 stw_phys(addr & ~1, val);
02aab46a
FB		 1303 break;
1304 case 4:
1305 default:
1a2fb1c0 1306 stl_phys(addr & ~3, val);
02aab46a 1307 break;
9e61bde5 1308 case 8:
1a2fb1c0 1309 stq_phys(addr & ~7, val);
9e61bde5 1310 break;
02aab46a 1311 }
0f8a249a 1312 }
8543e2cf 1313 break;
045380be 1314 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
0f8a249a 1315 {
5dcb6b91
BS		 1316 switch(size) {
1317 case 1:
1a2fb1c0
BS		 1318 stb_phys((target_phys_addr_t)addr
1319 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1320 break;
1321 case 2:
1a2fb1c0
BS		 1322 stw_phys((target_phys_addr_t)(addr & ~1)
1323 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1324 break;
1325 case 4:
1326 default:
1a2fb1c0
BS		 1327 stl_phys((target_phys_addr_t)(addr & ~3)
1328 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1329 break;
1330 case 8:
1a2fb1c0
BS		 1331 stq_phys((target_phys_addr_t)(addr & ~7)
1332 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1333 break;
1334 }
0f8a249a 1335 }
8543e2cf 1336 break;
045380be
BS		 1337 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
1338 case 0x31: // store buffer data, Ross RT620 I-cache flush or
1339 // Turbosparc snoop RAM
1340 case 0x32: // store buffer control or Turbosparc page table descriptor diagnostic
6c36d3fa
BS		 1341 case 0x36: /* I-cache flash clear */
1342 case 0x37: /* D-cache flash clear */
666c87aa
BS		 1343 case 0x38: /* breakpoint diagnostics */
1344 case 0x4c: /* breakpoint action */
6c36d3fa 1345 break;
045380be 1346 case 8: /* User code access, XXX */
6c36d3fa 1347 case 9: /* Supervisor code access, XXX */
e8af50a3 1348 default:
1a2fb1c0 1349 do_unassigned_access(addr, 1, 0, asi);
8543e2cf 1350 break;
e8af50a3 1351 }
8543e2cf 1352#ifdef DEBUG_ASI
1a2fb1c0 1353 dump_asi("write", addr, asi, size, val);
8543e2cf 1354#endif
e8af50a3
FB		 1355}
1356
81ad8ba2
BS		 1357#endif /* CONFIG_USER_ONLY */
1358#else /* TARGET_SPARC64 */
1359
1360#ifdef CONFIG_USER_ONLY
1a2fb1c0 1361uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
81ad8ba2
BS		 1362{
1363 uint64_t ret = 0;
1a2fb1c0
BS		 1364#if defined(DEBUG_ASI)
1365 target_ulong last_addr = addr;
1366#endif
81ad8ba2
BS		 1367
1368 if (asi < 0x80)
1369 raise_exception(TT_PRIV_ACT);
1370
1371 switch (asi) {
1372 case 0x80: // Primary
1373 case 0x82: // Primary no-fault
1374 case 0x88: // Primary LE
1375 case 0x8a: // Primary no-fault LE
1376 {
1377 switch(size) {
1378 case 1:
1a2fb1c0 1379 ret = ldub_raw(addr);
81ad8ba2
BS		 1380 break;
1381 case 2:
1a2fb1c0 1382 ret = lduw_raw(addr & ~1);
81ad8ba2
BS		 1383 break;
1384 case 4:
1a2fb1c0 1385 ret = ldl_raw(addr & ~3);
81ad8ba2
BS		 1386 break;
1387 default:
1388 case 8:
1a2fb1c0 1389 ret = ldq_raw(addr & ~7);
81ad8ba2
BS		 1390 break;
1391 }
1392 }
1393 break;
1394 case 0x81: // Secondary
1395 case 0x83: // Secondary no-fault
1396 case 0x89: // Secondary LE
1397 case 0x8b: // Secondary no-fault LE
1398 // XXX
1399 break;
1400 default:
1401 break;
1402 }
1403
1404 /* Convert from little endian */
1405 switch (asi) {
1406 case 0x88: // Primary LE
1407 case 0x89: // Secondary LE
1408 case 0x8a: // Primary no-fault LE
1409 case 0x8b: // Secondary no-fault LE
1410 switch(size) {
1411 case 2:
1412 ret = bswap16(ret);
e32664fb 1413 break;
81ad8ba2
BS		 1414 case 4:
1415 ret = bswap32(ret);
e32664fb 1416 break;
81ad8ba2
BS		 1417 case 8:
1418 ret = bswap64(ret);
e32664fb 1419 break;
81ad8ba2
BS		 1420 default:
1421 break;
1422 }
1423 default:
1424 break;
1425 }
1426
1427 /* Convert to signed number */
1428 if (sign) {
1429 switch(size) {
1430 case 1:
1431 ret = (int8_t) ret;
e32664fb 1432 break;
81ad8ba2
BS		 1433 case 2:
1434 ret = (int16_t) ret;
e32664fb 1435 break;
81ad8ba2
BS		 1436 case 4:
1437 ret = (int32_t) ret;
e32664fb 1438 break;
81ad8ba2
BS		 1439 default:
1440 break;
1441 }
1442 }
1a2fb1c0
BS		 1443#ifdef DEBUG_ASI
1444 dump_asi("read ", last_addr, asi, size, ret);
1445#endif
1446 return ret;
81ad8ba2
BS		 1447}
1448
1a2fb1c0 1449void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
81ad8ba2 1450{
1a2fb1c0
BS		 1451#ifdef DEBUG_ASI
1452 dump_asi("write", addr, asi, size, val);
1453#endif
81ad8ba2
BS		 1454 if (asi < 0x80)
1455 raise_exception(TT_PRIV_ACT);
1456
1457 /* Convert to little endian */
1458 switch (asi) {
1459 case 0x88: // Primary LE
1460 case 0x89: // Secondary LE
1461 switch(size) {
1462 case 2:
1a2fb1c0 1463 addr = bswap16(addr);
e32664fb 1464 break;
81ad8ba2 1465 case 4:
1a2fb1c0 1466 addr = bswap32(addr);
e32664fb 1467 break;
81ad8ba2 1468 case 8:
1a2fb1c0 1469 addr = bswap64(addr);
e32664fb 1470 break;
81ad8ba2
BS		 1471 default:
1472 break;
1473 }
1474 default:
1475 break;
1476 }
1477
1478 switch(asi) {
1479 case 0x80: // Primary
1480 case 0x88: // Primary LE
1481 {
1482 switch(size) {
1483 case 1:
1a2fb1c0 1484 stb_raw(addr, val);
81ad8ba2
BS		 1485 break;
1486 case 2:
1a2fb1c0 1487 stw_raw(addr & ~1, val);
81ad8ba2
BS		 1488 break;
1489 case 4:
1a2fb1c0 1490 stl_raw(addr & ~3, val);
81ad8ba2
BS		 1491 break;
1492 case 8:
1493 default:
1a2fb1c0 1494 stq_raw(addr & ~7, val);
81ad8ba2
BS		 1495 break;
1496 }
1497 }
1498 break;
1499 case 0x81: // Secondary
1500 case 0x89: // Secondary LE
1501 // XXX
1502 return;
1503
1504 case 0x82: // Primary no-fault, RO
1505 case 0x83: // Secondary no-fault, RO
1506 case 0x8a: // Primary no-fault LE, RO
1507 case 0x8b: // Secondary no-fault LE, RO
1508 default:
1a2fb1c0 1509 do_unassigned_access(addr, 1, 0, 1);
81ad8ba2
BS		 1510 return;
1511 }
1512}
1513
1514#else /* CONFIG_USER_ONLY */
3475187d 1515
1a2fb1c0 1516uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
3475187d 1517{
83469015 1518 uint64_t ret = 0;
1a2fb1c0
BS		 1519#if defined(DEBUG_ASI)
1520 target_ulong last_addr = addr;
1521#endif
3475187d 1522
6f27aba6 1523 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
20b749f6 1524 || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
0f8a249a 1525 raise_exception(TT_PRIV_ACT);
3475187d
FB		 1526
1527 switch (asi) {
81ad8ba2
BS		 1528 case 0x10: // As if user primary
1529 case 0x18: // As if user primary LE
1530 case 0x80: // Primary
1531 case 0x82: // Primary no-fault
1532 case 0x88: // Primary LE
1533 case 0x8a: // Primary no-fault LE
1534 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
6f27aba6
BS		 1535 if (env->hpstate & HS_PRIV) {
1536 switch(size) {
1537 case 1:
1a2fb1c0 1538 ret = ldub_hypv(addr);
6f27aba6
BS		 1539 break;
1540 case 2:
1a2fb1c0 1541 ret = lduw_hypv(addr & ~1);
6f27aba6
BS		 1542 break;
1543 case 4:
1a2fb1c0 1544 ret = ldl_hypv(addr & ~3);
6f27aba6
BS		 1545 break;
1546 default:
1547 case 8:
1a2fb1c0 1548 ret = ldq_hypv(addr & ~7);
6f27aba6
BS		 1549 break;
1550 }
1551 } else {
1552 switch(size) {
1553 case 1:
1a2fb1c0 1554 ret = ldub_kernel(addr);
6f27aba6
BS		 1555 break;
1556 case 2:
1a2fb1c0 1557 ret = lduw_kernel(addr & ~1);
6f27aba6
BS		 1558 break;
1559 case 4:
1a2fb1c0 1560 ret = ldl_kernel(addr & ~3);
6f27aba6
BS		 1561 break;
1562 default:
1563 case 8:
1a2fb1c0 1564 ret = ldq_kernel(addr & ~7);
6f27aba6
BS		 1565 break;
1566 }
81ad8ba2
BS		 1567 }
1568 } else {
1569 switch(size) {
1570 case 1:
1a2fb1c0 1571 ret = ldub_user(addr);
81ad8ba2
BS		 1572 break;
1573 case 2:
1a2fb1c0 1574 ret = lduw_user(addr & ~1);
81ad8ba2
BS		 1575 break;
1576 case 4:
1a2fb1c0 1577 ret = ldl_user(addr & ~3);
81ad8ba2
BS		 1578 break;
1579 default:
1580 case 8:
1a2fb1c0 1581 ret = ldq_user(addr & ~7);
81ad8ba2
BS		 1582 break;
1583 }
1584 }
1585 break;
3475187d
FB		 1586 case 0x14: // Bypass
1587 case 0x15: // Bypass, non-cacheable
81ad8ba2
BS		 1588 case 0x1c: // Bypass LE
1589 case 0x1d: // Bypass, non-cacheable LE
0f8a249a 1590 {
02aab46a
FB		 1591 switch(size) {
1592 case 1:
1a2fb1c0 1593 ret = ldub_phys(addr);
02aab46a
FB		 1594 break;
1595 case 2:
1a2fb1c0 1596 ret = lduw_phys(addr & ~1);
02aab46a
FB		 1597 break;
1598 case 4:
1a2fb1c0 1599 ret = ldl_phys(addr & ~3);
02aab46a
FB		 1600 break;
1601 default:
1602 case 8:
1a2fb1c0 1603 ret = ldq_phys(addr & ~7);
02aab46a
FB		 1604 break;
1605 }
0f8a249a
BS		 1606 break;
1607 }
83469015
FB		 1608 case 0x04: // Nucleus
1609 case 0x0c: // Nucleus Little Endian (LE)
83469015 1610 case 0x11: // As if user secondary
83469015 1611 case 0x19: // As if user secondary LE
83469015
FB		 1612 case 0x24: // Nucleus quad LDD 128 bit atomic
1613 case 0x2c: // Nucleus quad LDD 128 bit atomic
1614 case 0x4a: // UPA config
81ad8ba2 1615 case 0x81: // Secondary
83469015 1616 case 0x83: // Secondary no-fault
83469015 1617 case 0x89: // Secondary LE
83469015 1618 case 0x8b: // Secondary no-fault LE
0f8a249a
BS		 1619 // XXX
1620 break;
3475187d 1621 case 0x45: // LSU
0f8a249a
BS		 1622 ret = env->lsu;
1623 break;
3475187d 1624 case 0x50: // I-MMU regs
0f8a249a 1625 {
1a2fb1c0 1626 int reg = (addr >> 3) & 0xf;
3475187d 1627
0f8a249a
BS		 1628 ret = env->immuregs[reg];
1629 break;
1630 }
3475187d
FB		 1631 case 0x51: // I-MMU 8k TSB pointer
1632 case 0x52: // I-MMU 64k TSB pointer
1633 case 0x55: // I-MMU data access
0f8a249a
BS		 1634 // XXX
1635 break;
83469015 1636 case 0x56: // I-MMU tag read
0f8a249a
BS		 1637 {
1638 unsigned int i;
1639
1640 for (i = 0; i < 64; i++) {
1641 // Valid, ctx match, vaddr match
1642 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
1a2fb1c0 1643 env->itlb_tag[i] == addr) {
0f8a249a
BS		 1644 ret = env->itlb_tag[i];
1645 break;
1646 }
1647 }
1648 break;
1649 }
3475187d 1650 case 0x58: // D-MMU regs
0f8a249a 1651 {
1a2fb1c0 1652 int reg = (addr >> 3) & 0xf;
3475187d 1653
0f8a249a
BS		 1654 ret = env->dmmuregs[reg];
1655 break;
1656 }
83469015 1657 case 0x5e: // D-MMU tag read
0f8a249a
BS		 1658 {
1659 unsigned int i;
1660
1661 for (i = 0; i < 64; i++) {
1662 // Valid, ctx match, vaddr match
1663 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
1a2fb1c0 1664 env->dtlb_tag[i] == addr) {
0f8a249a
BS		 1665 ret = env->dtlb_tag[i];
1666 break;
1667 }
1668 }
1669 break;
1670 }
3475187d
FB		 1671 case 0x59: // D-MMU 8k TSB pointer
1672 case 0x5a: // D-MMU 64k TSB pointer
1673 case 0x5b: // D-MMU data pointer
1674 case 0x5d: // D-MMU data access
83469015
FB		 1675 case 0x48: // Interrupt dispatch, RO
1676 case 0x49: // Interrupt data receive
1677 case 0x7f: // Incoming interrupt vector, RO
0f8a249a
BS		 1678 // XXX
1679 break;
3475187d
FB		 1680 case 0x54: // I-MMU data in, WO
1681 case 0x57: // I-MMU demap, WO
1682 case 0x5c: // D-MMU data in, WO
1683 case 0x5f: // D-MMU demap, WO
83469015 1684 case 0x77: // Interrupt vector, WO
3475187d 1685 default:
1a2fb1c0 1686 do_unassigned_access(addr, 0, 0, 1);
0f8a249a
BS		 1687 ret = 0;
1688 break;
3475187d 1689 }
81ad8ba2
BS		 1690
1691 /* Convert from little endian */
1692 switch (asi) {
1693 case 0x0c: // Nucleus Little Endian (LE)
1694 case 0x18: // As if user primary LE
1695 case 0x19: // As if user secondary LE
1696 case 0x1c: // Bypass LE
1697 case 0x1d: // Bypass, non-cacheable LE
1698 case 0x88: // Primary LE
1699 case 0x89: // Secondary LE
1700 case 0x8a: // Primary no-fault LE
1701 case 0x8b: // Secondary no-fault LE
1702 switch(size) {
1703 case 2:
1704 ret = bswap16(ret);
e32664fb 1705 break;
81ad8ba2
BS		 1706 case 4:
1707 ret = bswap32(ret);
e32664fb 1708 break;
81ad8ba2
BS		 1709 case 8:
1710 ret = bswap64(ret);
e32664fb 1711 break;
81ad8ba2
BS		 1712 default:
1713 break;
1714 }
1715 default:
1716 break;
1717 }
1718
1719 /* Convert to signed number */
1720 if (sign) {
1721 switch(size) {
1722 case 1:
1723 ret = (int8_t) ret;
e32664fb 1724 break;
81ad8ba2
BS		 1725 case 2:
1726 ret = (int16_t) ret;
e32664fb 1727 break;
81ad8ba2
BS		 1728 case 4:
1729 ret = (int32_t) ret;
e32664fb 1730 break;
81ad8ba2
BS		 1731 default:
1732 break;
1733 }
1734 }
1a2fb1c0
BS		 1735#ifdef DEBUG_ASI
1736 dump_asi("read ", last_addr, asi, size, ret);
1737#endif
1738 return ret;
3475187d
FB		 1739}
1740
1a2fb1c0 1741void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
3475187d 1742{
1a2fb1c0
BS		 1743#ifdef DEBUG_ASI
1744 dump_asi("write", addr, asi, size, val);
1745#endif
6f27aba6 1746 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
20b749f6 1747 || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
0f8a249a 1748 raise_exception(TT_PRIV_ACT);
3475187d 1749
81ad8ba2
BS		 1750 /* Convert to little endian */
1751 switch (asi) {
1752 case 0x0c: // Nucleus Little Endian (LE)
1753 case 0x18: // As if user primary LE
1754 case 0x19: // As if user secondary LE
1755 case 0x1c: // Bypass LE
1756 case 0x1d: // Bypass, non-cacheable LE
81ad8ba2
BS		 1757 case 0x88: // Primary LE
1758 case 0x89: // Secondary LE
1759 switch(size) {
1760 case 2:
1a2fb1c0 1761 addr = bswap16(addr);
e32664fb 1762 break;
81ad8ba2 1763 case 4:
1a2fb1c0 1764 addr = bswap32(addr);
e32664fb 1765 break;
81ad8ba2 1766 case 8:
1a2fb1c0 1767 addr = bswap64(addr);
e32664fb 1768 break;
81ad8ba2
BS		 1769 default:
1770 break;
1771 }
1772 default:
1773 break;
1774 }
1775
3475187d 1776 switch(asi) {
81ad8ba2
BS		 1777 case 0x10: // As if user primary
1778 case 0x18: // As if user primary LE
1779 case 0x80: // Primary
1780 case 0x88: // Primary LE
1781 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
6f27aba6
BS		 1782 if (env->hpstate & HS_PRIV) {
1783 switch(size) {
1784 case 1:
1a2fb1c0 1785 stb_hypv(addr, val);
6f27aba6
BS		 1786 break;
1787 case 2:
1a2fb1c0 1788 stw_hypv(addr & ~1, val);
6f27aba6
BS		 1789 break;
1790 case 4:
1a2fb1c0 1791 stl_hypv(addr & ~3, val);
6f27aba6
BS		 1792 break;
1793 case 8:
1794 default:
1a2fb1c0 1795 stq_hypv(addr & ~7, val);
6f27aba6
BS		 1796 break;
1797 }
1798 } else {
1799 switch(size) {
1800 case 1:
1a2fb1c0 1801 stb_kernel(addr, val);
6f27aba6
BS		 1802 break;
1803 case 2:
1a2fb1c0 1804 stw_kernel(addr & ~1, val);
6f27aba6
BS		 1805 break;
1806 case 4:
1a2fb1c0 1807 stl_kernel(addr & ~3, val);
6f27aba6
BS		 1808 break;
1809 case 8:
1810 default:
1a2fb1c0 1811 stq_kernel(addr & ~7, val);
6f27aba6
BS		 1812 break;
1813 }
81ad8ba2
BS		 1814 }
1815 } else {
1816 switch(size) {
1817 case 1:
1a2fb1c0 1818 stb_user(addr, val);
81ad8ba2
BS		 1819 break;
1820 case 2:
1a2fb1c0 1821 stw_user(addr & ~1, val);
81ad8ba2
BS		 1822 break;
1823 case 4:
1a2fb1c0 1824 stl_user(addr & ~3, val);
81ad8ba2
BS		 1825 break;
1826 case 8:
1827 default:
1a2fb1c0 1828 stq_user(addr & ~7, val);
81ad8ba2
BS		 1829 break;
1830 }
1831 }
1832 break;
3475187d
FB		 1833 case 0x14: // Bypass
1834 case 0x15: // Bypass, non-cacheable
81ad8ba2
BS		 1835 case 0x1c: // Bypass LE
1836 case 0x1d: // Bypass, non-cacheable LE
0f8a249a 1837 {
02aab46a
FB		 1838 switch(size) {
1839 case 1:
1a2fb1c0 1840 stb_phys(addr, val);
02aab46a
FB		 1841 break;
1842 case 2:
1a2fb1c0 1843 stw_phys(addr & ~1, val);
02aab46a
FB		 1844 break;
1845 case 4:
1a2fb1c0 1846 stl_phys(addr & ~3, val);
02aab46a
FB		 1847 break;
1848 case 8:
1849 default:
1a2fb1c0 1850 stq_phys(addr & ~7, val);
02aab46a
FB		 1851 break;
1852 }
0f8a249a
BS		 1853 }
1854 return;
83469015
FB		 1855 case 0x04: // Nucleus
1856 case 0x0c: // Nucleus Little Endian (LE)
83469015 1857 case 0x11: // As if user secondary
83469015 1858 case 0x19: // As if user secondary LE
83469015
FB		 1859 case 0x24: // Nucleus quad LDD 128 bit atomic
1860 case 0x2c: // Nucleus quad LDD 128 bit atomic
1861 case 0x4a: // UPA config
51996525 1862 case 0x81: // Secondary
83469015 1863 case 0x89: // Secondary LE
0f8a249a
BS		 1864 // XXX
1865 return;
3475187d 1866 case 0x45: // LSU
0f8a249a
BS		 1867 {
1868 uint64_t oldreg;
1869
1870 oldreg = env->lsu;
1a2fb1c0 1871 env->lsu = val & (DMMU_E | IMMU_E);
0f8a249a
BS		 1872 // Mappings generated during D/I MMU disabled mode are
1873 // invalid in normal mode
1874 if (oldreg != env->lsu) {
952a328f 1875 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu);
83469015 1876#ifdef DEBUG_MMU
0f8a249a 1877 dump_mmu(env);
83469015 1878#endif
0f8a249a
BS		 1879 tlb_flush(env, 1);
1880 }
1881 return;
1882 }
3475187d 1883 case 0x50: // I-MMU regs
0f8a249a 1884 {
1a2fb1c0 1885 int reg = (addr >> 3) & 0xf;
0f8a249a 1886 uint64_t oldreg;
3b46e624 1887
0f8a249a 1888 oldreg = env->immuregs[reg];
3475187d
FB		 1889 switch(reg) {
1890 case 0: // RO
1891 case 4:
1892 return;
1893 case 1: // Not in I-MMU
1894 case 2:
1895 case 7:
1896 case 8:
1897 return;
1898 case 3: // SFSR
1a2fb1c0
BS		 1899 if ((val & 1) == 0)
1900 val = 0; // Clear SFSR
3475187d
FB		 1901 break;
1902 case 5: // TSB access
1903 case 6: // Tag access
1904 default:
1905 break;
1906 }
1a2fb1c0 1907 env->immuregs[reg] = val;
3475187d 1908 if (oldreg != env->immuregs[reg]) {
952a328f 1909 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
3475187d 1910 }
952a328f 1911#ifdef DEBUG_MMU
0f8a249a 1912 dump_mmu(env);
3475187d 1913#endif
0f8a249a
BS		 1914 return;
1915 }
3475187d 1916 case 0x54: // I-MMU data in
0f8a249a
BS		 1917 {
1918 unsigned int i;
1919
1920 // Try finding an invalid entry
1921 for (i = 0; i < 64; i++) {
1922 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
1923 env->itlb_tag[i] = env->immuregs[6];
1a2fb1c0 1924 env->itlb_tte[i] = val;
0f8a249a
BS		 1925 return;
1926 }
1927 }
1928 // Try finding an unlocked entry
1929 for (i = 0; i < 64; i++) {
1930 if ((env->itlb_tte[i] & 0x40) == 0) {
1931 env->itlb_tag[i] = env->immuregs[6];
1a2fb1c0 1932 env->itlb_tte[i] = val;
0f8a249a
BS		 1933 return;
1934 }
1935 }
1936 // error state?
1937 return;
1938 }
3475187d 1939 case 0x55: // I-MMU data access
0f8a249a 1940 {
1a2fb1c0 1941 unsigned int i = (addr >> 3) & 0x3f;
3475187d 1942
0f8a249a 1943 env->itlb_tag[i] = env->immuregs[6];
1a2fb1c0 1944 env->itlb_tte[i] = val;
0f8a249a
BS		 1945 return;
1946 }
3475187d 1947 case 0x57: // I-MMU demap
0f8a249a
BS		 1948 // XXX
1949 return;
3475187d 1950 case 0x58: // D-MMU regs
0f8a249a 1951 {
1a2fb1c0 1952 int reg = (addr >> 3) & 0xf;
0f8a249a 1953 uint64_t oldreg;
3b46e624 1954
0f8a249a 1955 oldreg = env->dmmuregs[reg];
3475187d
FB		 1956 switch(reg) {
1957 case 0: // RO
1958 case 4:
1959 return;
1960 case 3: // SFSR
1a2fb1c0
BS		 1961 if ((val & 1) == 0) {
1962 val = 0; // Clear SFSR, Fault address
0f8a249a
BS		 1963 env->dmmuregs[4] = 0;
1964 }
1a2fb1c0 1965 env->dmmuregs[reg] = val;
3475187d
FB		 1966 break;
1967 case 1: // Primary context
1968 case 2: // Secondary context
1969 case 5: // TSB access
1970 case 6: // Tag access
1971 case 7: // Virtual Watchpoint
1972 case 8: // Physical Watchpoint
1973 default:
1974 break;
1975 }
1a2fb1c0 1976 env->dmmuregs[reg] = val;
3475187d 1977 if (oldreg != env->dmmuregs[reg]) {
952a328f 1978 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
3475187d 1979 }
952a328f 1980#ifdef DEBUG_MMU
0f8a249a 1981 dump_mmu(env);
3475187d 1982#endif
0f8a249a
BS		 1983 return;
1984 }
3475187d 1985 case 0x5c: // D-MMU data in
0f8a249a
BS		 1986 {
1987 unsigned int i;
1988
1989 // Try finding an invalid entry
1990 for (i = 0; i < 64; i++) {
1991 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
1992 env->dtlb_tag[i] = env->dmmuregs[6];
1a2fb1c0 1993 env->dtlb_tte[i] = val;
0f8a249a
BS		 1994 return;
1995 }
1996 }
1997 // Try finding an unlocked entry
1998 for (i = 0; i < 64; i++) {
1999 if ((env->dtlb_tte[i] & 0x40) == 0) {
2000 env->dtlb_tag[i] = env->dmmuregs[6];
1a2fb1c0 2001 env->dtlb_tte[i] = val;
0f8a249a
BS		 2002 return;
2003 }
2004 }
2005 // error state?
2006 return;
2007 }
3475187d 2008 case 0x5d: // D-MMU data access
0f8a249a 2009 {
1a2fb1c0 2010 unsigned int i = (addr >> 3) & 0x3f;
3475187d 2011
0f8a249a 2012 env->dtlb_tag[i] = env->dmmuregs[6];
1a2fb1c0 2013 env->dtlb_tte[i] = val;
0f8a249a
BS		 2014 return;
2015 }
3475187d 2016 case 0x5f: // D-MMU demap
83469015 2017 case 0x49: // Interrupt data receive
0f8a249a
BS		 2018 // XXX
2019 return;
3475187d
FB		 2020 case 0x51: // I-MMU 8k TSB pointer, RO
2021 case 0x52: // I-MMU 64k TSB pointer, RO
2022 case 0x56: // I-MMU tag read, RO
2023 case 0x59: // D-MMU 8k TSB pointer, RO
2024 case 0x5a: // D-MMU 64k TSB pointer, RO
2025 case 0x5b: // D-MMU data pointer, RO
2026 case 0x5e: // D-MMU tag read, RO
83469015
FB		 2027 case 0x48: // Interrupt dispatch, RO
2028 case 0x7f: // Incoming interrupt vector, RO
2029 case 0x82: // Primary no-fault, RO
2030 case 0x83: // Secondary no-fault, RO
2031 case 0x8a: // Primary no-fault LE, RO
2032 case 0x8b: // Secondary no-fault LE, RO
3475187d 2033 default:
1a2fb1c0 2034 do_unassigned_access(addr, 1, 0, 1);
0f8a249a 2035 return;
3475187d
FB		 2036 }
2037}
81ad8ba2 2038#endif /* CONFIG_USER_ONLY */
3391c818 2039
1a2fb1c0 2040void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
3391c818 2041{
3391c818 2042 unsigned int i;
1a2fb1c0 2043 target_ulong val;
3391c818
BS		 2044
2045 switch (asi) {
2046 case 0xf0: // Block load primary
2047 case 0xf1: // Block load secondary
2048 case 0xf8: // Block load primary LE
2049 case 0xf9: // Block load secondary LE
51996525
BS		 2050 if (rd & 7) {
2051 raise_exception(TT_ILL_INSN);
2052 return;
2053 }
1a2fb1c0 2054 if (addr & 0x3f) {
51996525
BS		 2055 raise_exception(TT_UNALIGNED);
2056 return;
2057 }
2058 for (i = 0; i < 16; i++) {
1a2fb1c0
BS		 2059 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4, 0);
2060 addr += 4;
3391c818 2061 }
3391c818
BS		 2062
2063 return;
2064 default:
2065 break;
2066 }
2067
1a2fb1c0 2068 val = helper_ld_asi(addr, asi, size, 0);
3391c818
BS		 2069 switch(size) {
2070 default:
2071 case 4:
1a2fb1c0 2072 *((uint32_t *)&FT0) = val;
3391c818
BS		 2073 break;
2074 case 8:
1a2fb1c0 2075 *((int64_t *)&DT0) = val;
3391c818 2076 break;
1f587329
BS		 2077#if defined(CONFIG_USER_ONLY)
2078 case 16:
2079 // XXX
2080 break;
2081#endif
3391c818 2082 }
3391c818
BS		 2083}
2084
1a2fb1c0 2085void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
3391c818 2086{
3391c818 2087 unsigned int i;
1a2fb1c0 2088 target_ulong val = 0;
3391c818
BS		 2089
2090 switch (asi) {
2091 case 0xf0: // Block store primary
2092 case 0xf1: // Block store secondary
2093 case 0xf8: // Block store primary LE
2094 case 0xf9: // Block store secondary LE
51996525
BS		 2095 if (rd & 7) {
2096 raise_exception(TT_ILL_INSN);
2097 return;
2098 }
1a2fb1c0 2099 if (addr & 0x3f) {
51996525
BS		 2100 raise_exception(TT_UNALIGNED);
2101 return;
2102 }
2103 for (i = 0; i < 16; i++) {
1a2fb1c0
BS		 2104 val = *(uint32_t *)&env->fpr[rd++];
2105 helper_st_asi(addr, val, asi & 0x8f, 4);
2106 addr += 4;
3391c818 2107 }
3391c818
BS		 2108
2109 return;
2110 default:
2111 break;
2112 }
2113
2114 switch(size) {
2115 default:
2116 case 4:
1a2fb1c0 2117 val = *((uint32_t *)&FT0);
3391c818
BS		 2118 break;
2119 case 8:
1a2fb1c0 2120 val = *((int64_t *)&DT0);
3391c818 2121 break;
1f587329
BS		 2122#if defined(CONFIG_USER_ONLY)
2123 case 16:
2124 // XXX
2125 break;
2126#endif
3391c818 2127 }
1a2fb1c0
BS		 2128 helper_st_asi(addr, val, asi, size);
2129}
2130
2131target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
2132 target_ulong val2, uint32_t asi)
2133{
2134 target_ulong ret;
2135
2136 val1 &= 0xffffffffUL;
2137 ret = helper_ld_asi(addr, asi, 4, 0);
2138 ret &= 0xffffffffUL;
2139 if (val1 == ret)
2140 helper_st_asi(addr, val2 & 0xffffffffUL, asi, 4);
2141 return ret;
3391c818
BS		 2142}
2143
1a2fb1c0
BS		 2144target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
2145 target_ulong val2, uint32_t asi)
2146{
2147 target_ulong ret;
2148
2149 ret = helper_ld_asi(addr, asi, 8, 0);
2150 if (val1 == ret)
2151 helper_st_asi(addr, val2, asi, 8);
2152 return ret;
2153}
81ad8ba2 2154#endif /* TARGET_SPARC64 */
3475187d
FB		 2155
2156#ifndef TARGET_SPARC64
1a2fb1c0 2157void helper_rett(void)
e8af50a3 2158{
af7bf89b
FB		 2159 unsigned int cwp;
2160
d4218d99
BS		 2161 if (env->psret == 1)
2162 raise_exception(TT_ILL_INSN);
2163
e8af50a3 2164 env->psret = 1;
5fafdf24 2165 cwp = (env->cwp + 1) & (NWINDOWS - 1);
e8af50a3
FB		 2166 if (env->wim & (1 << cwp)) {
2167 raise_exception(TT_WIN_UNF);
2168 }
2169 set_cwp(cwp);
2170 env->psrs = env->psrps;
2171}
3475187d 2172#endif
e8af50a3 2173
3b89f26c
BS		 2174target_ulong helper_udiv(target_ulong a, target_ulong b)
2175{
2176 uint64_t x0;
2177 uint32_t x1;
2178
2179 x0 = a | ((uint64_t) (env->y) << 32);
2180 x1 = b;
2181
2182 if (x1 == 0) {
2183 raise_exception(TT_DIV_ZERO);
2184 }
2185
2186 x0 = x0 / x1;
2187 if (x0 > 0xffffffff) {
2188 env->cc_src2 = 1;
2189 return 0xffffffff;
2190 } else {
2191 env->cc_src2 = 0;
2192 return x0;
2193 }
2194}
2195
2196target_ulong helper_sdiv(target_ulong a, target_ulong b)
2197{
2198 int64_t x0;
2199 int32_t x1;
2200
2201 x0 = a | ((int64_t) (env->y) << 32);
2202 x1 = b;
2203
2204 if (x1 == 0) {
2205 raise_exception(TT_DIV_ZERO);
2206 }
2207
2208 x0 = x0 / x1;
2209 if ((int32_t) x0 != x0) {
2210 env->cc_src2 = 1;
2211 return x0 < 0? 0x80000000: 0x7fffffff;
2212 } else {
2213 env->cc_src2 = 0;
2214 return x0;
2215 }
2216}
2217
1a2fb1c0
BS		 2218uint64_t helper_pack64(target_ulong high, target_ulong low)
2219{
2220 return ((uint64_t)high << 32) | (uint64_t)(low & 0xffffffff);
2221}
2222
7fa76c0b
BS		 2223#ifdef TARGET_ABI32
2224#define ADDR(x) ((x) & 0xffffffff)
2225#else
2226#define ADDR(x) (x)
2227#endif
2228
2229#ifdef __i386__
2230void helper_std_i386(target_ulong addr, int mem_idx)
2231{
2232 uint64_t tmp = ((uint64_t)env->t1 << 32) | (uint64_t)(env->t2 & 0xffffffff);
2233
2234#if !defined(CONFIG_USER_ONLY)
2235 switch (mem_idx) {
2236 case 0:
2237 stq_user(ADDR(addr), tmp);
2238 break;
2239 case 1:
2240 stq_kernel(ADDR(addr), tmp);
2241 break;
2242#ifdef TARGET_SPARC64
2243 case 2:
2244 stq_hypv(ADDR(addr), tmp);
2245 break;
2246#endif
2247 default:
2248 break;
2249 }
2250#else
2251 stq_raw(ADDR(addr), tmp);
2252#endif
2253}
2254#endif /* __i386__ */
2255
2256void helper_stdf(target_ulong addr, int mem_idx)
2257{
2258#if !defined(CONFIG_USER_ONLY)
2259 switch (mem_idx) {
2260 case 0:
2261 stfq_user(ADDR(addr), DT0);
2262 break;
2263 case 1:
2264 stfq_kernel(ADDR(addr), DT0);
2265 break;
2266#ifdef TARGET_SPARC64
2267 case 2:
2268 stfq_hypv(ADDR(addr), DT0);
2269 break;
2270#endif
2271 default:
2272 break;
2273 }
2274#else
2275 stfq_raw(ADDR(addr), DT0);
2276#endif
2277}
2278
2279void helper_lddf(target_ulong addr, int mem_idx)
2280{
2281#if !defined(CONFIG_USER_ONLY)
2282 switch (mem_idx) {
2283 case 0:
2284 DT0 = ldfq_user(ADDR(addr));
2285 break;
2286 case 1:
2287 DT0 = ldfq_kernel(ADDR(addr));
2288 break;
2289#ifdef TARGET_SPARC64
2290 case 2:
2291 DT0 = ldfq_hypv(ADDR(addr));
2292 break;
2293#endif
2294 default:
2295 break;
2296 }
2297#else
2298 DT0 = ldfq_raw(ADDR(addr));
2299#endif
2300}
2301
2302#if defined(CONFIG_USER_ONLY)
2303void helper_ldqf(target_ulong addr)
2304{
2305 // XXX add 128 bit load
2306 CPU_QuadU u;
2307
2308 u.ll.upper = ldq_raw(ADDR(addr));
2309 u.ll.lower = ldq_raw(ADDR(addr + 8));
2310 QT0 = u.q;
2311}
2312
2313void helper_stqf(target_ulong addr)
2314{
2315 // XXX add 128 bit store
2316 CPU_QuadU u;
2317
2318 u.q = QT0;
2319 stq_raw(ADDR(addr), u.ll.upper);
2320 stq_raw(ADDR(addr + 8), u.ll.lower);
2321}
2322#endif
2323
2324#undef ADDR
2325
8d5f07fa 2326void helper_ldfsr(void)
e8af50a3 2327{
7a0e1f41 2328 int rnd_mode;
bb5529bb
BS		 2329
2330 PUT_FSR32(env, *((uint32_t *) &FT0));
e8af50a3
FB		 2331 switch (env->fsr & FSR_RD_MASK) {
2332 case FSR_RD_NEAREST:
7a0e1f41 2333 rnd_mode = float_round_nearest_even;
0f8a249a 2334 break;
ed910241 2335 default:
e8af50a3 2336 case FSR_RD_ZERO:
7a0e1f41 2337 rnd_mode = float_round_to_zero;
0f8a249a 2338 break;
e8af50a3 2339 case FSR_RD_POS:
7a0e1f41 2340 rnd_mode = float_round_up;
0f8a249a 2341 break;
e8af50a3 2342 case FSR_RD_NEG:
7a0e1f41 2343 rnd_mode = float_round_down;
0f8a249a 2344 break;
e8af50a3 2345 }
7a0e1f41 2346 set_float_rounding_mode(rnd_mode, &env->fp_status);
e8af50a3 2347}
e80cfcfc 2348
bb5529bb
BS		 2349void helper_stfsr(void)
2350{
2351 *((uint32_t *) &FT0) = GET_FSR32(env);
2352}
2353
2354void helper_debug(void)
e80cfcfc
FB		 2355{
2356 env->exception_index = EXCP_DEBUG;
2357 cpu_loop_exit();
2358}
af7bf89b 2359
3475187d 2360#ifndef TARGET_SPARC64
72a9747b
BS		 2361/* XXX: use another pointer for %iN registers to avoid slow wrapping
2362 handling ? */
2363void helper_save(void)
2364{
2365 uint32_t cwp;
2366
2367 cwp = (env->cwp - 1) & (NWINDOWS - 1);
2368 if (env->wim & (1 << cwp)) {
2369 raise_exception(TT_WIN_OVF);
2370 }
2371 set_cwp(cwp);
2372}
2373
2374void helper_restore(void)
2375{
2376 uint32_t cwp;
2377
2378 cwp = (env->cwp + 1) & (NWINDOWS - 1);
2379 if (env->wim & (1 << cwp)) {
2380 raise_exception(TT_WIN_UNF);
2381 }
2382 set_cwp(cwp);
2383}
2384
1a2fb1c0 2385void helper_wrpsr(target_ulong new_psr)
af7bf89b 2386{
1a2fb1c0 2387 if ((new_psr & PSR_CWP) >= NWINDOWS)
d4218d99
BS		 2388 raise_exception(TT_ILL_INSN);
2389 else
1a2fb1c0 2390 PUT_PSR(env, new_psr);
af7bf89b
FB		 2391}
2392
1a2fb1c0 2393target_ulong helper_rdpsr(void)
af7bf89b 2394{
1a2fb1c0 2395 return GET_PSR(env);
af7bf89b 2396}
3475187d
FB		 2397
2398#else
72a9747b
BS		 2399/* XXX: use another pointer for %iN registers to avoid slow wrapping
2400 handling ? */
2401void helper_save(void)
2402{
2403 uint32_t cwp;
2404
2405 cwp = (env->cwp - 1) & (NWINDOWS - 1);
2406 if (env->cansave == 0) {
2407 raise_exception(TT_SPILL | (env->otherwin != 0 ?
2408 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2409 ((env->wstate & 0x7) << 2)));
2410 } else {
2411 if (env->cleanwin - env->canrestore == 0) {
2412 // XXX Clean windows without trap
2413 raise_exception(TT_CLRWIN);
2414 } else {
2415 env->cansave--;
2416 env->canrestore++;
2417 set_cwp(cwp);
2418 }
2419 }
2420}
2421
2422void helper_restore(void)
2423{
2424 uint32_t cwp;
2425
2426 cwp = (env->cwp + 1) & (NWINDOWS - 1);
2427 if (env->canrestore == 0) {
2428 raise_exception(TT_FILL | (env->otherwin != 0 ?
2429 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2430 ((env->wstate & 0x7) << 2)));
2431 } else {
2432 env->cansave++;
2433 env->canrestore--;
2434 set_cwp(cwp);
2435 }
2436}
2437
2438void helper_flushw(void)
2439{
2440 if (env->cansave != NWINDOWS - 2) {
2441 raise_exception(TT_SPILL | (env->otherwin != 0 ?
2442 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2443 ((env->wstate & 0x7) << 2)));
2444 }
2445}
2446
2447void helper_saved(void)
2448{
2449 env->cansave++;
2450 if (env->otherwin == 0)
2451 env->canrestore--;
2452 else
2453 env->otherwin--;
2454}
2455
2456void helper_restored(void)
2457{
2458 env->canrestore++;
2459 if (env->cleanwin < NWINDOWS - 1)
2460 env->cleanwin++;
2461 if (env->otherwin == 0)
2462 env->cansave--;
2463 else
2464 env->otherwin--;
2465}
2466
d35527d9
BS		 2467target_ulong helper_rdccr(void)
2468{
2469 return GET_CCR(env);
2470}
2471
2472void helper_wrccr(target_ulong new_ccr)
2473{
2474 PUT_CCR(env, new_ccr);
2475}
2476
2477// CWP handling is reversed in V9, but we still use the V8 register
2478// order.
2479target_ulong helper_rdcwp(void)
2480{
2481 return GET_CWP64(env);
2482}
2483
2484void helper_wrcwp(target_ulong new_cwp)
2485{
2486 PUT_CWP64(env, new_cwp);
2487}
3475187d 2488
1f5063fb
BS		 2489// This function uses non-native bit order
2490#define GET_FIELD(X, FROM, TO) \
2491 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
2492
2493// This function uses the order in the manuals, i.e. bit 0 is 2^0
2494#define GET_FIELD_SP(X, FROM, TO) \
2495 GET_FIELD(X, 63 - (TO), 63 - (FROM))
2496
2497target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
2498{
2499 return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
2500 (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
2501 (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) |
2502 (GET_FIELD_SP(pixel_addr, 56, 59) << 13) |
2503 (GET_FIELD_SP(pixel_addr, 35, 38) << 9) |
2504 (GET_FIELD_SP(pixel_addr, 13, 16) << 5) |
2505 (((pixel_addr >> 55) & 1) << 4) |
2506 (GET_FIELD_SP(pixel_addr, 33, 34) << 2) |
2507 GET_FIELD_SP(pixel_addr, 11, 12);
2508}
2509
2510target_ulong helper_alignaddr(target_ulong addr, target_ulong offset)
2511{
2512 uint64_t tmp;
2513
2514 tmp = addr + offset;
2515 env->gsr &= ~7ULL;
2516 env->gsr |= tmp & 7ULL;
2517 return tmp & ~7ULL;
2518}
2519
1a2fb1c0 2520target_ulong helper_popc(target_ulong val)
3475187d 2521{
1a2fb1c0 2522 return ctpop64(val);
3475187d 2523}
83469015
FB		 2524
2525static inline uint64_t *get_gregset(uint64_t pstate)
2526{
2527 switch (pstate) {
2528 default:
2529 case 0:
0f8a249a 2530 return env->bgregs;
83469015 2531 case PS_AG:
0f8a249a 2532 return env->agregs;
83469015 2533 case PS_MG:
0f8a249a 2534 return env->mgregs;
83469015 2535 case PS_IG:
0f8a249a 2536 return env->igregs;
83469015
FB		 2537 }
2538}
2539
8f1f22f6 2540static inline void change_pstate(uint64_t new_pstate)
83469015 2541{
8f1f22f6 2542 uint64_t pstate_regs, new_pstate_regs;
83469015
FB		 2543 uint64_t *src, *dst;
2544
83469015
FB		 2545 pstate_regs = env->pstate & 0xc01;
2546 new_pstate_regs = new_pstate & 0xc01;
2547 if (new_pstate_regs != pstate_regs) {
0f8a249a
BS		 2548 // Switch global register bank
2549 src = get_gregset(new_pstate_regs);
2550 dst = get_gregset(pstate_regs);
2551 memcpy32(dst, env->gregs);
2552 memcpy32(env->gregs, src);
83469015
FB		 2553 }
2554 env->pstate = new_pstate;
2555}
2556
1a2fb1c0 2557void helper_wrpstate(target_ulong new_state)
8f1f22f6 2558{
1a2fb1c0 2559 change_pstate(new_state & 0xf3f);
8f1f22f6
BS		 2560}
2561
1a2fb1c0 2562void helper_done(void)
83469015
FB		 2563{
2564 env->tl--;
375ee38b
BS		 2565 env->tsptr = &env->ts[env->tl];
2566 env->pc = env->tsptr->tpc;
2567 env->npc = env->tsptr->tnpc + 4;
2568 PUT_CCR(env, env->tsptr->tstate >> 32);
2569 env->asi = (env->tsptr->tstate >> 24) & 0xff;
2570 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2571 PUT_CWP64(env, env->tsptr->tstate & 0xff);
83469015
FB		 2572}
2573
1a2fb1c0 2574void helper_retry(void)
83469015
FB		 2575{
2576 env->tl--;
375ee38b
BS		 2577 env->tsptr = &env->ts[env->tl];
2578 env->pc = env->tsptr->tpc;
2579 env->npc = env->tsptr->tnpc;
2580 PUT_CCR(env, env->tsptr->tstate >> 32);
2581 env->asi = (env->tsptr->tstate >> 24) & 0xff;
2582 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2583 PUT_CWP64(env, env->tsptr->tstate & 0xff);
83469015 2584}
3475187d 2585#endif
ee5bbe38
FB		 2586
2587void set_cwp(int new_cwp)
2588{
2589 /* put the modified wrap registers at their proper location */
2590 if (env->cwp == (NWINDOWS - 1))
2591 memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
2592 env->cwp = new_cwp;
2593 /* put the wrap registers at their temporary location */
2594 if (new_cwp == (NWINDOWS - 1))
2595 memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
2596 env->regwptr = env->regbase + (new_cwp * 16);
2597 REGWPTR = env->regwptr;
2598}
2599
2600void cpu_set_cwp(CPUState *env1, int new_cwp)
2601{
2602 CPUState *saved_env;
2603#ifdef reg_REGWPTR
2604 target_ulong *saved_regwptr;
2605#endif
2606
2607 saved_env = env;
2608#ifdef reg_REGWPTR
2609 saved_regwptr = REGWPTR;
2610#endif
2611 env = env1;
2612 set_cwp(new_cwp);
2613 env = saved_env;
2614#ifdef reg_REGWPTR
2615 REGWPTR = saved_regwptr;
2616#endif
2617}
2618
2619#ifdef TARGET_SPARC64
0b09be2b
BS		 2620#ifdef DEBUG_PCALL
2621static const char * const excp_names[0x50] = {
2622 [TT_TFAULT] = "Instruction Access Fault",
2623 [TT_TMISS] = "Instruction Access MMU Miss",
2624 [TT_CODE_ACCESS] = "Instruction Access Error",
2625 [TT_ILL_INSN] = "Illegal Instruction",
2626 [TT_PRIV_INSN] = "Privileged Instruction",
2627 [TT_NFPU_INSN] = "FPU Disabled",
2628 [TT_FP_EXCP] = "FPU Exception",
2629 [TT_TOVF] = "Tag Overflow",
2630 [TT_CLRWIN] = "Clean Windows",
2631 [TT_DIV_ZERO] = "Division By Zero",
2632 [TT_DFAULT] = "Data Access Fault",
2633 [TT_DMISS] = "Data Access MMU Miss",
2634 [TT_DATA_ACCESS] = "Data Access Error",
2635 [TT_DPROT] = "Data Protection Error",
2636 [TT_UNALIGNED] = "Unaligned Memory Access",
2637 [TT_PRIV_ACT] = "Privileged Action",
2638 [TT_EXTINT | 0x1] = "External Interrupt 1",
2639 [TT_EXTINT | 0x2] = "External Interrupt 2",
2640 [TT_EXTINT | 0x3] = "External Interrupt 3",
2641 [TT_EXTINT | 0x4] = "External Interrupt 4",
2642 [TT_EXTINT | 0x5] = "External Interrupt 5",
2643 [TT_EXTINT | 0x6] = "External Interrupt 6",
2644 [TT_EXTINT | 0x7] = "External Interrupt 7",
2645 [TT_EXTINT | 0x8] = "External Interrupt 8",
2646 [TT_EXTINT | 0x9] = "External Interrupt 9",
2647 [TT_EXTINT | 0xa] = "External Interrupt 10",
2648 [TT_EXTINT | 0xb] = "External Interrupt 11",
2649 [TT_EXTINT | 0xc] = "External Interrupt 12",
2650 [TT_EXTINT | 0xd] = "External Interrupt 13",
2651 [TT_EXTINT | 0xe] = "External Interrupt 14",
2652 [TT_EXTINT | 0xf] = "External Interrupt 15",
2653};
2654#endif
2655
ee5bbe38
FB		 2656void do_interrupt(int intno)
2657{
2658#ifdef DEBUG_PCALL
2659 if (loglevel & CPU_LOG_INT) {
0f8a249a 2660 static int count;
0b09be2b
BS		 2661 const char *name;
2662
2663 if (intno < 0 || intno >= 0x180 || (intno > 0x4f && intno < 0x80))
2664 name = "Unknown";
2665 else if (intno >= 0x100)
2666 name = "Trap Instruction";
2667 else if (intno >= 0xc0)
2668 name = "Window Fill";
2669 else if (intno >= 0x80)
2670 name = "Window Spill";
2671 else {
2672 name = excp_names[intno];
2673 if (!name)
2674 name = "Unknown";
2675 }
2676
2677 fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
2678 " SP=%016" PRIx64 "\n",
2679 count, name, intno,
ee5bbe38
FB		 2680 env->pc,
2681 env->npc, env->regwptr[6]);
0f8a249a 2682 cpu_dump_state(env, logfile, fprintf, 0);
ee5bbe38 2683#if 0
0f8a249a
BS		 2684 {
2685 int i;
2686 uint8_t *ptr;
2687
2688 fprintf(logfile, " code=");
2689 ptr = (uint8_t *)env->pc;
2690 for(i = 0; i < 16; i++) {
2691 fprintf(logfile, " %02x", ldub(ptr + i));
2692 }
2693 fprintf(logfile, "\n");
2694 }
ee5bbe38 2695#endif
0f8a249a 2696 count++;
ee5bbe38
FB		 2697 }
2698#endif
5fafdf24 2699#if !defined(CONFIG_USER_ONLY)
83469015 2700 if (env->tl == MAXTL) {
c68ea704 2701 cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
0f8a249a 2702 return;
ee5bbe38
FB		 2703 }
2704#endif
375ee38b
BS		 2705 env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
2706 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
2707 GET_CWP64(env);
2708 env->tsptr->tpc = env->pc;
2709 env->tsptr->tnpc = env->npc;
2710 env->tsptr->tt = intno;
8f1f22f6
BS		 2711 change_pstate(PS_PEF | PS_PRIV | PS_AG);
2712
2713 if (intno == TT_CLRWIN)
2714 set_cwp((env->cwp - 1) & (NWINDOWS - 1));
2715 else if ((intno & 0x1c0) == TT_SPILL)
2716 set_cwp((env->cwp - env->cansave - 2) & (NWINDOWS - 1));
2717 else if ((intno & 0x1c0) == TT_FILL)
2718 set_cwp((env->cwp + 1) & (NWINDOWS - 1));
83469015
FB		 2719 env->tbr &= ~0x7fffULL;
2720 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
2721 if (env->tl < MAXTL - 1) {
0f8a249a 2722 env->tl++;
83469015 2723 } else {
0f8a249a
BS		 2724 env->pstate |= PS_RED;
2725 if (env->tl != MAXTL)
2726 env->tl++;
83469015 2727 }
375ee38b 2728 env->tsptr = &env->ts[env->tl];
ee5bbe38
FB		 2729 env->pc = env->tbr;
2730 env->npc = env->pc + 4;
2731 env->exception_index = 0;
2732}
2733#else
0b09be2b
BS		 2734#ifdef DEBUG_PCALL
2735static const char * const excp_names[0x80] = {
2736 [TT_TFAULT] = "Instruction Access Fault",
2737 [TT_ILL_INSN] = "Illegal Instruction",
2738 [TT_PRIV_INSN] = "Privileged Instruction",
2739 [TT_NFPU_INSN] = "FPU Disabled",
2740 [TT_WIN_OVF] = "Window Overflow",
2741 [TT_WIN_UNF] = "Window Underflow",
2742 [TT_UNALIGNED] = "Unaligned Memory Access",
2743 [TT_FP_EXCP] = "FPU Exception",
2744 [TT_DFAULT] = "Data Access Fault",
2745 [TT_TOVF] = "Tag Overflow",
2746 [TT_EXTINT | 0x1] = "External Interrupt 1",
2747 [TT_EXTINT | 0x2] = "External Interrupt 2",
2748 [TT_EXTINT | 0x3] = "External Interrupt 3",
2749 [TT_EXTINT | 0x4] = "External Interrupt 4",
2750 [TT_EXTINT | 0x5] = "External Interrupt 5",
2751 [TT_EXTINT | 0x6] = "External Interrupt 6",
2752 [TT_EXTINT | 0x7] = "External Interrupt 7",
2753 [TT_EXTINT | 0x8] = "External Interrupt 8",
2754 [TT_EXTINT | 0x9] = "External Interrupt 9",
2755 [TT_EXTINT | 0xa] = "External Interrupt 10",
2756 [TT_EXTINT | 0xb] = "External Interrupt 11",
2757 [TT_EXTINT | 0xc] = "External Interrupt 12",
2758 [TT_EXTINT | 0xd] = "External Interrupt 13",
2759 [TT_EXTINT | 0xe] = "External Interrupt 14",
2760 [TT_EXTINT | 0xf] = "External Interrupt 15",
2761 [TT_TOVF] = "Tag Overflow",
2762 [TT_CODE_ACCESS] = "Instruction Access Error",
2763 [TT_DATA_ACCESS] = "Data Access Error",
2764 [TT_DIV_ZERO] = "Division By Zero",
2765 [TT_NCP_INSN] = "Coprocessor Disabled",
2766};
2767#endif
2768
ee5bbe38
FB		 2769void do_interrupt(int intno)
2770{
2771 int cwp;
2772
2773#ifdef DEBUG_PCALL
2774 if (loglevel & CPU_LOG_INT) {
0f8a249a 2775 static int count;
0b09be2b
BS		 2776 const char *name;
2777
2778 if (intno < 0 || intno >= 0x100)
2779 name = "Unknown";
2780 else if (intno >= 0x80)
2781 name = "Trap Instruction";
2782 else {
2783 name = excp_names[intno];
2784 if (!name)
2785 name = "Unknown";
2786 }
2787
2788 fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
2789 count, name, intno,
ee5bbe38
FB		 2790 env->pc,
2791 env->npc, env->regwptr[6]);
0f8a249a 2792 cpu_dump_state(env, logfile, fprintf, 0);
ee5bbe38 2793#if 0
0f8a249a
BS		 2794 {
2795 int i;
2796 uint8_t *ptr;
2797
2798 fprintf(logfile, " code=");
2799 ptr = (uint8_t *)env->pc;
2800 for(i = 0; i < 16; i++) {
2801 fprintf(logfile, " %02x", ldub(ptr + i));
2802 }
2803 fprintf(logfile, "\n");
2804 }
ee5bbe38 2805#endif
0f8a249a 2806 count++;
ee5bbe38
FB		 2807 }
2808#endif
5fafdf24 2809#if !defined(CONFIG_USER_ONLY)
ee5bbe38 2810 if (env->psret == 0) {
c68ea704 2811 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
0f8a249a 2812 return;
ee5bbe38
FB		 2813 }
2814#endif
2815 env->psret = 0;
5fafdf24 2816 cwp = (env->cwp - 1) & (NWINDOWS - 1);
ee5bbe38
FB		 2817 set_cwp(cwp);
2818 env->regwptr[9] = env->pc;
2819 env->regwptr[10] = env->npc;
2820 env->psrps = env->psrs;
2821 env->psrs = 1;
2822 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
2823 env->pc = env->tbr;
2824 env->npc = env->pc + 4;
2825 env->exception_index = 0;
2826}
2827#endif
2828
5fafdf24 2829#if !defined(CONFIG_USER_ONLY)
ee5bbe38 2830
d2889a3e
BS		 2831static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
2832 void *retaddr);
2833
ee5bbe38 2834#define MMUSUFFIX _mmu
d2889a3e 2835#define ALIGNED_ONLY
273af660
TS		 2836#ifdef __s390__
2837# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
2838#else
2839# define GETPC() (__builtin_return_address(0))
2840#endif
ee5bbe38
FB		 2841
2842#define SHIFT 0
2843#include "softmmu_template.h"
2844
2845#define SHIFT 1
2846#include "softmmu_template.h"
2847
2848#define SHIFT 2
2849#include "softmmu_template.h"
2850
2851#define SHIFT 3
2852#include "softmmu_template.h"
2853
d2889a3e
BS		 2854static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
2855 void *retaddr)
2856{
94554550
BS		 2857#ifdef DEBUG_UNALIGNED
2858 printf("Unaligned access to 0x%x from 0x%x\n", addr, env->pc);
2859#endif
2860 raise_exception(TT_UNALIGNED);
d2889a3e 2861}
ee5bbe38
FB		 2862
2863/* try to fill the TLB and return an exception if error. If retaddr is
2864 NULL, it means that the function was called in C code (i.e. not
2865 from generated code or from helper.c) */
2866/* XXX: fix it to restore all registers */
6ebbf390 2867void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
ee5bbe38
FB		 2868{
2869 TranslationBlock *tb;
2870 int ret;
2871 unsigned long pc;
2872 CPUState *saved_env;
2873
2874 /* XXX: hack to restore env in all cases, even if not called from
2875 generated code */
2876 saved_env = env;
2877 env = cpu_single_env;
2878
6ebbf390 2879 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ee5bbe38
FB		 2880 if (ret) {
2881 if (retaddr) {
2882 /* now we have a real cpu fault */
2883 pc = (unsigned long)retaddr;
2884 tb = tb_find_pc(pc);
2885 if (tb) {
2886 /* the PC is inside the translated code. It means that we have
2887 a virtual CPU fault */
2888 cpu_restore_state(tb, env, pc, (void *)T2);
2889 }
2890 }
2891 cpu_loop_exit();
2892 }
2893 env = saved_env;
2894}
2895
2896#endif
6c36d3fa
BS		 2897
2898#ifndef TARGET_SPARC64
5dcb6b91 2899void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
6c36d3fa
BS		 2900 int is_asi)
2901{
2902 CPUState *saved_env;
2903
2904 /* XXX: hack to restore env in all cases, even if not called from
2905 generated code */
2906 saved_env = env;
2907 env = cpu_single_env;
8543e2cf
BS		 2908#ifdef DEBUG_UNASSIGNED
2909 if (is_asi)
2910 printf("Unassigned mem %s access to " TARGET_FMT_plx " asi 0x%02x from "
2911 TARGET_FMT_lx "\n",
2912 is_exec ? "exec" : is_write ? "write" : "read", addr, is_asi,
2913 env->pc);
2914 else
2915 printf("Unassigned mem %s access to " TARGET_FMT_plx " from "
2916 TARGET_FMT_lx "\n",
2917 is_exec ? "exec" : is_write ? "write" : "read", addr, env->pc);
2918#endif
6c36d3fa 2919 if (env->mmuregs[3]) /* Fault status register */
0f8a249a 2920 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
6c36d3fa
BS		 2921 if (is_asi)
2922 env->mmuregs[3] |= 1 << 16;
2923 if (env->psrs)
2924 env->mmuregs[3] |= 1 << 5;
2925 if (is_exec)
2926 env->mmuregs[3] |= 1 << 6;
2927 if (is_write)
2928 env->mmuregs[3] |= 1 << 7;
2929 env->mmuregs[3] |= (5 << 2) | 2;
2930 env->mmuregs[4] = addr; /* Fault address register */
2931 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
1b2e93c1
BS		 2932 if (is_exec)
2933 raise_exception(TT_CODE_ACCESS);
2934 else
2935 raise_exception(TT_DATA_ACCESS);
6c36d3fa
BS		 2936 }
2937 env = saved_env;
2938}
2939#else
5dcb6b91 2940void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
6c36d3fa
BS		 2941 int is_asi)
2942{
2943#ifdef DEBUG_UNASSIGNED
2944 CPUState *saved_env;
2945
2946 /* XXX: hack to restore env in all cases, even if not called from
2947 generated code */
2948 saved_env = env;
2949 env = cpu_single_env;
5dcb6b91 2950 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n",
6c36d3fa
BS		 2951 addr, env->pc);
2952 env = saved_env;
2953#endif
1b2e93c1
BS		 2954 if (is_exec)
2955 raise_exception(TT_CODE_ACCESS);
2956 else
2957 raise_exception(TT_DATA_ACCESS);
6c36d3fa
BS		 2958}
2959#endif
20c9f095 2960
Qemu copy for testing