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Prepare for changing audio_pcm_ops dynamically (partially revert r5422)
[qemu.git] / target-sparc / op_helper.c
CommitLineData
e8af50a3 1#include "exec.h"
eed152bb 2#include "host-utils.h"
1a2fb1c0 3#include "helper.h"
0828b448
BS		 4#if !defined(CONFIG_USER_ONLY)
5#include "softmmu_exec.h"
6#endif /* !defined(CONFIG_USER_ONLY) */
e8af50a3 7
e80cfcfc 8//#define DEBUG_MMU
952a328f 9//#define DEBUG_MXCC
94554550 10//#define DEBUG_UNALIGNED
6c36d3fa 11//#define DEBUG_UNASSIGNED
8543e2cf 12//#define DEBUG_ASI
d81fd722 13//#define DEBUG_PCALL
e80cfcfc 14
952a328f
BS		 15#ifdef DEBUG_MMU
16#define DPRINTF_MMU(fmt, args...) \
17do { printf("MMU: " fmt , ##args); } while (0)
18#else
22548760 19#define DPRINTF_MMU(fmt, args...) do {} while (0)
952a328f
BS		 20#endif
21
22#ifdef DEBUG_MXCC
23#define DPRINTF_MXCC(fmt, args...) \
24do { printf("MXCC: " fmt , ##args); } while (0)
25#else
22548760 26#define DPRINTF_MXCC(fmt, args...) do {} while (0)
952a328f
BS		 27#endif
28
8543e2cf
BS		 29#ifdef DEBUG_ASI
30#define DPRINTF_ASI(fmt, args...) \
31do { printf("ASI: " fmt , ##args); } while (0)
32#else
22548760 33#define DPRINTF_ASI(fmt, args...) do {} while (0)
8543e2cf
BS		 34#endif
35
2cade6a3
BS		 36#ifdef TARGET_SPARC64
37#ifndef TARGET_ABI32
38#define AM_CHECK(env1) ((env1)->pstate & PS_AM)
c2bc0e38 39#else
2cade6a3
BS		 40#define AM_CHECK(env1) (1)
41#endif
c2bc0e38
BS		 42#endif
43
2cade6a3
BS		 44static inline void address_mask(CPUState *env1, target_ulong *addr)
45{
46#ifdef TARGET_SPARC64
47 if (AM_CHECK(env1))
48 *addr &= 0xffffffffULL;
49#endif
50}
51
9d893301
FB		 52void raise_exception(int tt)
53{
54 env->exception_index = tt;
55 cpu_loop_exit();
3b46e624 56}
9d893301 57
91736d37
BS		 58static inline void set_cwp(int new_cwp)
59{
60 cpu_set_cwp(env, new_cwp);
61}
62
2b29924f
BS		 63void helper_check_align(target_ulong addr, uint32_t align)
64{
c2bc0e38
BS		 65 if (addr & align) {
66#ifdef DEBUG_UNALIGNED
67 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
68 "\n", addr, env->pc);
69#endif
2b29924f 70 raise_exception(TT_UNALIGNED);
c2bc0e38 71 }
2b29924f
BS		 72}
73
44e7757c
BS		 74#define F_HELPER(name, p) void helper_f##name##p(void)
75
44e7757c 76#define F_BINOP(name) \
714547bb 77 float32 helper_f ## name ## s (float32 src1, float32 src2) \
44e7757c 78 { \
714547bb 79 return float32_ ## name (src1, src2, &env->fp_status); \
44e7757c
BS		 80 } \
81 F_HELPER(name, d) \
82 { \
83 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
4e14008f
BS		 84 } \
85 F_HELPER(name, q) \
86 { \
87 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
44e7757c 88 }
44e7757c
BS		 89
90F_BINOP(add);
91F_BINOP(sub);
92F_BINOP(mul);
93F_BINOP(div);
94#undef F_BINOP
95
d84763bc 96void helper_fsmuld(float32 src1, float32 src2)
1a2fb1c0 97{
d84763bc
BS		 98 DT0 = float64_mul(float32_to_float64(src1, &env->fp_status),
99 float32_to_float64(src2, &env->fp_status),
44e7757c
BS		 100 &env->fp_status);
101}
1a2fb1c0 102
4e14008f
BS		 103void helper_fdmulq(void)
104{
105 QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
106 float64_to_float128(DT1, &env->fp_status),
107 &env->fp_status);
108}
4e14008f 109
714547bb 110float32 helper_fnegs(float32 src)
44e7757c 111{
714547bb 112 return float32_chs(src);
417454b0
BS		 113}
114
44e7757c
BS		 115#ifdef TARGET_SPARC64
116F_HELPER(neg, d)
7e8c2b6c 117{
44e7757c 118 DT0 = float64_chs(DT1);
7e8c2b6c 119}
4e14008f 120
4e14008f
BS		 121F_HELPER(neg, q)
122{
123 QT0 = float128_chs(QT1);
124}
125#endif
44e7757c
BS		 126
127/* Integer to float conversion. */
714547bb 128float32 helper_fitos(int32_t src)
a0c4cb4a 129{
714547bb 130 return int32_to_float32(src, &env->fp_status);
a0c4cb4a
FB		 131}
132
d84763bc 133void helper_fitod(int32_t src)
a0c4cb4a 134{
d84763bc 135 DT0 = int32_to_float64(src, &env->fp_status);
a0c4cb4a 136}
9c2b428e 137
c5d04e99 138void helper_fitoq(int32_t src)
4e14008f 139{
c5d04e99 140 QT0 = int32_to_float128(src, &env->fp_status);
4e14008f 141}
4e14008f 142
1e64e78d 143#ifdef TARGET_SPARC64
d84763bc 144float32 helper_fxtos(void)
1e64e78d 145{
d84763bc 146 return int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
1e64e78d
BS		 147}
148
44e7757c 149F_HELPER(xto, d)
1e64e78d 150{
1e64e78d 151 DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
1e64e78d 152}
64a88d5d 153
4e14008f
BS		 154F_HELPER(xto, q)
155{
156 QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
157}
158#endif
44e7757c
BS		 159#undef F_HELPER
160
161/* floating point conversion */
d84763bc 162float32 helper_fdtos(void)
44e7757c 163{
d84763bc 164 return float64_to_float32(DT1, &env->fp_status);
44e7757c
BS		 165}
166
d84763bc 167void helper_fstod(float32 src)
44e7757c 168{
d84763bc 169 DT0 = float32_to_float64(src, &env->fp_status);
44e7757c 170}
9c2b428e 171
c5d04e99 172float32 helper_fqtos(void)
4e14008f 173{
c5d04e99 174 return float128_to_float32(QT1, &env->fp_status);
4e14008f
BS		 175}
176
c5d04e99 177void helper_fstoq(float32 src)
4e14008f 178{
c5d04e99 179 QT0 = float32_to_float128(src, &env->fp_status);
4e14008f
BS		 180}
181
182void helper_fqtod(void)
183{
184 DT0 = float128_to_float64(QT1, &env->fp_status);
185}
186
187void helper_fdtoq(void)
188{
189 QT0 = float64_to_float128(DT1, &env->fp_status);
190}
4e14008f 191
44e7757c 192/* Float to integer conversion. */
714547bb 193int32_t helper_fstoi(float32 src)
44e7757c 194{
714547bb 195 return float32_to_int32_round_to_zero(src, &env->fp_status);
44e7757c
BS		 196}
197
d84763bc 198int32_t helper_fdtoi(void)
44e7757c 199{
d84763bc 200 return float64_to_int32_round_to_zero(DT1, &env->fp_status);
44e7757c
BS		 201}
202
c5d04e99 203int32_t helper_fqtoi(void)
4e14008f 204{
c5d04e99 205 return float128_to_int32_round_to_zero(QT1, &env->fp_status);
4e14008f 206}
4e14008f 207
44e7757c 208#ifdef TARGET_SPARC64
d84763bc 209void helper_fstox(float32 src)
44e7757c 210{
d84763bc 211 *((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status);
44e7757c
BS		 212}
213
214void helper_fdtox(void)
215{
216 *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
217}
218
4e14008f
BS		 219void helper_fqtox(void)
220{
221 *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);
222}
4e14008f 223
44e7757c
BS		 224void helper_faligndata(void)
225{
226 uint64_t tmp;
227
228 tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
06057e6f
BS		 229 /* on many architectures a shift of 64 does nothing */
230 if ((env->gsr & 7) != 0) {
231 tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
232 }
44e7757c
BS		 233 *((uint64_t *)&DT0) = tmp;
234}
235
44e7757c
BS		 236#ifdef WORDS_BIGENDIAN
237#define VIS_B64(n) b[7 - (n)]
238#define VIS_W64(n) w[3 - (n)]
239#define VIS_SW64(n) sw[3 - (n)]
240#define VIS_L64(n) l[1 - (n)]
241#define VIS_B32(n) b[3 - (n)]
242#define VIS_W32(n) w[1 - (n)]
243#else
244#define VIS_B64(n) b[n]
245#define VIS_W64(n) w[n]
246#define VIS_SW64(n) sw[n]
247#define VIS_L64(n) l[n]
248#define VIS_B32(n) b[n]
249#define VIS_W32(n) w[n]
250#endif
251
252typedef union {
253 uint8_t b[8];
254 uint16_t w[4];
255 int16_t sw[4];
256 uint32_t l[2];
257 float64 d;
258} vis64;
259
260typedef union {
261 uint8_t b[4];
262 uint16_t w[2];
263 uint32_t l;
264 float32 f;
265} vis32;
266
267void helper_fpmerge(void)
268{
269 vis64 s, d;
270
271 s.d = DT0;
272 d.d = DT1;
273
274 // Reverse calculation order to handle overlap
275 d.VIS_B64(7) = s.VIS_B64(3);
276 d.VIS_B64(6) = d.VIS_B64(3);
277 d.VIS_B64(5) = s.VIS_B64(2);
278 d.VIS_B64(4) = d.VIS_B64(2);
279 d.VIS_B64(3) = s.VIS_B64(1);
280 d.VIS_B64(2) = d.VIS_B64(1);
281 d.VIS_B64(1) = s.VIS_B64(0);
282 //d.VIS_B64(0) = d.VIS_B64(0);
283
284 DT0 = d.d;
285}
286
287void helper_fmul8x16(void)
288{
289 vis64 s, d;
290 uint32_t tmp;
291
292 s.d = DT0;
293 d.d = DT1;
294
295#define PMUL(r) \
296 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
297 if ((tmp & 0xff) > 0x7f) \
298 tmp += 0x100; \
299 d.VIS_W64(r) = tmp >> 8;
300
301 PMUL(0);
302 PMUL(1);
303 PMUL(2);
304 PMUL(3);
305#undef PMUL
306
307 DT0 = d.d;
308}
309
310void helper_fmul8x16al(void)
311{
312 vis64 s, d;
313 uint32_t tmp;
314
315 s.d = DT0;
316 d.d = DT1;
317
318#define PMUL(r) \
319 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
320 if ((tmp & 0xff) > 0x7f) \
321 tmp += 0x100; \
322 d.VIS_W64(r) = tmp >> 8;
323
324 PMUL(0);
325 PMUL(1);
326 PMUL(2);
327 PMUL(3);
328#undef PMUL
329
330 DT0 = d.d;
331}
332
333void helper_fmul8x16au(void)
334{
335 vis64 s, d;
336 uint32_t tmp;
337
338 s.d = DT0;
339 d.d = DT1;
340
341#define PMUL(r) \
342 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
343 if ((tmp & 0xff) > 0x7f) \
344 tmp += 0x100; \
345 d.VIS_W64(r) = tmp >> 8;
346
347 PMUL(0);
348 PMUL(1);
349 PMUL(2);
350 PMUL(3);
351#undef PMUL
352
353 DT0 = d.d;
354}
355
356void helper_fmul8sux16(void)
357{
358 vis64 s, d;
359 uint32_t tmp;
360
361 s.d = DT0;
362 d.d = DT1;
363
364#define PMUL(r) \
365 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
366 if ((tmp & 0xff) > 0x7f) \
367 tmp += 0x100; \
368 d.VIS_W64(r) = tmp >> 8;
369
370 PMUL(0);
371 PMUL(1);
372 PMUL(2);
373 PMUL(3);
374#undef PMUL
375
376 DT0 = d.d;
377}
378
379void helper_fmul8ulx16(void)
380{
381 vis64 s, d;
382 uint32_t tmp;
383
384 s.d = DT0;
385 d.d = DT1;
386
387#define PMUL(r) \
388 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
389 if ((tmp & 0xff) > 0x7f) \
390 tmp += 0x100; \
391 d.VIS_W64(r) = tmp >> 8;
392
393 PMUL(0);
394 PMUL(1);
395 PMUL(2);
396 PMUL(3);
397#undef PMUL
398
399 DT0 = d.d;
400}
401
402void helper_fmuld8sux16(void)
403{
404 vis64 s, d;
405 uint32_t tmp;
406
407 s.d = DT0;
408 d.d = DT1;
409
410#define PMUL(r) \
411 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
412 if ((tmp & 0xff) > 0x7f) \
413 tmp += 0x100; \
414 d.VIS_L64(r) = tmp;
415
416 // Reverse calculation order to handle overlap
417 PMUL(1);
418 PMUL(0);
419#undef PMUL
420
421 DT0 = d.d;
422}
423
424void helper_fmuld8ulx16(void)
425{
426 vis64 s, d;
427 uint32_t tmp;
428
429 s.d = DT0;
430 d.d = DT1;
431
432#define PMUL(r) \
433 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
434 if ((tmp & 0xff) > 0x7f) \
435 tmp += 0x100; \
436 d.VIS_L64(r) = tmp;
437
438 // Reverse calculation order to handle overlap
439 PMUL(1);
440 PMUL(0);
441#undef PMUL
442
443 DT0 = d.d;
444}
445
446void helper_fexpand(void)
447{
448 vis32 s;
449 vis64 d;
450
451 s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
452 d.d = DT1;
453 d.VIS_L64(0) = s.VIS_W32(0) << 4;
454 d.VIS_L64(1) = s.VIS_W32(1) << 4;
455 d.VIS_L64(2) = s.VIS_W32(2) << 4;
456 d.VIS_L64(3) = s.VIS_W32(3) << 4;
457
458 DT0 = d.d;
459}
460
461#define VIS_HELPER(name, F) \
462 void name##16(void) \
463 { \
464 vis64 s, d; \
465 \
466 s.d = DT0; \
467 d.d = DT1; \
468 \
469 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
470 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
471 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
472 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
473 \
474 DT0 = d.d; \
475 } \
476 \
1d01299d 477 uint32_t name##16s(uint32_t src1, uint32_t src2) \
44e7757c
BS		 478 { \
479 vis32 s, d; \
480 \
1d01299d
BS		 481 s.l = src1; \
482 d.l = src2; \
44e7757c
BS		 483 \
484 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
485 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
486 \
1d01299d 487 return d.l; \
44e7757c
BS		 488 } \
489 \
490 void name##32(void) \
491 { \
492 vis64 s, d; \
493 \
494 s.d = DT0; \
495 d.d = DT1; \
496 \
497 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
498 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
499 \
500 DT0 = d.d; \
501 } \
502 \
1d01299d 503 uint32_t name##32s(uint32_t src1, uint32_t src2) \
44e7757c
BS		 504 { \
505 vis32 s, d; \
506 \
1d01299d
BS		 507 s.l = src1; \
508 d.l = src2; \
44e7757c
BS		 509 \
510 d.l = F(d.l, s.l); \
511 \
1d01299d 512 return d.l; \
44e7757c
BS		 513 }
514
515#define FADD(a, b) ((a) + (b))
516#define FSUB(a, b) ((a) - (b))
517VIS_HELPER(helper_fpadd, FADD)
518VIS_HELPER(helper_fpsub, FSUB)
519
520#define VIS_CMPHELPER(name, F) \
521 void name##16(void) \
522 { \
523 vis64 s, d; \
524 \
525 s.d = DT0; \
526 d.d = DT1; \
527 \
528 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
529 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
530 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
531 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
532 \
533 DT0 = d.d; \
534 } \
535 \
536 void name##32(void) \
537 { \
538 vis64 s, d; \
539 \
540 s.d = DT0; \
541 d.d = DT1; \
542 \
543 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
544 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
545 \
546 DT0 = d.d; \
547 }
548
549#define FCMPGT(a, b) ((a) > (b))
550#define FCMPEQ(a, b) ((a) == (b))
551#define FCMPLE(a, b) ((a) <= (b))
552#define FCMPNE(a, b) ((a) != (b))
553
554VIS_CMPHELPER(helper_fcmpgt, FCMPGT)
555VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)
556VIS_CMPHELPER(helper_fcmple, FCMPLE)
557VIS_CMPHELPER(helper_fcmpne, FCMPNE)
558#endif
559
560void helper_check_ieee_exceptions(void)
561{
562 target_ulong status;
563
564 status = get_float_exception_flags(&env->fp_status);
565 if (status) {
566 /* Copy IEEE 754 flags into FSR */
567 if (status & float_flag_invalid)
568 env->fsr |= FSR_NVC;
569 if (status & float_flag_overflow)
570 env->fsr |= FSR_OFC;
571 if (status & float_flag_underflow)
572 env->fsr |= FSR_UFC;
573 if (status & float_flag_divbyzero)
574 env->fsr |= FSR_DZC;
575 if (status & float_flag_inexact)
576 env->fsr |= FSR_NXC;
577
578 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
579 /* Unmasked exception, generate a trap */
580 env->fsr |= FSR_FTT_IEEE_EXCP;
581 raise_exception(TT_FP_EXCP);
582 } else {
583 /* Accumulate exceptions */
584 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
585 }
586 }
587}
588
589void helper_clear_float_exceptions(void)
590{
591 set_float_exception_flags(0, &env->fp_status);
592}
593
714547bb 594float32 helper_fabss(float32 src)
e8af50a3 595{
714547bb 596 return float32_abs(src);
e8af50a3
FB		 597}
598
3475187d 599#ifdef TARGET_SPARC64
7e8c2b6c 600void helper_fabsd(void)
3475187d
FB		 601{
602 DT0 = float64_abs(DT1);
603}
4e14008f 604
4e14008f
BS		 605void helper_fabsq(void)
606{
607 QT0 = float128_abs(QT1);
608}
609#endif
3475187d 610
714547bb 611float32 helper_fsqrts(float32 src)
e8af50a3 612{
714547bb 613 return float32_sqrt(src, &env->fp_status);
e8af50a3
FB		 614}
615
7e8c2b6c 616void helper_fsqrtd(void)
e8af50a3 617{
7a0e1f41 618 DT0 = float64_sqrt(DT1, &env->fp_status);
e8af50a3
FB		 619}
620
4e14008f
BS		 621void helper_fsqrtq(void)
622{
623 QT0 = float128_sqrt(QT1, &env->fp_status);
624}
4e14008f 625
417454b0 626#define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
7e8c2b6c 627 void glue(helper_, name) (void) \
65ce8c2f 628 { \
1a2fb1c0
BS		 629 target_ulong new_fsr; \
630 \
65ce8c2f
FB		 631 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
632 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
633 case float_relation_unordered: \
1a2fb1c0 634 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
417454b0 635 if ((env->fsr & FSR_NVM) || TRAP) { \
1a2fb1c0 636 env->fsr |= new_fsr; \
417454b0
BS		 637 env->fsr |= FSR_NVC; \
638 env->fsr |= FSR_FTT_IEEE_EXCP; \
65ce8c2f
FB		 639 raise_exception(TT_FP_EXCP); \
640 } else { \
641 env->fsr |= FSR_NVA; \
642 } \
643 break; \
644 case float_relation_less: \
1a2fb1c0 645 new_fsr = FSR_FCC0 << FS; \
65ce8c2f
FB		 646 break; \
647 case float_relation_greater: \
1a2fb1c0 648 new_fsr = FSR_FCC1 << FS; \
65ce8c2f
FB		 649 break; \
650 default: \
1a2fb1c0 651 new_fsr = 0; \
65ce8c2f
FB		 652 break; \
653 } \
1a2fb1c0 654 env->fsr |= new_fsr; \
e8af50a3 655 }
714547bb
BS		 656#define GEN_FCMPS(name, size, FS, TRAP) \
657 void glue(helper_, name)(float32 src1, float32 src2) \
658 { \
659 target_ulong new_fsr; \
660 \
661 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
662 switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
663 case float_relation_unordered: \
664 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
665 if ((env->fsr & FSR_NVM) || TRAP) { \
666 env->fsr |= new_fsr; \
667 env->fsr |= FSR_NVC; \
668 env->fsr |= FSR_FTT_IEEE_EXCP; \
669 raise_exception(TT_FP_EXCP); \
670 } else { \
671 env->fsr |= FSR_NVA; \
672 } \
673 break; \
674 case float_relation_less: \
675 new_fsr = FSR_FCC0 << FS; \
676 break; \
677 case float_relation_greater: \
678 new_fsr = FSR_FCC1 << FS; \
679 break; \
680 default: \
681 new_fsr = 0; \
682 break; \
683 } \
684 env->fsr |= new_fsr; \
685 }
e8af50a3 686
714547bb 687GEN_FCMPS(fcmps, float32, 0, 0);
417454b0
BS		 688GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
689
714547bb 690GEN_FCMPS(fcmpes, float32, 0, 1);
417454b0 691GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
3475187d 692
4e14008f
BS		 693GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
694GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
4e14008f 695
3475187d 696#ifdef TARGET_SPARC64
714547bb 697GEN_FCMPS(fcmps_fcc1, float32, 22, 0);
417454b0 698GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
64a88d5d 699GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
417454b0 700
714547bb 701GEN_FCMPS(fcmps_fcc2, float32, 24, 0);
417454b0 702GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
64a88d5d 703GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
417454b0 704
714547bb 705GEN_FCMPS(fcmps_fcc3, float32, 26, 0);
417454b0 706GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
64a88d5d 707GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
417454b0 708
714547bb 709GEN_FCMPS(fcmpes_fcc1, float32, 22, 1);
417454b0 710GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
64a88d5d 711GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
3475187d 712
714547bb 713GEN_FCMPS(fcmpes_fcc2, float32, 24, 1);
417454b0 714GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
64a88d5d 715GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
3475187d 716
714547bb 717GEN_FCMPS(fcmpes_fcc3, float32, 26, 1);
417454b0 718GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
4e14008f
BS		 719GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
720#endif
714547bb 721#undef GEN_FCMPS
3475187d 722
77f193da
BS		 723#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
724 defined(DEBUG_MXCC)
952a328f
BS		 725static void dump_mxcc(CPUState *env)
726{
727 printf("mxccdata: %016llx %016llx %016llx %016llx\n",
77f193da
BS		 728 env->mxccdata[0], env->mxccdata[1],
729 env->mxccdata[2], env->mxccdata[3]);
952a328f
BS		 730 printf("mxccregs: %016llx %016llx %016llx %016llx\n"
731 " %016llx %016llx %016llx %016llx\n",
77f193da
BS		 732 env->mxccregs[0], env->mxccregs[1],
733 env->mxccregs[2], env->mxccregs[3],
734 env->mxccregs[4], env->mxccregs[5],
735 env->mxccregs[6], env->mxccregs[7]);
952a328f
BS		 736}
737#endif
738
1a2fb1c0
BS		 739#if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
740 && defined(DEBUG_ASI)
741static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
742 uint64_t r1)
8543e2cf
BS		 743{
744 switch (size)
745 {
746 case 1:
1a2fb1c0
BS		 747 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
748 addr, asi, r1 & 0xff);
8543e2cf
BS		 749 break;
750 case 2:
1a2fb1c0
BS		 751 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
752 addr, asi, r1 & 0xffff);
8543e2cf
BS		 753 break;
754 case 4:
1a2fb1c0
BS		 755 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
756 addr, asi, r1 & 0xffffffff);
8543e2cf
BS		 757 break;
758 case 8:
1a2fb1c0
BS		 759 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
760 addr, asi, r1);
8543e2cf
BS		 761 break;
762 }
763}
764#endif
765
1a2fb1c0
BS		 766#ifndef TARGET_SPARC64
767#ifndef CONFIG_USER_ONLY
768uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
e8af50a3 769{
1a2fb1c0 770 uint64_t ret = 0;
8543e2cf 771#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
1a2fb1c0 772 uint32_t last_addr = addr;
952a328f 773#endif
e80cfcfc 774
c2bc0e38 775 helper_check_align(addr, size - 1);
e80cfcfc 776 switch (asi) {
6c36d3fa 777 case 2: /* SuperSparc MXCC registers */
1a2fb1c0 778 switch (addr) {
952a328f 779 case 0x01c00a00: /* MXCC control register */
1a2fb1c0
BS		 780 if (size == 8)
781 ret = env->mxccregs[3];
782 else
77f193da
BS		 783 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
784 size);
952a328f
BS		 785 break;
786 case 0x01c00a04: /* MXCC control register */
787 if (size == 4)
788 ret = env->mxccregs[3];
789 else
77f193da
BS		 790 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
791 size);
952a328f 792 break;
295db113
BS		 793 case 0x01c00c00: /* Module reset register */
794 if (size == 8) {
1a2fb1c0 795 ret = env->mxccregs[5];
295db113
BS		 796 // should we do something here?
797 } else
77f193da
BS		 798 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
799 size);
295db113 800 break;
952a328f 801 case 0x01c00f00: /* MBus port address register */
1a2fb1c0
BS		 802 if (size == 8)
803 ret = env->mxccregs[7];
804 else
77f193da
BS		 805 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
806 size);
952a328f
BS		 807 break;
808 default:
77f193da
BS		 809 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
810 size);
952a328f
BS		 811 break;
812 }
77f193da 813 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
9827e450 814 "addr = %08x -> ret = %" PRIx64 ","
1a2fb1c0 815 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
952a328f
BS		 816#ifdef DEBUG_MXCC
817 dump_mxcc(env);
818#endif
6c36d3fa 819 break;
e8af50a3 820 case 3: /* MMU probe */
0f8a249a
BS		 821 {
822 int mmulev;
823
1a2fb1c0 824 mmulev = (addr >> 8) & 15;
0f8a249a
BS		 825 if (mmulev > 4)
826 ret = 0;
1a2fb1c0
BS		 827 else
828 ret = mmu_probe(env, addr, mmulev);
829 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
830 addr, mmulev, ret);
0f8a249a
BS		 831 }
832 break;
e8af50a3 833 case 4: /* read MMU regs */
0f8a249a 834 {
1a2fb1c0 835 int reg = (addr >> 8) & 0x1f;
3b46e624 836
0f8a249a
BS		 837 ret = env->mmuregs[reg];
838 if (reg == 3) /* Fault status cleared on read */
3dd9a152
BS		 839 env->mmuregs[3] = 0;
840 else if (reg == 0x13) /* Fault status read */
841 ret = env->mmuregs[3];
842 else if (reg == 0x14) /* Fault address read */
843 ret = env->mmuregs[4];
1a2fb1c0 844 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
0f8a249a
BS		 845 }
846 break;
045380be
BS		 847 case 5: // Turbosparc ITLB Diagnostic
848 case 6: // Turbosparc DTLB Diagnostic
849 case 7: // Turbosparc IOTLB Diagnostic
850 break;
6c36d3fa
BS		 851 case 9: /* Supervisor code access */
852 switch(size) {
853 case 1:
1a2fb1c0 854 ret = ldub_code(addr);
6c36d3fa
BS		 855 break;
856 case 2:
a4e7dd52 857 ret = lduw_code(addr);
6c36d3fa
BS		 858 break;
859 default:
860 case 4:
a4e7dd52 861 ret = ldl_code(addr);
6c36d3fa
BS		 862 break;
863 case 8:
a4e7dd52 864 ret = ldq_code(addr);
6c36d3fa
BS		 865 break;
866 }
867 break;
81ad8ba2
BS		 868 case 0xa: /* User data access */
869 switch(size) {
870 case 1:
1a2fb1c0 871 ret = ldub_user(addr);
81ad8ba2
BS		 872 break;
873 case 2:
a4e7dd52 874 ret = lduw_user(addr);
81ad8ba2
BS		 875 break;
876 default:
877 case 4:
a4e7dd52 878 ret = ldl_user(addr);
81ad8ba2
BS		 879 break;
880 case 8:
a4e7dd52 881 ret = ldq_user(addr);
81ad8ba2
BS		 882 break;
883 }
884 break;
885 case 0xb: /* Supervisor data access */
886 switch(size) {
887 case 1:
1a2fb1c0 888 ret = ldub_kernel(addr);
81ad8ba2
BS		 889 break;
890 case 2:
a4e7dd52 891 ret = lduw_kernel(addr);
81ad8ba2
BS		 892 break;
893 default:
894 case 4:
a4e7dd52 895 ret = ldl_kernel(addr);
81ad8ba2
BS		 896 break;
897 case 8:
a4e7dd52 898 ret = ldq_kernel(addr);
81ad8ba2
BS		 899 break;
900 }
901 break;
6c36d3fa
BS		 902 case 0xc: /* I-cache tag */
903 case 0xd: /* I-cache data */
904 case 0xe: /* D-cache tag */
905 case 0xf: /* D-cache data */
906 break;
907 case 0x20: /* MMU passthrough */
02aab46a
FB		 908 switch(size) {
909 case 1:
1a2fb1c0 910 ret = ldub_phys(addr);
02aab46a
FB		 911 break;
912 case 2:
a4e7dd52 913 ret = lduw_phys(addr);
02aab46a
FB		 914 break;
915 default:
916 case 4:
a4e7dd52 917 ret = ldl_phys(addr);
02aab46a 918 break;
9e61bde5 919 case 8:
a4e7dd52 920 ret = ldq_phys(addr);
0f8a249a 921 break;
02aab46a 922 }
0f8a249a 923 break;
7d85892b 924 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
5dcb6b91
BS		 925 switch(size) {
926 case 1:
1a2fb1c0 927 ret = ldub_phys((target_phys_addr_t)addr
5dcb6b91
BS		 928 | ((target_phys_addr_t)(asi & 0xf) << 32));
929 break;
930 case 2:
a4e7dd52 931 ret = lduw_phys((target_phys_addr_t)addr
5dcb6b91
BS		 932 | ((target_phys_addr_t)(asi & 0xf) << 32));
933 break;
934 default:
935 case 4:
a4e7dd52 936 ret = ldl_phys((target_phys_addr_t)addr
5dcb6b91
BS		 937 | ((target_phys_addr_t)(asi & 0xf) << 32));
938 break;
939 case 8:
a4e7dd52 940 ret = ldq_phys((target_phys_addr_t)addr
5dcb6b91 941 | ((target_phys_addr_t)(asi & 0xf) << 32));
0f8a249a 942 break;
5dcb6b91 943 }
0f8a249a 944 break;
045380be
BS		 945 case 0x30: // Turbosparc secondary cache diagnostic
946 case 0x31: // Turbosparc RAM snoop
947 case 0x32: // Turbosparc page table descriptor diagnostic
666c87aa
BS		 948 case 0x39: /* data cache diagnostic register */
949 ret = 0;
950 break;
045380be 951 case 8: /* User code access, XXX */
e8af50a3 952 default:
1a2fb1c0 953 do_unassigned_access(addr, 0, 0, asi);
0f8a249a
BS		 954 ret = 0;
955 break;
e8af50a3 956 }
81ad8ba2
BS		 957 if (sign) {
958 switch(size) {
959 case 1:
1a2fb1c0 960 ret = (int8_t) ret;
e32664fb 961 break;
81ad8ba2 962 case 2:
1a2fb1c0
BS		 963 ret = (int16_t) ret;
964 break;
965 case 4:
966 ret = (int32_t) ret;
e32664fb 967 break;
81ad8ba2 968 default:
81ad8ba2
BS		 969 break;
970 }
971 }
8543e2cf 972#ifdef DEBUG_ASI
1a2fb1c0 973 dump_asi("read ", last_addr, asi, size, ret);
8543e2cf 974#endif
1a2fb1c0 975 return ret;
e8af50a3
FB		 976}
977
1a2fb1c0 978void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
e8af50a3 979{
c2bc0e38 980 helper_check_align(addr, size - 1);
e8af50a3 981 switch(asi) {
6c36d3fa 982 case 2: /* SuperSparc MXCC registers */
1a2fb1c0 983 switch (addr) {
952a328f
BS		 984 case 0x01c00000: /* MXCC stream data register 0 */
985 if (size == 8)
1a2fb1c0 986 env->mxccdata[0] = val;
952a328f 987 else
77f193da
BS		 988 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
989 size);
952a328f
BS		 990 break;
991 case 0x01c00008: /* MXCC stream data register 1 */
992 if (size == 8)
1a2fb1c0 993 env->mxccdata[1] = val;
952a328f 994 else
77f193da
BS		 995 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
996 size);
952a328f
BS		 997 break;
998 case 0x01c00010: /* MXCC stream data register 2 */
999 if (size == 8)
1a2fb1c0 1000 env->mxccdata[2] = val;
952a328f 1001 else
77f193da
BS		 1002 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1003 size);
952a328f
BS		 1004 break;
1005 case 0x01c00018: /* MXCC stream data register 3 */
1006 if (size == 8)
1a2fb1c0 1007 env->mxccdata[3] = val;
952a328f 1008 else
77f193da
BS		 1009 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1010 size);
952a328f
BS		 1011 break;
1012 case 0x01c00100: /* MXCC stream source */
1013 if (size == 8)
1a2fb1c0 1014 env->mxccregs[0] = val;
952a328f 1015 else
77f193da
BS		 1016 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1017 size);
1018 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1019 0);
1020 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1021 8);
1022 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1023 16);
1024 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1025 24);
952a328f
BS		 1026 break;
1027 case 0x01c00200: /* MXCC stream destination */
1028 if (size == 8)
1a2fb1c0 1029 env->mxccregs[1] = val;
952a328f 1030 else
77f193da
BS		 1031 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1032 size);
1033 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0,
1034 env->mxccdata[0]);
1035 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8,
1036 env->mxccdata[1]);
1037 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
1038 env->mxccdata[2]);
1039 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
1040 env->mxccdata[3]);
952a328f
BS		 1041 break;
1042 case 0x01c00a00: /* MXCC control register */
1043 if (size == 8)
1a2fb1c0 1044 env->mxccregs[3] = val;
952a328f 1045 else
77f193da
BS		 1046 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1047 size);
952a328f
BS		 1048 break;
1049 case 0x01c00a04: /* MXCC control register */
1050 if (size == 4)
9f4576f0 1051 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
77f193da 1052 | val;
952a328f 1053 else
77f193da
BS		 1054 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1055 size);
952a328f
BS		 1056 break;
1057 case 0x01c00e00: /* MXCC error register */
bbf7d96b 1058 // writing a 1 bit clears the error
952a328f 1059 if (size == 8)
1a2fb1c0 1060 env->mxccregs[6] &= ~val;
952a328f 1061 else
77f193da
BS		 1062 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1063 size);
952a328f
BS		 1064 break;
1065 case 0x01c00f00: /* MBus port address register */
1066 if (size == 8)
1a2fb1c0 1067 env->mxccregs[7] = val;
952a328f 1068 else
77f193da
BS		 1069 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1070 size);
952a328f
BS		 1071 break;
1072 default:
77f193da
BS		 1073 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
1074 size);
952a328f
BS		 1075 break;
1076 }
9827e450
BS		 1077 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
1078 asi, size, addr, val);
952a328f
BS		 1079#ifdef DEBUG_MXCC
1080 dump_mxcc(env);
1081#endif
6c36d3fa 1082 break;
e8af50a3 1083 case 3: /* MMU flush */
0f8a249a
BS		 1084 {
1085 int mmulev;
e80cfcfc 1086
1a2fb1c0 1087 mmulev = (addr >> 8) & 15;
952a328f 1088 DPRINTF_MMU("mmu flush level %d\n", mmulev);
0f8a249a
BS		 1089 switch (mmulev) {
1090 case 0: // flush page
1a2fb1c0 1091 tlb_flush_page(env, addr & 0xfffff000);
0f8a249a
BS		 1092 break;
1093 case 1: // flush segment (256k)
1094 case 2: // flush region (16M)
1095 case 3: // flush context (4G)
1096 case 4: // flush entire
1097 tlb_flush(env, 1);
1098 break;
1099 default:
1100 break;
1101 }
55754d9e 1102#ifdef DEBUG_MMU
0f8a249a 1103 dump_mmu(env);
55754d9e 1104#endif
0f8a249a 1105 }
8543e2cf 1106 break;
e8af50a3 1107 case 4: /* write MMU regs */
0f8a249a 1108 {
1a2fb1c0 1109 int reg = (addr >> 8) & 0x1f;
0f8a249a 1110 uint32_t oldreg;
3b46e624 1111
0f8a249a 1112 oldreg = env->mmuregs[reg];
55754d9e 1113 switch(reg) {
3deaeab7 1114 case 0: // Control Register
3dd9a152 1115 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
1a2fb1c0 1116 (val & 0x00ffffff);
0f8a249a
BS		 1117 // Mappings generated during no-fault mode or MMU
1118 // disabled mode are invalid in normal mode
5578ceab
BS		 1119 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
1120 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm)))
55754d9e
FB		 1121 tlb_flush(env, 1);
1122 break;
3deaeab7 1123 case 1: // Context Table Pointer Register
5578ceab 1124 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
3deaeab7
BS		 1125 break;
1126 case 2: // Context Register
5578ceab 1127 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
55754d9e
FB		 1128 if (oldreg != env->mmuregs[reg]) {
1129 /* we flush when the MMU context changes because
1130 QEMU has no MMU context support */
1131 tlb_flush(env, 1);
1132 }
1133 break;
3deaeab7
BS		 1134 case 3: // Synchronous Fault Status Register with Clear
1135 case 4: // Synchronous Fault Address Register
1136 break;
1137 case 0x10: // TLB Replacement Control Register
5578ceab 1138 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
55754d9e 1139 break;
3deaeab7 1140 case 0x13: // Synchronous Fault Status Register with Read and Clear
5578ceab 1141 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
3dd9a152 1142 break;
3deaeab7 1143 case 0x14: // Synchronous Fault Address Register
1a2fb1c0 1144 env->mmuregs[4] = val;
3dd9a152 1145 break;
55754d9e 1146 default:
1a2fb1c0 1147 env->mmuregs[reg] = val;
55754d9e
FB		 1148 break;
1149 }
55754d9e 1150 if (oldreg != env->mmuregs[reg]) {
77f193da
BS		 1151 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1152 reg, oldreg, env->mmuregs[reg]);
55754d9e 1153 }
952a328f 1154#ifdef DEBUG_MMU
0f8a249a 1155 dump_mmu(env);
55754d9e 1156#endif
0f8a249a 1157 }
8543e2cf 1158 break;
045380be
BS		 1159 case 5: // Turbosparc ITLB Diagnostic
1160 case 6: // Turbosparc DTLB Diagnostic
1161 case 7: // Turbosparc IOTLB Diagnostic
1162 break;
81ad8ba2
BS		 1163 case 0xa: /* User data access */
1164 switch(size) {
1165 case 1:
1a2fb1c0 1166 stb_user(addr, val);
81ad8ba2
BS		 1167 break;
1168 case 2:
a4e7dd52 1169 stw_user(addr, val);
81ad8ba2
BS		 1170 break;
1171 default:
1172 case 4:
a4e7dd52 1173 stl_user(addr, val);
81ad8ba2
BS		 1174 break;
1175 case 8:
a4e7dd52 1176 stq_user(addr, val);
81ad8ba2
BS		 1177 break;
1178 }
1179 break;
1180 case 0xb: /* Supervisor data access */
1181 switch(size) {
1182 case 1:
1a2fb1c0 1183 stb_kernel(addr, val);
81ad8ba2
BS		 1184 break;
1185 case 2:
a4e7dd52 1186 stw_kernel(addr, val);
81ad8ba2
BS		 1187 break;
1188 default:
1189 case 4:
a4e7dd52 1190 stl_kernel(addr, val);
81ad8ba2
BS		 1191 break;
1192 case 8:
a4e7dd52 1193 stq_kernel(addr, val);
81ad8ba2
BS		 1194 break;
1195 }
1196 break;
6c36d3fa
BS		 1197 case 0xc: /* I-cache tag */
1198 case 0xd: /* I-cache data */
1199 case 0xe: /* D-cache tag */
1200 case 0xf: /* D-cache data */
1201 case 0x10: /* I/D-cache flush page */
1202 case 0x11: /* I/D-cache flush segment */
1203 case 0x12: /* I/D-cache flush region */
1204 case 0x13: /* I/D-cache flush context */
1205 case 0x14: /* I/D-cache flush user */
1206 break;
e80cfcfc 1207 case 0x17: /* Block copy, sta access */
0f8a249a 1208 {
1a2fb1c0
BS		 1209 // val = src
1210 // addr = dst
0f8a249a 1211 // copy 32 bytes
6c36d3fa 1212 unsigned int i;
1a2fb1c0 1213 uint32_t src = val & ~3, dst = addr & ~3, temp;
3b46e624 1214
6c36d3fa
BS		 1215 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
1216 temp = ldl_kernel(src);
1217 stl_kernel(dst, temp);
1218 }
0f8a249a 1219 }
8543e2cf 1220 break;
e80cfcfc 1221 case 0x1f: /* Block fill, stda access */
0f8a249a 1222 {
1a2fb1c0
BS		 1223 // addr = dst
1224 // fill 32 bytes with val
6c36d3fa 1225 unsigned int i;
1a2fb1c0 1226 uint32_t dst = addr & 7;
6c36d3fa
BS		 1227
1228 for (i = 0; i < 32; i += 8, dst += 8)
1229 stq_kernel(dst, val);
0f8a249a 1230 }
8543e2cf 1231 break;
6c36d3fa 1232 case 0x20: /* MMU passthrough */
0f8a249a 1233 {
02aab46a
FB		 1234 switch(size) {
1235 case 1:
1a2fb1c0 1236 stb_phys(addr, val);
02aab46a
FB		 1237 break;
1238 case 2:
a4e7dd52 1239 stw_phys(addr, val);
02aab46a
FB		 1240 break;
1241 case 4:
1242 default:
a4e7dd52 1243 stl_phys(addr, val);
02aab46a 1244 break;
9e61bde5 1245 case 8:
a4e7dd52 1246 stq_phys(addr, val);
9e61bde5 1247 break;
02aab46a 1248 }
0f8a249a 1249 }
8543e2cf 1250 break;
045380be 1251 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
0f8a249a 1252 {
5dcb6b91
BS		 1253 switch(size) {
1254 case 1:
1a2fb1c0
BS		 1255 stb_phys((target_phys_addr_t)addr
1256 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1257 break;
1258 case 2:
a4e7dd52 1259 stw_phys((target_phys_addr_t)addr
1a2fb1c0 1260 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1261 break;
1262 case 4:
1263 default:
a4e7dd52 1264 stl_phys((target_phys_addr_t)addr
1a2fb1c0 1265 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1266 break;
1267 case 8:
a4e7dd52 1268 stq_phys((target_phys_addr_t)addr
1a2fb1c0 1269 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1270 break;
1271 }
0f8a249a 1272 }
8543e2cf 1273 break;
045380be
BS		 1274 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
1275 case 0x31: // store buffer data, Ross RT620 I-cache flush or
1276 // Turbosparc snoop RAM
77f193da
BS		 1277 case 0x32: // store buffer control or Turbosparc page table
1278 // descriptor diagnostic
6c36d3fa
BS		 1279 case 0x36: /* I-cache flash clear */
1280 case 0x37: /* D-cache flash clear */
666c87aa
BS		 1281 case 0x38: /* breakpoint diagnostics */
1282 case 0x4c: /* breakpoint action */
6c36d3fa 1283 break;
045380be 1284 case 8: /* User code access, XXX */
6c36d3fa 1285 case 9: /* Supervisor code access, XXX */
e8af50a3 1286 default:
1a2fb1c0 1287 do_unassigned_access(addr, 1, 0, asi);
8543e2cf 1288 break;
e8af50a3 1289 }
8543e2cf 1290#ifdef DEBUG_ASI
1a2fb1c0 1291 dump_asi("write", addr, asi, size, val);
8543e2cf 1292#endif
e8af50a3
FB		 1293}
1294
81ad8ba2
BS		 1295#endif /* CONFIG_USER_ONLY */
1296#else /* TARGET_SPARC64 */
1297
1298#ifdef CONFIG_USER_ONLY
1a2fb1c0 1299uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
81ad8ba2
BS		 1300{
1301 uint64_t ret = 0;
1a2fb1c0
BS		 1302#if defined(DEBUG_ASI)
1303 target_ulong last_addr = addr;
1304#endif
81ad8ba2
BS		 1305
1306 if (asi < 0x80)
1307 raise_exception(TT_PRIV_ACT);
1308
c2bc0e38 1309 helper_check_align(addr, size - 1);
2cade6a3 1310 address_mask(env, &addr);
c2bc0e38 1311
81ad8ba2 1312 switch (asi) {
81ad8ba2 1313 case 0x82: // Primary no-fault
81ad8ba2 1314 case 0x8a: // Primary no-fault LE
e83ce550
BS		 1315 if (page_check_range(addr, size, PAGE_READ) == -1) {
1316#ifdef DEBUG_ASI
1317 dump_asi("read ", last_addr, asi, size, ret);
1318#endif
1319 return 0;
1320 }
1321 // Fall through
1322 case 0x80: // Primary
1323 case 0x88: // Primary LE
81ad8ba2
BS		 1324 {
1325 switch(size) {
1326 case 1:
1a2fb1c0 1327 ret = ldub_raw(addr);
81ad8ba2
BS		 1328 break;
1329 case 2:
a4e7dd52 1330 ret = lduw_raw(addr);
81ad8ba2
BS		 1331 break;
1332 case 4:
a4e7dd52 1333 ret = ldl_raw(addr);
81ad8ba2
BS		 1334 break;
1335 default:
1336 case 8:
a4e7dd52 1337 ret = ldq_raw(addr);
81ad8ba2
BS		 1338 break;
1339 }
1340 }
1341 break;
81ad8ba2 1342 case 0x83: // Secondary no-fault
81ad8ba2 1343 case 0x8b: // Secondary no-fault LE
e83ce550
BS		 1344 if (page_check_range(addr, size, PAGE_READ) == -1) {
1345#ifdef DEBUG_ASI
1346 dump_asi("read ", last_addr, asi, size, ret);
1347#endif
1348 return 0;
1349 }
1350 // Fall through
1351 case 0x81: // Secondary
1352 case 0x89: // Secondary LE
81ad8ba2
BS		 1353 // XXX
1354 break;
1355 default:
1356 break;
1357 }
1358
1359 /* Convert from little endian */
1360 switch (asi) {
1361 case 0x88: // Primary LE
1362 case 0x89: // Secondary LE
1363 case 0x8a: // Primary no-fault LE
1364 case 0x8b: // Secondary no-fault LE
1365 switch(size) {
1366 case 2:
1367 ret = bswap16(ret);
e32664fb 1368 break;
81ad8ba2
BS		 1369 case 4:
1370 ret = bswap32(ret);
e32664fb 1371 break;
81ad8ba2
BS		 1372 case 8:
1373 ret = bswap64(ret);
e32664fb 1374 break;
81ad8ba2
BS		 1375 default:
1376 break;
1377 }
1378 default:
1379 break;
1380 }
1381
1382 /* Convert to signed number */
1383 if (sign) {
1384 switch(size) {
1385 case 1:
1386 ret = (int8_t) ret;
e32664fb 1387 break;
81ad8ba2
BS		 1388 case 2:
1389 ret = (int16_t) ret;
e32664fb 1390 break;
81ad8ba2
BS		 1391 case 4:
1392 ret = (int32_t) ret;
e32664fb 1393 break;
81ad8ba2
BS		 1394 default:
1395 break;
1396 }
1397 }
1a2fb1c0
BS		 1398#ifdef DEBUG_ASI
1399 dump_asi("read ", last_addr, asi, size, ret);
1400#endif
1401 return ret;
81ad8ba2
BS		 1402}
1403
1a2fb1c0 1404void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
81ad8ba2 1405{
1a2fb1c0
BS		 1406#ifdef DEBUG_ASI
1407 dump_asi("write", addr, asi, size, val);
1408#endif
81ad8ba2
BS		 1409 if (asi < 0x80)
1410 raise_exception(TT_PRIV_ACT);
1411
c2bc0e38 1412 helper_check_align(addr, size - 1);
2cade6a3 1413 address_mask(env, &addr);
c2bc0e38 1414
81ad8ba2
BS		 1415 /* Convert to little endian */
1416 switch (asi) {
1417 case 0x88: // Primary LE
1418 case 0x89: // Secondary LE
1419 switch(size) {
1420 case 2:
1a2fb1c0 1421 addr = bswap16(addr);
e32664fb 1422 break;
81ad8ba2 1423 case 4:
1a2fb1c0 1424 addr = bswap32(addr);
e32664fb 1425 break;
81ad8ba2 1426 case 8:
1a2fb1c0 1427 addr = bswap64(addr);
e32664fb 1428 break;
81ad8ba2
BS		 1429 default:
1430 break;
1431 }
1432 default:
1433 break;
1434 }
1435
1436 switch(asi) {
1437 case 0x80: // Primary
1438 case 0x88: // Primary LE
1439 {
1440 switch(size) {
1441 case 1:
1a2fb1c0 1442 stb_raw(addr, val);
81ad8ba2
BS		 1443 break;
1444 case 2:
a4e7dd52 1445 stw_raw(addr, val);
81ad8ba2
BS		 1446 break;
1447 case 4:
a4e7dd52 1448 stl_raw(addr, val);
81ad8ba2
BS		 1449 break;
1450 case 8:
1451 default:
a4e7dd52 1452 stq_raw(addr, val);
81ad8ba2
BS		 1453 break;
1454 }
1455 }
1456 break;
1457 case 0x81: // Secondary
1458 case 0x89: // Secondary LE
1459 // XXX
1460 return;
1461
1462 case 0x82: // Primary no-fault, RO
1463 case 0x83: // Secondary no-fault, RO
1464 case 0x8a: // Primary no-fault LE, RO
1465 case 0x8b: // Secondary no-fault LE, RO
1466 default:
1a2fb1c0 1467 do_unassigned_access(addr, 1, 0, 1);
81ad8ba2
BS		 1468 return;
1469 }
1470}
1471
1472#else /* CONFIG_USER_ONLY */
3475187d 1473
1a2fb1c0 1474uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
3475187d 1475{
83469015 1476 uint64_t ret = 0;
1a2fb1c0
BS		 1477#if defined(DEBUG_ASI)
1478 target_ulong last_addr = addr;
1479#endif
3475187d 1480
6f27aba6 1481 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
5578ceab
BS		 1482 || ((env->def->features & CPU_FEATURE_HYPV)
1483 && asi >= 0x30 && asi < 0x80
fb79ceb9 1484 && !(env->hpstate & HS_PRIV)))
0f8a249a 1485 raise_exception(TT_PRIV_ACT);
3475187d 1486
c2bc0e38 1487 helper_check_align(addr, size - 1);
3475187d 1488 switch (asi) {
e83ce550
BS		 1489 case 0x82: // Primary no-fault
1490 case 0x8a: // Primary no-fault LE
1491 if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
1492#ifdef DEBUG_ASI
1493 dump_asi("read ", last_addr, asi, size, ret);
1494#endif
1495 return 0;
1496 }
1497 // Fall through
81ad8ba2
BS		 1498 case 0x10: // As if user primary
1499 case 0x18: // As if user primary LE
1500 case 0x80: // Primary
81ad8ba2 1501 case 0x88: // Primary LE
c99657d3
BS		 1502 case 0xe2: // UA2007 Primary block init
1503 case 0xe3: // UA2007 Secondary block init
81ad8ba2 1504 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
5578ceab
BS		 1505 if ((env->def->features & CPU_FEATURE_HYPV)
1506 && env->hpstate & HS_PRIV) {
6f27aba6
BS		 1507 switch(size) {
1508 case 1:
1a2fb1c0 1509 ret = ldub_hypv(addr);
6f27aba6
BS		 1510 break;
1511 case 2:
a4e7dd52 1512 ret = lduw_hypv(addr);
6f27aba6
BS		 1513 break;
1514 case 4:
a4e7dd52 1515 ret = ldl_hypv(addr);
6f27aba6
BS		 1516 break;
1517 default:
1518 case 8:
a4e7dd52 1519 ret = ldq_hypv(addr);
6f27aba6
BS		 1520 break;
1521 }
1522 } else {
1523 switch(size) {
1524 case 1:
1a2fb1c0 1525 ret = ldub_kernel(addr);
6f27aba6
BS		 1526 break;
1527 case 2:
a4e7dd52 1528 ret = lduw_kernel(addr);
6f27aba6
BS		 1529 break;
1530 case 4:
a4e7dd52 1531 ret = ldl_kernel(addr);
6f27aba6
BS		 1532 break;
1533 default:
1534 case 8:
a4e7dd52 1535 ret = ldq_kernel(addr);
6f27aba6
BS		 1536 break;
1537 }
81ad8ba2
BS		 1538 }
1539 } else {
1540 switch(size) {
1541 case 1:
1a2fb1c0 1542 ret = ldub_user(addr);
81ad8ba2
BS		 1543 break;
1544 case 2:
a4e7dd52 1545 ret = lduw_user(addr);
81ad8ba2
BS		 1546 break;
1547 case 4:
a4e7dd52 1548 ret = ldl_user(addr);
81ad8ba2
BS		 1549 break;
1550 default:
1551 case 8:
a4e7dd52 1552 ret = ldq_user(addr);
81ad8ba2
BS		 1553 break;
1554 }
1555 }
1556 break;
3475187d
FB		 1557 case 0x14: // Bypass
1558 case 0x15: // Bypass, non-cacheable
81ad8ba2
BS		 1559 case 0x1c: // Bypass LE
1560 case 0x1d: // Bypass, non-cacheable LE
0f8a249a 1561 {
02aab46a
FB		 1562 switch(size) {
1563 case 1:
1a2fb1c0 1564 ret = ldub_phys(addr);
02aab46a
FB		 1565 break;
1566 case 2:
a4e7dd52 1567 ret = lduw_phys(addr);
02aab46a
FB		 1568 break;
1569 case 4:
a4e7dd52 1570 ret = ldl_phys(addr);
02aab46a
FB		 1571 break;
1572 default:
1573 case 8:
a4e7dd52 1574 ret = ldq_phys(addr);
02aab46a
FB		 1575 break;
1576 }
0f8a249a
BS		 1577 break;
1578 }
db166940
BS		 1579 case 0x24: // Nucleus quad LDD 128 bit atomic
1580 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
1581 // Only ldda allowed
1582 raise_exception(TT_ILL_INSN);
1583 return 0;
e83ce550
BS		 1584 case 0x83: // Secondary no-fault
1585 case 0x8b: // Secondary no-fault LE
1586 if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
1587#ifdef DEBUG_ASI
1588 dump_asi("read ", last_addr, asi, size, ret);
1589#endif
1590 return 0;
1591 }
1592 // Fall through
83469015
FB		 1593 case 0x04: // Nucleus
1594 case 0x0c: // Nucleus Little Endian (LE)
83469015 1595 case 0x11: // As if user secondary
83469015 1596 case 0x19: // As if user secondary LE
83469015 1597 case 0x4a: // UPA config
81ad8ba2 1598 case 0x81: // Secondary
83469015 1599 case 0x89: // Secondary LE
0f8a249a
BS		 1600 // XXX
1601 break;
3475187d 1602 case 0x45: // LSU
0f8a249a
BS		 1603 ret = env->lsu;
1604 break;
3475187d 1605 case 0x50: // I-MMU regs
0f8a249a 1606 {
1a2fb1c0 1607 int reg = (addr >> 3) & 0xf;
3475187d 1608
0f8a249a
BS		 1609 ret = env->immuregs[reg];
1610 break;
1611 }
3475187d
FB		 1612 case 0x51: // I-MMU 8k TSB pointer
1613 case 0x52: // I-MMU 64k TSB pointer
0f8a249a
BS		 1614 // XXX
1615 break;
a5a52cf2
BS		 1616 case 0x55: // I-MMU data access
1617 {
1618 int reg = (addr >> 3) & 0x3f;
1619
1620 ret = env->itlb_tte[reg];
1621 break;
1622 }
83469015 1623 case 0x56: // I-MMU tag read
0f8a249a 1624 {
43e9e742 1625 int reg = (addr >> 3) & 0x3f;
0f8a249a 1626
43e9e742 1627 ret = env->itlb_tag[reg];
0f8a249a
BS		 1628 break;
1629 }
3475187d 1630 case 0x58: // D-MMU regs
0f8a249a 1631 {
1a2fb1c0 1632 int reg = (addr >> 3) & 0xf;
3475187d 1633
0f8a249a
BS		 1634 ret = env->dmmuregs[reg];
1635 break;
1636 }
a5a52cf2
BS		 1637 case 0x5d: // D-MMU data access
1638 {
1639 int reg = (addr >> 3) & 0x3f;
1640
1641 ret = env->dtlb_tte[reg];
1642 break;
1643 }
83469015 1644 case 0x5e: // D-MMU tag read
0f8a249a 1645 {
43e9e742 1646 int reg = (addr >> 3) & 0x3f;
0f8a249a 1647
43e9e742 1648 ret = env->dtlb_tag[reg];
0f8a249a
BS		 1649 break;
1650 }
f7350b47
BS		 1651 case 0x46: // D-cache data
1652 case 0x47: // D-cache tag access
a5a52cf2
BS		 1653 case 0x4b: // E-cache error enable
1654 case 0x4c: // E-cache asynchronous fault status
1655 case 0x4d: // E-cache asynchronous fault address
f7350b47
BS		 1656 case 0x4e: // E-cache tag data
1657 case 0x66: // I-cache instruction access
1658 case 0x67: // I-cache tag access
1659 case 0x6e: // I-cache predecode
1660 case 0x6f: // I-cache LRU etc.
1661 case 0x76: // E-cache tag
1662 case 0x7e: // E-cache tag
1663 break;
3475187d
FB		 1664 case 0x59: // D-MMU 8k TSB pointer
1665 case 0x5a: // D-MMU 64k TSB pointer
1666 case 0x5b: // D-MMU data pointer
83469015
FB		 1667 case 0x48: // Interrupt dispatch, RO
1668 case 0x49: // Interrupt data receive
1669 case 0x7f: // Incoming interrupt vector, RO
0f8a249a
BS		 1670 // XXX
1671 break;
3475187d
FB		 1672 case 0x54: // I-MMU data in, WO
1673 case 0x57: // I-MMU demap, WO
1674 case 0x5c: // D-MMU data in, WO
1675 case 0x5f: // D-MMU demap, WO
83469015 1676 case 0x77: // Interrupt vector, WO
3475187d 1677 default:
1a2fb1c0 1678 do_unassigned_access(addr, 0, 0, 1);
0f8a249a
BS		 1679 ret = 0;
1680 break;
3475187d 1681 }
81ad8ba2
BS		 1682
1683 /* Convert from little endian */
1684 switch (asi) {
1685 case 0x0c: // Nucleus Little Endian (LE)
1686 case 0x18: // As if user primary LE
1687 case 0x19: // As if user secondary LE
1688 case 0x1c: // Bypass LE
1689 case 0x1d: // Bypass, non-cacheable LE
1690 case 0x88: // Primary LE
1691 case 0x89: // Secondary LE
1692 case 0x8a: // Primary no-fault LE
1693 case 0x8b: // Secondary no-fault LE
1694 switch(size) {
1695 case 2:
1696 ret = bswap16(ret);
e32664fb 1697 break;
81ad8ba2
BS		 1698 case 4:
1699 ret = bswap32(ret);
e32664fb 1700 break;
81ad8ba2
BS		 1701 case 8:
1702 ret = bswap64(ret);
e32664fb 1703 break;
81ad8ba2
BS		 1704 default:
1705 break;
1706 }
1707 default:
1708 break;
1709 }
1710
1711 /* Convert to signed number */
1712 if (sign) {
1713 switch(size) {
1714 case 1:
1715 ret = (int8_t) ret;
e32664fb 1716 break;
81ad8ba2
BS		 1717 case 2:
1718 ret = (int16_t) ret;
e32664fb 1719 break;
81ad8ba2
BS		 1720 case 4:
1721 ret = (int32_t) ret;
e32664fb 1722 break;
81ad8ba2
BS		 1723 default:
1724 break;
1725 }
1726 }
1a2fb1c0
BS		 1727#ifdef DEBUG_ASI
1728 dump_asi("read ", last_addr, asi, size, ret);
1729#endif
1730 return ret;
3475187d
FB		 1731}
1732
1a2fb1c0 1733void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
3475187d 1734{
1a2fb1c0
BS		 1735#ifdef DEBUG_ASI
1736 dump_asi("write", addr, asi, size, val);
1737#endif
6f27aba6 1738 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
5578ceab
BS		 1739 || ((env->def->features & CPU_FEATURE_HYPV)
1740 && asi >= 0x30 && asi < 0x80
fb79ceb9 1741 && !(env->hpstate & HS_PRIV)))
0f8a249a 1742 raise_exception(TT_PRIV_ACT);
3475187d 1743
c2bc0e38 1744 helper_check_align(addr, size - 1);
81ad8ba2
BS		 1745 /* Convert to little endian */
1746 switch (asi) {
1747 case 0x0c: // Nucleus Little Endian (LE)
1748 case 0x18: // As if user primary LE
1749 case 0x19: // As if user secondary LE
1750 case 0x1c: // Bypass LE
1751 case 0x1d: // Bypass, non-cacheable LE
81ad8ba2
BS		 1752 case 0x88: // Primary LE
1753 case 0x89: // Secondary LE
1754 switch(size) {
1755 case 2:
1a2fb1c0 1756 addr = bswap16(addr);
e32664fb 1757 break;
81ad8ba2 1758 case 4:
1a2fb1c0 1759 addr = bswap32(addr);
e32664fb 1760 break;
81ad8ba2 1761 case 8:
1a2fb1c0 1762 addr = bswap64(addr);
e32664fb 1763 break;
81ad8ba2
BS		 1764 default:
1765 break;
1766 }
1767 default:
1768 break;
1769 }
1770
3475187d 1771 switch(asi) {
81ad8ba2
BS		 1772 case 0x10: // As if user primary
1773 case 0x18: // As if user primary LE
1774 case 0x80: // Primary
1775 case 0x88: // Primary LE
c99657d3
BS		 1776 case 0xe2: // UA2007 Primary block init
1777 case 0xe3: // UA2007 Secondary block init
81ad8ba2 1778 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
5578ceab
BS		 1779 if ((env->def->features & CPU_FEATURE_HYPV)
1780 && env->hpstate & HS_PRIV) {
6f27aba6
BS		 1781 switch(size) {
1782 case 1:
1a2fb1c0 1783 stb_hypv(addr, val);
6f27aba6
BS		 1784 break;
1785 case 2:
a4e7dd52 1786 stw_hypv(addr, val);
6f27aba6
BS		 1787 break;
1788 case 4:
a4e7dd52 1789 stl_hypv(addr, val);
6f27aba6
BS		 1790 break;
1791 case 8:
1792 default:
a4e7dd52 1793 stq_hypv(addr, val);
6f27aba6
BS		 1794 break;
1795 }
1796 } else {
1797 switch(size) {
1798 case 1:
1a2fb1c0 1799 stb_kernel(addr, val);
6f27aba6
BS		 1800 break;
1801 case 2:
a4e7dd52 1802 stw_kernel(addr, val);
6f27aba6
BS		 1803 break;
1804 case 4:
a4e7dd52 1805 stl_kernel(addr, val);
6f27aba6
BS		 1806 break;
1807 case 8:
1808 default:
a4e7dd52 1809 stq_kernel(addr, val);
6f27aba6
BS		 1810 break;
1811 }
81ad8ba2
BS		 1812 }
1813 } else {
1814 switch(size) {
1815 case 1:
1a2fb1c0 1816 stb_user(addr, val);
81ad8ba2
BS		 1817 break;
1818 case 2:
a4e7dd52 1819 stw_user(addr, val);
81ad8ba2
BS		 1820 break;
1821 case 4:
a4e7dd52 1822 stl_user(addr, val);
81ad8ba2
BS		 1823 break;
1824 case 8:
1825 default:
a4e7dd52 1826 stq_user(addr, val);
81ad8ba2
BS		 1827 break;
1828 }
1829 }
1830 break;
3475187d
FB		 1831 case 0x14: // Bypass
1832 case 0x15: // Bypass, non-cacheable
81ad8ba2
BS		 1833 case 0x1c: // Bypass LE
1834 case 0x1d: // Bypass, non-cacheable LE
0f8a249a 1835 {
02aab46a
FB		 1836 switch(size) {
1837 case 1:
1a2fb1c0 1838 stb_phys(addr, val);
02aab46a
FB		 1839 break;
1840 case 2:
a4e7dd52 1841 stw_phys(addr, val);
02aab46a
FB		 1842 break;
1843 case 4:
a4e7dd52 1844 stl_phys(addr, val);
02aab46a
FB		 1845 break;
1846 case 8:
1847 default:
a4e7dd52 1848 stq_phys(addr, val);
02aab46a
FB		 1849 break;
1850 }
0f8a249a
BS		 1851 }
1852 return;
db166940
BS		 1853 case 0x24: // Nucleus quad LDD 128 bit atomic
1854 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
1855 // Only ldda allowed
1856 raise_exception(TT_ILL_INSN);
1857 return;
83469015
FB		 1858 case 0x04: // Nucleus
1859 case 0x0c: // Nucleus Little Endian (LE)
83469015 1860 case 0x11: // As if user secondary
83469015 1861 case 0x19: // As if user secondary LE
83469015 1862 case 0x4a: // UPA config
51996525 1863 case 0x81: // Secondary
83469015 1864 case 0x89: // Secondary LE
0f8a249a
BS		 1865 // XXX
1866 return;
3475187d 1867 case 0x45: // LSU
0f8a249a
BS		 1868 {
1869 uint64_t oldreg;
1870
1871 oldreg = env->lsu;
1a2fb1c0 1872 env->lsu = val & (DMMU_E | IMMU_E);
0f8a249a
BS		 1873 // Mappings generated during D/I MMU disabled mode are
1874 // invalid in normal mode
1875 if (oldreg != env->lsu) {
77f193da
BS		 1876 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
1877 oldreg, env->lsu);
83469015 1878#ifdef DEBUG_MMU
0f8a249a 1879 dump_mmu(env);
83469015 1880#endif
0f8a249a
BS		 1881 tlb_flush(env, 1);
1882 }
1883 return;
1884 }
3475187d 1885 case 0x50: // I-MMU regs
0f8a249a 1886 {
1a2fb1c0 1887 int reg = (addr >> 3) & 0xf;
0f8a249a 1888 uint64_t oldreg;
3b46e624 1889
0f8a249a 1890 oldreg = env->immuregs[reg];
3475187d
FB		 1891 switch(reg) {
1892 case 0: // RO
1893 case 4:
1894 return;
1895 case 1: // Not in I-MMU
1896 case 2:
1897 case 7:
1898 case 8:
1899 return;
1900 case 3: // SFSR
1a2fb1c0
BS		 1901 if ((val & 1) == 0)
1902 val = 0; // Clear SFSR
3475187d
FB		 1903 break;
1904 case 5: // TSB access
1905 case 6: // Tag access
1906 default:
1907 break;
1908 }
1a2fb1c0 1909 env->immuregs[reg] = val;
3475187d 1910 if (oldreg != env->immuregs[reg]) {
77f193da
BS		 1911 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
1912 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
3475187d 1913 }
952a328f 1914#ifdef DEBUG_MMU
0f8a249a 1915 dump_mmu(env);
3475187d 1916#endif
0f8a249a
BS		 1917 return;
1918 }
3475187d 1919 case 0x54: // I-MMU data in
0f8a249a
BS		 1920 {
1921 unsigned int i;
1922
1923 // Try finding an invalid entry
1924 for (i = 0; i < 64; i++) {
1925 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
1926 env->itlb_tag[i] = env->immuregs[6];
1a2fb1c0 1927 env->itlb_tte[i] = val;
0f8a249a
BS		 1928 return;
1929 }
1930 }
1931 // Try finding an unlocked entry
1932 for (i = 0; i < 64; i++) {
1933 if ((env->itlb_tte[i] & 0x40) == 0) {
1934 env->itlb_tag[i] = env->immuregs[6];
1a2fb1c0 1935 env->itlb_tte[i] = val;
0f8a249a
BS		 1936 return;
1937 }
1938 }
1939 // error state?
1940 return;
1941 }
3475187d 1942 case 0x55: // I-MMU data access
0f8a249a 1943 {
cc6747f4
BS		 1944 // TODO: auto demap
1945
1a2fb1c0 1946 unsigned int i = (addr >> 3) & 0x3f;
3475187d 1947
0f8a249a 1948 env->itlb_tag[i] = env->immuregs[6];
1a2fb1c0 1949 env->itlb_tte[i] = val;
0f8a249a
BS		 1950 return;
1951 }
3475187d 1952 case 0x57: // I-MMU demap
cc6747f4
BS		 1953 {
1954 unsigned int i;
1955
1956 for (i = 0; i < 64; i++) {
1957 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
1958 target_ulong mask = 0xffffffffffffe000ULL;
1959
1960 mask <<= 3 * ((env->itlb_tte[i] >> 61) & 3);
1961 if ((val & mask) == (env->itlb_tag[i] & mask)) {
1962 env->itlb_tag[i] = 0;
1963 env->itlb_tte[i] = 0;
1964 }
1965 return;
1966 }
1967 }
1968 }
0f8a249a 1969 return;
3475187d 1970 case 0x58: // D-MMU regs
0f8a249a 1971 {
1a2fb1c0 1972 int reg = (addr >> 3) & 0xf;
0f8a249a 1973 uint64_t oldreg;
3b46e624 1974
0f8a249a 1975 oldreg = env->dmmuregs[reg];
3475187d
FB		 1976 switch(reg) {
1977 case 0: // RO
1978 case 4:
1979 return;
1980 case 3: // SFSR
1a2fb1c0
BS		 1981 if ((val & 1) == 0) {
1982 val = 0; // Clear SFSR, Fault address
0f8a249a
BS		 1983 env->dmmuregs[4] = 0;
1984 }
1a2fb1c0 1985 env->dmmuregs[reg] = val;
3475187d
FB		 1986 break;
1987 case 1: // Primary context
1988 case 2: // Secondary context
1989 case 5: // TSB access
1990 case 6: // Tag access
1991 case 7: // Virtual Watchpoint
1992 case 8: // Physical Watchpoint
1993 default:
1994 break;
1995 }
1a2fb1c0 1996 env->dmmuregs[reg] = val;
3475187d 1997 if (oldreg != env->dmmuregs[reg]) {
77f193da
BS		 1998 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
1999 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
3475187d 2000 }
952a328f 2001#ifdef DEBUG_MMU
0f8a249a 2002 dump_mmu(env);
3475187d 2003#endif
0f8a249a
BS		 2004 return;
2005 }
3475187d 2006 case 0x5c: // D-MMU data in
0f8a249a
BS		 2007 {
2008 unsigned int i;
2009
2010 // Try finding an invalid entry
2011 for (i = 0; i < 64; i++) {
2012 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
2013 env->dtlb_tag[i] = env->dmmuregs[6];
1a2fb1c0 2014 env->dtlb_tte[i] = val;
0f8a249a
BS		 2015 return;
2016 }
2017 }
2018 // Try finding an unlocked entry
2019 for (i = 0; i < 64; i++) {
2020 if ((env->dtlb_tte[i] & 0x40) == 0) {
2021 env->dtlb_tag[i] = env->dmmuregs[6];
1a2fb1c0 2022 env->dtlb_tte[i] = val;
0f8a249a
BS		 2023 return;
2024 }
2025 }
2026 // error state?
2027 return;
2028 }
3475187d 2029 case 0x5d: // D-MMU data access
0f8a249a 2030 {
1a2fb1c0 2031 unsigned int i = (addr >> 3) & 0x3f;
3475187d 2032
0f8a249a 2033 env->dtlb_tag[i] = env->dmmuregs[6];
1a2fb1c0 2034 env->dtlb_tte[i] = val;
0f8a249a
BS		 2035 return;
2036 }
3475187d 2037 case 0x5f: // D-MMU demap
cc6747f4
BS		 2038 {
2039 unsigned int i;
2040
2041 for (i = 0; i < 64; i++) {
2042 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
2043 target_ulong mask = 0xffffffffffffe000ULL;
2044
2045 mask <<= 3 * ((env->dtlb_tte[i] >> 61) & 3);
2046 if ((val & mask) == (env->dtlb_tag[i] & mask)) {
2047 env->dtlb_tag[i] = 0;
2048 env->dtlb_tte[i] = 0;
2049 }
2050 return;
2051 }
2052 }
2053 }
2054 return;
83469015 2055 case 0x49: // Interrupt data receive
0f8a249a
BS		 2056 // XXX
2057 return;
f7350b47
BS		 2058 case 0x46: // D-cache data
2059 case 0x47: // D-cache tag access
a5a52cf2
BS		 2060 case 0x4b: // E-cache error enable
2061 case 0x4c: // E-cache asynchronous fault status
2062 case 0x4d: // E-cache asynchronous fault address
f7350b47
BS		 2063 case 0x4e: // E-cache tag data
2064 case 0x66: // I-cache instruction access
2065 case 0x67: // I-cache tag access
2066 case 0x6e: // I-cache predecode
2067 case 0x6f: // I-cache LRU etc.
2068 case 0x76: // E-cache tag
2069 case 0x7e: // E-cache tag
2070 return;
3475187d
FB		 2071 case 0x51: // I-MMU 8k TSB pointer, RO
2072 case 0x52: // I-MMU 64k TSB pointer, RO
2073 case 0x56: // I-MMU tag read, RO
2074 case 0x59: // D-MMU 8k TSB pointer, RO
2075 case 0x5a: // D-MMU 64k TSB pointer, RO
2076 case 0x5b: // D-MMU data pointer, RO
2077 case 0x5e: // D-MMU tag read, RO
83469015
FB		 2078 case 0x48: // Interrupt dispatch, RO
2079 case 0x7f: // Incoming interrupt vector, RO
2080 case 0x82: // Primary no-fault, RO
2081 case 0x83: // Secondary no-fault, RO
2082 case 0x8a: // Primary no-fault LE, RO
2083 case 0x8b: // Secondary no-fault LE, RO
3475187d 2084 default:
1a2fb1c0 2085 do_unassigned_access(addr, 1, 0, 1);
0f8a249a 2086 return;
3475187d
FB		 2087 }
2088}
81ad8ba2 2089#endif /* CONFIG_USER_ONLY */
3391c818 2090
db166940
BS		 2091void helper_ldda_asi(target_ulong addr, int asi, int rd)
2092{
db166940 2093 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
5578ceab
BS		 2094 || ((env->def->features & CPU_FEATURE_HYPV)
2095 && asi >= 0x30 && asi < 0x80
fb79ceb9 2096 && !(env->hpstate & HS_PRIV)))
db166940
BS		 2097 raise_exception(TT_PRIV_ACT);
2098
2099 switch (asi) {
2100 case 0x24: // Nucleus quad LDD 128 bit atomic
2101 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2102 helper_check_align(addr, 0xf);
2103 if (rd == 0) {
2104 env->gregs[1] = ldq_kernel(addr + 8);
2105 if (asi == 0x2c)
2106 bswap64s(&env->gregs[1]);
2107 } else if (rd < 8) {
2108 env->gregs[rd] = ldq_kernel(addr);
2109 env->gregs[rd + 1] = ldq_kernel(addr + 8);
2110 if (asi == 0x2c) {
2111 bswap64s(&env->gregs[rd]);
2112 bswap64s(&env->gregs[rd + 1]);
2113 }
2114 } else {
2115 env->regwptr[rd] = ldq_kernel(addr);
2116 env->regwptr[rd + 1] = ldq_kernel(addr + 8);
2117 if (asi == 0x2c) {
2118 bswap64s(&env->regwptr[rd]);
2119 bswap64s(&env->regwptr[rd + 1]);
2120 }
2121 }
2122 break;
2123 default:
2124 helper_check_align(addr, 0x3);
2125 if (rd == 0)
2126 env->gregs[1] = helper_ld_asi(addr + 4, asi, 4, 0);
2127 else if (rd < 8) {
2128 env->gregs[rd] = helper_ld_asi(addr, asi, 4, 0);
2129 env->gregs[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2130 } else {
2131 env->regwptr[rd] = helper_ld_asi(addr, asi, 4, 0);
2132 env->regwptr[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2133 }
2134 break;
2135 }
2136}
2137
1a2fb1c0 2138void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
3391c818 2139{
3391c818 2140 unsigned int i;
1a2fb1c0 2141 target_ulong val;
3391c818 2142
c2bc0e38 2143 helper_check_align(addr, 3);
3391c818
BS		 2144 switch (asi) {
2145 case 0xf0: // Block load primary
2146 case 0xf1: // Block load secondary
2147 case 0xf8: // Block load primary LE
2148 case 0xf9: // Block load secondary LE
51996525
BS		 2149 if (rd & 7) {
2150 raise_exception(TT_ILL_INSN);
2151 return;
2152 }
c2bc0e38 2153 helper_check_align(addr, 0x3f);
51996525 2154 for (i = 0; i < 16; i++) {
77f193da
BS		 2155 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4,
2156 0);
1a2fb1c0 2157 addr += 4;
3391c818 2158 }
3391c818
BS		 2159
2160 return;
2161 default:
2162 break;
2163 }
2164
1a2fb1c0 2165 val = helper_ld_asi(addr, asi, size, 0);
3391c818
BS		 2166 switch(size) {
2167 default:
2168 case 4:
714547bb 2169 *((uint32_t *)&env->fpr[rd]) = val;
3391c818
BS		 2170 break;
2171 case 8:
1a2fb1c0 2172 *((int64_t *)&DT0) = val;
3391c818 2173 break;
1f587329
BS		 2174 case 16:
2175 // XXX
2176 break;
3391c818 2177 }
3391c818
BS		 2178}
2179
1a2fb1c0 2180void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
3391c818 2181{
3391c818 2182 unsigned int i;
1a2fb1c0 2183 target_ulong val = 0;
3391c818 2184
c2bc0e38 2185 helper_check_align(addr, 3);
3391c818 2186 switch (asi) {
c99657d3
BS		 2187 case 0xe0: // UA2007 Block commit store primary (cache flush)
2188 case 0xe1: // UA2007 Block commit store secondary (cache flush)
3391c818
BS		 2189 case 0xf0: // Block store primary
2190 case 0xf1: // Block store secondary
2191 case 0xf8: // Block store primary LE
2192 case 0xf9: // Block store secondary LE
51996525
BS		 2193 if (rd & 7) {
2194 raise_exception(TT_ILL_INSN);
2195 return;
2196 }
c2bc0e38 2197 helper_check_align(addr, 0x3f);
51996525 2198 for (i = 0; i < 16; i++) {
1a2fb1c0
BS		 2199 val = *(uint32_t *)&env->fpr[rd++];
2200 helper_st_asi(addr, val, asi & 0x8f, 4);
2201 addr += 4;
3391c818 2202 }
3391c818
BS		 2203
2204 return;
2205 default:
2206 break;
2207 }
2208
2209 switch(size) {
2210 default:
2211 case 4:
714547bb 2212 val = *((uint32_t *)&env->fpr[rd]);
3391c818
BS		 2213 break;
2214 case 8:
1a2fb1c0 2215 val = *((int64_t *)&DT0);
3391c818 2216 break;
1f587329
BS		 2217 case 16:
2218 // XXX
2219 break;
3391c818 2220 }
1a2fb1c0
BS		 2221 helper_st_asi(addr, val, asi, size);
2222}
2223
2224target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
2225 target_ulong val2, uint32_t asi)
2226{
2227 target_ulong ret;
2228
1121f879 2229 val2 &= 0xffffffffUL;
1a2fb1c0
BS		 2230 ret = helper_ld_asi(addr, asi, 4, 0);
2231 ret &= 0xffffffffUL;
1121f879
BS		 2232 if (val2 == ret)
2233 helper_st_asi(addr, val1 & 0xffffffffUL, asi, 4);
1a2fb1c0 2234 return ret;
3391c818
BS		 2235}
2236
1a2fb1c0
BS		 2237target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
2238 target_ulong val2, uint32_t asi)
2239{
2240 target_ulong ret;
2241
2242 ret = helper_ld_asi(addr, asi, 8, 0);
1121f879
BS		 2243 if (val2 == ret)
2244 helper_st_asi(addr, val1, asi, 8);
1a2fb1c0
BS		 2245 return ret;
2246}
81ad8ba2 2247#endif /* TARGET_SPARC64 */
3475187d
FB		 2248
2249#ifndef TARGET_SPARC64
1a2fb1c0 2250void helper_rett(void)
e8af50a3 2251{
af7bf89b
FB		 2252 unsigned int cwp;
2253
d4218d99
BS		 2254 if (env->psret == 1)
2255 raise_exception(TT_ILL_INSN);
2256
e8af50a3 2257 env->psret = 1;
1a14026e 2258 cwp = cpu_cwp_inc(env, env->cwp + 1) ;
e8af50a3
FB		 2259 if (env->wim & (1 << cwp)) {
2260 raise_exception(TT_WIN_UNF);
2261 }
2262 set_cwp(cwp);
2263 env->psrs = env->psrps;
2264}
3475187d 2265#endif
e8af50a3 2266
3b89f26c
BS		 2267target_ulong helper_udiv(target_ulong a, target_ulong b)
2268{
2269 uint64_t x0;
2270 uint32_t x1;
2271
7621a90d 2272 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
3b89f26c
BS		 2273 x1 = b;
2274
2275 if (x1 == 0) {
2276 raise_exception(TT_DIV_ZERO);
2277 }
2278
2279 x0 = x0 / x1;
2280 if (x0 > 0xffffffff) {
2281 env->cc_src2 = 1;
2282 return 0xffffffff;
2283 } else {
2284 env->cc_src2 = 0;
2285 return x0;
2286 }
2287}
2288
2289target_ulong helper_sdiv(target_ulong a, target_ulong b)
2290{
2291 int64_t x0;
2292 int32_t x1;
2293
7621a90d 2294 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
3b89f26c
BS		 2295 x1 = b;
2296
2297 if (x1 == 0) {
2298 raise_exception(TT_DIV_ZERO);
2299 }
2300
2301 x0 = x0 / x1;
2302 if ((int32_t) x0 != x0) {
2303 env->cc_src2 = 1;
2304 return x0 < 0? 0x80000000: 0x7fffffff;
2305 } else {
2306 env->cc_src2 = 0;
2307 return x0;
2308 }
2309}
2310
7fa76c0b
BS		 2311void helper_stdf(target_ulong addr, int mem_idx)
2312{
c2bc0e38 2313 helper_check_align(addr, 7);
7fa76c0b
BS		 2314#if !defined(CONFIG_USER_ONLY)
2315 switch (mem_idx) {
2316 case 0:
c2bc0e38 2317 stfq_user(addr, DT0);
7fa76c0b
BS		 2318 break;
2319 case 1:
c2bc0e38 2320 stfq_kernel(addr, DT0);
7fa76c0b
BS		 2321 break;
2322#ifdef TARGET_SPARC64
2323 case 2:
c2bc0e38 2324 stfq_hypv(addr, DT0);
7fa76c0b
BS		 2325 break;
2326#endif
2327 default:
2328 break;
2329 }
2330#else
2cade6a3 2331 address_mask(env, &addr);
c2bc0e38 2332 stfq_raw(addr, DT0);
7fa76c0b
BS		 2333#endif
2334}
2335
2336void helper_lddf(target_ulong addr, int mem_idx)
2337{
c2bc0e38 2338 helper_check_align(addr, 7);
7fa76c0b
BS		 2339#if !defined(CONFIG_USER_ONLY)
2340 switch (mem_idx) {
2341 case 0:
c2bc0e38 2342 DT0 = ldfq_user(addr);
7fa76c0b
BS		 2343 break;
2344 case 1:
c2bc0e38 2345 DT0 = ldfq_kernel(addr);
7fa76c0b
BS		 2346 break;
2347#ifdef TARGET_SPARC64
2348 case 2:
c2bc0e38 2349 DT0 = ldfq_hypv(addr);
7fa76c0b
BS		 2350 break;
2351#endif
2352 default:
2353 break;
2354 }
2355#else
2cade6a3 2356 address_mask(env, &addr);
c2bc0e38 2357 DT0 = ldfq_raw(addr);
7fa76c0b
BS		 2358#endif
2359}
2360
64a88d5d 2361void helper_ldqf(target_ulong addr, int mem_idx)
7fa76c0b
BS		 2362{
2363 // XXX add 128 bit load
2364 CPU_QuadU u;
2365
c2bc0e38 2366 helper_check_align(addr, 7);
64a88d5d
BS		 2367#if !defined(CONFIG_USER_ONLY)
2368 switch (mem_idx) {
2369 case 0:
c2bc0e38
BS		 2370 u.ll.upper = ldq_user(addr);
2371 u.ll.lower = ldq_user(addr + 8);
64a88d5d
BS		 2372 QT0 = u.q;
2373 break;
2374 case 1:
c2bc0e38
BS		 2375 u.ll.upper = ldq_kernel(addr);
2376 u.ll.lower = ldq_kernel(addr + 8);
64a88d5d
BS		 2377 QT0 = u.q;
2378 break;
2379#ifdef TARGET_SPARC64
2380 case 2:
c2bc0e38
BS		 2381 u.ll.upper = ldq_hypv(addr);
2382 u.ll.lower = ldq_hypv(addr + 8);
64a88d5d
BS		 2383 QT0 = u.q;
2384 break;
2385#endif
2386 default:
2387 break;
2388 }
2389#else
2cade6a3 2390 address_mask(env, &addr);
c2bc0e38
BS		 2391 u.ll.upper = ldq_raw(addr);
2392 u.ll.lower = ldq_raw((addr + 8) & 0xffffffffULL);
7fa76c0b 2393 QT0 = u.q;
64a88d5d 2394#endif
7fa76c0b
BS		 2395}
2396
64a88d5d 2397void helper_stqf(target_ulong addr, int mem_idx)
7fa76c0b
BS		 2398{
2399 // XXX add 128 bit store
2400 CPU_QuadU u;
2401
c2bc0e38 2402 helper_check_align(addr, 7);
64a88d5d
BS		 2403#if !defined(CONFIG_USER_ONLY)
2404 switch (mem_idx) {
2405 case 0:
2406 u.q = QT0;
c2bc0e38
BS		 2407 stq_user(addr, u.ll.upper);
2408 stq_user(addr + 8, u.ll.lower);
64a88d5d
BS		 2409 break;
2410 case 1:
2411 u.q = QT0;
c2bc0e38
BS		 2412 stq_kernel(addr, u.ll.upper);
2413 stq_kernel(addr + 8, u.ll.lower);
64a88d5d
BS		 2414 break;
2415#ifdef TARGET_SPARC64
2416 case 2:
2417 u.q = QT0;
c2bc0e38
BS		 2418 stq_hypv(addr, u.ll.upper);
2419 stq_hypv(addr + 8, u.ll.lower);
64a88d5d
BS		 2420 break;
2421#endif
2422 default:
2423 break;
2424 }
2425#else
7fa76c0b 2426 u.q = QT0;
2cade6a3 2427 address_mask(env, &addr);
c2bc0e38
BS		 2428 stq_raw(addr, u.ll.upper);
2429 stq_raw((addr + 8) & 0xffffffffULL, u.ll.lower);
7fa76c0b 2430#endif
64a88d5d 2431}
7fa76c0b 2432
3a3b925d 2433static inline void set_fsr(void)
e8af50a3 2434{
7a0e1f41 2435 int rnd_mode;
bb5529bb 2436
e8af50a3
FB		 2437 switch (env->fsr & FSR_RD_MASK) {
2438 case FSR_RD_NEAREST:
7a0e1f41 2439 rnd_mode = float_round_nearest_even;
0f8a249a 2440 break;
ed910241 2441 default:
e8af50a3 2442 case FSR_RD_ZERO:
7a0e1f41 2443 rnd_mode = float_round_to_zero;
0f8a249a 2444 break;
e8af50a3 2445 case FSR_RD_POS:
7a0e1f41 2446 rnd_mode = float_round_up;
0f8a249a 2447 break;
e8af50a3 2448 case FSR_RD_NEG:
7a0e1f41 2449 rnd_mode = float_round_down;
0f8a249a 2450 break;
e8af50a3 2451 }
7a0e1f41 2452 set_float_rounding_mode(rnd_mode, &env->fp_status);
e8af50a3 2453}
e80cfcfc 2454
3a3b925d 2455void helper_ldfsr(uint32_t new_fsr)
bb5529bb 2456{
3a3b925d
BS		 2457 env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK);
2458 set_fsr();
bb5529bb
BS		 2459}
2460
3a3b925d
BS		 2461#ifdef TARGET_SPARC64
2462void helper_ldxfsr(uint64_t new_fsr)
2463{
2464 env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK);
2465 set_fsr();
2466}
2467#endif
2468
bb5529bb 2469void helper_debug(void)
e80cfcfc
FB		 2470{
2471 env->exception_index = EXCP_DEBUG;
2472 cpu_loop_exit();
2473}
af7bf89b 2474
3475187d 2475#ifndef TARGET_SPARC64
72a9747b
BS		 2476/* XXX: use another pointer for %iN registers to avoid slow wrapping
2477 handling ? */
2478void helper_save(void)
2479{
2480 uint32_t cwp;
2481
1a14026e 2482 cwp = cpu_cwp_dec(env, env->cwp - 1);
72a9747b
BS		 2483 if (env->wim & (1 << cwp)) {
2484 raise_exception(TT_WIN_OVF);
2485 }
2486 set_cwp(cwp);
2487}
2488
2489void helper_restore(void)
2490{
2491 uint32_t cwp;
2492
1a14026e 2493 cwp = cpu_cwp_inc(env, env->cwp + 1);
72a9747b
BS		 2494 if (env->wim & (1 << cwp)) {
2495 raise_exception(TT_WIN_UNF);
2496 }
2497 set_cwp(cwp);
2498}
2499
1a2fb1c0 2500void helper_wrpsr(target_ulong new_psr)
af7bf89b 2501{
1a14026e 2502 if ((new_psr & PSR_CWP) >= env->nwindows)
d4218d99
BS		 2503 raise_exception(TT_ILL_INSN);
2504 else
1a2fb1c0 2505 PUT_PSR(env, new_psr);
af7bf89b
FB		 2506}
2507
1a2fb1c0 2508target_ulong helper_rdpsr(void)
af7bf89b 2509{
1a2fb1c0 2510 return GET_PSR(env);
af7bf89b 2511}
3475187d
FB		 2512
2513#else
72a9747b
BS		 2514/* XXX: use another pointer for %iN registers to avoid slow wrapping
2515 handling ? */
2516void helper_save(void)
2517{
2518 uint32_t cwp;
2519
1a14026e 2520 cwp = cpu_cwp_dec(env, env->cwp - 1);
72a9747b
BS		 2521 if (env->cansave == 0) {
2522 raise_exception(TT_SPILL | (env->otherwin != 0 ?
2523 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2524 ((env->wstate & 0x7) << 2)));
2525 } else {
2526 if (env->cleanwin - env->canrestore == 0) {
2527 // XXX Clean windows without trap
2528 raise_exception(TT_CLRWIN);
2529 } else {
2530 env->cansave--;
2531 env->canrestore++;
2532 set_cwp(cwp);
2533 }
2534 }
2535}
2536
2537void helper_restore(void)
2538{
2539 uint32_t cwp;
2540
1a14026e 2541 cwp = cpu_cwp_inc(env, env->cwp + 1);
72a9747b
BS		 2542 if (env->canrestore == 0) {
2543 raise_exception(TT_FILL | (env->otherwin != 0 ?
2544 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2545 ((env->wstate & 0x7) << 2)));
2546 } else {
2547 env->cansave++;
2548 env->canrestore--;
2549 set_cwp(cwp);
2550 }
2551}
2552
2553void helper_flushw(void)
2554{
1a14026e 2555 if (env->cansave != env->nwindows - 2) {
72a9747b
BS		 2556 raise_exception(TT_SPILL | (env->otherwin != 0 ?
2557 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2558 ((env->wstate & 0x7) << 2)));
2559 }
2560}
2561
2562void helper_saved(void)
2563{
2564 env->cansave++;
2565 if (env->otherwin == 0)
2566 env->canrestore--;
2567 else
2568 env->otherwin--;
2569}
2570
2571void helper_restored(void)
2572{
2573 env->canrestore++;
1a14026e 2574 if (env->cleanwin < env->nwindows - 1)
72a9747b
BS		 2575 env->cleanwin++;
2576 if (env->otherwin == 0)
2577 env->cansave--;
2578 else
2579 env->otherwin--;
2580}
2581
d35527d9
BS		 2582target_ulong helper_rdccr(void)
2583{
2584 return GET_CCR(env);
2585}
2586
2587void helper_wrccr(target_ulong new_ccr)
2588{
2589 PUT_CCR(env, new_ccr);
2590}
2591
2592// CWP handling is reversed in V9, but we still use the V8 register
2593// order.
2594target_ulong helper_rdcwp(void)
2595{
2596 return GET_CWP64(env);
2597}
2598
2599void helper_wrcwp(target_ulong new_cwp)
2600{
2601 PUT_CWP64(env, new_cwp);
2602}
3475187d 2603
1f5063fb
BS		 2604// This function uses non-native bit order
2605#define GET_FIELD(X, FROM, TO) \
2606 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
2607
2608// This function uses the order in the manuals, i.e. bit 0 is 2^0
2609#define GET_FIELD_SP(X, FROM, TO) \
2610 GET_FIELD(X, 63 - (TO), 63 - (FROM))
2611
2612target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
2613{
2614 return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
2615 (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
2616 (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) |
2617 (GET_FIELD_SP(pixel_addr, 56, 59) << 13) |
2618 (GET_FIELD_SP(pixel_addr, 35, 38) << 9) |
2619 (GET_FIELD_SP(pixel_addr, 13, 16) << 5) |
2620 (((pixel_addr >> 55) & 1) << 4) |
2621 (GET_FIELD_SP(pixel_addr, 33, 34) << 2) |
2622 GET_FIELD_SP(pixel_addr, 11, 12);
2623}
2624
2625target_ulong helper_alignaddr(target_ulong addr, target_ulong offset)
2626{
2627 uint64_t tmp;
2628
2629 tmp = addr + offset;
2630 env->gsr &= ~7ULL;
2631 env->gsr |= tmp & 7ULL;
2632 return tmp & ~7ULL;
2633}
2634
1a2fb1c0 2635target_ulong helper_popc(target_ulong val)
3475187d 2636{
1a2fb1c0 2637 return ctpop64(val);
3475187d 2638}
83469015
FB		 2639
2640static inline uint64_t *get_gregset(uint64_t pstate)
2641{
2642 switch (pstate) {
2643 default:
2644 case 0:
0f8a249a 2645 return env->bgregs;
83469015 2646 case PS_AG:
0f8a249a 2647 return env->agregs;
83469015 2648 case PS_MG:
0f8a249a 2649 return env->mgregs;
83469015 2650 case PS_IG:
0f8a249a 2651 return env->igregs;
83469015
FB		 2652 }
2653}
2654
91736d37 2655static inline void change_pstate(uint64_t new_pstate)
83469015 2656{
8f1f22f6 2657 uint64_t pstate_regs, new_pstate_regs;
83469015
FB		 2658 uint64_t *src, *dst;
2659
83469015
FB		 2660 pstate_regs = env->pstate & 0xc01;
2661 new_pstate_regs = new_pstate & 0xc01;
2662 if (new_pstate_regs != pstate_regs) {
0f8a249a
BS		 2663 // Switch global register bank
2664 src = get_gregset(new_pstate_regs);
2665 dst = get_gregset(pstate_regs);
2666 memcpy32(dst, env->gregs);
2667 memcpy32(env->gregs, src);
83469015
FB		 2668 }
2669 env->pstate = new_pstate;
2670}
2671
1a2fb1c0 2672void helper_wrpstate(target_ulong new_state)
8f1f22f6 2673{
5578ceab 2674 if (!(env->def->features & CPU_FEATURE_GL))
fb79ceb9 2675 change_pstate(new_state & 0xf3f);
8f1f22f6
BS		 2676}
2677
1a2fb1c0 2678void helper_done(void)
83469015 2679{
375ee38b
BS		 2680 env->pc = env->tsptr->tpc;
2681 env->npc = env->tsptr->tnpc + 4;
2682 PUT_CCR(env, env->tsptr->tstate >> 32);
2683 env->asi = (env->tsptr->tstate >> 24) & 0xff;
2684 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2685 PUT_CWP64(env, env->tsptr->tstate & 0xff);
e6bf7d70 2686 env->tl--;
c19148bd 2687 env->tsptr = &env->ts[env->tl & MAXTL_MASK];
83469015
FB		 2688}
2689
1a2fb1c0 2690void helper_retry(void)
83469015 2691{
375ee38b
BS		 2692 env->pc = env->tsptr->tpc;
2693 env->npc = env->tsptr->tnpc;
2694 PUT_CCR(env, env->tsptr->tstate >> 32);
2695 env->asi = (env->tsptr->tstate >> 24) & 0xff;
2696 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2697 PUT_CWP64(env, env->tsptr->tstate & 0xff);
e6bf7d70 2698 env->tl--;
c19148bd 2699 env->tsptr = &env->ts[env->tl & MAXTL_MASK];
83469015 2700}
9d926598
BS		 2701
2702void helper_set_softint(uint64_t value)
2703{
2704 env->softint |= (uint32_t)value;
2705}
2706
2707void helper_clear_softint(uint64_t value)
2708{
2709 env->softint &= (uint32_t)~value;
2710}
2711
2712void helper_write_softint(uint64_t value)
2713{
2714 env->softint = (uint32_t)value;
2715}
3475187d 2716#endif
ee5bbe38 2717
91736d37 2718void helper_flush(target_ulong addr)
ee5bbe38 2719{
91736d37
BS		 2720 addr &= ~7;
2721 tb_invalidate_page_range(addr, addr + 8);
ee5bbe38
FB		 2722}
2723
91736d37
BS		 2724#ifdef TARGET_SPARC64
2725#ifdef DEBUG_PCALL
2726static const char * const excp_names[0x80] = {
2727 [TT_TFAULT] = "Instruction Access Fault",
2728 [TT_TMISS] = "Instruction Access MMU Miss",
2729 [TT_CODE_ACCESS] = "Instruction Access Error",
2730 [TT_ILL_INSN] = "Illegal Instruction",
2731 [TT_PRIV_INSN] = "Privileged Instruction",
2732 [TT_NFPU_INSN] = "FPU Disabled",
2733 [TT_FP_EXCP] = "FPU Exception",
2734 [TT_TOVF] = "Tag Overflow",
2735 [TT_CLRWIN] = "Clean Windows",
2736 [TT_DIV_ZERO] = "Division By Zero",
2737 [TT_DFAULT] = "Data Access Fault",
2738 [TT_DMISS] = "Data Access MMU Miss",
2739 [TT_DATA_ACCESS] = "Data Access Error",
2740 [TT_DPROT] = "Data Protection Error",
2741 [TT_UNALIGNED] = "Unaligned Memory Access",
2742 [TT_PRIV_ACT] = "Privileged Action",
2743 [TT_EXTINT | 0x1] = "External Interrupt 1",
2744 [TT_EXTINT | 0x2] = "External Interrupt 2",
2745 [TT_EXTINT | 0x3] = "External Interrupt 3",
2746 [TT_EXTINT | 0x4] = "External Interrupt 4",
2747 [TT_EXTINT | 0x5] = "External Interrupt 5",
2748 [TT_EXTINT | 0x6] = "External Interrupt 6",
2749 [TT_EXTINT | 0x7] = "External Interrupt 7",
2750 [TT_EXTINT | 0x8] = "External Interrupt 8",
2751 [TT_EXTINT | 0x9] = "External Interrupt 9",
2752 [TT_EXTINT | 0xa] = "External Interrupt 10",
2753 [TT_EXTINT | 0xb] = "External Interrupt 11",
2754 [TT_EXTINT | 0xc] = "External Interrupt 12",
2755 [TT_EXTINT | 0xd] = "External Interrupt 13",
2756 [TT_EXTINT | 0xe] = "External Interrupt 14",
2757 [TT_EXTINT | 0xf] = "External Interrupt 15",
2758};
2759#endif
2760
2761void do_interrupt(CPUState *env)
2762{
2763 int intno = env->exception_index;
2764
2765#ifdef DEBUG_PCALL
2766 if (loglevel & CPU_LOG_INT) {
2767 static int count;
2768 const char *name;
2769
2770 if (intno < 0 || intno >= 0x180)
2771 name = "Unknown";
2772 else if (intno >= 0x100)
2773 name = "Trap Instruction";
2774 else if (intno >= 0xc0)
2775 name = "Window Fill";
2776 else if (intno >= 0x80)
2777 name = "Window Spill";
2778 else {
2779 name = excp_names[intno];
2780 if (!name)
2781 name = "Unknown";
2782 }
2783
2784 fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
2785 " SP=%016" PRIx64 "\n",
2786 count, name, intno,
2787 env->pc,
2788 env->npc, env->regwptr[6]);
2789 cpu_dump_state(env, logfile, fprintf, 0);
2790#if 0
2791 {
2792 int i;
2793 uint8_t *ptr;
2794
2795 fprintf(logfile, " code=");
2796 ptr = (uint8_t *)env->pc;
2797 for(i = 0; i < 16; i++) {
2798 fprintf(logfile, " %02x", ldub(ptr + i));
2799 }
2800 fprintf(logfile, "\n");
2801 }
2802#endif
2803 count++;
2804 }
2805#endif
2806#if !defined(CONFIG_USER_ONLY)
2807 if (env->tl >= env->maxtl) {
2808 cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
2809 " Error state", env->exception_index, env->tl, env->maxtl);
2810 return;
2811 }
2812#endif
2813 if (env->tl < env->maxtl - 1) {
2814 env->tl++;
2815 } else {
2816 env->pstate |= PS_RED;
2817 if (env->tl < env->maxtl)
2818 env->tl++;
2819 }
2820 env->tsptr = &env->ts[env->tl & MAXTL_MASK];
2821 env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
2822 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
2823 GET_CWP64(env);
2824 env->tsptr->tpc = env->pc;
2825 env->tsptr->tnpc = env->npc;
2826 env->tsptr->tt = intno;
2827 if (!(env->def->features & CPU_FEATURE_GL)) {
2828 switch (intno) {
2829 case TT_IVEC:
2830 change_pstate(PS_PEF | PS_PRIV | PS_IG);
2831 break;
2832 case TT_TFAULT:
2833 case TT_TMISS:
2834 case TT_DFAULT:
2835 case TT_DMISS:
2836 case TT_DPROT:
2837 change_pstate(PS_PEF | PS_PRIV | PS_MG);
2838 break;
2839 default:
2840 change_pstate(PS_PEF | PS_PRIV | PS_AG);
2841 break;
2842 }
2843 }
2844 if (intno == TT_CLRWIN)
2845 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
2846 else if ((intno & 0x1c0) == TT_SPILL)
2847 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
2848 else if ((intno & 0x1c0) == TT_FILL)
2849 cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
2850 env->tbr &= ~0x7fffULL;
2851 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
2852 env->pc = env->tbr;
2853 env->npc = env->pc + 4;
2854 env->exception_index = 0;
ee5bbe38 2855}
91736d37
BS		 2856#else
2857#ifdef DEBUG_PCALL
2858static const char * const excp_names[0x80] = {
2859 [TT_TFAULT] = "Instruction Access Fault",
2860 [TT_ILL_INSN] = "Illegal Instruction",
2861 [TT_PRIV_INSN] = "Privileged Instruction",
2862 [TT_NFPU_INSN] = "FPU Disabled",
2863 [TT_WIN_OVF] = "Window Overflow",
2864 [TT_WIN_UNF] = "Window Underflow",
2865 [TT_UNALIGNED] = "Unaligned Memory Access",
2866 [TT_FP_EXCP] = "FPU Exception",
2867 [TT_DFAULT] = "Data Access Fault",
2868 [TT_TOVF] = "Tag Overflow",
2869 [TT_EXTINT | 0x1] = "External Interrupt 1",
2870 [TT_EXTINT | 0x2] = "External Interrupt 2",
2871 [TT_EXTINT | 0x3] = "External Interrupt 3",
2872 [TT_EXTINT | 0x4] = "External Interrupt 4",
2873 [TT_EXTINT | 0x5] = "External Interrupt 5",
2874 [TT_EXTINT | 0x6] = "External Interrupt 6",
2875 [TT_EXTINT | 0x7] = "External Interrupt 7",
2876 [TT_EXTINT | 0x8] = "External Interrupt 8",
2877 [TT_EXTINT | 0x9] = "External Interrupt 9",
2878 [TT_EXTINT | 0xa] = "External Interrupt 10",
2879 [TT_EXTINT | 0xb] = "External Interrupt 11",
2880 [TT_EXTINT | 0xc] = "External Interrupt 12",
2881 [TT_EXTINT | 0xd] = "External Interrupt 13",
2882 [TT_EXTINT | 0xe] = "External Interrupt 14",
2883 [TT_EXTINT | 0xf] = "External Interrupt 15",
2884 [TT_TOVF] = "Tag Overflow",
2885 [TT_CODE_ACCESS] = "Instruction Access Error",
2886 [TT_DATA_ACCESS] = "Data Access Error",
2887 [TT_DIV_ZERO] = "Division By Zero",
2888 [TT_NCP_INSN] = "Coprocessor Disabled",
2889};
2890#endif
ee5bbe38 2891
91736d37 2892void do_interrupt(CPUState *env)
ee5bbe38 2893{
91736d37
BS		 2894 int cwp, intno = env->exception_index;
2895
2896#ifdef DEBUG_PCALL
2897 if (loglevel & CPU_LOG_INT) {
2898 static int count;
2899 const char *name;
2900
2901 if (intno < 0 || intno >= 0x100)
2902 name = "Unknown";
2903 else if (intno >= 0x80)
2904 name = "Trap Instruction";
2905 else {
2906 name = excp_names[intno];
2907 if (!name)
2908 name = "Unknown";
2909 }
2910
2911 fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
2912 count, name, intno,
2913 env->pc,
2914 env->npc, env->regwptr[6]);
2915 cpu_dump_state(env, logfile, fprintf, 0);
2916#if 0
2917 {
2918 int i;
2919 uint8_t *ptr;
2920
2921 fprintf(logfile, " code=");
2922 ptr = (uint8_t *)env->pc;
2923 for(i = 0; i < 16; i++) {
2924 fprintf(logfile, " %02x", ldub(ptr + i));
2925 }
2926 fprintf(logfile, "\n");
2927 }
2928#endif
2929 count++;
2930 }
2931#endif
2932#if !defined(CONFIG_USER_ONLY)
2933 if (env->psret == 0) {
2934 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
2935 env->exception_index);
2936 return;
2937 }
2938#endif
2939 env->psret = 0;
2940 cwp = cpu_cwp_dec(env, env->cwp - 1);
2941 cpu_set_cwp(env, cwp);
2942 env->regwptr[9] = env->pc;
2943 env->regwptr[10] = env->npc;
2944 env->psrps = env->psrs;
2945 env->psrs = 1;
2946 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
2947 env->pc = env->tbr;
2948 env->npc = env->pc + 4;
2949 env->exception_index = 0;
ee5bbe38 2950}
91736d37 2951#endif
ee5bbe38 2952
5fafdf24 2953#if !defined(CONFIG_USER_ONLY)
ee5bbe38 2954
d2889a3e
BS		 2955static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
2956 void *retaddr);
2957
ee5bbe38 2958#define MMUSUFFIX _mmu
d2889a3e 2959#define ALIGNED_ONLY
ee5bbe38
FB		 2960
2961#define SHIFT 0
2962#include "softmmu_template.h"
2963
2964#define SHIFT 1
2965#include "softmmu_template.h"
2966
2967#define SHIFT 2
2968#include "softmmu_template.h"
2969
2970#define SHIFT 3
2971#include "softmmu_template.h"
2972
c2bc0e38
BS		 2973/* XXX: make it generic ? */
2974static void cpu_restore_state2(void *retaddr)
2975{
2976 TranslationBlock *tb;
2977 unsigned long pc;
2978
2979 if (retaddr) {
2980 /* now we have a real cpu fault */
2981 pc = (unsigned long)retaddr;
2982 tb = tb_find_pc(pc);
2983 if (tb) {
2984 /* the PC is inside the translated code. It means that we have
2985 a virtual CPU fault */
2986 cpu_restore_state(tb, env, pc, (void *)(long)env->cond);
2987 }
2988 }
2989}
2990
d2889a3e
BS		 2991static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
2992 void *retaddr)
2993{
94554550 2994#ifdef DEBUG_UNALIGNED
c2bc0e38
BS		 2995 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
2996 "\n", addr, env->pc);
94554550 2997#endif
c2bc0e38 2998 cpu_restore_state2(retaddr);
94554550 2999 raise_exception(TT_UNALIGNED);
d2889a3e 3000}
ee5bbe38
FB		 3001
3002/* try to fill the TLB and return an exception if error. If retaddr is
3003 NULL, it means that the function was called in C code (i.e. not
3004 from generated code or from helper.c) */
3005/* XXX: fix it to restore all registers */
6ebbf390 3006void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
ee5bbe38 3007{
ee5bbe38 3008 int ret;
ee5bbe38
FB		 3009 CPUState *saved_env;
3010
3011 /* XXX: hack to restore env in all cases, even if not called from
3012 generated code */
3013 saved_env = env;
3014 env = cpu_single_env;
3015
6ebbf390 3016 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ee5bbe38 3017 if (ret) {
c2bc0e38 3018 cpu_restore_state2(retaddr);
ee5bbe38
FB		 3019 cpu_loop_exit();
3020 }
3021 env = saved_env;
3022}
3023
3024#endif
6c36d3fa
BS		 3025
3026#ifndef TARGET_SPARC64
5dcb6b91 3027void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
6c36d3fa
BS		 3028 int is_asi)
3029{
3030 CPUState *saved_env;
3031
3032 /* XXX: hack to restore env in all cases, even if not called from
3033 generated code */
3034 saved_env = env;
3035 env = cpu_single_env;
8543e2cf
BS		 3036#ifdef DEBUG_UNASSIGNED
3037 if (is_asi)
77f193da
BS		 3038 printf("Unassigned mem %s access to " TARGET_FMT_plx
3039 " asi 0x%02x from " TARGET_FMT_lx "\n",
8543e2cf
BS		 3040 is_exec ? "exec" : is_write ? "write" : "read", addr, is_asi,
3041 env->pc);
3042 else
3043 printf("Unassigned mem %s access to " TARGET_FMT_plx " from "
3044 TARGET_FMT_lx "\n",
3045 is_exec ? "exec" : is_write ? "write" : "read", addr, env->pc);
3046#endif
6c36d3fa 3047 if (env->mmuregs[3]) /* Fault status register */
0f8a249a 3048 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
6c36d3fa
BS		 3049 if (is_asi)
3050 env->mmuregs[3] |= 1 << 16;
3051 if (env->psrs)
3052 env->mmuregs[3] |= 1 << 5;
3053 if (is_exec)
3054 env->mmuregs[3] |= 1 << 6;
3055 if (is_write)
3056 env->mmuregs[3] |= 1 << 7;
3057 env->mmuregs[3] |= (5 << 2) | 2;
3058 env->mmuregs[4] = addr; /* Fault address register */
3059 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
1b2e93c1
BS		 3060 if (is_exec)
3061 raise_exception(TT_CODE_ACCESS);
3062 else
3063 raise_exception(TT_DATA_ACCESS);
6c36d3fa
BS		 3064 }
3065 env = saved_env;
3066}
3067#else
5dcb6b91 3068void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
6c36d3fa
BS		 3069 int is_asi)
3070{
3071#ifdef DEBUG_UNASSIGNED
3072 CPUState *saved_env;
3073
3074 /* XXX: hack to restore env in all cases, even if not called from
3075 generated code */
3076 saved_env = env;
3077 env = cpu_single_env;
77f193da
BS		 3078 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
3079 "\n", addr, env->pc);
6c36d3fa
BS		 3080 env = saved_env;
3081#endif
1b2e93c1
BS		 3082 if (is_exec)
3083 raise_exception(TT_CODE_ACCESS);
3084 else
3085 raise_exception(TT_DATA_ACCESS);
6c36d3fa
BS		 3086}
3087#endif
20c9f095 3088
f4b1a842
BS		 3089#ifdef TARGET_SPARC64
3090void helper_tick_set_count(void *opaque, uint64_t count)
3091{
3092#if !defined(CONFIG_USER_ONLY)
3093 cpu_tick_set_count(opaque, count);
3094#endif
3095}
3096
3097uint64_t helper_tick_get_count(void *opaque)
3098{
3099#if !defined(CONFIG_USER_ONLY)
3100 return cpu_tick_get_count(opaque);
3101#else
3102 return 0;
3103#endif
3104}
3105
3106void helper_tick_set_limit(void *opaque, uint64_t limit)
3107{
3108#if !defined(CONFIG_USER_ONLY)
3109 cpu_tick_set_limit(opaque, limit);
3110#endif
3111}
3112#endif
Qemu copy for testing