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Convert other float and VIS ops to TCG
[qemu.git] / target-sparc / op_helper.c
CommitLineData
e8af50a3 1#include "exec.h"
eed152bb 2#include "host-utils.h"
1a2fb1c0 3#include "helper.h"
e8af50a3 4
83469015 5//#define DEBUG_PCALL
e80cfcfc 6//#define DEBUG_MMU
952a328f 7//#define DEBUG_MXCC
94554550 8//#define DEBUG_UNALIGNED
6c36d3fa 9//#define DEBUG_UNASSIGNED
8543e2cf 10//#define DEBUG_ASI
e80cfcfc 11
952a328f
BS		 12#ifdef DEBUG_MMU
13#define DPRINTF_MMU(fmt, args...) \
14do { printf("MMU: " fmt , ##args); } while (0)
15#else
16#define DPRINTF_MMU(fmt, args...)
17#endif
18
19#ifdef DEBUG_MXCC
20#define DPRINTF_MXCC(fmt, args...) \
21do { printf("MXCC: " fmt , ##args); } while (0)
22#else
23#define DPRINTF_MXCC(fmt, args...)
24#endif
25
8543e2cf
BS		 26#ifdef DEBUG_ASI
27#define DPRINTF_ASI(fmt, args...) \
28do { printf("ASI: " fmt , ##args); } while (0)
29#else
30#define DPRINTF_ASI(fmt, args...)
31#endif
32
9d893301
FB		 33void raise_exception(int tt)
34{
35 env->exception_index = tt;
36 cpu_loop_exit();
3b46e624 37}
9d893301 38
1a2fb1c0 39void helper_trap(target_ulong nb_trap)
417454b0 40{
1a2fb1c0
BS		 41 env->exception_index = TT_TRAP + (nb_trap & 0x7f);
42 cpu_loop_exit();
43}
44
45void helper_trapcc(target_ulong nb_trap, target_ulong do_trap)
46{
47 if (do_trap) {
48 env->exception_index = TT_TRAP + (nb_trap & 0x7f);
49 cpu_loop_exit();
50 }
51}
52
44e7757c
BS		 53#define F_HELPER(name, p) void helper_f##name##p(void)
54
55#if defined(CONFIG_USER_ONLY)
56#define F_BINOP(name) \
57 F_HELPER(name, s) \
58 { \
59 FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \
60 } \
61 F_HELPER(name, d) \
62 { \
63 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
64 } \
65 F_HELPER(name, q) \
66 { \
67 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
68 }
69#else
70#define F_BINOP(name) \
71 F_HELPER(name, s) \
72 { \
73 FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \
74 } \
75 F_HELPER(name, d) \
76 { \
77 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
78 }
79#endif
80
81F_BINOP(add);
82F_BINOP(sub);
83F_BINOP(mul);
84F_BINOP(div);
85#undef F_BINOP
86
87void helper_fsmuld(void)
1a2fb1c0 88{
44e7757c
BS		 89 DT0 = float64_mul(float32_to_float64(FT0, &env->fp_status),
90 float32_to_float64(FT1, &env->fp_status),
91 &env->fp_status);
92}
1a2fb1c0 93
44e7757c
BS		 94#if defined(CONFIG_USER_ONLY)
95void helper_fdmulq(void)
96{
97 QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
98 float64_to_float128(DT1, &env->fp_status),
99 &env->fp_status);
100}
101#endif
0f8a249a 102
44e7757c
BS		 103F_HELPER(neg, s)
104{
105 FT0 = float32_chs(FT1);
417454b0
BS		 106}
107
44e7757c
BS		 108#ifdef TARGET_SPARC64
109F_HELPER(neg, d)
7e8c2b6c 110{
44e7757c 111 DT0 = float64_chs(DT1);
7e8c2b6c
BS		 112}
113
44e7757c
BS		 114#if defined(CONFIG_USER_ONLY)
115F_HELPER(neg, q)
116{
117 QT0 = float128_chs(QT1);
118}
119#endif
120#endif
121
122/* Integer to float conversion. */
123F_HELPER(ito, s)
a0c4cb4a 124{
ec230928 125 FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
a0c4cb4a
FB		 126}
127
44e7757c 128F_HELPER(ito, d)
a0c4cb4a 129{
ec230928 130 DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
a0c4cb4a 131}
9c2b428e
BS		 132
133#if defined(CONFIG_USER_ONLY)
44e7757c 134F_HELPER(ito, q)
9c2b428e
BS		 135{
136 QT0 = int32_to_float128(*((int32_t *)&FT1), &env->fp_status);
137}
138#endif
139
1e64e78d 140#ifdef TARGET_SPARC64
44e7757c 141F_HELPER(xto, s)
1e64e78d 142{
1e64e78d 143 FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
1e64e78d
BS		 144}
145
44e7757c 146F_HELPER(xto, d)
1e64e78d 147{
1e64e78d 148 DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
1e64e78d 149}
44e7757c
BS		 150#if defined(CONFIG_USER_ONLY)
151F_HELPER(xto, q)
152{
153 QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
154}
155#endif
156#endif
157#undef F_HELPER
158
159/* floating point conversion */
160void helper_fdtos(void)
161{
162 FT0 = float64_to_float32(DT1, &env->fp_status);
163}
164
165void helper_fstod(void)
166{
167 DT0 = float32_to_float64(FT1, &env->fp_status);
168}
9c2b428e
BS		 169
170#if defined(CONFIG_USER_ONLY)
44e7757c
BS		 171void helper_fqtos(void)
172{
173 FT0 = float128_to_float32(QT1, &env->fp_status);
174}
175
176void helper_fstoq(void)
177{
178 QT0 = float32_to_float128(FT1, &env->fp_status);
179}
180
181void helper_fqtod(void)
182{
183 DT0 = float128_to_float64(QT1, &env->fp_status);
184}
185
186void helper_fdtoq(void)
9c2b428e 187{
44e7757c 188 QT0 = float64_to_float128(DT1, &env->fp_status);
9c2b428e
BS		 189}
190#endif
44e7757c
BS		 191
192/* Float to integer conversion. */
193void helper_fstoi(void)
194{
195 *((int32_t *)&FT0) = float32_to_int32_round_to_zero(FT1, &env->fp_status);
196}
197
198void helper_fdtoi(void)
199{
200 *((int32_t *)&FT0) = float64_to_int32_round_to_zero(DT1, &env->fp_status);
201}
202
203#if defined(CONFIG_USER_ONLY)
204void helper_fqtoi(void)
205{
206 *((int32_t *)&FT0) = float128_to_int32_round_to_zero(QT1, &env->fp_status);
207}
1e64e78d 208#endif
44e7757c
BS		 209
210#ifdef TARGET_SPARC64
211void helper_fstox(void)
212{
213 *((int64_t *)&DT0) = float32_to_int64_round_to_zero(FT1, &env->fp_status);
214}
215
216void helper_fdtox(void)
217{
218 *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
219}
220
221#if defined(CONFIG_USER_ONLY)
222void helper_fqtox(void)
223{
224 *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);
225}
a0c4cb4a
FB		 226#endif
227
44e7757c
BS		 228void helper_faligndata(void)
229{
230 uint64_t tmp;
231
232 tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
233 tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
234 *((uint64_t *)&DT0) = tmp;
235}
236
237void helper_movl_FT0_0(void)
238{
239 *((uint32_t *)&FT0) = 0;
240}
241
242void helper_movl_DT0_0(void)
243{
244 *((uint64_t *)&DT0) = 0;
245}
246
247void helper_movl_FT0_1(void)
248{
249 *((uint32_t *)&FT0) = 0xffffffff;
250}
251
252void helper_movl_DT0_1(void)
253{
254 *((uint64_t *)&DT0) = 0xffffffffffffffffULL;
255}
256
257void helper_fnot(void)
258{
259 *(uint64_t *)&DT0 = ~*(uint64_t *)&DT1;
260}
261
262void helper_fnots(void)
263{
264 *(uint32_t *)&FT0 = ~*(uint32_t *)&FT1;
265}
266
267void helper_fnor(void)
268{
269 *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 | *(uint64_t *)&DT1);
270}
271
272void helper_fnors(void)
273{
274 *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 | *(uint32_t *)&FT1);
275}
276
277void helper_for(void)
278{
279 *(uint64_t *)&DT0 |= *(uint64_t *)&DT1;
280}
281
282void helper_fors(void)
283{
284 *(uint32_t *)&FT0 |= *(uint32_t *)&FT1;
285}
286
287void helper_fxor(void)
288{
289 *(uint64_t *)&DT0 ^= *(uint64_t *)&DT1;
290}
291
292void helper_fxors(void)
293{
294 *(uint32_t *)&FT0 ^= *(uint32_t *)&FT1;
295}
296
297void helper_fand(void)
298{
299 *(uint64_t *)&DT0 &= *(uint64_t *)&DT1;
300}
301
302void helper_fands(void)
303{
304 *(uint32_t *)&FT0 &= *(uint32_t *)&FT1;
305}
306
307void helper_fornot(void)
308{
309 *(uint64_t *)&DT0 = *(uint64_t *)&DT0 | ~*(uint64_t *)&DT1;
310}
311
312void helper_fornots(void)
313{
314 *(uint32_t *)&FT0 = *(uint32_t *)&FT0 | ~*(uint32_t *)&FT1;
315}
316
317void helper_fandnot(void)
318{
319 *(uint64_t *)&DT0 = *(uint64_t *)&DT0 & ~*(uint64_t *)&DT1;
320}
321
322void helper_fandnots(void)
323{
324 *(uint32_t *)&FT0 = *(uint32_t *)&FT0 & ~*(uint32_t *)&FT1;
325}
326
327void helper_fnand(void)
328{
329 *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 & *(uint64_t *)&DT1);
330}
331
332void helper_fnands(void)
333{
334 *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 & *(uint32_t *)&FT1);
335}
336
337void helper_fxnor(void)
338{
339 *(uint64_t *)&DT0 ^= ~*(uint64_t *)&DT1;
340}
341
342void helper_fxnors(void)
343{
344 *(uint32_t *)&FT0 ^= ~*(uint32_t *)&FT1;
345}
346
347#ifdef WORDS_BIGENDIAN
348#define VIS_B64(n) b[7 - (n)]
349#define VIS_W64(n) w[3 - (n)]
350#define VIS_SW64(n) sw[3 - (n)]
351#define VIS_L64(n) l[1 - (n)]
352#define VIS_B32(n) b[3 - (n)]
353#define VIS_W32(n) w[1 - (n)]
354#else
355#define VIS_B64(n) b[n]
356#define VIS_W64(n) w[n]
357#define VIS_SW64(n) sw[n]
358#define VIS_L64(n) l[n]
359#define VIS_B32(n) b[n]
360#define VIS_W32(n) w[n]
361#endif
362
363typedef union {
364 uint8_t b[8];
365 uint16_t w[4];
366 int16_t sw[4];
367 uint32_t l[2];
368 float64 d;
369} vis64;
370
371typedef union {
372 uint8_t b[4];
373 uint16_t w[2];
374 uint32_t l;
375 float32 f;
376} vis32;
377
378void helper_fpmerge(void)
379{
380 vis64 s, d;
381
382 s.d = DT0;
383 d.d = DT1;
384
385 // Reverse calculation order to handle overlap
386 d.VIS_B64(7) = s.VIS_B64(3);
387 d.VIS_B64(6) = d.VIS_B64(3);
388 d.VIS_B64(5) = s.VIS_B64(2);
389 d.VIS_B64(4) = d.VIS_B64(2);
390 d.VIS_B64(3) = s.VIS_B64(1);
391 d.VIS_B64(2) = d.VIS_B64(1);
392 d.VIS_B64(1) = s.VIS_B64(0);
393 //d.VIS_B64(0) = d.VIS_B64(0);
394
395 DT0 = d.d;
396}
397
398void helper_fmul8x16(void)
399{
400 vis64 s, d;
401 uint32_t tmp;
402
403 s.d = DT0;
404 d.d = DT1;
405
406#define PMUL(r) \
407 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
408 if ((tmp & 0xff) > 0x7f) \
409 tmp += 0x100; \
410 d.VIS_W64(r) = tmp >> 8;
411
412 PMUL(0);
413 PMUL(1);
414 PMUL(2);
415 PMUL(3);
416#undef PMUL
417
418 DT0 = d.d;
419}
420
421void helper_fmul8x16al(void)
422{
423 vis64 s, d;
424 uint32_t tmp;
425
426 s.d = DT0;
427 d.d = DT1;
428
429#define PMUL(r) \
430 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
431 if ((tmp & 0xff) > 0x7f) \
432 tmp += 0x100; \
433 d.VIS_W64(r) = tmp >> 8;
434
435 PMUL(0);
436 PMUL(1);
437 PMUL(2);
438 PMUL(3);
439#undef PMUL
440
441 DT0 = d.d;
442}
443
444void helper_fmul8x16au(void)
445{
446 vis64 s, d;
447 uint32_t tmp;
448
449 s.d = DT0;
450 d.d = DT1;
451
452#define PMUL(r) \
453 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
454 if ((tmp & 0xff) > 0x7f) \
455 tmp += 0x100; \
456 d.VIS_W64(r) = tmp >> 8;
457
458 PMUL(0);
459 PMUL(1);
460 PMUL(2);
461 PMUL(3);
462#undef PMUL
463
464 DT0 = d.d;
465}
466
467void helper_fmul8sux16(void)
468{
469 vis64 s, d;
470 uint32_t tmp;
471
472 s.d = DT0;
473 d.d = DT1;
474
475#define PMUL(r) \
476 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
477 if ((tmp & 0xff) > 0x7f) \
478 tmp += 0x100; \
479 d.VIS_W64(r) = tmp >> 8;
480
481 PMUL(0);
482 PMUL(1);
483 PMUL(2);
484 PMUL(3);
485#undef PMUL
486
487 DT0 = d.d;
488}
489
490void helper_fmul8ulx16(void)
491{
492 vis64 s, d;
493 uint32_t tmp;
494
495 s.d = DT0;
496 d.d = DT1;
497
498#define PMUL(r) \
499 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
500 if ((tmp & 0xff) > 0x7f) \
501 tmp += 0x100; \
502 d.VIS_W64(r) = tmp >> 8;
503
504 PMUL(0);
505 PMUL(1);
506 PMUL(2);
507 PMUL(3);
508#undef PMUL
509
510 DT0 = d.d;
511}
512
513void helper_fmuld8sux16(void)
514{
515 vis64 s, d;
516 uint32_t tmp;
517
518 s.d = DT0;
519 d.d = DT1;
520
521#define PMUL(r) \
522 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
523 if ((tmp & 0xff) > 0x7f) \
524 tmp += 0x100; \
525 d.VIS_L64(r) = tmp;
526
527 // Reverse calculation order to handle overlap
528 PMUL(1);
529 PMUL(0);
530#undef PMUL
531
532 DT0 = d.d;
533}
534
535void helper_fmuld8ulx16(void)
536{
537 vis64 s, d;
538 uint32_t tmp;
539
540 s.d = DT0;
541 d.d = DT1;
542
543#define PMUL(r) \
544 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
545 if ((tmp & 0xff) > 0x7f) \
546 tmp += 0x100; \
547 d.VIS_L64(r) = tmp;
548
549 // Reverse calculation order to handle overlap
550 PMUL(1);
551 PMUL(0);
552#undef PMUL
553
554 DT0 = d.d;
555}
556
557void helper_fexpand(void)
558{
559 vis32 s;
560 vis64 d;
561
562 s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
563 d.d = DT1;
564 d.VIS_L64(0) = s.VIS_W32(0) << 4;
565 d.VIS_L64(1) = s.VIS_W32(1) << 4;
566 d.VIS_L64(2) = s.VIS_W32(2) << 4;
567 d.VIS_L64(3) = s.VIS_W32(3) << 4;
568
569 DT0 = d.d;
570}
571
572#define VIS_HELPER(name, F) \
573 void name##16(void) \
574 { \
575 vis64 s, d; \
576 \
577 s.d = DT0; \
578 d.d = DT1; \
579 \
580 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
581 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
582 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
583 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
584 \
585 DT0 = d.d; \
586 } \
587 \
588 void name##16s(void) \
589 { \
590 vis32 s, d; \
591 \
592 s.f = FT0; \
593 d.f = FT1; \
594 \
595 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
596 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
597 \
598 FT0 = d.f; \
599 } \
600 \
601 void name##32(void) \
602 { \
603 vis64 s, d; \
604 \
605 s.d = DT0; \
606 d.d = DT1; \
607 \
608 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
609 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
610 \
611 DT0 = d.d; \
612 } \
613 \
614 void name##32s(void) \
615 { \
616 vis32 s, d; \
617 \
618 s.f = FT0; \
619 d.f = FT1; \
620 \
621 d.l = F(d.l, s.l); \
622 \
623 FT0 = d.f; \
624 }
625
626#define FADD(a, b) ((a) + (b))
627#define FSUB(a, b) ((a) - (b))
628VIS_HELPER(helper_fpadd, FADD)
629VIS_HELPER(helper_fpsub, FSUB)
630
631#define VIS_CMPHELPER(name, F) \
632 void name##16(void) \
633 { \
634 vis64 s, d; \
635 \
636 s.d = DT0; \
637 d.d = DT1; \
638 \
639 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
640 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
641 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
642 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
643 \
644 DT0 = d.d; \
645 } \
646 \
647 void name##32(void) \
648 { \
649 vis64 s, d; \
650 \
651 s.d = DT0; \
652 d.d = DT1; \
653 \
654 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
655 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
656 \
657 DT0 = d.d; \
658 }
659
660#define FCMPGT(a, b) ((a) > (b))
661#define FCMPEQ(a, b) ((a) == (b))
662#define FCMPLE(a, b) ((a) <= (b))
663#define FCMPNE(a, b) ((a) != (b))
664
665VIS_CMPHELPER(helper_fcmpgt, FCMPGT)
666VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)
667VIS_CMPHELPER(helper_fcmple, FCMPLE)
668VIS_CMPHELPER(helper_fcmpne, FCMPNE)
669#endif
670
671void helper_check_ieee_exceptions(void)
672{
673 target_ulong status;
674
675 status = get_float_exception_flags(&env->fp_status);
676 if (status) {
677 /* Copy IEEE 754 flags into FSR */
678 if (status & float_flag_invalid)
679 env->fsr |= FSR_NVC;
680 if (status & float_flag_overflow)
681 env->fsr |= FSR_OFC;
682 if (status & float_flag_underflow)
683 env->fsr |= FSR_UFC;
684 if (status & float_flag_divbyzero)
685 env->fsr |= FSR_DZC;
686 if (status & float_flag_inexact)
687 env->fsr |= FSR_NXC;
688
689 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
690 /* Unmasked exception, generate a trap */
691 env->fsr |= FSR_FTT_IEEE_EXCP;
692 raise_exception(TT_FP_EXCP);
693 } else {
694 /* Accumulate exceptions */
695 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
696 }
697 }
698}
699
700void helper_clear_float_exceptions(void)
701{
702 set_float_exception_flags(0, &env->fp_status);
703}
704
7e8c2b6c 705void helper_fabss(void)
e8af50a3 706{
7a0e1f41 707 FT0 = float32_abs(FT1);
e8af50a3
FB		 708}
709
3475187d 710#ifdef TARGET_SPARC64
7e8c2b6c 711void helper_fabsd(void)
3475187d
FB		 712{
713 DT0 = float64_abs(DT1);
714}
1f587329
BS		 715
716#if defined(CONFIG_USER_ONLY)
7e8c2b6c 717void helper_fabsq(void)
1f587329
BS		 718{
719 QT0 = float128_abs(QT1);
720}
721#endif
3475187d
FB		 722#endif
723
7e8c2b6c 724void helper_fsqrts(void)
e8af50a3 725{
7a0e1f41 726 FT0 = float32_sqrt(FT1, &env->fp_status);
e8af50a3
FB		 727}
728
7e8c2b6c 729void helper_fsqrtd(void)
e8af50a3 730{
7a0e1f41 731 DT0 = float64_sqrt(DT1, &env->fp_status);
e8af50a3
FB		 732}
733
1f587329 734#if defined(CONFIG_USER_ONLY)
7e8c2b6c 735void helper_fsqrtq(void)
1f587329 736{
1f587329 737 QT0 = float128_sqrt(QT1, &env->fp_status);
1f587329
BS		 738}
739#endif
740
417454b0 741#define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
7e8c2b6c 742 void glue(helper_, name) (void) \
65ce8c2f 743 { \
1a2fb1c0
BS		 744 target_ulong new_fsr; \
745 \
65ce8c2f
FB		 746 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
747 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
748 case float_relation_unordered: \
1a2fb1c0 749 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
417454b0 750 if ((env->fsr & FSR_NVM) || TRAP) { \
1a2fb1c0 751 env->fsr |= new_fsr; \
417454b0
BS		 752 env->fsr |= FSR_NVC; \
753 env->fsr |= FSR_FTT_IEEE_EXCP; \
65ce8c2f
FB		 754 raise_exception(TT_FP_EXCP); \
755 } else { \
756 env->fsr |= FSR_NVA; \
757 } \
758 break; \
759 case float_relation_less: \
1a2fb1c0 760 new_fsr = FSR_FCC0 << FS; \
65ce8c2f
FB		 761 break; \
762 case float_relation_greater: \
1a2fb1c0 763 new_fsr = FSR_FCC1 << FS; \
65ce8c2f
FB		 764 break; \
765 default: \
1a2fb1c0 766 new_fsr = 0; \
65ce8c2f
FB		 767 break; \
768 } \
1a2fb1c0 769 env->fsr |= new_fsr; \
e8af50a3 770 }
e8af50a3 771
417454b0
BS		 772GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0);
773GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
774
775GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1);
776GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
3475187d 777
1f587329
BS		 778#ifdef CONFIG_USER_ONLY
779GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
780GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
781#endif
782
3475187d 783#ifdef TARGET_SPARC64
417454b0
BS		 784GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0);
785GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
786
787GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0);
788GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
789
790GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0);
791GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
792
793GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1);
794GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
3475187d 795
417454b0
BS		 796GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1);
797GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
3475187d 798
417454b0
BS		 799GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1);
800GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
1f587329
BS		 801#ifdef CONFIG_USER_ONLY
802GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
803GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
804GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
805GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
806GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
807GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
808#endif
3475187d
FB		 809#endif
810
1a2fb1c0 811#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && defined(DEBUG_MXCC)
952a328f
BS		 812static void dump_mxcc(CPUState *env)
813{
814 printf("mxccdata: %016llx %016llx %016llx %016llx\n",
815 env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]);
816 printf("mxccregs: %016llx %016llx %016llx %016llx\n"
817 " %016llx %016llx %016llx %016llx\n",
818 env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3],
819 env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]);
820}
821#endif
822
1a2fb1c0
BS		 823#if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
824 && defined(DEBUG_ASI)
825static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
826 uint64_t r1)
8543e2cf
BS		 827{
828 switch (size)
829 {
830 case 1:
1a2fb1c0
BS		 831 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
832 addr, asi, r1 & 0xff);
8543e2cf
BS		 833 break;
834 case 2:
1a2fb1c0
BS		 835 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
836 addr, asi, r1 & 0xffff);
8543e2cf
BS		 837 break;
838 case 4:
1a2fb1c0
BS		 839 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
840 addr, asi, r1 & 0xffffffff);
8543e2cf
BS		 841 break;
842 case 8:
1a2fb1c0
BS		 843 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
844 addr, asi, r1);
8543e2cf
BS		 845 break;
846 }
847}
848#endif
849
1a2fb1c0
BS		 850#ifndef TARGET_SPARC64
851#ifndef CONFIG_USER_ONLY
852uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
e8af50a3 853{
1a2fb1c0 854 uint64_t ret = 0;
8543e2cf 855#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
1a2fb1c0 856 uint32_t last_addr = addr;
952a328f 857#endif
e80cfcfc
FB		 858
859 switch (asi) {
6c36d3fa 860 case 2: /* SuperSparc MXCC registers */
1a2fb1c0 861 switch (addr) {
952a328f 862 case 0x01c00a00: /* MXCC control register */
1a2fb1c0
BS		 863 if (size == 8)
864 ret = env->mxccregs[3];
865 else
866 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 867 break;
868 case 0x01c00a04: /* MXCC control register */
869 if (size == 4)
870 ret = env->mxccregs[3];
871 else
1a2fb1c0 872 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f 873 break;
295db113
BS		 874 case 0x01c00c00: /* Module reset register */
875 if (size == 8) {
1a2fb1c0 876 ret = env->mxccregs[5];
295db113
BS		 877 // should we do something here?
878 } else
1a2fb1c0 879 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
295db113 880 break;
952a328f 881 case 0x01c00f00: /* MBus port address register */
1a2fb1c0
BS		 882 if (size == 8)
883 ret = env->mxccregs[7];
884 else
885 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 886 break;
887 default:
1a2fb1c0 888 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
952a328f
BS		 889 break;
890 }
1a2fb1c0
BS		 891 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, addr = %08x -> ret = %08x,"
892 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
952a328f
BS		 893#ifdef DEBUG_MXCC
894 dump_mxcc(env);
895#endif
6c36d3fa 896 break;
e8af50a3 897 case 3: /* MMU probe */
0f8a249a
BS		 898 {
899 int mmulev;
900
1a2fb1c0 901 mmulev = (addr >> 8) & 15;
0f8a249a
BS		 902 if (mmulev > 4)
903 ret = 0;
1a2fb1c0
BS		 904 else
905 ret = mmu_probe(env, addr, mmulev);
906 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
907 addr, mmulev, ret);
0f8a249a
BS		 908 }
909 break;
e8af50a3 910 case 4: /* read MMU regs */
0f8a249a 911 {
1a2fb1c0 912 int reg = (addr >> 8) & 0x1f;
3b46e624 913
0f8a249a
BS		 914 ret = env->mmuregs[reg];
915 if (reg == 3) /* Fault status cleared on read */
3dd9a152
BS		 916 env->mmuregs[3] = 0;
917 else if (reg == 0x13) /* Fault status read */
918 ret = env->mmuregs[3];
919 else if (reg == 0x14) /* Fault address read */
920 ret = env->mmuregs[4];
1a2fb1c0 921 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
0f8a249a
BS		 922 }
923 break;
045380be
BS		 924 case 5: // Turbosparc ITLB Diagnostic
925 case 6: // Turbosparc DTLB Diagnostic
926 case 7: // Turbosparc IOTLB Diagnostic
927 break;
6c36d3fa
BS		 928 case 9: /* Supervisor code access */
929 switch(size) {
930 case 1:
1a2fb1c0 931 ret = ldub_code(addr);
6c36d3fa
BS		 932 break;
933 case 2:
1a2fb1c0 934 ret = lduw_code(addr & ~1);
6c36d3fa
BS		 935 break;
936 default:
937 case 4:
1a2fb1c0 938 ret = ldl_code(addr & ~3);
6c36d3fa
BS		 939 break;
940 case 8:
1a2fb1c0 941 ret = ldq_code(addr & ~7);
6c36d3fa
BS		 942 break;
943 }
944 break;
81ad8ba2
BS		 945 case 0xa: /* User data access */
946 switch(size) {
947 case 1:
1a2fb1c0 948 ret = ldub_user(addr);
81ad8ba2
BS		 949 break;
950 case 2:
1a2fb1c0 951 ret = lduw_user(addr & ~1);
81ad8ba2
BS		 952 break;
953 default:
954 case 4:
1a2fb1c0 955 ret = ldl_user(addr & ~3);
81ad8ba2
BS		 956 break;
957 case 8:
1a2fb1c0 958 ret = ldq_user(addr & ~7);
81ad8ba2
BS		 959 break;
960 }
961 break;
962 case 0xb: /* Supervisor data access */
963 switch(size) {
964 case 1:
1a2fb1c0 965 ret = ldub_kernel(addr);
81ad8ba2
BS		 966 break;
967 case 2:
1a2fb1c0 968 ret = lduw_kernel(addr & ~1);
81ad8ba2
BS		 969 break;
970 default:
971 case 4:
1a2fb1c0 972 ret = ldl_kernel(addr & ~3);
81ad8ba2
BS		 973 break;
974 case 8:
1a2fb1c0 975 ret = ldq_kernel(addr & ~7);
81ad8ba2
BS		 976 break;
977 }
978 break;
6c36d3fa
BS		 979 case 0xc: /* I-cache tag */
980 case 0xd: /* I-cache data */
981 case 0xe: /* D-cache tag */
982 case 0xf: /* D-cache data */
983 break;
984 case 0x20: /* MMU passthrough */
02aab46a
FB		 985 switch(size) {
986 case 1:
1a2fb1c0 987 ret = ldub_phys(addr);
02aab46a
FB		 988 break;
989 case 2:
1a2fb1c0 990 ret = lduw_phys(addr & ~1);
02aab46a
FB		 991 break;
992 default:
993 case 4:
1a2fb1c0 994 ret = ldl_phys(addr & ~3);
02aab46a 995 break;
9e61bde5 996 case 8:
1a2fb1c0 997 ret = ldq_phys(addr & ~7);
0f8a249a 998 break;
02aab46a 999 }
0f8a249a 1000 break;
7d85892b 1001 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
5dcb6b91
BS		 1002 switch(size) {
1003 case 1:
1a2fb1c0 1004 ret = ldub_phys((target_phys_addr_t)addr
5dcb6b91
BS		 1005 | ((target_phys_addr_t)(asi & 0xf) << 32));
1006 break;
1007 case 2:
1a2fb1c0 1008 ret = lduw_phys((target_phys_addr_t)(addr & ~1)
5dcb6b91
BS		 1009 | ((target_phys_addr_t)(asi & 0xf) << 32));
1010 break;
1011 default:
1012 case 4:
1a2fb1c0 1013 ret = ldl_phys((target_phys_addr_t)(addr & ~3)
5dcb6b91
BS		 1014 | ((target_phys_addr_t)(asi & 0xf) << 32));
1015 break;
1016 case 8:
1a2fb1c0 1017 ret = ldq_phys((target_phys_addr_t)(addr & ~7)
5dcb6b91 1018 | ((target_phys_addr_t)(asi & 0xf) << 32));
0f8a249a 1019 break;
5dcb6b91 1020 }
0f8a249a 1021 break;
045380be
BS		 1022 case 0x30: // Turbosparc secondary cache diagnostic
1023 case 0x31: // Turbosparc RAM snoop
1024 case 0x32: // Turbosparc page table descriptor diagnostic
666c87aa
BS		 1025 case 0x39: /* data cache diagnostic register */
1026 ret = 0;
1027 break;
045380be 1028 case 8: /* User code access, XXX */
e8af50a3 1029 default:
1a2fb1c0 1030 do_unassigned_access(addr, 0, 0, asi);
0f8a249a
BS		 1031 ret = 0;
1032 break;
e8af50a3 1033 }
81ad8ba2
BS		 1034 if (sign) {
1035 switch(size) {
1036 case 1:
1a2fb1c0 1037 ret = (int8_t) ret;
e32664fb 1038 break;
81ad8ba2 1039 case 2:
1a2fb1c0
BS		 1040 ret = (int16_t) ret;
1041 break;
1042 case 4:
1043 ret = (int32_t) ret;
e32664fb 1044 break;
81ad8ba2 1045 default:
81ad8ba2
BS		 1046 break;
1047 }
1048 }
8543e2cf 1049#ifdef DEBUG_ASI
1a2fb1c0 1050 dump_asi("read ", last_addr, asi, size, ret);
8543e2cf 1051#endif
1a2fb1c0 1052 return ret;
e8af50a3
FB		 1053}
1054
1a2fb1c0 1055void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
e8af50a3
FB		 1056{
1057 switch(asi) {
6c36d3fa 1058 case 2: /* SuperSparc MXCC registers */
1a2fb1c0 1059 switch (addr) {
952a328f
BS		 1060 case 0x01c00000: /* MXCC stream data register 0 */
1061 if (size == 8)
1a2fb1c0 1062 env->mxccdata[0] = val;
952a328f 1063 else
1a2fb1c0 1064 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1065 break;
1066 case 0x01c00008: /* MXCC stream data register 1 */
1067 if (size == 8)
1a2fb1c0 1068 env->mxccdata[1] = val;
952a328f 1069 else
1a2fb1c0 1070 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1071 break;
1072 case 0x01c00010: /* MXCC stream data register 2 */
1073 if (size == 8)
1a2fb1c0 1074 env->mxccdata[2] = val;
952a328f 1075 else
1a2fb1c0 1076 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1077 break;
1078 case 0x01c00018: /* MXCC stream data register 3 */
1079 if (size == 8)
1a2fb1c0 1080 env->mxccdata[3] = val;
952a328f 1081 else
1a2fb1c0 1082 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1083 break;
1084 case 0x01c00100: /* MXCC stream source */
1085 if (size == 8)
1a2fb1c0 1086 env->mxccregs[0] = val;
952a328f 1087 else
1a2fb1c0 1088 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1089 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0);
1090 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8);
1091 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16);
1092 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 24);
1093 break;
1094 case 0x01c00200: /* MXCC stream destination */
1095 if (size == 8)
1a2fb1c0 1096 env->mxccregs[1] = val;
952a328f 1097 else
1a2fb1c0 1098 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1099 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]);
1100 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]);
1101 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]);
1102 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, env->mxccdata[3]);
1103 break;
1104 case 0x01c00a00: /* MXCC control register */
1105 if (size == 8)
1a2fb1c0 1106 env->mxccregs[3] = val;
952a328f 1107 else
1a2fb1c0 1108 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1109 break;
1110 case 0x01c00a04: /* MXCC control register */
1111 if (size == 4)
1a2fb1c0 1112 env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) | val;
952a328f 1113 else
1a2fb1c0 1114 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1115 break;
1116 case 0x01c00e00: /* MXCC error register */
bbf7d96b 1117 // writing a 1 bit clears the error
952a328f 1118 if (size == 8)
1a2fb1c0 1119 env->mxccregs[6] &= ~val;
952a328f 1120 else
1a2fb1c0 1121 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1122 break;
1123 case 0x01c00f00: /* MBus port address register */
1124 if (size == 8)
1a2fb1c0 1125 env->mxccregs[7] = val;
952a328f 1126 else
1a2fb1c0 1127 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1128 break;
1129 default:
1a2fb1c0 1130 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
952a328f
BS		 1131 break;
1132 }
1a2fb1c0 1133 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi, size, addr, val);
952a328f
BS		 1134#ifdef DEBUG_MXCC
1135 dump_mxcc(env);
1136#endif
6c36d3fa 1137 break;
e8af50a3 1138 case 3: /* MMU flush */
0f8a249a
BS		 1139 {
1140 int mmulev;
e80cfcfc 1141
1a2fb1c0 1142 mmulev = (addr >> 8) & 15;
952a328f 1143 DPRINTF_MMU("mmu flush level %d\n", mmulev);
0f8a249a
BS		 1144 switch (mmulev) {
1145 case 0: // flush page
1a2fb1c0 1146 tlb_flush_page(env, addr & 0xfffff000);
0f8a249a
BS		 1147 break;
1148 case 1: // flush segment (256k)
1149 case 2: // flush region (16M)
1150 case 3: // flush context (4G)
1151 case 4: // flush entire
1152 tlb_flush(env, 1);
1153 break;
1154 default:
1155 break;
1156 }
55754d9e 1157#ifdef DEBUG_MMU
0f8a249a 1158 dump_mmu(env);
55754d9e 1159#endif
0f8a249a 1160 }
8543e2cf 1161 break;
e8af50a3 1162 case 4: /* write MMU regs */
0f8a249a 1163 {
1a2fb1c0 1164 int reg = (addr >> 8) & 0x1f;
0f8a249a 1165 uint32_t oldreg;
3b46e624 1166
0f8a249a 1167 oldreg = env->mmuregs[reg];
55754d9e 1168 switch(reg) {
3deaeab7 1169 case 0: // Control Register
3dd9a152 1170 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
1a2fb1c0 1171 (val & 0x00ffffff);
0f8a249a
BS		 1172 // Mappings generated during no-fault mode or MMU
1173 // disabled mode are invalid in normal mode
3dd9a152
BS		 1174 if ((oldreg & (MMU_E | MMU_NF | env->mmu_bm)) !=
1175 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->mmu_bm)))
55754d9e
FB		 1176 tlb_flush(env, 1);
1177 break;
3deaeab7 1178 case 1: // Context Table Pointer Register
1a2fb1c0 1179 env->mmuregs[reg] = val & env->mmu_ctpr_mask;
3deaeab7
BS		 1180 break;
1181 case 2: // Context Register
1a2fb1c0 1182 env->mmuregs[reg] = val & env->mmu_cxr_mask;
55754d9e
FB		 1183 if (oldreg != env->mmuregs[reg]) {
1184 /* we flush when the MMU context changes because
1185 QEMU has no MMU context support */
1186 tlb_flush(env, 1);
1187 }
1188 break;
3deaeab7
BS		 1189 case 3: // Synchronous Fault Status Register with Clear
1190 case 4: // Synchronous Fault Address Register
1191 break;
1192 case 0x10: // TLB Replacement Control Register
1a2fb1c0 1193 env->mmuregs[reg] = val & env->mmu_trcr_mask;
55754d9e 1194 break;
3deaeab7 1195 case 0x13: // Synchronous Fault Status Register with Read and Clear
1a2fb1c0 1196 env->mmuregs[3] = val & env->mmu_sfsr_mask;
3dd9a152 1197 break;
3deaeab7 1198 case 0x14: // Synchronous Fault Address Register
1a2fb1c0 1199 env->mmuregs[4] = val;
3dd9a152 1200 break;
55754d9e 1201 default:
1a2fb1c0 1202 env->mmuregs[reg] = val;
55754d9e
FB		 1203 break;
1204 }
55754d9e 1205 if (oldreg != env->mmuregs[reg]) {
952a328f 1206 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
55754d9e 1207 }
952a328f 1208#ifdef DEBUG_MMU
0f8a249a 1209 dump_mmu(env);
55754d9e 1210#endif
0f8a249a 1211 }
8543e2cf 1212 break;
045380be
BS		 1213 case 5: // Turbosparc ITLB Diagnostic
1214 case 6: // Turbosparc DTLB Diagnostic
1215 case 7: // Turbosparc IOTLB Diagnostic
1216 break;
81ad8ba2
BS		 1217 case 0xa: /* User data access */
1218 switch(size) {
1219 case 1:
1a2fb1c0 1220 stb_user(addr, val);
81ad8ba2
BS		 1221 break;
1222 case 2:
1a2fb1c0 1223 stw_user(addr & ~1, val);
81ad8ba2
BS		 1224 break;
1225 default:
1226 case 4:
1a2fb1c0 1227 stl_user(addr & ~3, val);
81ad8ba2
BS		 1228 break;
1229 case 8:
1a2fb1c0 1230 stq_user(addr & ~7, val);
81ad8ba2
BS		 1231 break;
1232 }
1233 break;
1234 case 0xb: /* Supervisor data access */
1235 switch(size) {
1236 case 1:
1a2fb1c0 1237 stb_kernel(addr, val);
81ad8ba2
BS		 1238 break;
1239 case 2:
1a2fb1c0 1240 stw_kernel(addr & ~1, val);
81ad8ba2
BS		 1241 break;
1242 default:
1243 case 4:
1a2fb1c0 1244 stl_kernel(addr & ~3, val);
81ad8ba2
BS		 1245 break;
1246 case 8:
1a2fb1c0 1247 stq_kernel(addr & ~7, val);
81ad8ba2
BS		 1248 break;
1249 }
1250 break;
6c36d3fa
BS		 1251 case 0xc: /* I-cache tag */
1252 case 0xd: /* I-cache data */
1253 case 0xe: /* D-cache tag */
1254 case 0xf: /* D-cache data */
1255 case 0x10: /* I/D-cache flush page */
1256 case 0x11: /* I/D-cache flush segment */
1257 case 0x12: /* I/D-cache flush region */
1258 case 0x13: /* I/D-cache flush context */
1259 case 0x14: /* I/D-cache flush user */
1260 break;
e80cfcfc 1261 case 0x17: /* Block copy, sta access */
0f8a249a 1262 {
1a2fb1c0
BS		 1263 // val = src
1264 // addr = dst
0f8a249a 1265 // copy 32 bytes
6c36d3fa 1266 unsigned int i;
1a2fb1c0 1267 uint32_t src = val & ~3, dst = addr & ~3, temp;
3b46e624 1268
6c36d3fa
BS		 1269 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
1270 temp = ldl_kernel(src);
1271 stl_kernel(dst, temp);
1272 }
0f8a249a 1273 }
8543e2cf 1274 break;
e80cfcfc 1275 case 0x1f: /* Block fill, stda access */
0f8a249a 1276 {
1a2fb1c0
BS		 1277 // addr = dst
1278 // fill 32 bytes with val
6c36d3fa 1279 unsigned int i;
1a2fb1c0 1280 uint32_t dst = addr & 7;
6c36d3fa
BS		 1281
1282 for (i = 0; i < 32; i += 8, dst += 8)
1283 stq_kernel(dst, val);
0f8a249a 1284 }
8543e2cf 1285 break;
6c36d3fa 1286 case 0x20: /* MMU passthrough */
0f8a249a 1287 {
02aab46a
FB		 1288 switch(size) {
1289 case 1:
1a2fb1c0 1290 stb_phys(addr, val);
02aab46a
FB		 1291 break;
1292 case 2:
1a2fb1c0 1293 stw_phys(addr & ~1, val);
02aab46a
FB		 1294 break;
1295 case 4:
1296 default:
1a2fb1c0 1297 stl_phys(addr & ~3, val);
02aab46a 1298 break;
9e61bde5 1299 case 8:
1a2fb1c0 1300 stq_phys(addr & ~7, val);
9e61bde5 1301 break;
02aab46a 1302 }
0f8a249a 1303 }
8543e2cf 1304 break;
045380be 1305 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
0f8a249a 1306 {
5dcb6b91
BS		 1307 switch(size) {
1308 case 1:
1a2fb1c0
BS		 1309 stb_phys((target_phys_addr_t)addr
1310 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1311 break;
1312 case 2:
1a2fb1c0
BS		 1313 stw_phys((target_phys_addr_t)(addr & ~1)
1314 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1315 break;
1316 case 4:
1317 default:
1a2fb1c0
BS		 1318 stl_phys((target_phys_addr_t)(addr & ~3)
1319 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1320 break;
1321 case 8:
1a2fb1c0
BS		 1322 stq_phys((target_phys_addr_t)(addr & ~7)
1323 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1324 break;
1325 }
0f8a249a 1326 }
8543e2cf 1327 break;
045380be
BS		 1328 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
1329 case 0x31: // store buffer data, Ross RT620 I-cache flush or
1330 // Turbosparc snoop RAM
1331 case 0x32: // store buffer control or Turbosparc page table descriptor diagnostic
6c36d3fa
BS		 1332 case 0x36: /* I-cache flash clear */
1333 case 0x37: /* D-cache flash clear */
666c87aa
BS		 1334 case 0x38: /* breakpoint diagnostics */
1335 case 0x4c: /* breakpoint action */
6c36d3fa 1336 break;
045380be 1337 case 8: /* User code access, XXX */
6c36d3fa 1338 case 9: /* Supervisor code access, XXX */
e8af50a3 1339 default:
1a2fb1c0 1340 do_unassigned_access(addr, 1, 0, asi);
8543e2cf 1341 break;
e8af50a3 1342 }
8543e2cf 1343#ifdef DEBUG_ASI
1a2fb1c0 1344 dump_asi("write", addr, asi, size, val);
8543e2cf 1345#endif
e8af50a3
FB		 1346}
1347
81ad8ba2
BS		 1348#endif /* CONFIG_USER_ONLY */
1349#else /* TARGET_SPARC64 */
1350
1351#ifdef CONFIG_USER_ONLY
1a2fb1c0 1352uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
81ad8ba2
BS		 1353{
1354 uint64_t ret = 0;
1a2fb1c0
BS		 1355#if defined(DEBUG_ASI)
1356 target_ulong last_addr = addr;
1357#endif
81ad8ba2
BS		 1358
1359 if (asi < 0x80)
1360 raise_exception(TT_PRIV_ACT);
1361
1362 switch (asi) {
1363 case 0x80: // Primary
1364 case 0x82: // Primary no-fault
1365 case 0x88: // Primary LE
1366 case 0x8a: // Primary no-fault LE
1367 {
1368 switch(size) {
1369 case 1:
1a2fb1c0 1370 ret = ldub_raw(addr);
81ad8ba2
BS		 1371 break;
1372 case 2:
1a2fb1c0 1373 ret = lduw_raw(addr & ~1);
81ad8ba2
BS		 1374 break;
1375 case 4:
1a2fb1c0 1376 ret = ldl_raw(addr & ~3);
81ad8ba2
BS		 1377 break;
1378 default:
1379 case 8:
1a2fb1c0 1380 ret = ldq_raw(addr & ~7);
81ad8ba2
BS		 1381 break;
1382 }
1383 }
1384 break;
1385 case 0x81: // Secondary
1386 case 0x83: // Secondary no-fault
1387 case 0x89: // Secondary LE
1388 case 0x8b: // Secondary no-fault LE
1389 // XXX
1390 break;
1391 default:
1392 break;
1393 }
1394
1395 /* Convert from little endian */
1396 switch (asi) {
1397 case 0x88: // Primary LE
1398 case 0x89: // Secondary LE
1399 case 0x8a: // Primary no-fault LE
1400 case 0x8b: // Secondary no-fault LE
1401 switch(size) {
1402 case 2:
1403 ret = bswap16(ret);
e32664fb 1404 break;
81ad8ba2
BS		 1405 case 4:
1406 ret = bswap32(ret);
e32664fb 1407 break;
81ad8ba2
BS		 1408 case 8:
1409 ret = bswap64(ret);
e32664fb 1410 break;
81ad8ba2
BS		 1411 default:
1412 break;
1413 }
1414 default:
1415 break;
1416 }
1417
1418 /* Convert to signed number */
1419 if (sign) {
1420 switch(size) {
1421 case 1:
1422 ret = (int8_t) ret;
e32664fb 1423 break;
81ad8ba2
BS		 1424 case 2:
1425 ret = (int16_t) ret;
e32664fb 1426 break;
81ad8ba2
BS		 1427 case 4:
1428 ret = (int32_t) ret;
e32664fb 1429 break;
81ad8ba2
BS		 1430 default:
1431 break;
1432 }
1433 }
1a2fb1c0
BS		 1434#ifdef DEBUG_ASI
1435 dump_asi("read ", last_addr, asi, size, ret);
1436#endif
1437 return ret;
81ad8ba2
BS		 1438}
1439
1a2fb1c0 1440void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
81ad8ba2 1441{
1a2fb1c0
BS		 1442#ifdef DEBUG_ASI
1443 dump_asi("write", addr, asi, size, val);
1444#endif
81ad8ba2
BS		 1445 if (asi < 0x80)
1446 raise_exception(TT_PRIV_ACT);
1447
1448 /* Convert to little endian */
1449 switch (asi) {
1450 case 0x88: // Primary LE
1451 case 0x89: // Secondary LE
1452 switch(size) {
1453 case 2:
1a2fb1c0 1454 addr = bswap16(addr);
e32664fb 1455 break;
81ad8ba2 1456 case 4:
1a2fb1c0 1457 addr = bswap32(addr);
e32664fb 1458 break;
81ad8ba2 1459 case 8:
1a2fb1c0 1460 addr = bswap64(addr);
e32664fb 1461 break;
81ad8ba2
BS		 1462 default:
1463 break;
1464 }
1465 default:
1466 break;
1467 }
1468
1469 switch(asi) {
1470 case 0x80: // Primary
1471 case 0x88: // Primary LE
1472 {
1473 switch(size) {
1474 case 1:
1a2fb1c0 1475 stb_raw(addr, val);
81ad8ba2
BS		 1476 break;
1477 case 2:
1a2fb1c0 1478 stw_raw(addr & ~1, val);
81ad8ba2
BS		 1479 break;
1480 case 4:
1a2fb1c0 1481 stl_raw(addr & ~3, val);
81ad8ba2
BS		 1482 break;
1483 case 8:
1484 default:
1a2fb1c0 1485 stq_raw(addr & ~7, val);
81ad8ba2
BS		 1486 break;
1487 }
1488 }
1489 break;
1490 case 0x81: // Secondary
1491 case 0x89: // Secondary LE
1492 // XXX
1493 return;
1494
1495 case 0x82: // Primary no-fault, RO
1496 case 0x83: // Secondary no-fault, RO
1497 case 0x8a: // Primary no-fault LE, RO
1498 case 0x8b: // Secondary no-fault LE, RO
1499 default:
1a2fb1c0 1500 do_unassigned_access(addr, 1, 0, 1);
81ad8ba2
BS		 1501 return;
1502 }
1503}
1504
1505#else /* CONFIG_USER_ONLY */
3475187d 1506
1a2fb1c0 1507uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
3475187d 1508{
83469015 1509 uint64_t ret = 0;
1a2fb1c0
BS		 1510#if defined(DEBUG_ASI)
1511 target_ulong last_addr = addr;
1512#endif
3475187d 1513
6f27aba6 1514 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
20b749f6 1515 || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
0f8a249a 1516 raise_exception(TT_PRIV_ACT);
3475187d
FB		 1517
1518 switch (asi) {
81ad8ba2
BS		 1519 case 0x10: // As if user primary
1520 case 0x18: // As if user primary LE
1521 case 0x80: // Primary
1522 case 0x82: // Primary no-fault
1523 case 0x88: // Primary LE
1524 case 0x8a: // Primary no-fault LE
1525 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
6f27aba6
BS		 1526 if (env->hpstate & HS_PRIV) {
1527 switch(size) {
1528 case 1:
1a2fb1c0 1529 ret = ldub_hypv(addr);
6f27aba6
BS		 1530 break;
1531 case 2:
1a2fb1c0 1532 ret = lduw_hypv(addr & ~1);
6f27aba6
BS		 1533 break;
1534 case 4:
1a2fb1c0 1535 ret = ldl_hypv(addr & ~3);
6f27aba6
BS		 1536 break;
1537 default:
1538 case 8:
1a2fb1c0 1539 ret = ldq_hypv(addr & ~7);
6f27aba6
BS		 1540 break;
1541 }
1542 } else {
1543 switch(size) {
1544 case 1:
1a2fb1c0 1545 ret = ldub_kernel(addr);
6f27aba6
BS		 1546 break;
1547 case 2:
1a2fb1c0 1548 ret = lduw_kernel(addr & ~1);
6f27aba6
BS		 1549 break;
1550 case 4:
1a2fb1c0 1551 ret = ldl_kernel(addr & ~3);
6f27aba6
BS		 1552 break;
1553 default:
1554 case 8:
1a2fb1c0 1555 ret = ldq_kernel(addr & ~7);
6f27aba6
BS		 1556 break;
1557 }
81ad8ba2
BS		 1558 }
1559 } else {
1560 switch(size) {
1561 case 1:
1a2fb1c0 1562 ret = ldub_user(addr);
81ad8ba2
BS		 1563 break;
1564 case 2:
1a2fb1c0 1565 ret = lduw_user(addr & ~1);
81ad8ba2
BS		 1566 break;
1567 case 4:
1a2fb1c0 1568 ret = ldl_user(addr & ~3);
81ad8ba2
BS		 1569 break;
1570 default:
1571 case 8:
1a2fb1c0 1572 ret = ldq_user(addr & ~7);
81ad8ba2
BS		 1573 break;
1574 }
1575 }
1576 break;
3475187d
FB		 1577 case 0x14: // Bypass
1578 case 0x15: // Bypass, non-cacheable
81ad8ba2
BS		 1579 case 0x1c: // Bypass LE
1580 case 0x1d: // Bypass, non-cacheable LE
0f8a249a 1581 {
02aab46a
FB		 1582 switch(size) {
1583 case 1:
1a2fb1c0 1584 ret = ldub_phys(addr);
02aab46a
FB		 1585 break;
1586 case 2:
1a2fb1c0 1587 ret = lduw_phys(addr & ~1);
02aab46a
FB		 1588 break;
1589 case 4:
1a2fb1c0 1590 ret = ldl_phys(addr & ~3);
02aab46a
FB		 1591 break;
1592 default:
1593 case 8:
1a2fb1c0 1594 ret = ldq_phys(addr & ~7);
02aab46a
FB		 1595 break;
1596 }
0f8a249a
BS		 1597 break;
1598 }
83469015
FB		 1599 case 0x04: // Nucleus
1600 case 0x0c: // Nucleus Little Endian (LE)
83469015 1601 case 0x11: // As if user secondary
83469015 1602 case 0x19: // As if user secondary LE
83469015
FB		 1603 case 0x24: // Nucleus quad LDD 128 bit atomic
1604 case 0x2c: // Nucleus quad LDD 128 bit atomic
1605 case 0x4a: // UPA config
81ad8ba2 1606 case 0x81: // Secondary
83469015 1607 case 0x83: // Secondary no-fault
83469015 1608 case 0x89: // Secondary LE
83469015 1609 case 0x8b: // Secondary no-fault LE
0f8a249a
BS		 1610 // XXX
1611 break;
3475187d 1612 case 0x45: // LSU
0f8a249a
BS		 1613 ret = env->lsu;
1614 break;
3475187d 1615 case 0x50: // I-MMU regs
0f8a249a 1616 {
1a2fb1c0 1617 int reg = (addr >> 3) & 0xf;
3475187d 1618
0f8a249a
BS		 1619 ret = env->immuregs[reg];
1620 break;
1621 }
3475187d
FB		 1622 case 0x51: // I-MMU 8k TSB pointer
1623 case 0x52: // I-MMU 64k TSB pointer
1624 case 0x55: // I-MMU data access
0f8a249a
BS		 1625 // XXX
1626 break;
83469015 1627 case 0x56: // I-MMU tag read
0f8a249a
BS		 1628 {
1629 unsigned int i;
1630
1631 for (i = 0; i < 64; i++) {
1632 // Valid, ctx match, vaddr match
1633 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
1a2fb1c0 1634 env->itlb_tag[i] == addr) {
0f8a249a
BS		 1635 ret = env->itlb_tag[i];
1636 break;
1637 }
1638 }
1639 break;
1640 }
3475187d 1641 case 0x58: // D-MMU regs
0f8a249a 1642 {
1a2fb1c0 1643 int reg = (addr >> 3) & 0xf;
3475187d 1644
0f8a249a
BS		 1645 ret = env->dmmuregs[reg];
1646 break;
1647 }
83469015 1648 case 0x5e: // D-MMU tag read
0f8a249a
BS		 1649 {
1650 unsigned int i;
1651
1652 for (i = 0; i < 64; i++) {
1653 // Valid, ctx match, vaddr match
1654 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
1a2fb1c0 1655 env->dtlb_tag[i] == addr) {
0f8a249a
BS		 1656 ret = env->dtlb_tag[i];
1657 break;
1658 }
1659 }
1660 break;
1661 }
3475187d
FB		 1662 case 0x59: // D-MMU 8k TSB pointer
1663 case 0x5a: // D-MMU 64k TSB pointer
1664 case 0x5b: // D-MMU data pointer
1665 case 0x5d: // D-MMU data access
83469015
FB		 1666 case 0x48: // Interrupt dispatch, RO
1667 case 0x49: // Interrupt data receive
1668 case 0x7f: // Incoming interrupt vector, RO
0f8a249a
BS		 1669 // XXX
1670 break;
3475187d
FB		 1671 case 0x54: // I-MMU data in, WO
1672 case 0x57: // I-MMU demap, WO
1673 case 0x5c: // D-MMU data in, WO
1674 case 0x5f: // D-MMU demap, WO
83469015 1675 case 0x77: // Interrupt vector, WO
3475187d 1676 default:
1a2fb1c0 1677 do_unassigned_access(addr, 0, 0, 1);
0f8a249a
BS		 1678 ret = 0;
1679 break;
3475187d 1680 }
81ad8ba2
BS		 1681
1682 /* Convert from little endian */
1683 switch (asi) {
1684 case 0x0c: // Nucleus Little Endian (LE)
1685 case 0x18: // As if user primary LE
1686 case 0x19: // As if user secondary LE
1687 case 0x1c: // Bypass LE
1688 case 0x1d: // Bypass, non-cacheable LE
1689 case 0x88: // Primary LE
1690 case 0x89: // Secondary LE
1691 case 0x8a: // Primary no-fault LE
1692 case 0x8b: // Secondary no-fault LE
1693 switch(size) {
1694 case 2:
1695 ret = bswap16(ret);
e32664fb 1696 break;
81ad8ba2
BS		 1697 case 4:
1698 ret = bswap32(ret);
e32664fb 1699 break;
81ad8ba2
BS		 1700 case 8:
1701 ret = bswap64(ret);
e32664fb 1702 break;
81ad8ba2
BS		 1703 default:
1704 break;
1705 }
1706 default:
1707 break;
1708 }
1709
1710 /* Convert to signed number */
1711 if (sign) {
1712 switch(size) {
1713 case 1:
1714 ret = (int8_t) ret;
e32664fb 1715 break;
81ad8ba2
BS		 1716 case 2:
1717 ret = (int16_t) ret;
e32664fb 1718 break;
81ad8ba2
BS		 1719 case 4:
1720 ret = (int32_t) ret;
e32664fb 1721 break;
81ad8ba2
BS		 1722 default:
1723 break;
1724 }
1725 }
1a2fb1c0
BS		 1726#ifdef DEBUG_ASI
1727 dump_asi("read ", last_addr, asi, size, ret);
1728#endif
1729 return ret;
3475187d
FB		 1730}
1731
1a2fb1c0 1732void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
3475187d 1733{
1a2fb1c0
BS		 1734#ifdef DEBUG_ASI
1735 dump_asi("write", addr, asi, size, val);
1736#endif
6f27aba6 1737 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
20b749f6 1738 || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
0f8a249a 1739 raise_exception(TT_PRIV_ACT);
3475187d 1740
81ad8ba2
BS		 1741 /* Convert to little endian */
1742 switch (asi) {
1743 case 0x0c: // Nucleus Little Endian (LE)
1744 case 0x18: // As if user primary LE
1745 case 0x19: // As if user secondary LE
1746 case 0x1c: // Bypass LE
1747 case 0x1d: // Bypass, non-cacheable LE
81ad8ba2
BS		 1748 case 0x88: // Primary LE
1749 case 0x89: // Secondary LE
1750 switch(size) {
1751 case 2:
1a2fb1c0 1752 addr = bswap16(addr);
e32664fb 1753 break;
81ad8ba2 1754 case 4:
1a2fb1c0 1755 addr = bswap32(addr);
e32664fb 1756 break;
81ad8ba2 1757 case 8:
1a2fb1c0 1758 addr = bswap64(addr);
e32664fb 1759 break;
81ad8ba2
BS		 1760 default:
1761 break;
1762 }
1763 default:
1764 break;
1765 }
1766
3475187d 1767 switch(asi) {
81ad8ba2
BS		 1768 case 0x10: // As if user primary
1769 case 0x18: // As if user primary LE
1770 case 0x80: // Primary
1771 case 0x88: // Primary LE
1772 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
6f27aba6
BS		 1773 if (env->hpstate & HS_PRIV) {
1774 switch(size) {
1775 case 1:
1a2fb1c0 1776 stb_hypv(addr, val);
6f27aba6
BS		 1777 break;
1778 case 2:
1a2fb1c0 1779 stw_hypv(addr & ~1, val);
6f27aba6
BS		 1780 break;
1781 case 4:
1a2fb1c0 1782 stl_hypv(addr & ~3, val);
6f27aba6
BS		 1783 break;
1784 case 8:
1785 default:
1a2fb1c0 1786 stq_hypv(addr & ~7, val);
6f27aba6
BS		 1787 break;
1788 }
1789 } else {
1790 switch(size) {
1791 case 1:
1a2fb1c0 1792 stb_kernel(addr, val);
6f27aba6
BS		 1793 break;
1794 case 2:
1a2fb1c0 1795 stw_kernel(addr & ~1, val);
6f27aba6
BS		 1796 break;
1797 case 4:
1a2fb1c0 1798 stl_kernel(addr & ~3, val);
6f27aba6
BS		 1799 break;
1800 case 8:
1801 default:
1a2fb1c0 1802 stq_kernel(addr & ~7, val);
6f27aba6
BS		 1803 break;
1804 }
81ad8ba2
BS		 1805 }
1806 } else {
1807 switch(size) {
1808 case 1:
1a2fb1c0 1809 stb_user(addr, val);
81ad8ba2
BS		 1810 break;
1811 case 2:
1a2fb1c0 1812 stw_user(addr & ~1, val);
81ad8ba2
BS		 1813 break;
1814 case 4:
1a2fb1c0 1815 stl_user(addr & ~3, val);
81ad8ba2
BS		 1816 break;
1817 case 8:
1818 default:
1a2fb1c0 1819 stq_user(addr & ~7, val);
81ad8ba2
BS		 1820 break;
1821 }
1822 }
1823 break;
3475187d
FB		 1824 case 0x14: // Bypass
1825 case 0x15: // Bypass, non-cacheable
81ad8ba2
BS		 1826 case 0x1c: // Bypass LE
1827 case 0x1d: // Bypass, non-cacheable LE
0f8a249a 1828 {
02aab46a
FB		 1829 switch(size) {
1830 case 1:
1a2fb1c0 1831 stb_phys(addr, val);
02aab46a
FB		 1832 break;
1833 case 2:
1a2fb1c0 1834 stw_phys(addr & ~1, val);
02aab46a
FB		 1835 break;
1836 case 4:
1a2fb1c0 1837 stl_phys(addr & ~3, val);
02aab46a
FB		 1838 break;
1839 case 8:
1840 default:
1a2fb1c0 1841 stq_phys(addr & ~7, val);
02aab46a
FB		 1842 break;
1843 }
0f8a249a
BS		 1844 }
1845 return;
83469015
FB		 1846 case 0x04: // Nucleus
1847 case 0x0c: // Nucleus Little Endian (LE)
83469015 1848 case 0x11: // As if user secondary
83469015 1849 case 0x19: // As if user secondary LE
83469015
FB		 1850 case 0x24: // Nucleus quad LDD 128 bit atomic
1851 case 0x2c: // Nucleus quad LDD 128 bit atomic
1852 case 0x4a: // UPA config
51996525 1853 case 0x81: // Secondary
83469015 1854 case 0x89: // Secondary LE
0f8a249a
BS		 1855 // XXX
1856 return;
3475187d 1857 case 0x45: // LSU
0f8a249a
BS		 1858 {
1859 uint64_t oldreg;
1860
1861 oldreg = env->lsu;
1a2fb1c0 1862 env->lsu = val & (DMMU_E | IMMU_E);
0f8a249a
BS		 1863 // Mappings generated during D/I MMU disabled mode are
1864 // invalid in normal mode
1865 if (oldreg != env->lsu) {
952a328f 1866 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu);
83469015 1867#ifdef DEBUG_MMU
0f8a249a 1868 dump_mmu(env);
83469015 1869#endif
0f8a249a
BS		 1870 tlb_flush(env, 1);
1871 }
1872 return;
1873 }
3475187d 1874 case 0x50: // I-MMU regs
0f8a249a 1875 {
1a2fb1c0 1876 int reg = (addr >> 3) & 0xf;
0f8a249a 1877 uint64_t oldreg;
3b46e624 1878
0f8a249a 1879 oldreg = env->immuregs[reg];
3475187d
FB		 1880 switch(reg) {
1881 case 0: // RO
1882 case 4:
1883 return;
1884 case 1: // Not in I-MMU
1885 case 2:
1886 case 7:
1887 case 8:
1888 return;
1889 case 3: // SFSR
1a2fb1c0
BS		 1890 if ((val & 1) == 0)
1891 val = 0; // Clear SFSR
3475187d
FB		 1892 break;
1893 case 5: // TSB access
1894 case 6: // Tag access
1895 default:
1896 break;
1897 }
1a2fb1c0 1898 env->immuregs[reg] = val;
3475187d 1899 if (oldreg != env->immuregs[reg]) {
952a328f 1900 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
3475187d 1901 }
952a328f 1902#ifdef DEBUG_MMU
0f8a249a 1903 dump_mmu(env);
3475187d 1904#endif
0f8a249a
BS		 1905 return;
1906 }
3475187d 1907 case 0x54: // I-MMU data in
0f8a249a
BS		 1908 {
1909 unsigned int i;
1910
1911 // Try finding an invalid entry
1912 for (i = 0; i < 64; i++) {
1913 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
1914 env->itlb_tag[i] = env->immuregs[6];
1a2fb1c0 1915 env->itlb_tte[i] = val;
0f8a249a
BS		 1916 return;
1917 }
1918 }
1919 // Try finding an unlocked entry
1920 for (i = 0; i < 64; i++) {
1921 if ((env->itlb_tte[i] & 0x40) == 0) {
1922 env->itlb_tag[i] = env->immuregs[6];
1a2fb1c0 1923 env->itlb_tte[i] = val;
0f8a249a
BS		 1924 return;
1925 }
1926 }
1927 // error state?
1928 return;
1929 }
3475187d 1930 case 0x55: // I-MMU data access
0f8a249a 1931 {
1a2fb1c0 1932 unsigned int i = (addr >> 3) & 0x3f;
3475187d 1933
0f8a249a 1934 env->itlb_tag[i] = env->immuregs[6];
1a2fb1c0 1935 env->itlb_tte[i] = val;
0f8a249a
BS		 1936 return;
1937 }
3475187d 1938 case 0x57: // I-MMU demap
0f8a249a
BS		 1939 // XXX
1940 return;
3475187d 1941 case 0x58: // D-MMU regs
0f8a249a 1942 {
1a2fb1c0 1943 int reg = (addr >> 3) & 0xf;
0f8a249a 1944 uint64_t oldreg;
3b46e624 1945
0f8a249a 1946 oldreg = env->dmmuregs[reg];
3475187d
FB		 1947 switch(reg) {
1948 case 0: // RO
1949 case 4:
1950 return;
1951 case 3: // SFSR
1a2fb1c0
BS		 1952 if ((val & 1) == 0) {
1953 val = 0; // Clear SFSR, Fault address
0f8a249a
BS		 1954 env->dmmuregs[4] = 0;
1955 }
1a2fb1c0 1956 env->dmmuregs[reg] = val;
3475187d
FB		 1957 break;
1958 case 1: // Primary context
1959 case 2: // Secondary context
1960 case 5: // TSB access
1961 case 6: // Tag access
1962 case 7: // Virtual Watchpoint
1963 case 8: // Physical Watchpoint
1964 default:
1965 break;
1966 }
1a2fb1c0 1967 env->dmmuregs[reg] = val;
3475187d 1968 if (oldreg != env->dmmuregs[reg]) {
952a328f 1969 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
3475187d 1970 }
952a328f 1971#ifdef DEBUG_MMU
0f8a249a 1972 dump_mmu(env);
3475187d 1973#endif
0f8a249a
BS		 1974 return;
1975 }
3475187d 1976 case 0x5c: // D-MMU data in
0f8a249a
BS		 1977 {
1978 unsigned int i;
1979
1980 // Try finding an invalid entry
1981 for (i = 0; i < 64; i++) {
1982 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
1983 env->dtlb_tag[i] = env->dmmuregs[6];
1a2fb1c0 1984 env->dtlb_tte[i] = val;
0f8a249a
BS		 1985 return;
1986 }
1987 }
1988 // Try finding an unlocked entry
1989 for (i = 0; i < 64; i++) {
1990 if ((env->dtlb_tte[i] & 0x40) == 0) {
1991 env->dtlb_tag[i] = env->dmmuregs[6];
1a2fb1c0 1992 env->dtlb_tte[i] = val;
0f8a249a
BS		 1993 return;
1994 }
1995 }
1996 // error state?
1997 return;
1998 }
3475187d 1999 case 0x5d: // D-MMU data access
0f8a249a 2000 {
1a2fb1c0 2001 unsigned int i = (addr >> 3) & 0x3f;
3475187d 2002
0f8a249a 2003 env->dtlb_tag[i] = env->dmmuregs[6];
1a2fb1c0 2004 env->dtlb_tte[i] = val;
0f8a249a
BS		 2005 return;
2006 }
3475187d 2007 case 0x5f: // D-MMU demap
83469015 2008 case 0x49: // Interrupt data receive
0f8a249a
BS		 2009 // XXX
2010 return;
3475187d
FB		 2011 case 0x51: // I-MMU 8k TSB pointer, RO
2012 case 0x52: // I-MMU 64k TSB pointer, RO
2013 case 0x56: // I-MMU tag read, RO
2014 case 0x59: // D-MMU 8k TSB pointer, RO
2015 case 0x5a: // D-MMU 64k TSB pointer, RO
2016 case 0x5b: // D-MMU data pointer, RO
2017 case 0x5e: // D-MMU tag read, RO
83469015
FB		 2018 case 0x48: // Interrupt dispatch, RO
2019 case 0x7f: // Incoming interrupt vector, RO
2020 case 0x82: // Primary no-fault, RO
2021 case 0x83: // Secondary no-fault, RO
2022 case 0x8a: // Primary no-fault LE, RO
2023 case 0x8b: // Secondary no-fault LE, RO
3475187d 2024 default:
1a2fb1c0 2025 do_unassigned_access(addr, 1, 0, 1);
0f8a249a 2026 return;
3475187d
FB		 2027 }
2028}
81ad8ba2 2029#endif /* CONFIG_USER_ONLY */
3391c818 2030
1a2fb1c0 2031void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
3391c818 2032{
3391c818 2033 unsigned int i;
1a2fb1c0 2034 target_ulong val;
3391c818
BS		 2035
2036 switch (asi) {
2037 case 0xf0: // Block load primary
2038 case 0xf1: // Block load secondary
2039 case 0xf8: // Block load primary LE
2040 case 0xf9: // Block load secondary LE
51996525
BS		 2041 if (rd & 7) {
2042 raise_exception(TT_ILL_INSN);
2043 return;
2044 }
1a2fb1c0 2045 if (addr & 0x3f) {
51996525
BS		 2046 raise_exception(TT_UNALIGNED);
2047 return;
2048 }
2049 for (i = 0; i < 16; i++) {
1a2fb1c0
BS		 2050 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4, 0);
2051 addr += 4;
3391c818 2052 }
3391c818
BS		 2053
2054 return;
2055 default:
2056 break;
2057 }
2058
1a2fb1c0 2059 val = helper_ld_asi(addr, asi, size, 0);
3391c818
BS		 2060 switch(size) {
2061 default:
2062 case 4:
1a2fb1c0 2063 *((uint32_t *)&FT0) = val;
3391c818
BS		 2064 break;
2065 case 8:
1a2fb1c0 2066 *((int64_t *)&DT0) = val;
3391c818 2067 break;
1f587329
BS		 2068#if defined(CONFIG_USER_ONLY)
2069 case 16:
2070 // XXX
2071 break;
2072#endif
3391c818 2073 }
3391c818
BS		 2074}
2075
1a2fb1c0 2076void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
3391c818 2077{
3391c818 2078 unsigned int i;
1a2fb1c0 2079 target_ulong val = 0;
3391c818
BS		 2080
2081 switch (asi) {
2082 case 0xf0: // Block store primary
2083 case 0xf1: // Block store secondary
2084 case 0xf8: // Block store primary LE
2085 case 0xf9: // Block store secondary LE
51996525
BS		 2086 if (rd & 7) {
2087 raise_exception(TT_ILL_INSN);
2088 return;
2089 }
1a2fb1c0 2090 if (addr & 0x3f) {
51996525
BS		 2091 raise_exception(TT_UNALIGNED);
2092 return;
2093 }
2094 for (i = 0; i < 16; i++) {
1a2fb1c0
BS		 2095 val = *(uint32_t *)&env->fpr[rd++];
2096 helper_st_asi(addr, val, asi & 0x8f, 4);
2097 addr += 4;
3391c818 2098 }
3391c818
BS		 2099
2100 return;
2101 default:
2102 break;
2103 }
2104
2105 switch(size) {
2106 default:
2107 case 4:
1a2fb1c0 2108 val = *((uint32_t *)&FT0);
3391c818
BS		 2109 break;
2110 case 8:
1a2fb1c0 2111 val = *((int64_t *)&DT0);
3391c818 2112 break;
1f587329
BS		 2113#if defined(CONFIG_USER_ONLY)
2114 case 16:
2115 // XXX
2116 break;
2117#endif
3391c818 2118 }
1a2fb1c0
BS		 2119 helper_st_asi(addr, val, asi, size);
2120}
2121
2122target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
2123 target_ulong val2, uint32_t asi)
2124{
2125 target_ulong ret;
2126
2127 val1 &= 0xffffffffUL;
2128 ret = helper_ld_asi(addr, asi, 4, 0);
2129 ret &= 0xffffffffUL;
2130 if (val1 == ret)
2131 helper_st_asi(addr, val2 & 0xffffffffUL, asi, 4);
2132 return ret;
3391c818
BS		 2133}
2134
1a2fb1c0
BS		 2135target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
2136 target_ulong val2, uint32_t asi)
2137{
2138 target_ulong ret;
2139
2140 ret = helper_ld_asi(addr, asi, 8, 0);
2141 if (val1 == ret)
2142 helper_st_asi(addr, val2, asi, 8);
2143 return ret;
2144}
81ad8ba2 2145#endif /* TARGET_SPARC64 */
3475187d
FB		 2146
2147#ifndef TARGET_SPARC64
1a2fb1c0 2148void helper_rett(void)
e8af50a3 2149{
af7bf89b
FB		 2150 unsigned int cwp;
2151
d4218d99
BS		 2152 if (env->psret == 1)
2153 raise_exception(TT_ILL_INSN);
2154
e8af50a3 2155 env->psret = 1;
5fafdf24 2156 cwp = (env->cwp + 1) & (NWINDOWS - 1);
e8af50a3
FB		 2157 if (env->wim & (1 << cwp)) {
2158 raise_exception(TT_WIN_UNF);
2159 }
2160 set_cwp(cwp);
2161 env->psrs = env->psrps;
2162}
3475187d 2163#endif
e8af50a3 2164
3b89f26c
BS		 2165target_ulong helper_udiv(target_ulong a, target_ulong b)
2166{
2167 uint64_t x0;
2168 uint32_t x1;
2169
2170 x0 = a | ((uint64_t) (env->y) << 32);
2171 x1 = b;
2172
2173 if (x1 == 0) {
2174 raise_exception(TT_DIV_ZERO);
2175 }
2176
2177 x0 = x0 / x1;
2178 if (x0 > 0xffffffff) {
2179 env->cc_src2 = 1;
2180 return 0xffffffff;
2181 } else {
2182 env->cc_src2 = 0;
2183 return x0;
2184 }
2185}
2186
2187target_ulong helper_sdiv(target_ulong a, target_ulong b)
2188{
2189 int64_t x0;
2190 int32_t x1;
2191
2192 x0 = a | ((int64_t) (env->y) << 32);
2193 x1 = b;
2194
2195 if (x1 == 0) {
2196 raise_exception(TT_DIV_ZERO);
2197 }
2198
2199 x0 = x0 / x1;
2200 if ((int32_t) x0 != x0) {
2201 env->cc_src2 = 1;
2202 return x0 < 0? 0x80000000: 0x7fffffff;
2203 } else {
2204 env->cc_src2 = 0;
2205 return x0;
2206 }
2207}
2208
1a2fb1c0
BS		 2209uint64_t helper_pack64(target_ulong high, target_ulong low)
2210{
2211 return ((uint64_t)high << 32) | (uint64_t)(low & 0xffffffff);
2212}
2213
8d5f07fa 2214void helper_ldfsr(void)
e8af50a3 2215{
7a0e1f41 2216 int rnd_mode;
bb5529bb
BS		 2217
2218 PUT_FSR32(env, *((uint32_t *) &FT0));
e8af50a3
FB		 2219 switch (env->fsr & FSR_RD_MASK) {
2220 case FSR_RD_NEAREST:
7a0e1f41 2221 rnd_mode = float_round_nearest_even;
0f8a249a 2222 break;
ed910241 2223 default:
e8af50a3 2224 case FSR_RD_ZERO:
7a0e1f41 2225 rnd_mode = float_round_to_zero;
0f8a249a 2226 break;
e8af50a3 2227 case FSR_RD_POS:
7a0e1f41 2228 rnd_mode = float_round_up;
0f8a249a 2229 break;
e8af50a3 2230 case FSR_RD_NEG:
7a0e1f41 2231 rnd_mode = float_round_down;
0f8a249a 2232 break;
e8af50a3 2233 }
7a0e1f41 2234 set_float_rounding_mode(rnd_mode, &env->fp_status);
e8af50a3 2235}
e80cfcfc 2236
bb5529bb
BS		 2237void helper_stfsr(void)
2238{
2239 *((uint32_t *) &FT0) = GET_FSR32(env);
2240}
2241
2242void helper_debug(void)
e80cfcfc
FB		 2243{
2244 env->exception_index = EXCP_DEBUG;
2245 cpu_loop_exit();
2246}
af7bf89b 2247
3475187d 2248#ifndef TARGET_SPARC64
1a2fb1c0 2249void helper_wrpsr(target_ulong new_psr)
af7bf89b 2250{
1a2fb1c0 2251 if ((new_psr & PSR_CWP) >= NWINDOWS)
d4218d99
BS		 2252 raise_exception(TT_ILL_INSN);
2253 else
1a2fb1c0 2254 PUT_PSR(env, new_psr);
af7bf89b
FB		 2255}
2256
1a2fb1c0 2257target_ulong helper_rdpsr(void)
af7bf89b 2258{
1a2fb1c0 2259 return GET_PSR(env);
af7bf89b 2260}
3475187d
FB		 2261
2262#else
d35527d9
BS		 2263target_ulong helper_rdccr(void)
2264{
2265 return GET_CCR(env);
2266}
2267
2268void helper_wrccr(target_ulong new_ccr)
2269{
2270 PUT_CCR(env, new_ccr);
2271}
2272
2273// CWP handling is reversed in V9, but we still use the V8 register
2274// order.
2275target_ulong helper_rdcwp(void)
2276{
2277 return GET_CWP64(env);
2278}
2279
2280void helper_wrcwp(target_ulong new_cwp)
2281{
2282 PUT_CWP64(env, new_cwp);
2283}
3475187d 2284
1f5063fb
BS		 2285// This function uses non-native bit order
2286#define GET_FIELD(X, FROM, TO) \
2287 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
2288
2289// This function uses the order in the manuals, i.e. bit 0 is 2^0
2290#define GET_FIELD_SP(X, FROM, TO) \
2291 GET_FIELD(X, 63 - (TO), 63 - (FROM))
2292
2293target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
2294{
2295 return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
2296 (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
2297 (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) |
2298 (GET_FIELD_SP(pixel_addr, 56, 59) << 13) |
2299 (GET_FIELD_SP(pixel_addr, 35, 38) << 9) |
2300 (GET_FIELD_SP(pixel_addr, 13, 16) << 5) |
2301 (((pixel_addr >> 55) & 1) << 4) |
2302 (GET_FIELD_SP(pixel_addr, 33, 34) << 2) |
2303 GET_FIELD_SP(pixel_addr, 11, 12);
2304}
2305
2306target_ulong helper_alignaddr(target_ulong addr, target_ulong offset)
2307{
2308 uint64_t tmp;
2309
2310 tmp = addr + offset;
2311 env->gsr &= ~7ULL;
2312 env->gsr |= tmp & 7ULL;
2313 return tmp & ~7ULL;
2314}
2315
1a2fb1c0 2316target_ulong helper_popc(target_ulong val)
3475187d 2317{
1a2fb1c0 2318 return ctpop64(val);
3475187d 2319}
83469015
FB		 2320
2321static inline uint64_t *get_gregset(uint64_t pstate)
2322{
2323 switch (pstate) {
2324 default:
2325 case 0:
0f8a249a 2326 return env->bgregs;
83469015 2327 case PS_AG:
0f8a249a 2328 return env->agregs;
83469015 2329 case PS_MG:
0f8a249a 2330 return env->mgregs;
83469015 2331 case PS_IG:
0f8a249a 2332 return env->igregs;
83469015
FB		 2333 }
2334}
2335
8f1f22f6 2336static inline void change_pstate(uint64_t new_pstate)
83469015 2337{
8f1f22f6 2338 uint64_t pstate_regs, new_pstate_regs;
83469015
FB		 2339 uint64_t *src, *dst;
2340
83469015
FB		 2341 pstate_regs = env->pstate & 0xc01;
2342 new_pstate_regs = new_pstate & 0xc01;
2343 if (new_pstate_regs != pstate_regs) {
0f8a249a
BS		 2344 // Switch global register bank
2345 src = get_gregset(new_pstate_regs);
2346 dst = get_gregset(pstate_regs);
2347 memcpy32(dst, env->gregs);
2348 memcpy32(env->gregs, src);
83469015
FB		 2349 }
2350 env->pstate = new_pstate;
2351}
2352
1a2fb1c0 2353void helper_wrpstate(target_ulong new_state)
8f1f22f6 2354{
1a2fb1c0 2355 change_pstate(new_state & 0xf3f);
8f1f22f6
BS		 2356}
2357
1a2fb1c0 2358void helper_done(void)
83469015
FB		 2359{
2360 env->tl--;
375ee38b
BS		 2361 env->tsptr = &env->ts[env->tl];
2362 env->pc = env->tsptr->tpc;
2363 env->npc = env->tsptr->tnpc + 4;
2364 PUT_CCR(env, env->tsptr->tstate >> 32);
2365 env->asi = (env->tsptr->tstate >> 24) & 0xff;
2366 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2367 PUT_CWP64(env, env->tsptr->tstate & 0xff);
83469015
FB		 2368}
2369
1a2fb1c0 2370void helper_retry(void)
83469015
FB		 2371{
2372 env->tl--;
375ee38b
BS		 2373 env->tsptr = &env->ts[env->tl];
2374 env->pc = env->tsptr->tpc;
2375 env->npc = env->tsptr->tnpc;
2376 PUT_CCR(env, env->tsptr->tstate >> 32);
2377 env->asi = (env->tsptr->tstate >> 24) & 0xff;
2378 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2379 PUT_CWP64(env, env->tsptr->tstate & 0xff);
83469015 2380}
3475187d 2381#endif
ee5bbe38
FB		 2382
2383void set_cwp(int new_cwp)
2384{
2385 /* put the modified wrap registers at their proper location */
2386 if (env->cwp == (NWINDOWS - 1))
2387 memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
2388 env->cwp = new_cwp;
2389 /* put the wrap registers at their temporary location */
2390 if (new_cwp == (NWINDOWS - 1))
2391 memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
2392 env->regwptr = env->regbase + (new_cwp * 16);
2393 REGWPTR = env->regwptr;
2394}
2395
2396void cpu_set_cwp(CPUState *env1, int new_cwp)
2397{
2398 CPUState *saved_env;
2399#ifdef reg_REGWPTR
2400 target_ulong *saved_regwptr;
2401#endif
2402
2403 saved_env = env;
2404#ifdef reg_REGWPTR
2405 saved_regwptr = REGWPTR;
2406#endif
2407 env = env1;
2408 set_cwp(new_cwp);
2409 env = saved_env;
2410#ifdef reg_REGWPTR
2411 REGWPTR = saved_regwptr;
2412#endif
2413}
2414
2415#ifdef TARGET_SPARC64
0b09be2b
BS		 2416#ifdef DEBUG_PCALL
2417static const char * const excp_names[0x50] = {
2418 [TT_TFAULT] = "Instruction Access Fault",
2419 [TT_TMISS] = "Instruction Access MMU Miss",
2420 [TT_CODE_ACCESS] = "Instruction Access Error",
2421 [TT_ILL_INSN] = "Illegal Instruction",
2422 [TT_PRIV_INSN] = "Privileged Instruction",
2423 [TT_NFPU_INSN] = "FPU Disabled",
2424 [TT_FP_EXCP] = "FPU Exception",
2425 [TT_TOVF] = "Tag Overflow",
2426 [TT_CLRWIN] = "Clean Windows",
2427 [TT_DIV_ZERO] = "Division By Zero",
2428 [TT_DFAULT] = "Data Access Fault",
2429 [TT_DMISS] = "Data Access MMU Miss",
2430 [TT_DATA_ACCESS] = "Data Access Error",
2431 [TT_DPROT] = "Data Protection Error",
2432 [TT_UNALIGNED] = "Unaligned Memory Access",
2433 [TT_PRIV_ACT] = "Privileged Action",
2434 [TT_EXTINT | 0x1] = "External Interrupt 1",
2435 [TT_EXTINT | 0x2] = "External Interrupt 2",
2436 [TT_EXTINT | 0x3] = "External Interrupt 3",
2437 [TT_EXTINT | 0x4] = "External Interrupt 4",
2438 [TT_EXTINT | 0x5] = "External Interrupt 5",
2439 [TT_EXTINT | 0x6] = "External Interrupt 6",
2440 [TT_EXTINT | 0x7] = "External Interrupt 7",
2441 [TT_EXTINT | 0x8] = "External Interrupt 8",
2442 [TT_EXTINT | 0x9] = "External Interrupt 9",
2443 [TT_EXTINT | 0xa] = "External Interrupt 10",
2444 [TT_EXTINT | 0xb] = "External Interrupt 11",
2445 [TT_EXTINT | 0xc] = "External Interrupt 12",
2446 [TT_EXTINT | 0xd] = "External Interrupt 13",
2447 [TT_EXTINT | 0xe] = "External Interrupt 14",
2448 [TT_EXTINT | 0xf] = "External Interrupt 15",
2449};
2450#endif
2451
ee5bbe38
FB		 2452void do_interrupt(int intno)
2453{
2454#ifdef DEBUG_PCALL
2455 if (loglevel & CPU_LOG_INT) {
0f8a249a 2456 static int count;
0b09be2b
BS		 2457 const char *name;
2458
2459 if (intno < 0 || intno >= 0x180 || (intno > 0x4f && intno < 0x80))
2460 name = "Unknown";
2461 else if (intno >= 0x100)
2462 name = "Trap Instruction";
2463 else if (intno >= 0xc0)
2464 name = "Window Fill";
2465 else if (intno >= 0x80)
2466 name = "Window Spill";
2467 else {
2468 name = excp_names[intno];
2469 if (!name)
2470 name = "Unknown";
2471 }
2472
2473 fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
2474 " SP=%016" PRIx64 "\n",
2475 count, name, intno,
ee5bbe38
FB		 2476 env->pc,
2477 env->npc, env->regwptr[6]);
0f8a249a 2478 cpu_dump_state(env, logfile, fprintf, 0);
ee5bbe38 2479#if 0
0f8a249a
BS		 2480 {
2481 int i;
2482 uint8_t *ptr;
2483
2484 fprintf(logfile, " code=");
2485 ptr = (uint8_t *)env->pc;
2486 for(i = 0; i < 16; i++) {
2487 fprintf(logfile, " %02x", ldub(ptr + i));
2488 }
2489 fprintf(logfile, "\n");
2490 }
ee5bbe38 2491#endif
0f8a249a 2492 count++;
ee5bbe38
FB		 2493 }
2494#endif
5fafdf24 2495#if !defined(CONFIG_USER_ONLY)
83469015 2496 if (env->tl == MAXTL) {
c68ea704 2497 cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
0f8a249a 2498 return;
ee5bbe38
FB		 2499 }
2500#endif
375ee38b
BS		 2501 env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
2502 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
2503 GET_CWP64(env);
2504 env->tsptr->tpc = env->pc;
2505 env->tsptr->tnpc = env->npc;
2506 env->tsptr->tt = intno;
8f1f22f6
BS		 2507 change_pstate(PS_PEF | PS_PRIV | PS_AG);
2508
2509 if (intno == TT_CLRWIN)
2510 set_cwp((env->cwp - 1) & (NWINDOWS - 1));
2511 else if ((intno & 0x1c0) == TT_SPILL)
2512 set_cwp((env->cwp - env->cansave - 2) & (NWINDOWS - 1));
2513 else if ((intno & 0x1c0) == TT_FILL)
2514 set_cwp((env->cwp + 1) & (NWINDOWS - 1));
83469015
FB		 2515 env->tbr &= ~0x7fffULL;
2516 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
2517 if (env->tl < MAXTL - 1) {
0f8a249a 2518 env->tl++;
83469015 2519 } else {
0f8a249a
BS		 2520 env->pstate |= PS_RED;
2521 if (env->tl != MAXTL)
2522 env->tl++;
83469015 2523 }
375ee38b 2524 env->tsptr = &env->ts[env->tl];
ee5bbe38
FB		 2525 env->pc = env->tbr;
2526 env->npc = env->pc + 4;
2527 env->exception_index = 0;
2528}
2529#else
0b09be2b
BS		 2530#ifdef DEBUG_PCALL
2531static const char * const excp_names[0x80] = {
2532 [TT_TFAULT] = "Instruction Access Fault",
2533 [TT_ILL_INSN] = "Illegal Instruction",
2534 [TT_PRIV_INSN] = "Privileged Instruction",
2535 [TT_NFPU_INSN] = "FPU Disabled",
2536 [TT_WIN_OVF] = "Window Overflow",
2537 [TT_WIN_UNF] = "Window Underflow",
2538 [TT_UNALIGNED] = "Unaligned Memory Access",
2539 [TT_FP_EXCP] = "FPU Exception",
2540 [TT_DFAULT] = "Data Access Fault",
2541 [TT_TOVF] = "Tag Overflow",
2542 [TT_EXTINT | 0x1] = "External Interrupt 1",
2543 [TT_EXTINT | 0x2] = "External Interrupt 2",
2544 [TT_EXTINT | 0x3] = "External Interrupt 3",
2545 [TT_EXTINT | 0x4] = "External Interrupt 4",
2546 [TT_EXTINT | 0x5] = "External Interrupt 5",
2547 [TT_EXTINT | 0x6] = "External Interrupt 6",
2548 [TT_EXTINT | 0x7] = "External Interrupt 7",
2549 [TT_EXTINT | 0x8] = "External Interrupt 8",
2550 [TT_EXTINT | 0x9] = "External Interrupt 9",
2551 [TT_EXTINT | 0xa] = "External Interrupt 10",
2552 [TT_EXTINT | 0xb] = "External Interrupt 11",
2553 [TT_EXTINT | 0xc] = "External Interrupt 12",
2554 [TT_EXTINT | 0xd] = "External Interrupt 13",
2555 [TT_EXTINT | 0xe] = "External Interrupt 14",
2556 [TT_EXTINT | 0xf] = "External Interrupt 15",
2557 [TT_TOVF] = "Tag Overflow",
2558 [TT_CODE_ACCESS] = "Instruction Access Error",
2559 [TT_DATA_ACCESS] = "Data Access Error",
2560 [TT_DIV_ZERO] = "Division By Zero",
2561 [TT_NCP_INSN] = "Coprocessor Disabled",
2562};
2563#endif
2564
ee5bbe38
FB		 2565void do_interrupt(int intno)
2566{
2567 int cwp;
2568
2569#ifdef DEBUG_PCALL
2570 if (loglevel & CPU_LOG_INT) {
0f8a249a 2571 static int count;
0b09be2b
BS		 2572 const char *name;
2573
2574 if (intno < 0 || intno >= 0x100)
2575 name = "Unknown";
2576 else if (intno >= 0x80)
2577 name = "Trap Instruction";
2578 else {
2579 name = excp_names[intno];
2580 if (!name)
2581 name = "Unknown";
2582 }
2583
2584 fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
2585 count, name, intno,
ee5bbe38
FB		 2586 env->pc,
2587 env->npc, env->regwptr[6]);
0f8a249a 2588 cpu_dump_state(env, logfile, fprintf, 0);
ee5bbe38 2589#if 0
0f8a249a
BS		 2590 {
2591 int i;
2592 uint8_t *ptr;
2593
2594 fprintf(logfile, " code=");
2595 ptr = (uint8_t *)env->pc;
2596 for(i = 0; i < 16; i++) {
2597 fprintf(logfile, " %02x", ldub(ptr + i));
2598 }
2599 fprintf(logfile, "\n");
2600 }
ee5bbe38 2601#endif
0f8a249a 2602 count++;
ee5bbe38
FB		 2603 }
2604#endif
5fafdf24 2605#if !defined(CONFIG_USER_ONLY)
ee5bbe38 2606 if (env->psret == 0) {
c68ea704 2607 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
0f8a249a 2608 return;
ee5bbe38
FB		 2609 }
2610#endif
2611 env->psret = 0;
5fafdf24 2612 cwp = (env->cwp - 1) & (NWINDOWS - 1);
ee5bbe38
FB		 2613 set_cwp(cwp);
2614 env->regwptr[9] = env->pc;
2615 env->regwptr[10] = env->npc;
2616 env->psrps = env->psrs;
2617 env->psrs = 1;
2618 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
2619 env->pc = env->tbr;
2620 env->npc = env->pc + 4;
2621 env->exception_index = 0;
2622}
2623#endif
2624
5fafdf24 2625#if !defined(CONFIG_USER_ONLY)
ee5bbe38 2626
d2889a3e
BS		 2627static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
2628 void *retaddr);
2629
ee5bbe38 2630#define MMUSUFFIX _mmu
d2889a3e 2631#define ALIGNED_ONLY
273af660
TS		 2632#ifdef __s390__
2633# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
2634#else
2635# define GETPC() (__builtin_return_address(0))
2636#endif
ee5bbe38
FB		 2637
2638#define SHIFT 0
2639#include "softmmu_template.h"
2640
2641#define SHIFT 1
2642#include "softmmu_template.h"
2643
2644#define SHIFT 2
2645#include "softmmu_template.h"
2646
2647#define SHIFT 3
2648#include "softmmu_template.h"
2649
d2889a3e
BS		 2650static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
2651 void *retaddr)
2652{
94554550
BS		 2653#ifdef DEBUG_UNALIGNED
2654 printf("Unaligned access to 0x%x from 0x%x\n", addr, env->pc);
2655#endif
2656 raise_exception(TT_UNALIGNED);
d2889a3e 2657}
ee5bbe38
FB		 2658
2659/* try to fill the TLB and return an exception if error. If retaddr is
2660 NULL, it means that the function was called in C code (i.e. not
2661 from generated code or from helper.c) */
2662/* XXX: fix it to restore all registers */
6ebbf390 2663void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
ee5bbe38
FB		 2664{
2665 TranslationBlock *tb;
2666 int ret;
2667 unsigned long pc;
2668 CPUState *saved_env;
2669
2670 /* XXX: hack to restore env in all cases, even if not called from
2671 generated code */
2672 saved_env = env;
2673 env = cpu_single_env;
2674
6ebbf390 2675 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ee5bbe38
FB		 2676 if (ret) {
2677 if (retaddr) {
2678 /* now we have a real cpu fault */
2679 pc = (unsigned long)retaddr;
2680 tb = tb_find_pc(pc);
2681 if (tb) {
2682 /* the PC is inside the translated code. It means that we have
2683 a virtual CPU fault */
2684 cpu_restore_state(tb, env, pc, (void *)T2);
2685 }
2686 }
2687 cpu_loop_exit();
2688 }
2689 env = saved_env;
2690}
2691
2692#endif
6c36d3fa
BS		 2693
2694#ifndef TARGET_SPARC64
5dcb6b91 2695void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
6c36d3fa
BS		 2696 int is_asi)
2697{
2698 CPUState *saved_env;
2699
2700 /* XXX: hack to restore env in all cases, even if not called from
2701 generated code */
2702 saved_env = env;
2703 env = cpu_single_env;
8543e2cf
BS		 2704#ifdef DEBUG_UNASSIGNED
2705 if (is_asi)
2706 printf("Unassigned mem %s access to " TARGET_FMT_plx " asi 0x%02x from "
2707 TARGET_FMT_lx "\n",
2708 is_exec ? "exec" : is_write ? "write" : "read", addr, is_asi,
2709 env->pc);
2710 else
2711 printf("Unassigned mem %s access to " TARGET_FMT_plx " from "
2712 TARGET_FMT_lx "\n",
2713 is_exec ? "exec" : is_write ? "write" : "read", addr, env->pc);
2714#endif
6c36d3fa 2715 if (env->mmuregs[3]) /* Fault status register */
0f8a249a 2716 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
6c36d3fa
BS		 2717 if (is_asi)
2718 env->mmuregs[3] |= 1 << 16;
2719 if (env->psrs)
2720 env->mmuregs[3] |= 1 << 5;
2721 if (is_exec)
2722 env->mmuregs[3] |= 1 << 6;
2723 if (is_write)
2724 env->mmuregs[3] |= 1 << 7;
2725 env->mmuregs[3] |= (5 << 2) | 2;
2726 env->mmuregs[4] = addr; /* Fault address register */
2727 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
1b2e93c1
BS		 2728 if (is_exec)
2729 raise_exception(TT_CODE_ACCESS);
2730 else
2731 raise_exception(TT_DATA_ACCESS);
6c36d3fa
BS		 2732 }
2733 env = saved_env;
2734}
2735#else
5dcb6b91 2736void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
6c36d3fa
BS		 2737 int is_asi)
2738{
2739#ifdef DEBUG_UNASSIGNED
2740 CPUState *saved_env;
2741
2742 /* XXX: hack to restore env in all cases, even if not called from
2743 generated code */
2744 saved_env = env;
2745 env = cpu_single_env;
5dcb6b91 2746 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n",
6c36d3fa
BS		 2747 addr, env->pc);
2748 env = saved_env;
2749#endif
1b2e93c1
BS		 2750 if (is_exec)
2751 raise_exception(TT_CODE_ACCESS);
2752 else
2753 raise_exception(TT_DATA_ACCESS);
6c36d3fa
BS		 2754}
2755#endif
20c9f095 2756
Qemu copy for testing