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Merge branch 'master' of blueswir1@git.sv.gnu.org:/srv/git/qemu
[qemu.git] / target-sparc / op_helper.c
CommitLineData
e8af50a3 1#include "exec.h"
eed152bb 2#include "host-utils.h"
1a2fb1c0 3#include "helper.h"
0828b448
BS		 4#if !defined(CONFIG_USER_ONLY)
5#include "softmmu_exec.h"
6#endif /* !defined(CONFIG_USER_ONLY) */
e8af50a3 7
e80cfcfc 8//#define DEBUG_MMU
952a328f 9//#define DEBUG_MXCC
94554550 10//#define DEBUG_UNALIGNED
6c36d3fa 11//#define DEBUG_UNASSIGNED
8543e2cf 12//#define DEBUG_ASI
d81fd722 13//#define DEBUG_PCALL
e80cfcfc 14
952a328f
BS		 15#ifdef DEBUG_MMU
16#define DPRINTF_MMU(fmt, args...) \
17do { printf("MMU: " fmt , ##args); } while (0)
18#else
22548760 19#define DPRINTF_MMU(fmt, args...) do {} while (0)
952a328f
BS		 20#endif
21
22#ifdef DEBUG_MXCC
23#define DPRINTF_MXCC(fmt, args...) \
24do { printf("MXCC: " fmt , ##args); } while (0)
25#else
22548760 26#define DPRINTF_MXCC(fmt, args...) do {} while (0)
952a328f
BS		 27#endif
28
8543e2cf
BS		 29#ifdef DEBUG_ASI
30#define DPRINTF_ASI(fmt, args...) \
31do { printf("ASI: " fmt , ##args); } while (0)
8543e2cf
BS		 32#endif
33
2cade6a3
BS		 34#ifdef TARGET_SPARC64
35#ifndef TARGET_ABI32
36#define AM_CHECK(env1) ((env1)->pstate & PS_AM)
c2bc0e38 37#else
2cade6a3
BS		 38#define AM_CHECK(env1) (1)
39#endif
c2bc0e38
BS		 40#endif
41
697a77e6
IK		 42#ifdef TARGET_SPARC64
43// Calculates TSB pointer value for fault page size 8k or 64k
44static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
45 uint64_t tag_access_register,
46 int page_size)
47{
48 uint64_t tsb_base = tsb_register & ~0x1fffULL;
49 int tsb_split = (env->dmmuregs[5] & 0x1000ULL) ? 1 : 0;
50 int tsb_size = env->dmmuregs[5] & 0xf;
51
52 // discard lower 13 bits which hold tag access context
53 uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
54
55 // now reorder bits
56 uint64_t tsb_base_mask = ~0x1fffULL;
57 uint64_t va = tag_access_va;
58
59 // move va bits to correct position
60 if (page_size == 8*1024) {
61 va >>= 9;
62 } else if (page_size == 64*1024) {
63 va >>= 12;
64 }
65
66 if (tsb_size) {
67 tsb_base_mask <<= tsb_size;
68 }
69
70 // calculate tsb_base mask and adjust va if split is in use
71 if (tsb_split) {
72 if (page_size == 8*1024) {
73 va &= ~(1ULL << (13 + tsb_size));
74 } else if (page_size == 64*1024) {
75 va |= (1ULL << (13 + tsb_size));
76 }
77 tsb_base_mask <<= 1;
78 }
79
80 return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
81}
82
83// Calculates tag target register value by reordering bits
84// in tag access register
85static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
86{
87 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
88}
89
90#endif
91
2cade6a3
BS		 92static inline void address_mask(CPUState *env1, target_ulong *addr)
93{
94#ifdef TARGET_SPARC64
95 if (AM_CHECK(env1))
96 *addr &= 0xffffffffULL;
97#endif
98}
99
f4a5a5ba 100static void raise_exception(int tt)
9d893301
FB		 101{
102 env->exception_index = tt;
103 cpu_loop_exit();
3b46e624 104}
9d893301 105
a7812ae4
PB		 106void HELPER(raise_exception)(int tt)
107{
108 raise_exception(tt);
109}
110
91736d37
BS		 111static inline void set_cwp(int new_cwp)
112{
113 cpu_set_cwp(env, new_cwp);
114}
115
2b29924f
BS		 116void helper_check_align(target_ulong addr, uint32_t align)
117{
c2bc0e38
BS		 118 if (addr & align) {
119#ifdef DEBUG_UNALIGNED
120 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
121 "\n", addr, env->pc);
122#endif
2b29924f 123 raise_exception(TT_UNALIGNED);
c2bc0e38 124 }
2b29924f
BS		 125}
126
44e7757c
BS		 127#define F_HELPER(name, p) void helper_f##name##p(void)
128
44e7757c 129#define F_BINOP(name) \
714547bb 130 float32 helper_f ## name ## s (float32 src1, float32 src2) \
44e7757c 131 { \
714547bb 132 return float32_ ## name (src1, src2, &env->fp_status); \
44e7757c
BS		 133 } \
134 F_HELPER(name, d) \
135 { \
136 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
4e14008f
BS		 137 } \
138 F_HELPER(name, q) \
139 { \
140 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
44e7757c 141 }
44e7757c
BS		 142
143F_BINOP(add);
144F_BINOP(sub);
145F_BINOP(mul);
146F_BINOP(div);
147#undef F_BINOP
148
d84763bc 149void helper_fsmuld(float32 src1, float32 src2)
1a2fb1c0 150{
d84763bc
BS		 151 DT0 = float64_mul(float32_to_float64(src1, &env->fp_status),
152 float32_to_float64(src2, &env->fp_status),
44e7757c
BS		 153 &env->fp_status);
154}
1a2fb1c0 155
4e14008f
BS		 156void helper_fdmulq(void)
157{
158 QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
159 float64_to_float128(DT1, &env->fp_status),
160 &env->fp_status);
161}
4e14008f 162
714547bb 163float32 helper_fnegs(float32 src)
44e7757c 164{
714547bb 165 return float32_chs(src);
417454b0
BS		 166}
167
44e7757c
BS		 168#ifdef TARGET_SPARC64
169F_HELPER(neg, d)
7e8c2b6c 170{
44e7757c 171 DT0 = float64_chs(DT1);
7e8c2b6c 172}
4e14008f 173
4e14008f
BS		 174F_HELPER(neg, q)
175{
176 QT0 = float128_chs(QT1);
177}
178#endif
44e7757c
BS		 179
180/* Integer to float conversion. */
714547bb 181float32 helper_fitos(int32_t src)
a0c4cb4a 182{
714547bb 183 return int32_to_float32(src, &env->fp_status);
a0c4cb4a
FB		 184}
185
d84763bc 186void helper_fitod(int32_t src)
a0c4cb4a 187{
d84763bc 188 DT0 = int32_to_float64(src, &env->fp_status);
a0c4cb4a 189}
9c2b428e 190
c5d04e99 191void helper_fitoq(int32_t src)
4e14008f 192{
c5d04e99 193 QT0 = int32_to_float128(src, &env->fp_status);
4e14008f 194}
4e14008f 195
1e64e78d 196#ifdef TARGET_SPARC64
d84763bc 197float32 helper_fxtos(void)
1e64e78d 198{
d84763bc 199 return int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
1e64e78d
BS		 200}
201
44e7757c 202F_HELPER(xto, d)
1e64e78d 203{
1e64e78d 204 DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
1e64e78d 205}
64a88d5d 206
4e14008f
BS		 207F_HELPER(xto, q)
208{
209 QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
210}
211#endif
44e7757c
BS		 212#undef F_HELPER
213
214/* floating point conversion */
d84763bc 215float32 helper_fdtos(void)
44e7757c 216{
d84763bc 217 return float64_to_float32(DT1, &env->fp_status);
44e7757c
BS		 218}
219
d84763bc 220void helper_fstod(float32 src)
44e7757c 221{
d84763bc 222 DT0 = float32_to_float64(src, &env->fp_status);
44e7757c 223}
9c2b428e 224
c5d04e99 225float32 helper_fqtos(void)
4e14008f 226{
c5d04e99 227 return float128_to_float32(QT1, &env->fp_status);
4e14008f
BS		 228}
229
c5d04e99 230void helper_fstoq(float32 src)
4e14008f 231{
c5d04e99 232 QT0 = float32_to_float128(src, &env->fp_status);
4e14008f
BS		 233}
234
235void helper_fqtod(void)
236{
237 DT0 = float128_to_float64(QT1, &env->fp_status);
238}
239
240void helper_fdtoq(void)
241{
242 QT0 = float64_to_float128(DT1, &env->fp_status);
243}
4e14008f 244
44e7757c 245/* Float to integer conversion. */
714547bb 246int32_t helper_fstoi(float32 src)
44e7757c 247{
714547bb 248 return float32_to_int32_round_to_zero(src, &env->fp_status);
44e7757c
BS		 249}
250
d84763bc 251int32_t helper_fdtoi(void)
44e7757c 252{
d84763bc 253 return float64_to_int32_round_to_zero(DT1, &env->fp_status);
44e7757c
BS		 254}
255
c5d04e99 256int32_t helper_fqtoi(void)
4e14008f 257{
c5d04e99 258 return float128_to_int32_round_to_zero(QT1, &env->fp_status);
4e14008f 259}
4e14008f 260
44e7757c 261#ifdef TARGET_SPARC64
d84763bc 262void helper_fstox(float32 src)
44e7757c 263{
d84763bc 264 *((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status);
44e7757c
BS		 265}
266
267void helper_fdtox(void)
268{
269 *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
270}
271
4e14008f
BS		 272void helper_fqtox(void)
273{
274 *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);
275}
4e14008f 276
44e7757c
BS		 277void helper_faligndata(void)
278{
279 uint64_t tmp;
280
281 tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
06057e6f
BS		 282 /* on many architectures a shift of 64 does nothing */
283 if ((env->gsr & 7) != 0) {
284 tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
285 }
44e7757c
BS		 286 *((uint64_t *)&DT0) = tmp;
287}
288
44e7757c
BS		 289#ifdef WORDS_BIGENDIAN
290#define VIS_B64(n) b[7 - (n)]
291#define VIS_W64(n) w[3 - (n)]
292#define VIS_SW64(n) sw[3 - (n)]
293#define VIS_L64(n) l[1 - (n)]
294#define VIS_B32(n) b[3 - (n)]
295#define VIS_W32(n) w[1 - (n)]
296#else
297#define VIS_B64(n) b[n]
298#define VIS_W64(n) w[n]
299#define VIS_SW64(n) sw[n]
300#define VIS_L64(n) l[n]
301#define VIS_B32(n) b[n]
302#define VIS_W32(n) w[n]
303#endif
304
305typedef union {
306 uint8_t b[8];
307 uint16_t w[4];
308 int16_t sw[4];
309 uint32_t l[2];
310 float64 d;
311} vis64;
312
313typedef union {
314 uint8_t b[4];
315 uint16_t w[2];
316 uint32_t l;
317 float32 f;
318} vis32;
319
320void helper_fpmerge(void)
321{
322 vis64 s, d;
323
324 s.d = DT0;
325 d.d = DT1;
326
327 // Reverse calculation order to handle overlap
328 d.VIS_B64(7) = s.VIS_B64(3);
329 d.VIS_B64(6) = d.VIS_B64(3);
330 d.VIS_B64(5) = s.VIS_B64(2);
331 d.VIS_B64(4) = d.VIS_B64(2);
332 d.VIS_B64(3) = s.VIS_B64(1);
333 d.VIS_B64(2) = d.VIS_B64(1);
334 d.VIS_B64(1) = s.VIS_B64(0);
335 //d.VIS_B64(0) = d.VIS_B64(0);
336
337 DT0 = d.d;
338}
339
340void helper_fmul8x16(void)
341{
342 vis64 s, d;
343 uint32_t tmp;
344
345 s.d = DT0;
346 d.d = DT1;
347
348#define PMUL(r) \
349 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
350 if ((tmp & 0xff) > 0x7f) \
351 tmp += 0x100; \
352 d.VIS_W64(r) = tmp >> 8;
353
354 PMUL(0);
355 PMUL(1);
356 PMUL(2);
357 PMUL(3);
358#undef PMUL
359
360 DT0 = d.d;
361}
362
363void helper_fmul8x16al(void)
364{
365 vis64 s, d;
366 uint32_t tmp;
367
368 s.d = DT0;
369 d.d = DT1;
370
371#define PMUL(r) \
372 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
373 if ((tmp & 0xff) > 0x7f) \
374 tmp += 0x100; \
375 d.VIS_W64(r) = tmp >> 8;
376
377 PMUL(0);
378 PMUL(1);
379 PMUL(2);
380 PMUL(3);
381#undef PMUL
382
383 DT0 = d.d;
384}
385
386void helper_fmul8x16au(void)
387{
388 vis64 s, d;
389 uint32_t tmp;
390
391 s.d = DT0;
392 d.d = DT1;
393
394#define PMUL(r) \
395 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
396 if ((tmp & 0xff) > 0x7f) \
397 tmp += 0x100; \
398 d.VIS_W64(r) = tmp >> 8;
399
400 PMUL(0);
401 PMUL(1);
402 PMUL(2);
403 PMUL(3);
404#undef PMUL
405
406 DT0 = d.d;
407}
408
409void helper_fmul8sux16(void)
410{
411 vis64 s, d;
412 uint32_t tmp;
413
414 s.d = DT0;
415 d.d = DT1;
416
417#define PMUL(r) \
418 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
419 if ((tmp & 0xff) > 0x7f) \
420 tmp += 0x100; \
421 d.VIS_W64(r) = tmp >> 8;
422
423 PMUL(0);
424 PMUL(1);
425 PMUL(2);
426 PMUL(3);
427#undef PMUL
428
429 DT0 = d.d;
430}
431
432void helper_fmul8ulx16(void)
433{
434 vis64 s, d;
435 uint32_t tmp;
436
437 s.d = DT0;
438 d.d = DT1;
439
440#define PMUL(r) \
441 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
442 if ((tmp & 0xff) > 0x7f) \
443 tmp += 0x100; \
444 d.VIS_W64(r) = tmp >> 8;
445
446 PMUL(0);
447 PMUL(1);
448 PMUL(2);
449 PMUL(3);
450#undef PMUL
451
452 DT0 = d.d;
453}
454
455void helper_fmuld8sux16(void)
456{
457 vis64 s, d;
458 uint32_t tmp;
459
460 s.d = DT0;
461 d.d = DT1;
462
463#define PMUL(r) \
464 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
465 if ((tmp & 0xff) > 0x7f) \
466 tmp += 0x100; \
467 d.VIS_L64(r) = tmp;
468
469 // Reverse calculation order to handle overlap
470 PMUL(1);
471 PMUL(0);
472#undef PMUL
473
474 DT0 = d.d;
475}
476
477void helper_fmuld8ulx16(void)
478{
479 vis64 s, d;
480 uint32_t tmp;
481
482 s.d = DT0;
483 d.d = DT1;
484
485#define PMUL(r) \
486 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
487 if ((tmp & 0xff) > 0x7f) \
488 tmp += 0x100; \
489 d.VIS_L64(r) = tmp;
490
491 // Reverse calculation order to handle overlap
492 PMUL(1);
493 PMUL(0);
494#undef PMUL
495
496 DT0 = d.d;
497}
498
499void helper_fexpand(void)
500{
501 vis32 s;
502 vis64 d;
503
504 s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
505 d.d = DT1;
c55bda30
BS		 506 d.VIS_W64(0) = s.VIS_B32(0) << 4;
507 d.VIS_W64(1) = s.VIS_B32(1) << 4;
508 d.VIS_W64(2) = s.VIS_B32(2) << 4;
509 d.VIS_W64(3) = s.VIS_B32(3) << 4;
44e7757c
BS		 510
511 DT0 = d.d;
512}
513
514#define VIS_HELPER(name, F) \
515 void name##16(void) \
516 { \
517 vis64 s, d; \
518 \
519 s.d = DT0; \
520 d.d = DT1; \
521 \
522 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
523 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
524 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
525 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
526 \
527 DT0 = d.d; \
528 } \
529 \
1d01299d 530 uint32_t name##16s(uint32_t src1, uint32_t src2) \
44e7757c
BS		 531 { \
532 vis32 s, d; \
533 \
1d01299d
BS		 534 s.l = src1; \
535 d.l = src2; \
44e7757c
BS		 536 \
537 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
538 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
539 \
1d01299d 540 return d.l; \
44e7757c
BS		 541 } \
542 \
543 void name##32(void) \
544 { \
545 vis64 s, d; \
546 \
547 s.d = DT0; \
548 d.d = DT1; \
549 \
550 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
551 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
552 \
553 DT0 = d.d; \
554 } \
555 \
1d01299d 556 uint32_t name##32s(uint32_t src1, uint32_t src2) \
44e7757c
BS		 557 { \
558 vis32 s, d; \
559 \
1d01299d
BS		 560 s.l = src1; \
561 d.l = src2; \
44e7757c
BS		 562 \
563 d.l = F(d.l, s.l); \
564 \
1d01299d 565 return d.l; \
44e7757c
BS		 566 }
567
568#define FADD(a, b) ((a) + (b))
569#define FSUB(a, b) ((a) - (b))
570VIS_HELPER(helper_fpadd, FADD)
571VIS_HELPER(helper_fpsub, FSUB)
572
573#define VIS_CMPHELPER(name, F) \
574 void name##16(void) \
575 { \
576 vis64 s, d; \
577 \
578 s.d = DT0; \
579 d.d = DT1; \
580 \
581 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
582 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
583 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
584 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
585 \
586 DT0 = d.d; \
587 } \
588 \
589 void name##32(void) \
590 { \
591 vis64 s, d; \
592 \
593 s.d = DT0; \
594 d.d = DT1; \
595 \
596 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
597 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
598 \
599 DT0 = d.d; \
600 }
601
602#define FCMPGT(a, b) ((a) > (b))
603#define FCMPEQ(a, b) ((a) == (b))
604#define FCMPLE(a, b) ((a) <= (b))
605#define FCMPNE(a, b) ((a) != (b))
606
607VIS_CMPHELPER(helper_fcmpgt, FCMPGT)
608VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)
609VIS_CMPHELPER(helper_fcmple, FCMPLE)
610VIS_CMPHELPER(helper_fcmpne, FCMPNE)
611#endif
612
613void helper_check_ieee_exceptions(void)
614{
615 target_ulong status;
616
617 status = get_float_exception_flags(&env->fp_status);
618 if (status) {
619 /* Copy IEEE 754 flags into FSR */
620 if (status & float_flag_invalid)
621 env->fsr |= FSR_NVC;
622 if (status & float_flag_overflow)
623 env->fsr |= FSR_OFC;
624 if (status & float_flag_underflow)
625 env->fsr |= FSR_UFC;
626 if (status & float_flag_divbyzero)
627 env->fsr |= FSR_DZC;
628 if (status & float_flag_inexact)
629 env->fsr |= FSR_NXC;
630
631 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
632 /* Unmasked exception, generate a trap */
633 env->fsr |= FSR_FTT_IEEE_EXCP;
634 raise_exception(TT_FP_EXCP);
635 } else {
636 /* Accumulate exceptions */
637 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
638 }
639 }
640}
641
642void helper_clear_float_exceptions(void)
643{
644 set_float_exception_flags(0, &env->fp_status);
645}
646
714547bb 647float32 helper_fabss(float32 src)
e8af50a3 648{
714547bb 649 return float32_abs(src);
e8af50a3
FB		 650}
651
3475187d 652#ifdef TARGET_SPARC64
7e8c2b6c 653void helper_fabsd(void)
3475187d
FB		 654{
655 DT0 = float64_abs(DT1);
656}
4e14008f 657
4e14008f
BS		 658void helper_fabsq(void)
659{
660 QT0 = float128_abs(QT1);
661}
662#endif
3475187d 663
714547bb 664float32 helper_fsqrts(float32 src)
e8af50a3 665{
714547bb 666 return float32_sqrt(src, &env->fp_status);
e8af50a3
FB		 667}
668
7e8c2b6c 669void helper_fsqrtd(void)
e8af50a3 670{
7a0e1f41 671 DT0 = float64_sqrt(DT1, &env->fp_status);
e8af50a3
FB		 672}
673
4e14008f
BS		 674void helper_fsqrtq(void)
675{
676 QT0 = float128_sqrt(QT1, &env->fp_status);
677}
4e14008f 678
417454b0 679#define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
7e8c2b6c 680 void glue(helper_, name) (void) \
65ce8c2f 681 { \
1a2fb1c0
BS		 682 target_ulong new_fsr; \
683 \
65ce8c2f
FB		 684 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
685 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
686 case float_relation_unordered: \
1a2fb1c0 687 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
417454b0 688 if ((env->fsr & FSR_NVM) || TRAP) { \
1a2fb1c0 689 env->fsr |= new_fsr; \
417454b0
BS		 690 env->fsr |= FSR_NVC; \
691 env->fsr |= FSR_FTT_IEEE_EXCP; \
65ce8c2f
FB		 692 raise_exception(TT_FP_EXCP); \
693 } else { \
694 env->fsr |= FSR_NVA; \
695 } \
696 break; \
697 case float_relation_less: \
1a2fb1c0 698 new_fsr = FSR_FCC0 << FS; \
65ce8c2f
FB		 699 break; \
700 case float_relation_greater: \
1a2fb1c0 701 new_fsr = FSR_FCC1 << FS; \
65ce8c2f
FB		 702 break; \
703 default: \
1a2fb1c0 704 new_fsr = 0; \
65ce8c2f
FB		 705 break; \
706 } \
1a2fb1c0 707 env->fsr |= new_fsr; \
e8af50a3 708 }
714547bb
BS		 709#define GEN_FCMPS(name, size, FS, TRAP) \
710 void glue(helper_, name)(float32 src1, float32 src2) \
711 { \
712 target_ulong new_fsr; \
713 \
714 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
715 switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
716 case float_relation_unordered: \
717 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
718 if ((env->fsr & FSR_NVM) || TRAP) { \
719 env->fsr |= new_fsr; \
720 env->fsr |= FSR_NVC; \
721 env->fsr |= FSR_FTT_IEEE_EXCP; \
722 raise_exception(TT_FP_EXCP); \
723 } else { \
724 env->fsr |= FSR_NVA; \
725 } \
726 break; \
727 case float_relation_less: \
728 new_fsr = FSR_FCC0 << FS; \
729 break; \
730 case float_relation_greater: \
731 new_fsr = FSR_FCC1 << FS; \
732 break; \
733 default: \
734 new_fsr = 0; \
735 break; \
736 } \
737 env->fsr |= new_fsr; \
738 }
e8af50a3 739
714547bb 740GEN_FCMPS(fcmps, float32, 0, 0);
417454b0
BS		 741GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
742
714547bb 743GEN_FCMPS(fcmpes, float32, 0, 1);
417454b0 744GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
3475187d 745
4e14008f
BS		 746GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
747GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
4e14008f 748
3475187d 749#ifdef TARGET_SPARC64
714547bb 750GEN_FCMPS(fcmps_fcc1, float32, 22, 0);
417454b0 751GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
64a88d5d 752GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
417454b0 753
714547bb 754GEN_FCMPS(fcmps_fcc2, float32, 24, 0);
417454b0 755GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
64a88d5d 756GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
417454b0 757
714547bb 758GEN_FCMPS(fcmps_fcc3, float32, 26, 0);
417454b0 759GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
64a88d5d 760GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
417454b0 761
714547bb 762GEN_FCMPS(fcmpes_fcc1, float32, 22, 1);
417454b0 763GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
64a88d5d 764GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
3475187d 765
714547bb 766GEN_FCMPS(fcmpes_fcc2, float32, 24, 1);
417454b0 767GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
64a88d5d 768GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
3475187d 769
714547bb 770GEN_FCMPS(fcmpes_fcc3, float32, 26, 1);
417454b0 771GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
4e14008f
BS		 772GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
773#endif
714547bb 774#undef GEN_FCMPS
3475187d 775
77f193da
BS		 776#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
777 defined(DEBUG_MXCC)
952a328f
BS		 778static void dump_mxcc(CPUState *env)
779{
780 printf("mxccdata: %016llx %016llx %016llx %016llx\n",
77f193da
BS		 781 env->mxccdata[0], env->mxccdata[1],
782 env->mxccdata[2], env->mxccdata[3]);
952a328f
BS		 783 printf("mxccregs: %016llx %016llx %016llx %016llx\n"
784 " %016llx %016llx %016llx %016llx\n",
77f193da
BS		 785 env->mxccregs[0], env->mxccregs[1],
786 env->mxccregs[2], env->mxccregs[3],
787 env->mxccregs[4], env->mxccregs[5],
788 env->mxccregs[6], env->mxccregs[7]);
952a328f
BS		 789}
790#endif
791
1a2fb1c0
BS		 792#if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
793 && defined(DEBUG_ASI)
794static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
795 uint64_t r1)
8543e2cf
BS		 796{
797 switch (size)
798 {
799 case 1:
1a2fb1c0
BS		 800 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
801 addr, asi, r1 & 0xff);
8543e2cf
BS		 802 break;
803 case 2:
1a2fb1c0
BS		 804 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
805 addr, asi, r1 & 0xffff);
8543e2cf
BS		 806 break;
807 case 4:
1a2fb1c0
BS		 808 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
809 addr, asi, r1 & 0xffffffff);
8543e2cf
BS		 810 break;
811 case 8:
1a2fb1c0
BS		 812 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
813 addr, asi, r1);
8543e2cf
BS		 814 break;
815 }
816}
817#endif
818
1a2fb1c0
BS		 819#ifndef TARGET_SPARC64
820#ifndef CONFIG_USER_ONLY
821uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
e8af50a3 822{
1a2fb1c0 823 uint64_t ret = 0;
8543e2cf 824#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
1a2fb1c0 825 uint32_t last_addr = addr;
952a328f 826#endif
e80cfcfc 827
c2bc0e38 828 helper_check_align(addr, size - 1);
e80cfcfc 829 switch (asi) {
6c36d3fa 830 case 2: /* SuperSparc MXCC registers */
1a2fb1c0 831 switch (addr) {
952a328f 832 case 0x01c00a00: /* MXCC control register */
1a2fb1c0
BS		 833 if (size == 8)
834 ret = env->mxccregs[3];
835 else
77f193da
BS		 836 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
837 size);
952a328f
BS		 838 break;
839 case 0x01c00a04: /* MXCC control register */
840 if (size == 4)
841 ret = env->mxccregs[3];
842 else
77f193da
BS		 843 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
844 size);
952a328f 845 break;
295db113
BS		 846 case 0x01c00c00: /* Module reset register */
847 if (size == 8) {
1a2fb1c0 848 ret = env->mxccregs[5];
295db113
BS		 849 // should we do something here?
850 } else
77f193da
BS		 851 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
852 size);
295db113 853 break;
952a328f 854 case 0x01c00f00: /* MBus port address register */
1a2fb1c0
BS		 855 if (size == 8)
856 ret = env->mxccregs[7];
857 else
77f193da
BS		 858 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
859 size);
952a328f
BS		 860 break;
861 default:
77f193da
BS		 862 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
863 size);
952a328f
BS		 864 break;
865 }
77f193da 866 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
9827e450 867 "addr = %08x -> ret = %" PRIx64 ","
1a2fb1c0 868 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
952a328f
BS		 869#ifdef DEBUG_MXCC
870 dump_mxcc(env);
871#endif
6c36d3fa 872 break;
e8af50a3 873 case 3: /* MMU probe */
0f8a249a
BS		 874 {
875 int mmulev;
876
1a2fb1c0 877 mmulev = (addr >> 8) & 15;
0f8a249a
BS		 878 if (mmulev > 4)
879 ret = 0;
1a2fb1c0
BS		 880 else
881 ret = mmu_probe(env, addr, mmulev);
882 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
883 addr, mmulev, ret);
0f8a249a
BS		 884 }
885 break;
e8af50a3 886 case 4: /* read MMU regs */
0f8a249a 887 {
1a2fb1c0 888 int reg = (addr >> 8) & 0x1f;
3b46e624 889
0f8a249a
BS		 890 ret = env->mmuregs[reg];
891 if (reg == 3) /* Fault status cleared on read */
3dd9a152
BS		 892 env->mmuregs[3] = 0;
893 else if (reg == 0x13) /* Fault status read */
894 ret = env->mmuregs[3];
895 else if (reg == 0x14) /* Fault address read */
896 ret = env->mmuregs[4];
1a2fb1c0 897 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
0f8a249a
BS		 898 }
899 break;
045380be
BS		 900 case 5: // Turbosparc ITLB Diagnostic
901 case 6: // Turbosparc DTLB Diagnostic
902 case 7: // Turbosparc IOTLB Diagnostic
903 break;
6c36d3fa
BS		 904 case 9: /* Supervisor code access */
905 switch(size) {
906 case 1:
1a2fb1c0 907 ret = ldub_code(addr);
6c36d3fa
BS		 908 break;
909 case 2:
a4e7dd52 910 ret = lduw_code(addr);
6c36d3fa
BS		 911 break;
912 default:
913 case 4:
a4e7dd52 914 ret = ldl_code(addr);
6c36d3fa
BS		 915 break;
916 case 8:
a4e7dd52 917 ret = ldq_code(addr);
6c36d3fa
BS		 918 break;
919 }
920 break;
81ad8ba2
BS		 921 case 0xa: /* User data access */
922 switch(size) {
923 case 1:
1a2fb1c0 924 ret = ldub_user(addr);
81ad8ba2
BS		 925 break;
926 case 2:
a4e7dd52 927 ret = lduw_user(addr);
81ad8ba2
BS		 928 break;
929 default:
930 case 4:
a4e7dd52 931 ret = ldl_user(addr);
81ad8ba2
BS		 932 break;
933 case 8:
a4e7dd52 934 ret = ldq_user(addr);
81ad8ba2
BS		 935 break;
936 }
937 break;
938 case 0xb: /* Supervisor data access */
939 switch(size) {
940 case 1:
1a2fb1c0 941 ret = ldub_kernel(addr);
81ad8ba2
BS		 942 break;
943 case 2:
a4e7dd52 944 ret = lduw_kernel(addr);
81ad8ba2
BS		 945 break;
946 default:
947 case 4:
a4e7dd52 948 ret = ldl_kernel(addr);
81ad8ba2
BS		 949 break;
950 case 8:
a4e7dd52 951 ret = ldq_kernel(addr);
81ad8ba2
BS		 952 break;
953 }
954 break;
6c36d3fa
BS		 955 case 0xc: /* I-cache tag */
956 case 0xd: /* I-cache data */
957 case 0xe: /* D-cache tag */
958 case 0xf: /* D-cache data */
959 break;
960 case 0x20: /* MMU passthrough */
02aab46a
FB		 961 switch(size) {
962 case 1:
1a2fb1c0 963 ret = ldub_phys(addr);
02aab46a
FB		 964 break;
965 case 2:
a4e7dd52 966 ret = lduw_phys(addr);
02aab46a
FB		 967 break;
968 default:
969 case 4:
a4e7dd52 970 ret = ldl_phys(addr);
02aab46a 971 break;
9e61bde5 972 case 8:
a4e7dd52 973 ret = ldq_phys(addr);
0f8a249a 974 break;
02aab46a 975 }
0f8a249a 976 break;
7d85892b 977 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
5dcb6b91
BS		 978 switch(size) {
979 case 1:
1a2fb1c0 980 ret = ldub_phys((target_phys_addr_t)addr
5dcb6b91
BS		 981 | ((target_phys_addr_t)(asi & 0xf) << 32));
982 break;
983 case 2:
a4e7dd52 984 ret = lduw_phys((target_phys_addr_t)addr
5dcb6b91
BS		 985 | ((target_phys_addr_t)(asi & 0xf) << 32));
986 break;
987 default:
988 case 4:
a4e7dd52 989 ret = ldl_phys((target_phys_addr_t)addr
5dcb6b91
BS		 990 | ((target_phys_addr_t)(asi & 0xf) << 32));
991 break;
992 case 8:
a4e7dd52 993 ret = ldq_phys((target_phys_addr_t)addr
5dcb6b91 994 | ((target_phys_addr_t)(asi & 0xf) << 32));
0f8a249a 995 break;
5dcb6b91 996 }
0f8a249a 997 break;
045380be
BS		 998 case 0x30: // Turbosparc secondary cache diagnostic
999 case 0x31: // Turbosparc RAM snoop
1000 case 0x32: // Turbosparc page table descriptor diagnostic
666c87aa
BS		 1001 case 0x39: /* data cache diagnostic register */
1002 ret = 0;
1003 break;
4017190e
BS		 1004 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
1005 {
1006 int reg = (addr >> 8) & 3;
1007
1008 switch(reg) {
1009 case 0: /* Breakpoint Value (Addr) */
1010 ret = env->mmubpregs[reg];
1011 break;
1012 case 1: /* Breakpoint Mask */
1013 ret = env->mmubpregs[reg];
1014 break;
1015 case 2: /* Breakpoint Control */
1016 ret = env->mmubpregs[reg];
1017 break;
1018 case 3: /* Breakpoint Status */
1019 ret = env->mmubpregs[reg];
1020 env->mmubpregs[reg] = 0ULL;
1021 break;
1022 }
1023 DPRINTF_MMU("read breakpoint reg[%d] 0x%016llx\n", reg, ret);
1024 }
1025 break;
045380be 1026 case 8: /* User code access, XXX */
e8af50a3 1027 default:
e18231a3 1028 do_unassigned_access(addr, 0, 0, asi, size);
0f8a249a
BS		 1029 ret = 0;
1030 break;
e8af50a3 1031 }
81ad8ba2
BS		 1032 if (sign) {
1033 switch(size) {
1034 case 1:
1a2fb1c0 1035 ret = (int8_t) ret;
e32664fb 1036 break;
81ad8ba2 1037 case 2:
1a2fb1c0
BS		 1038 ret = (int16_t) ret;
1039 break;
1040 case 4:
1041 ret = (int32_t) ret;
e32664fb 1042 break;
81ad8ba2 1043 default:
81ad8ba2
BS		 1044 break;
1045 }
1046 }
8543e2cf 1047#ifdef DEBUG_ASI
1a2fb1c0 1048 dump_asi("read ", last_addr, asi, size, ret);
8543e2cf 1049#endif
1a2fb1c0 1050 return ret;
e8af50a3
FB		 1051}
1052
1a2fb1c0 1053void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
e8af50a3 1054{
c2bc0e38 1055 helper_check_align(addr, size - 1);
e8af50a3 1056 switch(asi) {
6c36d3fa 1057 case 2: /* SuperSparc MXCC registers */
1a2fb1c0 1058 switch (addr) {
952a328f
BS		 1059 case 0x01c00000: /* MXCC stream data register 0 */
1060 if (size == 8)
1a2fb1c0 1061 env->mxccdata[0] = val;
952a328f 1062 else
77f193da
BS		 1063 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1064 size);
952a328f
BS		 1065 break;
1066 case 0x01c00008: /* MXCC stream data register 1 */
1067 if (size == 8)
1a2fb1c0 1068 env->mxccdata[1] = val;
952a328f 1069 else
77f193da
BS		 1070 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1071 size);
952a328f
BS		 1072 break;
1073 case 0x01c00010: /* MXCC stream data register 2 */
1074 if (size == 8)
1a2fb1c0 1075 env->mxccdata[2] = val;
952a328f 1076 else
77f193da
BS		 1077 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1078 size);
952a328f
BS		 1079 break;
1080 case 0x01c00018: /* MXCC stream data register 3 */
1081 if (size == 8)
1a2fb1c0 1082 env->mxccdata[3] = val;
952a328f 1083 else
77f193da
BS		 1084 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1085 size);
952a328f
BS		 1086 break;
1087 case 0x01c00100: /* MXCC stream source */
1088 if (size == 8)
1a2fb1c0 1089 env->mxccregs[0] = val;
952a328f 1090 else
77f193da
BS		 1091 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1092 size);
1093 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1094 0);
1095 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1096 8);
1097 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1098 16);
1099 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1100 24);
952a328f
BS		 1101 break;
1102 case 0x01c00200: /* MXCC stream destination */
1103 if (size == 8)
1a2fb1c0 1104 env->mxccregs[1] = val;
952a328f 1105 else
77f193da
BS		 1106 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1107 size);
1108 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0,
1109 env->mxccdata[0]);
1110 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8,
1111 env->mxccdata[1]);
1112 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
1113 env->mxccdata[2]);
1114 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
1115 env->mxccdata[3]);
952a328f
BS		 1116 break;
1117 case 0x01c00a00: /* MXCC control register */
1118 if (size == 8)
1a2fb1c0 1119 env->mxccregs[3] = val;
952a328f 1120 else
77f193da
BS		 1121 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1122 size);
952a328f
BS		 1123 break;
1124 case 0x01c00a04: /* MXCC control register */
1125 if (size == 4)
9f4576f0 1126 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
77f193da 1127 | val;
952a328f 1128 else
77f193da
BS		 1129 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1130 size);
952a328f
BS		 1131 break;
1132 case 0x01c00e00: /* MXCC error register */
bbf7d96b 1133 // writing a 1 bit clears the error
952a328f 1134 if (size == 8)
1a2fb1c0 1135 env->mxccregs[6] &= ~val;
952a328f 1136 else
77f193da
BS		 1137 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1138 size);
952a328f
BS		 1139 break;
1140 case 0x01c00f00: /* MBus port address register */
1141 if (size == 8)
1a2fb1c0 1142 env->mxccregs[7] = val;
952a328f 1143 else
77f193da
BS		 1144 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1145 size);
952a328f
BS		 1146 break;
1147 default:
77f193da
BS		 1148 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
1149 size);
952a328f
BS		 1150 break;
1151 }
9827e450
BS		 1152 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
1153 asi, size, addr, val);
952a328f
BS		 1154#ifdef DEBUG_MXCC
1155 dump_mxcc(env);
1156#endif
6c36d3fa 1157 break;
e8af50a3 1158 case 3: /* MMU flush */
0f8a249a
BS		 1159 {
1160 int mmulev;
e80cfcfc 1161
1a2fb1c0 1162 mmulev = (addr >> 8) & 15;
952a328f 1163 DPRINTF_MMU("mmu flush level %d\n", mmulev);
0f8a249a
BS		 1164 switch (mmulev) {
1165 case 0: // flush page
1a2fb1c0 1166 tlb_flush_page(env, addr & 0xfffff000);
0f8a249a
BS		 1167 break;
1168 case 1: // flush segment (256k)
1169 case 2: // flush region (16M)
1170 case 3: // flush context (4G)
1171 case 4: // flush entire
1172 tlb_flush(env, 1);
1173 break;
1174 default:
1175 break;
1176 }
55754d9e 1177#ifdef DEBUG_MMU
0f8a249a 1178 dump_mmu(env);
55754d9e 1179#endif
0f8a249a 1180 }
8543e2cf 1181 break;
e8af50a3 1182 case 4: /* write MMU regs */
0f8a249a 1183 {
1a2fb1c0 1184 int reg = (addr >> 8) & 0x1f;
0f8a249a 1185 uint32_t oldreg;
3b46e624 1186
0f8a249a 1187 oldreg = env->mmuregs[reg];
55754d9e 1188 switch(reg) {
3deaeab7 1189 case 0: // Control Register
3dd9a152 1190 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
1a2fb1c0 1191 (val & 0x00ffffff);
0f8a249a
BS		 1192 // Mappings generated during no-fault mode or MMU
1193 // disabled mode are invalid in normal mode
5578ceab
BS		 1194 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
1195 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm)))
55754d9e
FB		 1196 tlb_flush(env, 1);
1197 break;
3deaeab7 1198 case 1: // Context Table Pointer Register
5578ceab 1199 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
3deaeab7
BS		 1200 break;
1201 case 2: // Context Register
5578ceab 1202 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
55754d9e
FB		 1203 if (oldreg != env->mmuregs[reg]) {
1204 /* we flush when the MMU context changes because
1205 QEMU has no MMU context support */
1206 tlb_flush(env, 1);
1207 }
1208 break;
3deaeab7
BS		 1209 case 3: // Synchronous Fault Status Register with Clear
1210 case 4: // Synchronous Fault Address Register
1211 break;
1212 case 0x10: // TLB Replacement Control Register
5578ceab 1213 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
55754d9e 1214 break;
3deaeab7 1215 case 0x13: // Synchronous Fault Status Register with Read and Clear
5578ceab 1216 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
3dd9a152 1217 break;
3deaeab7 1218 case 0x14: // Synchronous Fault Address Register
1a2fb1c0 1219 env->mmuregs[4] = val;
3dd9a152 1220 break;
55754d9e 1221 default:
1a2fb1c0 1222 env->mmuregs[reg] = val;
55754d9e
FB		 1223 break;
1224 }
55754d9e 1225 if (oldreg != env->mmuregs[reg]) {
77f193da
BS		 1226 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1227 reg, oldreg, env->mmuregs[reg]);
55754d9e 1228 }
952a328f 1229#ifdef DEBUG_MMU
0f8a249a 1230 dump_mmu(env);
55754d9e 1231#endif
0f8a249a 1232 }
8543e2cf 1233 break;
045380be
BS		 1234 case 5: // Turbosparc ITLB Diagnostic
1235 case 6: // Turbosparc DTLB Diagnostic
1236 case 7: // Turbosparc IOTLB Diagnostic
1237 break;
81ad8ba2
BS		 1238 case 0xa: /* User data access */
1239 switch(size) {
1240 case 1:
1a2fb1c0 1241 stb_user(addr, val);
81ad8ba2
BS		 1242 break;
1243 case 2:
a4e7dd52 1244 stw_user(addr, val);
81ad8ba2
BS		 1245 break;
1246 default:
1247 case 4:
a4e7dd52 1248 stl_user(addr, val);
81ad8ba2
BS		 1249 break;
1250 case 8:
a4e7dd52 1251 stq_user(addr, val);
81ad8ba2
BS		 1252 break;
1253 }
1254 break;
1255 case 0xb: /* Supervisor data access */
1256 switch(size) {
1257 case 1:
1a2fb1c0 1258 stb_kernel(addr, val);
81ad8ba2
BS		 1259 break;
1260 case 2:
a4e7dd52 1261 stw_kernel(addr, val);
81ad8ba2
BS		 1262 break;
1263 default:
1264 case 4:
a4e7dd52 1265 stl_kernel(addr, val);
81ad8ba2
BS		 1266 break;
1267 case 8:
a4e7dd52 1268 stq_kernel(addr, val);
81ad8ba2
BS		 1269 break;
1270 }
1271 break;
6c36d3fa
BS		 1272 case 0xc: /* I-cache tag */
1273 case 0xd: /* I-cache data */
1274 case 0xe: /* D-cache tag */
1275 case 0xf: /* D-cache data */
1276 case 0x10: /* I/D-cache flush page */
1277 case 0x11: /* I/D-cache flush segment */
1278 case 0x12: /* I/D-cache flush region */
1279 case 0x13: /* I/D-cache flush context */
1280 case 0x14: /* I/D-cache flush user */
1281 break;
e80cfcfc 1282 case 0x17: /* Block copy, sta access */
0f8a249a 1283 {
1a2fb1c0
BS		 1284 // val = src
1285 // addr = dst
0f8a249a 1286 // copy 32 bytes
6c36d3fa 1287 unsigned int i;
1a2fb1c0 1288 uint32_t src = val & ~3, dst = addr & ~3, temp;
3b46e624 1289
6c36d3fa
BS		 1290 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
1291 temp = ldl_kernel(src);
1292 stl_kernel(dst, temp);
1293 }
0f8a249a 1294 }
8543e2cf 1295 break;
e80cfcfc 1296 case 0x1f: /* Block fill, stda access */
0f8a249a 1297 {
1a2fb1c0
BS		 1298 // addr = dst
1299 // fill 32 bytes with val
6c36d3fa 1300 unsigned int i;
1a2fb1c0 1301 uint32_t dst = addr & 7;
6c36d3fa
BS		 1302
1303 for (i = 0; i < 32; i += 8, dst += 8)
1304 stq_kernel(dst, val);
0f8a249a 1305 }
8543e2cf 1306 break;
6c36d3fa 1307 case 0x20: /* MMU passthrough */
0f8a249a 1308 {
02aab46a
FB		 1309 switch(size) {
1310 case 1:
1a2fb1c0 1311 stb_phys(addr, val);
02aab46a
FB		 1312 break;
1313 case 2:
a4e7dd52 1314 stw_phys(addr, val);
02aab46a
FB		 1315 break;
1316 case 4:
1317 default:
a4e7dd52 1318 stl_phys(addr, val);
02aab46a 1319 break;
9e61bde5 1320 case 8:
a4e7dd52 1321 stq_phys(addr, val);
9e61bde5 1322 break;
02aab46a 1323 }
0f8a249a 1324 }
8543e2cf 1325 break;
045380be 1326 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
0f8a249a 1327 {
5dcb6b91
BS		 1328 switch(size) {
1329 case 1:
1a2fb1c0
BS		 1330 stb_phys((target_phys_addr_t)addr
1331 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1332 break;
1333 case 2:
a4e7dd52 1334 stw_phys((target_phys_addr_t)addr
1a2fb1c0 1335 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1336 break;
1337 case 4:
1338 default:
a4e7dd52 1339 stl_phys((target_phys_addr_t)addr
1a2fb1c0 1340 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1341 break;
1342 case 8:
a4e7dd52 1343 stq_phys((target_phys_addr_t)addr
1a2fb1c0 1344 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1345 break;
1346 }
0f8a249a 1347 }
8543e2cf 1348 break;
045380be
BS		 1349 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
1350 case 0x31: // store buffer data, Ross RT620 I-cache flush or
1351 // Turbosparc snoop RAM
77f193da
BS		 1352 case 0x32: // store buffer control or Turbosparc page table
1353 // descriptor diagnostic
6c36d3fa
BS		 1354 case 0x36: /* I-cache flash clear */
1355 case 0x37: /* D-cache flash clear */
666c87aa 1356 case 0x4c: /* breakpoint action */
6c36d3fa 1357 break;
4017190e
BS		 1358 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1359 {
1360 int reg = (addr >> 8) & 3;
1361
1362 switch(reg) {
1363 case 0: /* Breakpoint Value (Addr) */
1364 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1365 break;
1366 case 1: /* Breakpoint Mask */
1367 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1368 break;
1369 case 2: /* Breakpoint Control */
1370 env->mmubpregs[reg] = (val & 0x7fULL);
1371 break;
1372 case 3: /* Breakpoint Status */
1373 env->mmubpregs[reg] = (val & 0xfULL);
1374 break;
1375 }
1376 DPRINTF_MMU("write breakpoint reg[%d] 0x%016llx\n", reg,
1377 env->mmuregs[reg]);
1378 }
1379 break;
045380be 1380 case 8: /* User code access, XXX */
6c36d3fa 1381 case 9: /* Supervisor code access, XXX */
e8af50a3 1382 default:
e18231a3 1383 do_unassigned_access(addr, 1, 0, asi, size);
8543e2cf 1384 break;
e8af50a3 1385 }
8543e2cf 1386#ifdef DEBUG_ASI
1a2fb1c0 1387 dump_asi("write", addr, asi, size, val);
8543e2cf 1388#endif
e8af50a3
FB		 1389}
1390
81ad8ba2
BS		 1391#endif /* CONFIG_USER_ONLY */
1392#else /* TARGET_SPARC64 */
1393
1394#ifdef CONFIG_USER_ONLY
1a2fb1c0 1395uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
81ad8ba2
BS		 1396{
1397 uint64_t ret = 0;
1a2fb1c0
BS		 1398#if defined(DEBUG_ASI)
1399 target_ulong last_addr = addr;
1400#endif
81ad8ba2
BS		 1401
1402 if (asi < 0x80)
1403 raise_exception(TT_PRIV_ACT);
1404
c2bc0e38 1405 helper_check_align(addr, size - 1);
2cade6a3 1406 address_mask(env, &addr);
c2bc0e38 1407
81ad8ba2 1408 switch (asi) {
81ad8ba2 1409 case 0x82: // Primary no-fault
81ad8ba2 1410 case 0x8a: // Primary no-fault LE
e83ce550
BS		 1411 if (page_check_range(addr, size, PAGE_READ) == -1) {
1412#ifdef DEBUG_ASI
1413 dump_asi("read ", last_addr, asi, size, ret);
1414#endif
1415 return 0;
1416 }
1417 // Fall through
1418 case 0x80: // Primary
1419 case 0x88: // Primary LE
81ad8ba2
BS		 1420 {
1421 switch(size) {
1422 case 1:
1a2fb1c0 1423 ret = ldub_raw(addr);
81ad8ba2
BS		 1424 break;
1425 case 2:
a4e7dd52 1426 ret = lduw_raw(addr);
81ad8ba2
BS		 1427 break;
1428 case 4:
a4e7dd52 1429 ret = ldl_raw(addr);
81ad8ba2
BS		 1430 break;
1431 default:
1432 case 8:
a4e7dd52 1433 ret = ldq_raw(addr);
81ad8ba2
BS		 1434 break;
1435 }
1436 }
1437 break;
81ad8ba2 1438 case 0x83: // Secondary no-fault
81ad8ba2 1439 case 0x8b: // Secondary no-fault LE
e83ce550
BS		 1440 if (page_check_range(addr, size, PAGE_READ) == -1) {
1441#ifdef DEBUG_ASI
1442 dump_asi("read ", last_addr, asi, size, ret);
1443#endif
1444 return 0;
1445 }
1446 // Fall through
1447 case 0x81: // Secondary
1448 case 0x89: // Secondary LE
81ad8ba2
BS		 1449 // XXX
1450 break;
1451 default:
1452 break;
1453 }
1454
1455 /* Convert from little endian */
1456 switch (asi) {
1457 case 0x88: // Primary LE
1458 case 0x89: // Secondary LE
1459 case 0x8a: // Primary no-fault LE
1460 case 0x8b: // Secondary no-fault LE
1461 switch(size) {
1462 case 2:
1463 ret = bswap16(ret);
e32664fb 1464 break;
81ad8ba2
BS		 1465 case 4:
1466 ret = bswap32(ret);
e32664fb 1467 break;
81ad8ba2
BS		 1468 case 8:
1469 ret = bswap64(ret);
e32664fb 1470 break;
81ad8ba2
BS		 1471 default:
1472 break;
1473 }
1474 default:
1475 break;
1476 }
1477
1478 /* Convert to signed number */
1479 if (sign) {
1480 switch(size) {
1481 case 1:
1482 ret = (int8_t) ret;
e32664fb 1483 break;
81ad8ba2
BS		 1484 case 2:
1485 ret = (int16_t) ret;
e32664fb 1486 break;
81ad8ba2
BS		 1487 case 4:
1488 ret = (int32_t) ret;
e32664fb 1489 break;
81ad8ba2
BS		 1490 default:
1491 break;
1492 }
1493 }
1a2fb1c0
BS		 1494#ifdef DEBUG_ASI
1495 dump_asi("read ", last_addr, asi, size, ret);
1496#endif
1497 return ret;
81ad8ba2
BS		 1498}
1499
1a2fb1c0 1500void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
81ad8ba2 1501{
1a2fb1c0
BS		 1502#ifdef DEBUG_ASI
1503 dump_asi("write", addr, asi, size, val);
1504#endif
81ad8ba2
BS		 1505 if (asi < 0x80)
1506 raise_exception(TT_PRIV_ACT);
1507
c2bc0e38 1508 helper_check_align(addr, size - 1);
2cade6a3 1509 address_mask(env, &addr);
c2bc0e38 1510
81ad8ba2
BS		 1511 /* Convert to little endian */
1512 switch (asi) {
1513 case 0x88: // Primary LE
1514 case 0x89: // Secondary LE
1515 switch(size) {
1516 case 2:
1a2fb1c0 1517 addr = bswap16(addr);
e32664fb 1518 break;
81ad8ba2 1519 case 4:
1a2fb1c0 1520 addr = bswap32(addr);
e32664fb 1521 break;
81ad8ba2 1522 case 8:
1a2fb1c0 1523 addr = bswap64(addr);
e32664fb 1524 break;
81ad8ba2
BS		 1525 default:
1526 break;
1527 }
1528 default:
1529 break;
1530 }
1531
1532 switch(asi) {
1533 case 0x80: // Primary
1534 case 0x88: // Primary LE
1535 {
1536 switch(size) {
1537 case 1:
1a2fb1c0 1538 stb_raw(addr, val);
81ad8ba2
BS		 1539 break;
1540 case 2:
a4e7dd52 1541 stw_raw(addr, val);
81ad8ba2
BS		 1542 break;
1543 case 4:
a4e7dd52 1544 stl_raw(addr, val);
81ad8ba2
BS		 1545 break;
1546 case 8:
1547 default:
a4e7dd52 1548 stq_raw(addr, val);
81ad8ba2
BS		 1549 break;
1550 }
1551 }
1552 break;
1553 case 0x81: // Secondary
1554 case 0x89: // Secondary LE
1555 // XXX
1556 return;
1557
1558 case 0x82: // Primary no-fault, RO
1559 case 0x83: // Secondary no-fault, RO
1560 case 0x8a: // Primary no-fault LE, RO
1561 case 0x8b: // Secondary no-fault LE, RO
1562 default:
e18231a3 1563 do_unassigned_access(addr, 1, 0, 1, size);
81ad8ba2
BS		 1564 return;
1565 }
1566}
1567
1568#else /* CONFIG_USER_ONLY */
3475187d 1569
1a2fb1c0 1570uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
3475187d 1571{
83469015 1572 uint64_t ret = 0;
1a2fb1c0
BS		 1573#if defined(DEBUG_ASI)
1574 target_ulong last_addr = addr;
1575#endif
3475187d 1576
6f27aba6 1577 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
5578ceab
BS		 1578 || ((env->def->features & CPU_FEATURE_HYPV)
1579 && asi >= 0x30 && asi < 0x80
fb79ceb9 1580 && !(env->hpstate & HS_PRIV)))
0f8a249a 1581 raise_exception(TT_PRIV_ACT);
3475187d 1582
c2bc0e38 1583 helper_check_align(addr, size - 1);
3475187d 1584 switch (asi) {
e83ce550
BS		 1585 case 0x82: // Primary no-fault
1586 case 0x8a: // Primary no-fault LE
1587 if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
1588#ifdef DEBUG_ASI
1589 dump_asi("read ", last_addr, asi, size, ret);
1590#endif
1591 return 0;
1592 }
1593 // Fall through
81ad8ba2
BS		 1594 case 0x10: // As if user primary
1595 case 0x18: // As if user primary LE
1596 case 0x80: // Primary
81ad8ba2 1597 case 0x88: // Primary LE
c99657d3
BS		 1598 case 0xe2: // UA2007 Primary block init
1599 case 0xe3: // UA2007 Secondary block init
81ad8ba2 1600 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
5578ceab
BS		 1601 if ((env->def->features & CPU_FEATURE_HYPV)
1602 && env->hpstate & HS_PRIV) {
6f27aba6
BS		 1603 switch(size) {
1604 case 1:
1a2fb1c0 1605 ret = ldub_hypv(addr);
6f27aba6
BS		 1606 break;
1607 case 2:
a4e7dd52 1608 ret = lduw_hypv(addr);
6f27aba6
BS		 1609 break;
1610 case 4:
a4e7dd52 1611 ret = ldl_hypv(addr);
6f27aba6
BS		 1612 break;
1613 default:
1614 case 8:
a4e7dd52 1615 ret = ldq_hypv(addr);
6f27aba6
BS		 1616 break;
1617 }
1618 } else {
1619 switch(size) {
1620 case 1:
1a2fb1c0 1621 ret = ldub_kernel(addr);
6f27aba6
BS		 1622 break;
1623 case 2:
a4e7dd52 1624 ret = lduw_kernel(addr);
6f27aba6
BS		 1625 break;
1626 case 4:
a4e7dd52 1627 ret = ldl_kernel(addr);
6f27aba6
BS		 1628 break;
1629 default:
1630 case 8:
a4e7dd52 1631 ret = ldq_kernel(addr);
6f27aba6
BS		 1632 break;
1633 }
81ad8ba2
BS		 1634 }
1635 } else {
1636 switch(size) {
1637 case 1:
1a2fb1c0 1638 ret = ldub_user(addr);
81ad8ba2
BS		 1639 break;
1640 case 2:
a4e7dd52 1641 ret = lduw_user(addr);
81ad8ba2
BS		 1642 break;
1643 case 4:
a4e7dd52 1644 ret = ldl_user(addr);
81ad8ba2
BS		 1645 break;
1646 default:
1647 case 8:
a4e7dd52 1648 ret = ldq_user(addr);
81ad8ba2
BS		 1649 break;
1650 }
1651 }
1652 break;
3475187d
FB		 1653 case 0x14: // Bypass
1654 case 0x15: // Bypass, non-cacheable
81ad8ba2
BS		 1655 case 0x1c: // Bypass LE
1656 case 0x1d: // Bypass, non-cacheable LE
0f8a249a 1657 {
02aab46a
FB		 1658 switch(size) {
1659 case 1:
1a2fb1c0 1660 ret = ldub_phys(addr);
02aab46a
FB		 1661 break;
1662 case 2:
a4e7dd52 1663 ret = lduw_phys(addr);
02aab46a
FB		 1664 break;
1665 case 4:
a4e7dd52 1666 ret = ldl_phys(addr);
02aab46a
FB		 1667 break;
1668 default:
1669 case 8:
a4e7dd52 1670 ret = ldq_phys(addr);
02aab46a
FB		 1671 break;
1672 }
0f8a249a
BS		 1673 break;
1674 }
db166940
BS		 1675 case 0x24: // Nucleus quad LDD 128 bit atomic
1676 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
1677 // Only ldda allowed
1678 raise_exception(TT_ILL_INSN);
1679 return 0;
e83ce550
BS		 1680 case 0x83: // Secondary no-fault
1681 case 0x8b: // Secondary no-fault LE
1682 if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
1683#ifdef DEBUG_ASI
1684 dump_asi("read ", last_addr, asi, size, ret);
1685#endif
1686 return 0;
1687 }
1688 // Fall through
83469015
FB		 1689 case 0x04: // Nucleus
1690 case 0x0c: // Nucleus Little Endian (LE)
83469015 1691 case 0x11: // As if user secondary
83469015 1692 case 0x19: // As if user secondary LE
83469015 1693 case 0x4a: // UPA config
81ad8ba2 1694 case 0x81: // Secondary
83469015 1695 case 0x89: // Secondary LE
0f8a249a
BS		 1696 // XXX
1697 break;
3475187d 1698 case 0x45: // LSU
0f8a249a
BS		 1699 ret = env->lsu;
1700 break;
3475187d 1701 case 0x50: // I-MMU regs
0f8a249a 1702 {
1a2fb1c0 1703 int reg = (addr >> 3) & 0xf;
3475187d 1704
697a77e6
IK		 1705 if (reg == 0) {
1706 // I-TSB Tag Target register
1707 ret = ultrasparc_tag_target(env->immuregs[6]);
1708 } else {
1709 ret = env->immuregs[reg];
1710 }
1711
0f8a249a
BS		 1712 break;
1713 }
3475187d 1714 case 0x51: // I-MMU 8k TSB pointer
697a77e6
IK		 1715 {
1716 // env->immuregs[5] holds I-MMU TSB register value
1717 // env->immuregs[6] holds I-MMU Tag Access register value
1718 ret = ultrasparc_tsb_pointer(env->immuregs[5], env->immuregs[6],
1719 8*1024);
1720 break;
1721 }
3475187d 1722 case 0x52: // I-MMU 64k TSB pointer
697a77e6
IK		 1723 {
1724 // env->immuregs[5] holds I-MMU TSB register value
1725 // env->immuregs[6] holds I-MMU Tag Access register value
1726 ret = ultrasparc_tsb_pointer(env->immuregs[5], env->immuregs[6],
1727 64*1024);
1728 break;
1729 }
a5a52cf2
BS		 1730 case 0x55: // I-MMU data access
1731 {
1732 int reg = (addr >> 3) & 0x3f;
1733
1734 ret = env->itlb_tte[reg];
1735 break;
1736 }
83469015 1737 case 0x56: // I-MMU tag read
0f8a249a 1738 {
43e9e742 1739 int reg = (addr >> 3) & 0x3f;
0f8a249a 1740
43e9e742 1741 ret = env->itlb_tag[reg];
0f8a249a
BS		 1742 break;
1743 }
3475187d 1744 case 0x58: // D-MMU regs
0f8a249a 1745 {
1a2fb1c0 1746 int reg = (addr >> 3) & 0xf;
3475187d 1747
697a77e6
IK		 1748 if (reg == 0) {
1749 // D-TSB Tag Target register
1750 ret = ultrasparc_tag_target(env->dmmuregs[6]);
1751 } else {
1752 ret = env->dmmuregs[reg];
1753 }
1754 break;
1755 }
1756 case 0x59: // D-MMU 8k TSB pointer
1757 {
1758 // env->dmmuregs[5] holds D-MMU TSB register value
1759 // env->dmmuregs[6] holds D-MMU Tag Access register value
1760 ret = ultrasparc_tsb_pointer(env->dmmuregs[5], env->dmmuregs[6],
1761 8*1024);
1762 break;
1763 }
1764 case 0x5a: // D-MMU 64k TSB pointer
1765 {
1766 // env->dmmuregs[5] holds D-MMU TSB register value
1767 // env->dmmuregs[6] holds D-MMU Tag Access register value
1768 ret = ultrasparc_tsb_pointer(env->dmmuregs[5], env->dmmuregs[6],
1769 64*1024);
0f8a249a
BS		 1770 break;
1771 }
a5a52cf2
BS		 1772 case 0x5d: // D-MMU data access
1773 {
1774 int reg = (addr >> 3) & 0x3f;
1775
1776 ret = env->dtlb_tte[reg];
1777 break;
1778 }
83469015 1779 case 0x5e: // D-MMU tag read
0f8a249a 1780 {
43e9e742 1781 int reg = (addr >> 3) & 0x3f;
0f8a249a 1782
43e9e742 1783 ret = env->dtlb_tag[reg];
0f8a249a
BS		 1784 break;
1785 }
f7350b47
BS		 1786 case 0x46: // D-cache data
1787 case 0x47: // D-cache tag access
a5a52cf2
BS		 1788 case 0x4b: // E-cache error enable
1789 case 0x4c: // E-cache asynchronous fault status
1790 case 0x4d: // E-cache asynchronous fault address
f7350b47
BS		 1791 case 0x4e: // E-cache tag data
1792 case 0x66: // I-cache instruction access
1793 case 0x67: // I-cache tag access
1794 case 0x6e: // I-cache predecode
1795 case 0x6f: // I-cache LRU etc.
1796 case 0x76: // E-cache tag
1797 case 0x7e: // E-cache tag
1798 break;
3475187d 1799 case 0x5b: // D-MMU data pointer
83469015
FB		 1800 case 0x48: // Interrupt dispatch, RO
1801 case 0x49: // Interrupt data receive
1802 case 0x7f: // Incoming interrupt vector, RO
0f8a249a
BS		 1803 // XXX
1804 break;
3475187d
FB		 1805 case 0x54: // I-MMU data in, WO
1806 case 0x57: // I-MMU demap, WO
1807 case 0x5c: // D-MMU data in, WO
1808 case 0x5f: // D-MMU demap, WO
83469015 1809 case 0x77: // Interrupt vector, WO
3475187d 1810 default:
e18231a3 1811 do_unassigned_access(addr, 0, 0, 1, size);
0f8a249a
BS		 1812 ret = 0;
1813 break;
3475187d 1814 }
81ad8ba2
BS		 1815
1816 /* Convert from little endian */
1817 switch (asi) {
1818 case 0x0c: // Nucleus Little Endian (LE)
1819 case 0x18: // As if user primary LE
1820 case 0x19: // As if user secondary LE
1821 case 0x1c: // Bypass LE
1822 case 0x1d: // Bypass, non-cacheable LE
1823 case 0x88: // Primary LE
1824 case 0x89: // Secondary LE
1825 case 0x8a: // Primary no-fault LE
1826 case 0x8b: // Secondary no-fault LE
1827 switch(size) {
1828 case 2:
1829 ret = bswap16(ret);
e32664fb 1830 break;
81ad8ba2
BS		 1831 case 4:
1832 ret = bswap32(ret);
e32664fb 1833 break;
81ad8ba2
BS		 1834 case 8:
1835 ret = bswap64(ret);
e32664fb 1836 break;
81ad8ba2
BS		 1837 default:
1838 break;
1839 }
1840 default:
1841 break;
1842 }
1843
1844 /* Convert to signed number */
1845 if (sign) {
1846 switch(size) {
1847 case 1:
1848 ret = (int8_t) ret;
e32664fb 1849 break;
81ad8ba2
BS		 1850 case 2:
1851 ret = (int16_t) ret;
e32664fb 1852 break;
81ad8ba2
BS		 1853 case 4:
1854 ret = (int32_t) ret;
e32664fb 1855 break;
81ad8ba2
BS		 1856 default:
1857 break;
1858 }
1859 }
1a2fb1c0
BS		 1860#ifdef DEBUG_ASI
1861 dump_asi("read ", last_addr, asi, size, ret);
1862#endif
1863 return ret;
3475187d
FB		 1864}
1865
1a2fb1c0 1866void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
3475187d 1867{
1a2fb1c0
BS		 1868#ifdef DEBUG_ASI
1869 dump_asi("write", addr, asi, size, val);
1870#endif
6f27aba6 1871 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
5578ceab
BS		 1872 || ((env->def->features & CPU_FEATURE_HYPV)
1873 && asi >= 0x30 && asi < 0x80
fb79ceb9 1874 && !(env->hpstate & HS_PRIV)))
0f8a249a 1875 raise_exception(TT_PRIV_ACT);
3475187d 1876
c2bc0e38 1877 helper_check_align(addr, size - 1);
81ad8ba2
BS		 1878 /* Convert to little endian */
1879 switch (asi) {
1880 case 0x0c: // Nucleus Little Endian (LE)
1881 case 0x18: // As if user primary LE
1882 case 0x19: // As if user secondary LE
1883 case 0x1c: // Bypass LE
1884 case 0x1d: // Bypass, non-cacheable LE
81ad8ba2
BS		 1885 case 0x88: // Primary LE
1886 case 0x89: // Secondary LE
1887 switch(size) {
1888 case 2:
1a2fb1c0 1889 addr = bswap16(addr);
e32664fb 1890 break;
81ad8ba2 1891 case 4:
1a2fb1c0 1892 addr = bswap32(addr);
e32664fb 1893 break;
81ad8ba2 1894 case 8:
1a2fb1c0 1895 addr = bswap64(addr);
e32664fb 1896 break;
81ad8ba2
BS		 1897 default:
1898 break;
1899 }
1900 default:
1901 break;
1902 }
1903
3475187d 1904 switch(asi) {
81ad8ba2
BS		 1905 case 0x10: // As if user primary
1906 case 0x18: // As if user primary LE
1907 case 0x80: // Primary
1908 case 0x88: // Primary LE
c99657d3
BS		 1909 case 0xe2: // UA2007 Primary block init
1910 case 0xe3: // UA2007 Secondary block init
81ad8ba2 1911 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
5578ceab
BS		 1912 if ((env->def->features & CPU_FEATURE_HYPV)
1913 && env->hpstate & HS_PRIV) {
6f27aba6
BS		 1914 switch(size) {
1915 case 1:
1a2fb1c0 1916 stb_hypv(addr, val);
6f27aba6
BS		 1917 break;
1918 case 2:
a4e7dd52 1919 stw_hypv(addr, val);
6f27aba6
BS		 1920 break;
1921 case 4:
a4e7dd52 1922 stl_hypv(addr, val);
6f27aba6
BS		 1923 break;
1924 case 8:
1925 default:
a4e7dd52 1926 stq_hypv(addr, val);
6f27aba6
BS		 1927 break;
1928 }
1929 } else {
1930 switch(size) {
1931 case 1:
1a2fb1c0 1932 stb_kernel(addr, val);
6f27aba6
BS		 1933 break;
1934 case 2:
a4e7dd52 1935 stw_kernel(addr, val);
6f27aba6
BS		 1936 break;
1937 case 4:
a4e7dd52 1938 stl_kernel(addr, val);
6f27aba6
BS		 1939 break;
1940 case 8:
1941 default:
a4e7dd52 1942 stq_kernel(addr, val);
6f27aba6
BS		 1943 break;
1944 }
81ad8ba2
BS		 1945 }
1946 } else {
1947 switch(size) {
1948 case 1:
1a2fb1c0 1949 stb_user(addr, val);
81ad8ba2
BS		 1950 break;
1951 case 2:
a4e7dd52 1952 stw_user(addr, val);
81ad8ba2
BS		 1953 break;
1954 case 4:
a4e7dd52 1955 stl_user(addr, val);
81ad8ba2
BS		 1956 break;
1957 case 8:
1958 default:
a4e7dd52 1959 stq_user(addr, val);
81ad8ba2
BS		 1960 break;
1961 }
1962 }
1963 break;
3475187d
FB		 1964 case 0x14: // Bypass
1965 case 0x15: // Bypass, non-cacheable
81ad8ba2
BS		 1966 case 0x1c: // Bypass LE
1967 case 0x1d: // Bypass, non-cacheable LE
0f8a249a 1968 {
02aab46a
FB		 1969 switch(size) {
1970 case 1:
1a2fb1c0 1971 stb_phys(addr, val);
02aab46a
FB		 1972 break;
1973 case 2:
a4e7dd52 1974 stw_phys(addr, val);
02aab46a
FB		 1975 break;
1976 case 4:
a4e7dd52 1977 stl_phys(addr, val);
02aab46a
FB		 1978 break;
1979 case 8:
1980 default:
a4e7dd52 1981 stq_phys(addr, val);
02aab46a
FB		 1982 break;
1983 }
0f8a249a
BS		 1984 }
1985 return;
db166940
BS		 1986 case 0x24: // Nucleus quad LDD 128 bit atomic
1987 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
1988 // Only ldda allowed
1989 raise_exception(TT_ILL_INSN);
1990 return;
83469015
FB		 1991 case 0x04: // Nucleus
1992 case 0x0c: // Nucleus Little Endian (LE)
83469015 1993 case 0x11: // As if user secondary
83469015 1994 case 0x19: // As if user secondary LE
83469015 1995 case 0x4a: // UPA config
51996525 1996 case 0x81: // Secondary
83469015 1997 case 0x89: // Secondary LE
0f8a249a
BS		 1998 // XXX
1999 return;
3475187d 2000 case 0x45: // LSU
0f8a249a
BS		 2001 {
2002 uint64_t oldreg;
2003
2004 oldreg = env->lsu;
1a2fb1c0 2005 env->lsu = val & (DMMU_E | IMMU_E);
0f8a249a
BS		 2006 // Mappings generated during D/I MMU disabled mode are
2007 // invalid in normal mode
2008 if (oldreg != env->lsu) {
77f193da
BS		 2009 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
2010 oldreg, env->lsu);
83469015 2011#ifdef DEBUG_MMU
0f8a249a 2012 dump_mmu(env);
83469015 2013#endif
0f8a249a
BS		 2014 tlb_flush(env, 1);
2015 }
2016 return;
2017 }
3475187d 2018 case 0x50: // I-MMU regs
0f8a249a 2019 {
1a2fb1c0 2020 int reg = (addr >> 3) & 0xf;
0f8a249a 2021 uint64_t oldreg;
3b46e624 2022
0f8a249a 2023 oldreg = env->immuregs[reg];
3475187d
FB		 2024 switch(reg) {
2025 case 0: // RO
2026 case 4:
2027 return;
2028 case 1: // Not in I-MMU
2029 case 2:
2030 case 7:
2031 case 8:
2032 return;
2033 case 3: // SFSR
1a2fb1c0
BS		 2034 if ((val & 1) == 0)
2035 val = 0; // Clear SFSR
3475187d
FB		 2036 break;
2037 case 5: // TSB access
2038 case 6: // Tag access
2039 default:
2040 break;
2041 }
1a2fb1c0 2042 env->immuregs[reg] = val;
3475187d 2043 if (oldreg != env->immuregs[reg]) {
77f193da
BS		 2044 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
2045 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
3475187d 2046 }
952a328f 2047#ifdef DEBUG_MMU
0f8a249a 2048 dump_mmu(env);
3475187d 2049#endif
0f8a249a
BS		 2050 return;
2051 }
3475187d 2052 case 0x54: // I-MMU data in
0f8a249a
BS		 2053 {
2054 unsigned int i;
2055
2056 // Try finding an invalid entry
2057 for (i = 0; i < 64; i++) {
2058 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
2059 env->itlb_tag[i] = env->immuregs[6];
1a2fb1c0 2060 env->itlb_tte[i] = val;
0f8a249a
BS		 2061 return;
2062 }
2063 }
2064 // Try finding an unlocked entry
2065 for (i = 0; i < 64; i++) {
2066 if ((env->itlb_tte[i] & 0x40) == 0) {
2067 env->itlb_tag[i] = env->immuregs[6];
1a2fb1c0 2068 env->itlb_tte[i] = val;
0f8a249a
BS		 2069 return;
2070 }
2071 }
2072 // error state?
2073 return;
2074 }
3475187d 2075 case 0x55: // I-MMU data access
0f8a249a 2076 {
cc6747f4
BS		 2077 // TODO: auto demap
2078
1a2fb1c0 2079 unsigned int i = (addr >> 3) & 0x3f;
3475187d 2080
0f8a249a 2081 env->itlb_tag[i] = env->immuregs[6];
1a2fb1c0 2082 env->itlb_tte[i] = val;
0f8a249a
BS		 2083 return;
2084 }
3475187d 2085 case 0x57: // I-MMU demap
cc6747f4
BS		 2086 {
2087 unsigned int i;
2088
2089 for (i = 0; i < 64; i++) {
2090 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
2091 target_ulong mask = 0xffffffffffffe000ULL;
2092
2093 mask <<= 3 * ((env->itlb_tte[i] >> 61) & 3);
2094 if ((val & mask) == (env->itlb_tag[i] & mask)) {
2095 env->itlb_tag[i] = 0;
2096 env->itlb_tte[i] = 0;
2097 }
2098 return;
2099 }
2100 }
2101 }
0f8a249a 2102 return;
3475187d 2103 case 0x58: // D-MMU regs
0f8a249a 2104 {
1a2fb1c0 2105 int reg = (addr >> 3) & 0xf;
0f8a249a 2106 uint64_t oldreg;
3b46e624 2107
0f8a249a 2108 oldreg = env->dmmuregs[reg];
3475187d
FB		 2109 switch(reg) {
2110 case 0: // RO
2111 case 4:
2112 return;
2113 case 3: // SFSR
1a2fb1c0
BS		 2114 if ((val & 1) == 0) {
2115 val = 0; // Clear SFSR, Fault address
0f8a249a
BS		 2116 env->dmmuregs[4] = 0;
2117 }
1a2fb1c0 2118 env->dmmuregs[reg] = val;
3475187d
FB		 2119 break;
2120 case 1: // Primary context
2121 case 2: // Secondary context
2122 case 5: // TSB access
2123 case 6: // Tag access
2124 case 7: // Virtual Watchpoint
2125 case 8: // Physical Watchpoint
2126 default:
2127 break;
2128 }
1a2fb1c0 2129 env->dmmuregs[reg] = val;
3475187d 2130 if (oldreg != env->dmmuregs[reg]) {
77f193da
BS		 2131 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
2132 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
3475187d 2133 }
952a328f 2134#ifdef DEBUG_MMU
0f8a249a 2135 dump_mmu(env);
3475187d 2136#endif
0f8a249a
BS		 2137 return;
2138 }
3475187d 2139 case 0x5c: // D-MMU data in
0f8a249a
BS		 2140 {
2141 unsigned int i;
2142
2143 // Try finding an invalid entry
2144 for (i = 0; i < 64; i++) {
2145 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
2146 env->dtlb_tag[i] = env->dmmuregs[6];
1a2fb1c0 2147 env->dtlb_tte[i] = val;
0f8a249a
BS		 2148 return;
2149 }
2150 }
2151 // Try finding an unlocked entry
2152 for (i = 0; i < 64; i++) {
2153 if ((env->dtlb_tte[i] & 0x40) == 0) {
2154 env->dtlb_tag[i] = env->dmmuregs[6];
1a2fb1c0 2155 env->dtlb_tte[i] = val;
0f8a249a
BS		 2156 return;
2157 }
2158 }
2159 // error state?
2160 return;
2161 }
3475187d 2162 case 0x5d: // D-MMU data access
0f8a249a 2163 {
1a2fb1c0 2164 unsigned int i = (addr >> 3) & 0x3f;
3475187d 2165
0f8a249a 2166 env->dtlb_tag[i] = env->dmmuregs[6];
1a2fb1c0 2167 env->dtlb_tte[i] = val;
0f8a249a
BS		 2168 return;
2169 }
3475187d 2170 case 0x5f: // D-MMU demap
cc6747f4
BS		 2171 {
2172 unsigned int i;
2173
2174 for (i = 0; i < 64; i++) {
2175 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
2176 target_ulong mask = 0xffffffffffffe000ULL;
2177
2178 mask <<= 3 * ((env->dtlb_tte[i] >> 61) & 3);
2179 if ((val & mask) == (env->dtlb_tag[i] & mask)) {
2180 env->dtlb_tag[i] = 0;
2181 env->dtlb_tte[i] = 0;
2182 }
2183 return;
2184 }
2185 }
2186 }
2187 return;
83469015 2188 case 0x49: // Interrupt data receive
0f8a249a
BS		 2189 // XXX
2190 return;
f7350b47
BS		 2191 case 0x46: // D-cache data
2192 case 0x47: // D-cache tag access
a5a52cf2
BS		 2193 case 0x4b: // E-cache error enable
2194 case 0x4c: // E-cache asynchronous fault status
2195 case 0x4d: // E-cache asynchronous fault address
f7350b47
BS		 2196 case 0x4e: // E-cache tag data
2197 case 0x66: // I-cache instruction access
2198 case 0x67: // I-cache tag access
2199 case 0x6e: // I-cache predecode
2200 case 0x6f: // I-cache LRU etc.
2201 case 0x76: // E-cache tag
2202 case 0x7e: // E-cache tag
2203 return;
3475187d
FB		 2204 case 0x51: // I-MMU 8k TSB pointer, RO
2205 case 0x52: // I-MMU 64k TSB pointer, RO
2206 case 0x56: // I-MMU tag read, RO
2207 case 0x59: // D-MMU 8k TSB pointer, RO
2208 case 0x5a: // D-MMU 64k TSB pointer, RO
2209 case 0x5b: // D-MMU data pointer, RO
2210 case 0x5e: // D-MMU tag read, RO
83469015
FB		 2211 case 0x48: // Interrupt dispatch, RO
2212 case 0x7f: // Incoming interrupt vector, RO
2213 case 0x82: // Primary no-fault, RO
2214 case 0x83: // Secondary no-fault, RO
2215 case 0x8a: // Primary no-fault LE, RO
2216 case 0x8b: // Secondary no-fault LE, RO
3475187d 2217 default:
e18231a3 2218 do_unassigned_access(addr, 1, 0, 1, size);
0f8a249a 2219 return;
3475187d
FB		 2220 }
2221}
81ad8ba2 2222#endif /* CONFIG_USER_ONLY */
3391c818 2223
db166940
BS		 2224void helper_ldda_asi(target_ulong addr, int asi, int rd)
2225{
db166940 2226 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
5578ceab
BS		 2227 || ((env->def->features & CPU_FEATURE_HYPV)
2228 && asi >= 0x30 && asi < 0x80
fb79ceb9 2229 && !(env->hpstate & HS_PRIV)))
db166940
BS		 2230 raise_exception(TT_PRIV_ACT);
2231
2232 switch (asi) {
2233 case 0x24: // Nucleus quad LDD 128 bit atomic
2234 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2235 helper_check_align(addr, 0xf);
2236 if (rd == 0) {
2237 env->gregs[1] = ldq_kernel(addr + 8);
2238 if (asi == 0x2c)
2239 bswap64s(&env->gregs[1]);
2240 } else if (rd < 8) {
2241 env->gregs[rd] = ldq_kernel(addr);
2242 env->gregs[rd + 1] = ldq_kernel(addr + 8);
2243 if (asi == 0x2c) {
2244 bswap64s(&env->gregs[rd]);
2245 bswap64s(&env->gregs[rd + 1]);
2246 }
2247 } else {
2248 env->regwptr[rd] = ldq_kernel(addr);
2249 env->regwptr[rd + 1] = ldq_kernel(addr + 8);
2250 if (asi == 0x2c) {
2251 bswap64s(&env->regwptr[rd]);
2252 bswap64s(&env->regwptr[rd + 1]);
2253 }
2254 }
2255 break;
2256 default:
2257 helper_check_align(addr, 0x3);
2258 if (rd == 0)
2259 env->gregs[1] = helper_ld_asi(addr + 4, asi, 4, 0);
2260 else if (rd < 8) {
2261 env->gregs[rd] = helper_ld_asi(addr, asi, 4, 0);
2262 env->gregs[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2263 } else {
2264 env->regwptr[rd] = helper_ld_asi(addr, asi, 4, 0);
2265 env->regwptr[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2266 }
2267 break;
2268 }
2269}
2270
1a2fb1c0 2271void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
3391c818 2272{
3391c818 2273 unsigned int i;
1a2fb1c0 2274 target_ulong val;
3391c818 2275
c2bc0e38 2276 helper_check_align(addr, 3);
3391c818
BS		 2277 switch (asi) {
2278 case 0xf0: // Block load primary
2279 case 0xf1: // Block load secondary
2280 case 0xf8: // Block load primary LE
2281 case 0xf9: // Block load secondary LE
51996525
BS		 2282 if (rd & 7) {
2283 raise_exception(TT_ILL_INSN);
2284 return;
2285 }
c2bc0e38 2286 helper_check_align(addr, 0x3f);
51996525 2287 for (i = 0; i < 16; i++) {
77f193da
BS		 2288 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4,
2289 0);
1a2fb1c0 2290 addr += 4;
3391c818 2291 }
3391c818
BS		 2292
2293 return;
2294 default:
2295 break;
2296 }
2297
1a2fb1c0 2298 val = helper_ld_asi(addr, asi, size, 0);
3391c818
BS		 2299 switch(size) {
2300 default:
2301 case 4:
714547bb 2302 *((uint32_t *)&env->fpr[rd]) = val;
3391c818
BS		 2303 break;
2304 case 8:
1a2fb1c0 2305 *((int64_t *)&DT0) = val;
3391c818 2306 break;
1f587329
BS		 2307 case 16:
2308 // XXX
2309 break;
3391c818 2310 }
3391c818
BS		 2311}
2312
1a2fb1c0 2313void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
3391c818 2314{
3391c818 2315 unsigned int i;
1a2fb1c0 2316 target_ulong val = 0;
3391c818 2317
c2bc0e38 2318 helper_check_align(addr, 3);
3391c818 2319 switch (asi) {
c99657d3
BS		 2320 case 0xe0: // UA2007 Block commit store primary (cache flush)
2321 case 0xe1: // UA2007 Block commit store secondary (cache flush)
3391c818
BS		 2322 case 0xf0: // Block store primary
2323 case 0xf1: // Block store secondary
2324 case 0xf8: // Block store primary LE
2325 case 0xf9: // Block store secondary LE
51996525
BS		 2326 if (rd & 7) {
2327 raise_exception(TT_ILL_INSN);
2328 return;
2329 }
c2bc0e38 2330 helper_check_align(addr, 0x3f);
51996525 2331 for (i = 0; i < 16; i++) {
1a2fb1c0
BS		 2332 val = *(uint32_t *)&env->fpr[rd++];
2333 helper_st_asi(addr, val, asi & 0x8f, 4);
2334 addr += 4;
3391c818 2335 }
3391c818
BS		 2336
2337 return;
2338 default:
2339 break;
2340 }
2341
2342 switch(size) {
2343 default:
2344 case 4:
714547bb 2345 val = *((uint32_t *)&env->fpr[rd]);
3391c818
BS		 2346 break;
2347 case 8:
1a2fb1c0 2348 val = *((int64_t *)&DT0);
3391c818 2349 break;
1f587329
BS		 2350 case 16:
2351 // XXX
2352 break;
3391c818 2353 }
1a2fb1c0
BS		 2354 helper_st_asi(addr, val, asi, size);
2355}
2356
2357target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
2358 target_ulong val2, uint32_t asi)
2359{
2360 target_ulong ret;
2361
1121f879 2362 val2 &= 0xffffffffUL;
1a2fb1c0
BS		 2363 ret = helper_ld_asi(addr, asi, 4, 0);
2364 ret &= 0xffffffffUL;
1121f879
BS		 2365 if (val2 == ret)
2366 helper_st_asi(addr, val1 & 0xffffffffUL, asi, 4);
1a2fb1c0 2367 return ret;
3391c818
BS		 2368}
2369
1a2fb1c0
BS		 2370target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
2371 target_ulong val2, uint32_t asi)
2372{
2373 target_ulong ret;
2374
2375 ret = helper_ld_asi(addr, asi, 8, 0);
1121f879
BS		 2376 if (val2 == ret)
2377 helper_st_asi(addr, val1, asi, 8);
1a2fb1c0
BS		 2378 return ret;
2379}
81ad8ba2 2380#endif /* TARGET_SPARC64 */
3475187d
FB		 2381
2382#ifndef TARGET_SPARC64
1a2fb1c0 2383void helper_rett(void)
e8af50a3 2384{
af7bf89b
FB		 2385 unsigned int cwp;
2386
d4218d99
BS		 2387 if (env->psret == 1)
2388 raise_exception(TT_ILL_INSN);
2389
e8af50a3 2390 env->psret = 1;
1a14026e 2391 cwp = cpu_cwp_inc(env, env->cwp + 1) ;
e8af50a3
FB		 2392 if (env->wim & (1 << cwp)) {
2393 raise_exception(TT_WIN_UNF);
2394 }
2395 set_cwp(cwp);
2396 env->psrs = env->psrps;
2397}
3475187d 2398#endif
e8af50a3 2399
3b89f26c
BS		 2400target_ulong helper_udiv(target_ulong a, target_ulong b)
2401{
2402 uint64_t x0;
2403 uint32_t x1;
2404
7621a90d 2405 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
3b89f26c
BS		 2406 x1 = b;
2407
2408 if (x1 == 0) {
2409 raise_exception(TT_DIV_ZERO);
2410 }
2411
2412 x0 = x0 / x1;
2413 if (x0 > 0xffffffff) {
2414 env->cc_src2 = 1;
2415 return 0xffffffff;
2416 } else {
2417 env->cc_src2 = 0;
2418 return x0;
2419 }
2420}
2421
2422target_ulong helper_sdiv(target_ulong a, target_ulong b)
2423{
2424 int64_t x0;
2425 int32_t x1;
2426
7621a90d 2427 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
3b89f26c
BS		 2428 x1 = b;
2429
2430 if (x1 == 0) {
2431 raise_exception(TT_DIV_ZERO);
2432 }
2433
2434 x0 = x0 / x1;
2435 if ((int32_t) x0 != x0) {
2436 env->cc_src2 = 1;
2437 return x0 < 0? 0x80000000: 0x7fffffff;
2438 } else {
2439 env->cc_src2 = 0;
2440 return x0;
2441 }
2442}
2443
7fa76c0b
BS		 2444void helper_stdf(target_ulong addr, int mem_idx)
2445{
c2bc0e38 2446 helper_check_align(addr, 7);
7fa76c0b
BS		 2447#if !defined(CONFIG_USER_ONLY)
2448 switch (mem_idx) {
2449 case 0:
c2bc0e38 2450 stfq_user(addr, DT0);
7fa76c0b
BS		 2451 break;
2452 case 1:
c2bc0e38 2453 stfq_kernel(addr, DT0);
7fa76c0b
BS		 2454 break;
2455#ifdef TARGET_SPARC64
2456 case 2:
c2bc0e38 2457 stfq_hypv(addr, DT0);
7fa76c0b
BS		 2458 break;
2459#endif
2460 default:
2461 break;
2462 }
2463#else
2cade6a3 2464 address_mask(env, &addr);
c2bc0e38 2465 stfq_raw(addr, DT0);
7fa76c0b
BS		 2466#endif
2467}
2468
2469void helper_lddf(target_ulong addr, int mem_idx)
2470{
c2bc0e38 2471 helper_check_align(addr, 7);
7fa76c0b
BS		 2472#if !defined(CONFIG_USER_ONLY)
2473 switch (mem_idx) {
2474 case 0:
c2bc0e38 2475 DT0 = ldfq_user(addr);
7fa76c0b
BS		 2476 break;
2477 case 1:
c2bc0e38 2478 DT0 = ldfq_kernel(addr);
7fa76c0b
BS		 2479 break;
2480#ifdef TARGET_SPARC64
2481 case 2:
c2bc0e38 2482 DT0 = ldfq_hypv(addr);
7fa76c0b
BS		 2483 break;
2484#endif
2485 default:
2486 break;
2487 }
2488#else
2cade6a3 2489 address_mask(env, &addr);
c2bc0e38 2490 DT0 = ldfq_raw(addr);
7fa76c0b
BS		 2491#endif
2492}
2493
64a88d5d 2494void helper_ldqf(target_ulong addr, int mem_idx)
7fa76c0b
BS		 2495{
2496 // XXX add 128 bit load
2497 CPU_QuadU u;
2498
c2bc0e38 2499 helper_check_align(addr, 7);
64a88d5d
BS		 2500#if !defined(CONFIG_USER_ONLY)
2501 switch (mem_idx) {
2502 case 0:
c2bc0e38
BS		 2503 u.ll.upper = ldq_user(addr);
2504 u.ll.lower = ldq_user(addr + 8);
64a88d5d
BS		 2505 QT0 = u.q;
2506 break;
2507 case 1:
c2bc0e38
BS		 2508 u.ll.upper = ldq_kernel(addr);
2509 u.ll.lower = ldq_kernel(addr + 8);
64a88d5d
BS		 2510 QT0 = u.q;
2511 break;
2512#ifdef TARGET_SPARC64
2513 case 2:
c2bc0e38
BS		 2514 u.ll.upper = ldq_hypv(addr);
2515 u.ll.lower = ldq_hypv(addr + 8);
64a88d5d
BS		 2516 QT0 = u.q;
2517 break;
2518#endif
2519 default:
2520 break;
2521 }
2522#else
2cade6a3 2523 address_mask(env, &addr);
c2bc0e38
BS		 2524 u.ll.upper = ldq_raw(addr);
2525 u.ll.lower = ldq_raw((addr + 8) & 0xffffffffULL);
7fa76c0b 2526 QT0 = u.q;
64a88d5d 2527#endif
7fa76c0b
BS		 2528}
2529
64a88d5d 2530void helper_stqf(target_ulong addr, int mem_idx)
7fa76c0b
BS		 2531{
2532 // XXX add 128 bit store
2533 CPU_QuadU u;
2534
c2bc0e38 2535 helper_check_align(addr, 7);
64a88d5d
BS		 2536#if !defined(CONFIG_USER_ONLY)
2537 switch (mem_idx) {
2538 case 0:
2539 u.q = QT0;
c2bc0e38
BS		 2540 stq_user(addr, u.ll.upper);
2541 stq_user(addr + 8, u.ll.lower);
64a88d5d
BS		 2542 break;
2543 case 1:
2544 u.q = QT0;
c2bc0e38
BS		 2545 stq_kernel(addr, u.ll.upper);
2546 stq_kernel(addr + 8, u.ll.lower);
64a88d5d
BS		 2547 break;
2548#ifdef TARGET_SPARC64
2549 case 2:
2550 u.q = QT0;
c2bc0e38
BS		 2551 stq_hypv(addr, u.ll.upper);
2552 stq_hypv(addr + 8, u.ll.lower);
64a88d5d
BS		 2553 break;
2554#endif
2555 default:
2556 break;
2557 }
2558#else
7fa76c0b 2559 u.q = QT0;
2cade6a3 2560 address_mask(env, &addr);
c2bc0e38
BS		 2561 stq_raw(addr, u.ll.upper);
2562 stq_raw((addr + 8) & 0xffffffffULL, u.ll.lower);
7fa76c0b 2563#endif
64a88d5d 2564}
7fa76c0b 2565
3a3b925d 2566static inline void set_fsr(void)
e8af50a3 2567{
7a0e1f41 2568 int rnd_mode;
bb5529bb 2569
e8af50a3
FB		 2570 switch (env->fsr & FSR_RD_MASK) {
2571 case FSR_RD_NEAREST:
7a0e1f41 2572 rnd_mode = float_round_nearest_even;
0f8a249a 2573 break;
ed910241 2574 default:
e8af50a3 2575 case FSR_RD_ZERO:
7a0e1f41 2576 rnd_mode = float_round_to_zero;
0f8a249a 2577 break;
e8af50a3 2578 case FSR_RD_POS:
7a0e1f41 2579 rnd_mode = float_round_up;
0f8a249a 2580 break;
e8af50a3 2581 case FSR_RD_NEG:
7a0e1f41 2582 rnd_mode = float_round_down;
0f8a249a 2583 break;
e8af50a3 2584 }
7a0e1f41 2585 set_float_rounding_mode(rnd_mode, &env->fp_status);
e8af50a3 2586}
e80cfcfc 2587
3a3b925d 2588void helper_ldfsr(uint32_t new_fsr)
bb5529bb 2589{
3a3b925d
BS		 2590 env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK);
2591 set_fsr();
bb5529bb
BS		 2592}
2593
3a3b925d
BS		 2594#ifdef TARGET_SPARC64
2595void helper_ldxfsr(uint64_t new_fsr)
2596{
2597 env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK);
2598 set_fsr();
2599}
2600#endif
2601
bb5529bb 2602void helper_debug(void)
e80cfcfc
FB		 2603{
2604 env->exception_index = EXCP_DEBUG;
2605 cpu_loop_exit();
2606}
af7bf89b 2607
3475187d 2608#ifndef TARGET_SPARC64
72a9747b
BS		 2609/* XXX: use another pointer for %iN registers to avoid slow wrapping
2610 handling ? */
2611void helper_save(void)
2612{
2613 uint32_t cwp;
2614
1a14026e 2615 cwp = cpu_cwp_dec(env, env->cwp - 1);
72a9747b
BS		 2616 if (env->wim & (1 << cwp)) {
2617 raise_exception(TT_WIN_OVF);
2618 }
2619 set_cwp(cwp);
2620}
2621
2622void helper_restore(void)
2623{
2624 uint32_t cwp;
2625
1a14026e 2626 cwp = cpu_cwp_inc(env, env->cwp + 1);
72a9747b
BS		 2627 if (env->wim & (1 << cwp)) {
2628 raise_exception(TT_WIN_UNF);
2629 }
2630 set_cwp(cwp);
2631}
2632
1a2fb1c0 2633void helper_wrpsr(target_ulong new_psr)
af7bf89b 2634{
1a14026e 2635 if ((new_psr & PSR_CWP) >= env->nwindows)
d4218d99
BS		 2636 raise_exception(TT_ILL_INSN);
2637 else
1a2fb1c0 2638 PUT_PSR(env, new_psr);
af7bf89b
FB		 2639}
2640
1a2fb1c0 2641target_ulong helper_rdpsr(void)
af7bf89b 2642{
1a2fb1c0 2643 return GET_PSR(env);
af7bf89b 2644}
3475187d
FB		 2645
2646#else
72a9747b
BS		 2647/* XXX: use another pointer for %iN registers to avoid slow wrapping
2648 handling ? */
2649void helper_save(void)
2650{
2651 uint32_t cwp;
2652
1a14026e 2653 cwp = cpu_cwp_dec(env, env->cwp - 1);
72a9747b
BS		 2654 if (env->cansave == 0) {
2655 raise_exception(TT_SPILL | (env->otherwin != 0 ?
2656 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2657 ((env->wstate & 0x7) << 2)));
2658 } else {
2659 if (env->cleanwin - env->canrestore == 0) {
2660 // XXX Clean windows without trap
2661 raise_exception(TT_CLRWIN);
2662 } else {
2663 env->cansave--;
2664 env->canrestore++;
2665 set_cwp(cwp);
2666 }
2667 }
2668}
2669
2670void helper_restore(void)
2671{
2672 uint32_t cwp;
2673
1a14026e 2674 cwp = cpu_cwp_inc(env, env->cwp + 1);
72a9747b
BS		 2675 if (env->canrestore == 0) {
2676 raise_exception(TT_FILL | (env->otherwin != 0 ?
2677 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2678 ((env->wstate & 0x7) << 2)));
2679 } else {
2680 env->cansave++;
2681 env->canrestore--;
2682 set_cwp(cwp);
2683 }
2684}
2685
2686void helper_flushw(void)
2687{
1a14026e 2688 if (env->cansave != env->nwindows - 2) {
72a9747b
BS		 2689 raise_exception(TT_SPILL | (env->otherwin != 0 ?
2690 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2691 ((env->wstate & 0x7) << 2)));
2692 }
2693}
2694
2695void helper_saved(void)
2696{
2697 env->cansave++;
2698 if (env->otherwin == 0)
2699 env->canrestore--;
2700 else
2701 env->otherwin--;
2702}
2703
2704void helper_restored(void)
2705{
2706 env->canrestore++;
1a14026e 2707 if (env->cleanwin < env->nwindows - 1)
72a9747b
BS		 2708 env->cleanwin++;
2709 if (env->otherwin == 0)
2710 env->cansave--;
2711 else
2712 env->otherwin--;
2713}
2714
d35527d9
BS		 2715target_ulong helper_rdccr(void)
2716{
2717 return GET_CCR(env);
2718}
2719
2720void helper_wrccr(target_ulong new_ccr)
2721{
2722 PUT_CCR(env, new_ccr);
2723}
2724
2725// CWP handling is reversed in V9, but we still use the V8 register
2726// order.
2727target_ulong helper_rdcwp(void)
2728{
2729 return GET_CWP64(env);
2730}
2731
2732void helper_wrcwp(target_ulong new_cwp)
2733{
2734 PUT_CWP64(env, new_cwp);
2735}
3475187d 2736
1f5063fb
BS		 2737// This function uses non-native bit order
2738#define GET_FIELD(X, FROM, TO) \
2739 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
2740
2741// This function uses the order in the manuals, i.e. bit 0 is 2^0
2742#define GET_FIELD_SP(X, FROM, TO) \
2743 GET_FIELD(X, 63 - (TO), 63 - (FROM))
2744
2745target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
2746{
2747 return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
2748 (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
2749 (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) |
2750 (GET_FIELD_SP(pixel_addr, 56, 59) << 13) |
2751 (GET_FIELD_SP(pixel_addr, 35, 38) << 9) |
2752 (GET_FIELD_SP(pixel_addr, 13, 16) << 5) |
2753 (((pixel_addr >> 55) & 1) << 4) |
2754 (GET_FIELD_SP(pixel_addr, 33, 34) << 2) |
2755 GET_FIELD_SP(pixel_addr, 11, 12);
2756}
2757
2758target_ulong helper_alignaddr(target_ulong addr, target_ulong offset)
2759{
2760 uint64_t tmp;
2761
2762 tmp = addr + offset;
2763 env->gsr &= ~7ULL;
2764 env->gsr |= tmp & 7ULL;
2765 return tmp & ~7ULL;
2766}
2767
1a2fb1c0 2768target_ulong helper_popc(target_ulong val)
3475187d 2769{
1a2fb1c0 2770 return ctpop64(val);
3475187d 2771}
83469015
FB		 2772
2773static inline uint64_t *get_gregset(uint64_t pstate)
2774{
2775 switch (pstate) {
2776 default:
2777 case 0:
0f8a249a 2778 return env->bgregs;
83469015 2779 case PS_AG:
0f8a249a 2780 return env->agregs;
83469015 2781 case PS_MG:
0f8a249a 2782 return env->mgregs;
83469015 2783 case PS_IG:
0f8a249a 2784 return env->igregs;
83469015
FB		 2785 }
2786}
2787
91736d37 2788static inline void change_pstate(uint64_t new_pstate)
83469015 2789{
8f1f22f6 2790 uint64_t pstate_regs, new_pstate_regs;
83469015
FB		 2791 uint64_t *src, *dst;
2792
83469015
FB		 2793 pstate_regs = env->pstate & 0xc01;
2794 new_pstate_regs = new_pstate & 0xc01;
2795 if (new_pstate_regs != pstate_regs) {
0f8a249a
BS		 2796 // Switch global register bank
2797 src = get_gregset(new_pstate_regs);
2798 dst = get_gregset(pstate_regs);
2799 memcpy32(dst, env->gregs);
2800 memcpy32(env->gregs, src);
83469015
FB		 2801 }
2802 env->pstate = new_pstate;
2803}
2804
1a2fb1c0 2805void helper_wrpstate(target_ulong new_state)
8f1f22f6 2806{
5578ceab 2807 if (!(env->def->features & CPU_FEATURE_GL))
fb79ceb9 2808 change_pstate(new_state & 0xf3f);
8f1f22f6
BS		 2809}
2810
1a2fb1c0 2811void helper_done(void)
83469015 2812{
375ee38b
BS		 2813 env->pc = env->tsptr->tpc;
2814 env->npc = env->tsptr->tnpc + 4;
2815 PUT_CCR(env, env->tsptr->tstate >> 32);
2816 env->asi = (env->tsptr->tstate >> 24) & 0xff;
2817 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2818 PUT_CWP64(env, env->tsptr->tstate & 0xff);
e6bf7d70 2819 env->tl--;
c19148bd 2820 env->tsptr = &env->ts[env->tl & MAXTL_MASK];
83469015
FB		 2821}
2822
1a2fb1c0 2823void helper_retry(void)
83469015 2824{
375ee38b
BS		 2825 env->pc = env->tsptr->tpc;
2826 env->npc = env->tsptr->tnpc;
2827 PUT_CCR(env, env->tsptr->tstate >> 32);
2828 env->asi = (env->tsptr->tstate >> 24) & 0xff;
2829 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2830 PUT_CWP64(env, env->tsptr->tstate & 0xff);
e6bf7d70 2831 env->tl--;
c19148bd 2832 env->tsptr = &env->ts[env->tl & MAXTL_MASK];
83469015 2833}
9d926598
BS		 2834
2835void helper_set_softint(uint64_t value)
2836{
2837 env->softint |= (uint32_t)value;
2838}
2839
2840void helper_clear_softint(uint64_t value)
2841{
2842 env->softint &= (uint32_t)~value;
2843}
2844
2845void helper_write_softint(uint64_t value)
2846{
2847 env->softint = (uint32_t)value;
2848}
3475187d 2849#endif
ee5bbe38 2850
91736d37 2851void helper_flush(target_ulong addr)
ee5bbe38 2852{
91736d37
BS		 2853 addr &= ~7;
2854 tb_invalidate_page_range(addr, addr + 8);
ee5bbe38
FB		 2855}
2856
91736d37
BS		 2857#ifdef TARGET_SPARC64
2858#ifdef DEBUG_PCALL
2859static const char * const excp_names[0x80] = {
2860 [TT_TFAULT] = "Instruction Access Fault",
2861 [TT_TMISS] = "Instruction Access MMU Miss",
2862 [TT_CODE_ACCESS] = "Instruction Access Error",
2863 [TT_ILL_INSN] = "Illegal Instruction",
2864 [TT_PRIV_INSN] = "Privileged Instruction",
2865 [TT_NFPU_INSN] = "FPU Disabled",
2866 [TT_FP_EXCP] = "FPU Exception",
2867 [TT_TOVF] = "Tag Overflow",
2868 [TT_CLRWIN] = "Clean Windows",
2869 [TT_DIV_ZERO] = "Division By Zero",
2870 [TT_DFAULT] = "Data Access Fault",
2871 [TT_DMISS] = "Data Access MMU Miss",
2872 [TT_DATA_ACCESS] = "Data Access Error",
2873 [TT_DPROT] = "Data Protection Error",
2874 [TT_UNALIGNED] = "Unaligned Memory Access",
2875 [TT_PRIV_ACT] = "Privileged Action",
2876 [TT_EXTINT | 0x1] = "External Interrupt 1",
2877 [TT_EXTINT | 0x2] = "External Interrupt 2",
2878 [TT_EXTINT | 0x3] = "External Interrupt 3",
2879 [TT_EXTINT | 0x4] = "External Interrupt 4",
2880 [TT_EXTINT | 0x5] = "External Interrupt 5",
2881 [TT_EXTINT | 0x6] = "External Interrupt 6",
2882 [TT_EXTINT | 0x7] = "External Interrupt 7",
2883 [TT_EXTINT | 0x8] = "External Interrupt 8",
2884 [TT_EXTINT | 0x9] = "External Interrupt 9",
2885 [TT_EXTINT | 0xa] = "External Interrupt 10",
2886 [TT_EXTINT | 0xb] = "External Interrupt 11",
2887 [TT_EXTINT | 0xc] = "External Interrupt 12",
2888 [TT_EXTINT | 0xd] = "External Interrupt 13",
2889 [TT_EXTINT | 0xe] = "External Interrupt 14",
2890 [TT_EXTINT | 0xf] = "External Interrupt 15",
2891};
2892#endif
2893
2894void do_interrupt(CPUState *env)
2895{
2896 int intno = env->exception_index;
2897
2898#ifdef DEBUG_PCALL
8fec2b8c 2899 if (qemu_loglevel_mask(CPU_LOG_INT)) {
91736d37
BS		 2900 static int count;
2901 const char *name;
2902
2903 if (intno < 0 || intno >= 0x180)
2904 name = "Unknown";
2905 else if (intno >= 0x100)
2906 name = "Trap Instruction";
2907 else if (intno >= 0xc0)
2908 name = "Window Fill";
2909 else if (intno >= 0x80)
2910 name = "Window Spill";
2911 else {
2912 name = excp_names[intno];
2913 if (!name)
2914 name = "Unknown";
2915 }
2916
93fcfe39 2917 qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
91736d37
BS		 2918 " SP=%016" PRIx64 "\n",
2919 count, name, intno,
2920 env->pc,
2921 env->npc, env->regwptr[6]);
93fcfe39 2922 log_cpu_state(env, 0);
91736d37
BS		 2923#if 0
2924 {
2925 int i;
2926 uint8_t *ptr;
2927
93fcfe39 2928 qemu_log(" code=");
91736d37
BS		 2929 ptr = (uint8_t *)env->pc;
2930 for(i = 0; i < 16; i++) {
93fcfe39 2931 qemu_log(" %02x", ldub(ptr + i));
91736d37 2932 }
93fcfe39 2933 qemu_log("\n");
91736d37
BS		 2934 }
2935#endif
2936 count++;
2937 }
2938#endif
2939#if !defined(CONFIG_USER_ONLY)
2940 if (env->tl >= env->maxtl) {
2941 cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
2942 " Error state", env->exception_index, env->tl, env->maxtl);
2943 return;
2944 }
2945#endif
2946 if (env->tl < env->maxtl - 1) {
2947 env->tl++;
2948 } else {
2949 env->pstate |= PS_RED;
2950 if (env->tl < env->maxtl)
2951 env->tl++;
2952 }
2953 env->tsptr = &env->ts[env->tl & MAXTL_MASK];
2954 env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
2955 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
2956 GET_CWP64(env);
2957 env->tsptr->tpc = env->pc;
2958 env->tsptr->tnpc = env->npc;
2959 env->tsptr->tt = intno;
2960 if (!(env->def->features & CPU_FEATURE_GL)) {
2961 switch (intno) {
2962 case TT_IVEC:
2963 change_pstate(PS_PEF | PS_PRIV | PS_IG);
2964 break;
2965 case TT_TFAULT:
2966 case TT_TMISS:
2967 case TT_DFAULT:
2968 case TT_DMISS:
2969 case TT_DPROT:
2970 change_pstate(PS_PEF | PS_PRIV | PS_MG);
2971 break;
2972 default:
2973 change_pstate(PS_PEF | PS_PRIV | PS_AG);
2974 break;
2975 }
2976 }
2977 if (intno == TT_CLRWIN)
2978 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
2979 else if ((intno & 0x1c0) == TT_SPILL)
2980 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
2981 else if ((intno & 0x1c0) == TT_FILL)
2982 cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
2983 env->tbr &= ~0x7fffULL;
2984 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
2985 env->pc = env->tbr;
2986 env->npc = env->pc + 4;
2987 env->exception_index = 0;
ee5bbe38 2988}
91736d37
BS		 2989#else
2990#ifdef DEBUG_PCALL
2991static const char * const excp_names[0x80] = {
2992 [TT_TFAULT] = "Instruction Access Fault",
2993 [TT_ILL_INSN] = "Illegal Instruction",
2994 [TT_PRIV_INSN] = "Privileged Instruction",
2995 [TT_NFPU_INSN] = "FPU Disabled",
2996 [TT_WIN_OVF] = "Window Overflow",
2997 [TT_WIN_UNF] = "Window Underflow",
2998 [TT_UNALIGNED] = "Unaligned Memory Access",
2999 [TT_FP_EXCP] = "FPU Exception",
3000 [TT_DFAULT] = "Data Access Fault",
3001 [TT_TOVF] = "Tag Overflow",
3002 [TT_EXTINT | 0x1] = "External Interrupt 1",
3003 [TT_EXTINT | 0x2] = "External Interrupt 2",
3004 [TT_EXTINT | 0x3] = "External Interrupt 3",
3005 [TT_EXTINT | 0x4] = "External Interrupt 4",
3006 [TT_EXTINT | 0x5] = "External Interrupt 5",
3007 [TT_EXTINT | 0x6] = "External Interrupt 6",
3008 [TT_EXTINT | 0x7] = "External Interrupt 7",
3009 [TT_EXTINT | 0x8] = "External Interrupt 8",
3010 [TT_EXTINT | 0x9] = "External Interrupt 9",
3011 [TT_EXTINT | 0xa] = "External Interrupt 10",
3012 [TT_EXTINT | 0xb] = "External Interrupt 11",
3013 [TT_EXTINT | 0xc] = "External Interrupt 12",
3014 [TT_EXTINT | 0xd] = "External Interrupt 13",
3015 [TT_EXTINT | 0xe] = "External Interrupt 14",
3016 [TT_EXTINT | 0xf] = "External Interrupt 15",
3017 [TT_TOVF] = "Tag Overflow",
3018 [TT_CODE_ACCESS] = "Instruction Access Error",
3019 [TT_DATA_ACCESS] = "Data Access Error",
3020 [TT_DIV_ZERO] = "Division By Zero",
3021 [TT_NCP_INSN] = "Coprocessor Disabled",
3022};
3023#endif
ee5bbe38 3024
91736d37 3025void do_interrupt(CPUState *env)
ee5bbe38 3026{
91736d37
BS		 3027 int cwp, intno = env->exception_index;
3028
3029#ifdef DEBUG_PCALL
8fec2b8c 3030 if (qemu_loglevel_mask(CPU_LOG_INT)) {
91736d37
BS		 3031 static int count;
3032 const char *name;
3033
3034 if (intno < 0 || intno >= 0x100)
3035 name = "Unknown";
3036 else if (intno >= 0x80)
3037 name = "Trap Instruction";
3038 else {
3039 name = excp_names[intno];
3040 if (!name)
3041 name = "Unknown";
3042 }
3043
93fcfe39 3044 qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
91736d37
BS		 3045 count, name, intno,
3046 env->pc,
3047 env->npc, env->regwptr[6]);
93fcfe39 3048 log_cpu_state(env, 0);
91736d37
BS		 3049#if 0
3050 {
3051 int i;
3052 uint8_t *ptr;
3053
93fcfe39 3054 qemu_log(" code=");
91736d37
BS		 3055 ptr = (uint8_t *)env->pc;
3056 for(i = 0; i < 16; i++) {
93fcfe39 3057 qemu_log(" %02x", ldub(ptr + i));
91736d37 3058 }
93fcfe39 3059 qemu_log("\n");
91736d37
BS		 3060 }
3061#endif
3062 count++;
3063 }
3064#endif
3065#if !defined(CONFIG_USER_ONLY)
3066 if (env->psret == 0) {
3067 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
3068 env->exception_index);
3069 return;
3070 }
3071#endif
3072 env->psret = 0;
3073 cwp = cpu_cwp_dec(env, env->cwp - 1);
3074 cpu_set_cwp(env, cwp);
3075 env->regwptr[9] = env->pc;
3076 env->regwptr[10] = env->npc;
3077 env->psrps = env->psrs;
3078 env->psrs = 1;
3079 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
3080 env->pc = env->tbr;
3081 env->npc = env->pc + 4;
3082 env->exception_index = 0;
ee5bbe38 3083}
91736d37 3084#endif
ee5bbe38 3085
5fafdf24 3086#if !defined(CONFIG_USER_ONLY)
ee5bbe38 3087
d2889a3e
BS		 3088static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
3089 void *retaddr);
3090
ee5bbe38 3091#define MMUSUFFIX _mmu
d2889a3e 3092#define ALIGNED_ONLY
ee5bbe38
FB		 3093
3094#define SHIFT 0
3095#include "softmmu_template.h"
3096
3097#define SHIFT 1
3098#include "softmmu_template.h"
3099
3100#define SHIFT 2
3101#include "softmmu_template.h"
3102
3103#define SHIFT 3
3104#include "softmmu_template.h"
3105
c2bc0e38
BS		 3106/* XXX: make it generic ? */
3107static void cpu_restore_state2(void *retaddr)
3108{
3109 TranslationBlock *tb;
3110 unsigned long pc;
3111
3112 if (retaddr) {
3113 /* now we have a real cpu fault */
3114 pc = (unsigned long)retaddr;
3115 tb = tb_find_pc(pc);
3116 if (tb) {
3117 /* the PC is inside the translated code. It means that we have
3118 a virtual CPU fault */
3119 cpu_restore_state(tb, env, pc, (void *)(long)env->cond);
3120 }
3121 }
3122}
3123
d2889a3e
BS		 3124static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
3125 void *retaddr)
3126{
94554550 3127#ifdef DEBUG_UNALIGNED
c2bc0e38
BS		 3128 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
3129 "\n", addr, env->pc);
94554550 3130#endif
c2bc0e38 3131 cpu_restore_state2(retaddr);
94554550 3132 raise_exception(TT_UNALIGNED);
d2889a3e 3133}
ee5bbe38
FB		 3134
3135/* try to fill the TLB and return an exception if error. If retaddr is
3136 NULL, it means that the function was called in C code (i.e. not
3137 from generated code or from helper.c) */
3138/* XXX: fix it to restore all registers */
6ebbf390 3139void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
ee5bbe38 3140{
ee5bbe38 3141 int ret;
ee5bbe38
FB		 3142 CPUState *saved_env;
3143
3144 /* XXX: hack to restore env in all cases, even if not called from
3145 generated code */
3146 saved_env = env;
3147 env = cpu_single_env;
3148
6ebbf390 3149 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ee5bbe38 3150 if (ret) {
c2bc0e38 3151 cpu_restore_state2(retaddr);
ee5bbe38
FB		 3152 cpu_loop_exit();
3153 }
3154 env = saved_env;
3155}
3156
3157#endif
6c36d3fa
BS		 3158
3159#ifndef TARGET_SPARC64
5dcb6b91 3160void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
e18231a3 3161 int is_asi, int size)
6c36d3fa
BS		 3162{
3163 CPUState *saved_env;
3164
3165 /* XXX: hack to restore env in all cases, even if not called from
3166 generated code */
3167 saved_env = env;
3168 env = cpu_single_env;
8543e2cf
BS		 3169#ifdef DEBUG_UNASSIGNED
3170 if (is_asi)
e18231a3 3171 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
77f193da 3172 " asi 0x%02x from " TARGET_FMT_lx "\n",
e18231a3
BS		 3173 is_exec ? "exec" : is_write ? "write" : "read", size,
3174 size == 1 ? "" : "s", addr, is_asi, env->pc);
8543e2cf 3175 else
e18231a3
BS		 3176 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
3177 " from " TARGET_FMT_lx "\n",
3178 is_exec ? "exec" : is_write ? "write" : "read", size,
3179 size == 1 ? "" : "s", addr, env->pc);
8543e2cf 3180#endif
6c36d3fa 3181 if (env->mmuregs[3]) /* Fault status register */
0f8a249a 3182 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
6c36d3fa
BS		 3183 if (is_asi)
3184 env->mmuregs[3] |= 1 << 16;
3185 if (env->psrs)
3186 env->mmuregs[3] |= 1 << 5;
3187 if (is_exec)
3188 env->mmuregs[3] |= 1 << 6;
3189 if (is_write)
3190 env->mmuregs[3] |= 1 << 7;
3191 env->mmuregs[3] |= (5 << 2) | 2;
3192 env->mmuregs[4] = addr; /* Fault address register */
3193 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
1b2e93c1
BS		 3194 if (is_exec)
3195 raise_exception(TT_CODE_ACCESS);
3196 else
3197 raise_exception(TT_DATA_ACCESS);
6c36d3fa
BS		 3198 }
3199 env = saved_env;
3200}
3201#else
5dcb6b91 3202void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
e18231a3 3203 int is_asi, int size)
6c36d3fa
BS		 3204{
3205#ifdef DEBUG_UNASSIGNED
3206 CPUState *saved_env;
3207
3208 /* XXX: hack to restore env in all cases, even if not called from
3209 generated code */
3210 saved_env = env;
3211 env = cpu_single_env;
77f193da
BS		 3212 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
3213 "\n", addr, env->pc);
6c36d3fa
BS		 3214 env = saved_env;
3215#endif
1b2e93c1
BS		 3216 if (is_exec)
3217 raise_exception(TT_CODE_ACCESS);
3218 else
3219 raise_exception(TT_DATA_ACCESS);
6c36d3fa
BS		 3220}
3221#endif
20c9f095 3222
f4b1a842
BS		 3223#ifdef TARGET_SPARC64
3224void helper_tick_set_count(void *opaque, uint64_t count)
3225{
3226#if !defined(CONFIG_USER_ONLY)
3227 cpu_tick_set_count(opaque, count);
3228#endif
3229}
3230
3231uint64_t helper_tick_get_count(void *opaque)
3232{
3233#if !defined(CONFIG_USER_ONLY)
3234 return cpu_tick_get_count(opaque);
3235#else
3236 return 0;
3237#endif
3238}
3239
3240void helper_tick_set_limit(void *opaque, uint64_t limit)
3241{
3242#if !defined(CONFIG_USER_ONLY)
3243 cpu_tick_set_limit(opaque, limit);
3244#endif
3245}
3246#endif
Qemu copy for testing