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Set initial value of AFSR register properly (Robert Reif)
[qemu.git] / target-sparc / op_helper.c
CommitLineData
e8af50a3 1#include "exec.h"
eed152bb 2#include "host-utils.h"
e8af50a3 3
83469015 4//#define DEBUG_PCALL
e80cfcfc 5//#define DEBUG_MMU
952a328f 6//#define DEBUG_MXCC
94554550 7//#define DEBUG_UNALIGNED
6c36d3fa 8//#define DEBUG_UNASSIGNED
e80cfcfc 9
952a328f
BS		 10#ifdef DEBUG_MMU
11#define DPRINTF_MMU(fmt, args...) \
12do { printf("MMU: " fmt , ##args); } while (0)
13#else
14#define DPRINTF_MMU(fmt, args...)
15#endif
16
17#ifdef DEBUG_MXCC
18#define DPRINTF_MXCC(fmt, args...) \
19do { printf("MXCC: " fmt , ##args); } while (0)
20#else
21#define DPRINTF_MXCC(fmt, args...)
22#endif
23
9d893301
FB		 24void raise_exception(int tt)
25{
26 env->exception_index = tt;
27 cpu_loop_exit();
3b46e624 28}
9d893301 29
417454b0
BS		 30void check_ieee_exceptions()
31{
32 T0 = get_float_exception_flags(&env->fp_status);
33 if (T0)
34 {
0f8a249a
BS		 35 /* Copy IEEE 754 flags into FSR */
36 if (T0 & float_flag_invalid)
37 env->fsr |= FSR_NVC;
38 if (T0 & float_flag_overflow)
39 env->fsr |= FSR_OFC;
40 if (T0 & float_flag_underflow)
41 env->fsr |= FSR_UFC;
42 if (T0 & float_flag_divbyzero)
43 env->fsr |= FSR_DZC;
44 if (T0 & float_flag_inexact)
45 env->fsr |= FSR_NXC;
46
47 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23))
48 {
49 /* Unmasked exception, generate a trap */
50 env->fsr |= FSR_FTT_IEEE_EXCP;
51 raise_exception(TT_FP_EXCP);
52 }
53 else
54 {
55 /* Accumulate exceptions */
56 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
57 }
417454b0
BS		 58 }
59}
60
a0c4cb4a
FB		 61#ifdef USE_INT_TO_FLOAT_HELPERS
62void do_fitos(void)
63{
417454b0 64 set_float_exception_flags(0, &env->fp_status);
ec230928 65 FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
417454b0 66 check_ieee_exceptions();
a0c4cb4a
FB		 67}
68
69void do_fitod(void)
70{
ec230928 71 DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
a0c4cb4a 72}
1e64e78d
BS		 73#ifdef TARGET_SPARC64
74void do_fxtos(void)
75{
76 set_float_exception_flags(0, &env->fp_status);
77 FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
78 check_ieee_exceptions();
79}
80
81void do_fxtod(void)
82{
83 set_float_exception_flags(0, &env->fp_status);
84 DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
85 check_ieee_exceptions();
86}
87#endif
a0c4cb4a
FB		 88#endif
89
90void do_fabss(void)
e8af50a3 91{
7a0e1f41 92 FT0 = float32_abs(FT1);
e8af50a3
FB		 93}
94
3475187d
FB		 95#ifdef TARGET_SPARC64
96void do_fabsd(void)
97{
98 DT0 = float64_abs(DT1);
99}
100#endif
101
a0c4cb4a 102void do_fsqrts(void)
e8af50a3 103{
417454b0 104 set_float_exception_flags(0, &env->fp_status);
7a0e1f41 105 FT0 = float32_sqrt(FT1, &env->fp_status);
417454b0 106 check_ieee_exceptions();
e8af50a3
FB		 107}
108
a0c4cb4a 109void do_fsqrtd(void)
e8af50a3 110{
417454b0 111 set_float_exception_flags(0, &env->fp_status);
7a0e1f41 112 DT0 = float64_sqrt(DT1, &env->fp_status);
417454b0 113 check_ieee_exceptions();
e8af50a3
FB		 114}
115
417454b0 116#define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
65ce8c2f
FB		 117 void glue(do_, name) (void) \
118 { \
119 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
120 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
121 case float_relation_unordered: \
122 T0 = (FSR_FCC1 | FSR_FCC0) << FS; \
417454b0 123 if ((env->fsr & FSR_NVM) || TRAP) { \
65ce8c2f 124 env->fsr |= T0; \
417454b0
BS		 125 env->fsr |= FSR_NVC; \
126 env->fsr |= FSR_FTT_IEEE_EXCP; \
65ce8c2f
FB		 127 raise_exception(TT_FP_EXCP); \
128 } else { \
129 env->fsr |= FSR_NVA; \
130 } \
131 break; \
132 case float_relation_less: \
133 T0 = FSR_FCC0 << FS; \
134 break; \
135 case float_relation_greater: \
136 T0 = FSR_FCC1 << FS; \
137 break; \
138 default: \
139 T0 = 0; \
140 break; \
141 } \
142 env->fsr |= T0; \
e8af50a3 143 }
e8af50a3 144
417454b0
BS		 145GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0);
146GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
147
148GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1);
149GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
3475187d
FB		 150
151#ifdef TARGET_SPARC64
417454b0
BS		 152GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0);
153GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
154
155GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0);
156GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
157
158GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0);
159GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
160
161GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1);
162GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
3475187d 163
417454b0
BS		 164GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1);
165GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
3475187d 166
417454b0
BS		 167GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1);
168GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
3475187d
FB		 169#endif
170
171#ifndef TARGET_SPARC64
81ad8ba2 172#ifndef CONFIG_USER_ONLY
952a328f
BS		 173
174#ifdef DEBUG_MXCC
175static void dump_mxcc(CPUState *env)
176{
177 printf("mxccdata: %016llx %016llx %016llx %016llx\n",
178 env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]);
179 printf("mxccregs: %016llx %016llx %016llx %016llx\n"
180 " %016llx %016llx %016llx %016llx\n",
181 env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3],
182 env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]);
183}
184#endif
185
a0c4cb4a 186void helper_ld_asi(int asi, int size, int sign)
e8af50a3 187{
83469015 188 uint32_t ret = 0;
e909ec2f 189 uint64_t tmp;
952a328f
BS		 190#ifdef DEBUG_MXCC
191 uint32_t last_T0 = T0;
192#endif
e80cfcfc
FB		 193
194 switch (asi) {
6c36d3fa 195 case 2: /* SuperSparc MXCC registers */
952a328f
BS		 196 switch (T0) {
197 case 0x01c00a00: /* MXCC control register */
198 if (size == 8) {
d07b4d0e
BS		 199 ret = env->mxccregs[3] >> 32;
200 T0 = env->mxccregs[3];
952a328f
BS		 201 } else
202 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
203 break;
204 case 0x01c00a04: /* MXCC control register */
205 if (size == 4)
206 ret = env->mxccregs[3];
207 else
208 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
209 break;
295db113
BS		 210 case 0x01c00c00: /* Module reset register */
211 if (size == 8) {
212 ret = env->mxccregs[5] >> 32;
213 T0 = env->mxccregs[5];
214 // should we do something here?
215 } else
216 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
217 break;
952a328f
BS		 218 case 0x01c00f00: /* MBus port address register */
219 if (size == 8) {
d07b4d0e
BS		 220 ret = env->mxccregs[7] >> 32;
221 T0 = env->mxccregs[7];
952a328f
BS		 222 } else
223 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
224 break;
225 default:
226 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size);
227 break;
228 }
229 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, T0 = %08x -> ret = %08x,"
230 "T0 = %08x\n", asi, size, sign, last_T0, ret, T0);
231#ifdef DEBUG_MXCC
232 dump_mxcc(env);
233#endif
6c36d3fa 234 break;
e8af50a3 235 case 3: /* MMU probe */
0f8a249a
BS		 236 {
237 int mmulev;
238
239 mmulev = (T0 >> 8) & 15;
240 if (mmulev > 4)
241 ret = 0;
242 else {
243 ret = mmu_probe(env, T0, mmulev);
244 //bswap32s(&ret);
245 }
952a328f 246 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
0f8a249a
BS		 247 }
248 break;
e8af50a3 249 case 4: /* read MMU regs */
0f8a249a 250 {
3dd9a152 251 int reg = (T0 >> 8) & 0x1f;
3b46e624 252
0f8a249a
BS		 253 ret = env->mmuregs[reg];
254 if (reg == 3) /* Fault status cleared on read */
3dd9a152
BS		 255 env->mmuregs[3] = 0;
256 else if (reg == 0x13) /* Fault status read */
257 ret = env->mmuregs[3];
258 else if (reg == 0x14) /* Fault address read */
259 ret = env->mmuregs[4];
952a328f 260 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
0f8a249a
BS		 261 }
262 break;
6c36d3fa
BS		 263 case 9: /* Supervisor code access */
264 switch(size) {
265 case 1:
266 ret = ldub_code(T0);
267 break;
268 case 2:
269 ret = lduw_code(T0 & ~1);
270 break;
271 default:
272 case 4:
273 ret = ldl_code(T0 & ~3);
274 break;
275 case 8:
e909ec2f
BS		 276 tmp = ldq_code(T0 & ~7);
277 ret = tmp >> 32;
2761992d 278 T0 = tmp;
6c36d3fa
BS		 279 break;
280 }
281 break;
81ad8ba2
BS		 282 case 0xa: /* User data access */
283 switch(size) {
284 case 1:
285 ret = ldub_user(T0);
286 break;
287 case 2:
288 ret = lduw_user(T0 & ~1);
289 break;
290 default:
291 case 4:
292 ret = ldl_user(T0 & ~3);
293 break;
294 case 8:
e909ec2f
BS		 295 tmp = ldq_user(T0 & ~7);
296 ret = tmp >> 32;
2761992d 297 T0 = tmp;
81ad8ba2
BS		 298 break;
299 }
300 break;
301 case 0xb: /* Supervisor data access */
302 switch(size) {
303 case 1:
304 ret = ldub_kernel(T0);
305 break;
306 case 2:
307 ret = lduw_kernel(T0 & ~1);
308 break;
309 default:
310 case 4:
311 ret = ldl_kernel(T0 & ~3);
312 break;
313 case 8:
e909ec2f
BS		 314 tmp = ldq_kernel(T0 & ~7);
315 ret = tmp >> 32;
2761992d 316 T0 = tmp;
81ad8ba2
BS		 317 break;
318 }
319 break;
6c36d3fa
BS		 320 case 0xc: /* I-cache tag */
321 case 0xd: /* I-cache data */
322 case 0xe: /* D-cache tag */
323 case 0xf: /* D-cache data */
324 break;
325 case 0x20: /* MMU passthrough */
02aab46a
FB		 326 switch(size) {
327 case 1:
328 ret = ldub_phys(T0);
329 break;
330 case 2:
331 ret = lduw_phys(T0 & ~1);
332 break;
333 default:
334 case 4:
335 ret = ldl_phys(T0 & ~3);
336 break;
9e61bde5 337 case 8:
e909ec2f
BS		 338 tmp = ldq_phys(T0 & ~7);
339 ret = tmp >> 32;
2761992d 340 T0 = tmp;
0f8a249a 341 break;
02aab46a 342 }
0f8a249a 343 break;
5dcb6b91
BS		 344 case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
345 case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
346 switch(size) {
347 case 1:
348 ret = ldub_phys((target_phys_addr_t)T0
349 | ((target_phys_addr_t)(asi & 0xf) << 32));
350 break;
351 case 2:
352 ret = lduw_phys((target_phys_addr_t)(T0 & ~1)
353 | ((target_phys_addr_t)(asi & 0xf) << 32));
354 break;
355 default:
356 case 4:
357 ret = ldl_phys((target_phys_addr_t)(T0 & ~3)
358 | ((target_phys_addr_t)(asi & 0xf) << 32));
359 break;
360 case 8:
e909ec2f 361 tmp = ldq_phys((target_phys_addr_t)(T0 & ~7)
5dcb6b91 362 | ((target_phys_addr_t)(asi & 0xf) << 32));
e909ec2f 363 ret = tmp >> 32;
2761992d 364 T0 = tmp;
0f8a249a 365 break;
5dcb6b91 366 }
0f8a249a 367 break;
5dcb6b91 368 case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
e8af50a3 369 default:
6c36d3fa 370 do_unassigned_access(T0, 0, 0, 1);
0f8a249a
BS		 371 ret = 0;
372 break;
e8af50a3 373 }
81ad8ba2
BS		 374 if (sign) {
375 switch(size) {
376 case 1:
377 T1 = (int8_t) ret;
e32664fb 378 break;
81ad8ba2
BS		 379 case 2:
380 T1 = (int16_t) ret;
e32664fb 381 break;
81ad8ba2
BS		 382 default:
383 T1 = ret;
384 break;
385 }
386 }
387 else
388 T1 = ret;
e8af50a3
FB		 389}
390
81ad8ba2 391void helper_st_asi(int asi, int size)
e8af50a3
FB		 392{
393 switch(asi) {
6c36d3fa 394 case 2: /* SuperSparc MXCC registers */
952a328f
BS		 395 switch (T0) {
396 case 0x01c00000: /* MXCC stream data register 0 */
397 if (size == 8)
398 env->mxccdata[0] = ((uint64_t)T1 << 32) | T2;
399 else
400 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
401 break;
402 case 0x01c00008: /* MXCC stream data register 1 */
403 if (size == 8)
404 env->mxccdata[1] = ((uint64_t)T1 << 32) | T2;
405 else
406 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
407 break;
408 case 0x01c00010: /* MXCC stream data register 2 */
409 if (size == 8)
410 env->mxccdata[2] = ((uint64_t)T1 << 32) | T2;
411 else
412 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
413 break;
414 case 0x01c00018: /* MXCC stream data register 3 */
415 if (size == 8)
416 env->mxccdata[3] = ((uint64_t)T1 << 32) | T2;
417 else
418 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
419 break;
420 case 0x01c00100: /* MXCC stream source */
421 if (size == 8)
422 env->mxccregs[0] = ((uint64_t)T1 << 32) | T2;
423 else
424 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
425 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0);
426 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8);
427 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16);
428 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 24);
429 break;
430 case 0x01c00200: /* MXCC stream destination */
431 if (size == 8)
432 env->mxccregs[1] = ((uint64_t)T1 << 32) | T2;
433 else
434 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
435 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]);
436 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]);
437 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]);
438 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, env->mxccdata[3]);
439 break;
440 case 0x01c00a00: /* MXCC control register */
441 if (size == 8)
442 env->mxccregs[3] = ((uint64_t)T1 << 32) | T2;
443 else
444 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
445 break;
446 case 0x01c00a04: /* MXCC control register */
447 if (size == 4)
bd37ec21 448 env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) | T1;
952a328f
BS		 449 else
450 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
451 break;
452 case 0x01c00e00: /* MXCC error register */
bbf7d96b 453 // writing a 1 bit clears the error
952a328f 454 if (size == 8)
bbf7d96b 455 env->mxccregs[6] &= ~(((uint64_t)T1 << 32) | T2);
952a328f
BS		 456 else
457 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
952a328f
BS		 458 break;
459 case 0x01c00f00: /* MBus port address register */
460 if (size == 8)
461 env->mxccregs[7] = ((uint64_t)T1 << 32) | T2;
462 else
463 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
464 break;
465 default:
466 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size);
467 break;
468 }
469 DPRINTF_MXCC("asi = %d, size = %d, T0 = %08x, T1 = %08x\n", asi, size, T0, T1);
470#ifdef DEBUG_MXCC
471 dump_mxcc(env);
472#endif
6c36d3fa 473 break;
e8af50a3 474 case 3: /* MMU flush */
0f8a249a
BS		 475 {
476 int mmulev;
e80cfcfc 477
0f8a249a 478 mmulev = (T0 >> 8) & 15;
952a328f 479 DPRINTF_MMU("mmu flush level %d\n", mmulev);
0f8a249a
BS		 480 switch (mmulev) {
481 case 0: // flush page
482 tlb_flush_page(env, T0 & 0xfffff000);
483 break;
484 case 1: // flush segment (256k)
485 case 2: // flush region (16M)
486 case 3: // flush context (4G)
487 case 4: // flush entire
488 tlb_flush(env, 1);
489 break;
490 default:
491 break;
492 }
55754d9e 493#ifdef DEBUG_MMU
0f8a249a 494 dump_mmu(env);
55754d9e 495#endif
0f8a249a
BS		 496 return;
497 }
e8af50a3 498 case 4: /* write MMU regs */
0f8a249a 499 {
3dd9a152 500 int reg = (T0 >> 8) & 0x1f;
0f8a249a 501 uint32_t oldreg;
3b46e624 502
0f8a249a 503 oldreg = env->mmuregs[reg];
55754d9e
FB		 504 switch(reg) {
505 case 0:
3dd9a152
BS		 506 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
507 (T1 & 0x00ffffff);
0f8a249a
BS		 508 // Mappings generated during no-fault mode or MMU
509 // disabled mode are invalid in normal mode
3dd9a152
BS		 510 if ((oldreg & (MMU_E | MMU_NF | env->mmu_bm)) !=
511 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->mmu_bm)))
55754d9e
FB		 512 tlb_flush(env, 1);
513 break;
514 case 2:
0f8a249a 515 env->mmuregs[reg] = T1;
55754d9e
FB		 516 if (oldreg != env->mmuregs[reg]) {
517 /* we flush when the MMU context changes because
518 QEMU has no MMU context support */
519 tlb_flush(env, 1);
520 }
521 break;
522 case 3:
523 case 4:
524 break;
3dd9a152
BS		 525 case 0x13:
526 env->mmuregs[3] = T1;
527 break;
528 case 0x14:
529 env->mmuregs[4] = T1;
530 break;
55754d9e 531 default:
0f8a249a 532 env->mmuregs[reg] = T1;
55754d9e
FB		 533 break;
534 }
55754d9e 535 if (oldreg != env->mmuregs[reg]) {
952a328f 536 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
55754d9e 537 }
952a328f 538#ifdef DEBUG_MMU
0f8a249a 539 dump_mmu(env);
55754d9e 540#endif
0f8a249a
BS		 541 return;
542 }
81ad8ba2
BS		 543 case 0xa: /* User data access */
544 switch(size) {
545 case 1:
546 stb_user(T0, T1);
547 break;
548 case 2:
549 stw_user(T0 & ~1, T1);
550 break;
551 default:
552 case 4:
553 stl_user(T0 & ~3, T1);
554 break;
555 case 8:
e909ec2f 556 stq_user(T0 & ~7, ((uint64_t)T1 << 32) | T2);
81ad8ba2
BS		 557 break;
558 }
559 break;
560 case 0xb: /* Supervisor data access */
561 switch(size) {
562 case 1:
563 stb_kernel(T0, T1);
564 break;
565 case 2:
566 stw_kernel(T0 & ~1, T1);
567 break;
568 default:
569 case 4:
570 stl_kernel(T0 & ~3, T1);
571 break;
572 case 8:
e909ec2f 573 stq_kernel(T0 & ~7, ((uint64_t)T1 << 32) | T2);
81ad8ba2
BS		 574 break;
575 }
576 break;
6c36d3fa
BS		 577 case 0xc: /* I-cache tag */
578 case 0xd: /* I-cache data */
579 case 0xe: /* D-cache tag */
580 case 0xf: /* D-cache data */
581 case 0x10: /* I/D-cache flush page */
582 case 0x11: /* I/D-cache flush segment */
583 case 0x12: /* I/D-cache flush region */
584 case 0x13: /* I/D-cache flush context */
585 case 0x14: /* I/D-cache flush user */
586 break;
e80cfcfc 587 case 0x17: /* Block copy, sta access */
0f8a249a
BS		 588 {
589 // value (T1) = src
590 // address (T0) = dst
591 // copy 32 bytes
6c36d3fa
BS		 592 unsigned int i;
593 uint32_t src = T1 & ~3, dst = T0 & ~3, temp;
3b46e624 594
6c36d3fa
BS		 595 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
596 temp = ldl_kernel(src);
597 stl_kernel(dst, temp);
598 }
0f8a249a
BS		 599 }
600 return;
e80cfcfc 601 case 0x1f: /* Block fill, stda access */
0f8a249a
BS		 602 {
603 // value (T1, T2)
604 // address (T0) = dst
605 // fill 32 bytes
6c36d3fa
BS		 606 unsigned int i;
607 uint32_t dst = T0 & 7;
608 uint64_t val;
e80cfcfc 609
6c36d3fa
BS		 610 val = (((uint64_t)T1) << 32) | T2;
611
612 for (i = 0; i < 32; i += 8, dst += 8)
613 stq_kernel(dst, val);
0f8a249a
BS		 614 }
615 return;
6c36d3fa 616 case 0x20: /* MMU passthrough */
0f8a249a 617 {
02aab46a
FB		 618 switch(size) {
619 case 1:
620 stb_phys(T0, T1);
621 break;
622 case 2:
623 stw_phys(T0 & ~1, T1);
624 break;
625 case 4:
626 default:
627 stl_phys(T0 & ~3, T1);
628 break;
9e61bde5 629 case 8:
e909ec2f 630 stq_phys(T0 & ~7, ((uint64_t)T1 << 32) | T2);
9e61bde5 631 break;
02aab46a 632 }
0f8a249a
BS		 633 }
634 return;
5dcb6b91
BS		 635 case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
636 case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
0f8a249a 637 {
5dcb6b91
BS		 638 switch(size) {
639 case 1:
640 stb_phys((target_phys_addr_t)T0
641 | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
642 break;
643 case 2:
644 stw_phys((target_phys_addr_t)(T0 & ~1)
645 | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
646 break;
647 case 4:
648 default:
649 stl_phys((target_phys_addr_t)(T0 & ~3)
650 | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
651 break;
652 case 8:
e909ec2f
BS		 653 stq_phys((target_phys_addr_t)(T0 & ~7)
654 | ((target_phys_addr_t)(asi & 0xf) << 32),
655 ((uint64_t)T1 << 32) | T2);
5dcb6b91
BS		 656 break;
657 }
0f8a249a
BS		 658 }
659 return;
6c36d3fa
BS		 660 case 0x31: /* Ross RT620 I-cache flush */
661 case 0x36: /* I-cache flash clear */
662 case 0x37: /* D-cache flash clear */
663 break;
664 case 9: /* Supervisor code access, XXX */
5dcb6b91 665 case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
e8af50a3 666 default:
6c36d3fa 667 do_unassigned_access(T0, 1, 0, 1);
0f8a249a 668 return;
e8af50a3
FB		 669 }
670}
671
81ad8ba2
BS		 672#endif /* CONFIG_USER_ONLY */
673#else /* TARGET_SPARC64 */
674
675#ifdef CONFIG_USER_ONLY
676void helper_ld_asi(int asi, int size, int sign)
677{
678 uint64_t ret = 0;
679
680 if (asi < 0x80)
681 raise_exception(TT_PRIV_ACT);
682
683 switch (asi) {
684 case 0x80: // Primary
685 case 0x82: // Primary no-fault
686 case 0x88: // Primary LE
687 case 0x8a: // Primary no-fault LE
688 {
689 switch(size) {
690 case 1:
691 ret = ldub_raw(T0);
692 break;
693 case 2:
694 ret = lduw_raw(T0 & ~1);
695 break;
696 case 4:
697 ret = ldl_raw(T0 & ~3);
698 break;
699 default:
700 case 8:
701 ret = ldq_raw(T0 & ~7);
702 break;
703 }
704 }
705 break;
706 case 0x81: // Secondary
707 case 0x83: // Secondary no-fault
708 case 0x89: // Secondary LE
709 case 0x8b: // Secondary no-fault LE
710 // XXX
711 break;
712 default:
713 break;
714 }
715
716 /* Convert from little endian */
717 switch (asi) {
718 case 0x88: // Primary LE
719 case 0x89: // Secondary LE
720 case 0x8a: // Primary no-fault LE
721 case 0x8b: // Secondary no-fault LE
722 switch(size) {
723 case 2:
724 ret = bswap16(ret);
e32664fb 725 break;
81ad8ba2
BS		 726 case 4:
727 ret = bswap32(ret);
e32664fb 728 break;
81ad8ba2
BS		 729 case 8:
730 ret = bswap64(ret);
e32664fb 731 break;
81ad8ba2
BS		 732 default:
733 break;
734 }
735 default:
736 break;
737 }
738
739 /* Convert to signed number */
740 if (sign) {
741 switch(size) {
742 case 1:
743 ret = (int8_t) ret;
e32664fb 744 break;
81ad8ba2
BS		 745 case 2:
746 ret = (int16_t) ret;
e32664fb 747 break;
81ad8ba2
BS		 748 case 4:
749 ret = (int32_t) ret;
e32664fb 750 break;
81ad8ba2
BS		 751 default:
752 break;
753 }
754 }
755 T1 = ret;
756}
757
758void helper_st_asi(int asi, int size)
759{
760 if (asi < 0x80)
761 raise_exception(TT_PRIV_ACT);
762
763 /* Convert to little endian */
764 switch (asi) {
765 case 0x88: // Primary LE
766 case 0x89: // Secondary LE
767 switch(size) {
768 case 2:
769 T0 = bswap16(T0);
e32664fb 770 break;
81ad8ba2
BS		 771 case 4:
772 T0 = bswap32(T0);
e32664fb 773 break;
81ad8ba2
BS		 774 case 8:
775 T0 = bswap64(T0);
e32664fb 776 break;
81ad8ba2
BS		 777 default:
778 break;
779 }
780 default:
781 break;
782 }
783
784 switch(asi) {
785 case 0x80: // Primary
786 case 0x88: // Primary LE
787 {
788 switch(size) {
789 case 1:
790 stb_raw(T0, T1);
791 break;
792 case 2:
793 stw_raw(T0 & ~1, T1);
794 break;
795 case 4:
796 stl_raw(T0 & ~3, T1);
797 break;
798 case 8:
799 default:
800 stq_raw(T0 & ~7, T1);
801 break;
802 }
803 }
804 break;
805 case 0x81: // Secondary
806 case 0x89: // Secondary LE
807 // XXX
808 return;
809
810 case 0x82: // Primary no-fault, RO
811 case 0x83: // Secondary no-fault, RO
812 case 0x8a: // Primary no-fault LE, RO
813 case 0x8b: // Secondary no-fault LE, RO
814 default:
815 do_unassigned_access(T0, 1, 0, 1);
816 return;
817 }
818}
819
820#else /* CONFIG_USER_ONLY */
3475187d
FB		 821
822void helper_ld_asi(int asi, int size, int sign)
823{
83469015 824 uint64_t ret = 0;
3475187d 825
6f27aba6 826 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
20b749f6 827 || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
0f8a249a 828 raise_exception(TT_PRIV_ACT);
3475187d
FB		 829
830 switch (asi) {
81ad8ba2
BS		 831 case 0x10: // As if user primary
832 case 0x18: // As if user primary LE
833 case 0x80: // Primary
834 case 0x82: // Primary no-fault
835 case 0x88: // Primary LE
836 case 0x8a: // Primary no-fault LE
837 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
6f27aba6
BS		 838 if (env->hpstate & HS_PRIV) {
839 switch(size) {
840 case 1:
841 ret = ldub_hypv(T0);
842 break;
843 case 2:
844 ret = lduw_hypv(T0 & ~1);
845 break;
846 case 4:
847 ret = ldl_hypv(T0 & ~3);
848 break;
849 default:
850 case 8:
851 ret = ldq_hypv(T0 & ~7);
852 break;
853 }
854 } else {
855 switch(size) {
856 case 1:
857 ret = ldub_kernel(T0);
858 break;
859 case 2:
860 ret = lduw_kernel(T0 & ~1);
861 break;
862 case 4:
863 ret = ldl_kernel(T0 & ~3);
864 break;
865 default:
866 case 8:
867 ret = ldq_kernel(T0 & ~7);
868 break;
869 }
81ad8ba2
BS		 870 }
871 } else {
872 switch(size) {
873 case 1:
874 ret = ldub_user(T0);
875 break;
876 case 2:
877 ret = lduw_user(T0 & ~1);
878 break;
879 case 4:
880 ret = ldl_user(T0 & ~3);
881 break;
882 default:
883 case 8:
884 ret = ldq_user(T0 & ~7);
885 break;
886 }
887 }
888 break;
3475187d
FB		 889 case 0x14: // Bypass
890 case 0x15: // Bypass, non-cacheable
81ad8ba2
BS		 891 case 0x1c: // Bypass LE
892 case 0x1d: // Bypass, non-cacheable LE
0f8a249a 893 {
02aab46a
FB		 894 switch(size) {
895 case 1:
896 ret = ldub_phys(T0);
897 break;
898 case 2:
899 ret = lduw_phys(T0 & ~1);
900 break;
901 case 4:
902 ret = ldl_phys(T0 & ~3);
903 break;
904 default:
905 case 8:
906 ret = ldq_phys(T0 & ~7);
907 break;
908 }
0f8a249a
BS		 909 break;
910 }
83469015
FB		 911 case 0x04: // Nucleus
912 case 0x0c: // Nucleus Little Endian (LE)
83469015 913 case 0x11: // As if user secondary
83469015 914 case 0x19: // As if user secondary LE
83469015
FB		 915 case 0x24: // Nucleus quad LDD 128 bit atomic
916 case 0x2c: // Nucleus quad LDD 128 bit atomic
917 case 0x4a: // UPA config
81ad8ba2 918 case 0x81: // Secondary
83469015 919 case 0x83: // Secondary no-fault
83469015 920 case 0x89: // Secondary LE
83469015 921 case 0x8b: // Secondary no-fault LE
0f8a249a
BS		 922 // XXX
923 break;
3475187d 924 case 0x45: // LSU
0f8a249a
BS		 925 ret = env->lsu;
926 break;
3475187d 927 case 0x50: // I-MMU regs
0f8a249a
BS		 928 {
929 int reg = (T0 >> 3) & 0xf;
3475187d 930
0f8a249a
BS		 931 ret = env->immuregs[reg];
932 break;
933 }
3475187d
FB		 934 case 0x51: // I-MMU 8k TSB pointer
935 case 0x52: // I-MMU 64k TSB pointer
936 case 0x55: // I-MMU data access
0f8a249a
BS		 937 // XXX
938 break;
83469015 939 case 0x56: // I-MMU tag read
0f8a249a
BS		 940 {
941 unsigned int i;
942
943 for (i = 0; i < 64; i++) {
944 // Valid, ctx match, vaddr match
945 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
946 env->itlb_tag[i] == T0) {
947 ret = env->itlb_tag[i];
948 break;
949 }
950 }
951 break;
952 }
3475187d 953 case 0x58: // D-MMU regs
0f8a249a
BS		 954 {
955 int reg = (T0 >> 3) & 0xf;
3475187d 956
0f8a249a
BS		 957 ret = env->dmmuregs[reg];
958 break;
959 }
83469015 960 case 0x5e: // D-MMU tag read
0f8a249a
BS		 961 {
962 unsigned int i;
963
964 for (i = 0; i < 64; i++) {
965 // Valid, ctx match, vaddr match
966 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
967 env->dtlb_tag[i] == T0) {
968 ret = env->dtlb_tag[i];
969 break;
970 }
971 }
972 break;
973 }
3475187d
FB		 974 case 0x59: // D-MMU 8k TSB pointer
975 case 0x5a: // D-MMU 64k TSB pointer
976 case 0x5b: // D-MMU data pointer
977 case 0x5d: // D-MMU data access
83469015
FB		 978 case 0x48: // Interrupt dispatch, RO
979 case 0x49: // Interrupt data receive
980 case 0x7f: // Incoming interrupt vector, RO
0f8a249a
BS		 981 // XXX
982 break;
3475187d
FB		 983 case 0x54: // I-MMU data in, WO
984 case 0x57: // I-MMU demap, WO
985 case 0x5c: // D-MMU data in, WO
986 case 0x5f: // D-MMU demap, WO
83469015 987 case 0x77: // Interrupt vector, WO
3475187d 988 default:
6c36d3fa 989 do_unassigned_access(T0, 0, 0, 1);
0f8a249a
BS		 990 ret = 0;
991 break;
3475187d 992 }
81ad8ba2
BS		 993
994 /* Convert from little endian */
995 switch (asi) {
996 case 0x0c: // Nucleus Little Endian (LE)
997 case 0x18: // As if user primary LE
998 case 0x19: // As if user secondary LE
999 case 0x1c: // Bypass LE
1000 case 0x1d: // Bypass, non-cacheable LE
1001 case 0x88: // Primary LE
1002 case 0x89: // Secondary LE
1003 case 0x8a: // Primary no-fault LE
1004 case 0x8b: // Secondary no-fault LE
1005 switch(size) {
1006 case 2:
1007 ret = bswap16(ret);
e32664fb 1008 break;
81ad8ba2
BS		 1009 case 4:
1010 ret = bswap32(ret);
e32664fb 1011 break;
81ad8ba2
BS		 1012 case 8:
1013 ret = bswap64(ret);
e32664fb 1014 break;
81ad8ba2
BS		 1015 default:
1016 break;
1017 }
1018 default:
1019 break;
1020 }
1021
1022 /* Convert to signed number */
1023 if (sign) {
1024 switch(size) {
1025 case 1:
1026 ret = (int8_t) ret;
e32664fb 1027 break;
81ad8ba2
BS		 1028 case 2:
1029 ret = (int16_t) ret;
e32664fb 1030 break;
81ad8ba2
BS		 1031 case 4:
1032 ret = (int32_t) ret;
e32664fb 1033 break;
81ad8ba2
BS		 1034 default:
1035 break;
1036 }
1037 }
3475187d
FB		 1038 T1 = ret;
1039}
1040
81ad8ba2 1041void helper_st_asi(int asi, int size)
3475187d 1042{
6f27aba6 1043 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
20b749f6 1044 || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
0f8a249a 1045 raise_exception(TT_PRIV_ACT);
3475187d 1046
81ad8ba2
BS		 1047 /* Convert to little endian */
1048 switch (asi) {
1049 case 0x0c: // Nucleus Little Endian (LE)
1050 case 0x18: // As if user primary LE
1051 case 0x19: // As if user secondary LE
1052 case 0x1c: // Bypass LE
1053 case 0x1d: // Bypass, non-cacheable LE
81ad8ba2
BS		 1054 case 0x88: // Primary LE
1055 case 0x89: // Secondary LE
1056 switch(size) {
1057 case 2:
1058 T0 = bswap16(T0);
e32664fb 1059 break;
81ad8ba2
BS		 1060 case 4:
1061 T0 = bswap32(T0);
e32664fb 1062 break;
81ad8ba2
BS		 1063 case 8:
1064 T0 = bswap64(T0);
e32664fb 1065 break;
81ad8ba2
BS		 1066 default:
1067 break;
1068 }
1069 default:
1070 break;
1071 }
1072
3475187d 1073 switch(asi) {
81ad8ba2
BS		 1074 case 0x10: // As if user primary
1075 case 0x18: // As if user primary LE
1076 case 0x80: // Primary
1077 case 0x88: // Primary LE
1078 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
6f27aba6
BS		 1079 if (env->hpstate & HS_PRIV) {
1080 switch(size) {
1081 case 1:
1082 stb_hypv(T0, T1);
1083 break;
1084 case 2:
1085 stw_hypv(T0 & ~1, T1);
1086 break;
1087 case 4:
1088 stl_hypv(T0 & ~3, T1);
1089 break;
1090 case 8:
1091 default:
1092 stq_hypv(T0 & ~7, T1);
1093 break;
1094 }
1095 } else {
1096 switch(size) {
1097 case 1:
1098 stb_kernel(T0, T1);
1099 break;
1100 case 2:
1101 stw_kernel(T0 & ~1, T1);
1102 break;
1103 case 4:
1104 stl_kernel(T0 & ~3, T1);
1105 break;
1106 case 8:
1107 default:
1108 stq_kernel(T0 & ~7, T1);
1109 break;
1110 }
81ad8ba2
BS		 1111 }
1112 } else {
1113 switch(size) {
1114 case 1:
1115 stb_user(T0, T1);
1116 break;
1117 case 2:
1118 stw_user(T0 & ~1, T1);
1119 break;
1120 case 4:
1121 stl_user(T0 & ~3, T1);
1122 break;
1123 case 8:
1124 default:
1125 stq_user(T0 & ~7, T1);
1126 break;
1127 }
1128 }
1129 break;
3475187d
FB		 1130 case 0x14: // Bypass
1131 case 0x15: // Bypass, non-cacheable
81ad8ba2
BS		 1132 case 0x1c: // Bypass LE
1133 case 0x1d: // Bypass, non-cacheable LE
0f8a249a 1134 {
02aab46a
FB		 1135 switch(size) {
1136 case 1:
1137 stb_phys(T0, T1);
1138 break;
1139 case 2:
1140 stw_phys(T0 & ~1, T1);
1141 break;
1142 case 4:
1143 stl_phys(T0 & ~3, T1);
1144 break;
1145 case 8:
1146 default:
1147 stq_phys(T0 & ~7, T1);
1148 break;
1149 }
0f8a249a
BS		 1150 }
1151 return;
83469015
FB		 1152 case 0x04: // Nucleus
1153 case 0x0c: // Nucleus Little Endian (LE)
83469015 1154 case 0x11: // As if user secondary
83469015 1155 case 0x19: // As if user secondary LE
83469015
FB		 1156 case 0x24: // Nucleus quad LDD 128 bit atomic
1157 case 0x2c: // Nucleus quad LDD 128 bit atomic
1158 case 0x4a: // UPA config
51996525 1159 case 0x81: // Secondary
83469015 1160 case 0x89: // Secondary LE
0f8a249a
BS		 1161 // XXX
1162 return;
3475187d 1163 case 0x45: // LSU
0f8a249a
BS		 1164 {
1165 uint64_t oldreg;
1166
1167 oldreg = env->lsu;
1168 env->lsu = T1 & (DMMU_E | IMMU_E);
1169 // Mappings generated during D/I MMU disabled mode are
1170 // invalid in normal mode
1171 if (oldreg != env->lsu) {
952a328f 1172 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu);
83469015 1173#ifdef DEBUG_MMU
0f8a249a 1174 dump_mmu(env);
83469015 1175#endif
0f8a249a
BS		 1176 tlb_flush(env, 1);
1177 }
1178 return;
1179 }
3475187d 1180 case 0x50: // I-MMU regs
0f8a249a
BS		 1181 {
1182 int reg = (T0 >> 3) & 0xf;
1183 uint64_t oldreg;
3b46e624 1184
0f8a249a 1185 oldreg = env->immuregs[reg];
3475187d
FB		 1186 switch(reg) {
1187 case 0: // RO
1188 case 4:
1189 return;
1190 case 1: // Not in I-MMU
1191 case 2:
1192 case 7:
1193 case 8:
1194 return;
1195 case 3: // SFSR
0f8a249a
BS		 1196 if ((T1 & 1) == 0)
1197 T1 = 0; // Clear SFSR
3475187d
FB		 1198 break;
1199 case 5: // TSB access
1200 case 6: // Tag access
1201 default:
1202 break;
1203 }
0f8a249a 1204 env->immuregs[reg] = T1;
3475187d 1205 if (oldreg != env->immuregs[reg]) {
952a328f 1206 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
3475187d 1207 }
952a328f 1208#ifdef DEBUG_MMU
0f8a249a 1209 dump_mmu(env);
3475187d 1210#endif
0f8a249a
BS		 1211 return;
1212 }
3475187d 1213 case 0x54: // I-MMU data in
0f8a249a
BS		 1214 {
1215 unsigned int i;
1216
1217 // Try finding an invalid entry
1218 for (i = 0; i < 64; i++) {
1219 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
1220 env->itlb_tag[i] = env->immuregs[6];
1221 env->itlb_tte[i] = T1;
1222 return;
1223 }
1224 }
1225 // Try finding an unlocked entry
1226 for (i = 0; i < 64; i++) {
1227 if ((env->itlb_tte[i] & 0x40) == 0) {
1228 env->itlb_tag[i] = env->immuregs[6];
1229 env->itlb_tte[i] = T1;
1230 return;
1231 }
1232 }
1233 // error state?
1234 return;
1235 }
3475187d 1236 case 0x55: // I-MMU data access
0f8a249a
BS		 1237 {
1238 unsigned int i = (T0 >> 3) & 0x3f;
3475187d 1239
0f8a249a
BS		 1240 env->itlb_tag[i] = env->immuregs[6];
1241 env->itlb_tte[i] = T1;
1242 return;
1243 }
3475187d 1244 case 0x57: // I-MMU demap
0f8a249a
BS		 1245 // XXX
1246 return;
3475187d 1247 case 0x58: // D-MMU regs
0f8a249a
BS		 1248 {
1249 int reg = (T0 >> 3) & 0xf;
1250 uint64_t oldreg;
3b46e624 1251
0f8a249a 1252 oldreg = env->dmmuregs[reg];
3475187d
FB		 1253 switch(reg) {
1254 case 0: // RO
1255 case 4:
1256 return;
1257 case 3: // SFSR
0f8a249a
BS		 1258 if ((T1 & 1) == 0) {
1259 T1 = 0; // Clear SFSR, Fault address
1260 env->dmmuregs[4] = 0;
1261 }
1262 env->dmmuregs[reg] = T1;
3475187d
FB		 1263 break;
1264 case 1: // Primary context
1265 case 2: // Secondary context
1266 case 5: // TSB access
1267 case 6: // Tag access
1268 case 7: // Virtual Watchpoint
1269 case 8: // Physical Watchpoint
1270 default:
1271 break;
1272 }
0f8a249a 1273 env->dmmuregs[reg] = T1;
3475187d 1274 if (oldreg != env->dmmuregs[reg]) {
952a328f 1275 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
3475187d 1276 }
952a328f 1277#ifdef DEBUG_MMU
0f8a249a 1278 dump_mmu(env);
3475187d 1279#endif
0f8a249a
BS		 1280 return;
1281 }
3475187d 1282 case 0x5c: // D-MMU data in
0f8a249a
BS		 1283 {
1284 unsigned int i;
1285
1286 // Try finding an invalid entry
1287 for (i = 0; i < 64; i++) {
1288 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
1289 env->dtlb_tag[i] = env->dmmuregs[6];
1290 env->dtlb_tte[i] = T1;
1291 return;
1292 }
1293 }
1294 // Try finding an unlocked entry
1295 for (i = 0; i < 64; i++) {
1296 if ((env->dtlb_tte[i] & 0x40) == 0) {
1297 env->dtlb_tag[i] = env->dmmuregs[6];
1298 env->dtlb_tte[i] = T1;
1299 return;
1300 }
1301 }
1302 // error state?
1303 return;
1304 }
3475187d 1305 case 0x5d: // D-MMU data access
0f8a249a
BS		 1306 {
1307 unsigned int i = (T0 >> 3) & 0x3f;
3475187d 1308
0f8a249a
BS		 1309 env->dtlb_tag[i] = env->dmmuregs[6];
1310 env->dtlb_tte[i] = T1;
1311 return;
1312 }
3475187d 1313 case 0x5f: // D-MMU demap
83469015 1314 case 0x49: // Interrupt data receive
0f8a249a
BS		 1315 // XXX
1316 return;
3475187d
FB		 1317 case 0x51: // I-MMU 8k TSB pointer, RO
1318 case 0x52: // I-MMU 64k TSB pointer, RO
1319 case 0x56: // I-MMU tag read, RO
1320 case 0x59: // D-MMU 8k TSB pointer, RO
1321 case 0x5a: // D-MMU 64k TSB pointer, RO
1322 case 0x5b: // D-MMU data pointer, RO
1323 case 0x5e: // D-MMU tag read, RO
83469015
FB		 1324 case 0x48: // Interrupt dispatch, RO
1325 case 0x7f: // Incoming interrupt vector, RO
1326 case 0x82: // Primary no-fault, RO
1327 case 0x83: // Secondary no-fault, RO
1328 case 0x8a: // Primary no-fault LE, RO
1329 case 0x8b: // Secondary no-fault LE, RO
3475187d 1330 default:
6c36d3fa 1331 do_unassigned_access(T0, 1, 0, 1);
0f8a249a 1332 return;
3475187d
FB		 1333 }
1334}
81ad8ba2 1335#endif /* CONFIG_USER_ONLY */
3391c818
BS		 1336
1337void helper_ldf_asi(int asi, int size, int rd)
1338{
1339 target_ulong tmp_T0 = T0, tmp_T1 = T1;
1340 unsigned int i;
1341
1342 switch (asi) {
1343 case 0xf0: // Block load primary
1344 case 0xf1: // Block load secondary
1345 case 0xf8: // Block load primary LE
1346 case 0xf9: // Block load secondary LE
51996525
BS		 1347 if (rd & 7) {
1348 raise_exception(TT_ILL_INSN);
1349 return;
1350 }
1351 if (T0 & 0x3f) {
1352 raise_exception(TT_UNALIGNED);
1353 return;
1354 }
1355 for (i = 0; i < 16; i++) {
1356 helper_ld_asi(asi & 0x8f, 4, 0);
1357 *(uint32_t *)&env->fpr[rd++] = T1;
1358 T0 += 4;
3391c818
BS		 1359 }
1360 T0 = tmp_T0;
1361 T1 = tmp_T1;
1362
1363 return;
1364 default:
1365 break;
1366 }
1367
1368 helper_ld_asi(asi, size, 0);
1369 switch(size) {
1370 default:
1371 case 4:
1372 *((uint32_t *)&FT0) = T1;
1373 break;
1374 case 8:
1375 *((int64_t *)&DT0) = T1;
1376 break;
1377 }
1378 T1 = tmp_T1;
1379}
1380
1381void helper_stf_asi(int asi, int size, int rd)
1382{
1383 target_ulong tmp_T0 = T0, tmp_T1 = T1;
1384 unsigned int i;
1385
1386 switch (asi) {
1387 case 0xf0: // Block store primary
1388 case 0xf1: // Block store secondary
1389 case 0xf8: // Block store primary LE
1390 case 0xf9: // Block store secondary LE
51996525
BS		 1391 if (rd & 7) {
1392 raise_exception(TT_ILL_INSN);
1393 return;
1394 }
1395 if (T0 & 0x3f) {
1396 raise_exception(TT_UNALIGNED);
1397 return;
1398 }
1399 for (i = 0; i < 16; i++) {
1400 T1 = *(uint32_t *)&env->fpr[rd++];
1401 helper_st_asi(asi & 0x8f, 4);
1402 T0 += 4;
3391c818
BS		 1403 }
1404 T0 = tmp_T0;
1405 T1 = tmp_T1;
1406
1407 return;
1408 default:
1409 break;
1410 }
1411
1412 switch(size) {
1413 default:
1414 case 4:
1415 T1 = *((uint32_t *)&FT0);
1416 break;
1417 case 8:
1418 T1 = *((int64_t *)&DT0);
1419 break;
1420 }
1421 helper_st_asi(asi, size);
1422 T1 = tmp_T1;
1423}
1424
81ad8ba2 1425#endif /* TARGET_SPARC64 */
3475187d
FB		 1426
1427#ifndef TARGET_SPARC64
a0c4cb4a 1428void helper_rett()
e8af50a3 1429{
af7bf89b
FB		 1430 unsigned int cwp;
1431
d4218d99
BS		 1432 if (env->psret == 1)
1433 raise_exception(TT_ILL_INSN);
1434
e8af50a3 1435 env->psret = 1;
5fafdf24 1436 cwp = (env->cwp + 1) & (NWINDOWS - 1);
e8af50a3
FB		 1437 if (env->wim & (1 << cwp)) {
1438 raise_exception(TT_WIN_UNF);
1439 }
1440 set_cwp(cwp);
1441 env->psrs = env->psrps;
1442}
3475187d 1443#endif
e8af50a3 1444
8d5f07fa 1445void helper_ldfsr(void)
e8af50a3 1446{
7a0e1f41 1447 int rnd_mode;
e8af50a3
FB		 1448 switch (env->fsr & FSR_RD_MASK) {
1449 case FSR_RD_NEAREST:
7a0e1f41 1450 rnd_mode = float_round_nearest_even;
0f8a249a 1451 break;
ed910241 1452 default:
e8af50a3 1453 case FSR_RD_ZERO:
7a0e1f41 1454 rnd_mode = float_round_to_zero;
0f8a249a 1455 break;
e8af50a3 1456 case FSR_RD_POS:
7a0e1f41 1457 rnd_mode = float_round_up;
0f8a249a 1458 break;
e8af50a3 1459 case FSR_RD_NEG:
7a0e1f41 1460 rnd_mode = float_round_down;
0f8a249a 1461 break;
e8af50a3 1462 }
7a0e1f41 1463 set_float_rounding_mode(rnd_mode, &env->fp_status);
e8af50a3 1464}
e80cfcfc 1465
e80cfcfc
FB		 1466void helper_debug()
1467{
1468 env->exception_index = EXCP_DEBUG;
1469 cpu_loop_exit();
1470}
af7bf89b 1471
3475187d 1472#ifndef TARGET_SPARC64
af7bf89b
FB		 1473void do_wrpsr()
1474{
d4218d99
BS		 1475 if ((T0 & PSR_CWP) >= NWINDOWS)
1476 raise_exception(TT_ILL_INSN);
1477 else
1478 PUT_PSR(env, T0);
af7bf89b
FB		 1479}
1480
1481void do_rdpsr()
1482{
1483 T0 = GET_PSR(env);
1484}
3475187d
FB		 1485
1486#else
1487
1488void do_popc()
1489{
eed152bb 1490 T0 = ctpop64(T1);
3475187d 1491}
83469015
FB		 1492
1493static inline uint64_t *get_gregset(uint64_t pstate)
1494{
1495 switch (pstate) {
1496 default:
1497 case 0:
0f8a249a 1498 return env->bgregs;
83469015 1499 case PS_AG:
0f8a249a 1500 return env->agregs;
83469015 1501 case PS_MG:
0f8a249a 1502 return env->mgregs;
83469015 1503 case PS_IG:
0f8a249a 1504 return env->igregs;
83469015
FB		 1505 }
1506}
1507
8f1f22f6 1508static inline void change_pstate(uint64_t new_pstate)
83469015 1509{
8f1f22f6 1510 uint64_t pstate_regs, new_pstate_regs;
83469015
FB		 1511 uint64_t *src, *dst;
1512
83469015
FB		 1513 pstate_regs = env->pstate & 0xc01;
1514 new_pstate_regs = new_pstate & 0xc01;
1515 if (new_pstate_regs != pstate_regs) {
0f8a249a
BS		 1516 // Switch global register bank
1517 src = get_gregset(new_pstate_regs);
1518 dst = get_gregset(pstate_regs);
1519 memcpy32(dst, env->gregs);
1520 memcpy32(env->gregs, src);
83469015
FB		 1521 }
1522 env->pstate = new_pstate;
1523}
1524
8f1f22f6
BS		 1525void do_wrpstate(void)
1526{
1527 change_pstate(T0 & 0xf3f);
1528}
1529
83469015
FB		 1530void do_done(void)
1531{
1532 env->tl--;
1533 env->pc = env->tnpc[env->tl];
1534 env->npc = env->tnpc[env->tl] + 4;
1535 PUT_CCR(env, env->tstate[env->tl] >> 32);
1536 env->asi = (env->tstate[env->tl] >> 24) & 0xff;
8f1f22f6 1537 change_pstate((env->tstate[env->tl] >> 8) & 0xf3f);
17d996e1 1538 PUT_CWP64(env, env->tstate[env->tl] & 0xff);
83469015
FB		 1539}
1540
1541void do_retry(void)
1542{
1543 env->tl--;
1544 env->pc = env->tpc[env->tl];
1545 env->npc = env->tnpc[env->tl];
1546 PUT_CCR(env, env->tstate[env->tl] >> 32);
1547 env->asi = (env->tstate[env->tl] >> 24) & 0xff;
8f1f22f6 1548 change_pstate((env->tstate[env->tl] >> 8) & 0xf3f);
17d996e1 1549 PUT_CWP64(env, env->tstate[env->tl] & 0xff);
83469015 1550}
3475187d 1551#endif
ee5bbe38
FB		 1552
1553void set_cwp(int new_cwp)
1554{
1555 /* put the modified wrap registers at their proper location */
1556 if (env->cwp == (NWINDOWS - 1))
1557 memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
1558 env->cwp = new_cwp;
1559 /* put the wrap registers at their temporary location */
1560 if (new_cwp == (NWINDOWS - 1))
1561 memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
1562 env->regwptr = env->regbase + (new_cwp * 16);
1563 REGWPTR = env->regwptr;
1564}
1565
1566void cpu_set_cwp(CPUState *env1, int new_cwp)
1567{
1568 CPUState *saved_env;
1569#ifdef reg_REGWPTR
1570 target_ulong *saved_regwptr;
1571#endif
1572
1573 saved_env = env;
1574#ifdef reg_REGWPTR
1575 saved_regwptr = REGWPTR;
1576#endif
1577 env = env1;
1578 set_cwp(new_cwp);
1579 env = saved_env;
1580#ifdef reg_REGWPTR
1581 REGWPTR = saved_regwptr;
1582#endif
1583}
1584
1585#ifdef TARGET_SPARC64
1586void do_interrupt(int intno)
1587{
1588#ifdef DEBUG_PCALL
1589 if (loglevel & CPU_LOG_INT) {
0f8a249a
BS		 1590 static int count;
1591 fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n",
ee5bbe38
FB		 1592 count, intno,
1593 env->pc,
1594 env->npc, env->regwptr[6]);
0f8a249a 1595 cpu_dump_state(env, logfile, fprintf, 0);
ee5bbe38 1596#if 0
0f8a249a
BS		 1597 {
1598 int i;
1599 uint8_t *ptr;
1600
1601 fprintf(logfile, " code=");
1602 ptr = (uint8_t *)env->pc;
1603 for(i = 0; i < 16; i++) {
1604 fprintf(logfile, " %02x", ldub(ptr + i));
1605 }
1606 fprintf(logfile, "\n");
1607 }
ee5bbe38 1608#endif
0f8a249a 1609 count++;
ee5bbe38
FB		 1610 }
1611#endif
5fafdf24 1612#if !defined(CONFIG_USER_ONLY)
83469015 1613 if (env->tl == MAXTL) {
c68ea704 1614 cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
0f8a249a 1615 return;
ee5bbe38
FB		 1616 }
1617#endif
1618 env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) |
0f8a249a 1619 ((env->pstate & 0xf3f) << 8) | GET_CWP64(env);
ee5bbe38
FB		 1620 env->tpc[env->tl] = env->pc;
1621 env->tnpc[env->tl] = env->npc;
1622 env->tt[env->tl] = intno;
8f1f22f6
BS		 1623 change_pstate(PS_PEF | PS_PRIV | PS_AG);
1624
1625 if (intno == TT_CLRWIN)
1626 set_cwp((env->cwp - 1) & (NWINDOWS - 1));
1627 else if ((intno & 0x1c0) == TT_SPILL)
1628 set_cwp((env->cwp - env->cansave - 2) & (NWINDOWS - 1));
1629 else if ((intno & 0x1c0) == TT_FILL)
1630 set_cwp((env->cwp + 1) & (NWINDOWS - 1));
83469015
FB		 1631 env->tbr &= ~0x7fffULL;
1632 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
1633 if (env->tl < MAXTL - 1) {
0f8a249a 1634 env->tl++;
83469015 1635 } else {
0f8a249a
BS		 1636 env->pstate |= PS_RED;
1637 if (env->tl != MAXTL)
1638 env->tl++;
83469015 1639 }
ee5bbe38
FB		 1640 env->pc = env->tbr;
1641 env->npc = env->pc + 4;
1642 env->exception_index = 0;
1643}
1644#else
1645void do_interrupt(int intno)
1646{
1647 int cwp;
1648
1649#ifdef DEBUG_PCALL
1650 if (loglevel & CPU_LOG_INT) {
0f8a249a
BS		 1651 static int count;
1652 fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
ee5bbe38
FB		 1653 count, intno,
1654 env->pc,
1655 env->npc, env->regwptr[6]);
0f8a249a 1656 cpu_dump_state(env, logfile, fprintf, 0);
ee5bbe38 1657#if 0
0f8a249a
BS		 1658 {
1659 int i;
1660 uint8_t *ptr;
1661
1662 fprintf(logfile, " code=");
1663 ptr = (uint8_t *)env->pc;
1664 for(i = 0; i < 16; i++) {
1665 fprintf(logfile, " %02x", ldub(ptr + i));
1666 }
1667 fprintf(logfile, "\n");
1668 }
ee5bbe38 1669#endif
0f8a249a 1670 count++;
ee5bbe38
FB		 1671 }
1672#endif
5fafdf24 1673#if !defined(CONFIG_USER_ONLY)
ee5bbe38 1674 if (env->psret == 0) {
c68ea704 1675 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
0f8a249a 1676 return;
ee5bbe38
FB		 1677 }
1678#endif
1679 env->psret = 0;
5fafdf24 1680 cwp = (env->cwp - 1) & (NWINDOWS - 1);
ee5bbe38
FB		 1681 set_cwp(cwp);
1682 env->regwptr[9] = env->pc;
1683 env->regwptr[10] = env->npc;
1684 env->psrps = env->psrs;
1685 env->psrs = 1;
1686 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
1687 env->pc = env->tbr;
1688 env->npc = env->pc + 4;
1689 env->exception_index = 0;
1690}
1691#endif
1692
5fafdf24 1693#if !defined(CONFIG_USER_ONLY)
ee5bbe38 1694
d2889a3e
BS		 1695static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
1696 void *retaddr);
1697
ee5bbe38 1698#define MMUSUFFIX _mmu
d2889a3e 1699#define ALIGNED_ONLY
273af660
TS		 1700#ifdef __s390__
1701# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
1702#else
1703# define GETPC() (__builtin_return_address(0))
1704#endif
ee5bbe38
FB		 1705
1706#define SHIFT 0
1707#include "softmmu_template.h"
1708
1709#define SHIFT 1
1710#include "softmmu_template.h"
1711
1712#define SHIFT 2
1713#include "softmmu_template.h"
1714
1715#define SHIFT 3
1716#include "softmmu_template.h"
1717
d2889a3e
BS		 1718static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
1719 void *retaddr)
1720{
94554550
BS		 1721#ifdef DEBUG_UNALIGNED
1722 printf("Unaligned access to 0x%x from 0x%x\n", addr, env->pc);
1723#endif
1724 raise_exception(TT_UNALIGNED);
d2889a3e 1725}
ee5bbe38
FB		 1726
1727/* try to fill the TLB and return an exception if error. If retaddr is
1728 NULL, it means that the function was called in C code (i.e. not
1729 from generated code or from helper.c) */
1730/* XXX: fix it to restore all registers */
6ebbf390 1731void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
ee5bbe38
FB		 1732{
1733 TranslationBlock *tb;
1734 int ret;
1735 unsigned long pc;
1736 CPUState *saved_env;
1737
1738 /* XXX: hack to restore env in all cases, even if not called from
1739 generated code */
1740 saved_env = env;
1741 env = cpu_single_env;
1742
6ebbf390 1743 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ee5bbe38
FB		 1744 if (ret) {
1745 if (retaddr) {
1746 /* now we have a real cpu fault */
1747 pc = (unsigned long)retaddr;
1748 tb = tb_find_pc(pc);
1749 if (tb) {
1750 /* the PC is inside the translated code. It means that we have
1751 a virtual CPU fault */
1752 cpu_restore_state(tb, env, pc, (void *)T2);
1753 }
1754 }
1755 cpu_loop_exit();
1756 }
1757 env = saved_env;
1758}
1759
1760#endif
6c36d3fa
BS		 1761
1762#ifndef TARGET_SPARC64
5dcb6b91 1763void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
6c36d3fa
BS		 1764 int is_asi)
1765{
1766 CPUState *saved_env;
1767
1768 /* XXX: hack to restore env in all cases, even if not called from
1769 generated code */
1770 saved_env = env;
1771 env = cpu_single_env;
1772 if (env->mmuregs[3]) /* Fault status register */
0f8a249a 1773 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
6c36d3fa
BS		 1774 if (is_asi)
1775 env->mmuregs[3] |= 1 << 16;
1776 if (env->psrs)
1777 env->mmuregs[3] |= 1 << 5;
1778 if (is_exec)
1779 env->mmuregs[3] |= 1 << 6;
1780 if (is_write)
1781 env->mmuregs[3] |= 1 << 7;
1782 env->mmuregs[3] |= (5 << 2) | 2;
1783 env->mmuregs[4] = addr; /* Fault address register */
1784 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
1785#ifdef DEBUG_UNASSIGNED
5dcb6b91 1786 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
6c36d3fa
BS		 1787 "\n", addr, env->pc);
1788#endif
1b2e93c1
BS		 1789 if (is_exec)
1790 raise_exception(TT_CODE_ACCESS);
1791 else
1792 raise_exception(TT_DATA_ACCESS);
6c36d3fa
BS		 1793 }
1794 env = saved_env;
1795}
1796#else
5dcb6b91 1797void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
6c36d3fa
BS		 1798 int is_asi)
1799{
1800#ifdef DEBUG_UNASSIGNED
1801 CPUState *saved_env;
1802
1803 /* XXX: hack to restore env in all cases, even if not called from
1804 generated code */
1805 saved_env = env;
1806 env = cpu_single_env;
5dcb6b91 1807 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n",
6c36d3fa
BS		 1808 addr, env->pc);
1809 env = saved_env;
1810#endif
1b2e93c1
BS		 1811 if (is_exec)
1812 raise_exception(TT_CODE_ACCESS);
1813 else
1814 raise_exception(TT_DATA_ACCESS);
6c36d3fa
BS		 1815}
1816#endif
20c9f095 1817
Qemu copy for testing