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Commit | Line | Data |
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e8af50a3 FB |
1 | #include <math.h> |
2 | #include <fenv.h> | |
3 | #include "exec.h" | |
4 | ||
5 | void OPPROTO do_fabss(void) | |
6 | { | |
7 | FT0 = fabsf(FT1); | |
8 | } | |
9 | ||
10 | void OPPROTO do_fsqrts(void) | |
11 | { | |
12 | FT0 = sqrtf(FT1); | |
13 | } | |
14 | ||
15 | void OPPROTO do_fsqrtd(void) | |
16 | { | |
17 | DT0 = sqrt(DT1); | |
18 | } | |
19 | ||
20 | void OPPROTO do_fcmps (void) | |
21 | { | |
22 | if (isnan(FT0) || isnan(FT1)) { | |
23 | T0 = FSR_FCC1 | FSR_FCC0; | |
24 | } else if (FT0 < FT1) { | |
25 | T0 = FSR_FCC0; | |
26 | } else if (FT0 > FT1) { | |
27 | T0 = FSR_FCC1; | |
28 | } else { | |
29 | T0 = 0; | |
30 | } | |
31 | env->fsr = T0; | |
32 | } | |
33 | ||
34 | void OPPROTO do_fcmpd (void) | |
35 | { | |
36 | if (isnan(DT0) || isnan(DT1)) { | |
37 | T0 = FSR_FCC1 | FSR_FCC0; | |
38 | } else if (DT0 < DT1) { | |
39 | T0 = FSR_FCC0; | |
40 | } else if (DT0 > DT1) { | |
41 | T0 = FSR_FCC1; | |
42 | } else { | |
43 | T0 = 0; | |
44 | } | |
45 | env->fsr = T0; | |
46 | } | |
47 | ||
48 | void OPPROTO helper_ld_asi(int asi, int size, int sign) | |
49 | { | |
50 | switch(asi) { | |
51 | case 3: /* MMU probe */ | |
52 | T1 = 0; | |
53 | return; | |
54 | case 4: /* read MMU regs */ | |
55 | { | |
56 | int temp, reg = (T0 >> 8) & 0xf; | |
57 | ||
58 | temp = env->mmuregs[reg]; | |
59 | if (reg == 3 || reg == 4) /* Fault status, addr cleared on read*/ | |
60 | env->mmuregs[reg] = 0; | |
61 | T1 = temp; | |
62 | } | |
63 | return; | |
64 | case 0x20 ... 0x2f: /* MMU passthrough */ | |
65 | { | |
66 | int temp; | |
67 | ||
68 | cpu_physical_memory_read(T0, (void *) &temp, size); | |
69 | bswap32s(&temp); | |
70 | T1 = temp; | |
71 | } | |
72 | return; | |
73 | default: | |
74 | T1 = 0; | |
75 | return; | |
76 | } | |
77 | } | |
78 | ||
79 | void OPPROTO helper_st_asi(int asi, int size, int sign) | |
80 | { | |
81 | switch(asi) { | |
82 | case 3: /* MMU flush */ | |
83 | return; | |
84 | case 4: /* write MMU regs */ | |
85 | { | |
86 | int reg = (T0 >> 8) & 0xf; | |
87 | if (reg == 0) { | |
88 | env->mmuregs[reg] &= ~(MMU_E | MMU_NF); | |
89 | env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF); | |
90 | } else | |
91 | env->mmuregs[reg] = T1; | |
92 | return; | |
93 | } | |
94 | case 0x20 ... 0x2f: /* MMU passthrough */ | |
95 | { | |
96 | int temp = T1; | |
97 | ||
98 | bswap32s(&temp); | |
99 | cpu_physical_memory_write(T0, (void *) &temp, size); | |
100 | } | |
101 | return; | |
102 | default: | |
103 | return; | |
104 | } | |
105 | } | |
106 | ||
8d5f07fa FB |
107 | #if 0 |
108 | void do_ldd_raw(uint32_t addr) | |
109 | { | |
110 | T1 = ldl_raw((void *) addr); | |
111 | T0 = ldl_raw((void *) (addr + 4)); | |
112 | } | |
113 | ||
114 | #if !defined(CONFIG_USER_ONLY) | |
115 | void do_ldd_user(uint32_t addr) | |
116 | { | |
117 | T1 = ldl_user((void *) addr); | |
118 | T0 = ldl_user((void *) (addr + 4)); | |
119 | } | |
120 | void do_ldd_kernel(uint32_t addr) | |
121 | { | |
122 | T1 = ldl_kernel((void *) addr); | |
123 | T0 = ldl_kernel((void *) (addr + 4)); | |
124 | } | |
125 | #endif | |
126 | #endif | |
127 | ||
e8af50a3 FB |
128 | void OPPROTO helper_rett() |
129 | { | |
130 | int cwp; | |
131 | env->psret = 1; | |
132 | cwp = (env->cwp + 1) & (NWINDOWS - 1); | |
133 | if (env->wim & (1 << cwp)) { | |
134 | raise_exception(TT_WIN_UNF); | |
135 | } | |
136 | set_cwp(cwp); | |
137 | env->psrs = env->psrps; | |
138 | } | |
139 | ||
8d5f07fa | 140 | void helper_ldfsr(void) |
e8af50a3 FB |
141 | { |
142 | switch (env->fsr & FSR_RD_MASK) { | |
143 | case FSR_RD_NEAREST: | |
144 | fesetround(FE_TONEAREST); | |
145 | break; | |
146 | case FSR_RD_ZERO: | |
147 | fesetround(FE_TOWARDZERO); | |
148 | break; | |
149 | case FSR_RD_POS: | |
150 | fesetround(FE_UPWARD); | |
151 | break; | |
152 | case FSR_RD_NEG: | |
153 | fesetround(FE_DOWNWARD); | |
154 | break; | |
155 | } | |
156 | } |