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SH4 serial controler improvements
[qemu.git] / target-sparc / op_helper.c
CommitLineData
e8af50a3 1#include "exec.h"
eed152bb 2#include "host-utils.h"
1a2fb1c0 3#include "helper.h"
e8af50a3 4
83469015 5//#define DEBUG_PCALL
e80cfcfc 6//#define DEBUG_MMU
952a328f 7//#define DEBUG_MXCC
94554550 8//#define DEBUG_UNALIGNED
6c36d3fa 9//#define DEBUG_UNASSIGNED
8543e2cf 10//#define DEBUG_ASI
e80cfcfc 11
952a328f
BS		 12#ifdef DEBUG_MMU
13#define DPRINTF_MMU(fmt, args...) \
14do { printf("MMU: " fmt , ##args); } while (0)
15#else
16#define DPRINTF_MMU(fmt, args...)
17#endif
18
19#ifdef DEBUG_MXCC
20#define DPRINTF_MXCC(fmt, args...) \
21do { printf("MXCC: " fmt , ##args); } while (0)
22#else
23#define DPRINTF_MXCC(fmt, args...)
24#endif
25
8543e2cf
BS		 26#ifdef DEBUG_ASI
27#define DPRINTF_ASI(fmt, args...) \
28do { printf("ASI: " fmt , ##args); } while (0)
29#else
30#define DPRINTF_ASI(fmt, args...)
31#endif
32
9d893301
FB		 33void raise_exception(int tt)
34{
35 env->exception_index = tt;
36 cpu_loop_exit();
3b46e624 37}
9d893301 38
1a2fb1c0 39void helper_trap(target_ulong nb_trap)
417454b0 40{
1a2fb1c0
BS		 41 env->exception_index = TT_TRAP + (nb_trap & 0x7f);
42 cpu_loop_exit();
43}
44
45void helper_trapcc(target_ulong nb_trap, target_ulong do_trap)
46{
47 if (do_trap) {
48 env->exception_index = TT_TRAP + (nb_trap & 0x7f);
49 cpu_loop_exit();
50 }
51}
52
2b29924f
BS		 53void helper_check_align(target_ulong addr, uint32_t align)
54{
55 if (addr & align)
56 raise_exception(TT_UNALIGNED);
57}
58
44e7757c
BS		 59#define F_HELPER(name, p) void helper_f##name##p(void)
60
4e14008f 61#if defined(CONFIG_USER_ONLY)
44e7757c
BS		 62#define F_BINOP(name) \
63 F_HELPER(name, s) \
64 { \
65 FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \
66 } \
67 F_HELPER(name, d) \
68 { \
69 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
4e14008f
BS		 70 } \
71 F_HELPER(name, q) \
72 { \
73 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
44e7757c 74 }
4e14008f
BS		 75#else
76#define F_BINOP(name) \
77 F_HELPER(name, s) \
78 { \
79 FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \
80 } \
81 F_HELPER(name, d) \
82 { \
83 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
84 }
85#endif
44e7757c
BS		 86
87F_BINOP(add);
88F_BINOP(sub);
89F_BINOP(mul);
90F_BINOP(div);
91#undef F_BINOP
92
93void helper_fsmuld(void)
1a2fb1c0 94{
44e7757c
BS		 95 DT0 = float64_mul(float32_to_float64(FT0, &env->fp_status),
96 float32_to_float64(FT1, &env->fp_status),
97 &env->fp_status);
98}
1a2fb1c0 99
4e14008f
BS		 100#if defined(CONFIG_USER_ONLY)
101void helper_fdmulq(void)
102{
103 QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
104 float64_to_float128(DT1, &env->fp_status),
105 &env->fp_status);
106}
107#endif
108
44e7757c
BS		 109F_HELPER(neg, s)
110{
111 FT0 = float32_chs(FT1);
417454b0
BS		 112}
113
44e7757c
BS		 114#ifdef TARGET_SPARC64
115F_HELPER(neg, d)
7e8c2b6c 116{
44e7757c 117 DT0 = float64_chs(DT1);
7e8c2b6c 118}
4e14008f
BS		 119
120#if defined(CONFIG_USER_ONLY)
121F_HELPER(neg, q)
122{
123 QT0 = float128_chs(QT1);
124}
125#endif
44e7757c
BS		 126#endif
127
128/* Integer to float conversion. */
129F_HELPER(ito, s)
a0c4cb4a 130{
ec230928 131 FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
a0c4cb4a
FB		 132}
133
44e7757c 134F_HELPER(ito, d)
a0c4cb4a 135{
ec230928 136 DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
a0c4cb4a 137}
9c2b428e 138
4e14008f
BS		 139#if defined(CONFIG_USER_ONLY)
140F_HELPER(ito, q)
141{
142 QT0 = int32_to_float128(*((int32_t *)&FT1), &env->fp_status);
143}
144#endif
145
1e64e78d 146#ifdef TARGET_SPARC64
44e7757c 147F_HELPER(xto, s)
1e64e78d 148{
1e64e78d 149 FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
1e64e78d
BS		 150}
151
44e7757c 152F_HELPER(xto, d)
1e64e78d 153{
1e64e78d 154 DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
1e64e78d 155}
4e14008f
BS		 156#if defined(CONFIG_USER_ONLY)
157F_HELPER(xto, q)
158{
159 QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
160}
161#endif
44e7757c
BS		 162#endif
163#undef F_HELPER
164
165/* floating point conversion */
166void helper_fdtos(void)
167{
168 FT0 = float64_to_float32(DT1, &env->fp_status);
169}
170
171void helper_fstod(void)
172{
173 DT0 = float32_to_float64(FT1, &env->fp_status);
174}
9c2b428e 175
4e14008f
BS		 176#if defined(CONFIG_USER_ONLY)
177void helper_fqtos(void)
178{
179 FT0 = float128_to_float32(QT1, &env->fp_status);
180}
181
182void helper_fstoq(void)
183{
184 QT0 = float32_to_float128(FT1, &env->fp_status);
185}
186
187void helper_fqtod(void)
188{
189 DT0 = float128_to_float64(QT1, &env->fp_status);
190}
191
192void helper_fdtoq(void)
193{
194 QT0 = float64_to_float128(DT1, &env->fp_status);
195}
196#endif
197
44e7757c
BS		 198/* Float to integer conversion. */
199void helper_fstoi(void)
200{
201 *((int32_t *)&FT0) = float32_to_int32_round_to_zero(FT1, &env->fp_status);
202}
203
204void helper_fdtoi(void)
205{
206 *((int32_t *)&FT0) = float64_to_int32_round_to_zero(DT1, &env->fp_status);
207}
208
4e14008f
BS		 209#if defined(CONFIG_USER_ONLY)
210void helper_fqtoi(void)
211{
212 *((int32_t *)&FT0) = float128_to_int32_round_to_zero(QT1, &env->fp_status);
213}
214#endif
215
44e7757c
BS		 216#ifdef TARGET_SPARC64
217void helper_fstox(void)
218{
219 *((int64_t *)&DT0) = float32_to_int64_round_to_zero(FT1, &env->fp_status);
220}
221
222void helper_fdtox(void)
223{
224 *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
225}
226
4e14008f
BS		 227#if defined(CONFIG_USER_ONLY)
228void helper_fqtox(void)
229{
230 *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);
231}
232#endif
233
44e7757c
BS		 234void helper_faligndata(void)
235{
236 uint64_t tmp;
237
238 tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
239 tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
240 *((uint64_t *)&DT0) = tmp;
241}
242
243void helper_movl_FT0_0(void)
244{
245 *((uint32_t *)&FT0) = 0;
246}
247
248void helper_movl_DT0_0(void)
249{
250 *((uint64_t *)&DT0) = 0;
251}
252
253void helper_movl_FT0_1(void)
254{
255 *((uint32_t *)&FT0) = 0xffffffff;
256}
257
258void helper_movl_DT0_1(void)
259{
260 *((uint64_t *)&DT0) = 0xffffffffffffffffULL;
261}
262
263void helper_fnot(void)
264{
265 *(uint64_t *)&DT0 = ~*(uint64_t *)&DT1;
266}
267
268void helper_fnots(void)
269{
270 *(uint32_t *)&FT0 = ~*(uint32_t *)&FT1;
271}
272
273void helper_fnor(void)
274{
275 *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 | *(uint64_t *)&DT1);
276}
277
278void helper_fnors(void)
279{
280 *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 | *(uint32_t *)&FT1);
281}
282
283void helper_for(void)
284{
285 *(uint64_t *)&DT0 |= *(uint64_t *)&DT1;
286}
287
288void helper_fors(void)
289{
290 *(uint32_t *)&FT0 |= *(uint32_t *)&FT1;
291}
292
293void helper_fxor(void)
294{
295 *(uint64_t *)&DT0 ^= *(uint64_t *)&DT1;
296}
297
298void helper_fxors(void)
299{
300 *(uint32_t *)&FT0 ^= *(uint32_t *)&FT1;
301}
302
303void helper_fand(void)
304{
305 *(uint64_t *)&DT0 &= *(uint64_t *)&DT1;
306}
307
308void helper_fands(void)
309{
310 *(uint32_t *)&FT0 &= *(uint32_t *)&FT1;
311}
312
313void helper_fornot(void)
314{
315 *(uint64_t *)&DT0 = *(uint64_t *)&DT0 | ~*(uint64_t *)&DT1;
316}
317
318void helper_fornots(void)
319{
320 *(uint32_t *)&FT0 = *(uint32_t *)&FT0 | ~*(uint32_t *)&FT1;
321}
322
323void helper_fandnot(void)
324{
325 *(uint64_t *)&DT0 = *(uint64_t *)&DT0 & ~*(uint64_t *)&DT1;
326}
327
328void helper_fandnots(void)
329{
330 *(uint32_t *)&FT0 = *(uint32_t *)&FT0 & ~*(uint32_t *)&FT1;
331}
332
333void helper_fnand(void)
334{
335 *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 & *(uint64_t *)&DT1);
336}
337
338void helper_fnands(void)
339{
340 *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 & *(uint32_t *)&FT1);
341}
342
343void helper_fxnor(void)
344{
345 *(uint64_t *)&DT0 ^= ~*(uint64_t *)&DT1;
346}
347
348void helper_fxnors(void)
349{
350 *(uint32_t *)&FT0 ^= ~*(uint32_t *)&FT1;
351}
352
353#ifdef WORDS_BIGENDIAN
354#define VIS_B64(n) b[7 - (n)]
355#define VIS_W64(n) w[3 - (n)]
356#define VIS_SW64(n) sw[3 - (n)]
357#define VIS_L64(n) l[1 - (n)]
358#define VIS_B32(n) b[3 - (n)]
359#define VIS_W32(n) w[1 - (n)]
360#else
361#define VIS_B64(n) b[n]
362#define VIS_W64(n) w[n]
363#define VIS_SW64(n) sw[n]
364#define VIS_L64(n) l[n]
365#define VIS_B32(n) b[n]
366#define VIS_W32(n) w[n]
367#endif
368
369typedef union {
370 uint8_t b[8];
371 uint16_t w[4];
372 int16_t sw[4];
373 uint32_t l[2];
374 float64 d;
375} vis64;
376
377typedef union {
378 uint8_t b[4];
379 uint16_t w[2];
380 uint32_t l;
381 float32 f;
382} vis32;
383
384void helper_fpmerge(void)
385{
386 vis64 s, d;
387
388 s.d = DT0;
389 d.d = DT1;
390
391 // Reverse calculation order to handle overlap
392 d.VIS_B64(7) = s.VIS_B64(3);
393 d.VIS_B64(6) = d.VIS_B64(3);
394 d.VIS_B64(5) = s.VIS_B64(2);
395 d.VIS_B64(4) = d.VIS_B64(2);
396 d.VIS_B64(3) = s.VIS_B64(1);
397 d.VIS_B64(2) = d.VIS_B64(1);
398 d.VIS_B64(1) = s.VIS_B64(0);
399 //d.VIS_B64(0) = d.VIS_B64(0);
400
401 DT0 = d.d;
402}
403
404void helper_fmul8x16(void)
405{
406 vis64 s, d;
407 uint32_t tmp;
408
409 s.d = DT0;
410 d.d = DT1;
411
412#define PMUL(r) \
413 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
414 if ((tmp & 0xff) > 0x7f) \
415 tmp += 0x100; \
416 d.VIS_W64(r) = tmp >> 8;
417
418 PMUL(0);
419 PMUL(1);
420 PMUL(2);
421 PMUL(3);
422#undef PMUL
423
424 DT0 = d.d;
425}
426
427void helper_fmul8x16al(void)
428{
429 vis64 s, d;
430 uint32_t tmp;
431
432 s.d = DT0;
433 d.d = DT1;
434
435#define PMUL(r) \
436 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
437 if ((tmp & 0xff) > 0x7f) \
438 tmp += 0x100; \
439 d.VIS_W64(r) = tmp >> 8;
440
441 PMUL(0);
442 PMUL(1);
443 PMUL(2);
444 PMUL(3);
445#undef PMUL
446
447 DT0 = d.d;
448}
449
450void helper_fmul8x16au(void)
451{
452 vis64 s, d;
453 uint32_t tmp;
454
455 s.d = DT0;
456 d.d = DT1;
457
458#define PMUL(r) \
459 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
460 if ((tmp & 0xff) > 0x7f) \
461 tmp += 0x100; \
462 d.VIS_W64(r) = tmp >> 8;
463
464 PMUL(0);
465 PMUL(1);
466 PMUL(2);
467 PMUL(3);
468#undef PMUL
469
470 DT0 = d.d;
471}
472
473void helper_fmul8sux16(void)
474{
475 vis64 s, d;
476 uint32_t tmp;
477
478 s.d = DT0;
479 d.d = DT1;
480
481#define PMUL(r) \
482 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
483 if ((tmp & 0xff) > 0x7f) \
484 tmp += 0x100; \
485 d.VIS_W64(r) = tmp >> 8;
486
487 PMUL(0);
488 PMUL(1);
489 PMUL(2);
490 PMUL(3);
491#undef PMUL
492
493 DT0 = d.d;
494}
495
496void helper_fmul8ulx16(void)
497{
498 vis64 s, d;
499 uint32_t tmp;
500
501 s.d = DT0;
502 d.d = DT1;
503
504#define PMUL(r) \
505 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
506 if ((tmp & 0xff) > 0x7f) \
507 tmp += 0x100; \
508 d.VIS_W64(r) = tmp >> 8;
509
510 PMUL(0);
511 PMUL(1);
512 PMUL(2);
513 PMUL(3);
514#undef PMUL
515
516 DT0 = d.d;
517}
518
519void helper_fmuld8sux16(void)
520{
521 vis64 s, d;
522 uint32_t tmp;
523
524 s.d = DT0;
525 d.d = DT1;
526
527#define PMUL(r) \
528 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
529 if ((tmp & 0xff) > 0x7f) \
530 tmp += 0x100; \
531 d.VIS_L64(r) = tmp;
532
533 // Reverse calculation order to handle overlap
534 PMUL(1);
535 PMUL(0);
536#undef PMUL
537
538 DT0 = d.d;
539}
540
541void helper_fmuld8ulx16(void)
542{
543 vis64 s, d;
544 uint32_t tmp;
545
546 s.d = DT0;
547 d.d = DT1;
548
549#define PMUL(r) \
550 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
551 if ((tmp & 0xff) > 0x7f) \
552 tmp += 0x100; \
553 d.VIS_L64(r) = tmp;
554
555 // Reverse calculation order to handle overlap
556 PMUL(1);
557 PMUL(0);
558#undef PMUL
559
560 DT0 = d.d;
561}
562
563void helper_fexpand(void)
564{
565 vis32 s;
566 vis64 d;
567
568 s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
569 d.d = DT1;
570 d.VIS_L64(0) = s.VIS_W32(0) << 4;
571 d.VIS_L64(1) = s.VIS_W32(1) << 4;
572 d.VIS_L64(2) = s.VIS_W32(2) << 4;
573 d.VIS_L64(3) = s.VIS_W32(3) << 4;
574
575 DT0 = d.d;
576}
577
578#define VIS_HELPER(name, F) \
579 void name##16(void) \
580 { \
581 vis64 s, d; \
582 \
583 s.d = DT0; \
584 d.d = DT1; \
585 \
586 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
587 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
588 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
589 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
590 \
591 DT0 = d.d; \
592 } \
593 \
594 void name##16s(void) \
595 { \
596 vis32 s, d; \
597 \
598 s.f = FT0; \
599 d.f = FT1; \
600 \
601 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
602 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
603 \
604 FT0 = d.f; \
605 } \
606 \
607 void name##32(void) \
608 { \
609 vis64 s, d; \
610 \
611 s.d = DT0; \
612 d.d = DT1; \
613 \
614 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
615 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
616 \
617 DT0 = d.d; \
618 } \
619 \
620 void name##32s(void) \
621 { \
622 vis32 s, d; \
623 \
624 s.f = FT0; \
625 d.f = FT1; \
626 \
627 d.l = F(d.l, s.l); \
628 \
629 FT0 = d.f; \
630 }
631
632#define FADD(a, b) ((a) + (b))
633#define FSUB(a, b) ((a) - (b))
634VIS_HELPER(helper_fpadd, FADD)
635VIS_HELPER(helper_fpsub, FSUB)
636
637#define VIS_CMPHELPER(name, F) \
638 void name##16(void) \
639 { \
640 vis64 s, d; \
641 \
642 s.d = DT0; \
643 d.d = DT1; \
644 \
645 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
646 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
647 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
648 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
649 \
650 DT0 = d.d; \
651 } \
652 \
653 void name##32(void) \
654 { \
655 vis64 s, d; \
656 \
657 s.d = DT0; \
658 d.d = DT1; \
659 \
660 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
661 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
662 \
663 DT0 = d.d; \
664 }
665
666#define FCMPGT(a, b) ((a) > (b))
667#define FCMPEQ(a, b) ((a) == (b))
668#define FCMPLE(a, b) ((a) <= (b))
669#define FCMPNE(a, b) ((a) != (b))
670
671VIS_CMPHELPER(helper_fcmpgt, FCMPGT)
672VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)
673VIS_CMPHELPER(helper_fcmple, FCMPLE)
674VIS_CMPHELPER(helper_fcmpne, FCMPNE)
675#endif
676
677void helper_check_ieee_exceptions(void)
678{
679 target_ulong status;
680
681 status = get_float_exception_flags(&env->fp_status);
682 if (status) {
683 /* Copy IEEE 754 flags into FSR */
684 if (status & float_flag_invalid)
685 env->fsr |= FSR_NVC;
686 if (status & float_flag_overflow)
687 env->fsr |= FSR_OFC;
688 if (status & float_flag_underflow)
689 env->fsr |= FSR_UFC;
690 if (status & float_flag_divbyzero)
691 env->fsr |= FSR_DZC;
692 if (status & float_flag_inexact)
693 env->fsr |= FSR_NXC;
694
695 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
696 /* Unmasked exception, generate a trap */
697 env->fsr |= FSR_FTT_IEEE_EXCP;
698 raise_exception(TT_FP_EXCP);
699 } else {
700 /* Accumulate exceptions */
701 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
702 }
703 }
704}
705
706void helper_clear_float_exceptions(void)
707{
708 set_float_exception_flags(0, &env->fp_status);
709}
710
7e8c2b6c 711void helper_fabss(void)
e8af50a3 712{
7a0e1f41 713 FT0 = float32_abs(FT1);
e8af50a3
FB		 714}
715
3475187d 716#ifdef TARGET_SPARC64
7e8c2b6c 717void helper_fabsd(void)
3475187d
FB		 718{
719 DT0 = float64_abs(DT1);
720}
4e14008f
BS		 721
722#if defined(CONFIG_USER_ONLY)
723void helper_fabsq(void)
724{
725 QT0 = float128_abs(QT1);
726}
727#endif
3475187d
FB		 728#endif
729
7e8c2b6c 730void helper_fsqrts(void)
e8af50a3 731{
7a0e1f41 732 FT0 = float32_sqrt(FT1, &env->fp_status);
e8af50a3
FB		 733}
734
7e8c2b6c 735void helper_fsqrtd(void)
e8af50a3 736{
7a0e1f41 737 DT0 = float64_sqrt(DT1, &env->fp_status);
e8af50a3
FB		 738}
739
4e14008f
BS		 740#if defined(CONFIG_USER_ONLY)
741void helper_fsqrtq(void)
742{
743 QT0 = float128_sqrt(QT1, &env->fp_status);
744}
745#endif
746
417454b0 747#define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
7e8c2b6c 748 void glue(helper_, name) (void) \
65ce8c2f 749 { \
1a2fb1c0
BS		 750 target_ulong new_fsr; \
751 \
65ce8c2f
FB		 752 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
753 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
754 case float_relation_unordered: \
1a2fb1c0 755 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
417454b0 756 if ((env->fsr & FSR_NVM) || TRAP) { \
1a2fb1c0 757 env->fsr |= new_fsr; \
417454b0
BS		 758 env->fsr |= FSR_NVC; \
759 env->fsr |= FSR_FTT_IEEE_EXCP; \
65ce8c2f
FB		 760 raise_exception(TT_FP_EXCP); \
761 } else { \
762 env->fsr |= FSR_NVA; \
763 } \
764 break; \
765 case float_relation_less: \
1a2fb1c0 766 new_fsr = FSR_FCC0 << FS; \
65ce8c2f
FB		 767 break; \
768 case float_relation_greater: \
1a2fb1c0 769 new_fsr = FSR_FCC1 << FS; \
65ce8c2f
FB		 770 break; \
771 default: \
1a2fb1c0 772 new_fsr = 0; \
65ce8c2f
FB		 773 break; \
774 } \
1a2fb1c0 775 env->fsr |= new_fsr; \
e8af50a3 776 }
e8af50a3 777
417454b0
BS		 778GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0);
779GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
780
781GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1);
782GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
3475187d 783
4e14008f
BS		 784#ifdef CONFIG_USER_ONLY
785GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
786GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
787#endif
788
3475187d 789#ifdef TARGET_SPARC64
417454b0
BS		 790GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0);
791GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
792
793GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0);
794GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
795
796GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0);
797GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
798
799GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1);
800GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
3475187d 801
417454b0
BS		 802GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1);
803GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
3475187d 804
417454b0
BS		 805GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1);
806GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
4e14008f
BS		 807#ifdef CONFIG_USER_ONLY
808GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
809GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
810GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
811GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
812GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
813GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
814#endif
3475187d
FB		 815#endif
816
1a2fb1c0 817#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && defined(DEBUG_MXCC)
952a328f
BS		 818static void dump_mxcc(CPUState *env)
819{
820 printf("mxccdata: %016llx %016llx %016llx %016llx\n",
821 env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]);
822 printf("mxccregs: %016llx %016llx %016llx %016llx\n"
823 " %016llx %016llx %016llx %016llx\n",
824 env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3],
825 env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]);
826}
827#endif
828
1a2fb1c0
BS		 829#if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
830 && defined(DEBUG_ASI)
831static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
832 uint64_t r1)
8543e2cf
BS		 833{
834 switch (size)
835 {
836 case 1:
1a2fb1c0
BS		 837 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
838 addr, asi, r1 & 0xff);
8543e2cf
BS		 839 break;
840 case 2:
1a2fb1c0
BS		 841 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
842 addr, asi, r1 & 0xffff);
8543e2cf
BS		 843 break;
844 case 4:
1a2fb1c0
BS		 845 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
846 addr, asi, r1 & 0xffffffff);
8543e2cf
BS		 847 break;
848 case 8:
1a2fb1c0
BS		 849 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
850 addr, asi, r1);
8543e2cf
BS		 851 break;
852 }
853}
854#endif
855
1a2fb1c0
BS		 856#ifndef TARGET_SPARC64
857#ifndef CONFIG_USER_ONLY
858uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
e8af50a3 859{
1a2fb1c0 860 uint64_t ret = 0;
8543e2cf 861#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
1a2fb1c0 862 uint32_t last_addr = addr;
952a328f 863#endif
e80cfcfc
FB		 864
865 switch (asi) {
6c36d3fa 866 case 2: /* SuperSparc MXCC registers */
1a2fb1c0 867 switch (addr) {
952a328f 868 case 0x01c00a00: /* MXCC control register */
1a2fb1c0
BS		 869 if (size == 8)
870 ret = env->mxccregs[3];
871 else
872 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 873 break;
874 case 0x01c00a04: /* MXCC control register */
875 if (size == 4)
876 ret = env->mxccregs[3];
877 else
1a2fb1c0 878 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f 879 break;
295db113
BS		 880 case 0x01c00c00: /* Module reset register */
881 if (size == 8) {
1a2fb1c0 882 ret = env->mxccregs[5];
295db113
BS		 883 // should we do something here?
884 } else
1a2fb1c0 885 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
295db113 886 break;
952a328f 887 case 0x01c00f00: /* MBus port address register */
1a2fb1c0
BS		 888 if (size == 8)
889 ret = env->mxccregs[7];
890 else
891 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 892 break;
893 default:
1a2fb1c0 894 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
952a328f
BS		 895 break;
896 }
1a2fb1c0
BS		 897 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, addr = %08x -> ret = %08x,"
898 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
952a328f
BS		 899#ifdef DEBUG_MXCC
900 dump_mxcc(env);
901#endif
6c36d3fa 902 break;
e8af50a3 903 case 3: /* MMU probe */
0f8a249a
BS		 904 {
905 int mmulev;
906
1a2fb1c0 907 mmulev = (addr >> 8) & 15;
0f8a249a
BS		 908 if (mmulev > 4)
909 ret = 0;
1a2fb1c0
BS		 910 else
911 ret = mmu_probe(env, addr, mmulev);
912 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
913 addr, mmulev, ret);
0f8a249a
BS		 914 }
915 break;
e8af50a3 916 case 4: /* read MMU regs */
0f8a249a 917 {
1a2fb1c0 918 int reg = (addr >> 8) & 0x1f;
3b46e624 919
0f8a249a
BS		 920 ret = env->mmuregs[reg];
921 if (reg == 3) /* Fault status cleared on read */
3dd9a152
BS		 922 env->mmuregs[3] = 0;
923 else if (reg == 0x13) /* Fault status read */
924 ret = env->mmuregs[3];
925 else if (reg == 0x14) /* Fault address read */
926 ret = env->mmuregs[4];
1a2fb1c0 927 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
0f8a249a
BS		 928 }
929 break;
045380be
BS		 930 case 5: // Turbosparc ITLB Diagnostic
931 case 6: // Turbosparc DTLB Diagnostic
932 case 7: // Turbosparc IOTLB Diagnostic
933 break;
6c36d3fa
BS		 934 case 9: /* Supervisor code access */
935 switch(size) {
936 case 1:
1a2fb1c0 937 ret = ldub_code(addr);
6c36d3fa
BS		 938 break;
939 case 2:
1a2fb1c0 940 ret = lduw_code(addr & ~1);
6c36d3fa
BS		 941 break;
942 default:
943 case 4:
1a2fb1c0 944 ret = ldl_code(addr & ~3);
6c36d3fa
BS		 945 break;
946 case 8:
1a2fb1c0 947 ret = ldq_code(addr & ~7);
6c36d3fa
BS		 948 break;
949 }
950 break;
81ad8ba2
BS		 951 case 0xa: /* User data access */
952 switch(size) {
953 case 1:
1a2fb1c0 954 ret = ldub_user(addr);
81ad8ba2
BS		 955 break;
956 case 2:
1a2fb1c0 957 ret = lduw_user(addr & ~1);
81ad8ba2
BS		 958 break;
959 default:
960 case 4:
1a2fb1c0 961 ret = ldl_user(addr & ~3);
81ad8ba2
BS		 962 break;
963 case 8:
1a2fb1c0 964 ret = ldq_user(addr & ~7);
81ad8ba2
BS		 965 break;
966 }
967 break;
968 case 0xb: /* Supervisor data access */
969 switch(size) {
970 case 1:
1a2fb1c0 971 ret = ldub_kernel(addr);
81ad8ba2
BS		 972 break;
973 case 2:
1a2fb1c0 974 ret = lduw_kernel(addr & ~1);
81ad8ba2
BS		 975 break;
976 default:
977 case 4:
1a2fb1c0 978 ret = ldl_kernel(addr & ~3);
81ad8ba2
BS		 979 break;
980 case 8:
1a2fb1c0 981 ret = ldq_kernel(addr & ~7);
81ad8ba2
BS		 982 break;
983 }
984 break;
6c36d3fa
BS		 985 case 0xc: /* I-cache tag */
986 case 0xd: /* I-cache data */
987 case 0xe: /* D-cache tag */
988 case 0xf: /* D-cache data */
989 break;
990 case 0x20: /* MMU passthrough */
02aab46a
FB		 991 switch(size) {
992 case 1:
1a2fb1c0 993 ret = ldub_phys(addr);
02aab46a
FB		 994 break;
995 case 2:
1a2fb1c0 996 ret = lduw_phys(addr & ~1);
02aab46a
FB		 997 break;
998 default:
999 case 4:
1a2fb1c0 1000 ret = ldl_phys(addr & ~3);
02aab46a 1001 break;
9e61bde5 1002 case 8:
1a2fb1c0 1003 ret = ldq_phys(addr & ~7);
0f8a249a 1004 break;
02aab46a 1005 }
0f8a249a 1006 break;
7d85892b 1007 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
5dcb6b91
BS		 1008 switch(size) {
1009 case 1:
1a2fb1c0 1010 ret = ldub_phys((target_phys_addr_t)addr
5dcb6b91
BS		 1011 | ((target_phys_addr_t)(asi & 0xf) << 32));
1012 break;
1013 case 2:
1a2fb1c0 1014 ret = lduw_phys((target_phys_addr_t)(addr & ~1)
5dcb6b91
BS		 1015 | ((target_phys_addr_t)(asi & 0xf) << 32));
1016 break;
1017 default:
1018 case 4:
1a2fb1c0 1019 ret = ldl_phys((target_phys_addr_t)(addr & ~3)
5dcb6b91
BS		 1020 | ((target_phys_addr_t)(asi & 0xf) << 32));
1021 break;
1022 case 8:
1a2fb1c0 1023 ret = ldq_phys((target_phys_addr_t)(addr & ~7)
5dcb6b91 1024 | ((target_phys_addr_t)(asi & 0xf) << 32));
0f8a249a 1025 break;
5dcb6b91 1026 }
0f8a249a 1027 break;
045380be
BS		 1028 case 0x30: // Turbosparc secondary cache diagnostic
1029 case 0x31: // Turbosparc RAM snoop
1030 case 0x32: // Turbosparc page table descriptor diagnostic
666c87aa
BS		 1031 case 0x39: /* data cache diagnostic register */
1032 ret = 0;
1033 break;
045380be 1034 case 8: /* User code access, XXX */
e8af50a3 1035 default:
1a2fb1c0 1036 do_unassigned_access(addr, 0, 0, asi);
0f8a249a
BS		 1037 ret = 0;
1038 break;
e8af50a3 1039 }
81ad8ba2
BS		 1040 if (sign) {
1041 switch(size) {
1042 case 1:
1a2fb1c0 1043 ret = (int8_t) ret;
e32664fb 1044 break;
81ad8ba2 1045 case 2:
1a2fb1c0
BS		 1046 ret = (int16_t) ret;
1047 break;
1048 case 4:
1049 ret = (int32_t) ret;
e32664fb 1050 break;
81ad8ba2 1051 default:
81ad8ba2
BS		 1052 break;
1053 }
1054 }
8543e2cf 1055#ifdef DEBUG_ASI
1a2fb1c0 1056 dump_asi("read ", last_addr, asi, size, ret);
8543e2cf 1057#endif
1a2fb1c0 1058 return ret;
e8af50a3
FB		 1059}
1060
1a2fb1c0 1061void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
e8af50a3
FB		 1062{
1063 switch(asi) {
6c36d3fa 1064 case 2: /* SuperSparc MXCC registers */
1a2fb1c0 1065 switch (addr) {
952a328f
BS		 1066 case 0x01c00000: /* MXCC stream data register 0 */
1067 if (size == 8)
1a2fb1c0 1068 env->mxccdata[0] = val;
952a328f 1069 else
1a2fb1c0 1070 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1071 break;
1072 case 0x01c00008: /* MXCC stream data register 1 */
1073 if (size == 8)
1a2fb1c0 1074 env->mxccdata[1] = val;
952a328f 1075 else
1a2fb1c0 1076 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1077 break;
1078 case 0x01c00010: /* MXCC stream data register 2 */
1079 if (size == 8)
1a2fb1c0 1080 env->mxccdata[2] = val;
952a328f 1081 else
1a2fb1c0 1082 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1083 break;
1084 case 0x01c00018: /* MXCC stream data register 3 */
1085 if (size == 8)
1a2fb1c0 1086 env->mxccdata[3] = val;
952a328f 1087 else
1a2fb1c0 1088 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1089 break;
1090 case 0x01c00100: /* MXCC stream source */
1091 if (size == 8)
1a2fb1c0 1092 env->mxccregs[0] = val;
952a328f 1093 else
1a2fb1c0 1094 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1095 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0);
1096 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8);
1097 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16);
1098 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 24);
1099 break;
1100 case 0x01c00200: /* MXCC stream destination */
1101 if (size == 8)
1a2fb1c0 1102 env->mxccregs[1] = val;
952a328f 1103 else
1a2fb1c0 1104 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1105 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]);
1106 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]);
1107 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]);
1108 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, env->mxccdata[3]);
1109 break;
1110 case 0x01c00a00: /* MXCC control register */
1111 if (size == 8)
1a2fb1c0 1112 env->mxccregs[3] = val;
952a328f 1113 else
1a2fb1c0 1114 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1115 break;
1116 case 0x01c00a04: /* MXCC control register */
1117 if (size == 4)
1a2fb1c0 1118 env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) | val;
952a328f 1119 else
1a2fb1c0 1120 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1121 break;
1122 case 0x01c00e00: /* MXCC error register */
bbf7d96b 1123 // writing a 1 bit clears the error
952a328f 1124 if (size == 8)
1a2fb1c0 1125 env->mxccregs[6] &= ~val;
952a328f 1126 else
1a2fb1c0 1127 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1128 break;
1129 case 0x01c00f00: /* MBus port address register */
1130 if (size == 8)
1a2fb1c0 1131 env->mxccregs[7] = val;
952a328f 1132 else
1a2fb1c0 1133 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
952a328f
BS		 1134 break;
1135 default:
1a2fb1c0 1136 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
952a328f
BS		 1137 break;
1138 }
1a2fb1c0 1139 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi, size, addr, val);
952a328f
BS		 1140#ifdef DEBUG_MXCC
1141 dump_mxcc(env);
1142#endif
6c36d3fa 1143 break;
e8af50a3 1144 case 3: /* MMU flush */
0f8a249a
BS		 1145 {
1146 int mmulev;
e80cfcfc 1147
1a2fb1c0 1148 mmulev = (addr >> 8) & 15;
952a328f 1149 DPRINTF_MMU("mmu flush level %d\n", mmulev);
0f8a249a
BS		 1150 switch (mmulev) {
1151 case 0: // flush page
1a2fb1c0 1152 tlb_flush_page(env, addr & 0xfffff000);
0f8a249a
BS		 1153 break;
1154 case 1: // flush segment (256k)
1155 case 2: // flush region (16M)
1156 case 3: // flush context (4G)
1157 case 4: // flush entire
1158 tlb_flush(env, 1);
1159 break;
1160 default:
1161 break;
1162 }
55754d9e 1163#ifdef DEBUG_MMU
0f8a249a 1164 dump_mmu(env);
55754d9e 1165#endif
0f8a249a 1166 }
8543e2cf 1167 break;
e8af50a3 1168 case 4: /* write MMU regs */
0f8a249a 1169 {
1a2fb1c0 1170 int reg = (addr >> 8) & 0x1f;
0f8a249a 1171 uint32_t oldreg;
3b46e624 1172
0f8a249a 1173 oldreg = env->mmuregs[reg];
55754d9e 1174 switch(reg) {
3deaeab7 1175 case 0: // Control Register
3dd9a152 1176 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
1a2fb1c0 1177 (val & 0x00ffffff);
0f8a249a
BS		 1178 // Mappings generated during no-fault mode or MMU
1179 // disabled mode are invalid in normal mode
3dd9a152
BS		 1180 if ((oldreg & (MMU_E | MMU_NF | env->mmu_bm)) !=
1181 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->mmu_bm)))
55754d9e
FB		 1182 tlb_flush(env, 1);
1183 break;
3deaeab7 1184 case 1: // Context Table Pointer Register
1a2fb1c0 1185 env->mmuregs[reg] = val & env->mmu_ctpr_mask;
3deaeab7
BS		 1186 break;
1187 case 2: // Context Register
1a2fb1c0 1188 env->mmuregs[reg] = val & env->mmu_cxr_mask;
55754d9e
FB		 1189 if (oldreg != env->mmuregs[reg]) {
1190 /* we flush when the MMU context changes because
1191 QEMU has no MMU context support */
1192 tlb_flush(env, 1);
1193 }
1194 break;
3deaeab7
BS		 1195 case 3: // Synchronous Fault Status Register with Clear
1196 case 4: // Synchronous Fault Address Register
1197 break;
1198 case 0x10: // TLB Replacement Control Register
1a2fb1c0 1199 env->mmuregs[reg] = val & env->mmu_trcr_mask;
55754d9e 1200 break;
3deaeab7 1201 case 0x13: // Synchronous Fault Status Register with Read and Clear
1a2fb1c0 1202 env->mmuregs[3] = val & env->mmu_sfsr_mask;
3dd9a152 1203 break;
3deaeab7 1204 case 0x14: // Synchronous Fault Address Register
1a2fb1c0 1205 env->mmuregs[4] = val;
3dd9a152 1206 break;
55754d9e 1207 default:
1a2fb1c0 1208 env->mmuregs[reg] = val;
55754d9e
FB		 1209 break;
1210 }
55754d9e 1211 if (oldreg != env->mmuregs[reg]) {
952a328f 1212 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
55754d9e 1213 }
952a328f 1214#ifdef DEBUG_MMU
0f8a249a 1215 dump_mmu(env);
55754d9e 1216#endif
0f8a249a 1217 }
8543e2cf 1218 break;
045380be
BS		 1219 case 5: // Turbosparc ITLB Diagnostic
1220 case 6: // Turbosparc DTLB Diagnostic
1221 case 7: // Turbosparc IOTLB Diagnostic
1222 break;
81ad8ba2
BS		 1223 case 0xa: /* User data access */
1224 switch(size) {
1225 case 1:
1a2fb1c0 1226 stb_user(addr, val);
81ad8ba2
BS		 1227 break;
1228 case 2:
1a2fb1c0 1229 stw_user(addr & ~1, val);
81ad8ba2
BS		 1230 break;
1231 default:
1232 case 4:
1a2fb1c0 1233 stl_user(addr & ~3, val);
81ad8ba2
BS		 1234 break;
1235 case 8:
1a2fb1c0 1236 stq_user(addr & ~7, val);
81ad8ba2
BS		 1237 break;
1238 }
1239 break;
1240 case 0xb: /* Supervisor data access */
1241 switch(size) {
1242 case 1:
1a2fb1c0 1243 stb_kernel(addr, val);
81ad8ba2
BS		 1244 break;
1245 case 2:
1a2fb1c0 1246 stw_kernel(addr & ~1, val);
81ad8ba2
BS		 1247 break;
1248 default:
1249 case 4:
1a2fb1c0 1250 stl_kernel(addr & ~3, val);
81ad8ba2
BS		 1251 break;
1252 case 8:
1a2fb1c0 1253 stq_kernel(addr & ~7, val);
81ad8ba2
BS		 1254 break;
1255 }
1256 break;
6c36d3fa
BS		 1257 case 0xc: /* I-cache tag */
1258 case 0xd: /* I-cache data */
1259 case 0xe: /* D-cache tag */
1260 case 0xf: /* D-cache data */
1261 case 0x10: /* I/D-cache flush page */
1262 case 0x11: /* I/D-cache flush segment */
1263 case 0x12: /* I/D-cache flush region */
1264 case 0x13: /* I/D-cache flush context */
1265 case 0x14: /* I/D-cache flush user */
1266 break;
e80cfcfc 1267 case 0x17: /* Block copy, sta access */
0f8a249a 1268 {
1a2fb1c0
BS		 1269 // val = src
1270 // addr = dst
0f8a249a 1271 // copy 32 bytes
6c36d3fa 1272 unsigned int i;
1a2fb1c0 1273 uint32_t src = val & ~3, dst = addr & ~3, temp;
3b46e624 1274
6c36d3fa
BS		 1275 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
1276 temp = ldl_kernel(src);
1277 stl_kernel(dst, temp);
1278 }
0f8a249a 1279 }
8543e2cf 1280 break;
e80cfcfc 1281 case 0x1f: /* Block fill, stda access */
0f8a249a 1282 {
1a2fb1c0
BS		 1283 // addr = dst
1284 // fill 32 bytes with val
6c36d3fa 1285 unsigned int i;
1a2fb1c0 1286 uint32_t dst = addr & 7;
6c36d3fa
BS		 1287
1288 for (i = 0; i < 32; i += 8, dst += 8)
1289 stq_kernel(dst, val);
0f8a249a 1290 }
8543e2cf 1291 break;
6c36d3fa 1292 case 0x20: /* MMU passthrough */
0f8a249a 1293 {
02aab46a
FB		 1294 switch(size) {
1295 case 1:
1a2fb1c0 1296 stb_phys(addr, val);
02aab46a
FB		 1297 break;
1298 case 2:
1a2fb1c0 1299 stw_phys(addr & ~1, val);
02aab46a
FB		 1300 break;
1301 case 4:
1302 default:
1a2fb1c0 1303 stl_phys(addr & ~3, val);
02aab46a 1304 break;
9e61bde5 1305 case 8:
1a2fb1c0 1306 stq_phys(addr & ~7, val);
9e61bde5 1307 break;
02aab46a 1308 }
0f8a249a 1309 }
8543e2cf 1310 break;
045380be 1311 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
0f8a249a 1312 {
5dcb6b91
BS		 1313 switch(size) {
1314 case 1:
1a2fb1c0
BS		 1315 stb_phys((target_phys_addr_t)addr
1316 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1317 break;
1318 case 2:
1a2fb1c0
BS		 1319 stw_phys((target_phys_addr_t)(addr & ~1)
1320 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1321 break;
1322 case 4:
1323 default:
1a2fb1c0
BS		 1324 stl_phys((target_phys_addr_t)(addr & ~3)
1325 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1326 break;
1327 case 8:
1a2fb1c0
BS		 1328 stq_phys((target_phys_addr_t)(addr & ~7)
1329 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1330 break;
1331 }
0f8a249a 1332 }
8543e2cf 1333 break;
045380be
BS		 1334 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
1335 case 0x31: // store buffer data, Ross RT620 I-cache flush or
1336 // Turbosparc snoop RAM
1337 case 0x32: // store buffer control or Turbosparc page table descriptor diagnostic
6c36d3fa
BS		 1338 case 0x36: /* I-cache flash clear */
1339 case 0x37: /* D-cache flash clear */
666c87aa
BS		 1340 case 0x38: /* breakpoint diagnostics */
1341 case 0x4c: /* breakpoint action */
6c36d3fa 1342 break;
045380be 1343 case 8: /* User code access, XXX */
6c36d3fa 1344 case 9: /* Supervisor code access, XXX */
e8af50a3 1345 default:
1a2fb1c0 1346 do_unassigned_access(addr, 1, 0, asi);
8543e2cf 1347 break;
e8af50a3 1348 }
8543e2cf 1349#ifdef DEBUG_ASI
1a2fb1c0 1350 dump_asi("write", addr, asi, size, val);
8543e2cf 1351#endif
e8af50a3
FB		 1352}
1353
81ad8ba2
BS		 1354#endif /* CONFIG_USER_ONLY */
1355#else /* TARGET_SPARC64 */
1356
1357#ifdef CONFIG_USER_ONLY
1a2fb1c0 1358uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
81ad8ba2
BS		 1359{
1360 uint64_t ret = 0;
1a2fb1c0
BS		 1361#if defined(DEBUG_ASI)
1362 target_ulong last_addr = addr;
1363#endif
81ad8ba2
BS		 1364
1365 if (asi < 0x80)
1366 raise_exception(TT_PRIV_ACT);
1367
1368 switch (asi) {
1369 case 0x80: // Primary
1370 case 0x82: // Primary no-fault
1371 case 0x88: // Primary LE
1372 case 0x8a: // Primary no-fault LE
1373 {
1374 switch(size) {
1375 case 1:
1a2fb1c0 1376 ret = ldub_raw(addr);
81ad8ba2
BS		 1377 break;
1378 case 2:
1a2fb1c0 1379 ret = lduw_raw(addr & ~1);
81ad8ba2
BS		 1380 break;
1381 case 4:
1a2fb1c0 1382 ret = ldl_raw(addr & ~3);
81ad8ba2
BS		 1383 break;
1384 default:
1385 case 8:
1a2fb1c0 1386 ret = ldq_raw(addr & ~7);
81ad8ba2
BS		 1387 break;
1388 }
1389 }
1390 break;
1391 case 0x81: // Secondary
1392 case 0x83: // Secondary no-fault
1393 case 0x89: // Secondary LE
1394 case 0x8b: // Secondary no-fault LE
1395 // XXX
1396 break;
1397 default:
1398 break;
1399 }
1400
1401 /* Convert from little endian */
1402 switch (asi) {
1403 case 0x88: // Primary LE
1404 case 0x89: // Secondary LE
1405 case 0x8a: // Primary no-fault LE
1406 case 0x8b: // Secondary no-fault LE
1407 switch(size) {
1408 case 2:
1409 ret = bswap16(ret);
e32664fb 1410 break;
81ad8ba2
BS		 1411 case 4:
1412 ret = bswap32(ret);
e32664fb 1413 break;
81ad8ba2
BS		 1414 case 8:
1415 ret = bswap64(ret);
e32664fb 1416 break;
81ad8ba2
BS		 1417 default:
1418 break;
1419 }
1420 default:
1421 break;
1422 }
1423
1424 /* Convert to signed number */
1425 if (sign) {
1426 switch(size) {
1427 case 1:
1428 ret = (int8_t) ret;
e32664fb 1429 break;
81ad8ba2
BS		 1430 case 2:
1431 ret = (int16_t) ret;
e32664fb 1432 break;
81ad8ba2
BS		 1433 case 4:
1434 ret = (int32_t) ret;
e32664fb 1435 break;
81ad8ba2
BS		 1436 default:
1437 break;
1438 }
1439 }
1a2fb1c0
BS		 1440#ifdef DEBUG_ASI
1441 dump_asi("read ", last_addr, asi, size, ret);
1442#endif
1443 return ret;
81ad8ba2
BS		 1444}
1445
1a2fb1c0 1446void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
81ad8ba2 1447{
1a2fb1c0
BS		 1448#ifdef DEBUG_ASI
1449 dump_asi("write", addr, asi, size, val);
1450#endif
81ad8ba2
BS		 1451 if (asi < 0x80)
1452 raise_exception(TT_PRIV_ACT);
1453
1454 /* Convert to little endian */
1455 switch (asi) {
1456 case 0x88: // Primary LE
1457 case 0x89: // Secondary LE
1458 switch(size) {
1459 case 2:
1a2fb1c0 1460 addr = bswap16(addr);
e32664fb 1461 break;
81ad8ba2 1462 case 4:
1a2fb1c0 1463 addr = bswap32(addr);
e32664fb 1464 break;
81ad8ba2 1465 case 8:
1a2fb1c0 1466 addr = bswap64(addr);
e32664fb 1467 break;
81ad8ba2
BS		 1468 default:
1469 break;
1470 }
1471 default:
1472 break;
1473 }
1474
1475 switch(asi) {
1476 case 0x80: // Primary
1477 case 0x88: // Primary LE
1478 {
1479 switch(size) {
1480 case 1:
1a2fb1c0 1481 stb_raw(addr, val);
81ad8ba2
BS		 1482 break;
1483 case 2:
1a2fb1c0 1484 stw_raw(addr & ~1, val);
81ad8ba2
BS		 1485 break;
1486 case 4:
1a2fb1c0 1487 stl_raw(addr & ~3, val);
81ad8ba2
BS		 1488 break;
1489 case 8:
1490 default:
1a2fb1c0 1491 stq_raw(addr & ~7, val);
81ad8ba2
BS		 1492 break;
1493 }
1494 }
1495 break;
1496 case 0x81: // Secondary
1497 case 0x89: // Secondary LE
1498 // XXX
1499 return;
1500
1501 case 0x82: // Primary no-fault, RO
1502 case 0x83: // Secondary no-fault, RO
1503 case 0x8a: // Primary no-fault LE, RO
1504 case 0x8b: // Secondary no-fault LE, RO
1505 default:
1a2fb1c0 1506 do_unassigned_access(addr, 1, 0, 1);
81ad8ba2
BS		 1507 return;
1508 }
1509}
1510
1511#else /* CONFIG_USER_ONLY */
3475187d 1512
1a2fb1c0 1513uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
3475187d 1514{
83469015 1515 uint64_t ret = 0;
1a2fb1c0
BS		 1516#if defined(DEBUG_ASI)
1517 target_ulong last_addr = addr;
1518#endif
3475187d 1519
6f27aba6 1520 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
20b749f6 1521 || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
0f8a249a 1522 raise_exception(TT_PRIV_ACT);
3475187d
FB		 1523
1524 switch (asi) {
81ad8ba2
BS		 1525 case 0x10: // As if user primary
1526 case 0x18: // As if user primary LE
1527 case 0x80: // Primary
1528 case 0x82: // Primary no-fault
1529 case 0x88: // Primary LE
1530 case 0x8a: // Primary no-fault LE
1531 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
6f27aba6
BS		 1532 if (env->hpstate & HS_PRIV) {
1533 switch(size) {
1534 case 1:
1a2fb1c0 1535 ret = ldub_hypv(addr);
6f27aba6
BS		 1536 break;
1537 case 2:
1a2fb1c0 1538 ret = lduw_hypv(addr & ~1);
6f27aba6
BS		 1539 break;
1540 case 4:
1a2fb1c0 1541 ret = ldl_hypv(addr & ~3);
6f27aba6
BS		 1542 break;
1543 default:
1544 case 8:
1a2fb1c0 1545 ret = ldq_hypv(addr & ~7);
6f27aba6
BS		 1546 break;
1547 }
1548 } else {
1549 switch(size) {
1550 case 1:
1a2fb1c0 1551 ret = ldub_kernel(addr);
6f27aba6
BS		 1552 break;
1553 case 2:
1a2fb1c0 1554 ret = lduw_kernel(addr & ~1);
6f27aba6
BS		 1555 break;
1556 case 4:
1a2fb1c0 1557 ret = ldl_kernel(addr & ~3);
6f27aba6
BS		 1558 break;
1559 default:
1560 case 8:
1a2fb1c0 1561 ret = ldq_kernel(addr & ~7);
6f27aba6
BS		 1562 break;
1563 }
81ad8ba2
BS		 1564 }
1565 } else {
1566 switch(size) {
1567 case 1:
1a2fb1c0 1568 ret = ldub_user(addr);
81ad8ba2
BS		 1569 break;
1570 case 2:
1a2fb1c0 1571 ret = lduw_user(addr & ~1);
81ad8ba2
BS		 1572 break;
1573 case 4:
1a2fb1c0 1574 ret = ldl_user(addr & ~3);
81ad8ba2
BS		 1575 break;
1576 default:
1577 case 8:
1a2fb1c0 1578 ret = ldq_user(addr & ~7);
81ad8ba2
BS		 1579 break;
1580 }
1581 }
1582 break;
3475187d
FB		 1583 case 0x14: // Bypass
1584 case 0x15: // Bypass, non-cacheable
81ad8ba2
BS		 1585 case 0x1c: // Bypass LE
1586 case 0x1d: // Bypass, non-cacheable LE
0f8a249a 1587 {
02aab46a
FB		 1588 switch(size) {
1589 case 1:
1a2fb1c0 1590 ret = ldub_phys(addr);
02aab46a
FB		 1591 break;
1592 case 2:
1a2fb1c0 1593 ret = lduw_phys(addr & ~1);
02aab46a
FB		 1594 break;
1595 case 4:
1a2fb1c0 1596 ret = ldl_phys(addr & ~3);
02aab46a
FB		 1597 break;
1598 default:
1599 case 8:
1a2fb1c0 1600 ret = ldq_phys(addr & ~7);
02aab46a
FB		 1601 break;
1602 }
0f8a249a
BS		 1603 break;
1604 }
83469015
FB		 1605 case 0x04: // Nucleus
1606 case 0x0c: // Nucleus Little Endian (LE)
83469015 1607 case 0x11: // As if user secondary
83469015 1608 case 0x19: // As if user secondary LE
83469015
FB		 1609 case 0x24: // Nucleus quad LDD 128 bit atomic
1610 case 0x2c: // Nucleus quad LDD 128 bit atomic
1611 case 0x4a: // UPA config
81ad8ba2 1612 case 0x81: // Secondary
83469015 1613 case 0x83: // Secondary no-fault
83469015 1614 case 0x89: // Secondary LE
83469015 1615 case 0x8b: // Secondary no-fault LE
0f8a249a
BS		 1616 // XXX
1617 break;
3475187d 1618 case 0x45: // LSU
0f8a249a
BS		 1619 ret = env->lsu;
1620 break;
3475187d 1621 case 0x50: // I-MMU regs
0f8a249a 1622 {
1a2fb1c0 1623 int reg = (addr >> 3) & 0xf;
3475187d 1624
0f8a249a
BS		 1625 ret = env->immuregs[reg];
1626 break;
1627 }
3475187d
FB		 1628 case 0x51: // I-MMU 8k TSB pointer
1629 case 0x52: // I-MMU 64k TSB pointer
1630 case 0x55: // I-MMU data access
0f8a249a
BS		 1631 // XXX
1632 break;
83469015 1633 case 0x56: // I-MMU tag read
0f8a249a
BS		 1634 {
1635 unsigned int i;
1636
1637 for (i = 0; i < 64; i++) {
1638 // Valid, ctx match, vaddr match
1639 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
1a2fb1c0 1640 env->itlb_tag[i] == addr) {
0f8a249a
BS		 1641 ret = env->itlb_tag[i];
1642 break;
1643 }
1644 }
1645 break;
1646 }
3475187d 1647 case 0x58: // D-MMU regs
0f8a249a 1648 {
1a2fb1c0 1649 int reg = (addr >> 3) & 0xf;
3475187d 1650
0f8a249a
BS		 1651 ret = env->dmmuregs[reg];
1652 break;
1653 }
83469015 1654 case 0x5e: // D-MMU tag read
0f8a249a
BS		 1655 {
1656 unsigned int i;
1657
1658 for (i = 0; i < 64; i++) {
1659 // Valid, ctx match, vaddr match
1660 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
1a2fb1c0 1661 env->dtlb_tag[i] == addr) {
0f8a249a
BS		 1662 ret = env->dtlb_tag[i];
1663 break;
1664 }
1665 }
1666 break;
1667 }
3475187d
FB		 1668 case 0x59: // D-MMU 8k TSB pointer
1669 case 0x5a: // D-MMU 64k TSB pointer
1670 case 0x5b: // D-MMU data pointer
1671 case 0x5d: // D-MMU data access
83469015
FB		 1672 case 0x48: // Interrupt dispatch, RO
1673 case 0x49: // Interrupt data receive
1674 case 0x7f: // Incoming interrupt vector, RO
0f8a249a
BS		 1675 // XXX
1676 break;
3475187d
FB		 1677 case 0x54: // I-MMU data in, WO
1678 case 0x57: // I-MMU demap, WO
1679 case 0x5c: // D-MMU data in, WO
1680 case 0x5f: // D-MMU demap, WO
83469015 1681 case 0x77: // Interrupt vector, WO
3475187d 1682 default:
1a2fb1c0 1683 do_unassigned_access(addr, 0, 0, 1);
0f8a249a
BS		 1684 ret = 0;
1685 break;
3475187d 1686 }
81ad8ba2
BS		 1687
1688 /* Convert from little endian */
1689 switch (asi) {
1690 case 0x0c: // Nucleus Little Endian (LE)
1691 case 0x18: // As if user primary LE
1692 case 0x19: // As if user secondary LE
1693 case 0x1c: // Bypass LE
1694 case 0x1d: // Bypass, non-cacheable LE
1695 case 0x88: // Primary LE
1696 case 0x89: // Secondary LE
1697 case 0x8a: // Primary no-fault LE
1698 case 0x8b: // Secondary no-fault LE
1699 switch(size) {
1700 case 2:
1701 ret = bswap16(ret);
e32664fb 1702 break;
81ad8ba2
BS		 1703 case 4:
1704 ret = bswap32(ret);
e32664fb 1705 break;
81ad8ba2
BS		 1706 case 8:
1707 ret = bswap64(ret);
e32664fb 1708 break;
81ad8ba2
BS		 1709 default:
1710 break;
1711 }
1712 default:
1713 break;
1714 }
1715
1716 /* Convert to signed number */
1717 if (sign) {
1718 switch(size) {
1719 case 1:
1720 ret = (int8_t) ret;
e32664fb 1721 break;
81ad8ba2
BS		 1722 case 2:
1723 ret = (int16_t) ret;
e32664fb 1724 break;
81ad8ba2
BS		 1725 case 4:
1726 ret = (int32_t) ret;
e32664fb 1727 break;
81ad8ba2
BS		 1728 default:
1729 break;
1730 }
1731 }
1a2fb1c0
BS		 1732#ifdef DEBUG_ASI
1733 dump_asi("read ", last_addr, asi, size, ret);
1734#endif
1735 return ret;
3475187d
FB		 1736}
1737
1a2fb1c0 1738void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
3475187d 1739{
1a2fb1c0
BS		 1740#ifdef DEBUG_ASI
1741 dump_asi("write", addr, asi, size, val);
1742#endif
6f27aba6 1743 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
20b749f6 1744 || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
0f8a249a 1745 raise_exception(TT_PRIV_ACT);
3475187d 1746
81ad8ba2
BS		 1747 /* Convert to little endian */
1748 switch (asi) {
1749 case 0x0c: // Nucleus Little Endian (LE)
1750 case 0x18: // As if user primary LE
1751 case 0x19: // As if user secondary LE
1752 case 0x1c: // Bypass LE
1753 case 0x1d: // Bypass, non-cacheable LE
81ad8ba2
BS		 1754 case 0x88: // Primary LE
1755 case 0x89: // Secondary LE
1756 switch(size) {
1757 case 2:
1a2fb1c0 1758 addr = bswap16(addr);
e32664fb 1759 break;
81ad8ba2 1760 case 4:
1a2fb1c0 1761 addr = bswap32(addr);
e32664fb 1762 break;
81ad8ba2 1763 case 8:
1a2fb1c0 1764 addr = bswap64(addr);
e32664fb 1765 break;
81ad8ba2
BS		 1766 default:
1767 break;
1768 }
1769 default:
1770 break;
1771 }
1772
3475187d 1773 switch(asi) {
81ad8ba2
BS		 1774 case 0x10: // As if user primary
1775 case 0x18: // As if user primary LE
1776 case 0x80: // Primary
1777 case 0x88: // Primary LE
1778 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
6f27aba6
BS		 1779 if (env->hpstate & HS_PRIV) {
1780 switch(size) {
1781 case 1:
1a2fb1c0 1782 stb_hypv(addr, val);
6f27aba6
BS		 1783 break;
1784 case 2:
1a2fb1c0 1785 stw_hypv(addr & ~1, val);
6f27aba6
BS		 1786 break;
1787 case 4:
1a2fb1c0 1788 stl_hypv(addr & ~3, val);
6f27aba6
BS		 1789 break;
1790 case 8:
1791 default:
1a2fb1c0 1792 stq_hypv(addr & ~7, val);
6f27aba6
BS		 1793 break;
1794 }
1795 } else {
1796 switch(size) {
1797 case 1:
1a2fb1c0 1798 stb_kernel(addr, val);
6f27aba6
BS		 1799 break;
1800 case 2:
1a2fb1c0 1801 stw_kernel(addr & ~1, val);
6f27aba6
BS		 1802 break;
1803 case 4:
1a2fb1c0 1804 stl_kernel(addr & ~3, val);
6f27aba6
BS		 1805 break;
1806 case 8:
1807 default:
1a2fb1c0 1808 stq_kernel(addr & ~7, val);
6f27aba6
BS		 1809 break;
1810 }
81ad8ba2
BS		 1811 }
1812 } else {
1813 switch(size) {
1814 case 1:
1a2fb1c0 1815 stb_user(addr, val);
81ad8ba2
BS		 1816 break;
1817 case 2:
1a2fb1c0 1818 stw_user(addr & ~1, val);
81ad8ba2
BS		 1819 break;
1820 case 4:
1a2fb1c0 1821 stl_user(addr & ~3, val);
81ad8ba2
BS		 1822 break;
1823 case 8:
1824 default:
1a2fb1c0 1825 stq_user(addr & ~7, val);
81ad8ba2
BS		 1826 break;
1827 }
1828 }
1829 break;
3475187d
FB		 1830 case 0x14: // Bypass
1831 case 0x15: // Bypass, non-cacheable
81ad8ba2
BS		 1832 case 0x1c: // Bypass LE
1833 case 0x1d: // Bypass, non-cacheable LE
0f8a249a 1834 {
02aab46a
FB		 1835 switch(size) {
1836 case 1:
1a2fb1c0 1837 stb_phys(addr, val);
02aab46a
FB		 1838 break;
1839 case 2:
1a2fb1c0 1840 stw_phys(addr & ~1, val);
02aab46a
FB		 1841 break;
1842 case 4:
1a2fb1c0 1843 stl_phys(addr & ~3, val);
02aab46a
FB		 1844 break;
1845 case 8:
1846 default:
1a2fb1c0 1847 stq_phys(addr & ~7, val);
02aab46a
FB		 1848 break;
1849 }
0f8a249a
BS		 1850 }
1851 return;
83469015
FB		 1852 case 0x04: // Nucleus
1853 case 0x0c: // Nucleus Little Endian (LE)
83469015 1854 case 0x11: // As if user secondary
83469015 1855 case 0x19: // As if user secondary LE
83469015
FB		 1856 case 0x24: // Nucleus quad LDD 128 bit atomic
1857 case 0x2c: // Nucleus quad LDD 128 bit atomic
1858 case 0x4a: // UPA config
51996525 1859 case 0x81: // Secondary
83469015 1860 case 0x89: // Secondary LE
0f8a249a
BS		 1861 // XXX
1862 return;
3475187d 1863 case 0x45: // LSU
0f8a249a
BS		 1864 {
1865 uint64_t oldreg;
1866
1867 oldreg = env->lsu;
1a2fb1c0 1868 env->lsu = val & (DMMU_E | IMMU_E);
0f8a249a
BS		 1869 // Mappings generated during D/I MMU disabled mode are
1870 // invalid in normal mode
1871 if (oldreg != env->lsu) {
952a328f 1872 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu);
83469015 1873#ifdef DEBUG_MMU
0f8a249a 1874 dump_mmu(env);
83469015 1875#endif
0f8a249a
BS		 1876 tlb_flush(env, 1);
1877 }
1878 return;
1879 }
3475187d 1880 case 0x50: // I-MMU regs
0f8a249a 1881 {
1a2fb1c0 1882 int reg = (addr >> 3) & 0xf;
0f8a249a 1883 uint64_t oldreg;
3b46e624 1884
0f8a249a 1885 oldreg = env->immuregs[reg];
3475187d
FB		 1886 switch(reg) {
1887 case 0: // RO
1888 case 4:
1889 return;
1890 case 1: // Not in I-MMU
1891 case 2:
1892 case 7:
1893 case 8:
1894 return;
1895 case 3: // SFSR
1a2fb1c0
BS		 1896 if ((val & 1) == 0)
1897 val = 0; // Clear SFSR
3475187d
FB		 1898 break;
1899 case 5: // TSB access
1900 case 6: // Tag access
1901 default:
1902 break;
1903 }
1a2fb1c0 1904 env->immuregs[reg] = val;
3475187d 1905 if (oldreg != env->immuregs[reg]) {
952a328f 1906 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
3475187d 1907 }
952a328f 1908#ifdef DEBUG_MMU
0f8a249a 1909 dump_mmu(env);
3475187d 1910#endif
0f8a249a
BS		 1911 return;
1912 }
3475187d 1913 case 0x54: // I-MMU data in
0f8a249a
BS		 1914 {
1915 unsigned int i;
1916
1917 // Try finding an invalid entry
1918 for (i = 0; i < 64; i++) {
1919 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
1920 env->itlb_tag[i] = env->immuregs[6];
1a2fb1c0 1921 env->itlb_tte[i] = val;
0f8a249a
BS		 1922 return;
1923 }
1924 }
1925 // Try finding an unlocked entry
1926 for (i = 0; i < 64; i++) {
1927 if ((env->itlb_tte[i] & 0x40) == 0) {
1928 env->itlb_tag[i] = env->immuregs[6];
1a2fb1c0 1929 env->itlb_tte[i] = val;
0f8a249a
BS		 1930 return;
1931 }
1932 }
1933 // error state?
1934 return;
1935 }
3475187d 1936 case 0x55: // I-MMU data access
0f8a249a 1937 {
1a2fb1c0 1938 unsigned int i = (addr >> 3) & 0x3f;
3475187d 1939
0f8a249a 1940 env->itlb_tag[i] = env->immuregs[6];
1a2fb1c0 1941 env->itlb_tte[i] = val;
0f8a249a
BS		 1942 return;
1943 }
3475187d 1944 case 0x57: // I-MMU demap
0f8a249a
BS		 1945 // XXX
1946 return;
3475187d 1947 case 0x58: // D-MMU regs
0f8a249a 1948 {
1a2fb1c0 1949 int reg = (addr >> 3) & 0xf;
0f8a249a 1950 uint64_t oldreg;
3b46e624 1951
0f8a249a 1952 oldreg = env->dmmuregs[reg];
3475187d
FB		 1953 switch(reg) {
1954 case 0: // RO
1955 case 4:
1956 return;
1957 case 3: // SFSR
1a2fb1c0
BS		 1958 if ((val & 1) == 0) {
1959 val = 0; // Clear SFSR, Fault address
0f8a249a
BS		 1960 env->dmmuregs[4] = 0;
1961 }
1a2fb1c0 1962 env->dmmuregs[reg] = val;
3475187d
FB		 1963 break;
1964 case 1: // Primary context
1965 case 2: // Secondary context
1966 case 5: // TSB access
1967 case 6: // Tag access
1968 case 7: // Virtual Watchpoint
1969 case 8: // Physical Watchpoint
1970 default:
1971 break;
1972 }
1a2fb1c0 1973 env->dmmuregs[reg] = val;
3475187d 1974 if (oldreg != env->dmmuregs[reg]) {
952a328f 1975 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
3475187d 1976 }
952a328f 1977#ifdef DEBUG_MMU
0f8a249a 1978 dump_mmu(env);
3475187d 1979#endif
0f8a249a
BS		 1980 return;
1981 }
3475187d 1982 case 0x5c: // D-MMU data in
0f8a249a
BS		 1983 {
1984 unsigned int i;
1985
1986 // Try finding an invalid entry
1987 for (i = 0; i < 64; i++) {
1988 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
1989 env->dtlb_tag[i] = env->dmmuregs[6];
1a2fb1c0 1990 env->dtlb_tte[i] = val;
0f8a249a
BS		 1991 return;
1992 }
1993 }
1994 // Try finding an unlocked entry
1995 for (i = 0; i < 64; i++) {
1996 if ((env->dtlb_tte[i] & 0x40) == 0) {
1997 env->dtlb_tag[i] = env->dmmuregs[6];
1a2fb1c0 1998 env->dtlb_tte[i] = val;
0f8a249a
BS		 1999 return;
2000 }
2001 }
2002 // error state?
2003 return;
2004 }
3475187d 2005 case 0x5d: // D-MMU data access
0f8a249a 2006 {
1a2fb1c0 2007 unsigned int i = (addr >> 3) & 0x3f;
3475187d 2008
0f8a249a 2009 env->dtlb_tag[i] = env->dmmuregs[6];
1a2fb1c0 2010 env->dtlb_tte[i] = val;
0f8a249a
BS		 2011 return;
2012 }
3475187d 2013 case 0x5f: // D-MMU demap
83469015 2014 case 0x49: // Interrupt data receive
0f8a249a
BS		 2015 // XXX
2016 return;
3475187d
FB		 2017 case 0x51: // I-MMU 8k TSB pointer, RO
2018 case 0x52: // I-MMU 64k TSB pointer, RO
2019 case 0x56: // I-MMU tag read, RO
2020 case 0x59: // D-MMU 8k TSB pointer, RO
2021 case 0x5a: // D-MMU 64k TSB pointer, RO
2022 case 0x5b: // D-MMU data pointer, RO
2023 case 0x5e: // D-MMU tag read, RO
83469015
FB		 2024 case 0x48: // Interrupt dispatch, RO
2025 case 0x7f: // Incoming interrupt vector, RO
2026 case 0x82: // Primary no-fault, RO
2027 case 0x83: // Secondary no-fault, RO
2028 case 0x8a: // Primary no-fault LE, RO
2029 case 0x8b: // Secondary no-fault LE, RO
3475187d 2030 default:
1a2fb1c0 2031 do_unassigned_access(addr, 1, 0, 1);
0f8a249a 2032 return;
3475187d
FB		 2033 }
2034}
81ad8ba2 2035#endif /* CONFIG_USER_ONLY */
3391c818 2036
1a2fb1c0 2037void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
3391c818 2038{
3391c818 2039 unsigned int i;
1a2fb1c0 2040 target_ulong val;
3391c818
BS		 2041
2042 switch (asi) {
2043 case 0xf0: // Block load primary
2044 case 0xf1: // Block load secondary
2045 case 0xf8: // Block load primary LE
2046 case 0xf9: // Block load secondary LE
51996525
BS		 2047 if (rd & 7) {
2048 raise_exception(TT_ILL_INSN);
2049 return;
2050 }
1a2fb1c0 2051 if (addr & 0x3f) {
51996525
BS		 2052 raise_exception(TT_UNALIGNED);
2053 return;
2054 }
2055 for (i = 0; i < 16; i++) {
1a2fb1c0
BS		 2056 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4, 0);
2057 addr += 4;
3391c818 2058 }
3391c818
BS		 2059
2060 return;
2061 default:
2062 break;
2063 }
2064
1a2fb1c0 2065 val = helper_ld_asi(addr, asi, size, 0);
3391c818
BS		 2066 switch(size) {
2067 default:
2068 case 4:
1a2fb1c0 2069 *((uint32_t *)&FT0) = val;
3391c818
BS		 2070 break;
2071 case 8:
1a2fb1c0 2072 *((int64_t *)&DT0) = val;
3391c818 2073 break;
1f587329
BS		 2074#if defined(CONFIG_USER_ONLY)
2075 case 16:
2076 // XXX
2077 break;
2078#endif
3391c818 2079 }
3391c818
BS		 2080}
2081
1a2fb1c0 2082void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
3391c818 2083{
3391c818 2084 unsigned int i;
1a2fb1c0 2085 target_ulong val = 0;
3391c818
BS		 2086
2087 switch (asi) {
2088 case 0xf0: // Block store primary
2089 case 0xf1: // Block store secondary
2090 case 0xf8: // Block store primary LE
2091 case 0xf9: // Block store secondary LE
51996525
BS		 2092 if (rd & 7) {
2093 raise_exception(TT_ILL_INSN);
2094 return;
2095 }
1a2fb1c0 2096 if (addr & 0x3f) {
51996525
BS		 2097 raise_exception(TT_UNALIGNED);
2098 return;
2099 }
2100 for (i = 0; i < 16; i++) {
1a2fb1c0
BS		 2101 val = *(uint32_t *)&env->fpr[rd++];
2102 helper_st_asi(addr, val, asi & 0x8f, 4);
2103 addr += 4;
3391c818 2104 }
3391c818
BS		 2105
2106 return;
2107 default:
2108 break;
2109 }
2110
2111 switch(size) {
2112 default:
2113 case 4:
1a2fb1c0 2114 val = *((uint32_t *)&FT0);
3391c818
BS		 2115 break;
2116 case 8:
1a2fb1c0 2117 val = *((int64_t *)&DT0);
3391c818 2118 break;
1f587329
BS		 2119#if defined(CONFIG_USER_ONLY)
2120 case 16:
2121 // XXX
2122 break;
2123#endif
3391c818 2124 }
1a2fb1c0
BS		 2125 helper_st_asi(addr, val, asi, size);
2126}
2127
2128target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
2129 target_ulong val2, uint32_t asi)
2130{
2131 target_ulong ret;
2132
2133 val1 &= 0xffffffffUL;
2134 ret = helper_ld_asi(addr, asi, 4, 0);
2135 ret &= 0xffffffffUL;
2136 if (val1 == ret)
2137 helper_st_asi(addr, val2 & 0xffffffffUL, asi, 4);
2138 return ret;
3391c818
BS		 2139}
2140
1a2fb1c0
BS		 2141target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
2142 target_ulong val2, uint32_t asi)
2143{
2144 target_ulong ret;
2145
2146 ret = helper_ld_asi(addr, asi, 8, 0);
2147 if (val1 == ret)
2148 helper_st_asi(addr, val2, asi, 8);
2149 return ret;
2150}
81ad8ba2 2151#endif /* TARGET_SPARC64 */
3475187d
FB		 2152
2153#ifndef TARGET_SPARC64
1a2fb1c0 2154void helper_rett(void)
e8af50a3 2155{
af7bf89b
FB		 2156 unsigned int cwp;
2157
d4218d99
BS		 2158 if (env->psret == 1)
2159 raise_exception(TT_ILL_INSN);
2160
e8af50a3 2161 env->psret = 1;
5fafdf24 2162 cwp = (env->cwp + 1) & (NWINDOWS - 1);
e8af50a3
FB		 2163 if (env->wim & (1 << cwp)) {
2164 raise_exception(TT_WIN_UNF);
2165 }
2166 set_cwp(cwp);
2167 env->psrs = env->psrps;
2168}
3475187d 2169#endif
e8af50a3 2170
3b89f26c
BS		 2171target_ulong helper_udiv(target_ulong a, target_ulong b)
2172{
2173 uint64_t x0;
2174 uint32_t x1;
2175
2176 x0 = a | ((uint64_t) (env->y) << 32);
2177 x1 = b;
2178
2179 if (x1 == 0) {
2180 raise_exception(TT_DIV_ZERO);
2181 }
2182
2183 x0 = x0 / x1;
2184 if (x0 > 0xffffffff) {
2185 env->cc_src2 = 1;
2186 return 0xffffffff;
2187 } else {
2188 env->cc_src2 = 0;
2189 return x0;
2190 }
2191}
2192
2193target_ulong helper_sdiv(target_ulong a, target_ulong b)
2194{
2195 int64_t x0;
2196 int32_t x1;
2197
2198 x0 = a | ((int64_t) (env->y) << 32);
2199 x1 = b;
2200
2201 if (x1 == 0) {
2202 raise_exception(TT_DIV_ZERO);
2203 }
2204
2205 x0 = x0 / x1;
2206 if ((int32_t) x0 != x0) {
2207 env->cc_src2 = 1;
2208 return x0 < 0? 0x80000000: 0x7fffffff;
2209 } else {
2210 env->cc_src2 = 0;
2211 return x0;
2212 }
2213}
2214
1a2fb1c0
BS		 2215uint64_t helper_pack64(target_ulong high, target_ulong low)
2216{
2217 return ((uint64_t)high << 32) | (uint64_t)(low & 0xffffffff);
2218}
2219
7fa76c0b
BS		 2220#ifdef TARGET_ABI32
2221#define ADDR(x) ((x) & 0xffffffff)
2222#else
2223#define ADDR(x) (x)
2224#endif
2225
2226#ifdef __i386__
2227void helper_std_i386(target_ulong addr, int mem_idx)
2228{
2229 uint64_t tmp = ((uint64_t)env->t1 << 32) | (uint64_t)(env->t2 & 0xffffffff);
2230
2231#if !defined(CONFIG_USER_ONLY)
2232 switch (mem_idx) {
2233 case 0:
2234 stq_user(ADDR(addr), tmp);
2235 break;
2236 case 1:
2237 stq_kernel(ADDR(addr), tmp);
2238 break;
2239#ifdef TARGET_SPARC64
2240 case 2:
2241 stq_hypv(ADDR(addr), tmp);
2242 break;
2243#endif
2244 default:
2245 break;
2246 }
2247#else
2248 stq_raw(ADDR(addr), tmp);
2249#endif
2250}
2251#endif /* __i386__ */
2252
2253void helper_stdf(target_ulong addr, int mem_idx)
2254{
2255#if !defined(CONFIG_USER_ONLY)
2256 switch (mem_idx) {
2257 case 0:
2258 stfq_user(ADDR(addr), DT0);
2259 break;
2260 case 1:
2261 stfq_kernel(ADDR(addr), DT0);
2262 break;
2263#ifdef TARGET_SPARC64
2264 case 2:
2265 stfq_hypv(ADDR(addr), DT0);
2266 break;
2267#endif
2268 default:
2269 break;
2270 }
2271#else
2272 stfq_raw(ADDR(addr), DT0);
2273#endif
2274}
2275
2276void helper_lddf(target_ulong addr, int mem_idx)
2277{
2278#if !defined(CONFIG_USER_ONLY)
2279 switch (mem_idx) {
2280 case 0:
2281 DT0 = ldfq_user(ADDR(addr));
2282 break;
2283 case 1:
2284 DT0 = ldfq_kernel(ADDR(addr));
2285 break;
2286#ifdef TARGET_SPARC64
2287 case 2:
2288 DT0 = ldfq_hypv(ADDR(addr));
2289 break;
2290#endif
2291 default:
2292 break;
2293 }
2294#else
2295 DT0 = ldfq_raw(ADDR(addr));
2296#endif
2297}
2298
2299#if defined(CONFIG_USER_ONLY)
2300void helper_ldqf(target_ulong addr)
2301{
2302 // XXX add 128 bit load
2303 CPU_QuadU u;
2304
2305 u.ll.upper = ldq_raw(ADDR(addr));
2306 u.ll.lower = ldq_raw(ADDR(addr + 8));
2307 QT0 = u.q;
2308}
2309
2310void helper_stqf(target_ulong addr)
2311{
2312 // XXX add 128 bit store
2313 CPU_QuadU u;
2314
2315 u.q = QT0;
2316 stq_raw(ADDR(addr), u.ll.upper);
2317 stq_raw(ADDR(addr + 8), u.ll.lower);
2318}
2319#endif
2320
2321#undef ADDR
2322
8d5f07fa 2323void helper_ldfsr(void)
e8af50a3 2324{
7a0e1f41 2325 int rnd_mode;
bb5529bb
BS		 2326
2327 PUT_FSR32(env, *((uint32_t *) &FT0));
e8af50a3
FB		 2328 switch (env->fsr & FSR_RD_MASK) {
2329 case FSR_RD_NEAREST:
7a0e1f41 2330 rnd_mode = float_round_nearest_even;
0f8a249a 2331 break;
ed910241 2332 default:
e8af50a3 2333 case FSR_RD_ZERO:
7a0e1f41 2334 rnd_mode = float_round_to_zero;
0f8a249a 2335 break;
e8af50a3 2336 case FSR_RD_POS:
7a0e1f41 2337 rnd_mode = float_round_up;
0f8a249a 2338 break;
e8af50a3 2339 case FSR_RD_NEG:
7a0e1f41 2340 rnd_mode = float_round_down;
0f8a249a 2341 break;
e8af50a3 2342 }
7a0e1f41 2343 set_float_rounding_mode(rnd_mode, &env->fp_status);
e8af50a3 2344}
e80cfcfc 2345
bb5529bb
BS		 2346void helper_stfsr(void)
2347{
2348 *((uint32_t *) &FT0) = GET_FSR32(env);
2349}
2350
2351void helper_debug(void)
e80cfcfc
FB		 2352{
2353 env->exception_index = EXCP_DEBUG;
2354 cpu_loop_exit();
2355}
af7bf89b 2356
3475187d 2357#ifndef TARGET_SPARC64
72a9747b
BS		 2358/* XXX: use another pointer for %iN registers to avoid slow wrapping
2359 handling ? */
2360void helper_save(void)
2361{
2362 uint32_t cwp;
2363
2364 cwp = (env->cwp - 1) & (NWINDOWS - 1);
2365 if (env->wim & (1 << cwp)) {
2366 raise_exception(TT_WIN_OVF);
2367 }
2368 set_cwp(cwp);
2369}
2370
2371void helper_restore(void)
2372{
2373 uint32_t cwp;
2374
2375 cwp = (env->cwp + 1) & (NWINDOWS - 1);
2376 if (env->wim & (1 << cwp)) {
2377 raise_exception(TT_WIN_UNF);
2378 }
2379 set_cwp(cwp);
2380}
2381
1a2fb1c0 2382void helper_wrpsr(target_ulong new_psr)
af7bf89b 2383{
1a2fb1c0 2384 if ((new_psr & PSR_CWP) >= NWINDOWS)
d4218d99
BS		 2385 raise_exception(TT_ILL_INSN);
2386 else
1a2fb1c0 2387 PUT_PSR(env, new_psr);
af7bf89b
FB		 2388}
2389
1a2fb1c0 2390target_ulong helper_rdpsr(void)
af7bf89b 2391{
1a2fb1c0 2392 return GET_PSR(env);
af7bf89b 2393}
3475187d
FB		 2394
2395#else
72a9747b
BS		 2396/* XXX: use another pointer for %iN registers to avoid slow wrapping
2397 handling ? */
2398void helper_save(void)
2399{
2400 uint32_t cwp;
2401
2402 cwp = (env->cwp - 1) & (NWINDOWS - 1);
2403 if (env->cansave == 0) {
2404 raise_exception(TT_SPILL | (env->otherwin != 0 ?
2405 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2406 ((env->wstate & 0x7) << 2)));
2407 } else {
2408 if (env->cleanwin - env->canrestore == 0) {
2409 // XXX Clean windows without trap
2410 raise_exception(TT_CLRWIN);
2411 } else {
2412 env->cansave--;
2413 env->canrestore++;
2414 set_cwp(cwp);
2415 }
2416 }
2417}
2418
2419void helper_restore(void)
2420{
2421 uint32_t cwp;
2422
2423 cwp = (env->cwp + 1) & (NWINDOWS - 1);
2424 if (env->canrestore == 0) {
2425 raise_exception(TT_FILL | (env->otherwin != 0 ?
2426 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2427 ((env->wstate & 0x7) << 2)));
2428 } else {
2429 env->cansave++;
2430 env->canrestore--;
2431 set_cwp(cwp);
2432 }
2433}
2434
2435void helper_flushw(void)
2436{
2437 if (env->cansave != NWINDOWS - 2) {
2438 raise_exception(TT_SPILL | (env->otherwin != 0 ?
2439 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2440 ((env->wstate & 0x7) << 2)));
2441 }
2442}
2443
2444void helper_saved(void)
2445{
2446 env->cansave++;
2447 if (env->otherwin == 0)
2448 env->canrestore--;
2449 else
2450 env->otherwin--;
2451}
2452
2453void helper_restored(void)
2454{
2455 env->canrestore++;
2456 if (env->cleanwin < NWINDOWS - 1)
2457 env->cleanwin++;
2458 if (env->otherwin == 0)
2459 env->cansave--;
2460 else
2461 env->otherwin--;
2462}
2463
d35527d9
BS		 2464target_ulong helper_rdccr(void)
2465{
2466 return GET_CCR(env);
2467}
2468
2469void helper_wrccr(target_ulong new_ccr)
2470{
2471 PUT_CCR(env, new_ccr);
2472}
2473
2474// CWP handling is reversed in V9, but we still use the V8 register
2475// order.
2476target_ulong helper_rdcwp(void)
2477{
2478 return GET_CWP64(env);
2479}
2480
2481void helper_wrcwp(target_ulong new_cwp)
2482{
2483 PUT_CWP64(env, new_cwp);
2484}
3475187d 2485
1f5063fb
BS		 2486// This function uses non-native bit order
2487#define GET_FIELD(X, FROM, TO) \
2488 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
2489
2490// This function uses the order in the manuals, i.e. bit 0 is 2^0
2491#define GET_FIELD_SP(X, FROM, TO) \
2492 GET_FIELD(X, 63 - (TO), 63 - (FROM))
2493
2494target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
2495{
2496 return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
2497 (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
2498 (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) |
2499 (GET_FIELD_SP(pixel_addr, 56, 59) << 13) |
2500 (GET_FIELD_SP(pixel_addr, 35, 38) << 9) |
2501 (GET_FIELD_SP(pixel_addr, 13, 16) << 5) |
2502 (((pixel_addr >> 55) & 1) << 4) |
2503 (GET_FIELD_SP(pixel_addr, 33, 34) << 2) |
2504 GET_FIELD_SP(pixel_addr, 11, 12);
2505}
2506
2507target_ulong helper_alignaddr(target_ulong addr, target_ulong offset)
2508{
2509 uint64_t tmp;
2510
2511 tmp = addr + offset;
2512 env->gsr &= ~7ULL;
2513 env->gsr |= tmp & 7ULL;
2514 return tmp & ~7ULL;
2515}
2516
1a2fb1c0 2517target_ulong helper_popc(target_ulong val)
3475187d 2518{
1a2fb1c0 2519 return ctpop64(val);
3475187d 2520}
83469015
FB		 2521
2522static inline uint64_t *get_gregset(uint64_t pstate)
2523{
2524 switch (pstate) {
2525 default:
2526 case 0:
0f8a249a 2527 return env->bgregs;
83469015 2528 case PS_AG:
0f8a249a 2529 return env->agregs;
83469015 2530 case PS_MG:
0f8a249a 2531 return env->mgregs;
83469015 2532 case PS_IG:
0f8a249a 2533 return env->igregs;
83469015
FB		 2534 }
2535}
2536
8f1f22f6 2537static inline void change_pstate(uint64_t new_pstate)
83469015 2538{
8f1f22f6 2539 uint64_t pstate_regs, new_pstate_regs;
83469015
FB		 2540 uint64_t *src, *dst;
2541
83469015
FB		 2542 pstate_regs = env->pstate & 0xc01;
2543 new_pstate_regs = new_pstate & 0xc01;
2544 if (new_pstate_regs != pstate_regs) {
0f8a249a
BS		 2545 // Switch global register bank
2546 src = get_gregset(new_pstate_regs);
2547 dst = get_gregset(pstate_regs);
2548 memcpy32(dst, env->gregs);
2549 memcpy32(env->gregs, src);
83469015
FB		 2550 }
2551 env->pstate = new_pstate;
2552}
2553
1a2fb1c0 2554void helper_wrpstate(target_ulong new_state)
8f1f22f6 2555{
1a2fb1c0 2556 change_pstate(new_state & 0xf3f);
8f1f22f6
BS		 2557}
2558
1a2fb1c0 2559void helper_done(void)
83469015
FB		 2560{
2561 env->tl--;
375ee38b
BS		 2562 env->tsptr = &env->ts[env->tl];
2563 env->pc = env->tsptr->tpc;
2564 env->npc = env->tsptr->tnpc + 4;
2565 PUT_CCR(env, env->tsptr->tstate >> 32);
2566 env->asi = (env->tsptr->tstate >> 24) & 0xff;
2567 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2568 PUT_CWP64(env, env->tsptr->tstate & 0xff);
83469015
FB		 2569}
2570
1a2fb1c0 2571void helper_retry(void)
83469015
FB		 2572{
2573 env->tl--;
375ee38b
BS		 2574 env->tsptr = &env->ts[env->tl];
2575 env->pc = env->tsptr->tpc;
2576 env->npc = env->tsptr->tnpc;
2577 PUT_CCR(env, env->tsptr->tstate >> 32);
2578 env->asi = (env->tsptr->tstate >> 24) & 0xff;
2579 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2580 PUT_CWP64(env, env->tsptr->tstate & 0xff);
83469015 2581}
3475187d 2582#endif
ee5bbe38
FB		 2583
2584void set_cwp(int new_cwp)
2585{
2586 /* put the modified wrap registers at their proper location */
2587 if (env->cwp == (NWINDOWS - 1))
2588 memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
2589 env->cwp = new_cwp;
2590 /* put the wrap registers at their temporary location */
2591 if (new_cwp == (NWINDOWS - 1))
2592 memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
2593 env->regwptr = env->regbase + (new_cwp * 16);
2594 REGWPTR = env->regwptr;
2595}
2596
2597void cpu_set_cwp(CPUState *env1, int new_cwp)
2598{
2599 CPUState *saved_env;
2600#ifdef reg_REGWPTR
2601 target_ulong *saved_regwptr;
2602#endif
2603
2604 saved_env = env;
2605#ifdef reg_REGWPTR
2606 saved_regwptr = REGWPTR;
2607#endif
2608 env = env1;
2609 set_cwp(new_cwp);
2610 env = saved_env;
2611#ifdef reg_REGWPTR
2612 REGWPTR = saved_regwptr;
2613#endif
2614}
2615
2616#ifdef TARGET_SPARC64
0b09be2b
BS		 2617#ifdef DEBUG_PCALL
2618static const char * const excp_names[0x50] = {
2619 [TT_TFAULT] = "Instruction Access Fault",
2620 [TT_TMISS] = "Instruction Access MMU Miss",
2621 [TT_CODE_ACCESS] = "Instruction Access Error",
2622 [TT_ILL_INSN] = "Illegal Instruction",
2623 [TT_PRIV_INSN] = "Privileged Instruction",
2624 [TT_NFPU_INSN] = "FPU Disabled",
2625 [TT_FP_EXCP] = "FPU Exception",
2626 [TT_TOVF] = "Tag Overflow",
2627 [TT_CLRWIN] = "Clean Windows",
2628 [TT_DIV_ZERO] = "Division By Zero",
2629 [TT_DFAULT] = "Data Access Fault",
2630 [TT_DMISS] = "Data Access MMU Miss",
2631 [TT_DATA_ACCESS] = "Data Access Error",
2632 [TT_DPROT] = "Data Protection Error",
2633 [TT_UNALIGNED] = "Unaligned Memory Access",
2634 [TT_PRIV_ACT] = "Privileged Action",
2635 [TT_EXTINT | 0x1] = "External Interrupt 1",
2636 [TT_EXTINT | 0x2] = "External Interrupt 2",
2637 [TT_EXTINT | 0x3] = "External Interrupt 3",
2638 [TT_EXTINT | 0x4] = "External Interrupt 4",
2639 [TT_EXTINT | 0x5] = "External Interrupt 5",
2640 [TT_EXTINT | 0x6] = "External Interrupt 6",
2641 [TT_EXTINT | 0x7] = "External Interrupt 7",
2642 [TT_EXTINT | 0x8] = "External Interrupt 8",
2643 [TT_EXTINT | 0x9] = "External Interrupt 9",
2644 [TT_EXTINT | 0xa] = "External Interrupt 10",
2645 [TT_EXTINT | 0xb] = "External Interrupt 11",
2646 [TT_EXTINT | 0xc] = "External Interrupt 12",
2647 [TT_EXTINT | 0xd] = "External Interrupt 13",
2648 [TT_EXTINT | 0xe] = "External Interrupt 14",
2649 [TT_EXTINT | 0xf] = "External Interrupt 15",
2650};
2651#endif
2652
ee5bbe38
FB		 2653void do_interrupt(int intno)
2654{
2655#ifdef DEBUG_PCALL
2656 if (loglevel & CPU_LOG_INT) {
0f8a249a 2657 static int count;
0b09be2b
BS		 2658 const char *name;
2659
2660 if (intno < 0 || intno >= 0x180 || (intno > 0x4f && intno < 0x80))
2661 name = "Unknown";
2662 else if (intno >= 0x100)
2663 name = "Trap Instruction";
2664 else if (intno >= 0xc0)
2665 name = "Window Fill";
2666 else if (intno >= 0x80)
2667 name = "Window Spill";
2668 else {
2669 name = excp_names[intno];
2670 if (!name)
2671 name = "Unknown";
2672 }
2673
2674 fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
2675 " SP=%016" PRIx64 "\n",
2676 count, name, intno,
ee5bbe38
FB		 2677 env->pc,
2678 env->npc, env->regwptr[6]);
0f8a249a 2679 cpu_dump_state(env, logfile, fprintf, 0);
ee5bbe38 2680#if 0
0f8a249a
BS		 2681 {
2682 int i;
2683 uint8_t *ptr;
2684
2685 fprintf(logfile, " code=");
2686 ptr = (uint8_t *)env->pc;
2687 for(i = 0; i < 16; i++) {
2688 fprintf(logfile, " %02x", ldub(ptr + i));
2689 }
2690 fprintf(logfile, "\n");
2691 }
ee5bbe38 2692#endif
0f8a249a 2693 count++;
ee5bbe38
FB		 2694 }
2695#endif
5fafdf24 2696#if !defined(CONFIG_USER_ONLY)
83469015 2697 if (env->tl == MAXTL) {
c68ea704 2698 cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
0f8a249a 2699 return;
ee5bbe38
FB		 2700 }
2701#endif
375ee38b
BS		 2702 env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
2703 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
2704 GET_CWP64(env);
2705 env->tsptr->tpc = env->pc;
2706 env->tsptr->tnpc = env->npc;
2707 env->tsptr->tt = intno;
8f1f22f6
BS		 2708 change_pstate(PS_PEF | PS_PRIV | PS_AG);
2709
2710 if (intno == TT_CLRWIN)
2711 set_cwp((env->cwp - 1) & (NWINDOWS - 1));
2712 else if ((intno & 0x1c0) == TT_SPILL)
2713 set_cwp((env->cwp - env->cansave - 2) & (NWINDOWS - 1));
2714 else if ((intno & 0x1c0) == TT_FILL)
2715 set_cwp((env->cwp + 1) & (NWINDOWS - 1));
83469015
FB		 2716 env->tbr &= ~0x7fffULL;
2717 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
2718 if (env->tl < MAXTL - 1) {
0f8a249a 2719 env->tl++;
83469015 2720 } else {
0f8a249a
BS		 2721 env->pstate |= PS_RED;
2722 if (env->tl != MAXTL)
2723 env->tl++;
83469015 2724 }
375ee38b 2725 env->tsptr = &env->ts[env->tl];
ee5bbe38
FB		 2726 env->pc = env->tbr;
2727 env->npc = env->pc + 4;
2728 env->exception_index = 0;
2729}
2730#else
0b09be2b
BS		 2731#ifdef DEBUG_PCALL
2732static const char * const excp_names[0x80] = {
2733 [TT_TFAULT] = "Instruction Access Fault",
2734 [TT_ILL_INSN] = "Illegal Instruction",
2735 [TT_PRIV_INSN] = "Privileged Instruction",
2736 [TT_NFPU_INSN] = "FPU Disabled",
2737 [TT_WIN_OVF] = "Window Overflow",
2738 [TT_WIN_UNF] = "Window Underflow",
2739 [TT_UNALIGNED] = "Unaligned Memory Access",
2740 [TT_FP_EXCP] = "FPU Exception",
2741 [TT_DFAULT] = "Data Access Fault",
2742 [TT_TOVF] = "Tag Overflow",
2743 [TT_EXTINT | 0x1] = "External Interrupt 1",
2744 [TT_EXTINT | 0x2] = "External Interrupt 2",
2745 [TT_EXTINT | 0x3] = "External Interrupt 3",
2746 [TT_EXTINT | 0x4] = "External Interrupt 4",
2747 [TT_EXTINT | 0x5] = "External Interrupt 5",
2748 [TT_EXTINT | 0x6] = "External Interrupt 6",
2749 [TT_EXTINT | 0x7] = "External Interrupt 7",
2750 [TT_EXTINT | 0x8] = "External Interrupt 8",
2751 [TT_EXTINT | 0x9] = "External Interrupt 9",
2752 [TT_EXTINT | 0xa] = "External Interrupt 10",
2753 [TT_EXTINT | 0xb] = "External Interrupt 11",
2754 [TT_EXTINT | 0xc] = "External Interrupt 12",
2755 [TT_EXTINT | 0xd] = "External Interrupt 13",
2756 [TT_EXTINT | 0xe] = "External Interrupt 14",
2757 [TT_EXTINT | 0xf] = "External Interrupt 15",
2758 [TT_TOVF] = "Tag Overflow",
2759 [TT_CODE_ACCESS] = "Instruction Access Error",
2760 [TT_DATA_ACCESS] = "Data Access Error",
2761 [TT_DIV_ZERO] = "Division By Zero",
2762 [TT_NCP_INSN] = "Coprocessor Disabled",
2763};
2764#endif
2765
ee5bbe38
FB		 2766void do_interrupt(int intno)
2767{
2768 int cwp;
2769
2770#ifdef DEBUG_PCALL
2771 if (loglevel & CPU_LOG_INT) {
0f8a249a 2772 static int count;
0b09be2b
BS		 2773 const char *name;
2774
2775 if (intno < 0 || intno >= 0x100)
2776 name = "Unknown";
2777 else if (intno >= 0x80)
2778 name = "Trap Instruction";
2779 else {
2780 name = excp_names[intno];
2781 if (!name)
2782 name = "Unknown";
2783 }
2784
2785 fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
2786 count, name, intno,
ee5bbe38
FB		 2787 env->pc,
2788 env->npc, env->regwptr[6]);
0f8a249a 2789 cpu_dump_state(env, logfile, fprintf, 0);
ee5bbe38 2790#if 0
0f8a249a
BS		 2791 {
2792 int i;
2793 uint8_t *ptr;
2794
2795 fprintf(logfile, " code=");
2796 ptr = (uint8_t *)env->pc;
2797 for(i = 0; i < 16; i++) {
2798 fprintf(logfile, " %02x", ldub(ptr + i));
2799 }
2800 fprintf(logfile, "\n");
2801 }
ee5bbe38 2802#endif
0f8a249a 2803 count++;
ee5bbe38
FB		 2804 }
2805#endif
5fafdf24 2806#if !defined(CONFIG_USER_ONLY)
ee5bbe38 2807 if (env->psret == 0) {
c68ea704 2808 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
0f8a249a 2809 return;
ee5bbe38
FB		 2810 }
2811#endif
2812 env->psret = 0;
5fafdf24 2813 cwp = (env->cwp - 1) & (NWINDOWS - 1);
ee5bbe38
FB		 2814 set_cwp(cwp);
2815 env->regwptr[9] = env->pc;
2816 env->regwptr[10] = env->npc;
2817 env->psrps = env->psrs;
2818 env->psrs = 1;
2819 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
2820 env->pc = env->tbr;
2821 env->npc = env->pc + 4;
2822 env->exception_index = 0;
2823}
2824#endif
2825
5fafdf24 2826#if !defined(CONFIG_USER_ONLY)
ee5bbe38 2827
d2889a3e
BS		 2828static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
2829 void *retaddr);
2830
ee5bbe38 2831#define MMUSUFFIX _mmu
d2889a3e 2832#define ALIGNED_ONLY
273af660
TS		 2833#ifdef __s390__
2834# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
2835#else
2836# define GETPC() (__builtin_return_address(0))
2837#endif
ee5bbe38
FB		 2838
2839#define SHIFT 0
2840#include "softmmu_template.h"
2841
2842#define SHIFT 1
2843#include "softmmu_template.h"
2844
2845#define SHIFT 2
2846#include "softmmu_template.h"
2847
2848#define SHIFT 3
2849#include "softmmu_template.h"
2850
d2889a3e
BS		 2851static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
2852 void *retaddr)
2853{
94554550
BS		 2854#ifdef DEBUG_UNALIGNED
2855 printf("Unaligned access to 0x%x from 0x%x\n", addr, env->pc);
2856#endif
2857 raise_exception(TT_UNALIGNED);
d2889a3e 2858}
ee5bbe38
FB		 2859
2860/* try to fill the TLB and return an exception if error. If retaddr is
2861 NULL, it means that the function was called in C code (i.e. not
2862 from generated code or from helper.c) */
2863/* XXX: fix it to restore all registers */
6ebbf390 2864void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
ee5bbe38
FB		 2865{
2866 TranslationBlock *tb;
2867 int ret;
2868 unsigned long pc;
2869 CPUState *saved_env;
2870
2871 /* XXX: hack to restore env in all cases, even if not called from
2872 generated code */
2873 saved_env = env;
2874 env = cpu_single_env;
2875
6ebbf390 2876 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ee5bbe38
FB		 2877 if (ret) {
2878 if (retaddr) {
2879 /* now we have a real cpu fault */
2880 pc = (unsigned long)retaddr;
2881 tb = tb_find_pc(pc);
2882 if (tb) {
2883 /* the PC is inside the translated code. It means that we have
2884 a virtual CPU fault */
2885 cpu_restore_state(tb, env, pc, (void *)T2);
2886 }
2887 }
2888 cpu_loop_exit();
2889 }
2890 env = saved_env;
2891}
2892
2893#endif
6c36d3fa
BS		 2894
2895#ifndef TARGET_SPARC64
5dcb6b91 2896void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
6c36d3fa
BS		 2897 int is_asi)
2898{
2899 CPUState *saved_env;
2900
2901 /* XXX: hack to restore env in all cases, even if not called from
2902 generated code */
2903 saved_env = env;
2904 env = cpu_single_env;
8543e2cf
BS		 2905#ifdef DEBUG_UNASSIGNED
2906 if (is_asi)
2907 printf("Unassigned mem %s access to " TARGET_FMT_plx " asi 0x%02x from "
2908 TARGET_FMT_lx "\n",
2909 is_exec ? "exec" : is_write ? "write" : "read", addr, is_asi,
2910 env->pc);
2911 else
2912 printf("Unassigned mem %s access to " TARGET_FMT_plx " from "
2913 TARGET_FMT_lx "\n",
2914 is_exec ? "exec" : is_write ? "write" : "read", addr, env->pc);
2915#endif
6c36d3fa 2916 if (env->mmuregs[3]) /* Fault status register */
0f8a249a 2917 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
6c36d3fa
BS		 2918 if (is_asi)
2919 env->mmuregs[3] |= 1 << 16;
2920 if (env->psrs)
2921 env->mmuregs[3] |= 1 << 5;
2922 if (is_exec)
2923 env->mmuregs[3] |= 1 << 6;
2924 if (is_write)
2925 env->mmuregs[3] |= 1 << 7;
2926 env->mmuregs[3] |= (5 << 2) | 2;
2927 env->mmuregs[4] = addr; /* Fault address register */
2928 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
1b2e93c1
BS		 2929 if (is_exec)
2930 raise_exception(TT_CODE_ACCESS);
2931 else
2932 raise_exception(TT_DATA_ACCESS);
6c36d3fa
BS		 2933 }
2934 env = saved_env;
2935}
2936#else
5dcb6b91 2937void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
6c36d3fa
BS		 2938 int is_asi)
2939{
2940#ifdef DEBUG_UNASSIGNED
2941 CPUState *saved_env;
2942
2943 /* XXX: hack to restore env in all cases, even if not called from
2944 generated code */
2945 saved_env = env;
2946 env = cpu_single_env;
5dcb6b91 2947 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n",
6c36d3fa
BS		 2948 addr, env->pc);
2949 env = saved_env;
2950#endif
1b2e93c1
BS		 2951 if (is_exec)
2952 raise_exception(TT_CODE_ACCESS);
2953 else
2954 raise_exception(TT_DATA_ACCESS);
6c36d3fa
BS		 2955}
2956#endif
20c9f095 2957
Qemu copy for testing