]>
Commit | Line | Data |
---|---|---|
e8af50a3 | 1 | #include "exec.h" |
eed152bb | 2 | #include "host-utils.h" |
1a2fb1c0 | 3 | #include "helper.h" |
e8af50a3 | 4 | |
83469015 | 5 | //#define DEBUG_PCALL |
e80cfcfc | 6 | //#define DEBUG_MMU |
952a328f | 7 | //#define DEBUG_MXCC |
94554550 | 8 | //#define DEBUG_UNALIGNED |
6c36d3fa | 9 | //#define DEBUG_UNASSIGNED |
8543e2cf | 10 | //#define DEBUG_ASI |
e80cfcfc | 11 | |
952a328f BS |
12 | #ifdef DEBUG_MMU |
13 | #define DPRINTF_MMU(fmt, args...) \ | |
14 | do { printf("MMU: " fmt , ##args); } while (0) | |
15 | #else | |
16 | #define DPRINTF_MMU(fmt, args...) | |
17 | #endif | |
18 | ||
19 | #ifdef DEBUG_MXCC | |
20 | #define DPRINTF_MXCC(fmt, args...) \ | |
21 | do { printf("MXCC: " fmt , ##args); } while (0) | |
22 | #else | |
23 | #define DPRINTF_MXCC(fmt, args...) | |
24 | #endif | |
25 | ||
8543e2cf BS |
26 | #ifdef DEBUG_ASI |
27 | #define DPRINTF_ASI(fmt, args...) \ | |
28 | do { printf("ASI: " fmt , ##args); } while (0) | |
29 | #else | |
30 | #define DPRINTF_ASI(fmt, args...) | |
31 | #endif | |
32 | ||
9d893301 FB |
33 | void raise_exception(int tt) |
34 | { | |
35 | env->exception_index = tt; | |
36 | cpu_loop_exit(); | |
3b46e624 | 37 | } |
9d893301 | 38 | |
1a2fb1c0 | 39 | void helper_trap(target_ulong nb_trap) |
417454b0 | 40 | { |
1a2fb1c0 BS |
41 | env->exception_index = TT_TRAP + (nb_trap & 0x7f); |
42 | cpu_loop_exit(); | |
43 | } | |
44 | ||
45 | void helper_trapcc(target_ulong nb_trap, target_ulong do_trap) | |
46 | { | |
47 | if (do_trap) { | |
48 | env->exception_index = TT_TRAP + (nb_trap & 0x7f); | |
49 | cpu_loop_exit(); | |
50 | } | |
51 | } | |
52 | ||
7e8c2b6c | 53 | void helper_check_ieee_exceptions(void) |
1a2fb1c0 BS |
54 | { |
55 | target_ulong status; | |
56 | ||
57 | status = get_float_exception_flags(&env->fp_status); | |
58 | if (status) { | |
0f8a249a | 59 | /* Copy IEEE 754 flags into FSR */ |
1a2fb1c0 | 60 | if (status & float_flag_invalid) |
0f8a249a | 61 | env->fsr |= FSR_NVC; |
1a2fb1c0 | 62 | if (status & float_flag_overflow) |
0f8a249a | 63 | env->fsr |= FSR_OFC; |
1a2fb1c0 | 64 | if (status & float_flag_underflow) |
0f8a249a | 65 | env->fsr |= FSR_UFC; |
1a2fb1c0 | 66 | if (status & float_flag_divbyzero) |
0f8a249a | 67 | env->fsr |= FSR_DZC; |
1a2fb1c0 | 68 | if (status & float_flag_inexact) |
0f8a249a BS |
69 | env->fsr |= FSR_NXC; |
70 | ||
1a2fb1c0 | 71 | if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) { |
0f8a249a BS |
72 | /* Unmasked exception, generate a trap */ |
73 | env->fsr |= FSR_FTT_IEEE_EXCP; | |
74 | raise_exception(TT_FP_EXCP); | |
1a2fb1c0 | 75 | } else { |
0f8a249a BS |
76 | /* Accumulate exceptions */ |
77 | env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5; | |
78 | } | |
1a2fb1c0 | 79 | } |
417454b0 BS |
80 | } |
81 | ||
7e8c2b6c BS |
82 | void helper_clear_float_exceptions(void) |
83 | { | |
84 | set_float_exception_flags(0, &env->fp_status); | |
85 | } | |
86 | ||
a0c4cb4a FB |
87 | #ifdef USE_INT_TO_FLOAT_HELPERS |
88 | void do_fitos(void) | |
89 | { | |
ec230928 | 90 | FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status); |
a0c4cb4a FB |
91 | } |
92 | ||
93 | void do_fitod(void) | |
94 | { | |
ec230928 | 95 | DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status); |
a0c4cb4a | 96 | } |
9c2b428e BS |
97 | |
98 | #if defined(CONFIG_USER_ONLY) | |
99 | void do_fitoq(void) | |
100 | { | |
101 | QT0 = int32_to_float128(*((int32_t *)&FT1), &env->fp_status); | |
102 | } | |
103 | #endif | |
104 | ||
1e64e78d BS |
105 | #ifdef TARGET_SPARC64 |
106 | void do_fxtos(void) | |
107 | { | |
1e64e78d | 108 | FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status); |
1e64e78d BS |
109 | } |
110 | ||
111 | void do_fxtod(void) | |
112 | { | |
1e64e78d | 113 | DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status); |
1e64e78d | 114 | } |
9c2b428e BS |
115 | |
116 | #if defined(CONFIG_USER_ONLY) | |
117 | void do_fxtoq(void) | |
118 | { | |
9c2b428e | 119 | QT0 = int64_to_float128(*((int32_t *)&DT1), &env->fp_status); |
9c2b428e BS |
120 | } |
121 | #endif | |
1e64e78d | 122 | #endif |
a0c4cb4a FB |
123 | #endif |
124 | ||
7e8c2b6c | 125 | void helper_fabss(void) |
e8af50a3 | 126 | { |
7a0e1f41 | 127 | FT0 = float32_abs(FT1); |
e8af50a3 FB |
128 | } |
129 | ||
3475187d | 130 | #ifdef TARGET_SPARC64 |
7e8c2b6c | 131 | void helper_fabsd(void) |
3475187d FB |
132 | { |
133 | DT0 = float64_abs(DT1); | |
134 | } | |
1f587329 BS |
135 | |
136 | #if defined(CONFIG_USER_ONLY) | |
7e8c2b6c | 137 | void helper_fabsq(void) |
1f587329 BS |
138 | { |
139 | QT0 = float128_abs(QT1); | |
140 | } | |
141 | #endif | |
3475187d FB |
142 | #endif |
143 | ||
7e8c2b6c | 144 | void helper_fsqrts(void) |
e8af50a3 | 145 | { |
7a0e1f41 | 146 | FT0 = float32_sqrt(FT1, &env->fp_status); |
e8af50a3 FB |
147 | } |
148 | ||
7e8c2b6c | 149 | void helper_fsqrtd(void) |
e8af50a3 | 150 | { |
7a0e1f41 | 151 | DT0 = float64_sqrt(DT1, &env->fp_status); |
e8af50a3 FB |
152 | } |
153 | ||
1f587329 | 154 | #if defined(CONFIG_USER_ONLY) |
7e8c2b6c | 155 | void helper_fsqrtq(void) |
1f587329 | 156 | { |
1f587329 | 157 | QT0 = float128_sqrt(QT1, &env->fp_status); |
1f587329 BS |
158 | } |
159 | #endif | |
160 | ||
417454b0 | 161 | #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \ |
7e8c2b6c | 162 | void glue(helper_, name) (void) \ |
65ce8c2f | 163 | { \ |
1a2fb1c0 BS |
164 | target_ulong new_fsr; \ |
165 | \ | |
65ce8c2f FB |
166 | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
167 | switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \ | |
168 | case float_relation_unordered: \ | |
1a2fb1c0 | 169 | new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \ |
417454b0 | 170 | if ((env->fsr & FSR_NVM) || TRAP) { \ |
1a2fb1c0 | 171 | env->fsr |= new_fsr; \ |
417454b0 BS |
172 | env->fsr |= FSR_NVC; \ |
173 | env->fsr |= FSR_FTT_IEEE_EXCP; \ | |
65ce8c2f FB |
174 | raise_exception(TT_FP_EXCP); \ |
175 | } else { \ | |
176 | env->fsr |= FSR_NVA; \ | |
177 | } \ | |
178 | break; \ | |
179 | case float_relation_less: \ | |
1a2fb1c0 | 180 | new_fsr = FSR_FCC0 << FS; \ |
65ce8c2f FB |
181 | break; \ |
182 | case float_relation_greater: \ | |
1a2fb1c0 | 183 | new_fsr = FSR_FCC1 << FS; \ |
65ce8c2f FB |
184 | break; \ |
185 | default: \ | |
1a2fb1c0 | 186 | new_fsr = 0; \ |
65ce8c2f FB |
187 | break; \ |
188 | } \ | |
1a2fb1c0 | 189 | env->fsr |= new_fsr; \ |
e8af50a3 | 190 | } |
e8af50a3 | 191 | |
417454b0 BS |
192 | GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0); |
193 | GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0); | |
194 | ||
195 | GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1); | |
196 | GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1); | |
3475187d | 197 | |
1f587329 BS |
198 | #ifdef CONFIG_USER_ONLY |
199 | GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0); | |
200 | GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1); | |
201 | #endif | |
202 | ||
3475187d | 203 | #ifdef TARGET_SPARC64 |
417454b0 BS |
204 | GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0); |
205 | GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0); | |
206 | ||
207 | GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0); | |
208 | GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0); | |
209 | ||
210 | GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0); | |
211 | GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0); | |
212 | ||
213 | GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1); | |
214 | GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1); | |
3475187d | 215 | |
417454b0 BS |
216 | GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1); |
217 | GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1); | |
3475187d | 218 | |
417454b0 BS |
219 | GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1); |
220 | GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1); | |
1f587329 BS |
221 | #ifdef CONFIG_USER_ONLY |
222 | GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0); | |
223 | GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0); | |
224 | GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0); | |
225 | GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1); | |
226 | GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1); | |
227 | GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1); | |
228 | #endif | |
3475187d FB |
229 | #endif |
230 | ||
1a2fb1c0 | 231 | #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && defined(DEBUG_MXCC) |
952a328f BS |
232 | static void dump_mxcc(CPUState *env) |
233 | { | |
234 | printf("mxccdata: %016llx %016llx %016llx %016llx\n", | |
235 | env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]); | |
236 | printf("mxccregs: %016llx %016llx %016llx %016llx\n" | |
237 | " %016llx %016llx %016llx %016llx\n", | |
238 | env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3], | |
239 | env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]); | |
240 | } | |
241 | #endif | |
242 | ||
1a2fb1c0 BS |
243 | #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \ |
244 | && defined(DEBUG_ASI) | |
245 | static void dump_asi(const char *txt, target_ulong addr, int asi, int size, | |
246 | uint64_t r1) | |
8543e2cf BS |
247 | { |
248 | switch (size) | |
249 | { | |
250 | case 1: | |
1a2fb1c0 BS |
251 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt, |
252 | addr, asi, r1 & 0xff); | |
8543e2cf BS |
253 | break; |
254 | case 2: | |
1a2fb1c0 BS |
255 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt, |
256 | addr, asi, r1 & 0xffff); | |
8543e2cf BS |
257 | break; |
258 | case 4: | |
1a2fb1c0 BS |
259 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt, |
260 | addr, asi, r1 & 0xffffffff); | |
8543e2cf BS |
261 | break; |
262 | case 8: | |
1a2fb1c0 BS |
263 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt, |
264 | addr, asi, r1); | |
8543e2cf BS |
265 | break; |
266 | } | |
267 | } | |
268 | #endif | |
269 | ||
1a2fb1c0 BS |
270 | #ifndef TARGET_SPARC64 |
271 | #ifndef CONFIG_USER_ONLY | |
272 | uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) | |
e8af50a3 | 273 | { |
1a2fb1c0 | 274 | uint64_t ret = 0; |
8543e2cf | 275 | #if defined(DEBUG_MXCC) || defined(DEBUG_ASI) |
1a2fb1c0 | 276 | uint32_t last_addr = addr; |
952a328f | 277 | #endif |
e80cfcfc FB |
278 | |
279 | switch (asi) { | |
6c36d3fa | 280 | case 2: /* SuperSparc MXCC registers */ |
1a2fb1c0 | 281 | switch (addr) { |
952a328f | 282 | case 0x01c00a00: /* MXCC control register */ |
1a2fb1c0 BS |
283 | if (size == 8) |
284 | ret = env->mxccregs[3]; | |
285 | else | |
286 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); | |
952a328f BS |
287 | break; |
288 | case 0x01c00a04: /* MXCC control register */ | |
289 | if (size == 4) | |
290 | ret = env->mxccregs[3]; | |
291 | else | |
1a2fb1c0 | 292 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); |
952a328f | 293 | break; |
295db113 BS |
294 | case 0x01c00c00: /* Module reset register */ |
295 | if (size == 8) { | |
1a2fb1c0 | 296 | ret = env->mxccregs[5]; |
295db113 BS |
297 | // should we do something here? |
298 | } else | |
1a2fb1c0 | 299 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); |
295db113 | 300 | break; |
952a328f | 301 | case 0x01c00f00: /* MBus port address register */ |
1a2fb1c0 BS |
302 | if (size == 8) |
303 | ret = env->mxccregs[7]; | |
304 | else | |
305 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); | |
952a328f BS |
306 | break; |
307 | default: | |
1a2fb1c0 | 308 | DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size); |
952a328f BS |
309 | break; |
310 | } | |
1a2fb1c0 BS |
311 | DPRINTF_MXCC("asi = %d, size = %d, sign = %d, addr = %08x -> ret = %08x," |
312 | "addr = %08x\n", asi, size, sign, last_addr, ret, addr); | |
952a328f BS |
313 | #ifdef DEBUG_MXCC |
314 | dump_mxcc(env); | |
315 | #endif | |
6c36d3fa | 316 | break; |
e8af50a3 | 317 | case 3: /* MMU probe */ |
0f8a249a BS |
318 | { |
319 | int mmulev; | |
320 | ||
1a2fb1c0 | 321 | mmulev = (addr >> 8) & 15; |
0f8a249a BS |
322 | if (mmulev > 4) |
323 | ret = 0; | |
1a2fb1c0 BS |
324 | else |
325 | ret = mmu_probe(env, addr, mmulev); | |
326 | DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n", | |
327 | addr, mmulev, ret); | |
0f8a249a BS |
328 | } |
329 | break; | |
e8af50a3 | 330 | case 4: /* read MMU regs */ |
0f8a249a | 331 | { |
1a2fb1c0 | 332 | int reg = (addr >> 8) & 0x1f; |
3b46e624 | 333 | |
0f8a249a BS |
334 | ret = env->mmuregs[reg]; |
335 | if (reg == 3) /* Fault status cleared on read */ | |
3dd9a152 BS |
336 | env->mmuregs[3] = 0; |
337 | else if (reg == 0x13) /* Fault status read */ | |
338 | ret = env->mmuregs[3]; | |
339 | else if (reg == 0x14) /* Fault address read */ | |
340 | ret = env->mmuregs[4]; | |
1a2fb1c0 | 341 | DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret); |
0f8a249a BS |
342 | } |
343 | break; | |
045380be BS |
344 | case 5: // Turbosparc ITLB Diagnostic |
345 | case 6: // Turbosparc DTLB Diagnostic | |
346 | case 7: // Turbosparc IOTLB Diagnostic | |
347 | break; | |
6c36d3fa BS |
348 | case 9: /* Supervisor code access */ |
349 | switch(size) { | |
350 | case 1: | |
1a2fb1c0 | 351 | ret = ldub_code(addr); |
6c36d3fa BS |
352 | break; |
353 | case 2: | |
1a2fb1c0 | 354 | ret = lduw_code(addr & ~1); |
6c36d3fa BS |
355 | break; |
356 | default: | |
357 | case 4: | |
1a2fb1c0 | 358 | ret = ldl_code(addr & ~3); |
6c36d3fa BS |
359 | break; |
360 | case 8: | |
1a2fb1c0 | 361 | ret = ldq_code(addr & ~7); |
6c36d3fa BS |
362 | break; |
363 | } | |
364 | break; | |
81ad8ba2 BS |
365 | case 0xa: /* User data access */ |
366 | switch(size) { | |
367 | case 1: | |
1a2fb1c0 | 368 | ret = ldub_user(addr); |
81ad8ba2 BS |
369 | break; |
370 | case 2: | |
1a2fb1c0 | 371 | ret = lduw_user(addr & ~1); |
81ad8ba2 BS |
372 | break; |
373 | default: | |
374 | case 4: | |
1a2fb1c0 | 375 | ret = ldl_user(addr & ~3); |
81ad8ba2 BS |
376 | break; |
377 | case 8: | |
1a2fb1c0 | 378 | ret = ldq_user(addr & ~7); |
81ad8ba2 BS |
379 | break; |
380 | } | |
381 | break; | |
382 | case 0xb: /* Supervisor data access */ | |
383 | switch(size) { | |
384 | case 1: | |
1a2fb1c0 | 385 | ret = ldub_kernel(addr); |
81ad8ba2 BS |
386 | break; |
387 | case 2: | |
1a2fb1c0 | 388 | ret = lduw_kernel(addr & ~1); |
81ad8ba2 BS |
389 | break; |
390 | default: | |
391 | case 4: | |
1a2fb1c0 | 392 | ret = ldl_kernel(addr & ~3); |
81ad8ba2 BS |
393 | break; |
394 | case 8: | |
1a2fb1c0 | 395 | ret = ldq_kernel(addr & ~7); |
81ad8ba2 BS |
396 | break; |
397 | } | |
398 | break; | |
6c36d3fa BS |
399 | case 0xc: /* I-cache tag */ |
400 | case 0xd: /* I-cache data */ | |
401 | case 0xe: /* D-cache tag */ | |
402 | case 0xf: /* D-cache data */ | |
403 | break; | |
404 | case 0x20: /* MMU passthrough */ | |
02aab46a FB |
405 | switch(size) { |
406 | case 1: | |
1a2fb1c0 | 407 | ret = ldub_phys(addr); |
02aab46a FB |
408 | break; |
409 | case 2: | |
1a2fb1c0 | 410 | ret = lduw_phys(addr & ~1); |
02aab46a FB |
411 | break; |
412 | default: | |
413 | case 4: | |
1a2fb1c0 | 414 | ret = ldl_phys(addr & ~3); |
02aab46a | 415 | break; |
9e61bde5 | 416 | case 8: |
1a2fb1c0 | 417 | ret = ldq_phys(addr & ~7); |
0f8a249a | 418 | break; |
02aab46a | 419 | } |
0f8a249a | 420 | break; |
7d85892b | 421 | case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ |
5dcb6b91 BS |
422 | switch(size) { |
423 | case 1: | |
1a2fb1c0 | 424 | ret = ldub_phys((target_phys_addr_t)addr |
5dcb6b91 BS |
425 | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
426 | break; | |
427 | case 2: | |
1a2fb1c0 | 428 | ret = lduw_phys((target_phys_addr_t)(addr & ~1) |
5dcb6b91 BS |
429 | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
430 | break; | |
431 | default: | |
432 | case 4: | |
1a2fb1c0 | 433 | ret = ldl_phys((target_phys_addr_t)(addr & ~3) |
5dcb6b91 BS |
434 | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
435 | break; | |
436 | case 8: | |
1a2fb1c0 | 437 | ret = ldq_phys((target_phys_addr_t)(addr & ~7) |
5dcb6b91 | 438 | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
0f8a249a | 439 | break; |
5dcb6b91 | 440 | } |
0f8a249a | 441 | break; |
045380be BS |
442 | case 0x30: // Turbosparc secondary cache diagnostic |
443 | case 0x31: // Turbosparc RAM snoop | |
444 | case 0x32: // Turbosparc page table descriptor diagnostic | |
666c87aa BS |
445 | case 0x39: /* data cache diagnostic register */ |
446 | ret = 0; | |
447 | break; | |
045380be | 448 | case 8: /* User code access, XXX */ |
e8af50a3 | 449 | default: |
1a2fb1c0 | 450 | do_unassigned_access(addr, 0, 0, asi); |
0f8a249a BS |
451 | ret = 0; |
452 | break; | |
e8af50a3 | 453 | } |
81ad8ba2 BS |
454 | if (sign) { |
455 | switch(size) { | |
456 | case 1: | |
1a2fb1c0 | 457 | ret = (int8_t) ret; |
e32664fb | 458 | break; |
81ad8ba2 | 459 | case 2: |
1a2fb1c0 BS |
460 | ret = (int16_t) ret; |
461 | break; | |
462 | case 4: | |
463 | ret = (int32_t) ret; | |
e32664fb | 464 | break; |
81ad8ba2 | 465 | default: |
81ad8ba2 BS |
466 | break; |
467 | } | |
468 | } | |
8543e2cf | 469 | #ifdef DEBUG_ASI |
1a2fb1c0 | 470 | dump_asi("read ", last_addr, asi, size, ret); |
8543e2cf | 471 | #endif |
1a2fb1c0 | 472 | return ret; |
e8af50a3 FB |
473 | } |
474 | ||
1a2fb1c0 | 475 | void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size) |
e8af50a3 FB |
476 | { |
477 | switch(asi) { | |
6c36d3fa | 478 | case 2: /* SuperSparc MXCC registers */ |
1a2fb1c0 | 479 | switch (addr) { |
952a328f BS |
480 | case 0x01c00000: /* MXCC stream data register 0 */ |
481 | if (size == 8) | |
1a2fb1c0 | 482 | env->mxccdata[0] = val; |
952a328f | 483 | else |
1a2fb1c0 | 484 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); |
952a328f BS |
485 | break; |
486 | case 0x01c00008: /* MXCC stream data register 1 */ | |
487 | if (size == 8) | |
1a2fb1c0 | 488 | env->mxccdata[1] = val; |
952a328f | 489 | else |
1a2fb1c0 | 490 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); |
952a328f BS |
491 | break; |
492 | case 0x01c00010: /* MXCC stream data register 2 */ | |
493 | if (size == 8) | |
1a2fb1c0 | 494 | env->mxccdata[2] = val; |
952a328f | 495 | else |
1a2fb1c0 | 496 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); |
952a328f BS |
497 | break; |
498 | case 0x01c00018: /* MXCC stream data register 3 */ | |
499 | if (size == 8) | |
1a2fb1c0 | 500 | env->mxccdata[3] = val; |
952a328f | 501 | else |
1a2fb1c0 | 502 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); |
952a328f BS |
503 | break; |
504 | case 0x01c00100: /* MXCC stream source */ | |
505 | if (size == 8) | |
1a2fb1c0 | 506 | env->mxccregs[0] = val; |
952a328f | 507 | else |
1a2fb1c0 | 508 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); |
952a328f BS |
509 | env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0); |
510 | env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8); | |
511 | env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16); | |
512 | env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 24); | |
513 | break; | |
514 | case 0x01c00200: /* MXCC stream destination */ | |
515 | if (size == 8) | |
1a2fb1c0 | 516 | env->mxccregs[1] = val; |
952a328f | 517 | else |
1a2fb1c0 | 518 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); |
952a328f BS |
519 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]); |
520 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]); | |
521 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]); | |
522 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, env->mxccdata[3]); | |
523 | break; | |
524 | case 0x01c00a00: /* MXCC control register */ | |
525 | if (size == 8) | |
1a2fb1c0 | 526 | env->mxccregs[3] = val; |
952a328f | 527 | else |
1a2fb1c0 | 528 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); |
952a328f BS |
529 | break; |
530 | case 0x01c00a04: /* MXCC control register */ | |
531 | if (size == 4) | |
1a2fb1c0 | 532 | env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) | val; |
952a328f | 533 | else |
1a2fb1c0 | 534 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); |
952a328f BS |
535 | break; |
536 | case 0x01c00e00: /* MXCC error register */ | |
bbf7d96b | 537 | // writing a 1 bit clears the error |
952a328f | 538 | if (size == 8) |
1a2fb1c0 | 539 | env->mxccregs[6] &= ~val; |
952a328f | 540 | else |
1a2fb1c0 | 541 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); |
952a328f BS |
542 | break; |
543 | case 0x01c00f00: /* MBus port address register */ | |
544 | if (size == 8) | |
1a2fb1c0 | 545 | env->mxccregs[7] = val; |
952a328f | 546 | else |
1a2fb1c0 | 547 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size); |
952a328f BS |
548 | break; |
549 | default: | |
1a2fb1c0 | 550 | DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size); |
952a328f BS |
551 | break; |
552 | } | |
1a2fb1c0 | 553 | DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi, size, addr, val); |
952a328f BS |
554 | #ifdef DEBUG_MXCC |
555 | dump_mxcc(env); | |
556 | #endif | |
6c36d3fa | 557 | break; |
e8af50a3 | 558 | case 3: /* MMU flush */ |
0f8a249a BS |
559 | { |
560 | int mmulev; | |
e80cfcfc | 561 | |
1a2fb1c0 | 562 | mmulev = (addr >> 8) & 15; |
952a328f | 563 | DPRINTF_MMU("mmu flush level %d\n", mmulev); |
0f8a249a BS |
564 | switch (mmulev) { |
565 | case 0: // flush page | |
1a2fb1c0 | 566 | tlb_flush_page(env, addr & 0xfffff000); |
0f8a249a BS |
567 | break; |
568 | case 1: // flush segment (256k) | |
569 | case 2: // flush region (16M) | |
570 | case 3: // flush context (4G) | |
571 | case 4: // flush entire | |
572 | tlb_flush(env, 1); | |
573 | break; | |
574 | default: | |
575 | break; | |
576 | } | |
55754d9e | 577 | #ifdef DEBUG_MMU |
0f8a249a | 578 | dump_mmu(env); |
55754d9e | 579 | #endif |
0f8a249a | 580 | } |
8543e2cf | 581 | break; |
e8af50a3 | 582 | case 4: /* write MMU regs */ |
0f8a249a | 583 | { |
1a2fb1c0 | 584 | int reg = (addr >> 8) & 0x1f; |
0f8a249a | 585 | uint32_t oldreg; |
3b46e624 | 586 | |
0f8a249a | 587 | oldreg = env->mmuregs[reg]; |
55754d9e | 588 | switch(reg) { |
3deaeab7 | 589 | case 0: // Control Register |
3dd9a152 | 590 | env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) | |
1a2fb1c0 | 591 | (val & 0x00ffffff); |
0f8a249a BS |
592 | // Mappings generated during no-fault mode or MMU |
593 | // disabled mode are invalid in normal mode | |
3dd9a152 BS |
594 | if ((oldreg & (MMU_E | MMU_NF | env->mmu_bm)) != |
595 | (env->mmuregs[reg] & (MMU_E | MMU_NF | env->mmu_bm))) | |
55754d9e FB |
596 | tlb_flush(env, 1); |
597 | break; | |
3deaeab7 | 598 | case 1: // Context Table Pointer Register |
1a2fb1c0 | 599 | env->mmuregs[reg] = val & env->mmu_ctpr_mask; |
3deaeab7 BS |
600 | break; |
601 | case 2: // Context Register | |
1a2fb1c0 | 602 | env->mmuregs[reg] = val & env->mmu_cxr_mask; |
55754d9e FB |
603 | if (oldreg != env->mmuregs[reg]) { |
604 | /* we flush when the MMU context changes because | |
605 | QEMU has no MMU context support */ | |
606 | tlb_flush(env, 1); | |
607 | } | |
608 | break; | |
3deaeab7 BS |
609 | case 3: // Synchronous Fault Status Register with Clear |
610 | case 4: // Synchronous Fault Address Register | |
611 | break; | |
612 | case 0x10: // TLB Replacement Control Register | |
1a2fb1c0 | 613 | env->mmuregs[reg] = val & env->mmu_trcr_mask; |
55754d9e | 614 | break; |
3deaeab7 | 615 | case 0x13: // Synchronous Fault Status Register with Read and Clear |
1a2fb1c0 | 616 | env->mmuregs[3] = val & env->mmu_sfsr_mask; |
3dd9a152 | 617 | break; |
3deaeab7 | 618 | case 0x14: // Synchronous Fault Address Register |
1a2fb1c0 | 619 | env->mmuregs[4] = val; |
3dd9a152 | 620 | break; |
55754d9e | 621 | default: |
1a2fb1c0 | 622 | env->mmuregs[reg] = val; |
55754d9e FB |
623 | break; |
624 | } | |
55754d9e | 625 | if (oldreg != env->mmuregs[reg]) { |
952a328f | 626 | DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]); |
55754d9e | 627 | } |
952a328f | 628 | #ifdef DEBUG_MMU |
0f8a249a | 629 | dump_mmu(env); |
55754d9e | 630 | #endif |
0f8a249a | 631 | } |
8543e2cf | 632 | break; |
045380be BS |
633 | case 5: // Turbosparc ITLB Diagnostic |
634 | case 6: // Turbosparc DTLB Diagnostic | |
635 | case 7: // Turbosparc IOTLB Diagnostic | |
636 | break; | |
81ad8ba2 BS |
637 | case 0xa: /* User data access */ |
638 | switch(size) { | |
639 | case 1: | |
1a2fb1c0 | 640 | stb_user(addr, val); |
81ad8ba2 BS |
641 | break; |
642 | case 2: | |
1a2fb1c0 | 643 | stw_user(addr & ~1, val); |
81ad8ba2 BS |
644 | break; |
645 | default: | |
646 | case 4: | |
1a2fb1c0 | 647 | stl_user(addr & ~3, val); |
81ad8ba2 BS |
648 | break; |
649 | case 8: | |
1a2fb1c0 | 650 | stq_user(addr & ~7, val); |
81ad8ba2 BS |
651 | break; |
652 | } | |
653 | break; | |
654 | case 0xb: /* Supervisor data access */ | |
655 | switch(size) { | |
656 | case 1: | |
1a2fb1c0 | 657 | stb_kernel(addr, val); |
81ad8ba2 BS |
658 | break; |
659 | case 2: | |
1a2fb1c0 | 660 | stw_kernel(addr & ~1, val); |
81ad8ba2 BS |
661 | break; |
662 | default: | |
663 | case 4: | |
1a2fb1c0 | 664 | stl_kernel(addr & ~3, val); |
81ad8ba2 BS |
665 | break; |
666 | case 8: | |
1a2fb1c0 | 667 | stq_kernel(addr & ~7, val); |
81ad8ba2 BS |
668 | break; |
669 | } | |
670 | break; | |
6c36d3fa BS |
671 | case 0xc: /* I-cache tag */ |
672 | case 0xd: /* I-cache data */ | |
673 | case 0xe: /* D-cache tag */ | |
674 | case 0xf: /* D-cache data */ | |
675 | case 0x10: /* I/D-cache flush page */ | |
676 | case 0x11: /* I/D-cache flush segment */ | |
677 | case 0x12: /* I/D-cache flush region */ | |
678 | case 0x13: /* I/D-cache flush context */ | |
679 | case 0x14: /* I/D-cache flush user */ | |
680 | break; | |
e80cfcfc | 681 | case 0x17: /* Block copy, sta access */ |
0f8a249a | 682 | { |
1a2fb1c0 BS |
683 | // val = src |
684 | // addr = dst | |
0f8a249a | 685 | // copy 32 bytes |
6c36d3fa | 686 | unsigned int i; |
1a2fb1c0 | 687 | uint32_t src = val & ~3, dst = addr & ~3, temp; |
3b46e624 | 688 | |
6c36d3fa BS |
689 | for (i = 0; i < 32; i += 4, src += 4, dst += 4) { |
690 | temp = ldl_kernel(src); | |
691 | stl_kernel(dst, temp); | |
692 | } | |
0f8a249a | 693 | } |
8543e2cf | 694 | break; |
e80cfcfc | 695 | case 0x1f: /* Block fill, stda access */ |
0f8a249a | 696 | { |
1a2fb1c0 BS |
697 | // addr = dst |
698 | // fill 32 bytes with val | |
6c36d3fa | 699 | unsigned int i; |
1a2fb1c0 | 700 | uint32_t dst = addr & 7; |
6c36d3fa BS |
701 | |
702 | for (i = 0; i < 32; i += 8, dst += 8) | |
703 | stq_kernel(dst, val); | |
0f8a249a | 704 | } |
8543e2cf | 705 | break; |
6c36d3fa | 706 | case 0x20: /* MMU passthrough */ |
0f8a249a | 707 | { |
02aab46a FB |
708 | switch(size) { |
709 | case 1: | |
1a2fb1c0 | 710 | stb_phys(addr, val); |
02aab46a FB |
711 | break; |
712 | case 2: | |
1a2fb1c0 | 713 | stw_phys(addr & ~1, val); |
02aab46a FB |
714 | break; |
715 | case 4: | |
716 | default: | |
1a2fb1c0 | 717 | stl_phys(addr & ~3, val); |
02aab46a | 718 | break; |
9e61bde5 | 719 | case 8: |
1a2fb1c0 | 720 | stq_phys(addr & ~7, val); |
9e61bde5 | 721 | break; |
02aab46a | 722 | } |
0f8a249a | 723 | } |
8543e2cf | 724 | break; |
045380be | 725 | case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ |
0f8a249a | 726 | { |
5dcb6b91 BS |
727 | switch(size) { |
728 | case 1: | |
1a2fb1c0 BS |
729 | stb_phys((target_phys_addr_t)addr |
730 | | ((target_phys_addr_t)(asi & 0xf) << 32), val); | |
5dcb6b91 BS |
731 | break; |
732 | case 2: | |
1a2fb1c0 BS |
733 | stw_phys((target_phys_addr_t)(addr & ~1) |
734 | | ((target_phys_addr_t)(asi & 0xf) << 32), val); | |
5dcb6b91 BS |
735 | break; |
736 | case 4: | |
737 | default: | |
1a2fb1c0 BS |
738 | stl_phys((target_phys_addr_t)(addr & ~3) |
739 | | ((target_phys_addr_t)(asi & 0xf) << 32), val); | |
5dcb6b91 BS |
740 | break; |
741 | case 8: | |
1a2fb1c0 BS |
742 | stq_phys((target_phys_addr_t)(addr & ~7) |
743 | | ((target_phys_addr_t)(asi & 0xf) << 32), val); | |
5dcb6b91 BS |
744 | break; |
745 | } | |
0f8a249a | 746 | } |
8543e2cf | 747 | break; |
045380be BS |
748 | case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic |
749 | case 0x31: // store buffer data, Ross RT620 I-cache flush or | |
750 | // Turbosparc snoop RAM | |
751 | case 0x32: // store buffer control or Turbosparc page table descriptor diagnostic | |
6c36d3fa BS |
752 | case 0x36: /* I-cache flash clear */ |
753 | case 0x37: /* D-cache flash clear */ | |
666c87aa BS |
754 | case 0x38: /* breakpoint diagnostics */ |
755 | case 0x4c: /* breakpoint action */ | |
6c36d3fa | 756 | break; |
045380be | 757 | case 8: /* User code access, XXX */ |
6c36d3fa | 758 | case 9: /* Supervisor code access, XXX */ |
e8af50a3 | 759 | default: |
1a2fb1c0 | 760 | do_unassigned_access(addr, 1, 0, asi); |
8543e2cf | 761 | break; |
e8af50a3 | 762 | } |
8543e2cf | 763 | #ifdef DEBUG_ASI |
1a2fb1c0 | 764 | dump_asi("write", addr, asi, size, val); |
8543e2cf | 765 | #endif |
e8af50a3 FB |
766 | } |
767 | ||
81ad8ba2 BS |
768 | #endif /* CONFIG_USER_ONLY */ |
769 | #else /* TARGET_SPARC64 */ | |
770 | ||
771 | #ifdef CONFIG_USER_ONLY | |
1a2fb1c0 | 772 | uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
81ad8ba2 BS |
773 | { |
774 | uint64_t ret = 0; | |
1a2fb1c0 BS |
775 | #if defined(DEBUG_ASI) |
776 | target_ulong last_addr = addr; | |
777 | #endif | |
81ad8ba2 BS |
778 | |
779 | if (asi < 0x80) | |
780 | raise_exception(TT_PRIV_ACT); | |
781 | ||
782 | switch (asi) { | |
783 | case 0x80: // Primary | |
784 | case 0x82: // Primary no-fault | |
785 | case 0x88: // Primary LE | |
786 | case 0x8a: // Primary no-fault LE | |
787 | { | |
788 | switch(size) { | |
789 | case 1: | |
1a2fb1c0 | 790 | ret = ldub_raw(addr); |
81ad8ba2 BS |
791 | break; |
792 | case 2: | |
1a2fb1c0 | 793 | ret = lduw_raw(addr & ~1); |
81ad8ba2 BS |
794 | break; |
795 | case 4: | |
1a2fb1c0 | 796 | ret = ldl_raw(addr & ~3); |
81ad8ba2 BS |
797 | break; |
798 | default: | |
799 | case 8: | |
1a2fb1c0 | 800 | ret = ldq_raw(addr & ~7); |
81ad8ba2 BS |
801 | break; |
802 | } | |
803 | } | |
804 | break; | |
805 | case 0x81: // Secondary | |
806 | case 0x83: // Secondary no-fault | |
807 | case 0x89: // Secondary LE | |
808 | case 0x8b: // Secondary no-fault LE | |
809 | // XXX | |
810 | break; | |
811 | default: | |
812 | break; | |
813 | } | |
814 | ||
815 | /* Convert from little endian */ | |
816 | switch (asi) { | |
817 | case 0x88: // Primary LE | |
818 | case 0x89: // Secondary LE | |
819 | case 0x8a: // Primary no-fault LE | |
820 | case 0x8b: // Secondary no-fault LE | |
821 | switch(size) { | |
822 | case 2: | |
823 | ret = bswap16(ret); | |
e32664fb | 824 | break; |
81ad8ba2 BS |
825 | case 4: |
826 | ret = bswap32(ret); | |
e32664fb | 827 | break; |
81ad8ba2 BS |
828 | case 8: |
829 | ret = bswap64(ret); | |
e32664fb | 830 | break; |
81ad8ba2 BS |
831 | default: |
832 | break; | |
833 | } | |
834 | default: | |
835 | break; | |
836 | } | |
837 | ||
838 | /* Convert to signed number */ | |
839 | if (sign) { | |
840 | switch(size) { | |
841 | case 1: | |
842 | ret = (int8_t) ret; | |
e32664fb | 843 | break; |
81ad8ba2 BS |
844 | case 2: |
845 | ret = (int16_t) ret; | |
e32664fb | 846 | break; |
81ad8ba2 BS |
847 | case 4: |
848 | ret = (int32_t) ret; | |
e32664fb | 849 | break; |
81ad8ba2 BS |
850 | default: |
851 | break; | |
852 | } | |
853 | } | |
1a2fb1c0 BS |
854 | #ifdef DEBUG_ASI |
855 | dump_asi("read ", last_addr, asi, size, ret); | |
856 | #endif | |
857 | return ret; | |
81ad8ba2 BS |
858 | } |
859 | ||
1a2fb1c0 | 860 | void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) |
81ad8ba2 | 861 | { |
1a2fb1c0 BS |
862 | #ifdef DEBUG_ASI |
863 | dump_asi("write", addr, asi, size, val); | |
864 | #endif | |
81ad8ba2 BS |
865 | if (asi < 0x80) |
866 | raise_exception(TT_PRIV_ACT); | |
867 | ||
868 | /* Convert to little endian */ | |
869 | switch (asi) { | |
870 | case 0x88: // Primary LE | |
871 | case 0x89: // Secondary LE | |
872 | switch(size) { | |
873 | case 2: | |
1a2fb1c0 | 874 | addr = bswap16(addr); |
e32664fb | 875 | break; |
81ad8ba2 | 876 | case 4: |
1a2fb1c0 | 877 | addr = bswap32(addr); |
e32664fb | 878 | break; |
81ad8ba2 | 879 | case 8: |
1a2fb1c0 | 880 | addr = bswap64(addr); |
e32664fb | 881 | break; |
81ad8ba2 BS |
882 | default: |
883 | break; | |
884 | } | |
885 | default: | |
886 | break; | |
887 | } | |
888 | ||
889 | switch(asi) { | |
890 | case 0x80: // Primary | |
891 | case 0x88: // Primary LE | |
892 | { | |
893 | switch(size) { | |
894 | case 1: | |
1a2fb1c0 | 895 | stb_raw(addr, val); |
81ad8ba2 BS |
896 | break; |
897 | case 2: | |
1a2fb1c0 | 898 | stw_raw(addr & ~1, val); |
81ad8ba2 BS |
899 | break; |
900 | case 4: | |
1a2fb1c0 | 901 | stl_raw(addr & ~3, val); |
81ad8ba2 BS |
902 | break; |
903 | case 8: | |
904 | default: | |
1a2fb1c0 | 905 | stq_raw(addr & ~7, val); |
81ad8ba2 BS |
906 | break; |
907 | } | |
908 | } | |
909 | break; | |
910 | case 0x81: // Secondary | |
911 | case 0x89: // Secondary LE | |
912 | // XXX | |
913 | return; | |
914 | ||
915 | case 0x82: // Primary no-fault, RO | |
916 | case 0x83: // Secondary no-fault, RO | |
917 | case 0x8a: // Primary no-fault LE, RO | |
918 | case 0x8b: // Secondary no-fault LE, RO | |
919 | default: | |
1a2fb1c0 | 920 | do_unassigned_access(addr, 1, 0, 1); |
81ad8ba2 BS |
921 | return; |
922 | } | |
923 | } | |
924 | ||
925 | #else /* CONFIG_USER_ONLY */ | |
3475187d | 926 | |
1a2fb1c0 | 927 | uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
3475187d | 928 | { |
83469015 | 929 | uint64_t ret = 0; |
1a2fb1c0 BS |
930 | #if defined(DEBUG_ASI) |
931 | target_ulong last_addr = addr; | |
932 | #endif | |
3475187d | 933 | |
6f27aba6 | 934 | if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
20b749f6 | 935 | || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV))) |
0f8a249a | 936 | raise_exception(TT_PRIV_ACT); |
3475187d FB |
937 | |
938 | switch (asi) { | |
81ad8ba2 BS |
939 | case 0x10: // As if user primary |
940 | case 0x18: // As if user primary LE | |
941 | case 0x80: // Primary | |
942 | case 0x82: // Primary no-fault | |
943 | case 0x88: // Primary LE | |
944 | case 0x8a: // Primary no-fault LE | |
945 | if ((asi & 0x80) && (env->pstate & PS_PRIV)) { | |
6f27aba6 BS |
946 | if (env->hpstate & HS_PRIV) { |
947 | switch(size) { | |
948 | case 1: | |
1a2fb1c0 | 949 | ret = ldub_hypv(addr); |
6f27aba6 BS |
950 | break; |
951 | case 2: | |
1a2fb1c0 | 952 | ret = lduw_hypv(addr & ~1); |
6f27aba6 BS |
953 | break; |
954 | case 4: | |
1a2fb1c0 | 955 | ret = ldl_hypv(addr & ~3); |
6f27aba6 BS |
956 | break; |
957 | default: | |
958 | case 8: | |
1a2fb1c0 | 959 | ret = ldq_hypv(addr & ~7); |
6f27aba6 BS |
960 | break; |
961 | } | |
962 | } else { | |
963 | switch(size) { | |
964 | case 1: | |
1a2fb1c0 | 965 | ret = ldub_kernel(addr); |
6f27aba6 BS |
966 | break; |
967 | case 2: | |
1a2fb1c0 | 968 | ret = lduw_kernel(addr & ~1); |
6f27aba6 BS |
969 | break; |
970 | case 4: | |
1a2fb1c0 | 971 | ret = ldl_kernel(addr & ~3); |
6f27aba6 BS |
972 | break; |
973 | default: | |
974 | case 8: | |
1a2fb1c0 | 975 | ret = ldq_kernel(addr & ~7); |
6f27aba6 BS |
976 | break; |
977 | } | |
81ad8ba2 BS |
978 | } |
979 | } else { | |
980 | switch(size) { | |
981 | case 1: | |
1a2fb1c0 | 982 | ret = ldub_user(addr); |
81ad8ba2 BS |
983 | break; |
984 | case 2: | |
1a2fb1c0 | 985 | ret = lduw_user(addr & ~1); |
81ad8ba2 BS |
986 | break; |
987 | case 4: | |
1a2fb1c0 | 988 | ret = ldl_user(addr & ~3); |
81ad8ba2 BS |
989 | break; |
990 | default: | |
991 | case 8: | |
1a2fb1c0 | 992 | ret = ldq_user(addr & ~7); |
81ad8ba2 BS |
993 | break; |
994 | } | |
995 | } | |
996 | break; | |
3475187d FB |
997 | case 0x14: // Bypass |
998 | case 0x15: // Bypass, non-cacheable | |
81ad8ba2 BS |
999 | case 0x1c: // Bypass LE |
1000 | case 0x1d: // Bypass, non-cacheable LE | |
0f8a249a | 1001 | { |
02aab46a FB |
1002 | switch(size) { |
1003 | case 1: | |
1a2fb1c0 | 1004 | ret = ldub_phys(addr); |
02aab46a FB |
1005 | break; |
1006 | case 2: | |
1a2fb1c0 | 1007 | ret = lduw_phys(addr & ~1); |
02aab46a FB |
1008 | break; |
1009 | case 4: | |
1a2fb1c0 | 1010 | ret = ldl_phys(addr & ~3); |
02aab46a FB |
1011 | break; |
1012 | default: | |
1013 | case 8: | |
1a2fb1c0 | 1014 | ret = ldq_phys(addr & ~7); |
02aab46a FB |
1015 | break; |
1016 | } | |
0f8a249a BS |
1017 | break; |
1018 | } | |
83469015 FB |
1019 | case 0x04: // Nucleus |
1020 | case 0x0c: // Nucleus Little Endian (LE) | |
83469015 | 1021 | case 0x11: // As if user secondary |
83469015 | 1022 | case 0x19: // As if user secondary LE |
83469015 FB |
1023 | case 0x24: // Nucleus quad LDD 128 bit atomic |
1024 | case 0x2c: // Nucleus quad LDD 128 bit atomic | |
1025 | case 0x4a: // UPA config | |
81ad8ba2 | 1026 | case 0x81: // Secondary |
83469015 | 1027 | case 0x83: // Secondary no-fault |
83469015 | 1028 | case 0x89: // Secondary LE |
83469015 | 1029 | case 0x8b: // Secondary no-fault LE |
0f8a249a BS |
1030 | // XXX |
1031 | break; | |
3475187d | 1032 | case 0x45: // LSU |
0f8a249a BS |
1033 | ret = env->lsu; |
1034 | break; | |
3475187d | 1035 | case 0x50: // I-MMU regs |
0f8a249a | 1036 | { |
1a2fb1c0 | 1037 | int reg = (addr >> 3) & 0xf; |
3475187d | 1038 | |
0f8a249a BS |
1039 | ret = env->immuregs[reg]; |
1040 | break; | |
1041 | } | |
3475187d FB |
1042 | case 0x51: // I-MMU 8k TSB pointer |
1043 | case 0x52: // I-MMU 64k TSB pointer | |
1044 | case 0x55: // I-MMU data access | |
0f8a249a BS |
1045 | // XXX |
1046 | break; | |
83469015 | 1047 | case 0x56: // I-MMU tag read |
0f8a249a BS |
1048 | { |
1049 | unsigned int i; | |
1050 | ||
1051 | for (i = 0; i < 64; i++) { | |
1052 | // Valid, ctx match, vaddr match | |
1053 | if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 && | |
1a2fb1c0 | 1054 | env->itlb_tag[i] == addr) { |
0f8a249a BS |
1055 | ret = env->itlb_tag[i]; |
1056 | break; | |
1057 | } | |
1058 | } | |
1059 | break; | |
1060 | } | |
3475187d | 1061 | case 0x58: // D-MMU regs |
0f8a249a | 1062 | { |
1a2fb1c0 | 1063 | int reg = (addr >> 3) & 0xf; |
3475187d | 1064 | |
0f8a249a BS |
1065 | ret = env->dmmuregs[reg]; |
1066 | break; | |
1067 | } | |
83469015 | 1068 | case 0x5e: // D-MMU tag read |
0f8a249a BS |
1069 | { |
1070 | unsigned int i; | |
1071 | ||
1072 | for (i = 0; i < 64; i++) { | |
1073 | // Valid, ctx match, vaddr match | |
1074 | if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 && | |
1a2fb1c0 | 1075 | env->dtlb_tag[i] == addr) { |
0f8a249a BS |
1076 | ret = env->dtlb_tag[i]; |
1077 | break; | |
1078 | } | |
1079 | } | |
1080 | break; | |
1081 | } | |
3475187d FB |
1082 | case 0x59: // D-MMU 8k TSB pointer |
1083 | case 0x5a: // D-MMU 64k TSB pointer | |
1084 | case 0x5b: // D-MMU data pointer | |
1085 | case 0x5d: // D-MMU data access | |
83469015 FB |
1086 | case 0x48: // Interrupt dispatch, RO |
1087 | case 0x49: // Interrupt data receive | |
1088 | case 0x7f: // Incoming interrupt vector, RO | |
0f8a249a BS |
1089 | // XXX |
1090 | break; | |
3475187d FB |
1091 | case 0x54: // I-MMU data in, WO |
1092 | case 0x57: // I-MMU demap, WO | |
1093 | case 0x5c: // D-MMU data in, WO | |
1094 | case 0x5f: // D-MMU demap, WO | |
83469015 | 1095 | case 0x77: // Interrupt vector, WO |
3475187d | 1096 | default: |
1a2fb1c0 | 1097 | do_unassigned_access(addr, 0, 0, 1); |
0f8a249a BS |
1098 | ret = 0; |
1099 | break; | |
3475187d | 1100 | } |
81ad8ba2 BS |
1101 | |
1102 | /* Convert from little endian */ | |
1103 | switch (asi) { | |
1104 | case 0x0c: // Nucleus Little Endian (LE) | |
1105 | case 0x18: // As if user primary LE | |
1106 | case 0x19: // As if user secondary LE | |
1107 | case 0x1c: // Bypass LE | |
1108 | case 0x1d: // Bypass, non-cacheable LE | |
1109 | case 0x88: // Primary LE | |
1110 | case 0x89: // Secondary LE | |
1111 | case 0x8a: // Primary no-fault LE | |
1112 | case 0x8b: // Secondary no-fault LE | |
1113 | switch(size) { | |
1114 | case 2: | |
1115 | ret = bswap16(ret); | |
e32664fb | 1116 | break; |
81ad8ba2 BS |
1117 | case 4: |
1118 | ret = bswap32(ret); | |
e32664fb | 1119 | break; |
81ad8ba2 BS |
1120 | case 8: |
1121 | ret = bswap64(ret); | |
e32664fb | 1122 | break; |
81ad8ba2 BS |
1123 | default: |
1124 | break; | |
1125 | } | |
1126 | default: | |
1127 | break; | |
1128 | } | |
1129 | ||
1130 | /* Convert to signed number */ | |
1131 | if (sign) { | |
1132 | switch(size) { | |
1133 | case 1: | |
1134 | ret = (int8_t) ret; | |
e32664fb | 1135 | break; |
81ad8ba2 BS |
1136 | case 2: |
1137 | ret = (int16_t) ret; | |
e32664fb | 1138 | break; |
81ad8ba2 BS |
1139 | case 4: |
1140 | ret = (int32_t) ret; | |
e32664fb | 1141 | break; |
81ad8ba2 BS |
1142 | default: |
1143 | break; | |
1144 | } | |
1145 | } | |
1a2fb1c0 BS |
1146 | #ifdef DEBUG_ASI |
1147 | dump_asi("read ", last_addr, asi, size, ret); | |
1148 | #endif | |
1149 | return ret; | |
3475187d FB |
1150 | } |
1151 | ||
1a2fb1c0 | 1152 | void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) |
3475187d | 1153 | { |
1a2fb1c0 BS |
1154 | #ifdef DEBUG_ASI |
1155 | dump_asi("write", addr, asi, size, val); | |
1156 | #endif | |
6f27aba6 | 1157 | if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
20b749f6 | 1158 | || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV))) |
0f8a249a | 1159 | raise_exception(TT_PRIV_ACT); |
3475187d | 1160 | |
81ad8ba2 BS |
1161 | /* Convert to little endian */ |
1162 | switch (asi) { | |
1163 | case 0x0c: // Nucleus Little Endian (LE) | |
1164 | case 0x18: // As if user primary LE | |
1165 | case 0x19: // As if user secondary LE | |
1166 | case 0x1c: // Bypass LE | |
1167 | case 0x1d: // Bypass, non-cacheable LE | |
81ad8ba2 BS |
1168 | case 0x88: // Primary LE |
1169 | case 0x89: // Secondary LE | |
1170 | switch(size) { | |
1171 | case 2: | |
1a2fb1c0 | 1172 | addr = bswap16(addr); |
e32664fb | 1173 | break; |
81ad8ba2 | 1174 | case 4: |
1a2fb1c0 | 1175 | addr = bswap32(addr); |
e32664fb | 1176 | break; |
81ad8ba2 | 1177 | case 8: |
1a2fb1c0 | 1178 | addr = bswap64(addr); |
e32664fb | 1179 | break; |
81ad8ba2 BS |
1180 | default: |
1181 | break; | |
1182 | } | |
1183 | default: | |
1184 | break; | |
1185 | } | |
1186 | ||
3475187d | 1187 | switch(asi) { |
81ad8ba2 BS |
1188 | case 0x10: // As if user primary |
1189 | case 0x18: // As if user primary LE | |
1190 | case 0x80: // Primary | |
1191 | case 0x88: // Primary LE | |
1192 | if ((asi & 0x80) && (env->pstate & PS_PRIV)) { | |
6f27aba6 BS |
1193 | if (env->hpstate & HS_PRIV) { |
1194 | switch(size) { | |
1195 | case 1: | |
1a2fb1c0 | 1196 | stb_hypv(addr, val); |
6f27aba6 BS |
1197 | break; |
1198 | case 2: | |
1a2fb1c0 | 1199 | stw_hypv(addr & ~1, val); |
6f27aba6 BS |
1200 | break; |
1201 | case 4: | |
1a2fb1c0 | 1202 | stl_hypv(addr & ~3, val); |
6f27aba6 BS |
1203 | break; |
1204 | case 8: | |
1205 | default: | |
1a2fb1c0 | 1206 | stq_hypv(addr & ~7, val); |
6f27aba6 BS |
1207 | break; |
1208 | } | |
1209 | } else { | |
1210 | switch(size) { | |
1211 | case 1: | |
1a2fb1c0 | 1212 | stb_kernel(addr, val); |
6f27aba6 BS |
1213 | break; |
1214 | case 2: | |
1a2fb1c0 | 1215 | stw_kernel(addr & ~1, val); |
6f27aba6 BS |
1216 | break; |
1217 | case 4: | |
1a2fb1c0 | 1218 | stl_kernel(addr & ~3, val); |
6f27aba6 BS |
1219 | break; |
1220 | case 8: | |
1221 | default: | |
1a2fb1c0 | 1222 | stq_kernel(addr & ~7, val); |
6f27aba6 BS |
1223 | break; |
1224 | } | |
81ad8ba2 BS |
1225 | } |
1226 | } else { | |
1227 | switch(size) { | |
1228 | case 1: | |
1a2fb1c0 | 1229 | stb_user(addr, val); |
81ad8ba2 BS |
1230 | break; |
1231 | case 2: | |
1a2fb1c0 | 1232 | stw_user(addr & ~1, val); |
81ad8ba2 BS |
1233 | break; |
1234 | case 4: | |
1a2fb1c0 | 1235 | stl_user(addr & ~3, val); |
81ad8ba2 BS |
1236 | break; |
1237 | case 8: | |
1238 | default: | |
1a2fb1c0 | 1239 | stq_user(addr & ~7, val); |
81ad8ba2 BS |
1240 | break; |
1241 | } | |
1242 | } | |
1243 | break; | |
3475187d FB |
1244 | case 0x14: // Bypass |
1245 | case 0x15: // Bypass, non-cacheable | |
81ad8ba2 BS |
1246 | case 0x1c: // Bypass LE |
1247 | case 0x1d: // Bypass, non-cacheable LE | |
0f8a249a | 1248 | { |
02aab46a FB |
1249 | switch(size) { |
1250 | case 1: | |
1a2fb1c0 | 1251 | stb_phys(addr, val); |
02aab46a FB |
1252 | break; |
1253 | case 2: | |
1a2fb1c0 | 1254 | stw_phys(addr & ~1, val); |
02aab46a FB |
1255 | break; |
1256 | case 4: | |
1a2fb1c0 | 1257 | stl_phys(addr & ~3, val); |
02aab46a FB |
1258 | break; |
1259 | case 8: | |
1260 | default: | |
1a2fb1c0 | 1261 | stq_phys(addr & ~7, val); |
02aab46a FB |
1262 | break; |
1263 | } | |
0f8a249a BS |
1264 | } |
1265 | return; | |
83469015 FB |
1266 | case 0x04: // Nucleus |
1267 | case 0x0c: // Nucleus Little Endian (LE) | |
83469015 | 1268 | case 0x11: // As if user secondary |
83469015 | 1269 | case 0x19: // As if user secondary LE |
83469015 FB |
1270 | case 0x24: // Nucleus quad LDD 128 bit atomic |
1271 | case 0x2c: // Nucleus quad LDD 128 bit atomic | |
1272 | case 0x4a: // UPA config | |
51996525 | 1273 | case 0x81: // Secondary |
83469015 | 1274 | case 0x89: // Secondary LE |
0f8a249a BS |
1275 | // XXX |
1276 | return; | |
3475187d | 1277 | case 0x45: // LSU |
0f8a249a BS |
1278 | { |
1279 | uint64_t oldreg; | |
1280 | ||
1281 | oldreg = env->lsu; | |
1a2fb1c0 | 1282 | env->lsu = val & (DMMU_E | IMMU_E); |
0f8a249a BS |
1283 | // Mappings generated during D/I MMU disabled mode are |
1284 | // invalid in normal mode | |
1285 | if (oldreg != env->lsu) { | |
952a328f | 1286 | DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu); |
83469015 | 1287 | #ifdef DEBUG_MMU |
0f8a249a | 1288 | dump_mmu(env); |
83469015 | 1289 | #endif |
0f8a249a BS |
1290 | tlb_flush(env, 1); |
1291 | } | |
1292 | return; | |
1293 | } | |
3475187d | 1294 | case 0x50: // I-MMU regs |
0f8a249a | 1295 | { |
1a2fb1c0 | 1296 | int reg = (addr >> 3) & 0xf; |
0f8a249a | 1297 | uint64_t oldreg; |
3b46e624 | 1298 | |
0f8a249a | 1299 | oldreg = env->immuregs[reg]; |
3475187d FB |
1300 | switch(reg) { |
1301 | case 0: // RO | |
1302 | case 4: | |
1303 | return; | |
1304 | case 1: // Not in I-MMU | |
1305 | case 2: | |
1306 | case 7: | |
1307 | case 8: | |
1308 | return; | |
1309 | case 3: // SFSR | |
1a2fb1c0 BS |
1310 | if ((val & 1) == 0) |
1311 | val = 0; // Clear SFSR | |
3475187d FB |
1312 | break; |
1313 | case 5: // TSB access | |
1314 | case 6: // Tag access | |
1315 | default: | |
1316 | break; | |
1317 | } | |
1a2fb1c0 | 1318 | env->immuregs[reg] = val; |
3475187d | 1319 | if (oldreg != env->immuregs[reg]) { |
952a328f | 1320 | DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]); |
3475187d | 1321 | } |
952a328f | 1322 | #ifdef DEBUG_MMU |
0f8a249a | 1323 | dump_mmu(env); |
3475187d | 1324 | #endif |
0f8a249a BS |
1325 | return; |
1326 | } | |
3475187d | 1327 | case 0x54: // I-MMU data in |
0f8a249a BS |
1328 | { |
1329 | unsigned int i; | |
1330 | ||
1331 | // Try finding an invalid entry | |
1332 | for (i = 0; i < 64; i++) { | |
1333 | if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) { | |
1334 | env->itlb_tag[i] = env->immuregs[6]; | |
1a2fb1c0 | 1335 | env->itlb_tte[i] = val; |
0f8a249a BS |
1336 | return; |
1337 | } | |
1338 | } | |
1339 | // Try finding an unlocked entry | |
1340 | for (i = 0; i < 64; i++) { | |
1341 | if ((env->itlb_tte[i] & 0x40) == 0) { | |
1342 | env->itlb_tag[i] = env->immuregs[6]; | |
1a2fb1c0 | 1343 | env->itlb_tte[i] = val; |
0f8a249a BS |
1344 | return; |
1345 | } | |
1346 | } | |
1347 | // error state? | |
1348 | return; | |
1349 | } | |
3475187d | 1350 | case 0x55: // I-MMU data access |
0f8a249a | 1351 | { |
1a2fb1c0 | 1352 | unsigned int i = (addr >> 3) & 0x3f; |
3475187d | 1353 | |
0f8a249a | 1354 | env->itlb_tag[i] = env->immuregs[6]; |
1a2fb1c0 | 1355 | env->itlb_tte[i] = val; |
0f8a249a BS |
1356 | return; |
1357 | } | |
3475187d | 1358 | case 0x57: // I-MMU demap |
0f8a249a BS |
1359 | // XXX |
1360 | return; | |
3475187d | 1361 | case 0x58: // D-MMU regs |
0f8a249a | 1362 | { |
1a2fb1c0 | 1363 | int reg = (addr >> 3) & 0xf; |
0f8a249a | 1364 | uint64_t oldreg; |
3b46e624 | 1365 | |
0f8a249a | 1366 | oldreg = env->dmmuregs[reg]; |
3475187d FB |
1367 | switch(reg) { |
1368 | case 0: // RO | |
1369 | case 4: | |
1370 | return; | |
1371 | case 3: // SFSR | |
1a2fb1c0 BS |
1372 | if ((val & 1) == 0) { |
1373 | val = 0; // Clear SFSR, Fault address | |
0f8a249a BS |
1374 | env->dmmuregs[4] = 0; |
1375 | } | |
1a2fb1c0 | 1376 | env->dmmuregs[reg] = val; |
3475187d FB |
1377 | break; |
1378 | case 1: // Primary context | |
1379 | case 2: // Secondary context | |
1380 | case 5: // TSB access | |
1381 | case 6: // Tag access | |
1382 | case 7: // Virtual Watchpoint | |
1383 | case 8: // Physical Watchpoint | |
1384 | default: | |
1385 | break; | |
1386 | } | |
1a2fb1c0 | 1387 | env->dmmuregs[reg] = val; |
3475187d | 1388 | if (oldreg != env->dmmuregs[reg]) { |
952a328f | 1389 | DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); |
3475187d | 1390 | } |
952a328f | 1391 | #ifdef DEBUG_MMU |
0f8a249a | 1392 | dump_mmu(env); |
3475187d | 1393 | #endif |
0f8a249a BS |
1394 | return; |
1395 | } | |
3475187d | 1396 | case 0x5c: // D-MMU data in |
0f8a249a BS |
1397 | { |
1398 | unsigned int i; | |
1399 | ||
1400 | // Try finding an invalid entry | |
1401 | for (i = 0; i < 64; i++) { | |
1402 | if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) { | |
1403 | env->dtlb_tag[i] = env->dmmuregs[6]; | |
1a2fb1c0 | 1404 | env->dtlb_tte[i] = val; |
0f8a249a BS |
1405 | return; |
1406 | } | |
1407 | } | |
1408 | // Try finding an unlocked entry | |
1409 | for (i = 0; i < 64; i++) { | |
1410 | if ((env->dtlb_tte[i] & 0x40) == 0) { | |
1411 | env->dtlb_tag[i] = env->dmmuregs[6]; | |
1a2fb1c0 | 1412 | env->dtlb_tte[i] = val; |
0f8a249a BS |
1413 | return; |
1414 | } | |
1415 | } | |
1416 | // error state? | |
1417 | return; | |
1418 | } | |
3475187d | 1419 | case 0x5d: // D-MMU data access |
0f8a249a | 1420 | { |
1a2fb1c0 | 1421 | unsigned int i = (addr >> 3) & 0x3f; |
3475187d | 1422 | |
0f8a249a | 1423 | env->dtlb_tag[i] = env->dmmuregs[6]; |
1a2fb1c0 | 1424 | env->dtlb_tte[i] = val; |
0f8a249a BS |
1425 | return; |
1426 | } | |
3475187d | 1427 | case 0x5f: // D-MMU demap |
83469015 | 1428 | case 0x49: // Interrupt data receive |
0f8a249a BS |
1429 | // XXX |
1430 | return; | |
3475187d FB |
1431 | case 0x51: // I-MMU 8k TSB pointer, RO |
1432 | case 0x52: // I-MMU 64k TSB pointer, RO | |
1433 | case 0x56: // I-MMU tag read, RO | |
1434 | case 0x59: // D-MMU 8k TSB pointer, RO | |
1435 | case 0x5a: // D-MMU 64k TSB pointer, RO | |
1436 | case 0x5b: // D-MMU data pointer, RO | |
1437 | case 0x5e: // D-MMU tag read, RO | |
83469015 FB |
1438 | case 0x48: // Interrupt dispatch, RO |
1439 | case 0x7f: // Incoming interrupt vector, RO | |
1440 | case 0x82: // Primary no-fault, RO | |
1441 | case 0x83: // Secondary no-fault, RO | |
1442 | case 0x8a: // Primary no-fault LE, RO | |
1443 | case 0x8b: // Secondary no-fault LE, RO | |
3475187d | 1444 | default: |
1a2fb1c0 | 1445 | do_unassigned_access(addr, 1, 0, 1); |
0f8a249a | 1446 | return; |
3475187d FB |
1447 | } |
1448 | } | |
81ad8ba2 | 1449 | #endif /* CONFIG_USER_ONLY */ |
3391c818 | 1450 | |
1a2fb1c0 | 1451 | void helper_ldf_asi(target_ulong addr, int asi, int size, int rd) |
3391c818 | 1452 | { |
3391c818 | 1453 | unsigned int i; |
1a2fb1c0 | 1454 | target_ulong val; |
3391c818 BS |
1455 | |
1456 | switch (asi) { | |
1457 | case 0xf0: // Block load primary | |
1458 | case 0xf1: // Block load secondary | |
1459 | case 0xf8: // Block load primary LE | |
1460 | case 0xf9: // Block load secondary LE | |
51996525 BS |
1461 | if (rd & 7) { |
1462 | raise_exception(TT_ILL_INSN); | |
1463 | return; | |
1464 | } | |
1a2fb1c0 | 1465 | if (addr & 0x3f) { |
51996525 BS |
1466 | raise_exception(TT_UNALIGNED); |
1467 | return; | |
1468 | } | |
1469 | for (i = 0; i < 16; i++) { | |
1a2fb1c0 BS |
1470 | *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4, 0); |
1471 | addr += 4; | |
3391c818 | 1472 | } |
3391c818 BS |
1473 | |
1474 | return; | |
1475 | default: | |
1476 | break; | |
1477 | } | |
1478 | ||
1a2fb1c0 | 1479 | val = helper_ld_asi(addr, asi, size, 0); |
3391c818 BS |
1480 | switch(size) { |
1481 | default: | |
1482 | case 4: | |
1a2fb1c0 | 1483 | *((uint32_t *)&FT0) = val; |
3391c818 BS |
1484 | break; |
1485 | case 8: | |
1a2fb1c0 | 1486 | *((int64_t *)&DT0) = val; |
3391c818 | 1487 | break; |
1f587329 BS |
1488 | #if defined(CONFIG_USER_ONLY) |
1489 | case 16: | |
1490 | // XXX | |
1491 | break; | |
1492 | #endif | |
3391c818 | 1493 | } |
3391c818 BS |
1494 | } |
1495 | ||
1a2fb1c0 | 1496 | void helper_stf_asi(target_ulong addr, int asi, int size, int rd) |
3391c818 | 1497 | { |
3391c818 | 1498 | unsigned int i; |
1a2fb1c0 | 1499 | target_ulong val = 0; |
3391c818 BS |
1500 | |
1501 | switch (asi) { | |
1502 | case 0xf0: // Block store primary | |
1503 | case 0xf1: // Block store secondary | |
1504 | case 0xf8: // Block store primary LE | |
1505 | case 0xf9: // Block store secondary LE | |
51996525 BS |
1506 | if (rd & 7) { |
1507 | raise_exception(TT_ILL_INSN); | |
1508 | return; | |
1509 | } | |
1a2fb1c0 | 1510 | if (addr & 0x3f) { |
51996525 BS |
1511 | raise_exception(TT_UNALIGNED); |
1512 | return; | |
1513 | } | |
1514 | for (i = 0; i < 16; i++) { | |
1a2fb1c0 BS |
1515 | val = *(uint32_t *)&env->fpr[rd++]; |
1516 | helper_st_asi(addr, val, asi & 0x8f, 4); | |
1517 | addr += 4; | |
3391c818 | 1518 | } |
3391c818 BS |
1519 | |
1520 | return; | |
1521 | default: | |
1522 | break; | |
1523 | } | |
1524 | ||
1525 | switch(size) { | |
1526 | default: | |
1527 | case 4: | |
1a2fb1c0 | 1528 | val = *((uint32_t *)&FT0); |
3391c818 BS |
1529 | break; |
1530 | case 8: | |
1a2fb1c0 | 1531 | val = *((int64_t *)&DT0); |
3391c818 | 1532 | break; |
1f587329 BS |
1533 | #if defined(CONFIG_USER_ONLY) |
1534 | case 16: | |
1535 | // XXX | |
1536 | break; | |
1537 | #endif | |
3391c818 | 1538 | } |
1a2fb1c0 BS |
1539 | helper_st_asi(addr, val, asi, size); |
1540 | } | |
1541 | ||
1542 | target_ulong helper_cas_asi(target_ulong addr, target_ulong val1, | |
1543 | target_ulong val2, uint32_t asi) | |
1544 | { | |
1545 | target_ulong ret; | |
1546 | ||
1547 | val1 &= 0xffffffffUL; | |
1548 | ret = helper_ld_asi(addr, asi, 4, 0); | |
1549 | ret &= 0xffffffffUL; | |
1550 | if (val1 == ret) | |
1551 | helper_st_asi(addr, val2 & 0xffffffffUL, asi, 4); | |
1552 | return ret; | |
3391c818 BS |
1553 | } |
1554 | ||
1a2fb1c0 BS |
1555 | target_ulong helper_casx_asi(target_ulong addr, target_ulong val1, |
1556 | target_ulong val2, uint32_t asi) | |
1557 | { | |
1558 | target_ulong ret; | |
1559 | ||
1560 | ret = helper_ld_asi(addr, asi, 8, 0); | |
1561 | if (val1 == ret) | |
1562 | helper_st_asi(addr, val2, asi, 8); | |
1563 | return ret; | |
1564 | } | |
81ad8ba2 | 1565 | #endif /* TARGET_SPARC64 */ |
3475187d FB |
1566 | |
1567 | #ifndef TARGET_SPARC64 | |
1a2fb1c0 | 1568 | void helper_rett(void) |
e8af50a3 | 1569 | { |
af7bf89b FB |
1570 | unsigned int cwp; |
1571 | ||
d4218d99 BS |
1572 | if (env->psret == 1) |
1573 | raise_exception(TT_ILL_INSN); | |
1574 | ||
e8af50a3 | 1575 | env->psret = 1; |
5fafdf24 | 1576 | cwp = (env->cwp + 1) & (NWINDOWS - 1); |
e8af50a3 FB |
1577 | if (env->wim & (1 << cwp)) { |
1578 | raise_exception(TT_WIN_UNF); | |
1579 | } | |
1580 | set_cwp(cwp); | |
1581 | env->psrs = env->psrps; | |
1582 | } | |
3475187d | 1583 | #endif |
e8af50a3 | 1584 | |
1a2fb1c0 BS |
1585 | uint64_t helper_pack64(target_ulong high, target_ulong low) |
1586 | { | |
1587 | return ((uint64_t)high << 32) | (uint64_t)(low & 0xffffffff); | |
1588 | } | |
1589 | ||
8d5f07fa | 1590 | void helper_ldfsr(void) |
e8af50a3 | 1591 | { |
7a0e1f41 | 1592 | int rnd_mode; |
bb5529bb BS |
1593 | |
1594 | PUT_FSR32(env, *((uint32_t *) &FT0)); | |
e8af50a3 FB |
1595 | switch (env->fsr & FSR_RD_MASK) { |
1596 | case FSR_RD_NEAREST: | |
7a0e1f41 | 1597 | rnd_mode = float_round_nearest_even; |
0f8a249a | 1598 | break; |
ed910241 | 1599 | default: |
e8af50a3 | 1600 | case FSR_RD_ZERO: |
7a0e1f41 | 1601 | rnd_mode = float_round_to_zero; |
0f8a249a | 1602 | break; |
e8af50a3 | 1603 | case FSR_RD_POS: |
7a0e1f41 | 1604 | rnd_mode = float_round_up; |
0f8a249a | 1605 | break; |
e8af50a3 | 1606 | case FSR_RD_NEG: |
7a0e1f41 | 1607 | rnd_mode = float_round_down; |
0f8a249a | 1608 | break; |
e8af50a3 | 1609 | } |
7a0e1f41 | 1610 | set_float_rounding_mode(rnd_mode, &env->fp_status); |
e8af50a3 | 1611 | } |
e80cfcfc | 1612 | |
bb5529bb BS |
1613 | void helper_stfsr(void) |
1614 | { | |
1615 | *((uint32_t *) &FT0) = GET_FSR32(env); | |
1616 | } | |
1617 | ||
1618 | void helper_debug(void) | |
e80cfcfc FB |
1619 | { |
1620 | env->exception_index = EXCP_DEBUG; | |
1621 | cpu_loop_exit(); | |
1622 | } | |
af7bf89b | 1623 | |
3475187d | 1624 | #ifndef TARGET_SPARC64 |
1a2fb1c0 | 1625 | void helper_wrpsr(target_ulong new_psr) |
af7bf89b | 1626 | { |
1a2fb1c0 | 1627 | if ((new_psr & PSR_CWP) >= NWINDOWS) |
d4218d99 BS |
1628 | raise_exception(TT_ILL_INSN); |
1629 | else | |
1a2fb1c0 | 1630 | PUT_PSR(env, new_psr); |
af7bf89b FB |
1631 | } |
1632 | ||
1a2fb1c0 | 1633 | target_ulong helper_rdpsr(void) |
af7bf89b | 1634 | { |
1a2fb1c0 | 1635 | return GET_PSR(env); |
af7bf89b | 1636 | } |
3475187d FB |
1637 | |
1638 | #else | |
1639 | ||
1a2fb1c0 | 1640 | target_ulong helper_popc(target_ulong val) |
3475187d | 1641 | { |
1a2fb1c0 | 1642 | return ctpop64(val); |
3475187d | 1643 | } |
83469015 FB |
1644 | |
1645 | static inline uint64_t *get_gregset(uint64_t pstate) | |
1646 | { | |
1647 | switch (pstate) { | |
1648 | default: | |
1649 | case 0: | |
0f8a249a | 1650 | return env->bgregs; |
83469015 | 1651 | case PS_AG: |
0f8a249a | 1652 | return env->agregs; |
83469015 | 1653 | case PS_MG: |
0f8a249a | 1654 | return env->mgregs; |
83469015 | 1655 | case PS_IG: |
0f8a249a | 1656 | return env->igregs; |
83469015 FB |
1657 | } |
1658 | } | |
1659 | ||
8f1f22f6 | 1660 | static inline void change_pstate(uint64_t new_pstate) |
83469015 | 1661 | { |
8f1f22f6 | 1662 | uint64_t pstate_regs, new_pstate_regs; |
83469015 FB |
1663 | uint64_t *src, *dst; |
1664 | ||
83469015 FB |
1665 | pstate_regs = env->pstate & 0xc01; |
1666 | new_pstate_regs = new_pstate & 0xc01; | |
1667 | if (new_pstate_regs != pstate_regs) { | |
0f8a249a BS |
1668 | // Switch global register bank |
1669 | src = get_gregset(new_pstate_regs); | |
1670 | dst = get_gregset(pstate_regs); | |
1671 | memcpy32(dst, env->gregs); | |
1672 | memcpy32(env->gregs, src); | |
83469015 FB |
1673 | } |
1674 | env->pstate = new_pstate; | |
1675 | } | |
1676 | ||
1a2fb1c0 | 1677 | void helper_wrpstate(target_ulong new_state) |
8f1f22f6 | 1678 | { |
1a2fb1c0 | 1679 | change_pstate(new_state & 0xf3f); |
8f1f22f6 BS |
1680 | } |
1681 | ||
1a2fb1c0 | 1682 | void helper_done(void) |
83469015 FB |
1683 | { |
1684 | env->tl--; | |
375ee38b BS |
1685 | env->tsptr = &env->ts[env->tl]; |
1686 | env->pc = env->tsptr->tpc; | |
1687 | env->npc = env->tsptr->tnpc + 4; | |
1688 | PUT_CCR(env, env->tsptr->tstate >> 32); | |
1689 | env->asi = (env->tsptr->tstate >> 24) & 0xff; | |
1690 | change_pstate((env->tsptr->tstate >> 8) & 0xf3f); | |
1691 | PUT_CWP64(env, env->tsptr->tstate & 0xff); | |
83469015 FB |
1692 | } |
1693 | ||
1a2fb1c0 | 1694 | void helper_retry(void) |
83469015 FB |
1695 | { |
1696 | env->tl--; | |
375ee38b BS |
1697 | env->tsptr = &env->ts[env->tl]; |
1698 | env->pc = env->tsptr->tpc; | |
1699 | env->npc = env->tsptr->tnpc; | |
1700 | PUT_CCR(env, env->tsptr->tstate >> 32); | |
1701 | env->asi = (env->tsptr->tstate >> 24) & 0xff; | |
1702 | change_pstate((env->tsptr->tstate >> 8) & 0xf3f); | |
1703 | PUT_CWP64(env, env->tsptr->tstate & 0xff); | |
83469015 | 1704 | } |
3475187d | 1705 | #endif |
ee5bbe38 FB |
1706 | |
1707 | void set_cwp(int new_cwp) | |
1708 | { | |
1709 | /* put the modified wrap registers at their proper location */ | |
1710 | if (env->cwp == (NWINDOWS - 1)) | |
1711 | memcpy32(env->regbase, env->regbase + NWINDOWS * 16); | |
1712 | env->cwp = new_cwp; | |
1713 | /* put the wrap registers at their temporary location */ | |
1714 | if (new_cwp == (NWINDOWS - 1)) | |
1715 | memcpy32(env->regbase + NWINDOWS * 16, env->regbase); | |
1716 | env->regwptr = env->regbase + (new_cwp * 16); | |
1717 | REGWPTR = env->regwptr; | |
1718 | } | |
1719 | ||
1720 | void cpu_set_cwp(CPUState *env1, int new_cwp) | |
1721 | { | |
1722 | CPUState *saved_env; | |
1723 | #ifdef reg_REGWPTR | |
1724 | target_ulong *saved_regwptr; | |
1725 | #endif | |
1726 | ||
1727 | saved_env = env; | |
1728 | #ifdef reg_REGWPTR | |
1729 | saved_regwptr = REGWPTR; | |
1730 | #endif | |
1731 | env = env1; | |
1732 | set_cwp(new_cwp); | |
1733 | env = saved_env; | |
1734 | #ifdef reg_REGWPTR | |
1735 | REGWPTR = saved_regwptr; | |
1736 | #endif | |
1737 | } | |
1738 | ||
1739 | #ifdef TARGET_SPARC64 | |
0b09be2b BS |
1740 | #ifdef DEBUG_PCALL |
1741 | static const char * const excp_names[0x50] = { | |
1742 | [TT_TFAULT] = "Instruction Access Fault", | |
1743 | [TT_TMISS] = "Instruction Access MMU Miss", | |
1744 | [TT_CODE_ACCESS] = "Instruction Access Error", | |
1745 | [TT_ILL_INSN] = "Illegal Instruction", | |
1746 | [TT_PRIV_INSN] = "Privileged Instruction", | |
1747 | [TT_NFPU_INSN] = "FPU Disabled", | |
1748 | [TT_FP_EXCP] = "FPU Exception", | |
1749 | [TT_TOVF] = "Tag Overflow", | |
1750 | [TT_CLRWIN] = "Clean Windows", | |
1751 | [TT_DIV_ZERO] = "Division By Zero", | |
1752 | [TT_DFAULT] = "Data Access Fault", | |
1753 | [TT_DMISS] = "Data Access MMU Miss", | |
1754 | [TT_DATA_ACCESS] = "Data Access Error", | |
1755 | [TT_DPROT] = "Data Protection Error", | |
1756 | [TT_UNALIGNED] = "Unaligned Memory Access", | |
1757 | [TT_PRIV_ACT] = "Privileged Action", | |
1758 | [TT_EXTINT | 0x1] = "External Interrupt 1", | |
1759 | [TT_EXTINT | 0x2] = "External Interrupt 2", | |
1760 | [TT_EXTINT | 0x3] = "External Interrupt 3", | |
1761 | [TT_EXTINT | 0x4] = "External Interrupt 4", | |
1762 | [TT_EXTINT | 0x5] = "External Interrupt 5", | |
1763 | [TT_EXTINT | 0x6] = "External Interrupt 6", | |
1764 | [TT_EXTINT | 0x7] = "External Interrupt 7", | |
1765 | [TT_EXTINT | 0x8] = "External Interrupt 8", | |
1766 | [TT_EXTINT | 0x9] = "External Interrupt 9", | |
1767 | [TT_EXTINT | 0xa] = "External Interrupt 10", | |
1768 | [TT_EXTINT | 0xb] = "External Interrupt 11", | |
1769 | [TT_EXTINT | 0xc] = "External Interrupt 12", | |
1770 | [TT_EXTINT | 0xd] = "External Interrupt 13", | |
1771 | [TT_EXTINT | 0xe] = "External Interrupt 14", | |
1772 | [TT_EXTINT | 0xf] = "External Interrupt 15", | |
1773 | }; | |
1774 | #endif | |
1775 | ||
ee5bbe38 FB |
1776 | void do_interrupt(int intno) |
1777 | { | |
1778 | #ifdef DEBUG_PCALL | |
1779 | if (loglevel & CPU_LOG_INT) { | |
0f8a249a | 1780 | static int count; |
0b09be2b BS |
1781 | const char *name; |
1782 | ||
1783 | if (intno < 0 || intno >= 0x180 || (intno > 0x4f && intno < 0x80)) | |
1784 | name = "Unknown"; | |
1785 | else if (intno >= 0x100) | |
1786 | name = "Trap Instruction"; | |
1787 | else if (intno >= 0xc0) | |
1788 | name = "Window Fill"; | |
1789 | else if (intno >= 0x80) | |
1790 | name = "Window Spill"; | |
1791 | else { | |
1792 | name = excp_names[intno]; | |
1793 | if (!name) | |
1794 | name = "Unknown"; | |
1795 | } | |
1796 | ||
1797 | fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64 | |
1798 | " SP=%016" PRIx64 "\n", | |
1799 | count, name, intno, | |
ee5bbe38 FB |
1800 | env->pc, |
1801 | env->npc, env->regwptr[6]); | |
0f8a249a | 1802 | cpu_dump_state(env, logfile, fprintf, 0); |
ee5bbe38 | 1803 | #if 0 |
0f8a249a BS |
1804 | { |
1805 | int i; | |
1806 | uint8_t *ptr; | |
1807 | ||
1808 | fprintf(logfile, " code="); | |
1809 | ptr = (uint8_t *)env->pc; | |
1810 | for(i = 0; i < 16; i++) { | |
1811 | fprintf(logfile, " %02x", ldub(ptr + i)); | |
1812 | } | |
1813 | fprintf(logfile, "\n"); | |
1814 | } | |
ee5bbe38 | 1815 | #endif |
0f8a249a | 1816 | count++; |
ee5bbe38 FB |
1817 | } |
1818 | #endif | |
5fafdf24 | 1819 | #if !defined(CONFIG_USER_ONLY) |
83469015 | 1820 | if (env->tl == MAXTL) { |
c68ea704 | 1821 | cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index); |
0f8a249a | 1822 | return; |
ee5bbe38 FB |
1823 | } |
1824 | #endif | |
375ee38b BS |
1825 | env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) | |
1826 | ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | | |
1827 | GET_CWP64(env); | |
1828 | env->tsptr->tpc = env->pc; | |
1829 | env->tsptr->tnpc = env->npc; | |
1830 | env->tsptr->tt = intno; | |
8f1f22f6 BS |
1831 | change_pstate(PS_PEF | PS_PRIV | PS_AG); |
1832 | ||
1833 | if (intno == TT_CLRWIN) | |
1834 | set_cwp((env->cwp - 1) & (NWINDOWS - 1)); | |
1835 | else if ((intno & 0x1c0) == TT_SPILL) | |
1836 | set_cwp((env->cwp - env->cansave - 2) & (NWINDOWS - 1)); | |
1837 | else if ((intno & 0x1c0) == TT_FILL) | |
1838 | set_cwp((env->cwp + 1) & (NWINDOWS - 1)); | |
83469015 FB |
1839 | env->tbr &= ~0x7fffULL; |
1840 | env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); | |
1841 | if (env->tl < MAXTL - 1) { | |
0f8a249a | 1842 | env->tl++; |
83469015 | 1843 | } else { |
0f8a249a BS |
1844 | env->pstate |= PS_RED; |
1845 | if (env->tl != MAXTL) | |
1846 | env->tl++; | |
83469015 | 1847 | } |
375ee38b | 1848 | env->tsptr = &env->ts[env->tl]; |
ee5bbe38 FB |
1849 | env->pc = env->tbr; |
1850 | env->npc = env->pc + 4; | |
1851 | env->exception_index = 0; | |
1852 | } | |
1853 | #else | |
0b09be2b BS |
1854 | #ifdef DEBUG_PCALL |
1855 | static const char * const excp_names[0x80] = { | |
1856 | [TT_TFAULT] = "Instruction Access Fault", | |
1857 | [TT_ILL_INSN] = "Illegal Instruction", | |
1858 | [TT_PRIV_INSN] = "Privileged Instruction", | |
1859 | [TT_NFPU_INSN] = "FPU Disabled", | |
1860 | [TT_WIN_OVF] = "Window Overflow", | |
1861 | [TT_WIN_UNF] = "Window Underflow", | |
1862 | [TT_UNALIGNED] = "Unaligned Memory Access", | |
1863 | [TT_FP_EXCP] = "FPU Exception", | |
1864 | [TT_DFAULT] = "Data Access Fault", | |
1865 | [TT_TOVF] = "Tag Overflow", | |
1866 | [TT_EXTINT | 0x1] = "External Interrupt 1", | |
1867 | [TT_EXTINT | 0x2] = "External Interrupt 2", | |
1868 | [TT_EXTINT | 0x3] = "External Interrupt 3", | |
1869 | [TT_EXTINT | 0x4] = "External Interrupt 4", | |
1870 | [TT_EXTINT | 0x5] = "External Interrupt 5", | |
1871 | [TT_EXTINT | 0x6] = "External Interrupt 6", | |
1872 | [TT_EXTINT | 0x7] = "External Interrupt 7", | |
1873 | [TT_EXTINT | 0x8] = "External Interrupt 8", | |
1874 | [TT_EXTINT | 0x9] = "External Interrupt 9", | |
1875 | [TT_EXTINT | 0xa] = "External Interrupt 10", | |
1876 | [TT_EXTINT | 0xb] = "External Interrupt 11", | |
1877 | [TT_EXTINT | 0xc] = "External Interrupt 12", | |
1878 | [TT_EXTINT | 0xd] = "External Interrupt 13", | |
1879 | [TT_EXTINT | 0xe] = "External Interrupt 14", | |
1880 | [TT_EXTINT | 0xf] = "External Interrupt 15", | |
1881 | [TT_TOVF] = "Tag Overflow", | |
1882 | [TT_CODE_ACCESS] = "Instruction Access Error", | |
1883 | [TT_DATA_ACCESS] = "Data Access Error", | |
1884 | [TT_DIV_ZERO] = "Division By Zero", | |
1885 | [TT_NCP_INSN] = "Coprocessor Disabled", | |
1886 | }; | |
1887 | #endif | |
1888 | ||
ee5bbe38 FB |
1889 | void do_interrupt(int intno) |
1890 | { | |
1891 | int cwp; | |
1892 | ||
1893 | #ifdef DEBUG_PCALL | |
1894 | if (loglevel & CPU_LOG_INT) { | |
0f8a249a | 1895 | static int count; |
0b09be2b BS |
1896 | const char *name; |
1897 | ||
1898 | if (intno < 0 || intno >= 0x100) | |
1899 | name = "Unknown"; | |
1900 | else if (intno >= 0x80) | |
1901 | name = "Trap Instruction"; | |
1902 | else { | |
1903 | name = excp_names[intno]; | |
1904 | if (!name) | |
1905 | name = "Unknown"; | |
1906 | } | |
1907 | ||
1908 | fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n", | |
1909 | count, name, intno, | |
ee5bbe38 FB |
1910 | env->pc, |
1911 | env->npc, env->regwptr[6]); | |
0f8a249a | 1912 | cpu_dump_state(env, logfile, fprintf, 0); |
ee5bbe38 | 1913 | #if 0 |
0f8a249a BS |
1914 | { |
1915 | int i; | |
1916 | uint8_t *ptr; | |
1917 | ||
1918 | fprintf(logfile, " code="); | |
1919 | ptr = (uint8_t *)env->pc; | |
1920 | for(i = 0; i < 16; i++) { | |
1921 | fprintf(logfile, " %02x", ldub(ptr + i)); | |
1922 | } | |
1923 | fprintf(logfile, "\n"); | |
1924 | } | |
ee5bbe38 | 1925 | #endif |
0f8a249a | 1926 | count++; |
ee5bbe38 FB |
1927 | } |
1928 | #endif | |
5fafdf24 | 1929 | #if !defined(CONFIG_USER_ONLY) |
ee5bbe38 | 1930 | if (env->psret == 0) { |
c68ea704 | 1931 | cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index); |
0f8a249a | 1932 | return; |
ee5bbe38 FB |
1933 | } |
1934 | #endif | |
1935 | env->psret = 0; | |
5fafdf24 | 1936 | cwp = (env->cwp - 1) & (NWINDOWS - 1); |
ee5bbe38 FB |
1937 | set_cwp(cwp); |
1938 | env->regwptr[9] = env->pc; | |
1939 | env->regwptr[10] = env->npc; | |
1940 | env->psrps = env->psrs; | |
1941 | env->psrs = 1; | |
1942 | env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4); | |
1943 | env->pc = env->tbr; | |
1944 | env->npc = env->pc + 4; | |
1945 | env->exception_index = 0; | |
1946 | } | |
1947 | #endif | |
1948 | ||
5fafdf24 | 1949 | #if !defined(CONFIG_USER_ONLY) |
ee5bbe38 | 1950 | |
d2889a3e BS |
1951 | static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
1952 | void *retaddr); | |
1953 | ||
ee5bbe38 | 1954 | #define MMUSUFFIX _mmu |
d2889a3e | 1955 | #define ALIGNED_ONLY |
273af660 TS |
1956 | #ifdef __s390__ |
1957 | # define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL)) | |
1958 | #else | |
1959 | # define GETPC() (__builtin_return_address(0)) | |
1960 | #endif | |
ee5bbe38 FB |
1961 | |
1962 | #define SHIFT 0 | |
1963 | #include "softmmu_template.h" | |
1964 | ||
1965 | #define SHIFT 1 | |
1966 | #include "softmmu_template.h" | |
1967 | ||
1968 | #define SHIFT 2 | |
1969 | #include "softmmu_template.h" | |
1970 | ||
1971 | #define SHIFT 3 | |
1972 | #include "softmmu_template.h" | |
1973 | ||
d2889a3e BS |
1974 | static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
1975 | void *retaddr) | |
1976 | { | |
94554550 BS |
1977 | #ifdef DEBUG_UNALIGNED |
1978 | printf("Unaligned access to 0x%x from 0x%x\n", addr, env->pc); | |
1979 | #endif | |
1980 | raise_exception(TT_UNALIGNED); | |
d2889a3e | 1981 | } |
ee5bbe38 FB |
1982 | |
1983 | /* try to fill the TLB and return an exception if error. If retaddr is | |
1984 | NULL, it means that the function was called in C code (i.e. not | |
1985 | from generated code or from helper.c) */ | |
1986 | /* XXX: fix it to restore all registers */ | |
6ebbf390 | 1987 | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
ee5bbe38 FB |
1988 | { |
1989 | TranslationBlock *tb; | |
1990 | int ret; | |
1991 | unsigned long pc; | |
1992 | CPUState *saved_env; | |
1993 | ||
1994 | /* XXX: hack to restore env in all cases, even if not called from | |
1995 | generated code */ | |
1996 | saved_env = env; | |
1997 | env = cpu_single_env; | |
1998 | ||
6ebbf390 | 1999 | ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1); |
ee5bbe38 FB |
2000 | if (ret) { |
2001 | if (retaddr) { | |
2002 | /* now we have a real cpu fault */ | |
2003 | pc = (unsigned long)retaddr; | |
2004 | tb = tb_find_pc(pc); | |
2005 | if (tb) { | |
2006 | /* the PC is inside the translated code. It means that we have | |
2007 | a virtual CPU fault */ | |
2008 | cpu_restore_state(tb, env, pc, (void *)T2); | |
2009 | } | |
2010 | } | |
2011 | cpu_loop_exit(); | |
2012 | } | |
2013 | env = saved_env; | |
2014 | } | |
2015 | ||
2016 | #endif | |
6c36d3fa BS |
2017 | |
2018 | #ifndef TARGET_SPARC64 | |
5dcb6b91 | 2019 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
6c36d3fa BS |
2020 | int is_asi) |
2021 | { | |
2022 | CPUState *saved_env; | |
2023 | ||
2024 | /* XXX: hack to restore env in all cases, even if not called from | |
2025 | generated code */ | |
2026 | saved_env = env; | |
2027 | env = cpu_single_env; | |
8543e2cf BS |
2028 | #ifdef DEBUG_UNASSIGNED |
2029 | if (is_asi) | |
2030 | printf("Unassigned mem %s access to " TARGET_FMT_plx " asi 0x%02x from " | |
2031 | TARGET_FMT_lx "\n", | |
2032 | is_exec ? "exec" : is_write ? "write" : "read", addr, is_asi, | |
2033 | env->pc); | |
2034 | else | |
2035 | printf("Unassigned mem %s access to " TARGET_FMT_plx " from " | |
2036 | TARGET_FMT_lx "\n", | |
2037 | is_exec ? "exec" : is_write ? "write" : "read", addr, env->pc); | |
2038 | #endif | |
6c36d3fa | 2039 | if (env->mmuregs[3]) /* Fault status register */ |
0f8a249a | 2040 | env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
6c36d3fa BS |
2041 | if (is_asi) |
2042 | env->mmuregs[3] |= 1 << 16; | |
2043 | if (env->psrs) | |
2044 | env->mmuregs[3] |= 1 << 5; | |
2045 | if (is_exec) | |
2046 | env->mmuregs[3] |= 1 << 6; | |
2047 | if (is_write) | |
2048 | env->mmuregs[3] |= 1 << 7; | |
2049 | env->mmuregs[3] |= (5 << 2) | 2; | |
2050 | env->mmuregs[4] = addr; /* Fault address register */ | |
2051 | if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { | |
1b2e93c1 BS |
2052 | if (is_exec) |
2053 | raise_exception(TT_CODE_ACCESS); | |
2054 | else | |
2055 | raise_exception(TT_DATA_ACCESS); | |
6c36d3fa BS |
2056 | } |
2057 | env = saved_env; | |
2058 | } | |
2059 | #else | |
5dcb6b91 | 2060 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
6c36d3fa BS |
2061 | int is_asi) |
2062 | { | |
2063 | #ifdef DEBUG_UNASSIGNED | |
2064 | CPUState *saved_env; | |
2065 | ||
2066 | /* XXX: hack to restore env in all cases, even if not called from | |
2067 | generated code */ | |
2068 | saved_env = env; | |
2069 | env = cpu_single_env; | |
5dcb6b91 | 2070 | printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n", |
6c36d3fa BS |
2071 | addr, env->pc); |
2072 | env = saved_env; | |
2073 | #endif | |
1b2e93c1 BS |
2074 | if (is_exec) |
2075 | raise_exception(TT_CODE_ACCESS); | |
2076 | else | |
2077 | raise_exception(TT_DATA_ACCESS); | |
6c36d3fa BS |
2078 | } |
2079 | #endif | |
20c9f095 | 2080 |