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Commit | Line | Data |
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e8af50a3 FB |
1 | #include "exec.h" |
2 | ||
83469015 | 3 | //#define DEBUG_PCALL |
e80cfcfc | 4 | //#define DEBUG_MMU |
952a328f | 5 | //#define DEBUG_MXCC |
94554550 | 6 | //#define DEBUG_UNALIGNED |
6c36d3fa | 7 | //#define DEBUG_UNASSIGNED |
e80cfcfc | 8 | |
952a328f BS |
9 | #ifdef DEBUG_MMU |
10 | #define DPRINTF_MMU(fmt, args...) \ | |
11 | do { printf("MMU: " fmt , ##args); } while (0) | |
12 | #else | |
13 | #define DPRINTF_MMU(fmt, args...) | |
14 | #endif | |
15 | ||
16 | #ifdef DEBUG_MXCC | |
17 | #define DPRINTF_MXCC(fmt, args...) \ | |
18 | do { printf("MXCC: " fmt , ##args); } while (0) | |
19 | #else | |
20 | #define DPRINTF_MXCC(fmt, args...) | |
21 | #endif | |
22 | ||
9d893301 FB |
23 | void raise_exception(int tt) |
24 | { | |
25 | env->exception_index = tt; | |
26 | cpu_loop_exit(); | |
3b46e624 | 27 | } |
9d893301 | 28 | |
417454b0 BS |
29 | void check_ieee_exceptions() |
30 | { | |
31 | T0 = get_float_exception_flags(&env->fp_status); | |
32 | if (T0) | |
33 | { | |
0f8a249a BS |
34 | /* Copy IEEE 754 flags into FSR */ |
35 | if (T0 & float_flag_invalid) | |
36 | env->fsr |= FSR_NVC; | |
37 | if (T0 & float_flag_overflow) | |
38 | env->fsr |= FSR_OFC; | |
39 | if (T0 & float_flag_underflow) | |
40 | env->fsr |= FSR_UFC; | |
41 | if (T0 & float_flag_divbyzero) | |
42 | env->fsr |= FSR_DZC; | |
43 | if (T0 & float_flag_inexact) | |
44 | env->fsr |= FSR_NXC; | |
45 | ||
46 | if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) | |
47 | { | |
48 | /* Unmasked exception, generate a trap */ | |
49 | env->fsr |= FSR_FTT_IEEE_EXCP; | |
50 | raise_exception(TT_FP_EXCP); | |
51 | } | |
52 | else | |
53 | { | |
54 | /* Accumulate exceptions */ | |
55 | env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5; | |
56 | } | |
417454b0 BS |
57 | } |
58 | } | |
59 | ||
a0c4cb4a FB |
60 | #ifdef USE_INT_TO_FLOAT_HELPERS |
61 | void do_fitos(void) | |
62 | { | |
417454b0 | 63 | set_float_exception_flags(0, &env->fp_status); |
ec230928 | 64 | FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status); |
417454b0 | 65 | check_ieee_exceptions(); |
a0c4cb4a FB |
66 | } |
67 | ||
68 | void do_fitod(void) | |
69 | { | |
ec230928 | 70 | DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status); |
a0c4cb4a FB |
71 | } |
72 | #endif | |
73 | ||
74 | void do_fabss(void) | |
e8af50a3 | 75 | { |
7a0e1f41 | 76 | FT0 = float32_abs(FT1); |
e8af50a3 FB |
77 | } |
78 | ||
3475187d FB |
79 | #ifdef TARGET_SPARC64 |
80 | void do_fabsd(void) | |
81 | { | |
82 | DT0 = float64_abs(DT1); | |
83 | } | |
84 | #endif | |
85 | ||
a0c4cb4a | 86 | void do_fsqrts(void) |
e8af50a3 | 87 | { |
417454b0 | 88 | set_float_exception_flags(0, &env->fp_status); |
7a0e1f41 | 89 | FT0 = float32_sqrt(FT1, &env->fp_status); |
417454b0 | 90 | check_ieee_exceptions(); |
e8af50a3 FB |
91 | } |
92 | ||
a0c4cb4a | 93 | void do_fsqrtd(void) |
e8af50a3 | 94 | { |
417454b0 | 95 | set_float_exception_flags(0, &env->fp_status); |
7a0e1f41 | 96 | DT0 = float64_sqrt(DT1, &env->fp_status); |
417454b0 | 97 | check_ieee_exceptions(); |
e8af50a3 FB |
98 | } |
99 | ||
417454b0 | 100 | #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \ |
65ce8c2f FB |
101 | void glue(do_, name) (void) \ |
102 | { \ | |
103 | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ | |
104 | switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \ | |
105 | case float_relation_unordered: \ | |
106 | T0 = (FSR_FCC1 | FSR_FCC0) << FS; \ | |
417454b0 | 107 | if ((env->fsr & FSR_NVM) || TRAP) { \ |
65ce8c2f | 108 | env->fsr |= T0; \ |
417454b0 BS |
109 | env->fsr |= FSR_NVC; \ |
110 | env->fsr |= FSR_FTT_IEEE_EXCP; \ | |
65ce8c2f FB |
111 | raise_exception(TT_FP_EXCP); \ |
112 | } else { \ | |
113 | env->fsr |= FSR_NVA; \ | |
114 | } \ | |
115 | break; \ | |
116 | case float_relation_less: \ | |
117 | T0 = FSR_FCC0 << FS; \ | |
118 | break; \ | |
119 | case float_relation_greater: \ | |
120 | T0 = FSR_FCC1 << FS; \ | |
121 | break; \ | |
122 | default: \ | |
123 | T0 = 0; \ | |
124 | break; \ | |
125 | } \ | |
126 | env->fsr |= T0; \ | |
e8af50a3 | 127 | } |
e8af50a3 | 128 | |
417454b0 BS |
129 | GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0); |
130 | GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0); | |
131 | ||
132 | GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1); | |
133 | GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1); | |
3475187d FB |
134 | |
135 | #ifdef TARGET_SPARC64 | |
417454b0 BS |
136 | GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0); |
137 | GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0); | |
138 | ||
139 | GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0); | |
140 | GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0); | |
141 | ||
142 | GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0); | |
143 | GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0); | |
144 | ||
145 | GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1); | |
146 | GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1); | |
3475187d | 147 | |
417454b0 BS |
148 | GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1); |
149 | GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1); | |
3475187d | 150 | |
417454b0 BS |
151 | GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1); |
152 | GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1); | |
3475187d FB |
153 | #endif |
154 | ||
155 | #ifndef TARGET_SPARC64 | |
81ad8ba2 | 156 | #ifndef CONFIG_USER_ONLY |
952a328f BS |
157 | |
158 | #ifdef DEBUG_MXCC | |
159 | static void dump_mxcc(CPUState *env) | |
160 | { | |
161 | printf("mxccdata: %016llx %016llx %016llx %016llx\n", | |
162 | env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]); | |
163 | printf("mxccregs: %016llx %016llx %016llx %016llx\n" | |
164 | " %016llx %016llx %016llx %016llx\n", | |
165 | env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3], | |
166 | env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]); | |
167 | } | |
168 | #endif | |
169 | ||
a0c4cb4a | 170 | void helper_ld_asi(int asi, int size, int sign) |
e8af50a3 | 171 | { |
83469015 | 172 | uint32_t ret = 0; |
e909ec2f | 173 | uint64_t tmp; |
952a328f BS |
174 | #ifdef DEBUG_MXCC |
175 | uint32_t last_T0 = T0; | |
176 | #endif | |
e80cfcfc FB |
177 | |
178 | switch (asi) { | |
6c36d3fa | 179 | case 2: /* SuperSparc MXCC registers */ |
952a328f BS |
180 | switch (T0) { |
181 | case 0x01c00a00: /* MXCC control register */ | |
182 | if (size == 8) { | |
183 | ret = env->mxccregs[3]; | |
184 | T0 = env->mxccregs[3] >> 32; | |
185 | } else | |
186 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); | |
187 | break; | |
188 | case 0x01c00a04: /* MXCC control register */ | |
189 | if (size == 4) | |
190 | ret = env->mxccregs[3]; | |
191 | else | |
192 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); | |
193 | break; | |
194 | case 0x01c00f00: /* MBus port address register */ | |
195 | if (size == 8) { | |
196 | ret = env->mxccregs[7]; | |
197 | T0 = env->mxccregs[7] >> 32; | |
198 | } else | |
199 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); | |
200 | break; | |
201 | default: | |
202 | DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size); | |
203 | break; | |
204 | } | |
205 | DPRINTF_MXCC("asi = %d, size = %d, sign = %d, T0 = %08x -> ret = %08x," | |
206 | "T0 = %08x\n", asi, size, sign, last_T0, ret, T0); | |
207 | #ifdef DEBUG_MXCC | |
208 | dump_mxcc(env); | |
209 | #endif | |
6c36d3fa | 210 | break; |
e8af50a3 | 211 | case 3: /* MMU probe */ |
0f8a249a BS |
212 | { |
213 | int mmulev; | |
214 | ||
215 | mmulev = (T0 >> 8) & 15; | |
216 | if (mmulev > 4) | |
217 | ret = 0; | |
218 | else { | |
219 | ret = mmu_probe(env, T0, mmulev); | |
220 | //bswap32s(&ret); | |
221 | } | |
952a328f | 222 | DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret); |
0f8a249a BS |
223 | } |
224 | break; | |
e8af50a3 | 225 | case 4: /* read MMU regs */ |
0f8a249a BS |
226 | { |
227 | int reg = (T0 >> 8) & 0xf; | |
3b46e624 | 228 | |
0f8a249a BS |
229 | ret = env->mmuregs[reg]; |
230 | if (reg == 3) /* Fault status cleared on read */ | |
231 | env->mmuregs[reg] = 0; | |
952a328f | 232 | DPRINTF_MMU("mmu_read: reg[%d] = 0x%08x\n", reg, ret); |
0f8a249a BS |
233 | } |
234 | break; | |
6c36d3fa BS |
235 | case 9: /* Supervisor code access */ |
236 | switch(size) { | |
237 | case 1: | |
238 | ret = ldub_code(T0); | |
239 | break; | |
240 | case 2: | |
241 | ret = lduw_code(T0 & ~1); | |
242 | break; | |
243 | default: | |
244 | case 4: | |
245 | ret = ldl_code(T0 & ~3); | |
246 | break; | |
247 | case 8: | |
e909ec2f BS |
248 | tmp = ldq_code(T0 & ~7); |
249 | ret = tmp >> 32; | |
250 | T0 = tmp & 0xffffffff; | |
6c36d3fa BS |
251 | break; |
252 | } | |
253 | break; | |
81ad8ba2 BS |
254 | case 0xa: /* User data access */ |
255 | switch(size) { | |
256 | case 1: | |
257 | ret = ldub_user(T0); | |
258 | break; | |
259 | case 2: | |
260 | ret = lduw_user(T0 & ~1); | |
261 | break; | |
262 | default: | |
263 | case 4: | |
264 | ret = ldl_user(T0 & ~3); | |
265 | break; | |
266 | case 8: | |
e909ec2f BS |
267 | tmp = ldq_user(T0 & ~7); |
268 | ret = tmp >> 32; | |
269 | T0 = tmp & 0xffffffff; | |
81ad8ba2 BS |
270 | break; |
271 | } | |
272 | break; | |
273 | case 0xb: /* Supervisor data access */ | |
274 | switch(size) { | |
275 | case 1: | |
276 | ret = ldub_kernel(T0); | |
277 | break; | |
278 | case 2: | |
279 | ret = lduw_kernel(T0 & ~1); | |
280 | break; | |
281 | default: | |
282 | case 4: | |
283 | ret = ldl_kernel(T0 & ~3); | |
284 | break; | |
285 | case 8: | |
e909ec2f BS |
286 | tmp = ldq_kernel(T0 & ~7); |
287 | ret = tmp >> 32; | |
288 | T0 = tmp & 0xffffffff; | |
81ad8ba2 BS |
289 | break; |
290 | } | |
291 | break; | |
6c36d3fa BS |
292 | case 0xc: /* I-cache tag */ |
293 | case 0xd: /* I-cache data */ | |
294 | case 0xe: /* D-cache tag */ | |
295 | case 0xf: /* D-cache data */ | |
296 | break; | |
297 | case 0x20: /* MMU passthrough */ | |
02aab46a FB |
298 | switch(size) { |
299 | case 1: | |
300 | ret = ldub_phys(T0); | |
301 | break; | |
302 | case 2: | |
303 | ret = lduw_phys(T0 & ~1); | |
304 | break; | |
305 | default: | |
306 | case 4: | |
307 | ret = ldl_phys(T0 & ~3); | |
308 | break; | |
9e61bde5 | 309 | case 8: |
e909ec2f BS |
310 | tmp = ldq_phys(T0 & ~7); |
311 | ret = tmp >> 32; | |
312 | T0 = tmp & 0xffffffff; | |
0f8a249a | 313 | break; |
02aab46a | 314 | } |
0f8a249a | 315 | break; |
5dcb6b91 BS |
316 | case 0x2e: /* MMU passthrough, 0xexxxxxxxx */ |
317 | case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */ | |
318 | switch(size) { | |
319 | case 1: | |
320 | ret = ldub_phys((target_phys_addr_t)T0 | |
321 | | ((target_phys_addr_t)(asi & 0xf) << 32)); | |
322 | break; | |
323 | case 2: | |
324 | ret = lduw_phys((target_phys_addr_t)(T0 & ~1) | |
325 | | ((target_phys_addr_t)(asi & 0xf) << 32)); | |
326 | break; | |
327 | default: | |
328 | case 4: | |
329 | ret = ldl_phys((target_phys_addr_t)(T0 & ~3) | |
330 | | ((target_phys_addr_t)(asi & 0xf) << 32)); | |
331 | break; | |
332 | case 8: | |
e909ec2f | 333 | tmp = ldq_phys((target_phys_addr_t)(T0 & ~7) |
5dcb6b91 | 334 | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
e909ec2f BS |
335 | ret = tmp >> 32; |
336 | T0 = tmp & 0xffffffff; | |
0f8a249a | 337 | break; |
5dcb6b91 | 338 | } |
0f8a249a | 339 | break; |
5dcb6b91 | 340 | case 0x21 ... 0x2d: /* MMU passthrough, unassigned */ |
e8af50a3 | 341 | default: |
6c36d3fa | 342 | do_unassigned_access(T0, 0, 0, 1); |
0f8a249a BS |
343 | ret = 0; |
344 | break; | |
e8af50a3 | 345 | } |
81ad8ba2 BS |
346 | if (sign) { |
347 | switch(size) { | |
348 | case 1: | |
349 | T1 = (int8_t) ret; | |
e32664fb | 350 | break; |
81ad8ba2 BS |
351 | case 2: |
352 | T1 = (int16_t) ret; | |
e32664fb | 353 | break; |
81ad8ba2 BS |
354 | default: |
355 | T1 = ret; | |
356 | break; | |
357 | } | |
358 | } | |
359 | else | |
360 | T1 = ret; | |
e8af50a3 FB |
361 | } |
362 | ||
81ad8ba2 | 363 | void helper_st_asi(int asi, int size) |
e8af50a3 FB |
364 | { |
365 | switch(asi) { | |
6c36d3fa | 366 | case 2: /* SuperSparc MXCC registers */ |
952a328f BS |
367 | switch (T0) { |
368 | case 0x01c00000: /* MXCC stream data register 0 */ | |
369 | if (size == 8) | |
370 | env->mxccdata[0] = ((uint64_t)T1 << 32) | T2; | |
371 | else | |
372 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); | |
373 | break; | |
374 | case 0x01c00008: /* MXCC stream data register 1 */ | |
375 | if (size == 8) | |
376 | env->mxccdata[1] = ((uint64_t)T1 << 32) | T2; | |
377 | else | |
378 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); | |
379 | break; | |
380 | case 0x01c00010: /* MXCC stream data register 2 */ | |
381 | if (size == 8) | |
382 | env->mxccdata[2] = ((uint64_t)T1 << 32) | T2; | |
383 | else | |
384 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); | |
385 | break; | |
386 | case 0x01c00018: /* MXCC stream data register 3 */ | |
387 | if (size == 8) | |
388 | env->mxccdata[3] = ((uint64_t)T1 << 32) | T2; | |
389 | else | |
390 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); | |
391 | break; | |
392 | case 0x01c00100: /* MXCC stream source */ | |
393 | if (size == 8) | |
394 | env->mxccregs[0] = ((uint64_t)T1 << 32) | T2; | |
395 | else | |
396 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); | |
397 | env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0); | |
398 | env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8); | |
399 | env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16); | |
400 | env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 24); | |
401 | break; | |
402 | case 0x01c00200: /* MXCC stream destination */ | |
403 | if (size == 8) | |
404 | env->mxccregs[1] = ((uint64_t)T1 << 32) | T2; | |
405 | else | |
406 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); | |
407 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]); | |
408 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]); | |
409 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]); | |
410 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, env->mxccdata[3]); | |
411 | break; | |
412 | case 0x01c00a00: /* MXCC control register */ | |
413 | if (size == 8) | |
414 | env->mxccregs[3] = ((uint64_t)T1 << 32) | T2; | |
415 | else | |
416 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); | |
417 | break; | |
418 | case 0x01c00a04: /* MXCC control register */ | |
419 | if (size == 4) | |
420 | env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000) | T1; | |
421 | else | |
422 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); | |
423 | break; | |
424 | case 0x01c00e00: /* MXCC error register */ | |
425 | if (size == 8) | |
426 | env->mxccregs[6] = ((uint64_t)T1 << 32) | T2; | |
427 | else | |
428 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); | |
429 | if (env->mxccregs[6] == 0xffffffffffffffffULL) { | |
430 | // this is probably a reset | |
431 | } | |
432 | break; | |
433 | case 0x01c00f00: /* MBus port address register */ | |
434 | if (size == 8) | |
435 | env->mxccregs[7] = ((uint64_t)T1 << 32) | T2; | |
436 | else | |
437 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); | |
438 | break; | |
439 | default: | |
440 | DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size); | |
441 | break; | |
442 | } | |
443 | DPRINTF_MXCC("asi = %d, size = %d, T0 = %08x, T1 = %08x\n", asi, size, T0, T1); | |
444 | #ifdef DEBUG_MXCC | |
445 | dump_mxcc(env); | |
446 | #endif | |
6c36d3fa | 447 | break; |
e8af50a3 | 448 | case 3: /* MMU flush */ |
0f8a249a BS |
449 | { |
450 | int mmulev; | |
e80cfcfc | 451 | |
0f8a249a | 452 | mmulev = (T0 >> 8) & 15; |
952a328f | 453 | DPRINTF_MMU("mmu flush level %d\n", mmulev); |
0f8a249a BS |
454 | switch (mmulev) { |
455 | case 0: // flush page | |
456 | tlb_flush_page(env, T0 & 0xfffff000); | |
457 | break; | |
458 | case 1: // flush segment (256k) | |
459 | case 2: // flush region (16M) | |
460 | case 3: // flush context (4G) | |
461 | case 4: // flush entire | |
462 | tlb_flush(env, 1); | |
463 | break; | |
464 | default: | |
465 | break; | |
466 | } | |
55754d9e | 467 | #ifdef DEBUG_MMU |
0f8a249a | 468 | dump_mmu(env); |
55754d9e | 469 | #endif |
0f8a249a BS |
470 | return; |
471 | } | |
e8af50a3 | 472 | case 4: /* write MMU regs */ |
0f8a249a BS |
473 | { |
474 | int reg = (T0 >> 8) & 0xf; | |
475 | uint32_t oldreg; | |
3b46e624 | 476 | |
0f8a249a | 477 | oldreg = env->mmuregs[reg]; |
55754d9e FB |
478 | switch(reg) { |
479 | case 0: | |
40ce0a9a BS |
480 | env->mmuregs[reg] &= ~(MMU_E | MMU_NF | MMU_BM); |
481 | env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | MMU_BM); | |
0f8a249a BS |
482 | // Mappings generated during no-fault mode or MMU |
483 | // disabled mode are invalid in normal mode | |
6f7e9aec | 484 | if (oldreg != env->mmuregs[reg]) |
55754d9e FB |
485 | tlb_flush(env, 1); |
486 | break; | |
487 | case 2: | |
0f8a249a | 488 | env->mmuregs[reg] = T1; |
55754d9e FB |
489 | if (oldreg != env->mmuregs[reg]) { |
490 | /* we flush when the MMU context changes because | |
491 | QEMU has no MMU context support */ | |
492 | tlb_flush(env, 1); | |
493 | } | |
494 | break; | |
495 | case 3: | |
496 | case 4: | |
497 | break; | |
498 | default: | |
0f8a249a | 499 | env->mmuregs[reg] = T1; |
55754d9e FB |
500 | break; |
501 | } | |
55754d9e | 502 | if (oldreg != env->mmuregs[reg]) { |
952a328f | 503 | DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]); |
55754d9e | 504 | } |
952a328f | 505 | #ifdef DEBUG_MMU |
0f8a249a | 506 | dump_mmu(env); |
55754d9e | 507 | #endif |
0f8a249a BS |
508 | return; |
509 | } | |
81ad8ba2 BS |
510 | case 0xa: /* User data access */ |
511 | switch(size) { | |
512 | case 1: | |
513 | stb_user(T0, T1); | |
514 | break; | |
515 | case 2: | |
516 | stw_user(T0 & ~1, T1); | |
517 | break; | |
518 | default: | |
519 | case 4: | |
520 | stl_user(T0 & ~3, T1); | |
521 | break; | |
522 | case 8: | |
e909ec2f | 523 | stq_user(T0 & ~7, ((uint64_t)T1 << 32) | T2); |
81ad8ba2 BS |
524 | break; |
525 | } | |
526 | break; | |
527 | case 0xb: /* Supervisor data access */ | |
528 | switch(size) { | |
529 | case 1: | |
530 | stb_kernel(T0, T1); | |
531 | break; | |
532 | case 2: | |
533 | stw_kernel(T0 & ~1, T1); | |
534 | break; | |
535 | default: | |
536 | case 4: | |
537 | stl_kernel(T0 & ~3, T1); | |
538 | break; | |
539 | case 8: | |
e909ec2f | 540 | stq_kernel(T0 & ~7, ((uint64_t)T1 << 32) | T2); |
81ad8ba2 BS |
541 | break; |
542 | } | |
543 | break; | |
6c36d3fa BS |
544 | case 0xc: /* I-cache tag */ |
545 | case 0xd: /* I-cache data */ | |
546 | case 0xe: /* D-cache tag */ | |
547 | case 0xf: /* D-cache data */ | |
548 | case 0x10: /* I/D-cache flush page */ | |
549 | case 0x11: /* I/D-cache flush segment */ | |
550 | case 0x12: /* I/D-cache flush region */ | |
551 | case 0x13: /* I/D-cache flush context */ | |
552 | case 0x14: /* I/D-cache flush user */ | |
553 | break; | |
e80cfcfc | 554 | case 0x17: /* Block copy, sta access */ |
0f8a249a BS |
555 | { |
556 | // value (T1) = src | |
557 | // address (T0) = dst | |
558 | // copy 32 bytes | |
6c36d3fa BS |
559 | unsigned int i; |
560 | uint32_t src = T1 & ~3, dst = T0 & ~3, temp; | |
3b46e624 | 561 | |
6c36d3fa BS |
562 | for (i = 0; i < 32; i += 4, src += 4, dst += 4) { |
563 | temp = ldl_kernel(src); | |
564 | stl_kernel(dst, temp); | |
565 | } | |
0f8a249a BS |
566 | } |
567 | return; | |
e80cfcfc | 568 | case 0x1f: /* Block fill, stda access */ |
0f8a249a BS |
569 | { |
570 | // value (T1, T2) | |
571 | // address (T0) = dst | |
572 | // fill 32 bytes | |
6c36d3fa BS |
573 | unsigned int i; |
574 | uint32_t dst = T0 & 7; | |
575 | uint64_t val; | |
e80cfcfc | 576 | |
6c36d3fa BS |
577 | val = (((uint64_t)T1) << 32) | T2; |
578 | ||
579 | for (i = 0; i < 32; i += 8, dst += 8) | |
580 | stq_kernel(dst, val); | |
0f8a249a BS |
581 | } |
582 | return; | |
6c36d3fa | 583 | case 0x20: /* MMU passthrough */ |
0f8a249a | 584 | { |
02aab46a FB |
585 | switch(size) { |
586 | case 1: | |
587 | stb_phys(T0, T1); | |
588 | break; | |
589 | case 2: | |
590 | stw_phys(T0 & ~1, T1); | |
591 | break; | |
592 | case 4: | |
593 | default: | |
594 | stl_phys(T0 & ~3, T1); | |
595 | break; | |
9e61bde5 | 596 | case 8: |
e909ec2f | 597 | stq_phys(T0 & ~7, ((uint64_t)T1 << 32) | T2); |
9e61bde5 | 598 | break; |
02aab46a | 599 | } |
0f8a249a BS |
600 | } |
601 | return; | |
5dcb6b91 BS |
602 | case 0x2e: /* MMU passthrough, 0xexxxxxxxx */ |
603 | case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */ | |
0f8a249a | 604 | { |
5dcb6b91 BS |
605 | switch(size) { |
606 | case 1: | |
607 | stb_phys((target_phys_addr_t)T0 | |
608 | | ((target_phys_addr_t)(asi & 0xf) << 32), T1); | |
609 | break; | |
610 | case 2: | |
611 | stw_phys((target_phys_addr_t)(T0 & ~1) | |
612 | | ((target_phys_addr_t)(asi & 0xf) << 32), T1); | |
613 | break; | |
614 | case 4: | |
615 | default: | |
616 | stl_phys((target_phys_addr_t)(T0 & ~3) | |
617 | | ((target_phys_addr_t)(asi & 0xf) << 32), T1); | |
618 | break; | |
619 | case 8: | |
e909ec2f BS |
620 | stq_phys((target_phys_addr_t)(T0 & ~7) |
621 | | ((target_phys_addr_t)(asi & 0xf) << 32), | |
622 | ((uint64_t)T1 << 32) | T2); | |
5dcb6b91 BS |
623 | break; |
624 | } | |
0f8a249a BS |
625 | } |
626 | return; | |
6c36d3fa BS |
627 | case 0x31: /* Ross RT620 I-cache flush */ |
628 | case 0x36: /* I-cache flash clear */ | |
629 | case 0x37: /* D-cache flash clear */ | |
630 | break; | |
631 | case 9: /* Supervisor code access, XXX */ | |
5dcb6b91 | 632 | case 0x21 ... 0x2d: /* MMU passthrough, unassigned */ |
e8af50a3 | 633 | default: |
6c36d3fa | 634 | do_unassigned_access(T0, 1, 0, 1); |
0f8a249a | 635 | return; |
e8af50a3 FB |
636 | } |
637 | } | |
638 | ||
81ad8ba2 BS |
639 | #endif /* CONFIG_USER_ONLY */ |
640 | #else /* TARGET_SPARC64 */ | |
641 | ||
642 | #ifdef CONFIG_USER_ONLY | |
643 | void helper_ld_asi(int asi, int size, int sign) | |
644 | { | |
645 | uint64_t ret = 0; | |
646 | ||
647 | if (asi < 0x80) | |
648 | raise_exception(TT_PRIV_ACT); | |
649 | ||
650 | switch (asi) { | |
651 | case 0x80: // Primary | |
652 | case 0x82: // Primary no-fault | |
653 | case 0x88: // Primary LE | |
654 | case 0x8a: // Primary no-fault LE | |
655 | { | |
656 | switch(size) { | |
657 | case 1: | |
658 | ret = ldub_raw(T0); | |
659 | break; | |
660 | case 2: | |
661 | ret = lduw_raw(T0 & ~1); | |
662 | break; | |
663 | case 4: | |
664 | ret = ldl_raw(T0 & ~3); | |
665 | break; | |
666 | default: | |
667 | case 8: | |
668 | ret = ldq_raw(T0 & ~7); | |
669 | break; | |
670 | } | |
671 | } | |
672 | break; | |
673 | case 0x81: // Secondary | |
674 | case 0x83: // Secondary no-fault | |
675 | case 0x89: // Secondary LE | |
676 | case 0x8b: // Secondary no-fault LE | |
677 | // XXX | |
678 | break; | |
679 | default: | |
680 | break; | |
681 | } | |
682 | ||
683 | /* Convert from little endian */ | |
684 | switch (asi) { | |
685 | case 0x88: // Primary LE | |
686 | case 0x89: // Secondary LE | |
687 | case 0x8a: // Primary no-fault LE | |
688 | case 0x8b: // Secondary no-fault LE | |
689 | switch(size) { | |
690 | case 2: | |
691 | ret = bswap16(ret); | |
e32664fb | 692 | break; |
81ad8ba2 BS |
693 | case 4: |
694 | ret = bswap32(ret); | |
e32664fb | 695 | break; |
81ad8ba2 BS |
696 | case 8: |
697 | ret = bswap64(ret); | |
e32664fb | 698 | break; |
81ad8ba2 BS |
699 | default: |
700 | break; | |
701 | } | |
702 | default: | |
703 | break; | |
704 | } | |
705 | ||
706 | /* Convert to signed number */ | |
707 | if (sign) { | |
708 | switch(size) { | |
709 | case 1: | |
710 | ret = (int8_t) ret; | |
e32664fb | 711 | break; |
81ad8ba2 BS |
712 | case 2: |
713 | ret = (int16_t) ret; | |
e32664fb | 714 | break; |
81ad8ba2 BS |
715 | case 4: |
716 | ret = (int32_t) ret; | |
e32664fb | 717 | break; |
81ad8ba2 BS |
718 | default: |
719 | break; | |
720 | } | |
721 | } | |
722 | T1 = ret; | |
723 | } | |
724 | ||
725 | void helper_st_asi(int asi, int size) | |
726 | { | |
727 | if (asi < 0x80) | |
728 | raise_exception(TT_PRIV_ACT); | |
729 | ||
730 | /* Convert to little endian */ | |
731 | switch (asi) { | |
732 | case 0x88: // Primary LE | |
733 | case 0x89: // Secondary LE | |
734 | switch(size) { | |
735 | case 2: | |
736 | T0 = bswap16(T0); | |
e32664fb | 737 | break; |
81ad8ba2 BS |
738 | case 4: |
739 | T0 = bswap32(T0); | |
e32664fb | 740 | break; |
81ad8ba2 BS |
741 | case 8: |
742 | T0 = bswap64(T0); | |
e32664fb | 743 | break; |
81ad8ba2 BS |
744 | default: |
745 | break; | |
746 | } | |
747 | default: | |
748 | break; | |
749 | } | |
750 | ||
751 | switch(asi) { | |
752 | case 0x80: // Primary | |
753 | case 0x88: // Primary LE | |
754 | { | |
755 | switch(size) { | |
756 | case 1: | |
757 | stb_raw(T0, T1); | |
758 | break; | |
759 | case 2: | |
760 | stw_raw(T0 & ~1, T1); | |
761 | break; | |
762 | case 4: | |
763 | stl_raw(T0 & ~3, T1); | |
764 | break; | |
765 | case 8: | |
766 | default: | |
767 | stq_raw(T0 & ~7, T1); | |
768 | break; | |
769 | } | |
770 | } | |
771 | break; | |
772 | case 0x81: // Secondary | |
773 | case 0x89: // Secondary LE | |
774 | // XXX | |
775 | return; | |
776 | ||
777 | case 0x82: // Primary no-fault, RO | |
778 | case 0x83: // Secondary no-fault, RO | |
779 | case 0x8a: // Primary no-fault LE, RO | |
780 | case 0x8b: // Secondary no-fault LE, RO | |
781 | default: | |
782 | do_unassigned_access(T0, 1, 0, 1); | |
783 | return; | |
784 | } | |
785 | } | |
786 | ||
787 | #else /* CONFIG_USER_ONLY */ | |
3475187d FB |
788 | |
789 | void helper_ld_asi(int asi, int size, int sign) | |
790 | { | |
83469015 | 791 | uint64_t ret = 0; |
3475187d | 792 | |
6f27aba6 BS |
793 | if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
794 | || (asi >= 0x30 && asi < 0x80) && !(env->hpstate & HS_PRIV)) | |
0f8a249a | 795 | raise_exception(TT_PRIV_ACT); |
3475187d FB |
796 | |
797 | switch (asi) { | |
81ad8ba2 BS |
798 | case 0x10: // As if user primary |
799 | case 0x18: // As if user primary LE | |
800 | case 0x80: // Primary | |
801 | case 0x82: // Primary no-fault | |
802 | case 0x88: // Primary LE | |
803 | case 0x8a: // Primary no-fault LE | |
804 | if ((asi & 0x80) && (env->pstate & PS_PRIV)) { | |
6f27aba6 BS |
805 | if (env->hpstate & HS_PRIV) { |
806 | switch(size) { | |
807 | case 1: | |
808 | ret = ldub_hypv(T0); | |
809 | break; | |
810 | case 2: | |
811 | ret = lduw_hypv(T0 & ~1); | |
812 | break; | |
813 | case 4: | |
814 | ret = ldl_hypv(T0 & ~3); | |
815 | break; | |
816 | default: | |
817 | case 8: | |
818 | ret = ldq_hypv(T0 & ~7); | |
819 | break; | |
820 | } | |
821 | } else { | |
822 | switch(size) { | |
823 | case 1: | |
824 | ret = ldub_kernel(T0); | |
825 | break; | |
826 | case 2: | |
827 | ret = lduw_kernel(T0 & ~1); | |
828 | break; | |
829 | case 4: | |
830 | ret = ldl_kernel(T0 & ~3); | |
831 | break; | |
832 | default: | |
833 | case 8: | |
834 | ret = ldq_kernel(T0 & ~7); | |
835 | break; | |
836 | } | |
81ad8ba2 BS |
837 | } |
838 | } else { | |
839 | switch(size) { | |
840 | case 1: | |
841 | ret = ldub_user(T0); | |
842 | break; | |
843 | case 2: | |
844 | ret = lduw_user(T0 & ~1); | |
845 | break; | |
846 | case 4: | |
847 | ret = ldl_user(T0 & ~3); | |
848 | break; | |
849 | default: | |
850 | case 8: | |
851 | ret = ldq_user(T0 & ~7); | |
852 | break; | |
853 | } | |
854 | } | |
855 | break; | |
3475187d FB |
856 | case 0x14: // Bypass |
857 | case 0x15: // Bypass, non-cacheable | |
81ad8ba2 BS |
858 | case 0x1c: // Bypass LE |
859 | case 0x1d: // Bypass, non-cacheable LE | |
0f8a249a | 860 | { |
02aab46a FB |
861 | switch(size) { |
862 | case 1: | |
863 | ret = ldub_phys(T0); | |
864 | break; | |
865 | case 2: | |
866 | ret = lduw_phys(T0 & ~1); | |
867 | break; | |
868 | case 4: | |
869 | ret = ldl_phys(T0 & ~3); | |
870 | break; | |
871 | default: | |
872 | case 8: | |
873 | ret = ldq_phys(T0 & ~7); | |
874 | break; | |
875 | } | |
0f8a249a BS |
876 | break; |
877 | } | |
83469015 FB |
878 | case 0x04: // Nucleus |
879 | case 0x0c: // Nucleus Little Endian (LE) | |
83469015 | 880 | case 0x11: // As if user secondary |
83469015 | 881 | case 0x19: // As if user secondary LE |
83469015 FB |
882 | case 0x24: // Nucleus quad LDD 128 bit atomic |
883 | case 0x2c: // Nucleus quad LDD 128 bit atomic | |
884 | case 0x4a: // UPA config | |
81ad8ba2 | 885 | case 0x81: // Secondary |
83469015 | 886 | case 0x83: // Secondary no-fault |
83469015 | 887 | case 0x89: // Secondary LE |
83469015 | 888 | case 0x8b: // Secondary no-fault LE |
0f8a249a BS |
889 | // XXX |
890 | break; | |
3475187d | 891 | case 0x45: // LSU |
0f8a249a BS |
892 | ret = env->lsu; |
893 | break; | |
3475187d | 894 | case 0x50: // I-MMU regs |
0f8a249a BS |
895 | { |
896 | int reg = (T0 >> 3) & 0xf; | |
3475187d | 897 | |
0f8a249a BS |
898 | ret = env->immuregs[reg]; |
899 | break; | |
900 | } | |
3475187d FB |
901 | case 0x51: // I-MMU 8k TSB pointer |
902 | case 0x52: // I-MMU 64k TSB pointer | |
903 | case 0x55: // I-MMU data access | |
0f8a249a BS |
904 | // XXX |
905 | break; | |
83469015 | 906 | case 0x56: // I-MMU tag read |
0f8a249a BS |
907 | { |
908 | unsigned int i; | |
909 | ||
910 | for (i = 0; i < 64; i++) { | |
911 | // Valid, ctx match, vaddr match | |
912 | if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 && | |
913 | env->itlb_tag[i] == T0) { | |
914 | ret = env->itlb_tag[i]; | |
915 | break; | |
916 | } | |
917 | } | |
918 | break; | |
919 | } | |
3475187d | 920 | case 0x58: // D-MMU regs |
0f8a249a BS |
921 | { |
922 | int reg = (T0 >> 3) & 0xf; | |
3475187d | 923 | |
0f8a249a BS |
924 | ret = env->dmmuregs[reg]; |
925 | break; | |
926 | } | |
83469015 | 927 | case 0x5e: // D-MMU tag read |
0f8a249a BS |
928 | { |
929 | unsigned int i; | |
930 | ||
931 | for (i = 0; i < 64; i++) { | |
932 | // Valid, ctx match, vaddr match | |
933 | if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 && | |
934 | env->dtlb_tag[i] == T0) { | |
935 | ret = env->dtlb_tag[i]; | |
936 | break; | |
937 | } | |
938 | } | |
939 | break; | |
940 | } | |
3475187d FB |
941 | case 0x59: // D-MMU 8k TSB pointer |
942 | case 0x5a: // D-MMU 64k TSB pointer | |
943 | case 0x5b: // D-MMU data pointer | |
944 | case 0x5d: // D-MMU data access | |
83469015 FB |
945 | case 0x48: // Interrupt dispatch, RO |
946 | case 0x49: // Interrupt data receive | |
947 | case 0x7f: // Incoming interrupt vector, RO | |
0f8a249a BS |
948 | // XXX |
949 | break; | |
3475187d FB |
950 | case 0x54: // I-MMU data in, WO |
951 | case 0x57: // I-MMU demap, WO | |
952 | case 0x5c: // D-MMU data in, WO | |
953 | case 0x5f: // D-MMU demap, WO | |
83469015 | 954 | case 0x77: // Interrupt vector, WO |
3475187d | 955 | default: |
6c36d3fa | 956 | do_unassigned_access(T0, 0, 0, 1); |
0f8a249a BS |
957 | ret = 0; |
958 | break; | |
3475187d | 959 | } |
81ad8ba2 BS |
960 | |
961 | /* Convert from little endian */ | |
962 | switch (asi) { | |
963 | case 0x0c: // Nucleus Little Endian (LE) | |
964 | case 0x18: // As if user primary LE | |
965 | case 0x19: // As if user secondary LE | |
966 | case 0x1c: // Bypass LE | |
967 | case 0x1d: // Bypass, non-cacheable LE | |
968 | case 0x88: // Primary LE | |
969 | case 0x89: // Secondary LE | |
970 | case 0x8a: // Primary no-fault LE | |
971 | case 0x8b: // Secondary no-fault LE | |
972 | switch(size) { | |
973 | case 2: | |
974 | ret = bswap16(ret); | |
e32664fb | 975 | break; |
81ad8ba2 BS |
976 | case 4: |
977 | ret = bswap32(ret); | |
e32664fb | 978 | break; |
81ad8ba2 BS |
979 | case 8: |
980 | ret = bswap64(ret); | |
e32664fb | 981 | break; |
81ad8ba2 BS |
982 | default: |
983 | break; | |
984 | } | |
985 | default: | |
986 | break; | |
987 | } | |
988 | ||
989 | /* Convert to signed number */ | |
990 | if (sign) { | |
991 | switch(size) { | |
992 | case 1: | |
993 | ret = (int8_t) ret; | |
e32664fb | 994 | break; |
81ad8ba2 BS |
995 | case 2: |
996 | ret = (int16_t) ret; | |
e32664fb | 997 | break; |
81ad8ba2 BS |
998 | case 4: |
999 | ret = (int32_t) ret; | |
e32664fb | 1000 | break; |
81ad8ba2 BS |
1001 | default: |
1002 | break; | |
1003 | } | |
1004 | } | |
3475187d FB |
1005 | T1 = ret; |
1006 | } | |
1007 | ||
81ad8ba2 | 1008 | void helper_st_asi(int asi, int size) |
3475187d | 1009 | { |
6f27aba6 BS |
1010 | if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
1011 | || (asi >= 0x30 && asi < 0x80) && !(env->hpstate & HS_PRIV)) | |
0f8a249a | 1012 | raise_exception(TT_PRIV_ACT); |
3475187d | 1013 | |
81ad8ba2 BS |
1014 | /* Convert to little endian */ |
1015 | switch (asi) { | |
1016 | case 0x0c: // Nucleus Little Endian (LE) | |
1017 | case 0x18: // As if user primary LE | |
1018 | case 0x19: // As if user secondary LE | |
1019 | case 0x1c: // Bypass LE | |
1020 | case 0x1d: // Bypass, non-cacheable LE | |
81ad8ba2 BS |
1021 | case 0x88: // Primary LE |
1022 | case 0x89: // Secondary LE | |
1023 | switch(size) { | |
1024 | case 2: | |
1025 | T0 = bswap16(T0); | |
e32664fb | 1026 | break; |
81ad8ba2 BS |
1027 | case 4: |
1028 | T0 = bswap32(T0); | |
e32664fb | 1029 | break; |
81ad8ba2 BS |
1030 | case 8: |
1031 | T0 = bswap64(T0); | |
e32664fb | 1032 | break; |
81ad8ba2 BS |
1033 | default: |
1034 | break; | |
1035 | } | |
1036 | default: | |
1037 | break; | |
1038 | } | |
1039 | ||
3475187d | 1040 | switch(asi) { |
81ad8ba2 BS |
1041 | case 0x10: // As if user primary |
1042 | case 0x18: // As if user primary LE | |
1043 | case 0x80: // Primary | |
1044 | case 0x88: // Primary LE | |
1045 | if ((asi & 0x80) && (env->pstate & PS_PRIV)) { | |
6f27aba6 BS |
1046 | if (env->hpstate & HS_PRIV) { |
1047 | switch(size) { | |
1048 | case 1: | |
1049 | stb_hypv(T0, T1); | |
1050 | break; | |
1051 | case 2: | |
1052 | stw_hypv(T0 & ~1, T1); | |
1053 | break; | |
1054 | case 4: | |
1055 | stl_hypv(T0 & ~3, T1); | |
1056 | break; | |
1057 | case 8: | |
1058 | default: | |
1059 | stq_hypv(T0 & ~7, T1); | |
1060 | break; | |
1061 | } | |
1062 | } else { | |
1063 | switch(size) { | |
1064 | case 1: | |
1065 | stb_kernel(T0, T1); | |
1066 | break; | |
1067 | case 2: | |
1068 | stw_kernel(T0 & ~1, T1); | |
1069 | break; | |
1070 | case 4: | |
1071 | stl_kernel(T0 & ~3, T1); | |
1072 | break; | |
1073 | case 8: | |
1074 | default: | |
1075 | stq_kernel(T0 & ~7, T1); | |
1076 | break; | |
1077 | } | |
81ad8ba2 BS |
1078 | } |
1079 | } else { | |
1080 | switch(size) { | |
1081 | case 1: | |
1082 | stb_user(T0, T1); | |
1083 | break; | |
1084 | case 2: | |
1085 | stw_user(T0 & ~1, T1); | |
1086 | break; | |
1087 | case 4: | |
1088 | stl_user(T0 & ~3, T1); | |
1089 | break; | |
1090 | case 8: | |
1091 | default: | |
1092 | stq_user(T0 & ~7, T1); | |
1093 | break; | |
1094 | } | |
1095 | } | |
1096 | break; | |
3475187d FB |
1097 | case 0x14: // Bypass |
1098 | case 0x15: // Bypass, non-cacheable | |
81ad8ba2 BS |
1099 | case 0x1c: // Bypass LE |
1100 | case 0x1d: // Bypass, non-cacheable LE | |
0f8a249a | 1101 | { |
02aab46a FB |
1102 | switch(size) { |
1103 | case 1: | |
1104 | stb_phys(T0, T1); | |
1105 | break; | |
1106 | case 2: | |
1107 | stw_phys(T0 & ~1, T1); | |
1108 | break; | |
1109 | case 4: | |
1110 | stl_phys(T0 & ~3, T1); | |
1111 | break; | |
1112 | case 8: | |
1113 | default: | |
1114 | stq_phys(T0 & ~7, T1); | |
1115 | break; | |
1116 | } | |
0f8a249a BS |
1117 | } |
1118 | return; | |
83469015 FB |
1119 | case 0x04: // Nucleus |
1120 | case 0x0c: // Nucleus Little Endian (LE) | |
83469015 | 1121 | case 0x11: // As if user secondary |
83469015 | 1122 | case 0x19: // As if user secondary LE |
83469015 FB |
1123 | case 0x24: // Nucleus quad LDD 128 bit atomic |
1124 | case 0x2c: // Nucleus quad LDD 128 bit atomic | |
1125 | case 0x4a: // UPA config | |
51996525 | 1126 | case 0x81: // Secondary |
83469015 | 1127 | case 0x89: // Secondary LE |
0f8a249a BS |
1128 | // XXX |
1129 | return; | |
3475187d | 1130 | case 0x45: // LSU |
0f8a249a BS |
1131 | { |
1132 | uint64_t oldreg; | |
1133 | ||
1134 | oldreg = env->lsu; | |
1135 | env->lsu = T1 & (DMMU_E | IMMU_E); | |
1136 | // Mappings generated during D/I MMU disabled mode are | |
1137 | // invalid in normal mode | |
1138 | if (oldreg != env->lsu) { | |
952a328f | 1139 | DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu); |
83469015 | 1140 | #ifdef DEBUG_MMU |
0f8a249a | 1141 | dump_mmu(env); |
83469015 | 1142 | #endif |
0f8a249a BS |
1143 | tlb_flush(env, 1); |
1144 | } | |
1145 | return; | |
1146 | } | |
3475187d | 1147 | case 0x50: // I-MMU regs |
0f8a249a BS |
1148 | { |
1149 | int reg = (T0 >> 3) & 0xf; | |
1150 | uint64_t oldreg; | |
3b46e624 | 1151 | |
0f8a249a | 1152 | oldreg = env->immuregs[reg]; |
3475187d FB |
1153 | switch(reg) { |
1154 | case 0: // RO | |
1155 | case 4: | |
1156 | return; | |
1157 | case 1: // Not in I-MMU | |
1158 | case 2: | |
1159 | case 7: | |
1160 | case 8: | |
1161 | return; | |
1162 | case 3: // SFSR | |
0f8a249a BS |
1163 | if ((T1 & 1) == 0) |
1164 | T1 = 0; // Clear SFSR | |
3475187d FB |
1165 | break; |
1166 | case 5: // TSB access | |
1167 | case 6: // Tag access | |
1168 | default: | |
1169 | break; | |
1170 | } | |
0f8a249a | 1171 | env->immuregs[reg] = T1; |
3475187d | 1172 | if (oldreg != env->immuregs[reg]) { |
952a328f | 1173 | DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]); |
3475187d | 1174 | } |
952a328f | 1175 | #ifdef DEBUG_MMU |
0f8a249a | 1176 | dump_mmu(env); |
3475187d | 1177 | #endif |
0f8a249a BS |
1178 | return; |
1179 | } | |
3475187d | 1180 | case 0x54: // I-MMU data in |
0f8a249a BS |
1181 | { |
1182 | unsigned int i; | |
1183 | ||
1184 | // Try finding an invalid entry | |
1185 | for (i = 0; i < 64; i++) { | |
1186 | if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) { | |
1187 | env->itlb_tag[i] = env->immuregs[6]; | |
1188 | env->itlb_tte[i] = T1; | |
1189 | return; | |
1190 | } | |
1191 | } | |
1192 | // Try finding an unlocked entry | |
1193 | for (i = 0; i < 64; i++) { | |
1194 | if ((env->itlb_tte[i] & 0x40) == 0) { | |
1195 | env->itlb_tag[i] = env->immuregs[6]; | |
1196 | env->itlb_tte[i] = T1; | |
1197 | return; | |
1198 | } | |
1199 | } | |
1200 | // error state? | |
1201 | return; | |
1202 | } | |
3475187d | 1203 | case 0x55: // I-MMU data access |
0f8a249a BS |
1204 | { |
1205 | unsigned int i = (T0 >> 3) & 0x3f; | |
3475187d | 1206 | |
0f8a249a BS |
1207 | env->itlb_tag[i] = env->immuregs[6]; |
1208 | env->itlb_tte[i] = T1; | |
1209 | return; | |
1210 | } | |
3475187d | 1211 | case 0x57: // I-MMU demap |
0f8a249a BS |
1212 | // XXX |
1213 | return; | |
3475187d | 1214 | case 0x58: // D-MMU regs |
0f8a249a BS |
1215 | { |
1216 | int reg = (T0 >> 3) & 0xf; | |
1217 | uint64_t oldreg; | |
3b46e624 | 1218 | |
0f8a249a | 1219 | oldreg = env->dmmuregs[reg]; |
3475187d FB |
1220 | switch(reg) { |
1221 | case 0: // RO | |
1222 | case 4: | |
1223 | return; | |
1224 | case 3: // SFSR | |
0f8a249a BS |
1225 | if ((T1 & 1) == 0) { |
1226 | T1 = 0; // Clear SFSR, Fault address | |
1227 | env->dmmuregs[4] = 0; | |
1228 | } | |
1229 | env->dmmuregs[reg] = T1; | |
3475187d FB |
1230 | break; |
1231 | case 1: // Primary context | |
1232 | case 2: // Secondary context | |
1233 | case 5: // TSB access | |
1234 | case 6: // Tag access | |
1235 | case 7: // Virtual Watchpoint | |
1236 | case 8: // Physical Watchpoint | |
1237 | default: | |
1238 | break; | |
1239 | } | |
0f8a249a | 1240 | env->dmmuregs[reg] = T1; |
3475187d | 1241 | if (oldreg != env->dmmuregs[reg]) { |
952a328f | 1242 | DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); |
3475187d | 1243 | } |
952a328f | 1244 | #ifdef DEBUG_MMU |
0f8a249a | 1245 | dump_mmu(env); |
3475187d | 1246 | #endif |
0f8a249a BS |
1247 | return; |
1248 | } | |
3475187d | 1249 | case 0x5c: // D-MMU data in |
0f8a249a BS |
1250 | { |
1251 | unsigned int i; | |
1252 | ||
1253 | // Try finding an invalid entry | |
1254 | for (i = 0; i < 64; i++) { | |
1255 | if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) { | |
1256 | env->dtlb_tag[i] = env->dmmuregs[6]; | |
1257 | env->dtlb_tte[i] = T1; | |
1258 | return; | |
1259 | } | |
1260 | } | |
1261 | // Try finding an unlocked entry | |
1262 | for (i = 0; i < 64; i++) { | |
1263 | if ((env->dtlb_tte[i] & 0x40) == 0) { | |
1264 | env->dtlb_tag[i] = env->dmmuregs[6]; | |
1265 | env->dtlb_tte[i] = T1; | |
1266 | return; | |
1267 | } | |
1268 | } | |
1269 | // error state? | |
1270 | return; | |
1271 | } | |
3475187d | 1272 | case 0x5d: // D-MMU data access |
0f8a249a BS |
1273 | { |
1274 | unsigned int i = (T0 >> 3) & 0x3f; | |
3475187d | 1275 | |
0f8a249a BS |
1276 | env->dtlb_tag[i] = env->dmmuregs[6]; |
1277 | env->dtlb_tte[i] = T1; | |
1278 | return; | |
1279 | } | |
3475187d | 1280 | case 0x5f: // D-MMU demap |
83469015 | 1281 | case 0x49: // Interrupt data receive |
0f8a249a BS |
1282 | // XXX |
1283 | return; | |
3475187d FB |
1284 | case 0x51: // I-MMU 8k TSB pointer, RO |
1285 | case 0x52: // I-MMU 64k TSB pointer, RO | |
1286 | case 0x56: // I-MMU tag read, RO | |
1287 | case 0x59: // D-MMU 8k TSB pointer, RO | |
1288 | case 0x5a: // D-MMU 64k TSB pointer, RO | |
1289 | case 0x5b: // D-MMU data pointer, RO | |
1290 | case 0x5e: // D-MMU tag read, RO | |
83469015 FB |
1291 | case 0x48: // Interrupt dispatch, RO |
1292 | case 0x7f: // Incoming interrupt vector, RO | |
1293 | case 0x82: // Primary no-fault, RO | |
1294 | case 0x83: // Secondary no-fault, RO | |
1295 | case 0x8a: // Primary no-fault LE, RO | |
1296 | case 0x8b: // Secondary no-fault LE, RO | |
3475187d | 1297 | default: |
6c36d3fa | 1298 | do_unassigned_access(T0, 1, 0, 1); |
0f8a249a | 1299 | return; |
3475187d FB |
1300 | } |
1301 | } | |
81ad8ba2 | 1302 | #endif /* CONFIG_USER_ONLY */ |
3391c818 BS |
1303 | |
1304 | void helper_ldf_asi(int asi, int size, int rd) | |
1305 | { | |
1306 | target_ulong tmp_T0 = T0, tmp_T1 = T1; | |
1307 | unsigned int i; | |
1308 | ||
1309 | switch (asi) { | |
1310 | case 0xf0: // Block load primary | |
1311 | case 0xf1: // Block load secondary | |
1312 | case 0xf8: // Block load primary LE | |
1313 | case 0xf9: // Block load secondary LE | |
51996525 BS |
1314 | if (rd & 7) { |
1315 | raise_exception(TT_ILL_INSN); | |
1316 | return; | |
1317 | } | |
1318 | if (T0 & 0x3f) { | |
1319 | raise_exception(TT_UNALIGNED); | |
1320 | return; | |
1321 | } | |
1322 | for (i = 0; i < 16; i++) { | |
1323 | helper_ld_asi(asi & 0x8f, 4, 0); | |
1324 | *(uint32_t *)&env->fpr[rd++] = T1; | |
1325 | T0 += 4; | |
3391c818 BS |
1326 | } |
1327 | T0 = tmp_T0; | |
1328 | T1 = tmp_T1; | |
1329 | ||
1330 | return; | |
1331 | default: | |
1332 | break; | |
1333 | } | |
1334 | ||
1335 | helper_ld_asi(asi, size, 0); | |
1336 | switch(size) { | |
1337 | default: | |
1338 | case 4: | |
1339 | *((uint32_t *)&FT0) = T1; | |
1340 | break; | |
1341 | case 8: | |
1342 | *((int64_t *)&DT0) = T1; | |
1343 | break; | |
1344 | } | |
1345 | T1 = tmp_T1; | |
1346 | } | |
1347 | ||
1348 | void helper_stf_asi(int asi, int size, int rd) | |
1349 | { | |
1350 | target_ulong tmp_T0 = T0, tmp_T1 = T1; | |
1351 | unsigned int i; | |
1352 | ||
1353 | switch (asi) { | |
1354 | case 0xf0: // Block store primary | |
1355 | case 0xf1: // Block store secondary | |
1356 | case 0xf8: // Block store primary LE | |
1357 | case 0xf9: // Block store secondary LE | |
51996525 BS |
1358 | if (rd & 7) { |
1359 | raise_exception(TT_ILL_INSN); | |
1360 | return; | |
1361 | } | |
1362 | if (T0 & 0x3f) { | |
1363 | raise_exception(TT_UNALIGNED); | |
1364 | return; | |
1365 | } | |
1366 | for (i = 0; i < 16; i++) { | |
1367 | T1 = *(uint32_t *)&env->fpr[rd++]; | |
1368 | helper_st_asi(asi & 0x8f, 4); | |
1369 | T0 += 4; | |
3391c818 BS |
1370 | } |
1371 | T0 = tmp_T0; | |
1372 | T1 = tmp_T1; | |
1373 | ||
1374 | return; | |
1375 | default: | |
1376 | break; | |
1377 | } | |
1378 | ||
1379 | switch(size) { | |
1380 | default: | |
1381 | case 4: | |
1382 | T1 = *((uint32_t *)&FT0); | |
1383 | break; | |
1384 | case 8: | |
1385 | T1 = *((int64_t *)&DT0); | |
1386 | break; | |
1387 | } | |
1388 | helper_st_asi(asi, size); | |
1389 | T1 = tmp_T1; | |
1390 | } | |
1391 | ||
81ad8ba2 | 1392 | #endif /* TARGET_SPARC64 */ |
3475187d FB |
1393 | |
1394 | #ifndef TARGET_SPARC64 | |
a0c4cb4a | 1395 | void helper_rett() |
e8af50a3 | 1396 | { |
af7bf89b FB |
1397 | unsigned int cwp; |
1398 | ||
d4218d99 BS |
1399 | if (env->psret == 1) |
1400 | raise_exception(TT_ILL_INSN); | |
1401 | ||
e8af50a3 | 1402 | env->psret = 1; |
5fafdf24 | 1403 | cwp = (env->cwp + 1) & (NWINDOWS - 1); |
e8af50a3 FB |
1404 | if (env->wim & (1 << cwp)) { |
1405 | raise_exception(TT_WIN_UNF); | |
1406 | } | |
1407 | set_cwp(cwp); | |
1408 | env->psrs = env->psrps; | |
1409 | } | |
3475187d | 1410 | #endif |
e8af50a3 | 1411 | |
8d5f07fa | 1412 | void helper_ldfsr(void) |
e8af50a3 | 1413 | { |
7a0e1f41 | 1414 | int rnd_mode; |
e8af50a3 FB |
1415 | switch (env->fsr & FSR_RD_MASK) { |
1416 | case FSR_RD_NEAREST: | |
7a0e1f41 | 1417 | rnd_mode = float_round_nearest_even; |
0f8a249a | 1418 | break; |
ed910241 | 1419 | default: |
e8af50a3 | 1420 | case FSR_RD_ZERO: |
7a0e1f41 | 1421 | rnd_mode = float_round_to_zero; |
0f8a249a | 1422 | break; |
e8af50a3 | 1423 | case FSR_RD_POS: |
7a0e1f41 | 1424 | rnd_mode = float_round_up; |
0f8a249a | 1425 | break; |
e8af50a3 | 1426 | case FSR_RD_NEG: |
7a0e1f41 | 1427 | rnd_mode = float_round_down; |
0f8a249a | 1428 | break; |
e8af50a3 | 1429 | } |
7a0e1f41 | 1430 | set_float_rounding_mode(rnd_mode, &env->fp_status); |
e8af50a3 | 1431 | } |
e80cfcfc | 1432 | |
e80cfcfc FB |
1433 | void helper_debug() |
1434 | { | |
1435 | env->exception_index = EXCP_DEBUG; | |
1436 | cpu_loop_exit(); | |
1437 | } | |
af7bf89b | 1438 | |
3475187d | 1439 | #ifndef TARGET_SPARC64 |
af7bf89b FB |
1440 | void do_wrpsr() |
1441 | { | |
d4218d99 BS |
1442 | if ((T0 & PSR_CWP) >= NWINDOWS) |
1443 | raise_exception(TT_ILL_INSN); | |
1444 | else | |
1445 | PUT_PSR(env, T0); | |
af7bf89b FB |
1446 | } |
1447 | ||
1448 | void do_rdpsr() | |
1449 | { | |
1450 | T0 = GET_PSR(env); | |
1451 | } | |
3475187d FB |
1452 | |
1453 | #else | |
1454 | ||
1455 | void do_popc() | |
1456 | { | |
1457 | T0 = (T1 & 0x5555555555555555ULL) + ((T1 >> 1) & 0x5555555555555555ULL); | |
1458 | T0 = (T0 & 0x3333333333333333ULL) + ((T0 >> 2) & 0x3333333333333333ULL); | |
1459 | T0 = (T0 & 0x0f0f0f0f0f0f0f0fULL) + ((T0 >> 4) & 0x0f0f0f0f0f0f0f0fULL); | |
1460 | T0 = (T0 & 0x00ff00ff00ff00ffULL) + ((T0 >> 8) & 0x00ff00ff00ff00ffULL); | |
1461 | T0 = (T0 & 0x0000ffff0000ffffULL) + ((T0 >> 16) & 0x0000ffff0000ffffULL); | |
1462 | T0 = (T0 & 0x00000000ffffffffULL) + ((T0 >> 32) & 0x00000000ffffffffULL); | |
1463 | } | |
83469015 FB |
1464 | |
1465 | static inline uint64_t *get_gregset(uint64_t pstate) | |
1466 | { | |
1467 | switch (pstate) { | |
1468 | default: | |
1469 | case 0: | |
0f8a249a | 1470 | return env->bgregs; |
83469015 | 1471 | case PS_AG: |
0f8a249a | 1472 | return env->agregs; |
83469015 | 1473 | case PS_MG: |
0f8a249a | 1474 | return env->mgregs; |
83469015 | 1475 | case PS_IG: |
0f8a249a | 1476 | return env->igregs; |
83469015 FB |
1477 | } |
1478 | } | |
1479 | ||
8f1f22f6 | 1480 | static inline void change_pstate(uint64_t new_pstate) |
83469015 | 1481 | { |
8f1f22f6 | 1482 | uint64_t pstate_regs, new_pstate_regs; |
83469015 FB |
1483 | uint64_t *src, *dst; |
1484 | ||
83469015 FB |
1485 | pstate_regs = env->pstate & 0xc01; |
1486 | new_pstate_regs = new_pstate & 0xc01; | |
1487 | if (new_pstate_regs != pstate_regs) { | |
0f8a249a BS |
1488 | // Switch global register bank |
1489 | src = get_gregset(new_pstate_regs); | |
1490 | dst = get_gregset(pstate_regs); | |
1491 | memcpy32(dst, env->gregs); | |
1492 | memcpy32(env->gregs, src); | |
83469015 FB |
1493 | } |
1494 | env->pstate = new_pstate; | |
1495 | } | |
1496 | ||
8f1f22f6 BS |
1497 | void do_wrpstate(void) |
1498 | { | |
1499 | change_pstate(T0 & 0xf3f); | |
1500 | } | |
1501 | ||
83469015 FB |
1502 | void do_done(void) |
1503 | { | |
1504 | env->tl--; | |
1505 | env->pc = env->tnpc[env->tl]; | |
1506 | env->npc = env->tnpc[env->tl] + 4; | |
1507 | PUT_CCR(env, env->tstate[env->tl] >> 32); | |
1508 | env->asi = (env->tstate[env->tl] >> 24) & 0xff; | |
8f1f22f6 | 1509 | change_pstate((env->tstate[env->tl] >> 8) & 0xf3f); |
17d996e1 | 1510 | PUT_CWP64(env, env->tstate[env->tl] & 0xff); |
83469015 FB |
1511 | } |
1512 | ||
1513 | void do_retry(void) | |
1514 | { | |
1515 | env->tl--; | |
1516 | env->pc = env->tpc[env->tl]; | |
1517 | env->npc = env->tnpc[env->tl]; | |
1518 | PUT_CCR(env, env->tstate[env->tl] >> 32); | |
1519 | env->asi = (env->tstate[env->tl] >> 24) & 0xff; | |
8f1f22f6 | 1520 | change_pstate((env->tstate[env->tl] >> 8) & 0xf3f); |
17d996e1 | 1521 | PUT_CWP64(env, env->tstate[env->tl] & 0xff); |
83469015 | 1522 | } |
3475187d | 1523 | #endif |
ee5bbe38 FB |
1524 | |
1525 | void set_cwp(int new_cwp) | |
1526 | { | |
1527 | /* put the modified wrap registers at their proper location */ | |
1528 | if (env->cwp == (NWINDOWS - 1)) | |
1529 | memcpy32(env->regbase, env->regbase + NWINDOWS * 16); | |
1530 | env->cwp = new_cwp; | |
1531 | /* put the wrap registers at their temporary location */ | |
1532 | if (new_cwp == (NWINDOWS - 1)) | |
1533 | memcpy32(env->regbase + NWINDOWS * 16, env->regbase); | |
1534 | env->regwptr = env->regbase + (new_cwp * 16); | |
1535 | REGWPTR = env->regwptr; | |
1536 | } | |
1537 | ||
1538 | void cpu_set_cwp(CPUState *env1, int new_cwp) | |
1539 | { | |
1540 | CPUState *saved_env; | |
1541 | #ifdef reg_REGWPTR | |
1542 | target_ulong *saved_regwptr; | |
1543 | #endif | |
1544 | ||
1545 | saved_env = env; | |
1546 | #ifdef reg_REGWPTR | |
1547 | saved_regwptr = REGWPTR; | |
1548 | #endif | |
1549 | env = env1; | |
1550 | set_cwp(new_cwp); | |
1551 | env = saved_env; | |
1552 | #ifdef reg_REGWPTR | |
1553 | REGWPTR = saved_regwptr; | |
1554 | #endif | |
1555 | } | |
1556 | ||
1557 | #ifdef TARGET_SPARC64 | |
1558 | void do_interrupt(int intno) | |
1559 | { | |
1560 | #ifdef DEBUG_PCALL | |
1561 | if (loglevel & CPU_LOG_INT) { | |
0f8a249a BS |
1562 | static int count; |
1563 | fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n", | |
ee5bbe38 FB |
1564 | count, intno, |
1565 | env->pc, | |
1566 | env->npc, env->regwptr[6]); | |
0f8a249a | 1567 | cpu_dump_state(env, logfile, fprintf, 0); |
ee5bbe38 | 1568 | #if 0 |
0f8a249a BS |
1569 | { |
1570 | int i; | |
1571 | uint8_t *ptr; | |
1572 | ||
1573 | fprintf(logfile, " code="); | |
1574 | ptr = (uint8_t *)env->pc; | |
1575 | for(i = 0; i < 16; i++) { | |
1576 | fprintf(logfile, " %02x", ldub(ptr + i)); | |
1577 | } | |
1578 | fprintf(logfile, "\n"); | |
1579 | } | |
ee5bbe38 | 1580 | #endif |
0f8a249a | 1581 | count++; |
ee5bbe38 FB |
1582 | } |
1583 | #endif | |
5fafdf24 | 1584 | #if !defined(CONFIG_USER_ONLY) |
83469015 | 1585 | if (env->tl == MAXTL) { |
c68ea704 | 1586 | cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index); |
0f8a249a | 1587 | return; |
ee5bbe38 FB |
1588 | } |
1589 | #endif | |
1590 | env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) | | |
0f8a249a | 1591 | ((env->pstate & 0xf3f) << 8) | GET_CWP64(env); |
ee5bbe38 FB |
1592 | env->tpc[env->tl] = env->pc; |
1593 | env->tnpc[env->tl] = env->npc; | |
1594 | env->tt[env->tl] = intno; | |
8f1f22f6 BS |
1595 | change_pstate(PS_PEF | PS_PRIV | PS_AG); |
1596 | ||
1597 | if (intno == TT_CLRWIN) | |
1598 | set_cwp((env->cwp - 1) & (NWINDOWS - 1)); | |
1599 | else if ((intno & 0x1c0) == TT_SPILL) | |
1600 | set_cwp((env->cwp - env->cansave - 2) & (NWINDOWS - 1)); | |
1601 | else if ((intno & 0x1c0) == TT_FILL) | |
1602 | set_cwp((env->cwp + 1) & (NWINDOWS - 1)); | |
83469015 FB |
1603 | env->tbr &= ~0x7fffULL; |
1604 | env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); | |
1605 | if (env->tl < MAXTL - 1) { | |
0f8a249a | 1606 | env->tl++; |
83469015 | 1607 | } else { |
0f8a249a BS |
1608 | env->pstate |= PS_RED; |
1609 | if (env->tl != MAXTL) | |
1610 | env->tl++; | |
83469015 | 1611 | } |
ee5bbe38 FB |
1612 | env->pc = env->tbr; |
1613 | env->npc = env->pc + 4; | |
1614 | env->exception_index = 0; | |
1615 | } | |
1616 | #else | |
1617 | void do_interrupt(int intno) | |
1618 | { | |
1619 | int cwp; | |
1620 | ||
1621 | #ifdef DEBUG_PCALL | |
1622 | if (loglevel & CPU_LOG_INT) { | |
0f8a249a BS |
1623 | static int count; |
1624 | fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n", | |
ee5bbe38 FB |
1625 | count, intno, |
1626 | env->pc, | |
1627 | env->npc, env->regwptr[6]); | |
0f8a249a | 1628 | cpu_dump_state(env, logfile, fprintf, 0); |
ee5bbe38 | 1629 | #if 0 |
0f8a249a BS |
1630 | { |
1631 | int i; | |
1632 | uint8_t *ptr; | |
1633 | ||
1634 | fprintf(logfile, " code="); | |
1635 | ptr = (uint8_t *)env->pc; | |
1636 | for(i = 0; i < 16; i++) { | |
1637 | fprintf(logfile, " %02x", ldub(ptr + i)); | |
1638 | } | |
1639 | fprintf(logfile, "\n"); | |
1640 | } | |
ee5bbe38 | 1641 | #endif |
0f8a249a | 1642 | count++; |
ee5bbe38 FB |
1643 | } |
1644 | #endif | |
5fafdf24 | 1645 | #if !defined(CONFIG_USER_ONLY) |
ee5bbe38 | 1646 | if (env->psret == 0) { |
c68ea704 | 1647 | cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index); |
0f8a249a | 1648 | return; |
ee5bbe38 FB |
1649 | } |
1650 | #endif | |
1651 | env->psret = 0; | |
5fafdf24 | 1652 | cwp = (env->cwp - 1) & (NWINDOWS - 1); |
ee5bbe38 FB |
1653 | set_cwp(cwp); |
1654 | env->regwptr[9] = env->pc; | |
1655 | env->regwptr[10] = env->npc; | |
1656 | env->psrps = env->psrs; | |
1657 | env->psrs = 1; | |
1658 | env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4); | |
1659 | env->pc = env->tbr; | |
1660 | env->npc = env->pc + 4; | |
1661 | env->exception_index = 0; | |
1662 | } | |
1663 | #endif | |
1664 | ||
5fafdf24 | 1665 | #if !defined(CONFIG_USER_ONLY) |
ee5bbe38 | 1666 | |
d2889a3e BS |
1667 | static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
1668 | void *retaddr); | |
1669 | ||
ee5bbe38 | 1670 | #define MMUSUFFIX _mmu |
d2889a3e | 1671 | #define ALIGNED_ONLY |
ee5bbe38 FB |
1672 | #define GETPC() (__builtin_return_address(0)) |
1673 | ||
1674 | #define SHIFT 0 | |
1675 | #include "softmmu_template.h" | |
1676 | ||
1677 | #define SHIFT 1 | |
1678 | #include "softmmu_template.h" | |
1679 | ||
1680 | #define SHIFT 2 | |
1681 | #include "softmmu_template.h" | |
1682 | ||
1683 | #define SHIFT 3 | |
1684 | #include "softmmu_template.h" | |
1685 | ||
d2889a3e BS |
1686 | static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
1687 | void *retaddr) | |
1688 | { | |
94554550 BS |
1689 | #ifdef DEBUG_UNALIGNED |
1690 | printf("Unaligned access to 0x%x from 0x%x\n", addr, env->pc); | |
1691 | #endif | |
1692 | raise_exception(TT_UNALIGNED); | |
d2889a3e | 1693 | } |
ee5bbe38 FB |
1694 | |
1695 | /* try to fill the TLB and return an exception if error. If retaddr is | |
1696 | NULL, it means that the function was called in C code (i.e. not | |
1697 | from generated code or from helper.c) */ | |
1698 | /* XXX: fix it to restore all registers */ | |
6ebbf390 | 1699 | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
ee5bbe38 FB |
1700 | { |
1701 | TranslationBlock *tb; | |
1702 | int ret; | |
1703 | unsigned long pc; | |
1704 | CPUState *saved_env; | |
1705 | ||
1706 | /* XXX: hack to restore env in all cases, even if not called from | |
1707 | generated code */ | |
1708 | saved_env = env; | |
1709 | env = cpu_single_env; | |
1710 | ||
6ebbf390 | 1711 | ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1); |
ee5bbe38 FB |
1712 | if (ret) { |
1713 | if (retaddr) { | |
1714 | /* now we have a real cpu fault */ | |
1715 | pc = (unsigned long)retaddr; | |
1716 | tb = tb_find_pc(pc); | |
1717 | if (tb) { | |
1718 | /* the PC is inside the translated code. It means that we have | |
1719 | a virtual CPU fault */ | |
1720 | cpu_restore_state(tb, env, pc, (void *)T2); | |
1721 | } | |
1722 | } | |
1723 | cpu_loop_exit(); | |
1724 | } | |
1725 | env = saved_env; | |
1726 | } | |
1727 | ||
1728 | #endif | |
6c36d3fa BS |
1729 | |
1730 | #ifndef TARGET_SPARC64 | |
5dcb6b91 | 1731 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
6c36d3fa BS |
1732 | int is_asi) |
1733 | { | |
1734 | CPUState *saved_env; | |
1735 | ||
1736 | /* XXX: hack to restore env in all cases, even if not called from | |
1737 | generated code */ | |
1738 | saved_env = env; | |
1739 | env = cpu_single_env; | |
1740 | if (env->mmuregs[3]) /* Fault status register */ | |
0f8a249a | 1741 | env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
6c36d3fa BS |
1742 | if (is_asi) |
1743 | env->mmuregs[3] |= 1 << 16; | |
1744 | if (env->psrs) | |
1745 | env->mmuregs[3] |= 1 << 5; | |
1746 | if (is_exec) | |
1747 | env->mmuregs[3] |= 1 << 6; | |
1748 | if (is_write) | |
1749 | env->mmuregs[3] |= 1 << 7; | |
1750 | env->mmuregs[3] |= (5 << 2) | 2; | |
1751 | env->mmuregs[4] = addr; /* Fault address register */ | |
1752 | if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { | |
1753 | #ifdef DEBUG_UNASSIGNED | |
5dcb6b91 | 1754 | printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx |
6c36d3fa BS |
1755 | "\n", addr, env->pc); |
1756 | #endif | |
1b2e93c1 BS |
1757 | if (is_exec) |
1758 | raise_exception(TT_CODE_ACCESS); | |
1759 | else | |
1760 | raise_exception(TT_DATA_ACCESS); | |
6c36d3fa BS |
1761 | } |
1762 | env = saved_env; | |
1763 | } | |
1764 | #else | |
5dcb6b91 | 1765 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
6c36d3fa BS |
1766 | int is_asi) |
1767 | { | |
1768 | #ifdef DEBUG_UNASSIGNED | |
1769 | CPUState *saved_env; | |
1770 | ||
1771 | /* XXX: hack to restore env in all cases, even if not called from | |
1772 | generated code */ | |
1773 | saved_env = env; | |
1774 | env = cpu_single_env; | |
5dcb6b91 | 1775 | printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n", |
6c36d3fa BS |
1776 | addr, env->pc); |
1777 | env = saved_env; | |
1778 | #endif | |
1b2e93c1 BS |
1779 | if (is_exec) |
1780 | raise_exception(TT_CODE_ACCESS); | |
1781 | else | |
1782 | raise_exception(TT_DATA_ACCESS); | |
6c36d3fa BS |
1783 | } |
1784 | #endif | |
20c9f095 BS |
1785 | |
1786 | #ifdef TARGET_SPARC64 | |
1787 | void do_tick_set_count(void *opaque, uint64_t count) | |
1788 | { | |
d8bdf5fa | 1789 | #if !defined(CONFIG_USER_ONLY) |
20c9f095 | 1790 | ptimer_set_count(opaque, -count); |
d8bdf5fa | 1791 | #endif |
20c9f095 BS |
1792 | } |
1793 | ||
1794 | uint64_t do_tick_get_count(void *opaque) | |
1795 | { | |
d8bdf5fa | 1796 | #if !defined(CONFIG_USER_ONLY) |
20c9f095 | 1797 | return -ptimer_get_count(opaque); |
d8bdf5fa BS |
1798 | #else |
1799 | return 0; | |
1800 | #endif | |
20c9f095 BS |
1801 | } |
1802 | ||
1803 | void do_tick_set_limit(void *opaque, uint64_t limit) | |
1804 | { | |
d8bdf5fa | 1805 | #if !defined(CONFIG_USER_ONLY) |
20c9f095 | 1806 | ptimer_set_limit(opaque, -limit, 0); |
d8bdf5fa | 1807 | #endif |
20c9f095 BS |
1808 | } |
1809 | #endif |