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Commit | Line | Data |
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7a3f1944 FB |
1 | /* |
2 | SPARC translation | |
3 | ||
4 | Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at> | |
3475187d | 5 | Copyright (C) 2003-2005 Fabrice Bellard |
7a3f1944 FB |
6 | |
7 | This library is free software; you can redistribute it and/or | |
8 | modify it under the terms of the GNU Lesser General Public | |
9 | License as published by the Free Software Foundation; either | |
10 | version 2 of the License, or (at your option) any later version. | |
11 | ||
12 | This library is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | Lesser General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU Lesser General Public | |
18 | License along with this library; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | /* | |
7a3f1944 FB |
23 | TODO-list: |
24 | ||
3475187d | 25 | Rest of V9 instructions, VIS instructions |
bd497938 | 26 | NPC/PC static optimisations (use JUMP_TB when possible) |
7a3f1944 | 27 | Optimize synthetic instructions |
bd497938 | 28 | */ |
7a3f1944 FB |
29 | |
30 | #include <stdarg.h> | |
31 | #include <stdlib.h> | |
32 | #include <stdio.h> | |
33 | #include <string.h> | |
34 | #include <inttypes.h> | |
35 | ||
36 | #include "cpu.h" | |
37 | #include "exec-all.h" | |
38 | #include "disas.h" | |
1a2fb1c0 | 39 | #include "helper.h" |
57fec1fe | 40 | #include "tcg-op.h" |
7a3f1944 FB |
41 | |
42 | #define DEBUG_DISAS | |
43 | ||
72cbca10 FB |
44 | #define DYNAMIC_PC 1 /* dynamic pc value */ |
45 | #define JUMP_PC 2 /* dynamic pc value which takes only two values | |
46 | according to jump_pc[T2] */ | |
47 | ||
1a2fb1c0 BS |
48 | /* global register indexes */ |
49 | static TCGv cpu_env, cpu_T[3], cpu_regwptr; | |
50 | /* local register indexes (only used inside old micro ops) */ | |
51 | static TCGv cpu_tmp0; | |
52 | ||
7a3f1944 | 53 | typedef struct DisasContext { |
0f8a249a BS |
54 | target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */ |
55 | target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */ | |
72cbca10 | 56 | target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ |
cf495bcf | 57 | int is_br; |
e8af50a3 | 58 | int mem_idx; |
a80dde08 | 59 | int fpu_enabled; |
cf495bcf | 60 | struct TranslationBlock *tb; |
7a3f1944 FB |
61 | } DisasContext; |
62 | ||
aaed909a FB |
63 | typedef struct sparc_def_t sparc_def_t; |
64 | ||
62724a37 BS |
65 | struct sparc_def_t { |
66 | const unsigned char *name; | |
67 | target_ulong iu_version; | |
68 | uint32_t fpu_version; | |
69 | uint32_t mmu_version; | |
6d5f237a | 70 | uint32_t mmu_bm; |
3deaeab7 BS |
71 | uint32_t mmu_ctpr_mask; |
72 | uint32_t mmu_cxr_mask; | |
73 | uint32_t mmu_sfsr_mask; | |
74 | uint32_t mmu_trcr_mask; | |
62724a37 BS |
75 | }; |
76 | ||
aaed909a FB |
77 | static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name); |
78 | ||
7a3f1944 FB |
79 | extern FILE *logfile; |
80 | extern int loglevel; | |
81 | ||
3475187d | 82 | // This function uses non-native bit order |
7a3f1944 FB |
83 | #define GET_FIELD(X, FROM, TO) \ |
84 | ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) | |
85 | ||
3475187d FB |
86 | // This function uses the order in the manuals, i.e. bit 0 is 2^0 |
87 | #define GET_FIELD_SP(X, FROM, TO) \ | |
88 | GET_FIELD(X, 31 - (TO), 31 - (FROM)) | |
89 | ||
90 | #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) | |
46d38ba8 | 91 | #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1)) |
3475187d FB |
92 | |
93 | #ifdef TARGET_SPARC64 | |
19f329ad | 94 | #define FFPREG(r) (r) |
0387d928 | 95 | #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e)) |
1f587329 | 96 | #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c)) |
3475187d | 97 | #else |
19f329ad | 98 | #define FFPREG(r) (r) |
c185970a | 99 | #define DFPREG(r) (r & 0x1e) |
1f587329 | 100 | #define QFPREG(r) (r & 0x1c) |
3475187d FB |
101 | #endif |
102 | ||
103 | static int sign_extend(int x, int len) | |
104 | { | |
105 | len = 32 - len; | |
106 | return (x << len) >> len; | |
107 | } | |
108 | ||
7a3f1944 FB |
109 | #define IS_IMM (insn & (1<<13)) |
110 | ||
cf495bcf | 111 | static void disas_sparc_insn(DisasContext * dc); |
7a3f1944 | 112 | |
3475187d FB |
113 | #ifdef TARGET_SPARC64 |
114 | #define GEN32(func, NAME) \ | |
a68156d0 | 115 | static GenOpFunc * const NAME ## _table [64] = { \ |
3475187d FB |
116 | NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
117 | NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ | |
118 | NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ | |
119 | NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ | |
120 | NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \ | |
121 | NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ | |
122 | NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ | |
123 | NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ | |
124 | NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \ | |
125 | NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \ | |
126 | NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \ | |
127 | NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \ | |
128 | }; \ | |
129 | static inline void func(int n) \ | |
130 | { \ | |
131 | NAME ## _table[n](); \ | |
132 | } | |
133 | #else | |
e8af50a3 | 134 | #define GEN32(func, NAME) \ |
a68156d0 | 135 | static GenOpFunc *const NAME ## _table [32] = { \ |
e8af50a3 FB |
136 | NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
137 | NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ | |
138 | NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ | |
139 | NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ | |
140 | NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \ | |
141 | NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ | |
142 | NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ | |
143 | NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ | |
144 | }; \ | |
145 | static inline void func(int n) \ | |
146 | { \ | |
147 | NAME ## _table[n](); \ | |
148 | } | |
3475187d | 149 | #endif |
e8af50a3 FB |
150 | |
151 | /* floating point registers moves */ | |
152 | GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf); | |
153 | GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf); | |
e8af50a3 FB |
154 | GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf); |
155 | GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf); | |
e8af50a3 FB |
156 | |
157 | GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf); | |
158 | GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf); | |
e8af50a3 FB |
159 | GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf); |
160 | GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf); | |
e8af50a3 | 161 | |
1f587329 BS |
162 | #if defined(CONFIG_USER_ONLY) |
163 | GEN32(gen_op_load_fpr_QT0, gen_op_load_fpr_QT0_fprf); | |
164 | GEN32(gen_op_load_fpr_QT1, gen_op_load_fpr_QT1_fprf); | |
165 | GEN32(gen_op_store_QT0_fpr, gen_op_store_QT0_fpr_fprf); | |
166 | GEN32(gen_op_store_QT1_fpr, gen_op_store_QT1_fpr_fprf); | |
167 | #endif | |
168 | ||
81ad8ba2 BS |
169 | /* moves */ |
170 | #ifdef CONFIG_USER_ONLY | |
3475187d | 171 | #define supervisor(dc) 0 |
81ad8ba2 | 172 | #ifdef TARGET_SPARC64 |
e9ebed4d | 173 | #define hypervisor(dc) 0 |
81ad8ba2 | 174 | #endif |
3475187d | 175 | #define gen_op_ldst(name) gen_op_##name##_raw() |
3475187d | 176 | #else |
6f27aba6 | 177 | #define supervisor(dc) (dc->mem_idx >= 1) |
81ad8ba2 BS |
178 | #ifdef TARGET_SPARC64 |
179 | #define hypervisor(dc) (dc->mem_idx == 2) | |
6f27aba6 BS |
180 | #define OP_LD_TABLE(width) \ |
181 | static GenOpFunc * const gen_op_##width[] = { \ | |
182 | &gen_op_##width##_user, \ | |
183 | &gen_op_##width##_kernel, \ | |
184 | &gen_op_##width##_hypv, \ | |
185 | }; | |
186 | #else | |
0f8a249a | 187 | #define OP_LD_TABLE(width) \ |
a68156d0 | 188 | static GenOpFunc * const gen_op_##width[] = { \ |
0f8a249a BS |
189 | &gen_op_##width##_user, \ |
190 | &gen_op_##width##_kernel, \ | |
81ad8ba2 | 191 | }; |
3475187d | 192 | #endif |
6f27aba6 BS |
193 | #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])() |
194 | #endif | |
e8af50a3 | 195 | |
81ad8ba2 | 196 | #ifndef CONFIG_USER_ONLY |
b25deda7 BS |
197 | #ifdef __i386__ |
198 | OP_LD_TABLE(std); | |
199 | #endif /* __i386__ */ | |
e8af50a3 FB |
200 | OP_LD_TABLE(stf); |
201 | OP_LD_TABLE(stdf); | |
202 | OP_LD_TABLE(ldf); | |
203 | OP_LD_TABLE(lddf); | |
81ad8ba2 BS |
204 | #endif |
205 | ||
1a2fb1c0 BS |
206 | #ifdef TARGET_ABI32 |
207 | #define ABI32_MASK(addr) tcg_gen_andi_i64(addr, addr, 0xffffffffULL); | |
208 | #else | |
209 | #define ABI32_MASK(addr) | |
210 | #endif | |
3391c818 | 211 | |
1a2fb1c0 | 212 | static inline void gen_movl_simm_T1(int32_t val) |
81ad8ba2 | 213 | { |
1a2fb1c0 | 214 | tcg_gen_movi_tl(cpu_T[1], val); |
81ad8ba2 BS |
215 | } |
216 | ||
1a2fb1c0 | 217 | static inline void gen_movl_reg_TN(int reg, TCGv tn) |
81ad8ba2 | 218 | { |
1a2fb1c0 BS |
219 | if (reg == 0) |
220 | tcg_gen_movi_tl(tn, 0); | |
221 | else if (reg < 8) | |
222 | tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUState, gregs[reg])); | |
223 | else { | |
1a2fb1c0 | 224 | tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
81ad8ba2 BS |
225 | } |
226 | } | |
227 | ||
1a2fb1c0 | 228 | static inline void gen_movl_reg_T0(int reg) |
81ad8ba2 | 229 | { |
1a2fb1c0 | 230 | gen_movl_reg_TN(reg, cpu_T[0]); |
81ad8ba2 BS |
231 | } |
232 | ||
1a2fb1c0 | 233 | static inline void gen_movl_reg_T1(int reg) |
81ad8ba2 | 234 | { |
1a2fb1c0 | 235 | gen_movl_reg_TN(reg, cpu_T[1]); |
81ad8ba2 BS |
236 | } |
237 | ||
b25deda7 BS |
238 | #ifdef __i386__ |
239 | static inline void gen_movl_reg_T2(int reg) | |
240 | { | |
241 | gen_movl_reg_TN(reg, cpu_T[2]); | |
242 | } | |
243 | ||
244 | #endif /* __i386__ */ | |
1a2fb1c0 | 245 | static inline void gen_movl_TN_reg(int reg, TCGv tn) |
81ad8ba2 | 246 | { |
1a2fb1c0 BS |
247 | if (reg == 0) |
248 | return; | |
249 | else if (reg < 8) | |
250 | tcg_gen_st_tl(tn, cpu_env, offsetof(CPUState, gregs[reg])); | |
251 | else { | |
1a2fb1c0 | 252 | tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
81ad8ba2 BS |
253 | } |
254 | } | |
255 | ||
1a2fb1c0 | 256 | static inline void gen_movl_T0_reg(int reg) |
3475187d | 257 | { |
1a2fb1c0 | 258 | gen_movl_TN_reg(reg, cpu_T[0]); |
3475187d FB |
259 | } |
260 | ||
1a2fb1c0 | 261 | static inline void gen_movl_T1_reg(int reg) |
3475187d | 262 | { |
1a2fb1c0 | 263 | gen_movl_TN_reg(reg, cpu_T[1]); |
3475187d FB |
264 | } |
265 | ||
1a2fb1c0 | 266 | static inline void gen_op_movl_T0_env(size_t offset) |
7a3f1944 | 267 | { |
1a2fb1c0 | 268 | tcg_gen_ld_i32(cpu_T[0], cpu_env, offset); |
7a3f1944 FB |
269 | } |
270 | ||
1a2fb1c0 | 271 | static inline void gen_op_movl_env_T0(size_t offset) |
7a3f1944 | 272 | { |
1a2fb1c0 | 273 | tcg_gen_st_i32(cpu_T[0], cpu_env, offset); |
7a3f1944 FB |
274 | } |
275 | ||
1a2fb1c0 | 276 | static inline void gen_op_movtl_T0_env(size_t offset) |
7a3f1944 | 277 | { |
1a2fb1c0 | 278 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offset); |
7a3f1944 FB |
279 | } |
280 | ||
1a2fb1c0 | 281 | static inline void gen_op_movtl_env_T0(size_t offset) |
7a3f1944 | 282 | { |
1a2fb1c0 | 283 | tcg_gen_st_tl(cpu_T[0], cpu_env, offset); |
7a3f1944 FB |
284 | } |
285 | ||
1a2fb1c0 | 286 | static inline void gen_op_add_T1_T0(void) |
7a3f1944 | 287 | { |
1a2fb1c0 | 288 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
7a3f1944 FB |
289 | } |
290 | ||
1a2fb1c0 | 291 | static inline void gen_op_or_T1_T0(void) |
7a3f1944 | 292 | { |
1a2fb1c0 | 293 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
7a3f1944 FB |
294 | } |
295 | ||
1a2fb1c0 | 296 | static inline void gen_op_xor_T1_T0(void) |
7a3f1944 | 297 | { |
1a2fb1c0 | 298 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
7a3f1944 FB |
299 | } |
300 | ||
3475187d FB |
301 | static inline void gen_jmp_im(target_ulong pc) |
302 | { | |
1a2fb1c0 BS |
303 | tcg_gen_movi_tl(cpu_tmp0, pc); |
304 | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, pc)); | |
3475187d FB |
305 | } |
306 | ||
307 | static inline void gen_movl_npc_im(target_ulong npc) | |
308 | { | |
1a2fb1c0 BS |
309 | tcg_gen_movi_tl(cpu_tmp0, npc); |
310 | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, npc)); | |
3475187d FB |
311 | } |
312 | ||
5fafdf24 | 313 | static inline void gen_goto_tb(DisasContext *s, int tb_num, |
6e256c93 FB |
314 | target_ulong pc, target_ulong npc) |
315 | { | |
316 | TranslationBlock *tb; | |
317 | ||
318 | tb = s->tb; | |
319 | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) && | |
320 | (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) { | |
321 | /* jump to same page: we can use a direct jump */ | |
57fec1fe | 322 | tcg_gen_goto_tb(tb_num); |
6e256c93 FB |
323 | gen_jmp_im(pc); |
324 | gen_movl_npc_im(npc); | |
57fec1fe | 325 | tcg_gen_exit_tb((long)tb + tb_num); |
6e256c93 FB |
326 | } else { |
327 | /* jump to another page: currently not optimized */ | |
328 | gen_jmp_im(pc); | |
329 | gen_movl_npc_im(npc); | |
57fec1fe | 330 | tcg_gen_exit_tb(0); |
6e256c93 FB |
331 | } |
332 | } | |
333 | ||
19f329ad BS |
334 | // XXX suboptimal |
335 | static inline void gen_mov_reg_N(TCGv reg, TCGv src) | |
336 | { | |
337 | tcg_gen_shri_i32(reg, src, 23); | |
338 | tcg_gen_andi_tl(reg, reg, 0x1); | |
339 | } | |
340 | ||
341 | static inline void gen_mov_reg_Z(TCGv reg, TCGv src) | |
342 | { | |
343 | tcg_gen_shri_i32(reg, src, 22); | |
344 | tcg_gen_andi_tl(reg, reg, 0x1); | |
345 | } | |
346 | ||
347 | static inline void gen_mov_reg_V(TCGv reg, TCGv src) | |
348 | { | |
349 | tcg_gen_shri_i32(reg, src, 21); | |
350 | tcg_gen_andi_tl(reg, reg, 0x1); | |
351 | } | |
352 | ||
353 | static inline void gen_mov_reg_C(TCGv reg, TCGv src) | |
354 | { | |
355 | tcg_gen_shri_i32(reg, src, 20); | |
356 | tcg_gen_andi_tl(reg, reg, 0x1); | |
357 | } | |
358 | ||
359 | // 1 | |
360 | static inline void gen_op_eval_ba(TCGv dst) | |
361 | { | |
362 | tcg_gen_movi_tl(dst, 1); | |
363 | } | |
364 | ||
365 | // Z | |
366 | static inline void gen_op_eval_be(TCGv dst, TCGv src) | |
367 | { | |
368 | gen_mov_reg_Z(dst, src); | |
369 | } | |
370 | ||
371 | // Z | (N ^ V) | |
372 | static inline void gen_op_eval_ble(TCGv dst, TCGv src) | |
373 | { | |
374 | TCGv r_flag; | |
375 | ||
376 | r_flag = tcg_temp_new(TCG_TYPE_TL); | |
377 | gen_mov_reg_N(r_flag, src); | |
378 | gen_mov_reg_V(dst, src); | |
379 | tcg_gen_xor_tl(dst, dst, r_flag); | |
380 | gen_mov_reg_Z(r_flag, src); | |
381 | tcg_gen_or_tl(dst, dst, r_flag); | |
382 | } | |
383 | ||
384 | // N ^ V | |
385 | static inline void gen_op_eval_bl(TCGv dst, TCGv src) | |
386 | { | |
387 | TCGv r_V; | |
388 | ||
389 | r_V = tcg_temp_new(TCG_TYPE_TL); | |
390 | gen_mov_reg_V(r_V, src); | |
391 | gen_mov_reg_N(dst, src); | |
392 | tcg_gen_xor_tl(dst, dst, r_V); | |
393 | } | |
394 | ||
395 | // C | Z | |
396 | static inline void gen_op_eval_bleu(TCGv dst, TCGv src) | |
397 | { | |
398 | TCGv r_Z; | |
399 | ||
400 | r_Z = tcg_temp_new(TCG_TYPE_TL); | |
401 | gen_mov_reg_Z(r_Z, src); | |
402 | gen_mov_reg_C(dst, src); | |
403 | tcg_gen_or_tl(dst, dst, r_Z); | |
404 | } | |
405 | ||
406 | // C | |
407 | static inline void gen_op_eval_bcs(TCGv dst, TCGv src) | |
408 | { | |
409 | gen_mov_reg_C(dst, src); | |
410 | } | |
411 | ||
412 | // V | |
413 | static inline void gen_op_eval_bvs(TCGv dst, TCGv src) | |
414 | { | |
415 | gen_mov_reg_V(dst, src); | |
416 | } | |
417 | ||
418 | // 0 | |
419 | static inline void gen_op_eval_bn(TCGv dst) | |
420 | { | |
421 | tcg_gen_movi_tl(dst, 0); | |
422 | } | |
423 | ||
424 | // N | |
425 | static inline void gen_op_eval_bneg(TCGv dst, TCGv src) | |
426 | { | |
427 | gen_mov_reg_N(dst, src); | |
428 | } | |
429 | ||
430 | // !Z | |
431 | static inline void gen_op_eval_bne(TCGv dst, TCGv src) | |
432 | { | |
433 | gen_mov_reg_Z(dst, src); | |
434 | tcg_gen_xori_tl(dst, dst, 0x1); | |
435 | } | |
436 | ||
437 | // !(Z | (N ^ V)) | |
438 | static inline void gen_op_eval_bg(TCGv dst, TCGv src) | |
439 | { | |
440 | TCGv r_flag; | |
441 | ||
442 | r_flag = tcg_temp_new(TCG_TYPE_TL); | |
443 | gen_mov_reg_N(r_flag, src); | |
444 | gen_mov_reg_V(dst, src); | |
445 | tcg_gen_xor_tl(dst, dst, r_flag); | |
446 | gen_mov_reg_Z(r_flag, src); | |
447 | tcg_gen_or_tl(dst, dst, r_flag); | |
448 | tcg_gen_xori_tl(dst, dst, 0x1); | |
449 | } | |
450 | ||
451 | // !(N ^ V) | |
452 | static inline void gen_op_eval_bge(TCGv dst, TCGv src) | |
453 | { | |
454 | TCGv r_V; | |
455 | ||
456 | r_V = tcg_temp_new(TCG_TYPE_TL); | |
457 | gen_mov_reg_V(r_V, src); | |
458 | gen_mov_reg_N(dst, src); | |
459 | tcg_gen_xor_tl(dst, dst, r_V); | |
460 | tcg_gen_xori_tl(dst, dst, 0x1); | |
461 | } | |
462 | ||
463 | // !(C | Z) | |
464 | static inline void gen_op_eval_bgu(TCGv dst, TCGv src) | |
465 | { | |
466 | TCGv r_Z; | |
467 | ||
468 | r_Z = tcg_temp_new(TCG_TYPE_TL); | |
469 | gen_mov_reg_Z(r_Z, src); | |
470 | gen_mov_reg_C(dst, src); | |
471 | tcg_gen_or_tl(dst, dst, r_Z); | |
472 | tcg_gen_xori_tl(dst, dst, 0x1); | |
473 | } | |
474 | ||
475 | // !C | |
476 | static inline void gen_op_eval_bcc(TCGv dst, TCGv src) | |
477 | { | |
478 | gen_mov_reg_C(dst, src); | |
479 | tcg_gen_xori_tl(dst, dst, 0x1); | |
480 | } | |
481 | ||
482 | // !N | |
483 | static inline void gen_op_eval_bpos(TCGv dst, TCGv src) | |
484 | { | |
485 | gen_mov_reg_N(dst, src); | |
486 | tcg_gen_xori_tl(dst, dst, 0x1); | |
487 | } | |
488 | ||
489 | // !V | |
490 | static inline void gen_op_eval_bvc(TCGv dst, TCGv src) | |
491 | { | |
492 | gen_mov_reg_V(dst, src); | |
493 | tcg_gen_xori_tl(dst, dst, 0x1); | |
494 | } | |
495 | ||
496 | /* | |
497 | FPSR bit field FCC1 | FCC0: | |
498 | 0 = | |
499 | 1 < | |
500 | 2 > | |
501 | 3 unordered | |
502 | */ | |
503 | static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, | |
504 | unsigned int fcc_offset) | |
505 | { | |
506 | tcg_gen_shri_i32(reg, src, 10 + fcc_offset); | |
507 | tcg_gen_andi_tl(reg, reg, 0x1); | |
508 | } | |
509 | ||
510 | static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, | |
511 | unsigned int fcc_offset) | |
512 | { | |
513 | tcg_gen_shri_i32(reg, src, 11 + fcc_offset); | |
514 | tcg_gen_andi_tl(reg, reg, 0x1); | |
515 | } | |
516 | ||
517 | // !0: FCC0 | FCC1 | |
518 | static inline void gen_op_eval_fbne(TCGv dst, TCGv src, | |
519 | unsigned int fcc_offset) | |
520 | { | |
521 | TCGv r_fcc1; | |
522 | ||
523 | r_fcc1 = tcg_temp_new(TCG_TYPE_TL); | |
524 | gen_mov_reg_FCC0(dst, src, fcc_offset); | |
525 | gen_mov_reg_FCC1(r_fcc1, src, fcc_offset); | |
526 | tcg_gen_or_tl(dst, dst, r_fcc1); | |
527 | } | |
528 | ||
529 | // 1 or 2: FCC0 ^ FCC1 | |
530 | static inline void gen_op_eval_fblg(TCGv dst, TCGv src, | |
531 | unsigned int fcc_offset) | |
532 | { | |
533 | TCGv r_fcc1; | |
534 | ||
535 | r_fcc1 = tcg_temp_new(TCG_TYPE_TL); | |
536 | gen_mov_reg_FCC0(dst, src, fcc_offset); | |
537 | gen_mov_reg_FCC1(r_fcc1, src, fcc_offset); | |
538 | tcg_gen_xor_tl(dst, dst, r_fcc1); | |
539 | } | |
540 | ||
541 | // 1 or 3: FCC0 | |
542 | static inline void gen_op_eval_fbul(TCGv dst, TCGv src, | |
543 | unsigned int fcc_offset) | |
544 | { | |
545 | gen_mov_reg_FCC0(dst, src, fcc_offset); | |
546 | } | |
547 | ||
548 | // 1: FCC0 & !FCC1 | |
549 | static inline void gen_op_eval_fbl(TCGv dst, TCGv src, | |
550 | unsigned int fcc_offset) | |
551 | { | |
552 | TCGv r_fcc1; | |
553 | ||
554 | r_fcc1 = tcg_temp_new(TCG_TYPE_TL); | |
555 | gen_mov_reg_FCC0(dst, src, fcc_offset); | |
556 | gen_mov_reg_FCC1(r_fcc1, src, fcc_offset); | |
557 | tcg_gen_xori_tl(r_fcc1, r_fcc1, 0x1); | |
558 | tcg_gen_and_tl(dst, dst, r_fcc1); | |
559 | } | |
560 | ||
561 | // 2 or 3: FCC1 | |
562 | static inline void gen_op_eval_fbug(TCGv dst, TCGv src, | |
563 | unsigned int fcc_offset) | |
564 | { | |
565 | gen_mov_reg_FCC1(dst, src, fcc_offset); | |
566 | } | |
567 | ||
568 | // 2: !FCC0 & FCC1 | |
569 | static inline void gen_op_eval_fbg(TCGv dst, TCGv src, | |
570 | unsigned int fcc_offset) | |
571 | { | |
572 | TCGv r_fcc1; | |
573 | ||
574 | r_fcc1 = tcg_temp_new(TCG_TYPE_TL); | |
575 | gen_mov_reg_FCC0(dst, src, fcc_offset); | |
576 | tcg_gen_xori_tl(dst, dst, 0x1); | |
577 | gen_mov_reg_FCC1(r_fcc1, src, fcc_offset); | |
578 | tcg_gen_and_tl(dst, dst, r_fcc1); | |
579 | } | |
580 | ||
581 | // 3: FCC0 & FCC1 | |
582 | static inline void gen_op_eval_fbu(TCGv dst, TCGv src, | |
583 | unsigned int fcc_offset) | |
584 | { | |
585 | TCGv r_fcc1; | |
586 | ||
587 | r_fcc1 = tcg_temp_new(TCG_TYPE_TL); | |
588 | gen_mov_reg_FCC0(dst, src, fcc_offset); | |
589 | gen_mov_reg_FCC1(r_fcc1, src, fcc_offset); | |
590 | tcg_gen_and_tl(dst, dst, r_fcc1); | |
591 | } | |
592 | ||
593 | // 0: !(FCC0 | FCC1) | |
594 | static inline void gen_op_eval_fbe(TCGv dst, TCGv src, | |
595 | unsigned int fcc_offset) | |
596 | { | |
597 | TCGv r_fcc1; | |
598 | ||
599 | r_fcc1 = tcg_temp_new(TCG_TYPE_TL); | |
600 | gen_mov_reg_FCC0(dst, src, fcc_offset); | |
601 | gen_mov_reg_FCC1(r_fcc1, src, fcc_offset); | |
602 | tcg_gen_or_tl(dst, dst, r_fcc1); | |
603 | tcg_gen_xori_tl(dst, dst, 0x1); | |
604 | } | |
605 | ||
606 | // 0 or 3: !(FCC0 ^ FCC1) | |
607 | static inline void gen_op_eval_fbue(TCGv dst, TCGv src, | |
608 | unsigned int fcc_offset) | |
609 | { | |
610 | TCGv r_fcc1; | |
611 | ||
612 | r_fcc1 = tcg_temp_new(TCG_TYPE_TL); | |
613 | gen_mov_reg_FCC0(dst, src, fcc_offset); | |
614 | gen_mov_reg_FCC1(r_fcc1, src, fcc_offset); | |
615 | tcg_gen_xor_tl(dst, dst, r_fcc1); | |
616 | tcg_gen_xori_tl(dst, dst, 0x1); | |
617 | } | |
618 | ||
619 | // 0 or 2: !FCC0 | |
620 | static inline void gen_op_eval_fbge(TCGv dst, TCGv src, | |
621 | unsigned int fcc_offset) | |
622 | { | |
623 | gen_mov_reg_FCC0(dst, src, fcc_offset); | |
624 | tcg_gen_xori_tl(dst, dst, 0x1); | |
625 | } | |
626 | ||
627 | // !1: !(FCC0 & !FCC1) | |
628 | static inline void gen_op_eval_fbuge(TCGv dst, TCGv src, | |
629 | unsigned int fcc_offset) | |
630 | { | |
631 | TCGv r_fcc1; | |
632 | ||
633 | r_fcc1 = tcg_temp_new(TCG_TYPE_TL); | |
634 | gen_mov_reg_FCC0(dst, src, fcc_offset); | |
635 | gen_mov_reg_FCC1(r_fcc1, src, fcc_offset); | |
636 | tcg_gen_xori_tl(r_fcc1, r_fcc1, 0x1); | |
637 | tcg_gen_and_tl(dst, dst, r_fcc1); | |
638 | tcg_gen_xori_tl(dst, dst, 0x1); | |
639 | } | |
640 | ||
641 | // 0 or 1: !FCC1 | |
642 | static inline void gen_op_eval_fble(TCGv dst, TCGv src, | |
643 | unsigned int fcc_offset) | |
644 | { | |
645 | gen_mov_reg_FCC1(dst, src, fcc_offset); | |
646 | tcg_gen_xori_tl(dst, dst, 0x1); | |
647 | } | |
648 | ||
649 | // !2: !(!FCC0 & FCC1) | |
650 | static inline void gen_op_eval_fbule(TCGv dst, TCGv src, | |
651 | unsigned int fcc_offset) | |
652 | { | |
653 | TCGv r_fcc1; | |
654 | ||
655 | r_fcc1 = tcg_temp_new(TCG_TYPE_TL); | |
656 | gen_mov_reg_FCC0(dst, src, fcc_offset); | |
657 | tcg_gen_xori_tl(dst, dst, 0x1); | |
658 | gen_mov_reg_FCC1(r_fcc1, src, fcc_offset); | |
659 | tcg_gen_and_tl(dst, dst, r_fcc1); | |
660 | tcg_gen_xori_tl(dst, dst, 0x1); | |
661 | } | |
662 | ||
663 | // !3: !(FCC0 & FCC1) | |
664 | static inline void gen_op_eval_fbo(TCGv dst, TCGv src, | |
665 | unsigned int fcc_offset) | |
666 | { | |
667 | TCGv r_fcc1; | |
668 | ||
669 | r_fcc1 = tcg_temp_new(TCG_TYPE_TL); | |
670 | gen_mov_reg_FCC0(dst, src, fcc_offset); | |
671 | gen_mov_reg_FCC1(r_fcc1, src, fcc_offset); | |
672 | tcg_gen_and_tl(dst, dst, r_fcc1); | |
673 | tcg_gen_xori_tl(dst, dst, 0x1); | |
674 | } | |
675 | ||
46525e1f | 676 | static inline void gen_branch2(DisasContext *dc, target_ulong pc1, |
19f329ad | 677 | target_ulong pc2, TCGv r_cond) |
83469015 | 678 | { |
19f329ad | 679 | TCGv r_zero; |
83469015 FB |
680 | int l1; |
681 | ||
682 | l1 = gen_new_label(); | |
19f329ad BS |
683 | r_zero = tcg_temp_new(TCG_TYPE_TL); |
684 | tcg_gen_movi_tl(r_zero, 0); | |
83469015 | 685 | |
19f329ad | 686 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1); |
83469015 | 687 | |
6e256c93 | 688 | gen_goto_tb(dc, 0, pc1, pc1 + 4); |
83469015 FB |
689 | |
690 | gen_set_label(l1); | |
6e256c93 | 691 | gen_goto_tb(dc, 1, pc2, pc2 + 4); |
83469015 FB |
692 | } |
693 | ||
46525e1f | 694 | static inline void gen_branch_a(DisasContext *dc, target_ulong pc1, |
19f329ad | 695 | target_ulong pc2, TCGv r_cond) |
83469015 | 696 | { |
19f329ad | 697 | TCGv r_zero; |
83469015 FB |
698 | int l1; |
699 | ||
700 | l1 = gen_new_label(); | |
19f329ad BS |
701 | r_zero = tcg_temp_new(TCG_TYPE_TL); |
702 | tcg_gen_movi_tl(r_zero, 0); | |
83469015 | 703 | |
19f329ad | 704 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1); |
83469015 | 705 | |
6e256c93 | 706 | gen_goto_tb(dc, 0, pc2, pc1); |
83469015 FB |
707 | |
708 | gen_set_label(l1); | |
6e256c93 | 709 | gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8); |
83469015 FB |
710 | } |
711 | ||
46525e1f BS |
712 | static inline void gen_branch(DisasContext *dc, target_ulong pc, |
713 | target_ulong npc) | |
83469015 | 714 | { |
6e256c93 | 715 | gen_goto_tb(dc, 0, pc, npc); |
83469015 FB |
716 | } |
717 | ||
19f329ad BS |
718 | static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2, |
719 | TCGv r_cond) | |
83469015 | 720 | { |
19f329ad | 721 | TCGv r_zero; |
83469015 FB |
722 | int l1, l2; |
723 | ||
724 | l1 = gen_new_label(); | |
725 | l2 = gen_new_label(); | |
19f329ad BS |
726 | r_zero = tcg_temp_new(TCG_TYPE_TL); |
727 | tcg_gen_movi_tl(r_zero, 0); | |
728 | ||
729 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1); | |
83469015 FB |
730 | |
731 | gen_movl_npc_im(npc1); | |
732 | gen_op_jmp_label(l2); | |
733 | ||
734 | gen_set_label(l1); | |
735 | gen_movl_npc_im(npc2); | |
736 | gen_set_label(l2); | |
737 | } | |
738 | ||
739 | /* call this function before using T2 as it may have been set for a jump */ | |
740 | static inline void flush_T2(DisasContext * dc) | |
741 | { | |
742 | if (dc->npc == JUMP_PC) { | |
19f329ad | 743 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]); |
83469015 FB |
744 | dc->npc = DYNAMIC_PC; |
745 | } | |
746 | } | |
747 | ||
72cbca10 FB |
748 | static inline void save_npc(DisasContext * dc) |
749 | { | |
750 | if (dc->npc == JUMP_PC) { | |
19f329ad | 751 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]); |
72cbca10 FB |
752 | dc->npc = DYNAMIC_PC; |
753 | } else if (dc->npc != DYNAMIC_PC) { | |
3475187d | 754 | gen_movl_npc_im(dc->npc); |
72cbca10 FB |
755 | } |
756 | } | |
757 | ||
758 | static inline void save_state(DisasContext * dc) | |
759 | { | |
3475187d | 760 | gen_jmp_im(dc->pc); |
72cbca10 FB |
761 | save_npc(dc); |
762 | } | |
763 | ||
0bee699e FB |
764 | static inline void gen_mov_pc_npc(DisasContext * dc) |
765 | { | |
766 | if (dc->npc == JUMP_PC) { | |
19f329ad | 767 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]); |
38bc628b BS |
768 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc)); |
769 | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc)); | |
0bee699e FB |
770 | dc->pc = DYNAMIC_PC; |
771 | } else if (dc->npc == DYNAMIC_PC) { | |
38bc628b BS |
772 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc)); |
773 | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc)); | |
0bee699e FB |
774 | dc->pc = DYNAMIC_PC; |
775 | } else { | |
776 | dc->pc = dc->npc; | |
777 | } | |
778 | } | |
779 | ||
38bc628b BS |
780 | static inline void gen_op_next_insn(void) |
781 | { | |
782 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc)); | |
783 | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc)); | |
784 | tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, 4); | |
785 | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc)); | |
786 | } | |
787 | ||
19f329ad BS |
788 | static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond) |
789 | { | |
790 | TCGv r_src; | |
3475187d | 791 | |
19f329ad | 792 | r_src = tcg_temp_new(TCG_TYPE_TL); |
3475187d | 793 | #ifdef TARGET_SPARC64 |
19f329ad BS |
794 | if (cc) |
795 | tcg_gen_ld_i32(r_src, cpu_env, offsetof(CPUSPARCState, xcc)); | |
796 | else | |
797 | tcg_gen_ld_i32(r_src, cpu_env, offsetof(CPUSPARCState, psr)); | |
3475187d | 798 | #else |
19f329ad | 799 | tcg_gen_ld_i32(r_src, cpu_env, offsetof(CPUSPARCState, psr)); |
3475187d | 800 | #endif |
19f329ad BS |
801 | switch (cond) { |
802 | case 0x0: | |
803 | gen_op_eval_bn(r_dst); | |
804 | break; | |
805 | case 0x1: | |
806 | gen_op_eval_be(r_dst, r_src); | |
807 | break; | |
808 | case 0x2: | |
809 | gen_op_eval_ble(r_dst, r_src); | |
810 | break; | |
811 | case 0x3: | |
812 | gen_op_eval_bl(r_dst, r_src); | |
813 | break; | |
814 | case 0x4: | |
815 | gen_op_eval_bleu(r_dst, r_src); | |
816 | break; | |
817 | case 0x5: | |
818 | gen_op_eval_bcs(r_dst, r_src); | |
819 | break; | |
820 | case 0x6: | |
821 | gen_op_eval_bneg(r_dst, r_src); | |
822 | break; | |
823 | case 0x7: | |
824 | gen_op_eval_bvs(r_dst, r_src); | |
825 | break; | |
826 | case 0x8: | |
827 | gen_op_eval_ba(r_dst); | |
828 | break; | |
829 | case 0x9: | |
830 | gen_op_eval_bne(r_dst, r_src); | |
831 | break; | |
832 | case 0xa: | |
833 | gen_op_eval_bg(r_dst, r_src); | |
834 | break; | |
835 | case 0xb: | |
836 | gen_op_eval_bge(r_dst, r_src); | |
837 | break; | |
838 | case 0xc: | |
839 | gen_op_eval_bgu(r_dst, r_src); | |
840 | break; | |
841 | case 0xd: | |
842 | gen_op_eval_bcc(r_dst, r_src); | |
843 | break; | |
844 | case 0xe: | |
845 | gen_op_eval_bpos(r_dst, r_src); | |
846 | break; | |
847 | case 0xf: | |
848 | gen_op_eval_bvc(r_dst, r_src); | |
849 | break; | |
850 | } | |
851 | } | |
7a3f1944 | 852 | |
19f329ad | 853 | static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) |
e8af50a3 | 854 | { |
19f329ad BS |
855 | TCGv r_src; |
856 | unsigned int offset; | |
857 | ||
858 | r_src = tcg_temp_new(TCG_TYPE_TL); | |
859 | tcg_gen_ld_tl(r_src, cpu_env, offsetof(CPUSPARCState, fsr)); | |
860 | ||
861 | switch (cc) { | |
862 | default: | |
863 | case 0x0: | |
864 | offset = 0; | |
865 | break; | |
866 | case 0x1: | |
867 | offset = 32 - 10; | |
868 | break; | |
869 | case 0x2: | |
870 | offset = 34 - 10; | |
871 | break; | |
872 | case 0x3: | |
873 | offset = 36 - 10; | |
874 | break; | |
875 | } | |
876 | ||
877 | switch (cond) { | |
878 | case 0x0: | |
879 | gen_op_eval_bn(r_dst); | |
880 | break; | |
881 | case 0x1: | |
882 | gen_op_eval_fbne(r_dst, r_src, offset); | |
883 | break; | |
884 | case 0x2: | |
885 | gen_op_eval_fblg(r_dst, r_src, offset); | |
886 | break; | |
887 | case 0x3: | |
888 | gen_op_eval_fbul(r_dst, r_src, offset); | |
889 | break; | |
890 | case 0x4: | |
891 | gen_op_eval_fbl(r_dst, r_src, offset); | |
892 | break; | |
893 | case 0x5: | |
894 | gen_op_eval_fbug(r_dst, r_src, offset); | |
895 | break; | |
896 | case 0x6: | |
897 | gen_op_eval_fbg(r_dst, r_src, offset); | |
898 | break; | |
899 | case 0x7: | |
900 | gen_op_eval_fbu(r_dst, r_src, offset); | |
901 | break; | |
902 | case 0x8: | |
903 | gen_op_eval_ba(r_dst); | |
904 | break; | |
905 | case 0x9: | |
906 | gen_op_eval_fbe(r_dst, r_src, offset); | |
907 | break; | |
908 | case 0xa: | |
909 | gen_op_eval_fbue(r_dst, r_src, offset); | |
910 | break; | |
911 | case 0xb: | |
912 | gen_op_eval_fbge(r_dst, r_src, offset); | |
913 | break; | |
914 | case 0xc: | |
915 | gen_op_eval_fbuge(r_dst, r_src, offset); | |
916 | break; | |
917 | case 0xd: | |
918 | gen_op_eval_fble(r_dst, r_src, offset); | |
919 | break; | |
920 | case 0xe: | |
921 | gen_op_eval_fbule(r_dst, r_src, offset); | |
922 | break; | |
923 | case 0xf: | |
924 | gen_op_eval_fbo(r_dst, r_src, offset); | |
925 | break; | |
926 | } | |
e8af50a3 | 927 | } |
00f219bf | 928 | |
19f329ad | 929 | #ifdef TARGET_SPARC64 |
00f219bf BS |
930 | // Inverted logic |
931 | static const int gen_tcg_cond_reg[8] = { | |
932 | -1, | |
933 | TCG_COND_NE, | |
934 | TCG_COND_GT, | |
935 | TCG_COND_GE, | |
936 | -1, | |
937 | TCG_COND_EQ, | |
938 | TCG_COND_LE, | |
939 | TCG_COND_LT, | |
940 | }; | |
19f329ad BS |
941 | |
942 | static inline void gen_cond_reg(TCGv r_dst, int cond) | |
943 | { | |
944 | TCGv r_zero; | |
945 | int l1; | |
946 | ||
947 | l1 = gen_new_label(); | |
948 | r_zero = tcg_temp_new(TCG_TYPE_TL); | |
949 | tcg_gen_movi_tl(r_zero, 0); | |
950 | tcg_gen_mov_tl(r_dst, r_zero); | |
951 | tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1); | |
952 | tcg_gen_movi_tl(r_dst, 1); | |
953 | gen_set_label(l1); | |
954 | } | |
3475187d | 955 | #endif |
cf495bcf | 956 | |
0bee699e | 957 | /* XXX: potentially incorrect if dynamic npc */ |
3475187d | 958 | static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) |
7a3f1944 | 959 | { |
cf495bcf | 960 | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
af7bf89b | 961 | target_ulong target = dc->pc + offset; |
5fafdf24 | 962 | |
cf495bcf | 963 | if (cond == 0x0) { |
0f8a249a BS |
964 | /* unconditional not taken */ |
965 | if (a) { | |
966 | dc->pc = dc->npc + 4; | |
967 | dc->npc = dc->pc + 4; | |
968 | } else { | |
969 | dc->pc = dc->npc; | |
970 | dc->npc = dc->pc + 4; | |
971 | } | |
cf495bcf | 972 | } else if (cond == 0x8) { |
0f8a249a BS |
973 | /* unconditional taken */ |
974 | if (a) { | |
975 | dc->pc = target; | |
976 | dc->npc = dc->pc + 4; | |
977 | } else { | |
978 | dc->pc = dc->npc; | |
979 | dc->npc = target; | |
980 | } | |
cf495bcf | 981 | } else { |
72cbca10 | 982 | flush_T2(dc); |
19f329ad | 983 | gen_cond(cpu_T[2], cc, cond); |
0f8a249a | 984 | if (a) { |
19f329ad | 985 | gen_branch_a(dc, target, dc->npc, cpu_T[2]); |
cf495bcf | 986 | dc->is_br = 1; |
0f8a249a | 987 | } else { |
cf495bcf | 988 | dc->pc = dc->npc; |
72cbca10 FB |
989 | dc->jump_pc[0] = target; |
990 | dc->jump_pc[1] = dc->npc + 4; | |
991 | dc->npc = JUMP_PC; | |
0f8a249a | 992 | } |
cf495bcf | 993 | } |
7a3f1944 FB |
994 | } |
995 | ||
0bee699e | 996 | /* XXX: potentially incorrect if dynamic npc */ |
3475187d | 997 | static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) |
e8af50a3 FB |
998 | { |
999 | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); | |
af7bf89b FB |
1000 | target_ulong target = dc->pc + offset; |
1001 | ||
e8af50a3 | 1002 | if (cond == 0x0) { |
0f8a249a BS |
1003 | /* unconditional not taken */ |
1004 | if (a) { | |
1005 | dc->pc = dc->npc + 4; | |
1006 | dc->npc = dc->pc + 4; | |
1007 | } else { | |
1008 | dc->pc = dc->npc; | |
1009 | dc->npc = dc->pc + 4; | |
1010 | } | |
e8af50a3 | 1011 | } else if (cond == 0x8) { |
0f8a249a BS |
1012 | /* unconditional taken */ |
1013 | if (a) { | |
1014 | dc->pc = target; | |
1015 | dc->npc = dc->pc + 4; | |
1016 | } else { | |
1017 | dc->pc = dc->npc; | |
1018 | dc->npc = target; | |
1019 | } | |
e8af50a3 FB |
1020 | } else { |
1021 | flush_T2(dc); | |
19f329ad | 1022 | gen_fcond(cpu_T[2], cc, cond); |
0f8a249a | 1023 | if (a) { |
19f329ad | 1024 | gen_branch_a(dc, target, dc->npc, cpu_T[2]); |
e8af50a3 | 1025 | dc->is_br = 1; |
0f8a249a | 1026 | } else { |
e8af50a3 FB |
1027 | dc->pc = dc->npc; |
1028 | dc->jump_pc[0] = target; | |
1029 | dc->jump_pc[1] = dc->npc + 4; | |
1030 | dc->npc = JUMP_PC; | |
0f8a249a | 1031 | } |
e8af50a3 FB |
1032 | } |
1033 | } | |
1034 | ||
3475187d FB |
1035 | #ifdef TARGET_SPARC64 |
1036 | /* XXX: potentially incorrect if dynamic npc */ | |
1037 | static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn) | |
7a3f1944 | 1038 | { |
3475187d FB |
1039 | unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); |
1040 | target_ulong target = dc->pc + offset; | |
1041 | ||
1042 | flush_T2(dc); | |
19f329ad | 1043 | gen_cond_reg(cpu_T[2], cond); |
3475187d | 1044 | if (a) { |
19f329ad | 1045 | gen_branch_a(dc, target, dc->npc, cpu_T[2]); |
0f8a249a | 1046 | dc->is_br = 1; |
3475187d | 1047 | } else { |
0f8a249a BS |
1048 | dc->pc = dc->npc; |
1049 | dc->jump_pc[0] = target; | |
1050 | dc->jump_pc[1] = dc->npc + 4; | |
1051 | dc->npc = JUMP_PC; | |
3475187d | 1052 | } |
7a3f1944 FB |
1053 | } |
1054 | ||
3475187d | 1055 | static GenOpFunc * const gen_fcmps[4] = { |
7e8c2b6c BS |
1056 | helper_fcmps, |
1057 | helper_fcmps_fcc1, | |
1058 | helper_fcmps_fcc2, | |
1059 | helper_fcmps_fcc3, | |
3475187d FB |
1060 | }; |
1061 | ||
1062 | static GenOpFunc * const gen_fcmpd[4] = { | |
7e8c2b6c BS |
1063 | helper_fcmpd, |
1064 | helper_fcmpd_fcc1, | |
1065 | helper_fcmpd_fcc2, | |
1066 | helper_fcmpd_fcc3, | |
3475187d | 1067 | }; |
417454b0 | 1068 | |
1f587329 BS |
1069 | #if defined(CONFIG_USER_ONLY) |
1070 | static GenOpFunc * const gen_fcmpq[4] = { | |
7e8c2b6c BS |
1071 | helper_fcmpq, |
1072 | helper_fcmpq_fcc1, | |
1073 | helper_fcmpq_fcc2, | |
1074 | helper_fcmpq_fcc3, | |
1f587329 BS |
1075 | }; |
1076 | #endif | |
1077 | ||
417454b0 | 1078 | static GenOpFunc * const gen_fcmpes[4] = { |
7e8c2b6c BS |
1079 | helper_fcmpes, |
1080 | helper_fcmpes_fcc1, | |
1081 | helper_fcmpes_fcc2, | |
1082 | helper_fcmpes_fcc3, | |
417454b0 BS |
1083 | }; |
1084 | ||
1085 | static GenOpFunc * const gen_fcmped[4] = { | |
7e8c2b6c BS |
1086 | helper_fcmped, |
1087 | helper_fcmped_fcc1, | |
1088 | helper_fcmped_fcc2, | |
1089 | helper_fcmped_fcc3, | |
417454b0 BS |
1090 | }; |
1091 | ||
1f587329 BS |
1092 | #if defined(CONFIG_USER_ONLY) |
1093 | static GenOpFunc * const gen_fcmpeq[4] = { | |
7e8c2b6c BS |
1094 | helper_fcmpeq, |
1095 | helper_fcmpeq_fcc1, | |
1096 | helper_fcmpeq_fcc2, | |
1097 | helper_fcmpeq_fcc3, | |
1f587329 BS |
1098 | }; |
1099 | #endif | |
7e8c2b6c BS |
1100 | |
1101 | static inline void gen_op_fcmps(int fccno) | |
1102 | { | |
1103 | tcg_gen_helper_0_0(gen_fcmps[fccno]); | |
1104 | } | |
1105 | ||
1106 | static inline void gen_op_fcmpd(int fccno) | |
1107 | { | |
1108 | tcg_gen_helper_0_0(gen_fcmpd[fccno]); | |
1109 | } | |
1110 | ||
1111 | #if defined(CONFIG_USER_ONLY) | |
1112 | static inline void gen_op_fcmpq(int fccno) | |
1113 | { | |
1114 | tcg_gen_helper_0_0(gen_fcmpq[fccno]); | |
1115 | } | |
1116 | #endif | |
1117 | ||
1118 | static inline void gen_op_fcmpes(int fccno) | |
1119 | { | |
1120 | tcg_gen_helper_0_0(gen_fcmpes[fccno]); | |
1121 | } | |
1122 | ||
1123 | static inline void gen_op_fcmped(int fccno) | |
1124 | { | |
1125 | tcg_gen_helper_0_0(gen_fcmped[fccno]); | |
1126 | } | |
1127 | ||
1128 | #if defined(CONFIG_USER_ONLY) | |
1129 | static inline void gen_op_fcmpeq(int fccno) | |
1130 | { | |
1131 | tcg_gen_helper_0_0(gen_fcmpeq[fccno]); | |
1132 | } | |
1133 | #endif | |
1134 | ||
1135 | #else | |
1136 | ||
1137 | static inline void gen_op_fcmps(int fccno) | |
1138 | { | |
1139 | tcg_gen_helper_0_0(helper_fcmps); | |
1140 | } | |
1141 | ||
1142 | static inline void gen_op_fcmpd(int fccno) | |
1143 | { | |
1144 | tcg_gen_helper_0_0(helper_fcmpd); | |
1145 | } | |
1146 | ||
1147 | #if defined(CONFIG_USER_ONLY) | |
1148 | static inline void gen_op_fcmpq(int fccno) | |
1149 | { | |
1150 | tcg_gen_helper_0_0(helper_fcmpq); | |
1151 | } | |
1152 | #endif | |
1153 | ||
1154 | static inline void gen_op_fcmpes(int fccno) | |
1155 | { | |
1156 | tcg_gen_helper_0_0(helper_fcmpes); | |
1157 | } | |
1158 | ||
1159 | static inline void gen_op_fcmped(int fccno) | |
1160 | { | |
1161 | tcg_gen_helper_0_0(helper_fcmped); | |
1162 | } | |
1163 | ||
1164 | #if defined(CONFIG_USER_ONLY) | |
1165 | static inline void gen_op_fcmpeq(int fccno) | |
1166 | { | |
1167 | tcg_gen_helper_0_0(helper_fcmpeq); | |
1168 | } | |
1169 | #endif | |
1170 | ||
3475187d FB |
1171 | #endif |
1172 | ||
134d77a1 BS |
1173 | static inline void gen_op_exception(int exception) |
1174 | { | |
1175 | TCGv r_except; | |
1176 | ||
1177 | r_except = tcg_temp_new(TCG_TYPE_I32); | |
1178 | tcg_gen_movi_i32(r_except, exception); | |
1179 | tcg_gen_helper_0_1(raise_exception, r_except); | |
1180 | } | |
1181 | ||
1182 | static inline void gen_op_fpexception_im(int fsr_flags) | |
1183 | { | |
1184 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr)); | |
1185 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, ~FSR_FTT_MASK); | |
1186 | tcg_gen_ori_tl(cpu_tmp0, cpu_tmp0, fsr_flags); | |
1187 | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr)); | |
1188 | gen_op_exception(TT_FP_EXCP); | |
1189 | } | |
1190 | ||
a80dde08 FB |
1191 | static int gen_trap_ifnofpu(DisasContext * dc) |
1192 | { | |
1193 | #if !defined(CONFIG_USER_ONLY) | |
1194 | if (!dc->fpu_enabled) { | |
1195 | save_state(dc); | |
1196 | gen_op_exception(TT_NFPU_INSN); | |
1197 | dc->is_br = 1; | |
1198 | return 1; | |
1199 | } | |
1200 | #endif | |
1201 | return 0; | |
1202 | } | |
1203 | ||
7e8c2b6c BS |
1204 | static inline void gen_op_clear_ieee_excp_and_FTT(void) |
1205 | { | |
1206 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr)); | |
1207 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, ~(FSR_FTT_MASK | FSR_CEXC_MASK)); | |
1208 | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr)); | |
1209 | } | |
1210 | ||
1211 | static inline void gen_clear_float_exceptions(void) | |
1212 | { | |
1213 | tcg_gen_helper_0_0(helper_clear_float_exceptions); | |
1214 | } | |
1215 | ||
1a2fb1c0 BS |
1216 | /* asi moves */ |
1217 | #ifdef TARGET_SPARC64 | |
1218 | static inline void gen_ld_asi(int insn, int size, int sign) | |
1219 | { | |
1220 | int asi, offset; | |
1221 | TCGv r_size, r_sign; | |
1222 | ||
1223 | r_size = tcg_temp_new(TCG_TYPE_I32); | |
1224 | r_sign = tcg_temp_new(TCG_TYPE_I32); | |
1225 | tcg_gen_movi_i32(r_size, size); | |
1226 | tcg_gen_movi_i32(r_sign, sign); | |
1227 | if (IS_IMM) { | |
1228 | offset = GET_FIELD(insn, 25, 31); | |
1229 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset); | |
1230 | tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi)); | |
1231 | } else { | |
1232 | asi = GET_FIELD(insn, 19, 26); | |
1233 | tcg_gen_movi_i32(cpu_T[1], asi); | |
1234 | } | |
1235 | tcg_gen_helper_1_4(helper_ld_asi, cpu_T[1], cpu_T[0], cpu_T[1], r_size, | |
1236 | r_sign); | |
1237 | } | |
1238 | ||
1239 | static inline void gen_st_asi(int insn, int size) | |
1240 | { | |
1241 | int asi, offset; | |
1242 | TCGv r_asi, r_size; | |
1243 | ||
1244 | r_asi = tcg_temp_new(TCG_TYPE_I32); | |
1245 | r_size = tcg_temp_new(TCG_TYPE_I32); | |
1246 | tcg_gen_movi_i32(r_size, size); | |
1247 | if (IS_IMM) { | |
1248 | offset = GET_FIELD(insn, 25, 31); | |
1249 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset); | |
1250 | tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi)); | |
1251 | } else { | |
1252 | asi = GET_FIELD(insn, 19, 26); | |
1253 | tcg_gen_movi_i32(r_asi, asi); | |
1254 | } | |
1255 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_asi, r_size); | |
1256 | } | |
1257 | ||
1258 | static inline void gen_ldf_asi(int insn, int size, int rd) | |
1259 | { | |
1260 | int asi, offset; | |
1261 | TCGv r_asi, r_size, r_rd; | |
1262 | ||
1263 | r_asi = tcg_temp_new(TCG_TYPE_I32); | |
1264 | r_size = tcg_temp_new(TCG_TYPE_I32); | |
1265 | r_rd = tcg_temp_new(TCG_TYPE_I32); | |
1266 | tcg_gen_movi_i32(r_size, size); | |
1267 | tcg_gen_movi_i32(r_rd, rd); | |
1268 | if (IS_IMM) { | |
1269 | offset = GET_FIELD(insn, 25, 31); | |
1270 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset); | |
1271 | tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi)); | |
1272 | } else { | |
1273 | asi = GET_FIELD(insn, 19, 26); | |
1274 | tcg_gen_movi_i32(r_asi, asi); | |
1275 | } | |
1276 | tcg_gen_helper_0_4(helper_ldf_asi, cpu_T[0], r_asi, r_size, r_rd); | |
1277 | } | |
1278 | ||
1279 | static inline void gen_stf_asi(int insn, int size, int rd) | |
1280 | { | |
1281 | int asi, offset; | |
1282 | TCGv r_asi, r_size, r_rd; | |
1283 | ||
1284 | r_asi = tcg_temp_new(TCG_TYPE_I32); | |
1285 | r_size = tcg_temp_new(TCG_TYPE_I32); | |
1286 | r_rd = tcg_temp_new(TCG_TYPE_I32); | |
1287 | tcg_gen_movi_i32(r_size, size); | |
1288 | tcg_gen_movi_i32(r_rd, rd); | |
1289 | if (IS_IMM) { | |
1290 | offset = GET_FIELD(insn, 25, 31); | |
1291 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset); | |
1292 | tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi)); | |
1293 | } else { | |
1294 | asi = GET_FIELD(insn, 19, 26); | |
1295 | tcg_gen_movi_i32(r_asi, asi); | |
1296 | } | |
1297 | tcg_gen_helper_0_4(helper_stf_asi, cpu_T[0], r_asi, r_size, r_rd); | |
1298 | } | |
1299 | ||
1300 | static inline void gen_swap_asi(int insn) | |
1301 | { | |
1302 | int asi, offset; | |
1303 | TCGv r_size, r_sign, r_temp; | |
1304 | ||
1305 | r_size = tcg_temp_new(TCG_TYPE_I32); | |
1306 | r_sign = tcg_temp_new(TCG_TYPE_I32); | |
1307 | r_temp = tcg_temp_new(TCG_TYPE_I32); | |
1308 | tcg_gen_movi_i32(r_size, 4); | |
1309 | tcg_gen_movi_i32(r_sign, 0); | |
1310 | if (IS_IMM) { | |
1311 | offset = GET_FIELD(insn, 25, 31); | |
1312 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset); | |
1313 | tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi)); | |
1314 | } else { | |
1315 | asi = GET_FIELD(insn, 19, 26); | |
1316 | tcg_gen_movi_i32(cpu_T[1], asi); | |
1317 | } | |
1318 | tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], cpu_T[1], r_size, | |
1319 | r_sign); | |
1320 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_size, r_sign); | |
1321 | tcg_gen_mov_i32(cpu_T[1], r_temp); | |
1322 | } | |
1323 | ||
1324 | static inline void gen_ldda_asi(int insn) | |
1325 | { | |
1326 | int asi, offset; | |
1327 | TCGv r_size, r_sign, r_dword; | |
1328 | ||
1329 | r_size = tcg_temp_new(TCG_TYPE_I32); | |
1330 | r_sign = tcg_temp_new(TCG_TYPE_I32); | |
1331 | r_dword = tcg_temp_new(TCG_TYPE_I64); | |
1332 | tcg_gen_movi_i32(r_size, 8); | |
1333 | tcg_gen_movi_i32(r_sign, 0); | |
1334 | if (IS_IMM) { | |
1335 | offset = GET_FIELD(insn, 25, 31); | |
1336 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset); | |
1337 | tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi)); | |
1338 | } else { | |
1339 | asi = GET_FIELD(insn, 19, 26); | |
1340 | tcg_gen_movi_i32(cpu_T[1], asi); | |
1341 | } | |
1342 | tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size, | |
1343 | r_sign); | |
1344 | tcg_gen_trunc_i64_i32(cpu_T[0], r_dword); | |
1345 | tcg_gen_shri_i64(r_dword, r_dword, 32); | |
1346 | tcg_gen_trunc_i64_i32(cpu_T[1], r_dword); | |
1347 | } | |
1348 | ||
1349 | static inline void gen_cas_asi(int insn, int rd) | |
1350 | { | |
1351 | int asi, offset; | |
1352 | TCGv r_val1, r_asi; | |
1353 | ||
1354 | r_val1 = tcg_temp_new(TCG_TYPE_I32); | |
1355 | r_asi = tcg_temp_new(TCG_TYPE_I32); | |
1356 | gen_movl_reg_TN(rd, r_val1); | |
1357 | if (IS_IMM) { | |
1358 | offset = GET_FIELD(insn, 25, 31); | |
1359 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset); | |
1360 | tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi)); | |
1361 | } else { | |
1362 | asi = GET_FIELD(insn, 19, 26); | |
1363 | tcg_gen_movi_i32(r_asi, asi); | |
1364 | } | |
1365 | tcg_gen_helper_1_4(helper_cas_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1], | |
1366 | r_asi); | |
1367 | } | |
1368 | ||
1369 | static inline void gen_casx_asi(int insn, int rd) | |
1370 | { | |
1371 | int asi, offset; | |
1372 | TCGv r_val1, r_asi; | |
1373 | ||
1374 | r_val1 = tcg_temp_new(TCG_TYPE_I64); | |
1375 | r_asi = tcg_temp_new(TCG_TYPE_I32); | |
1376 | gen_movl_reg_TN(rd, r_val1); | |
1377 | if (IS_IMM) { | |
1378 | offset = GET_FIELD(insn, 25, 31); | |
1379 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset); | |
1380 | tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi)); | |
1381 | } else { | |
1382 | asi = GET_FIELD(insn, 19, 26); | |
1383 | tcg_gen_movi_i32(r_asi, asi); | |
1384 | } | |
1385 | tcg_gen_helper_1_4(helper_casx_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1], | |
1386 | r_asi); | |
1387 | } | |
1388 | ||
1389 | #elif !defined(CONFIG_USER_ONLY) | |
1390 | ||
1391 | static inline void gen_ld_asi(int insn, int size, int sign) | |
1392 | { | |
1393 | int asi; | |
1394 | TCGv r_size, r_sign, r_dword; | |
1395 | ||
1396 | r_size = tcg_temp_new(TCG_TYPE_I32); | |
1397 | r_sign = tcg_temp_new(TCG_TYPE_I32); | |
1398 | r_dword = tcg_temp_new(TCG_TYPE_I64); | |
1399 | tcg_gen_movi_i32(r_size, size); | |
1400 | tcg_gen_movi_i32(r_sign, sign); | |
1401 | asi = GET_FIELD(insn, 19, 26); | |
1402 | tcg_gen_movi_i32(cpu_T[1], asi); | |
1403 | tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size, | |
1404 | r_sign); | |
1405 | tcg_gen_trunc_i64_i32(cpu_T[1], r_dword); | |
1406 | } | |
1407 | ||
1408 | static inline void gen_st_asi(int insn, int size) | |
1409 | { | |
1410 | int asi; | |
1411 | TCGv r_dword, r_asi, r_size; | |
1412 | ||
1413 | r_dword = tcg_temp_new(TCG_TYPE_I64); | |
1414 | tcg_gen_extu_i32_i64(r_dword, cpu_T[1]); | |
1415 | r_asi = tcg_temp_new(TCG_TYPE_I32); | |
1416 | r_size = tcg_temp_new(TCG_TYPE_I32); | |
1417 | asi = GET_FIELD(insn, 19, 26); | |
1418 | tcg_gen_movi_i32(r_asi, asi); | |
1419 | tcg_gen_movi_i32(r_size, size); | |
1420 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_asi, r_size); | |
1421 | } | |
1422 | ||
1423 | static inline void gen_swap_asi(int insn) | |
1424 | { | |
1425 | int asi; | |
1426 | TCGv r_size, r_sign, r_temp; | |
1427 | ||
1428 | r_size = tcg_temp_new(TCG_TYPE_I32); | |
1429 | r_sign = tcg_temp_new(TCG_TYPE_I32); | |
1430 | r_temp = tcg_temp_new(TCG_TYPE_I32); | |
1431 | tcg_gen_movi_i32(r_size, 4); | |
1432 | tcg_gen_movi_i32(r_sign, 0); | |
1433 | asi = GET_FIELD(insn, 19, 26); | |
1434 | tcg_gen_movi_i32(cpu_T[1], asi); | |
1435 | tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], cpu_T[1], r_size, | |
1436 | r_sign); | |
1437 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_size, r_sign); | |
1438 | tcg_gen_mov_i32(cpu_T[1], r_temp); | |
1439 | } | |
1440 | ||
1441 | static inline void gen_ldda_asi(int insn) | |
1442 | { | |
1443 | int asi; | |
1444 | TCGv r_size, r_sign, r_dword; | |
1445 | ||
1446 | r_size = tcg_temp_new(TCG_TYPE_I32); | |
1447 | r_sign = tcg_temp_new(TCG_TYPE_I32); | |
1448 | r_dword = tcg_temp_new(TCG_TYPE_I64); | |
1449 | tcg_gen_movi_i32(r_size, 8); | |
1450 | tcg_gen_movi_i32(r_sign, 0); | |
1451 | asi = GET_FIELD(insn, 19, 26); | |
1452 | tcg_gen_movi_i32(cpu_T[1], asi); | |
1453 | tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size, | |
1454 | r_sign); | |
1455 | tcg_gen_trunc_i64_i32(cpu_T[0], r_dword); | |
1456 | tcg_gen_shri_i64(r_dword, r_dword, 32); | |
1457 | tcg_gen_trunc_i64_i32(cpu_T[1], r_dword); | |
1458 | } | |
1459 | #endif | |
1460 | ||
1461 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) | |
1462 | static inline void gen_ldstub_asi(int insn) | |
1463 | { | |
1464 | int asi; | |
1465 | TCGv r_dword, r_asi, r_size; | |
1466 | ||
1467 | gen_ld_asi(insn, 1, 0); | |
1468 | ||
1469 | r_dword = tcg_temp_new(TCG_TYPE_I64); | |
1470 | r_asi = tcg_temp_new(TCG_TYPE_I32); | |
1471 | r_size = tcg_temp_new(TCG_TYPE_I32); | |
1472 | asi = GET_FIELD(insn, 19, 26); | |
1473 | tcg_gen_movi_i32(r_dword, 0xff); | |
1474 | tcg_gen_movi_i32(r_asi, asi); | |
1475 | tcg_gen_movi_i32(r_size, 1); | |
1476 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_asi, r_size); | |
1477 | } | |
1478 | #endif | |
1479 | ||
0bee699e | 1480 | /* before an instruction, dc->pc must be static */ |
cf495bcf FB |
1481 | static void disas_sparc_insn(DisasContext * dc) |
1482 | { | |
1483 | unsigned int insn, opc, rs1, rs2, rd; | |
7a3f1944 | 1484 | |
0fa85d43 | 1485 | insn = ldl_code(dc->pc); |
cf495bcf | 1486 | opc = GET_FIELD(insn, 0, 1); |
7a3f1944 | 1487 | |
cf495bcf FB |
1488 | rd = GET_FIELD(insn, 2, 6); |
1489 | switch (opc) { | |
0f8a249a BS |
1490 | case 0: /* branches/sethi */ |
1491 | { | |
1492 | unsigned int xop = GET_FIELD(insn, 7, 9); | |
1493 | int32_t target; | |
1494 | switch (xop) { | |
3475187d | 1495 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
1496 | case 0x1: /* V9 BPcc */ |
1497 | { | |
1498 | int cc; | |
1499 | ||
1500 | target = GET_FIELD_SP(insn, 0, 18); | |
1501 | target = sign_extend(target, 18); | |
1502 | target <<= 2; | |
1503 | cc = GET_FIELD_SP(insn, 20, 21); | |
1504 | if (cc == 0) | |
1505 | do_branch(dc, target, insn, 0); | |
1506 | else if (cc == 2) | |
1507 | do_branch(dc, target, insn, 1); | |
1508 | else | |
1509 | goto illegal_insn; | |
1510 | goto jmp_insn; | |
1511 | } | |
1512 | case 0x3: /* V9 BPr */ | |
1513 | { | |
1514 | target = GET_FIELD_SP(insn, 0, 13) | | |
13846e70 | 1515 | (GET_FIELD_SP(insn, 20, 21) << 14); |
0f8a249a BS |
1516 | target = sign_extend(target, 16); |
1517 | target <<= 2; | |
1518 | rs1 = GET_FIELD(insn, 13, 17); | |
1519 | gen_movl_reg_T0(rs1); | |
1520 | do_branch_reg(dc, target, insn); | |
1521 | goto jmp_insn; | |
1522 | } | |
1523 | case 0x5: /* V9 FBPcc */ | |
1524 | { | |
1525 | int cc = GET_FIELD_SP(insn, 20, 21); | |
a80dde08 FB |
1526 | if (gen_trap_ifnofpu(dc)) |
1527 | goto jmp_insn; | |
0f8a249a BS |
1528 | target = GET_FIELD_SP(insn, 0, 18); |
1529 | target = sign_extend(target, 19); | |
1530 | target <<= 2; | |
1531 | do_fbranch(dc, target, insn, cc); | |
1532 | goto jmp_insn; | |
1533 | } | |
a4d17f19 | 1534 | #else |
0f8a249a BS |
1535 | case 0x7: /* CBN+x */ |
1536 | { | |
1537 | goto ncp_insn; | |
1538 | } | |
1539 | #endif | |
1540 | case 0x2: /* BN+x */ | |
1541 | { | |
1542 | target = GET_FIELD(insn, 10, 31); | |
1543 | target = sign_extend(target, 22); | |
1544 | target <<= 2; | |
1545 | do_branch(dc, target, insn, 0); | |
1546 | goto jmp_insn; | |
1547 | } | |
1548 | case 0x6: /* FBN+x */ | |
1549 | { | |
a80dde08 FB |
1550 | if (gen_trap_ifnofpu(dc)) |
1551 | goto jmp_insn; | |
0f8a249a BS |
1552 | target = GET_FIELD(insn, 10, 31); |
1553 | target = sign_extend(target, 22); | |
1554 | target <<= 2; | |
1555 | do_fbranch(dc, target, insn, 0); | |
1556 | goto jmp_insn; | |
1557 | } | |
1558 | case 0x4: /* SETHI */ | |
e80cfcfc FB |
1559 | #define OPTIM |
1560 | #if defined(OPTIM) | |
0f8a249a | 1561 | if (rd) { // nop |
e80cfcfc | 1562 | #endif |
0f8a249a | 1563 | uint32_t value = GET_FIELD(insn, 10, 31); |
1a2fb1c0 | 1564 | tcg_gen_movi_tl(cpu_T[0], value << 10); |
0f8a249a | 1565 | gen_movl_T0_reg(rd); |
e80cfcfc | 1566 | #if defined(OPTIM) |
0f8a249a | 1567 | } |
e80cfcfc | 1568 | #endif |
0f8a249a BS |
1569 | break; |
1570 | case 0x0: /* UNIMPL */ | |
1571 | default: | |
3475187d | 1572 | goto illegal_insn; |
0f8a249a BS |
1573 | } |
1574 | break; | |
1575 | } | |
1576 | break; | |
cf495bcf | 1577 | case 1: |
0f8a249a BS |
1578 | /*CALL*/ { |
1579 | target_long target = GET_FIELDs(insn, 2, 31) << 2; | |
cf495bcf | 1580 | |
1a2fb1c0 | 1581 | tcg_gen_movi_tl(cpu_T[0], dc->pc); |
0f8a249a BS |
1582 | gen_movl_T0_reg(15); |
1583 | target += dc->pc; | |
0bee699e | 1584 | gen_mov_pc_npc(dc); |
0f8a249a BS |
1585 | dc->npc = target; |
1586 | } | |
1587 | goto jmp_insn; | |
1588 | case 2: /* FPU & Logical Operations */ | |
1589 | { | |
1590 | unsigned int xop = GET_FIELD(insn, 7, 12); | |
1591 | if (xop == 0x3a) { /* generate trap */ | |
cf495bcf | 1592 | int cond; |
3475187d | 1593 | |
cf495bcf FB |
1594 | rs1 = GET_FIELD(insn, 13, 17); |
1595 | gen_movl_reg_T0(rs1); | |
0f8a249a BS |
1596 | if (IS_IMM) { |
1597 | rs2 = GET_FIELD(insn, 25, 31); | |
1a2fb1c0 | 1598 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], rs2); |
cf495bcf FB |
1599 | } else { |
1600 | rs2 = GET_FIELD(insn, 27, 31); | |
e80cfcfc | 1601 | #if defined(OPTIM) |
0f8a249a | 1602 | if (rs2 != 0) { |
e80cfcfc | 1603 | #endif |
0f8a249a BS |
1604 | gen_movl_reg_T1(rs2); |
1605 | gen_op_add_T1_T0(); | |
e80cfcfc | 1606 | #if defined(OPTIM) |
0f8a249a | 1607 | } |
e80cfcfc | 1608 | #endif |
cf495bcf | 1609 | } |
cf495bcf FB |
1610 | cond = GET_FIELD(insn, 3, 6); |
1611 | if (cond == 0x8) { | |
a80dde08 | 1612 | save_state(dc); |
1a2fb1c0 | 1613 | tcg_gen_helper_0_1(helper_trap, cpu_T[0]); |
af7bf89b | 1614 | } else if (cond != 0) { |
3475187d | 1615 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
1616 | /* V9 icc/xcc */ |
1617 | int cc = GET_FIELD_SP(insn, 11, 12); | |
1618 | flush_T2(dc); | |
a80dde08 | 1619 | save_state(dc); |
0f8a249a | 1620 | if (cc == 0) |
19f329ad | 1621 | gen_cond(cpu_T[2], 0, cond); |
0f8a249a | 1622 | else if (cc == 2) |
19f329ad | 1623 | gen_cond(cpu_T[2], 1, cond); |
0f8a249a BS |
1624 | else |
1625 | goto illegal_insn; | |
3475187d | 1626 | #else |
0f8a249a | 1627 | flush_T2(dc); |
a80dde08 | 1628 | save_state(dc); |
19f329ad | 1629 | gen_cond(cpu_T[2], 0, cond); |
3475187d | 1630 | #endif |
1a2fb1c0 | 1631 | tcg_gen_helper_0_2(helper_trapcc, cpu_T[0], cpu_T[2]); |
cf495bcf | 1632 | } |
a80dde08 | 1633 | gen_op_next_insn(); |
57fec1fe | 1634 | tcg_gen_exit_tb(0); |
a80dde08 FB |
1635 | dc->is_br = 1; |
1636 | goto jmp_insn; | |
cf495bcf FB |
1637 | } else if (xop == 0x28) { |
1638 | rs1 = GET_FIELD(insn, 13, 17); | |
1639 | switch(rs1) { | |
1640 | case 0: /* rdy */ | |
65fe7b09 BS |
1641 | #ifndef TARGET_SPARC64 |
1642 | case 0x01 ... 0x0e: /* undefined in the SPARCv8 | |
1643 | manual, rdy on the microSPARC | |
1644 | II */ | |
1645 | case 0x0f: /* stbar in the SPARCv8 manual, | |
1646 | rdy on the microSPARC II */ | |
1647 | case 0x10 ... 0x1f: /* implementation-dependent in the | |
1648 | SPARCv8 manual, rdy on the | |
1649 | microSPARC II */ | |
1650 | #endif | |
1651 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, y)); | |
cf495bcf FB |
1652 | gen_movl_T0_reg(rd); |
1653 | break; | |
3475187d | 1654 | #ifdef TARGET_SPARC64 |
0f8a249a | 1655 | case 0x2: /* V9 rdccr */ |
3475187d FB |
1656 | gen_op_rdccr(); |
1657 | gen_movl_T0_reg(rd); | |
1658 | break; | |
0f8a249a BS |
1659 | case 0x3: /* V9 rdasi */ |
1660 | gen_op_movl_T0_env(offsetof(CPUSPARCState, asi)); | |
3475187d FB |
1661 | gen_movl_T0_reg(rd); |
1662 | break; | |
0f8a249a | 1663 | case 0x4: /* V9 rdtick */ |
ccd4a219 BS |
1664 | { |
1665 | TCGv r_tickptr; | |
1666 | ||
1667 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
1668 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
1669 | offsetof(CPUState, tick)); | |
1670 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0], | |
1671 | r_tickptr); | |
1672 | gen_movl_T0_reg(rd); | |
1673 | } | |
3475187d | 1674 | break; |
0f8a249a | 1675 | case 0x5: /* V9 rdpc */ |
1a2fb1c0 | 1676 | tcg_gen_movi_tl(cpu_T[0], dc->pc); |
0f8a249a BS |
1677 | gen_movl_T0_reg(rd); |
1678 | break; | |
1679 | case 0x6: /* V9 rdfprs */ | |
1680 | gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs)); | |
3475187d FB |
1681 | gen_movl_T0_reg(rd); |
1682 | break; | |
65fe7b09 BS |
1683 | case 0xf: /* V9 membar */ |
1684 | break; /* no effect */ | |
0f8a249a | 1685 | case 0x13: /* Graphics Status */ |
725cb90b FB |
1686 | if (gen_trap_ifnofpu(dc)) |
1687 | goto jmp_insn; | |
0f8a249a | 1688 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr)); |
725cb90b FB |
1689 | gen_movl_T0_reg(rd); |
1690 | break; | |
0f8a249a BS |
1691 | case 0x17: /* Tick compare */ |
1692 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr)); | |
83469015 FB |
1693 | gen_movl_T0_reg(rd); |
1694 | break; | |
0f8a249a | 1695 | case 0x18: /* System tick */ |
ccd4a219 BS |
1696 | { |
1697 | TCGv r_tickptr; | |
1698 | ||
1699 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
1700 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
1701 | offsetof(CPUState, stick)); | |
1702 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0], | |
1703 | r_tickptr); | |
1704 | gen_movl_T0_reg(rd); | |
1705 | } | |
83469015 | 1706 | break; |
0f8a249a BS |
1707 | case 0x19: /* System tick compare */ |
1708 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr)); | |
83469015 FB |
1709 | gen_movl_T0_reg(rd); |
1710 | break; | |
0f8a249a BS |
1711 | case 0x10: /* Performance Control */ |
1712 | case 0x11: /* Performance Instrumentation Counter */ | |
1713 | case 0x12: /* Dispatch Control */ | |
1714 | case 0x14: /* Softint set, WO */ | |
1715 | case 0x15: /* Softint clear, WO */ | |
1716 | case 0x16: /* Softint write */ | |
3475187d FB |
1717 | #endif |
1718 | default: | |
cf495bcf FB |
1719 | goto illegal_insn; |
1720 | } | |
e8af50a3 | 1721 | #if !defined(CONFIG_USER_ONLY) |
e9ebed4d | 1722 | } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ |
3475187d | 1723 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
1724 | if (!supervisor(dc)) |
1725 | goto priv_insn; | |
1a2fb1c0 | 1726 | tcg_gen_helper_1_0(helper_rdpsr, cpu_T[0]); |
e9ebed4d BS |
1727 | #else |
1728 | if (!hypervisor(dc)) | |
1729 | goto priv_insn; | |
1730 | rs1 = GET_FIELD(insn, 13, 17); | |
1731 | switch (rs1) { | |
1732 | case 0: // hpstate | |
1733 | // gen_op_rdhpstate(); | |
1734 | break; | |
1735 | case 1: // htstate | |
1736 | // gen_op_rdhtstate(); | |
1737 | break; | |
1738 | case 3: // hintp | |
1739 | gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp)); | |
1740 | break; | |
1741 | case 5: // htba | |
1742 | gen_op_movl_T0_env(offsetof(CPUSPARCState, htba)); | |
1743 | break; | |
1744 | case 6: // hver | |
1745 | gen_op_movl_T0_env(offsetof(CPUSPARCState, hver)); | |
1746 | break; | |
1747 | case 31: // hstick_cmpr | |
1748 | gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr)); | |
1749 | break; | |
1750 | default: | |
1751 | goto illegal_insn; | |
1752 | } | |
1753 | #endif | |
e8af50a3 FB |
1754 | gen_movl_T0_reg(rd); |
1755 | break; | |
3475187d | 1756 | } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ |
0f8a249a BS |
1757 | if (!supervisor(dc)) |
1758 | goto priv_insn; | |
3475187d FB |
1759 | #ifdef TARGET_SPARC64 |
1760 | rs1 = GET_FIELD(insn, 13, 17); | |
0f8a249a BS |
1761 | switch (rs1) { |
1762 | case 0: // tpc | |
375ee38b BS |
1763 | { |
1764 | TCGv r_tsptr; | |
1765 | ||
1766 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
1767 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
1768 | offsetof(CPUState, tsptr)); | |
1769 | tcg_gen_ld_tl(cpu_T[0], r_tsptr, | |
1770 | offsetof(trap_state, tpc)); | |
1771 | } | |
0f8a249a BS |
1772 | break; |
1773 | case 1: // tnpc | |
375ee38b BS |
1774 | { |
1775 | TCGv r_tsptr; | |
1776 | ||
1777 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
1778 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
1779 | offsetof(CPUState, tsptr)); | |
1780 | tcg_gen_ld_tl(cpu_T[0], r_tsptr, | |
1781 | offsetof(trap_state, tnpc)); | |
1782 | } | |
0f8a249a BS |
1783 | break; |
1784 | case 2: // tstate | |
375ee38b BS |
1785 | { |
1786 | TCGv r_tsptr; | |
1787 | ||
1788 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
1789 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
1790 | offsetof(CPUState, tsptr)); | |
1791 | tcg_gen_ld_tl(cpu_T[0], r_tsptr, | |
1792 | offsetof(trap_state, tstate)); | |
1793 | } | |
0f8a249a BS |
1794 | break; |
1795 | case 3: // tt | |
375ee38b BS |
1796 | { |
1797 | TCGv r_tsptr; | |
1798 | ||
1799 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
1800 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
1801 | offsetof(CPUState, tsptr)); | |
1802 | tcg_gen_ld_i32(cpu_T[0], r_tsptr, | |
1803 | offsetof(trap_state, tt)); | |
1804 | } | |
0f8a249a BS |
1805 | break; |
1806 | case 4: // tick | |
ccd4a219 BS |
1807 | { |
1808 | TCGv r_tickptr; | |
1809 | ||
1810 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
1811 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
1812 | offsetof(CPUState, tick)); | |
1813 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0], | |
1814 | r_tickptr); | |
1815 | gen_movl_T0_reg(rd); | |
1816 | } | |
0f8a249a BS |
1817 | break; |
1818 | case 5: // tba | |
1819 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); | |
1820 | break; | |
1821 | case 6: // pstate | |
1a2fb1c0 | 1822 | gen_op_movl_T0_env(offsetof(CPUSPARCState, pstate)); |
0f8a249a BS |
1823 | break; |
1824 | case 7: // tl | |
1825 | gen_op_movl_T0_env(offsetof(CPUSPARCState, tl)); | |
1826 | break; | |
1827 | case 8: // pil | |
1828 | gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil)); | |
1829 | break; | |
1830 | case 9: // cwp | |
1831 | gen_op_rdcwp(); | |
1832 | break; | |
1833 | case 10: // cansave | |
1834 | gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave)); | |
1835 | break; | |
1836 | case 11: // canrestore | |
1837 | gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore)); | |
1838 | break; | |
1839 | case 12: // cleanwin | |
1840 | gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin)); | |
1841 | break; | |
1842 | case 13: // otherwin | |
1843 | gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin)); | |
1844 | break; | |
1845 | case 14: // wstate | |
1846 | gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate)); | |
1847 | break; | |
e9ebed4d BS |
1848 | case 16: // UA2005 gl |
1849 | gen_op_movl_T0_env(offsetof(CPUSPARCState, gl)); | |
1850 | break; | |
1851 | case 26: // UA2005 strand status | |
1852 | if (!hypervisor(dc)) | |
1853 | goto priv_insn; | |
1854 | gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr)); | |
1855 | break; | |
0f8a249a BS |
1856 | case 31: // ver |
1857 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, version)); | |
1858 | break; | |
1859 | case 15: // fq | |
1860 | default: | |
1861 | goto illegal_insn; | |
1862 | } | |
3475187d | 1863 | #else |
0f8a249a | 1864 | gen_op_movl_T0_env(offsetof(CPUSPARCState, wim)); |
3475187d | 1865 | #endif |
e8af50a3 FB |
1866 | gen_movl_T0_reg(rd); |
1867 | break; | |
3475187d FB |
1868 | } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ |
1869 | #ifdef TARGET_SPARC64 | |
0f8a249a | 1870 | gen_op_flushw(); |
3475187d | 1871 | #else |
0f8a249a BS |
1872 | if (!supervisor(dc)) |
1873 | goto priv_insn; | |
1874 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); | |
e8af50a3 | 1875 | gen_movl_T0_reg(rd); |
3475187d | 1876 | #endif |
e8af50a3 FB |
1877 | break; |
1878 | #endif | |
0f8a249a | 1879 | } else if (xop == 0x34) { /* FPU Operations */ |
a80dde08 FB |
1880 | if (gen_trap_ifnofpu(dc)) |
1881 | goto jmp_insn; | |
0f8a249a | 1882 | gen_op_clear_ieee_excp_and_FTT(); |
e8af50a3 | 1883 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a BS |
1884 | rs2 = GET_FIELD(insn, 27, 31); |
1885 | xop = GET_FIELD(insn, 18, 26); | |
1886 | switch (xop) { | |
1887 | case 0x1: /* fmovs */ | |
1888 | gen_op_load_fpr_FT0(rs2); | |
1889 | gen_op_store_FT0_fpr(rd); | |
1890 | break; | |
1891 | case 0x5: /* fnegs */ | |
1892 | gen_op_load_fpr_FT1(rs2); | |
1893 | gen_op_fnegs(); | |
1894 | gen_op_store_FT0_fpr(rd); | |
1895 | break; | |
1896 | case 0x9: /* fabss */ | |
1897 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 1898 | tcg_gen_helper_0_0(helper_fabss); |
0f8a249a BS |
1899 | gen_op_store_FT0_fpr(rd); |
1900 | break; | |
1901 | case 0x29: /* fsqrts */ | |
1902 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c BS |
1903 | gen_clear_float_exceptions(); |
1904 | tcg_gen_helper_0_0(helper_fsqrts); | |
1905 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); | |
0f8a249a BS |
1906 | gen_op_store_FT0_fpr(rd); |
1907 | break; | |
1908 | case 0x2a: /* fsqrtd */ | |
1909 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c BS |
1910 | gen_clear_float_exceptions(); |
1911 | tcg_gen_helper_0_0(helper_fsqrtd); | |
1912 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); | |
0f8a249a BS |
1913 | gen_op_store_DT0_fpr(DFPREG(rd)); |
1914 | break; | |
1915 | case 0x2b: /* fsqrtq */ | |
1f587329 BS |
1916 | #if defined(CONFIG_USER_ONLY) |
1917 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c BS |
1918 | gen_clear_float_exceptions(); |
1919 | tcg_gen_helper_0_0(helper_fsqrtq); | |
1920 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); | |
1f587329 BS |
1921 | gen_op_store_QT0_fpr(QFPREG(rd)); |
1922 | break; | |
1923 | #else | |
0f8a249a | 1924 | goto nfpu_insn; |
1f587329 | 1925 | #endif |
0f8a249a BS |
1926 | case 0x41: |
1927 | gen_op_load_fpr_FT0(rs1); | |
1928 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 1929 | gen_clear_float_exceptions(); |
0f8a249a | 1930 | gen_op_fadds(); |
7e8c2b6c | 1931 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
1932 | gen_op_store_FT0_fpr(rd); |
1933 | break; | |
1934 | case 0x42: | |
1935 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
1936 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 1937 | gen_clear_float_exceptions(); |
0f8a249a | 1938 | gen_op_faddd(); |
7e8c2b6c | 1939 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
1940 | gen_op_store_DT0_fpr(DFPREG(rd)); |
1941 | break; | |
1942 | case 0x43: /* faddq */ | |
1f587329 BS |
1943 | #if defined(CONFIG_USER_ONLY) |
1944 | gen_op_load_fpr_QT0(QFPREG(rs1)); | |
1945 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 1946 | gen_clear_float_exceptions(); |
1f587329 | 1947 | gen_op_faddq(); |
7e8c2b6c | 1948 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
1949 | gen_op_store_QT0_fpr(QFPREG(rd)); |
1950 | break; | |
1951 | #else | |
0f8a249a | 1952 | goto nfpu_insn; |
1f587329 | 1953 | #endif |
0f8a249a BS |
1954 | case 0x45: |
1955 | gen_op_load_fpr_FT0(rs1); | |
1956 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 1957 | gen_clear_float_exceptions(); |
0f8a249a | 1958 | gen_op_fsubs(); |
7e8c2b6c | 1959 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
1960 | gen_op_store_FT0_fpr(rd); |
1961 | break; | |
1962 | case 0x46: | |
1963 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
1964 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 1965 | gen_clear_float_exceptions(); |
0f8a249a | 1966 | gen_op_fsubd(); |
7e8c2b6c | 1967 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
1968 | gen_op_store_DT0_fpr(DFPREG(rd)); |
1969 | break; | |
1970 | case 0x47: /* fsubq */ | |
1f587329 BS |
1971 | #if defined(CONFIG_USER_ONLY) |
1972 | gen_op_load_fpr_QT0(QFPREG(rs1)); | |
1973 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 1974 | gen_clear_float_exceptions(); |
1f587329 | 1975 | gen_op_fsubq(); |
7e8c2b6c | 1976 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
1977 | gen_op_store_QT0_fpr(QFPREG(rd)); |
1978 | break; | |
1979 | #else | |
0f8a249a | 1980 | goto nfpu_insn; |
1f587329 | 1981 | #endif |
0f8a249a BS |
1982 | case 0x49: |
1983 | gen_op_load_fpr_FT0(rs1); | |
1984 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 1985 | gen_clear_float_exceptions(); |
0f8a249a | 1986 | gen_op_fmuls(); |
7e8c2b6c | 1987 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
1988 | gen_op_store_FT0_fpr(rd); |
1989 | break; | |
1990 | case 0x4a: | |
1991 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
1992 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 1993 | gen_clear_float_exceptions(); |
0f8a249a | 1994 | gen_op_fmuld(); |
7e8c2b6c | 1995 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2382dc6b | 1996 | gen_op_store_DT0_fpr(DFPREG(rd)); |
0f8a249a BS |
1997 | break; |
1998 | case 0x4b: /* fmulq */ | |
1f587329 BS |
1999 | #if defined(CONFIG_USER_ONLY) |
2000 | gen_op_load_fpr_QT0(QFPREG(rs1)); | |
2001 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2002 | gen_clear_float_exceptions(); |
1f587329 | 2003 | gen_op_fmulq(); |
7e8c2b6c | 2004 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2005 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2006 | break; | |
2007 | #else | |
0f8a249a | 2008 | goto nfpu_insn; |
1f587329 | 2009 | #endif |
0f8a249a BS |
2010 | case 0x4d: |
2011 | gen_op_load_fpr_FT0(rs1); | |
2012 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2013 | gen_clear_float_exceptions(); |
0f8a249a | 2014 | gen_op_fdivs(); |
7e8c2b6c | 2015 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2016 | gen_op_store_FT0_fpr(rd); |
2017 | break; | |
2018 | case 0x4e: | |
2019 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
2020 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2021 | gen_clear_float_exceptions(); |
0f8a249a | 2022 | gen_op_fdivd(); |
7e8c2b6c | 2023 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2024 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2025 | break; | |
2026 | case 0x4f: /* fdivq */ | |
1f587329 BS |
2027 | #if defined(CONFIG_USER_ONLY) |
2028 | gen_op_load_fpr_QT0(QFPREG(rs1)); | |
2029 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2030 | gen_clear_float_exceptions(); |
1f587329 | 2031 | gen_op_fdivq(); |
7e8c2b6c | 2032 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2033 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2034 | break; | |
2035 | #else | |
0f8a249a | 2036 | goto nfpu_insn; |
1f587329 | 2037 | #endif |
0f8a249a BS |
2038 | case 0x69: |
2039 | gen_op_load_fpr_FT0(rs1); | |
2040 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2041 | gen_clear_float_exceptions(); |
0f8a249a | 2042 | gen_op_fsmuld(); |
7e8c2b6c | 2043 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2044 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2045 | break; | |
2046 | case 0x6e: /* fdmulq */ | |
1f587329 BS |
2047 | #if defined(CONFIG_USER_ONLY) |
2048 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
2049 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2050 | gen_clear_float_exceptions(); |
1f587329 | 2051 | gen_op_fdmulq(); |
7e8c2b6c | 2052 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2053 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2054 | break; | |
2055 | #else | |
0f8a249a | 2056 | goto nfpu_insn; |
1f587329 | 2057 | #endif |
0f8a249a BS |
2058 | case 0xc4: |
2059 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2060 | gen_clear_float_exceptions(); |
0f8a249a | 2061 | gen_op_fitos(); |
7e8c2b6c | 2062 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2063 | gen_op_store_FT0_fpr(rd); |
2064 | break; | |
2065 | case 0xc6: | |
2066 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2067 | gen_clear_float_exceptions(); |
0f8a249a | 2068 | gen_op_fdtos(); |
7e8c2b6c | 2069 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2070 | gen_op_store_FT0_fpr(rd); |
2071 | break; | |
2072 | case 0xc7: /* fqtos */ | |
1f587329 BS |
2073 | #if defined(CONFIG_USER_ONLY) |
2074 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2075 | gen_clear_float_exceptions(); |
1f587329 | 2076 | gen_op_fqtos(); |
7e8c2b6c | 2077 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2078 | gen_op_store_FT0_fpr(rd); |
2079 | break; | |
2080 | #else | |
0f8a249a | 2081 | goto nfpu_insn; |
1f587329 | 2082 | #endif |
0f8a249a BS |
2083 | case 0xc8: |
2084 | gen_op_load_fpr_FT1(rs2); | |
2085 | gen_op_fitod(); | |
2086 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
2087 | break; | |
2088 | case 0xc9: | |
2089 | gen_op_load_fpr_FT1(rs2); | |
2090 | gen_op_fstod(); | |
2091 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
2092 | break; | |
2093 | case 0xcb: /* fqtod */ | |
1f587329 BS |
2094 | #if defined(CONFIG_USER_ONLY) |
2095 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2096 | gen_clear_float_exceptions(); |
1f587329 | 2097 | gen_op_fqtod(); |
7e8c2b6c | 2098 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2099 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2100 | break; | |
2101 | #else | |
0f8a249a | 2102 | goto nfpu_insn; |
1f587329 | 2103 | #endif |
0f8a249a | 2104 | case 0xcc: /* fitoq */ |
1f587329 BS |
2105 | #if defined(CONFIG_USER_ONLY) |
2106 | gen_op_load_fpr_FT1(rs2); | |
2107 | gen_op_fitoq(); | |
2108 | gen_op_store_QT0_fpr(QFPREG(rd)); | |
2109 | break; | |
2110 | #else | |
0f8a249a | 2111 | goto nfpu_insn; |
1f587329 | 2112 | #endif |
0f8a249a | 2113 | case 0xcd: /* fstoq */ |
1f587329 BS |
2114 | #if defined(CONFIG_USER_ONLY) |
2115 | gen_op_load_fpr_FT1(rs2); | |
2116 | gen_op_fstoq(); | |
2117 | gen_op_store_QT0_fpr(QFPREG(rd)); | |
2118 | break; | |
2119 | #else | |
0f8a249a | 2120 | goto nfpu_insn; |
1f587329 | 2121 | #endif |
0f8a249a | 2122 | case 0xce: /* fdtoq */ |
1f587329 BS |
2123 | #if defined(CONFIG_USER_ONLY) |
2124 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
2125 | gen_op_fdtoq(); | |
2126 | gen_op_store_QT0_fpr(QFPREG(rd)); | |
2127 | break; | |
2128 | #else | |
0f8a249a | 2129 | goto nfpu_insn; |
1f587329 | 2130 | #endif |
0f8a249a BS |
2131 | case 0xd1: |
2132 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2133 | gen_clear_float_exceptions(); |
0f8a249a | 2134 | gen_op_fstoi(); |
7e8c2b6c | 2135 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2136 | gen_op_store_FT0_fpr(rd); |
2137 | break; | |
2138 | case 0xd2: | |
2382dc6b | 2139 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
7e8c2b6c | 2140 | gen_clear_float_exceptions(); |
0f8a249a | 2141 | gen_op_fdtoi(); |
7e8c2b6c | 2142 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2143 | gen_op_store_FT0_fpr(rd); |
2144 | break; | |
2145 | case 0xd3: /* fqtoi */ | |
1f587329 BS |
2146 | #if defined(CONFIG_USER_ONLY) |
2147 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2148 | gen_clear_float_exceptions(); |
1f587329 | 2149 | gen_op_fqtoi(); |
7e8c2b6c | 2150 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2151 | gen_op_store_FT0_fpr(rd); |
2152 | break; | |
2153 | #else | |
0f8a249a | 2154 | goto nfpu_insn; |
1f587329 | 2155 | #endif |
3475187d | 2156 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
2157 | case 0x2: /* V9 fmovd */ |
2158 | gen_op_load_fpr_DT0(DFPREG(rs2)); | |
2159 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
2160 | break; | |
1f587329 BS |
2161 | case 0x3: /* V9 fmovq */ |
2162 | #if defined(CONFIG_USER_ONLY) | |
2163 | gen_op_load_fpr_QT0(QFPREG(rs2)); | |
2164 | gen_op_store_QT0_fpr(QFPREG(rd)); | |
2165 | break; | |
2166 | #else | |
2167 | goto nfpu_insn; | |
2168 | #endif | |
0f8a249a BS |
2169 | case 0x6: /* V9 fnegd */ |
2170 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
2171 | gen_op_fnegd(); | |
2172 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
2173 | break; | |
1f587329 BS |
2174 | case 0x7: /* V9 fnegq */ |
2175 | #if defined(CONFIG_USER_ONLY) | |
2176 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
2177 | gen_op_fnegq(); | |
2178 | gen_op_store_QT0_fpr(QFPREG(rd)); | |
2179 | break; | |
2180 | #else | |
2181 | goto nfpu_insn; | |
2182 | #endif | |
0f8a249a BS |
2183 | case 0xa: /* V9 fabsd */ |
2184 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2185 | tcg_gen_helper_0_0(helper_fabsd); |
0f8a249a BS |
2186 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2187 | break; | |
1f587329 BS |
2188 | case 0xb: /* V9 fabsq */ |
2189 | #if defined(CONFIG_USER_ONLY) | |
2190 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2191 | tcg_gen_helper_0_0(helper_fabsq); |
1f587329 BS |
2192 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2193 | break; | |
2194 | #else | |
2195 | goto nfpu_insn; | |
2196 | #endif | |
0f8a249a BS |
2197 | case 0x81: /* V9 fstox */ |
2198 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2199 | gen_clear_float_exceptions(); |
0f8a249a | 2200 | gen_op_fstox(); |
7e8c2b6c | 2201 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2202 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2203 | break; | |
2204 | case 0x82: /* V9 fdtox */ | |
2205 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2206 | gen_clear_float_exceptions(); |
0f8a249a | 2207 | gen_op_fdtox(); |
7e8c2b6c | 2208 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2209 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2210 | break; | |
1f587329 BS |
2211 | case 0x83: /* V9 fqtox */ |
2212 | #if defined(CONFIG_USER_ONLY) | |
2213 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2214 | gen_clear_float_exceptions(); |
1f587329 | 2215 | gen_op_fqtox(); |
7e8c2b6c | 2216 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2217 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2218 | break; | |
2219 | #else | |
2220 | goto nfpu_insn; | |
2221 | #endif | |
0f8a249a BS |
2222 | case 0x84: /* V9 fxtos */ |
2223 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2224 | gen_clear_float_exceptions(); |
0f8a249a | 2225 | gen_op_fxtos(); |
7e8c2b6c | 2226 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2227 | gen_op_store_FT0_fpr(rd); |
2228 | break; | |
2229 | case 0x88: /* V9 fxtod */ | |
2230 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2231 | gen_clear_float_exceptions(); |
0f8a249a | 2232 | gen_op_fxtod(); |
7e8c2b6c | 2233 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2234 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2235 | break; | |
0f8a249a | 2236 | case 0x8c: /* V9 fxtoq */ |
1f587329 BS |
2237 | #if defined(CONFIG_USER_ONLY) |
2238 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2239 | gen_clear_float_exceptions(); |
1f587329 | 2240 | gen_op_fxtoq(); |
7e8c2b6c | 2241 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2242 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2243 | break; | |
2244 | #else | |
0f8a249a | 2245 | goto nfpu_insn; |
1f587329 | 2246 | #endif |
0f8a249a BS |
2247 | #endif |
2248 | default: | |
2249 | goto illegal_insn; | |
2250 | } | |
2251 | } else if (xop == 0x35) { /* FPU Operations */ | |
3475187d | 2252 | #ifdef TARGET_SPARC64 |
0f8a249a | 2253 | int cond; |
3475187d | 2254 | #endif |
a80dde08 FB |
2255 | if (gen_trap_ifnofpu(dc)) |
2256 | goto jmp_insn; | |
0f8a249a | 2257 | gen_op_clear_ieee_excp_and_FTT(); |
cf495bcf | 2258 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a BS |
2259 | rs2 = GET_FIELD(insn, 27, 31); |
2260 | xop = GET_FIELD(insn, 18, 26); | |
3475187d | 2261 | #ifdef TARGET_SPARC64 |
0f8a249a | 2262 | if ((xop & 0x11f) == 0x005) { // V9 fmovsr |
dcf24905 BS |
2263 | TCGv r_zero; |
2264 | int l1; | |
2265 | ||
2266 | l1 = gen_new_label(); | |
2267 | r_zero = tcg_temp_new(TCG_TYPE_TL); | |
0f8a249a | 2268 | cond = GET_FIELD_SP(insn, 14, 17); |
0f8a249a BS |
2269 | rs1 = GET_FIELD(insn, 13, 17); |
2270 | gen_movl_reg_T0(rs1); | |
dcf24905 BS |
2271 | tcg_gen_movi_tl(r_zero, 0); |
2272 | tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1); | |
19f329ad | 2273 | gen_op_load_fpr_FT0(rs2); |
0f8a249a | 2274 | gen_op_store_FT0_fpr(rd); |
dcf24905 | 2275 | gen_set_label(l1); |
0f8a249a BS |
2276 | break; |
2277 | } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr | |
dcf24905 BS |
2278 | TCGv r_zero; |
2279 | int l1; | |
2280 | ||
2281 | l1 = gen_new_label(); | |
2282 | r_zero = tcg_temp_new(TCG_TYPE_TL); | |
0f8a249a | 2283 | cond = GET_FIELD_SP(insn, 14, 17); |
0f8a249a BS |
2284 | rs1 = GET_FIELD(insn, 13, 17); |
2285 | gen_movl_reg_T0(rs1); | |
dcf24905 BS |
2286 | tcg_gen_movi_tl(r_zero, 0); |
2287 | tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1); | |
19f329ad | 2288 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
2382dc6b | 2289 | gen_op_store_DT0_fpr(DFPREG(rd)); |
dcf24905 | 2290 | gen_set_label(l1); |
0f8a249a BS |
2291 | break; |
2292 | } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr | |
1f587329 | 2293 | #if defined(CONFIG_USER_ONLY) |
dcf24905 BS |
2294 | TCGv r_zero; |
2295 | int l1; | |
2296 | ||
2297 | l1 = gen_new_label(); | |
2298 | r_zero = tcg_temp_new(TCG_TYPE_TL); | |
1f587329 | 2299 | cond = GET_FIELD_SP(insn, 14, 17); |
1f587329 BS |
2300 | rs1 = GET_FIELD(insn, 13, 17); |
2301 | gen_movl_reg_T0(rs1); | |
dcf24905 BS |
2302 | tcg_gen_movi_tl(r_zero, 0); |
2303 | tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1); | |
19f329ad | 2304 | gen_op_load_fpr_QT0(QFPREG(rs2)); |
1f587329 | 2305 | gen_op_store_QT0_fpr(QFPREG(rd)); |
dcf24905 | 2306 | gen_set_label(l1); |
1f587329 BS |
2307 | break; |
2308 | #else | |
0f8a249a | 2309 | goto nfpu_insn; |
1f587329 | 2310 | #endif |
0f8a249a BS |
2311 | } |
2312 | #endif | |
2313 | switch (xop) { | |
3475187d | 2314 | #ifdef TARGET_SPARC64 |
19f329ad BS |
2315 | #define FMOVCC(size_FDQ, fcc) \ |
2316 | { \ | |
2317 | TCGv r_zero, r_cond; \ | |
2318 | int l1; \ | |
2319 | \ | |
2320 | l1 = gen_new_label(); \ | |
2321 | r_zero = tcg_temp_new(TCG_TYPE_TL); \ | |
2322 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ | |
2323 | tcg_gen_movi_tl(r_zero, 0); \ | |
2324 | cond = GET_FIELD_SP(insn, 14, 17); \ | |
2325 | gen_fcond(r_cond, fcc, cond); \ | |
2326 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1); \ | |
2327 | glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \ | |
2328 | glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \ | |
2329 | gen_set_label(l1); \ | |
2330 | } | |
0f8a249a | 2331 | case 0x001: /* V9 fmovscc %fcc0 */ |
19f329ad | 2332 | FMOVCC(F, 0); |
0f8a249a BS |
2333 | break; |
2334 | case 0x002: /* V9 fmovdcc %fcc0 */ | |
19f329ad | 2335 | FMOVCC(D, 0); |
0f8a249a BS |
2336 | break; |
2337 | case 0x003: /* V9 fmovqcc %fcc0 */ | |
1f587329 | 2338 | #if defined(CONFIG_USER_ONLY) |
19f329ad | 2339 | FMOVCC(Q, 0); |
1f587329 BS |
2340 | break; |
2341 | #else | |
0f8a249a | 2342 | goto nfpu_insn; |
1f587329 | 2343 | #endif |
0f8a249a | 2344 | case 0x041: /* V9 fmovscc %fcc1 */ |
19f329ad | 2345 | FMOVCC(F, 1); |
0f8a249a BS |
2346 | break; |
2347 | case 0x042: /* V9 fmovdcc %fcc1 */ | |
19f329ad | 2348 | FMOVCC(D, 1); |
0f8a249a BS |
2349 | break; |
2350 | case 0x043: /* V9 fmovqcc %fcc1 */ | |
1f587329 | 2351 | #if defined(CONFIG_USER_ONLY) |
19f329ad | 2352 | FMOVCC(Q, 1); |
1f587329 BS |
2353 | break; |
2354 | #else | |
0f8a249a | 2355 | goto nfpu_insn; |
1f587329 | 2356 | #endif |
0f8a249a | 2357 | case 0x081: /* V9 fmovscc %fcc2 */ |
19f329ad | 2358 | FMOVCC(F, 2); |
0f8a249a BS |
2359 | break; |
2360 | case 0x082: /* V9 fmovdcc %fcc2 */ | |
19f329ad | 2361 | FMOVCC(D, 2); |
0f8a249a BS |
2362 | break; |
2363 | case 0x083: /* V9 fmovqcc %fcc2 */ | |
1f587329 | 2364 | #if defined(CONFIG_USER_ONLY) |
19f329ad | 2365 | FMOVCC(Q, 2); |
1f587329 BS |
2366 | break; |
2367 | #else | |
0f8a249a | 2368 | goto nfpu_insn; |
1f587329 | 2369 | #endif |
0f8a249a | 2370 | case 0x0c1: /* V9 fmovscc %fcc3 */ |
19f329ad | 2371 | FMOVCC(F, 3); |
0f8a249a BS |
2372 | break; |
2373 | case 0x0c2: /* V9 fmovdcc %fcc3 */ | |
19f329ad | 2374 | FMOVCC(D, 3); |
0f8a249a BS |
2375 | break; |
2376 | case 0x0c3: /* V9 fmovqcc %fcc3 */ | |
1f587329 | 2377 | #if defined(CONFIG_USER_ONLY) |
19f329ad | 2378 | FMOVCC(Q, 3); |
1f587329 BS |
2379 | break; |
2380 | #else | |
0f8a249a | 2381 | goto nfpu_insn; |
1f587329 | 2382 | #endif |
19f329ad BS |
2383 | #undef FMOVCC |
2384 | #define FMOVCC(size_FDQ, icc) \ | |
2385 | { \ | |
2386 | TCGv r_zero, r_cond; \ | |
2387 | int l1; \ | |
2388 | \ | |
2389 | l1 = gen_new_label(); \ | |
2390 | r_zero = tcg_temp_new(TCG_TYPE_TL); \ | |
2391 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ | |
2392 | tcg_gen_movi_tl(r_zero, 0); \ | |
2393 | cond = GET_FIELD_SP(insn, 14, 17); \ | |
2394 | gen_cond(r_cond, icc, cond); \ | |
2395 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1); \ | |
2396 | glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \ | |
2397 | glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \ | |
2398 | gen_set_label(l1); \ | |
2399 | } | |
2400 | ||
0f8a249a | 2401 | case 0x101: /* V9 fmovscc %icc */ |
19f329ad | 2402 | FMOVCC(F, 0); |
0f8a249a BS |
2403 | break; |
2404 | case 0x102: /* V9 fmovdcc %icc */ | |
19f329ad | 2405 | FMOVCC(D, 0); |
0f8a249a | 2406 | case 0x103: /* V9 fmovqcc %icc */ |
1f587329 | 2407 | #if defined(CONFIG_USER_ONLY) |
19f329ad | 2408 | FMOVCC(D, 0); |
1f587329 BS |
2409 | break; |
2410 | #else | |
0f8a249a | 2411 | goto nfpu_insn; |
1f587329 | 2412 | #endif |
0f8a249a | 2413 | case 0x181: /* V9 fmovscc %xcc */ |
19f329ad | 2414 | FMOVCC(F, 1); |
0f8a249a BS |
2415 | break; |
2416 | case 0x182: /* V9 fmovdcc %xcc */ | |
19f329ad | 2417 | FMOVCC(D, 1); |
0f8a249a BS |
2418 | break; |
2419 | case 0x183: /* V9 fmovqcc %xcc */ | |
1f587329 | 2420 | #if defined(CONFIG_USER_ONLY) |
19f329ad | 2421 | FMOVCC(Q, 1); |
1f587329 BS |
2422 | break; |
2423 | #else | |
0f8a249a BS |
2424 | goto nfpu_insn; |
2425 | #endif | |
19f329ad | 2426 | #undef FMOVCC |
1f587329 BS |
2427 | #endif |
2428 | case 0x51: /* fcmps, V9 %fcc */ | |
0f8a249a BS |
2429 | gen_op_load_fpr_FT0(rs1); |
2430 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2431 | gen_op_fcmps(rd & 3); |
0f8a249a | 2432 | break; |
1f587329 | 2433 | case 0x52: /* fcmpd, V9 %fcc */ |
0f8a249a BS |
2434 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2435 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2436 | gen_op_fcmpd(rd & 3); |
0f8a249a | 2437 | break; |
1f587329 BS |
2438 | case 0x53: /* fcmpq, V9 %fcc */ |
2439 | #if defined(CONFIG_USER_ONLY) | |
2440 | gen_op_load_fpr_QT0(QFPREG(rs1)); | |
2441 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2442 | gen_op_fcmpq(rd & 3); |
1f587329 BS |
2443 | break; |
2444 | #else /* !defined(CONFIG_USER_ONLY) */ | |
0f8a249a | 2445 | goto nfpu_insn; |
1f587329 | 2446 | #endif |
0f8a249a BS |
2447 | case 0x55: /* fcmpes, V9 %fcc */ |
2448 | gen_op_load_fpr_FT0(rs1); | |
2449 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2450 | gen_op_fcmpes(rd & 3); |
0f8a249a BS |
2451 | break; |
2452 | case 0x56: /* fcmped, V9 %fcc */ | |
2453 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
2454 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2455 | gen_op_fcmped(rd & 3); |
0f8a249a | 2456 | break; |
1f587329 BS |
2457 | case 0x57: /* fcmpeq, V9 %fcc */ |
2458 | #if defined(CONFIG_USER_ONLY) | |
2459 | gen_op_load_fpr_QT0(QFPREG(rs1)); | |
2460 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2461 | gen_op_fcmpeq(rd & 3); |
1f587329 BS |
2462 | break; |
2463 | #else/* !defined(CONFIG_USER_ONLY) */ | |
0f8a249a | 2464 | goto nfpu_insn; |
1f587329 | 2465 | #endif |
0f8a249a BS |
2466 | default: |
2467 | goto illegal_insn; | |
2468 | } | |
e80cfcfc | 2469 | #if defined(OPTIM) |
0f8a249a BS |
2470 | } else if (xop == 0x2) { |
2471 | // clr/mov shortcut | |
e80cfcfc FB |
2472 | |
2473 | rs1 = GET_FIELD(insn, 13, 17); | |
0f8a249a | 2474 | if (rs1 == 0) { |
1a2fb1c0 | 2475 | // or %g0, x, y -> mov T0, x; mov y, T0 |
0f8a249a BS |
2476 | if (IS_IMM) { /* immediate */ |
2477 | rs2 = GET_FIELDs(insn, 19, 31); | |
1a2fb1c0 | 2478 | tcg_gen_movi_tl(cpu_T[0], (int)rs2); |
0f8a249a BS |
2479 | } else { /* register */ |
2480 | rs2 = GET_FIELD(insn, 27, 31); | |
1a2fb1c0 | 2481 | gen_movl_reg_T0(rs2); |
0f8a249a | 2482 | } |
0f8a249a BS |
2483 | } else { |
2484 | gen_movl_reg_T0(rs1); | |
2485 | if (IS_IMM) { /* immediate */ | |
0f8a249a | 2486 | rs2 = GET_FIELDs(insn, 19, 31); |
1a2fb1c0 | 2487 | tcg_gen_ori_tl(cpu_T[0], cpu_T[0], (int)rs2); |
0f8a249a BS |
2488 | } else { /* register */ |
2489 | // or x, %g0, y -> mov T1, x; mov y, T1 | |
2490 | rs2 = GET_FIELD(insn, 27, 31); | |
2491 | if (rs2 != 0) { | |
2492 | gen_movl_reg_T1(rs2); | |
2493 | gen_op_or_T1_T0(); | |
2494 | } | |
2495 | } | |
0f8a249a | 2496 | } |
1a2fb1c0 | 2497 | gen_movl_T0_reg(rd); |
83469015 FB |
2498 | #endif |
2499 | #ifdef TARGET_SPARC64 | |
0f8a249a | 2500 | } else if (xop == 0x25) { /* sll, V9 sllx */ |
83469015 | 2501 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a BS |
2502 | gen_movl_reg_T0(rs1); |
2503 | if (IS_IMM) { /* immediate */ | |
83469015 | 2504 | rs2 = GET_FIELDs(insn, 20, 31); |
1a2fb1c0 BS |
2505 | if (insn & (1 << 12)) { |
2506 | tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f); | |
2507 | } else { | |
2508 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); | |
2509 | tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f); | |
2510 | } | |
0f8a249a | 2511 | } else { /* register */ |
83469015 FB |
2512 | rs2 = GET_FIELD(insn, 27, 31); |
2513 | gen_movl_reg_T1(rs2); | |
1a2fb1c0 BS |
2514 | if (insn & (1 << 12)) { |
2515 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f); | |
2516 | tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]); | |
2517 | } else { | |
2518 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f); | |
2519 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); | |
2520 | tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]); | |
2521 | } | |
83469015 | 2522 | } |
0f8a249a BS |
2523 | gen_movl_T0_reg(rd); |
2524 | } else if (xop == 0x26) { /* srl, V9 srlx */ | |
83469015 | 2525 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a BS |
2526 | gen_movl_reg_T0(rs1); |
2527 | if (IS_IMM) { /* immediate */ | |
83469015 | 2528 | rs2 = GET_FIELDs(insn, 20, 31); |
1a2fb1c0 BS |
2529 | if (insn & (1 << 12)) { |
2530 | tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f); | |
2531 | } else { | |
2532 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); | |
2533 | tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f); | |
2534 | } | |
0f8a249a | 2535 | } else { /* register */ |
83469015 FB |
2536 | rs2 = GET_FIELD(insn, 27, 31); |
2537 | gen_movl_reg_T1(rs2); | |
1a2fb1c0 BS |
2538 | if (insn & (1 << 12)) { |
2539 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f); | |
2540 | tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]); | |
2541 | } else { | |
2542 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f); | |
2543 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); | |
2544 | tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]); | |
2545 | } | |
83469015 | 2546 | } |
0f8a249a BS |
2547 | gen_movl_T0_reg(rd); |
2548 | } else if (xop == 0x27) { /* sra, V9 srax */ | |
83469015 | 2549 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a BS |
2550 | gen_movl_reg_T0(rs1); |
2551 | if (IS_IMM) { /* immediate */ | |
83469015 | 2552 | rs2 = GET_FIELDs(insn, 20, 31); |
1a2fb1c0 BS |
2553 | if (insn & (1 << 12)) { |
2554 | tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f); | |
2555 | } else { | |
2556 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); | |
2557 | tcg_gen_ext_i32_i64(cpu_T[0], cpu_T[0]); | |
2558 | tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f); | |
2559 | } | |
0f8a249a | 2560 | } else { /* register */ |
83469015 FB |
2561 | rs2 = GET_FIELD(insn, 27, 31); |
2562 | gen_movl_reg_T1(rs2); | |
1a2fb1c0 BS |
2563 | if (insn & (1 << 12)) { |
2564 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f); | |
2565 | tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]); | |
2566 | } else { | |
2567 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f); | |
2568 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); | |
2569 | tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]); | |
2570 | } | |
83469015 | 2571 | } |
0f8a249a | 2572 | gen_movl_T0_reg(rd); |
e80cfcfc | 2573 | #endif |
fcc72045 | 2574 | } else if (xop < 0x36) { |
e80cfcfc | 2575 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a BS |
2576 | gen_movl_reg_T0(rs1); |
2577 | if (IS_IMM) { /* immediate */ | |
cf495bcf | 2578 | rs2 = GET_FIELDs(insn, 19, 31); |
3475187d | 2579 | gen_movl_simm_T1(rs2); |
0f8a249a | 2580 | } else { /* register */ |
cf495bcf FB |
2581 | rs2 = GET_FIELD(insn, 27, 31); |
2582 | gen_movl_reg_T1(rs2); | |
2583 | } | |
2584 | if (xop < 0x20) { | |
2585 | switch (xop & ~0x10) { | |
2586 | case 0x0: | |
2587 | if (xop & 0x10) | |
2588 | gen_op_add_T1_T0_cc(); | |
2589 | else | |
2590 | gen_op_add_T1_T0(); | |
2591 | break; | |
2592 | case 0x1: | |
1a2fb1c0 | 2593 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cf495bcf FB |
2594 | if (xop & 0x10) |
2595 | gen_op_logic_T0_cc(); | |
2596 | break; | |
2597 | case 0x2: | |
1a2fb1c0 | 2598 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
0f8a249a BS |
2599 | if (xop & 0x10) |
2600 | gen_op_logic_T0_cc(); | |
2601 | break; | |
cf495bcf | 2602 | case 0x3: |
1a2fb1c0 | 2603 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cf495bcf FB |
2604 | if (xop & 0x10) |
2605 | gen_op_logic_T0_cc(); | |
2606 | break; | |
2607 | case 0x4: | |
2608 | if (xop & 0x10) | |
2609 | gen_op_sub_T1_T0_cc(); | |
2610 | else | |
1a2fb1c0 | 2611 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cf495bcf FB |
2612 | break; |
2613 | case 0x5: | |
56ec06bb BS |
2614 | tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1); |
2615 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
cf495bcf FB |
2616 | if (xop & 0x10) |
2617 | gen_op_logic_T0_cc(); | |
2618 | break; | |
2619 | case 0x6: | |
56ec06bb BS |
2620 | tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1); |
2621 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
cf495bcf FB |
2622 | if (xop & 0x10) |
2623 | gen_op_logic_T0_cc(); | |
2624 | break; | |
2625 | case 0x7: | |
56ec06bb BS |
2626 | tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1); |
2627 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
cf495bcf FB |
2628 | if (xop & 0x10) |
2629 | gen_op_logic_T0_cc(); | |
2630 | break; | |
2631 | case 0x8: | |
cf495bcf | 2632 | if (xop & 0x10) |
af7bf89b | 2633 | gen_op_addx_T1_T0_cc(); |
38bc628b | 2634 | else { |
19f329ad BS |
2635 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, |
2636 | offsetof(CPUSPARCState, psr)); | |
2637 | gen_mov_reg_C(cpu_tmp0, cpu_tmp0); | |
38bc628b BS |
2638 | tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0); |
2639 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
2640 | } | |
cf495bcf | 2641 | break; |
ded3ab80 | 2642 | #ifdef TARGET_SPARC64 |
0f8a249a | 2643 | case 0x9: /* V9 mulx */ |
1a2fb1c0 | 2644 | tcg_gen_mul_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
ded3ab80 PB |
2645 | break; |
2646 | #endif | |
cf495bcf FB |
2647 | case 0xa: |
2648 | gen_op_umul_T1_T0(); | |
2649 | if (xop & 0x10) | |
2650 | gen_op_logic_T0_cc(); | |
2651 | break; | |
2652 | case 0xb: | |
2653 | gen_op_smul_T1_T0(); | |
2654 | if (xop & 0x10) | |
2655 | gen_op_logic_T0_cc(); | |
2656 | break; | |
2657 | case 0xc: | |
cf495bcf | 2658 | if (xop & 0x10) |
af7bf89b | 2659 | gen_op_subx_T1_T0_cc(); |
38bc628b | 2660 | else { |
19f329ad BS |
2661 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, |
2662 | offsetof(CPUSPARCState, psr)); | |
2663 | gen_mov_reg_C(cpu_tmp0, cpu_tmp0); | |
38bc628b BS |
2664 | tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0); |
2665 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
2666 | } | |
cf495bcf | 2667 | break; |
ded3ab80 | 2668 | #ifdef TARGET_SPARC64 |
0f8a249a | 2669 | case 0xd: /* V9 udivx */ |
ded3ab80 PB |
2670 | gen_op_udivx_T1_T0(); |
2671 | break; | |
2672 | #endif | |
cf495bcf FB |
2673 | case 0xe: |
2674 | gen_op_udiv_T1_T0(); | |
2675 | if (xop & 0x10) | |
2676 | gen_op_div_cc(); | |
2677 | break; | |
2678 | case 0xf: | |
2679 | gen_op_sdiv_T1_T0(); | |
2680 | if (xop & 0x10) | |
2681 | gen_op_div_cc(); | |
2682 | break; | |
2683 | default: | |
2684 | goto illegal_insn; | |
2685 | } | |
0f8a249a | 2686 | gen_movl_T0_reg(rd); |
cf495bcf FB |
2687 | } else { |
2688 | switch (xop) { | |
0f8a249a BS |
2689 | case 0x20: /* taddcc */ |
2690 | gen_op_tadd_T1_T0_cc(); | |
2691 | gen_movl_T0_reg(rd); | |
2692 | break; | |
2693 | case 0x21: /* tsubcc */ | |
2694 | gen_op_tsub_T1_T0_cc(); | |
2695 | gen_movl_T0_reg(rd); | |
2696 | break; | |
2697 | case 0x22: /* taddcctv */ | |
90251fb9 | 2698 | save_state(dc); |
0f8a249a BS |
2699 | gen_op_tadd_T1_T0_ccTV(); |
2700 | gen_movl_T0_reg(rd); | |
2701 | break; | |
2702 | case 0x23: /* tsubcctv */ | |
90251fb9 | 2703 | save_state(dc); |
0f8a249a BS |
2704 | gen_op_tsub_T1_T0_ccTV(); |
2705 | gen_movl_T0_reg(rd); | |
2706 | break; | |
cf495bcf FB |
2707 | case 0x24: /* mulscc */ |
2708 | gen_op_mulscc_T1_T0(); | |
2709 | gen_movl_T0_reg(rd); | |
2710 | break; | |
83469015 | 2711 | #ifndef TARGET_SPARC64 |
0f8a249a | 2712 | case 0x25: /* sll */ |
1a2fb1c0 BS |
2713 | tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f); |
2714 | tcg_gen_shl_i32(cpu_T[0], cpu_T[0], cpu_T[1]); | |
cf495bcf FB |
2715 | gen_movl_T0_reg(rd); |
2716 | break; | |
83469015 | 2717 | case 0x26: /* srl */ |
1a2fb1c0 BS |
2718 | tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f); |
2719 | tcg_gen_shr_i32(cpu_T[0], cpu_T[0], cpu_T[1]); | |
cf495bcf FB |
2720 | gen_movl_T0_reg(rd); |
2721 | break; | |
83469015 | 2722 | case 0x27: /* sra */ |
1a2fb1c0 BS |
2723 | tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f); |
2724 | tcg_gen_sar_i32(cpu_T[0], cpu_T[0], cpu_T[1]); | |
cf495bcf FB |
2725 | gen_movl_T0_reg(rd); |
2726 | break; | |
83469015 | 2727 | #endif |
cf495bcf FB |
2728 | case 0x30: |
2729 | { | |
cf495bcf | 2730 | switch(rd) { |
3475187d | 2731 | case 0: /* wry */ |
0f8a249a BS |
2732 | gen_op_xor_T1_T0(); |
2733 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, y)); | |
cf495bcf | 2734 | break; |
65fe7b09 BS |
2735 | #ifndef TARGET_SPARC64 |
2736 | case 0x01 ... 0x0f: /* undefined in the | |
2737 | SPARCv8 manual, nop | |
2738 | on the microSPARC | |
2739 | II */ | |
2740 | case 0x10 ... 0x1f: /* implementation-dependent | |
2741 | in the SPARCv8 | |
2742 | manual, nop on the | |
2743 | microSPARC II */ | |
2744 | break; | |
2745 | #else | |
0f8a249a | 2746 | case 0x2: /* V9 wrccr */ |
ee0b03fd | 2747 | gen_op_xor_T1_T0(); |
3475187d | 2748 | gen_op_wrccr(); |
0f8a249a BS |
2749 | break; |
2750 | case 0x3: /* V9 wrasi */ | |
ee0b03fd | 2751 | gen_op_xor_T1_T0(); |
0f8a249a BS |
2752 | gen_op_movl_env_T0(offsetof(CPUSPARCState, asi)); |
2753 | break; | |
2754 | case 0x6: /* V9 wrfprs */ | |
2755 | gen_op_xor_T1_T0(); | |
2756 | gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs)); | |
3299908c BS |
2757 | save_state(dc); |
2758 | gen_op_next_insn(); | |
57fec1fe | 2759 | tcg_gen_exit_tb(0); |
3299908c | 2760 | dc->is_br = 1; |
0f8a249a BS |
2761 | break; |
2762 | case 0xf: /* V9 sir, nop if user */ | |
3475187d | 2763 | #if !defined(CONFIG_USER_ONLY) |
0f8a249a | 2764 | if (supervisor(dc)) |
1a2fb1c0 | 2765 | ; // XXX |
3475187d | 2766 | #endif |
0f8a249a BS |
2767 | break; |
2768 | case 0x13: /* Graphics Status */ | |
725cb90b FB |
2769 | if (gen_trap_ifnofpu(dc)) |
2770 | goto jmp_insn; | |
ee0b03fd | 2771 | gen_op_xor_T1_T0(); |
0f8a249a BS |
2772 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr)); |
2773 | break; | |
2774 | case 0x17: /* Tick compare */ | |
83469015 | 2775 | #if !defined(CONFIG_USER_ONLY) |
0f8a249a BS |
2776 | if (!supervisor(dc)) |
2777 | goto illegal_insn; | |
83469015 | 2778 | #endif |
ccd4a219 BS |
2779 | { |
2780 | TCGv r_tickptr; | |
2781 | ||
2782 | gen_op_xor_T1_T0(); | |
2783 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, | |
2784 | tick_cmpr)); | |
2785 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
2786 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
2787 | offsetof(CPUState, tick)); | |
2788 | tcg_gen_helper_0_2(helper_tick_set_limit, | |
2789 | r_tickptr, cpu_T[0]); | |
2790 | } | |
0f8a249a BS |
2791 | break; |
2792 | case 0x18: /* System tick */ | |
83469015 | 2793 | #if !defined(CONFIG_USER_ONLY) |
0f8a249a BS |
2794 | if (!supervisor(dc)) |
2795 | goto illegal_insn; | |
83469015 | 2796 | #endif |
ccd4a219 BS |
2797 | { |
2798 | TCGv r_tickptr; | |
2799 | ||
2800 | gen_op_xor_T1_T0(); | |
2801 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
2802 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
2803 | offsetof(CPUState, stick)); | |
2804 | tcg_gen_helper_0_2(helper_tick_set_count, | |
2805 | r_tickptr, cpu_T[0]); | |
2806 | } | |
0f8a249a BS |
2807 | break; |
2808 | case 0x19: /* System tick compare */ | |
83469015 | 2809 | #if !defined(CONFIG_USER_ONLY) |
0f8a249a BS |
2810 | if (!supervisor(dc)) |
2811 | goto illegal_insn; | |
3475187d | 2812 | #endif |
ccd4a219 BS |
2813 | { |
2814 | TCGv r_tickptr; | |
2815 | ||
2816 | gen_op_xor_T1_T0(); | |
2817 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, | |
2818 | stick_cmpr)); | |
2819 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
2820 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
2821 | offsetof(CPUState, stick)); | |
2822 | tcg_gen_helper_0_2(helper_tick_set_limit, | |
2823 | r_tickptr, cpu_T[0]); | |
2824 | } | |
0f8a249a | 2825 | break; |
83469015 | 2826 | |
0f8a249a BS |
2827 | case 0x10: /* Performance Control */ |
2828 | case 0x11: /* Performance Instrumentation Counter */ | |
2829 | case 0x12: /* Dispatch Control */ | |
2830 | case 0x14: /* Softint set */ | |
2831 | case 0x15: /* Softint clear */ | |
2832 | case 0x16: /* Softint write */ | |
83469015 | 2833 | #endif |
3475187d | 2834 | default: |
cf495bcf FB |
2835 | goto illegal_insn; |
2836 | } | |
2837 | } | |
2838 | break; | |
e8af50a3 | 2839 | #if !defined(CONFIG_USER_ONLY) |
af7bf89b | 2840 | case 0x31: /* wrpsr, V9 saved, restored */ |
e8af50a3 | 2841 | { |
0f8a249a BS |
2842 | if (!supervisor(dc)) |
2843 | goto priv_insn; | |
3475187d | 2844 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
2845 | switch (rd) { |
2846 | case 0: | |
2847 | gen_op_saved(); | |
2848 | break; | |
2849 | case 1: | |
2850 | gen_op_restored(); | |
2851 | break; | |
e9ebed4d BS |
2852 | case 2: /* UA2005 allclean */ |
2853 | case 3: /* UA2005 otherw */ | |
2854 | case 4: /* UA2005 normalw */ | |
2855 | case 5: /* UA2005 invalw */ | |
2856 | // XXX | |
0f8a249a | 2857 | default: |
3475187d FB |
2858 | goto illegal_insn; |
2859 | } | |
2860 | #else | |
e8af50a3 | 2861 | gen_op_xor_T1_T0(); |
1a2fb1c0 | 2862 | tcg_gen_helper_0_1(helper_wrpsr, cpu_T[0]); |
9e61bde5 FB |
2863 | save_state(dc); |
2864 | gen_op_next_insn(); | |
57fec1fe | 2865 | tcg_gen_exit_tb(0); |
0f8a249a | 2866 | dc->is_br = 1; |
3475187d | 2867 | #endif |
e8af50a3 FB |
2868 | } |
2869 | break; | |
af7bf89b | 2870 | case 0x32: /* wrwim, V9 wrpr */ |
e8af50a3 | 2871 | { |
0f8a249a BS |
2872 | if (!supervisor(dc)) |
2873 | goto priv_insn; | |
e8af50a3 | 2874 | gen_op_xor_T1_T0(); |
3475187d | 2875 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
2876 | switch (rd) { |
2877 | case 0: // tpc | |
375ee38b BS |
2878 | { |
2879 | TCGv r_tsptr; | |
2880 | ||
2881 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
2882 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
2883 | offsetof(CPUState, tsptr)); | |
2884 | tcg_gen_st_tl(cpu_T[0], r_tsptr, | |
2885 | offsetof(trap_state, tpc)); | |
2886 | } | |
0f8a249a BS |
2887 | break; |
2888 | case 1: // tnpc | |
375ee38b BS |
2889 | { |
2890 | TCGv r_tsptr; | |
2891 | ||
2892 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
2893 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
2894 | offsetof(CPUState, tsptr)); | |
2895 | tcg_gen_st_tl(cpu_T[0], r_tsptr, | |
2896 | offsetof(trap_state, tnpc)); | |
2897 | } | |
0f8a249a BS |
2898 | break; |
2899 | case 2: // tstate | |
375ee38b BS |
2900 | { |
2901 | TCGv r_tsptr; | |
2902 | ||
2903 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
2904 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
2905 | offsetof(CPUState, tsptr)); | |
2906 | tcg_gen_st_tl(cpu_T[0], r_tsptr, | |
2907 | offsetof(trap_state, tstate)); | |
2908 | } | |
0f8a249a BS |
2909 | break; |
2910 | case 3: // tt | |
375ee38b BS |
2911 | { |
2912 | TCGv r_tsptr; | |
2913 | ||
2914 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
2915 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
2916 | offsetof(CPUState, tsptr)); | |
2917 | tcg_gen_st_i32(cpu_T[0], r_tsptr, | |
2918 | offsetof(trap_state, tt)); | |
2919 | } | |
0f8a249a BS |
2920 | break; |
2921 | case 4: // tick | |
ccd4a219 BS |
2922 | { |
2923 | TCGv r_tickptr; | |
2924 | ||
2925 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
2926 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
2927 | offsetof(CPUState, tick)); | |
2928 | tcg_gen_helper_0_2(helper_tick_set_count, | |
2929 | r_tickptr, cpu_T[0]); | |
2930 | } | |
0f8a249a BS |
2931 | break; |
2932 | case 5: // tba | |
2933 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); | |
2934 | break; | |
2935 | case 6: // pstate | |
ded3ab80 | 2936 | save_state(dc); |
1a2fb1c0 | 2937 | tcg_gen_helper_0_1(helper_wrpstate, cpu_T[0]); |
ded3ab80 | 2938 | gen_op_next_insn(); |
57fec1fe | 2939 | tcg_gen_exit_tb(0); |
ded3ab80 | 2940 | dc->is_br = 1; |
0f8a249a BS |
2941 | break; |
2942 | case 7: // tl | |
2943 | gen_op_movl_env_T0(offsetof(CPUSPARCState, tl)); | |
2944 | break; | |
2945 | case 8: // pil | |
2946 | gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil)); | |
2947 | break; | |
2948 | case 9: // cwp | |
2949 | gen_op_wrcwp(); | |
2950 | break; | |
2951 | case 10: // cansave | |
2952 | gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave)); | |
2953 | break; | |
2954 | case 11: // canrestore | |
2955 | gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore)); | |
2956 | break; | |
2957 | case 12: // cleanwin | |
2958 | gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin)); | |
2959 | break; | |
2960 | case 13: // otherwin | |
2961 | gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin)); | |
2962 | break; | |
2963 | case 14: // wstate | |
2964 | gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate)); | |
2965 | break; | |
e9ebed4d BS |
2966 | case 16: // UA2005 gl |
2967 | gen_op_movl_env_T0(offsetof(CPUSPARCState, gl)); | |
2968 | break; | |
2969 | case 26: // UA2005 strand status | |
2970 | if (!hypervisor(dc)) | |
2971 | goto priv_insn; | |
2972 | gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr)); | |
2973 | break; | |
0f8a249a BS |
2974 | default: |
2975 | goto illegal_insn; | |
2976 | } | |
3475187d | 2977 | #else |
1a2fb1c0 BS |
2978 | tcg_gen_andi_i32(cpu_T[0], cpu_T[0], ((1 << NWINDOWS) - 1)); |
2979 | gen_op_movl_env_T0(offsetof(CPUSPARCState, wim)); | |
3475187d | 2980 | #endif |
e8af50a3 FB |
2981 | } |
2982 | break; | |
e9ebed4d | 2983 | case 0x33: /* wrtbr, UA2005 wrhpr */ |
e8af50a3 | 2984 | { |
e9ebed4d | 2985 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
2986 | if (!supervisor(dc)) |
2987 | goto priv_insn; | |
e8af50a3 | 2988 | gen_op_xor_T1_T0(); |
e9ebed4d BS |
2989 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); |
2990 | #else | |
2991 | if (!hypervisor(dc)) | |
2992 | goto priv_insn; | |
2993 | gen_op_xor_T1_T0(); | |
2994 | switch (rd) { | |
2995 | case 0: // hpstate | |
2996 | // XXX gen_op_wrhpstate(); | |
2997 | save_state(dc); | |
2998 | gen_op_next_insn(); | |
57fec1fe | 2999 | tcg_gen_exit_tb(0); |
e9ebed4d BS |
3000 | dc->is_br = 1; |
3001 | break; | |
3002 | case 1: // htstate | |
3003 | // XXX gen_op_wrhtstate(); | |
3004 | break; | |
3005 | case 3: // hintp | |
3006 | gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp)); | |
3007 | break; | |
3008 | case 5: // htba | |
3009 | gen_op_movl_env_T0(offsetof(CPUSPARCState, htba)); | |
3010 | break; | |
3011 | case 31: // hstick_cmpr | |
ccd4a219 BS |
3012 | { |
3013 | TCGv r_tickptr; | |
3014 | ||
3015 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, | |
3016 | hstick_cmpr)); | |
3017 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
3018 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
3019 | offsetof(CPUState, hstick)); | |
3020 | tcg_gen_helper_0_2(helper_tick_set_limit, | |
3021 | r_tickptr, cpu_T[0]); | |
3022 | } | |
e9ebed4d BS |
3023 | break; |
3024 | case 6: // hver readonly | |
3025 | default: | |
3026 | goto illegal_insn; | |
3027 | } | |
3028 | #endif | |
e8af50a3 FB |
3029 | } |
3030 | break; | |
3031 | #endif | |
3475187d | 3032 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
3033 | case 0x2c: /* V9 movcc */ |
3034 | { | |
3035 | int cc = GET_FIELD_SP(insn, 11, 12); | |
3036 | int cond = GET_FIELD_SP(insn, 14, 17); | |
00f219bf BS |
3037 | TCGv r_zero; |
3038 | int l1; | |
3039 | ||
0f8a249a BS |
3040 | flush_T2(dc); |
3041 | if (insn & (1 << 18)) { | |
3042 | if (cc == 0) | |
19f329ad | 3043 | gen_cond(cpu_T[2], 0, cond); |
0f8a249a | 3044 | else if (cc == 2) |
19f329ad | 3045 | gen_cond(cpu_T[2], 1, cond); |
0f8a249a BS |
3046 | else |
3047 | goto illegal_insn; | |
3048 | } else { | |
19f329ad | 3049 | gen_fcond(cpu_T[2], cc, cond); |
0f8a249a | 3050 | } |
00f219bf BS |
3051 | |
3052 | l1 = gen_new_label(); | |
3053 | ||
3054 | r_zero = tcg_temp_new(TCG_TYPE_TL); | |
3055 | tcg_gen_movi_tl(r_zero, 0); | |
3056 | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[2], r_zero, l1); | |
3057 | if (IS_IMM) { /* immediate */ | |
3058 | rs2 = GET_FIELD_SPs(insn, 0, 10); | |
3059 | gen_movl_simm_T1(rs2); | |
3060 | } else { | |
3061 | rs2 = GET_FIELD_SP(insn, 0, 4); | |
3062 | gen_movl_reg_T1(rs2); | |
3063 | } | |
3064 | gen_movl_T1_reg(rd); | |
3065 | gen_set_label(l1); | |
0f8a249a BS |
3066 | break; |
3067 | } | |
3068 | case 0x2d: /* V9 sdivx */ | |
3475187d | 3069 | gen_op_sdivx_T1_T0(); |
0f8a249a BS |
3070 | gen_movl_T0_reg(rd); |
3071 | break; | |
3072 | case 0x2e: /* V9 popc */ | |
3073 | { | |
3074 | if (IS_IMM) { /* immediate */ | |
3075 | rs2 = GET_FIELD_SPs(insn, 0, 12); | |
3076 | gen_movl_simm_T1(rs2); | |
3077 | // XXX optimize: popc(constant) | |
3078 | } | |
3079 | else { | |
3080 | rs2 = GET_FIELD_SP(insn, 0, 4); | |
3081 | gen_movl_reg_T1(rs2); | |
3082 | } | |
1a2fb1c0 BS |
3083 | tcg_gen_helper_1_1(helper_popc, cpu_T[0], |
3084 | cpu_T[1]); | |
0f8a249a BS |
3085 | gen_movl_T0_reg(rd); |
3086 | } | |
3087 | case 0x2f: /* V9 movr */ | |
3088 | { | |
3089 | int cond = GET_FIELD_SP(insn, 10, 12); | |
00f219bf BS |
3090 | TCGv r_zero; |
3091 | int l1; | |
3092 | ||
0f8a249a | 3093 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a | 3094 | gen_movl_reg_T0(rs1); |
00f219bf BS |
3095 | |
3096 | l1 = gen_new_label(); | |
3097 | ||
3098 | r_zero = tcg_temp_new(TCG_TYPE_TL); | |
3099 | tcg_gen_movi_tl(r_zero, 0); | |
3100 | tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1); | |
0f8a249a BS |
3101 | if (IS_IMM) { /* immediate */ |
3102 | rs2 = GET_FIELD_SPs(insn, 0, 9); | |
3103 | gen_movl_simm_T1(rs2); | |
00f219bf | 3104 | } else { |
0f8a249a BS |
3105 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3106 | gen_movl_reg_T1(rs2); | |
3107 | } | |
00f219bf BS |
3108 | gen_movl_T1_reg(rd); |
3109 | gen_set_label(l1); | |
0f8a249a BS |
3110 | break; |
3111 | } | |
3112 | #endif | |
3113 | default: | |
3114 | goto illegal_insn; | |
3115 | } | |
3116 | } | |
3299908c BS |
3117 | } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ |
3118 | #ifdef TARGET_SPARC64 | |
3119 | int opf = GET_FIELD_SP(insn, 5, 13); | |
3120 | rs1 = GET_FIELD(insn, 13, 17); | |
3121 | rs2 = GET_FIELD(insn, 27, 31); | |
e9ebed4d BS |
3122 | if (gen_trap_ifnofpu(dc)) |
3123 | goto jmp_insn; | |
3299908c BS |
3124 | |
3125 | switch (opf) { | |
e9ebed4d BS |
3126 | case 0x000: /* VIS I edge8cc */ |
3127 | case 0x001: /* VIS II edge8n */ | |
3128 | case 0x002: /* VIS I edge8lcc */ | |
3129 | case 0x003: /* VIS II edge8ln */ | |
3130 | case 0x004: /* VIS I edge16cc */ | |
3131 | case 0x005: /* VIS II edge16n */ | |
3132 | case 0x006: /* VIS I edge16lcc */ | |
3133 | case 0x007: /* VIS II edge16ln */ | |
3134 | case 0x008: /* VIS I edge32cc */ | |
3135 | case 0x009: /* VIS II edge32n */ | |
3136 | case 0x00a: /* VIS I edge32lcc */ | |
3137 | case 0x00b: /* VIS II edge32ln */ | |
3138 | // XXX | |
3139 | goto illegal_insn; | |
3140 | case 0x010: /* VIS I array8 */ | |
3141 | gen_movl_reg_T0(rs1); | |
3142 | gen_movl_reg_T1(rs2); | |
3143 | gen_op_array8(); | |
3144 | gen_movl_T0_reg(rd); | |
3145 | break; | |
3146 | case 0x012: /* VIS I array16 */ | |
3147 | gen_movl_reg_T0(rs1); | |
3148 | gen_movl_reg_T1(rs2); | |
3149 | gen_op_array16(); | |
3150 | gen_movl_T0_reg(rd); | |
3151 | break; | |
3152 | case 0x014: /* VIS I array32 */ | |
3153 | gen_movl_reg_T0(rs1); | |
3154 | gen_movl_reg_T1(rs2); | |
3155 | gen_op_array32(); | |
3156 | gen_movl_T0_reg(rd); | |
3157 | break; | |
3299908c | 3158 | case 0x018: /* VIS I alignaddr */ |
3299908c BS |
3159 | gen_movl_reg_T0(rs1); |
3160 | gen_movl_reg_T1(rs2); | |
3161 | gen_op_alignaddr(); | |
3162 | gen_movl_T0_reg(rd); | |
3163 | break; | |
e9ebed4d | 3164 | case 0x019: /* VIS II bmask */ |
3299908c | 3165 | case 0x01a: /* VIS I alignaddrl */ |
3299908c | 3166 | // XXX |
e9ebed4d BS |
3167 | goto illegal_insn; |
3168 | case 0x020: /* VIS I fcmple16 */ | |
2382dc6b BS |
3169 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3170 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3171 | gen_op_fcmple16(); |
2382dc6b | 3172 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3173 | break; |
3174 | case 0x022: /* VIS I fcmpne16 */ | |
2382dc6b BS |
3175 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3176 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3177 | gen_op_fcmpne16(); |
2382dc6b | 3178 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3299908c | 3179 | break; |
e9ebed4d | 3180 | case 0x024: /* VIS I fcmple32 */ |
2382dc6b BS |
3181 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3182 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3183 | gen_op_fcmple32(); |
2382dc6b | 3184 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3185 | break; |
3186 | case 0x026: /* VIS I fcmpne32 */ | |
2382dc6b BS |
3187 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3188 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3189 | gen_op_fcmpne32(); |
2382dc6b | 3190 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3191 | break; |
3192 | case 0x028: /* VIS I fcmpgt16 */ | |
2382dc6b BS |
3193 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3194 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3195 | gen_op_fcmpgt16(); |
2382dc6b | 3196 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3197 | break; |
3198 | case 0x02a: /* VIS I fcmpeq16 */ | |
2382dc6b BS |
3199 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3200 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3201 | gen_op_fcmpeq16(); |
2382dc6b | 3202 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3203 | break; |
3204 | case 0x02c: /* VIS I fcmpgt32 */ | |
2382dc6b BS |
3205 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3206 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3207 | gen_op_fcmpgt32(); |
2382dc6b | 3208 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3209 | break; |
3210 | case 0x02e: /* VIS I fcmpeq32 */ | |
2382dc6b BS |
3211 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3212 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3213 | gen_op_fcmpeq32(); |
2382dc6b | 3214 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3215 | break; |
3216 | case 0x031: /* VIS I fmul8x16 */ | |
2382dc6b BS |
3217 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3218 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3219 | gen_op_fmul8x16(); |
2382dc6b | 3220 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3221 | break; |
3222 | case 0x033: /* VIS I fmul8x16au */ | |
2382dc6b BS |
3223 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3224 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3225 | gen_op_fmul8x16au(); |
2382dc6b | 3226 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3227 | break; |
3228 | case 0x035: /* VIS I fmul8x16al */ | |
2382dc6b BS |
3229 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3230 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3231 | gen_op_fmul8x16al(); |
2382dc6b | 3232 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3233 | break; |
3234 | case 0x036: /* VIS I fmul8sux16 */ | |
2382dc6b BS |
3235 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3236 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3237 | gen_op_fmul8sux16(); |
2382dc6b | 3238 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3239 | break; |
3240 | case 0x037: /* VIS I fmul8ulx16 */ | |
2382dc6b BS |
3241 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3242 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3243 | gen_op_fmul8ulx16(); |
2382dc6b | 3244 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3245 | break; |
3246 | case 0x038: /* VIS I fmuld8sux16 */ | |
2382dc6b BS |
3247 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3248 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3249 | gen_op_fmuld8sux16(); |
2382dc6b | 3250 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3251 | break; |
3252 | case 0x039: /* VIS I fmuld8ulx16 */ | |
2382dc6b BS |
3253 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3254 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3255 | gen_op_fmuld8ulx16(); |
2382dc6b | 3256 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3257 | break; |
3258 | case 0x03a: /* VIS I fpack32 */ | |
3259 | case 0x03b: /* VIS I fpack16 */ | |
3260 | case 0x03d: /* VIS I fpackfix */ | |
3261 | case 0x03e: /* VIS I pdist */ | |
3262 | // XXX | |
3263 | goto illegal_insn; | |
3299908c | 3264 | case 0x048: /* VIS I faligndata */ |
2382dc6b BS |
3265 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3266 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
3299908c | 3267 | gen_op_faligndata(); |
2382dc6b | 3268 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3299908c | 3269 | break; |
e9ebed4d | 3270 | case 0x04b: /* VIS I fpmerge */ |
2382dc6b BS |
3271 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3272 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3273 | gen_op_fpmerge(); |
2382dc6b | 3274 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3275 | break; |
3276 | case 0x04c: /* VIS II bshuffle */ | |
3277 | // XXX | |
3278 | goto illegal_insn; | |
3279 | case 0x04d: /* VIS I fexpand */ | |
2382dc6b BS |
3280 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3281 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3282 | gen_op_fexpand(); |
2382dc6b | 3283 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3284 | break; |
3285 | case 0x050: /* VIS I fpadd16 */ | |
2382dc6b BS |
3286 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3287 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3288 | gen_op_fpadd16(); |
2382dc6b | 3289 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3290 | break; |
3291 | case 0x051: /* VIS I fpadd16s */ | |
3292 | gen_op_load_fpr_FT0(rs1); | |
3293 | gen_op_load_fpr_FT1(rs2); | |
3294 | gen_op_fpadd16s(); | |
3295 | gen_op_store_FT0_fpr(rd); | |
3296 | break; | |
3297 | case 0x052: /* VIS I fpadd32 */ | |
2382dc6b BS |
3298 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3299 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3300 | gen_op_fpadd32(); |
2382dc6b | 3301 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3302 | break; |
3303 | case 0x053: /* VIS I fpadd32s */ | |
3304 | gen_op_load_fpr_FT0(rs1); | |
3305 | gen_op_load_fpr_FT1(rs2); | |
3306 | gen_op_fpadd32s(); | |
3307 | gen_op_store_FT0_fpr(rd); | |
3308 | break; | |
3309 | case 0x054: /* VIS I fpsub16 */ | |
2382dc6b BS |
3310 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3311 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3312 | gen_op_fpsub16(); |
2382dc6b | 3313 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3314 | break; |
3315 | case 0x055: /* VIS I fpsub16s */ | |
3316 | gen_op_load_fpr_FT0(rs1); | |
3317 | gen_op_load_fpr_FT1(rs2); | |
3318 | gen_op_fpsub16s(); | |
3319 | gen_op_store_FT0_fpr(rd); | |
3320 | break; | |
3321 | case 0x056: /* VIS I fpsub32 */ | |
2382dc6b BS |
3322 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3323 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3324 | gen_op_fpadd32(); |
2382dc6b | 3325 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3326 | break; |
3327 | case 0x057: /* VIS I fpsub32s */ | |
3328 | gen_op_load_fpr_FT0(rs1); | |
3329 | gen_op_load_fpr_FT1(rs2); | |
3330 | gen_op_fpsub32s(); | |
3331 | gen_op_store_FT0_fpr(rd); | |
3332 | break; | |
3299908c | 3333 | case 0x060: /* VIS I fzero */ |
3299908c | 3334 | gen_op_movl_DT0_0(); |
2382dc6b | 3335 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3299908c BS |
3336 | break; |
3337 | case 0x061: /* VIS I fzeros */ | |
3299908c BS |
3338 | gen_op_movl_FT0_0(); |
3339 | gen_op_store_FT0_fpr(rd); | |
3340 | break; | |
e9ebed4d | 3341 | case 0x062: /* VIS I fnor */ |
2382dc6b BS |
3342 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3343 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3344 | gen_op_fnor(); |
2382dc6b | 3345 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3346 | break; |
3347 | case 0x063: /* VIS I fnors */ | |
3348 | gen_op_load_fpr_FT0(rs1); | |
3349 | gen_op_load_fpr_FT1(rs2); | |
3350 | gen_op_fnors(); | |
3351 | gen_op_store_FT0_fpr(rd); | |
3352 | break; | |
3353 | case 0x064: /* VIS I fandnot2 */ | |
2382dc6b BS |
3354 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
3355 | gen_op_load_fpr_DT0(DFPREG(rs2)); | |
e9ebed4d | 3356 | gen_op_fandnot(); |
2382dc6b | 3357 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3358 | break; |
3359 | case 0x065: /* VIS I fandnot2s */ | |
3360 | gen_op_load_fpr_FT1(rs1); | |
3361 | gen_op_load_fpr_FT0(rs2); | |
3362 | gen_op_fandnots(); | |
3363 | gen_op_store_FT0_fpr(rd); | |
3364 | break; | |
3365 | case 0x066: /* VIS I fnot2 */ | |
2382dc6b | 3366 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
e9ebed4d | 3367 | gen_op_fnot(); |
2382dc6b | 3368 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3369 | break; |
3370 | case 0x067: /* VIS I fnot2s */ | |
3371 | gen_op_load_fpr_FT1(rs2); | |
3372 | gen_op_fnot(); | |
3373 | gen_op_store_FT0_fpr(rd); | |
3374 | break; | |
3375 | case 0x068: /* VIS I fandnot1 */ | |
2382dc6b BS |
3376 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3377 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3378 | gen_op_fandnot(); |
2382dc6b | 3379 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3380 | break; |
3381 | case 0x069: /* VIS I fandnot1s */ | |
3382 | gen_op_load_fpr_FT0(rs1); | |
3383 | gen_op_load_fpr_FT1(rs2); | |
3384 | gen_op_fandnots(); | |
3385 | gen_op_store_FT0_fpr(rd); | |
3386 | break; | |
3387 | case 0x06a: /* VIS I fnot1 */ | |
2382dc6b | 3388 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
e9ebed4d | 3389 | gen_op_fnot(); |
2382dc6b | 3390 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3391 | break; |
3392 | case 0x06b: /* VIS I fnot1s */ | |
3393 | gen_op_load_fpr_FT1(rs1); | |
3394 | gen_op_fnot(); | |
3395 | gen_op_store_FT0_fpr(rd); | |
3396 | break; | |
3397 | case 0x06c: /* VIS I fxor */ | |
2382dc6b BS |
3398 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3399 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3400 | gen_op_fxor(); |
2382dc6b | 3401 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3402 | break; |
3403 | case 0x06d: /* VIS I fxors */ | |
3404 | gen_op_load_fpr_FT0(rs1); | |
3405 | gen_op_load_fpr_FT1(rs2); | |
3406 | gen_op_fxors(); | |
3407 | gen_op_store_FT0_fpr(rd); | |
3408 | break; | |
3409 | case 0x06e: /* VIS I fnand */ | |
2382dc6b BS |
3410 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3411 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3412 | gen_op_fnand(); |
2382dc6b | 3413 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3414 | break; |
3415 | case 0x06f: /* VIS I fnands */ | |
3416 | gen_op_load_fpr_FT0(rs1); | |
3417 | gen_op_load_fpr_FT1(rs2); | |
3418 | gen_op_fnands(); | |
3419 | gen_op_store_FT0_fpr(rd); | |
3420 | break; | |
3421 | case 0x070: /* VIS I fand */ | |
2382dc6b BS |
3422 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3423 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3424 | gen_op_fand(); |
2382dc6b | 3425 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3426 | break; |
3427 | case 0x071: /* VIS I fands */ | |
3428 | gen_op_load_fpr_FT0(rs1); | |
3429 | gen_op_load_fpr_FT1(rs2); | |
3430 | gen_op_fands(); | |
3431 | gen_op_store_FT0_fpr(rd); | |
3432 | break; | |
3433 | case 0x072: /* VIS I fxnor */ | |
2382dc6b BS |
3434 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3435 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3436 | gen_op_fxnor(); |
2382dc6b | 3437 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3438 | break; |
3439 | case 0x073: /* VIS I fxnors */ | |
3440 | gen_op_load_fpr_FT0(rs1); | |
3441 | gen_op_load_fpr_FT1(rs2); | |
3442 | gen_op_fxnors(); | |
3443 | gen_op_store_FT0_fpr(rd); | |
3444 | break; | |
3299908c | 3445 | case 0x074: /* VIS I fsrc1 */ |
2382dc6b BS |
3446 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3447 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
3299908c BS |
3448 | break; |
3449 | case 0x075: /* VIS I fsrc1s */ | |
3299908c BS |
3450 | gen_op_load_fpr_FT0(rs1); |
3451 | gen_op_store_FT0_fpr(rd); | |
3452 | break; | |
e9ebed4d | 3453 | case 0x076: /* VIS I fornot2 */ |
2382dc6b BS |
3454 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
3455 | gen_op_load_fpr_DT0(DFPREG(rs2)); | |
e9ebed4d | 3456 | gen_op_fornot(); |
2382dc6b | 3457 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3458 | break; |
3459 | case 0x077: /* VIS I fornot2s */ | |
3460 | gen_op_load_fpr_FT1(rs1); | |
3461 | gen_op_load_fpr_FT0(rs2); | |
3462 | gen_op_fornots(); | |
3463 | gen_op_store_FT0_fpr(rd); | |
3464 | break; | |
3299908c | 3465 | case 0x078: /* VIS I fsrc2 */ |
2382dc6b BS |
3466 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
3467 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
3299908c BS |
3468 | break; |
3469 | case 0x079: /* VIS I fsrc2s */ | |
3299908c BS |
3470 | gen_op_load_fpr_FT0(rs2); |
3471 | gen_op_store_FT0_fpr(rd); | |
3472 | break; | |
e9ebed4d | 3473 | case 0x07a: /* VIS I fornot1 */ |
2382dc6b BS |
3474 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3475 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3476 | gen_op_fornot(); |
2382dc6b | 3477 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3478 | break; |
3479 | case 0x07b: /* VIS I fornot1s */ | |
3480 | gen_op_load_fpr_FT0(rs1); | |
3481 | gen_op_load_fpr_FT1(rs2); | |
3482 | gen_op_fornots(); | |
3483 | gen_op_store_FT0_fpr(rd); | |
3484 | break; | |
3485 | case 0x07c: /* VIS I for */ | |
2382dc6b BS |
3486 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3487 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
e9ebed4d | 3488 | gen_op_for(); |
2382dc6b | 3489 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3490 | break; |
3491 | case 0x07d: /* VIS I fors */ | |
3492 | gen_op_load_fpr_FT0(rs1); | |
3493 | gen_op_load_fpr_FT1(rs2); | |
3494 | gen_op_fors(); | |
3495 | gen_op_store_FT0_fpr(rd); | |
3496 | break; | |
3299908c | 3497 | case 0x07e: /* VIS I fone */ |
3299908c | 3498 | gen_op_movl_DT0_1(); |
2382dc6b | 3499 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3299908c BS |
3500 | break; |
3501 | case 0x07f: /* VIS I fones */ | |
3299908c BS |
3502 | gen_op_movl_FT0_1(); |
3503 | gen_op_store_FT0_fpr(rd); | |
3504 | break; | |
e9ebed4d BS |
3505 | case 0x080: /* VIS I shutdown */ |
3506 | case 0x081: /* VIS II siam */ | |
3507 | // XXX | |
3508 | goto illegal_insn; | |
3299908c BS |
3509 | default: |
3510 | goto illegal_insn; | |
3511 | } | |
3512 | #else | |
0f8a249a | 3513 | goto ncp_insn; |
3299908c BS |
3514 | #endif |
3515 | } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ | |
fcc72045 | 3516 | #ifdef TARGET_SPARC64 |
0f8a249a | 3517 | goto illegal_insn; |
fcc72045 | 3518 | #else |
0f8a249a | 3519 | goto ncp_insn; |
fcc72045 | 3520 | #endif |
3475187d | 3521 | #ifdef TARGET_SPARC64 |
0f8a249a | 3522 | } else if (xop == 0x39) { /* V9 return */ |
3475187d | 3523 | rs1 = GET_FIELD(insn, 13, 17); |
1ad21e69 | 3524 | save_state(dc); |
0f8a249a BS |
3525 | gen_movl_reg_T0(rs1); |
3526 | if (IS_IMM) { /* immediate */ | |
3527 | rs2 = GET_FIELDs(insn, 19, 31); | |
1a2fb1c0 | 3528 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2); |
0f8a249a | 3529 | } else { /* register */ |
3475187d FB |
3530 | rs2 = GET_FIELD(insn, 27, 31); |
3531 | #if defined(OPTIM) | |
0f8a249a | 3532 | if (rs2) { |
3475187d | 3533 | #endif |
0f8a249a BS |
3534 | gen_movl_reg_T1(rs2); |
3535 | gen_op_add_T1_T0(); | |
3475187d | 3536 | #if defined(OPTIM) |
0f8a249a | 3537 | } |
3475187d FB |
3538 | #endif |
3539 | } | |
0f8a249a BS |
3540 | gen_op_restore(); |
3541 | gen_mov_pc_npc(dc); | |
6ea4a6c8 | 3542 | gen_op_check_align_T0_3(); |
1a2fb1c0 | 3543 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc)); |
0f8a249a BS |
3544 | dc->npc = DYNAMIC_PC; |
3545 | goto jmp_insn; | |
3475187d | 3546 | #endif |
0f8a249a | 3547 | } else { |
e80cfcfc | 3548 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a BS |
3549 | gen_movl_reg_T0(rs1); |
3550 | if (IS_IMM) { /* immediate */ | |
3551 | rs2 = GET_FIELDs(insn, 19, 31); | |
1a2fb1c0 | 3552 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2); |
0f8a249a | 3553 | } else { /* register */ |
e80cfcfc FB |
3554 | rs2 = GET_FIELD(insn, 27, 31); |
3555 | #if defined(OPTIM) | |
0f8a249a | 3556 | if (rs2) { |
e80cfcfc | 3557 | #endif |
0f8a249a BS |
3558 | gen_movl_reg_T1(rs2); |
3559 | gen_op_add_T1_T0(); | |
e80cfcfc | 3560 | #if defined(OPTIM) |
0f8a249a | 3561 | } |
e8af50a3 | 3562 | #endif |
cf495bcf | 3563 | } |
0f8a249a BS |
3564 | switch (xop) { |
3565 | case 0x38: /* jmpl */ | |
3566 | { | |
3567 | if (rd != 0) { | |
1a2fb1c0 | 3568 | tcg_gen_movi_tl(cpu_T[1], dc->pc); |
0f8a249a BS |
3569 | gen_movl_T1_reg(rd); |
3570 | } | |
0bee699e | 3571 | gen_mov_pc_npc(dc); |
6ea4a6c8 | 3572 | gen_op_check_align_T0_3(); |
1a2fb1c0 | 3573 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc)); |
0f8a249a BS |
3574 | dc->npc = DYNAMIC_PC; |
3575 | } | |
3576 | goto jmp_insn; | |
3475187d | 3577 | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) |
0f8a249a BS |
3578 | case 0x39: /* rett, V9 return */ |
3579 | { | |
3580 | if (!supervisor(dc)) | |
3581 | goto priv_insn; | |
0bee699e | 3582 | gen_mov_pc_npc(dc); |
6ea4a6c8 | 3583 | gen_op_check_align_T0_3(); |
1a2fb1c0 | 3584 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc)); |
0f8a249a | 3585 | dc->npc = DYNAMIC_PC; |
1a2fb1c0 | 3586 | tcg_gen_helper_0_0(helper_rett); |
0f8a249a BS |
3587 | } |
3588 | goto jmp_insn; | |
3589 | #endif | |
3590 | case 0x3b: /* flush */ | |
1a2fb1c0 | 3591 | tcg_gen_helper_0_1(helper_flush, cpu_T[0]); |
0f8a249a BS |
3592 | break; |
3593 | case 0x3c: /* save */ | |
3594 | save_state(dc); | |
3595 | gen_op_save(); | |
3596 | gen_movl_T0_reg(rd); | |
3597 | break; | |
3598 | case 0x3d: /* restore */ | |
3599 | save_state(dc); | |
3600 | gen_op_restore(); | |
3601 | gen_movl_T0_reg(rd); | |
3602 | break; | |
3475187d | 3603 | #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64) |
0f8a249a BS |
3604 | case 0x3e: /* V9 done/retry */ |
3605 | { | |
3606 | switch (rd) { | |
3607 | case 0: | |
3608 | if (!supervisor(dc)) | |
3609 | goto priv_insn; | |
3610 | dc->npc = DYNAMIC_PC; | |
3611 | dc->pc = DYNAMIC_PC; | |
1a2fb1c0 | 3612 | tcg_gen_helper_0_0(helper_done); |
0f8a249a BS |
3613 | goto jmp_insn; |
3614 | case 1: | |
3615 | if (!supervisor(dc)) | |
3616 | goto priv_insn; | |
3617 | dc->npc = DYNAMIC_PC; | |
3618 | dc->pc = DYNAMIC_PC; | |
1a2fb1c0 | 3619 | tcg_gen_helper_0_0(helper_retry); |
0f8a249a BS |
3620 | goto jmp_insn; |
3621 | default: | |
3622 | goto illegal_insn; | |
3623 | } | |
3624 | } | |
3625 | break; | |
3626 | #endif | |
3627 | default: | |
3628 | goto illegal_insn; | |
3629 | } | |
cf495bcf | 3630 | } |
0f8a249a BS |
3631 | break; |
3632 | } | |
3633 | break; | |
3634 | case 3: /* load/store instructions */ | |
3635 | { | |
3636 | unsigned int xop = GET_FIELD(insn, 7, 12); | |
3637 | rs1 = GET_FIELD(insn, 13, 17); | |
2371aaa2 | 3638 | save_state(dc); |
0f8a249a | 3639 | gen_movl_reg_T0(rs1); |
81ad8ba2 BS |
3640 | if (xop == 0x3c || xop == 0x3e) |
3641 | { | |
3642 | rs2 = GET_FIELD(insn, 27, 31); | |
3643 | gen_movl_reg_T1(rs2); | |
3644 | } | |
3645 | else if (IS_IMM) { /* immediate */ | |
0f8a249a | 3646 | rs2 = GET_FIELDs(insn, 19, 31); |
1a2fb1c0 | 3647 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2); |
0f8a249a BS |
3648 | } else { /* register */ |
3649 | rs2 = GET_FIELD(insn, 27, 31); | |
e80cfcfc | 3650 | #if defined(OPTIM) |
0f8a249a | 3651 | if (rs2 != 0) { |
e80cfcfc | 3652 | #endif |
0f8a249a BS |
3653 | gen_movl_reg_T1(rs2); |
3654 | gen_op_add_T1_T0(); | |
e80cfcfc | 3655 | #if defined(OPTIM) |
0f8a249a | 3656 | } |
e80cfcfc | 3657 | #endif |
0f8a249a | 3658 | } |
2f2ecb83 BS |
3659 | if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || |
3660 | (xop > 0x17 && xop <= 0x1d ) || | |
3661 | (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { | |
0f8a249a | 3662 | switch (xop) { |
1a2fb1c0 | 3663 | case 0x0: /* load unsigned word */ |
6ea4a6c8 | 3664 | gen_op_check_align_T0_3(); |
1a2fb1c0 BS |
3665 | ABI32_MASK(cpu_T[0]); |
3666 | tcg_gen_qemu_ld32u(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a BS |
3667 | break; |
3668 | case 0x1: /* load unsigned byte */ | |
1a2fb1c0 BS |
3669 | ABI32_MASK(cpu_T[0]); |
3670 | tcg_gen_qemu_ld8u(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a BS |
3671 | break; |
3672 | case 0x2: /* load unsigned halfword */ | |
6ea4a6c8 | 3673 | gen_op_check_align_T0_1(); |
1a2fb1c0 BS |
3674 | ABI32_MASK(cpu_T[0]); |
3675 | tcg_gen_qemu_ld16u(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a BS |
3676 | break; |
3677 | case 0x3: /* load double word */ | |
0f8a249a | 3678 | if (rd & 1) |
d4218d99 | 3679 | goto illegal_insn; |
1a2fb1c0 BS |
3680 | else { |
3681 | TCGv r_dword; | |
3682 | ||
3683 | r_dword = tcg_temp_new(TCG_TYPE_I64); | |
3684 | gen_op_check_align_T0_7(); | |
3685 | ABI32_MASK(cpu_T[0]); | |
3686 | tcg_gen_qemu_ld64(r_dword, cpu_T[0], dc->mem_idx); | |
3687 | tcg_gen_trunc_i64_i32(cpu_T[0], r_dword); | |
3688 | gen_movl_T0_reg(rd + 1); | |
3689 | tcg_gen_shri_i64(r_dword, r_dword, 32); | |
3690 | tcg_gen_trunc_i64_i32(cpu_T[1], r_dword); | |
3691 | } | |
0f8a249a BS |
3692 | break; |
3693 | case 0x9: /* load signed byte */ | |
1a2fb1c0 BS |
3694 | ABI32_MASK(cpu_T[0]); |
3695 | tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a BS |
3696 | break; |
3697 | case 0xa: /* load signed halfword */ | |
6ea4a6c8 | 3698 | gen_op_check_align_T0_1(); |
1a2fb1c0 BS |
3699 | ABI32_MASK(cpu_T[0]); |
3700 | tcg_gen_qemu_ld16s(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a BS |
3701 | break; |
3702 | case 0xd: /* ldstub -- XXX: should be atomically */ | |
1a2fb1c0 BS |
3703 | tcg_gen_movi_i32(cpu_tmp0, 0xff); |
3704 | ABI32_MASK(cpu_T[0]); | |
3705 | tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx); | |
3706 | tcg_gen_qemu_st8(cpu_tmp0, cpu_T[0], dc->mem_idx); | |
0f8a249a BS |
3707 | break; |
3708 | case 0x0f: /* swap register with memory. Also atomically */ | |
6ea4a6c8 | 3709 | gen_op_check_align_T0_3(); |
0f8a249a | 3710 | gen_movl_reg_T1(rd); |
1a2fb1c0 BS |
3711 | ABI32_MASK(cpu_T[0]); |
3712 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_T[0], dc->mem_idx); | |
3713 | tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx); | |
3714 | tcg_gen_mov_i32(cpu_T[1], cpu_tmp0); | |
0f8a249a | 3715 | break; |
3475187d | 3716 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) |
0f8a249a | 3717 | case 0x10: /* load word alternate */ |
3475187d | 3718 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
3719 | if (IS_IMM) |
3720 | goto illegal_insn; | |
3721 | if (!supervisor(dc)) | |
3722 | goto priv_insn; | |
6ea4a6c8 | 3723 | #endif |
8f577d3d | 3724 | gen_op_check_align_T0_3(); |
81ad8ba2 | 3725 | gen_ld_asi(insn, 4, 0); |
0f8a249a BS |
3726 | break; |
3727 | case 0x11: /* load unsigned byte alternate */ | |
3475187d | 3728 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
3729 | if (IS_IMM) |
3730 | goto illegal_insn; | |
3731 | if (!supervisor(dc)) | |
3732 | goto priv_insn; | |
3733 | #endif | |
81ad8ba2 | 3734 | gen_ld_asi(insn, 1, 0); |
0f8a249a BS |
3735 | break; |
3736 | case 0x12: /* load unsigned halfword alternate */ | |
3475187d | 3737 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
3738 | if (IS_IMM) |
3739 | goto illegal_insn; | |
3740 | if (!supervisor(dc)) | |
3741 | goto priv_insn; | |
3475187d | 3742 | #endif |
8f577d3d | 3743 | gen_op_check_align_T0_1(); |
81ad8ba2 | 3744 | gen_ld_asi(insn, 2, 0); |
0f8a249a BS |
3745 | break; |
3746 | case 0x13: /* load double word alternate */ | |
3475187d | 3747 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
3748 | if (IS_IMM) |
3749 | goto illegal_insn; | |
3750 | if (!supervisor(dc)) | |
3751 | goto priv_insn; | |
3475187d | 3752 | #endif |
0f8a249a | 3753 | if (rd & 1) |
d4218d99 | 3754 | goto illegal_insn; |
6ea4a6c8 | 3755 | gen_op_check_align_T0_7(); |
81ad8ba2 | 3756 | gen_ldda_asi(insn); |
0f8a249a BS |
3757 | gen_movl_T0_reg(rd + 1); |
3758 | break; | |
3759 | case 0x19: /* load signed byte alternate */ | |
3475187d | 3760 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
3761 | if (IS_IMM) |
3762 | goto illegal_insn; | |
3763 | if (!supervisor(dc)) | |
3764 | goto priv_insn; | |
3765 | #endif | |
81ad8ba2 | 3766 | gen_ld_asi(insn, 1, 1); |
0f8a249a BS |
3767 | break; |
3768 | case 0x1a: /* load signed halfword alternate */ | |
3475187d | 3769 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
3770 | if (IS_IMM) |
3771 | goto illegal_insn; | |
3772 | if (!supervisor(dc)) | |
3773 | goto priv_insn; | |
3475187d | 3774 | #endif |
8f577d3d | 3775 | gen_op_check_align_T0_1(); |
81ad8ba2 | 3776 | gen_ld_asi(insn, 2, 1); |
0f8a249a BS |
3777 | break; |
3778 | case 0x1d: /* ldstuba -- XXX: should be atomically */ | |
3475187d | 3779 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
3780 | if (IS_IMM) |
3781 | goto illegal_insn; | |
3782 | if (!supervisor(dc)) | |
3783 | goto priv_insn; | |
3784 | #endif | |
81ad8ba2 | 3785 | gen_ldstub_asi(insn); |
0f8a249a BS |
3786 | break; |
3787 | case 0x1f: /* swap reg with alt. memory. Also atomically */ | |
3475187d | 3788 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
3789 | if (IS_IMM) |
3790 | goto illegal_insn; | |
3791 | if (!supervisor(dc)) | |
3792 | goto priv_insn; | |
6ea4a6c8 | 3793 | #endif |
8f577d3d | 3794 | gen_op_check_align_T0_3(); |
81ad8ba2 BS |
3795 | gen_movl_reg_T1(rd); |
3796 | gen_swap_asi(insn); | |
0f8a249a | 3797 | break; |
3475187d FB |
3798 | |
3799 | #ifndef TARGET_SPARC64 | |
0f8a249a BS |
3800 | case 0x30: /* ldc */ |
3801 | case 0x31: /* ldcsr */ | |
3802 | case 0x33: /* lddc */ | |
3803 | goto ncp_insn; | |
3475187d FB |
3804 | #endif |
3805 | #endif | |
3806 | #ifdef TARGET_SPARC64 | |
0f8a249a | 3807 | case 0x08: /* V9 ldsw */ |
6ea4a6c8 | 3808 | gen_op_check_align_T0_3(); |
1a2fb1c0 BS |
3809 | ABI32_MASK(cpu_T[0]); |
3810 | tcg_gen_qemu_ld32s(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a BS |
3811 | break; |
3812 | case 0x0b: /* V9 ldx */ | |
6ea4a6c8 | 3813 | gen_op_check_align_T0_7(); |
1a2fb1c0 BS |
3814 | ABI32_MASK(cpu_T[0]); |
3815 | tcg_gen_qemu_ld64(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a BS |
3816 | break; |
3817 | case 0x18: /* V9 ldswa */ | |
6ea4a6c8 | 3818 | gen_op_check_align_T0_3(); |
81ad8ba2 | 3819 | gen_ld_asi(insn, 4, 1); |
0f8a249a BS |
3820 | break; |
3821 | case 0x1b: /* V9 ldxa */ | |
6ea4a6c8 | 3822 | gen_op_check_align_T0_7(); |
81ad8ba2 | 3823 | gen_ld_asi(insn, 8, 0); |
0f8a249a BS |
3824 | break; |
3825 | case 0x2d: /* V9 prefetch, no effect */ | |
3826 | goto skip_move; | |
3827 | case 0x30: /* V9 ldfa */ | |
6ea4a6c8 | 3828 | gen_op_check_align_T0_3(); |
2382dc6b | 3829 | gen_ldf_asi(insn, 4, rd); |
81ad8ba2 | 3830 | goto skip_move; |
0f8a249a | 3831 | case 0x33: /* V9 lddfa */ |
3391c818 | 3832 | gen_op_check_align_T0_3(); |
2382dc6b | 3833 | gen_ldf_asi(insn, 8, DFPREG(rd)); |
81ad8ba2 | 3834 | goto skip_move; |
0f8a249a BS |
3835 | case 0x3d: /* V9 prefetcha, no effect */ |
3836 | goto skip_move; | |
3837 | case 0x32: /* V9 ldqfa */ | |
1f587329 BS |
3838 | #if defined(CONFIG_USER_ONLY) |
3839 | gen_op_check_align_T0_3(); | |
2382dc6b | 3840 | gen_ldf_asi(insn, 16, QFPREG(rd)); |
1f587329 BS |
3841 | goto skip_move; |
3842 | #else | |
0f8a249a | 3843 | goto nfpu_insn; |
1f587329 | 3844 | #endif |
0f8a249a BS |
3845 | #endif |
3846 | default: | |
3847 | goto illegal_insn; | |
3848 | } | |
3849 | gen_movl_T1_reg(rd); | |
3475187d | 3850 | #ifdef TARGET_SPARC64 |
0f8a249a | 3851 | skip_move: ; |
3475187d | 3852 | #endif |
0f8a249a | 3853 | } else if (xop >= 0x20 && xop < 0x24) { |
a80dde08 FB |
3854 | if (gen_trap_ifnofpu(dc)) |
3855 | goto jmp_insn; | |
0f8a249a BS |
3856 | switch (xop) { |
3857 | case 0x20: /* load fpreg */ | |
6ea4a6c8 | 3858 | gen_op_check_align_T0_3(); |
0f8a249a BS |
3859 | gen_op_ldst(ldf); |
3860 | gen_op_store_FT0_fpr(rd); | |
3861 | break; | |
3862 | case 0x21: /* load fsr */ | |
6ea4a6c8 | 3863 | gen_op_check_align_T0_3(); |
0f8a249a BS |
3864 | gen_op_ldst(ldf); |
3865 | gen_op_ldfsr(); | |
7e8c2b6c | 3866 | tcg_gen_helper_0_0(helper_ldfsr); |
0f8a249a BS |
3867 | break; |
3868 | case 0x22: /* load quad fpreg */ | |
1f587329 BS |
3869 | #if defined(CONFIG_USER_ONLY) |
3870 | gen_op_check_align_T0_7(); | |
3871 | gen_op_ldst(ldqf); | |
3872 | gen_op_store_QT0_fpr(QFPREG(rd)); | |
3873 | break; | |
3874 | #else | |
0f8a249a | 3875 | goto nfpu_insn; |
1f587329 | 3876 | #endif |
0f8a249a | 3877 | case 0x23: /* load double fpreg */ |
6ea4a6c8 | 3878 | gen_op_check_align_T0_7(); |
0f8a249a BS |
3879 | gen_op_ldst(lddf); |
3880 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
3881 | break; | |
3882 | default: | |
3883 | goto illegal_insn; | |
3884 | } | |
3885 | } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \ | |
3886 | xop == 0xe || xop == 0x1e) { | |
3887 | gen_movl_reg_T1(rd); | |
3888 | switch (xop) { | |
1a2fb1c0 | 3889 | case 0x4: /* store word */ |
6ea4a6c8 | 3890 | gen_op_check_align_T0_3(); |
1a2fb1c0 BS |
3891 | ABI32_MASK(cpu_T[0]); |
3892 | tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a | 3893 | break; |
1a2fb1c0 BS |
3894 | case 0x5: /* store byte */ |
3895 | ABI32_MASK(cpu_T[0]); | |
3896 | tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a | 3897 | break; |
1a2fb1c0 | 3898 | case 0x6: /* store halfword */ |
6ea4a6c8 | 3899 | gen_op_check_align_T0_1(); |
1a2fb1c0 BS |
3900 | ABI32_MASK(cpu_T[0]); |
3901 | tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a | 3902 | break; |
1a2fb1c0 | 3903 | case 0x7: /* store double word */ |
0f8a249a | 3904 | if (rd & 1) |
d4218d99 | 3905 | goto illegal_insn; |
b25deda7 | 3906 | #ifndef __i386__ |
1a2fb1c0 BS |
3907 | else { |
3908 | TCGv r_dword, r_low; | |
3909 | ||
3910 | gen_op_check_align_T0_7(); | |
3911 | r_dword = tcg_temp_new(TCG_TYPE_I64); | |
3912 | r_low = tcg_temp_new(TCG_TYPE_I32); | |
3913 | gen_movl_reg_TN(rd + 1, r_low); | |
3914 | tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1], | |
3915 | r_low); | |
3916 | tcg_gen_qemu_st64(r_dword, cpu_T[0], dc->mem_idx); | |
3917 | } | |
b25deda7 BS |
3918 | #else /* __i386__ */ |
3919 | gen_op_check_align_T0_7(); | |
3920 | flush_T2(dc); | |
3921 | gen_movl_reg_T2(rd + 1); | |
3922 | gen_op_ldst(std); | |
3923 | #endif /* __i386__ */ | |
0f8a249a | 3924 | break; |
3475187d | 3925 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) |
1a2fb1c0 | 3926 | case 0x14: /* store word alternate */ |
3475187d | 3927 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
3928 | if (IS_IMM) |
3929 | goto illegal_insn; | |
3930 | if (!supervisor(dc)) | |
3931 | goto priv_insn; | |
6ea4a6c8 | 3932 | #endif |
6ea4a6c8 | 3933 | gen_op_check_align_T0_3(); |
81ad8ba2 | 3934 | gen_st_asi(insn, 4); |
d39c0b99 | 3935 | break; |
1a2fb1c0 | 3936 | case 0x15: /* store byte alternate */ |
3475187d | 3937 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
3938 | if (IS_IMM) |
3939 | goto illegal_insn; | |
3940 | if (!supervisor(dc)) | |
3941 | goto priv_insn; | |
3475187d | 3942 | #endif |
81ad8ba2 | 3943 | gen_st_asi(insn, 1); |
d39c0b99 | 3944 | break; |
1a2fb1c0 | 3945 | case 0x16: /* store halfword alternate */ |
3475187d | 3946 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
3947 | if (IS_IMM) |
3948 | goto illegal_insn; | |
3949 | if (!supervisor(dc)) | |
3950 | goto priv_insn; | |
6ea4a6c8 | 3951 | #endif |
6ea4a6c8 | 3952 | gen_op_check_align_T0_1(); |
81ad8ba2 | 3953 | gen_st_asi(insn, 2); |
d39c0b99 | 3954 | break; |
1a2fb1c0 | 3955 | case 0x17: /* store double word alternate */ |
3475187d | 3956 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
3957 | if (IS_IMM) |
3958 | goto illegal_insn; | |
3959 | if (!supervisor(dc)) | |
3960 | goto priv_insn; | |
3475187d | 3961 | #endif |
0f8a249a | 3962 | if (rd & 1) |
d4218d99 | 3963 | goto illegal_insn; |
1a2fb1c0 BS |
3964 | else { |
3965 | int asi; | |
3966 | TCGv r_dword, r_temp, r_size; | |
3967 | ||
3968 | gen_op_check_align_T0_7(); | |
3969 | r_dword = tcg_temp_new(TCG_TYPE_I64); | |
3970 | r_temp = tcg_temp_new(TCG_TYPE_I32); | |
3971 | r_size = tcg_temp_new(TCG_TYPE_I32); | |
3972 | gen_movl_reg_TN(rd + 1, r_temp); | |
3973 | tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1], | |
3974 | r_temp); | |
3975 | #ifdef TARGET_SPARC64 | |
3976 | if (IS_IMM) { | |
3977 | int offset; | |
3978 | ||
3979 | offset = GET_FIELD(insn, 25, 31); | |
3980 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset); | |
3981 | tcg_gen_ld_i32(r_dword, cpu_env, offsetof(CPUSPARCState, asi)); | |
3982 | } else { | |
3983 | #endif | |
3984 | asi = GET_FIELD(insn, 19, 26); | |
3985 | tcg_gen_movi_i32(r_temp, asi); | |
3986 | #ifdef TARGET_SPARC64 | |
3987 | } | |
3988 | #endif | |
3989 | tcg_gen_movi_i32(r_size, 8); | |
3990 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_temp, r_size); | |
3991 | } | |
d39c0b99 | 3992 | break; |
e80cfcfc | 3993 | #endif |
3475187d | 3994 | #ifdef TARGET_SPARC64 |
0f8a249a | 3995 | case 0x0e: /* V9 stx */ |
6ea4a6c8 | 3996 | gen_op_check_align_T0_7(); |
1a2fb1c0 BS |
3997 | ABI32_MASK(cpu_T[0]); |
3998 | tcg_gen_qemu_st64(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a BS |
3999 | break; |
4000 | case 0x1e: /* V9 stxa */ | |
6ea4a6c8 | 4001 | gen_op_check_align_T0_7(); |
81ad8ba2 | 4002 | gen_st_asi(insn, 8); |
0f8a249a | 4003 | break; |
3475187d | 4004 | #endif |
0f8a249a BS |
4005 | default: |
4006 | goto illegal_insn; | |
4007 | } | |
4008 | } else if (xop > 0x23 && xop < 0x28) { | |
a80dde08 FB |
4009 | if (gen_trap_ifnofpu(dc)) |
4010 | goto jmp_insn; | |
0f8a249a BS |
4011 | switch (xop) { |
4012 | case 0x24: | |
6ea4a6c8 | 4013 | gen_op_check_align_T0_3(); |
e8af50a3 | 4014 | gen_op_load_fpr_FT0(rd); |
0f8a249a BS |
4015 | gen_op_ldst(stf); |
4016 | break; | |
4017 | case 0x25: /* stfsr, V9 stxfsr */ | |
6ea4a6c8 BS |
4018 | #ifdef CONFIG_USER_ONLY |
4019 | gen_op_check_align_T0_3(); | |
4020 | #endif | |
0f8a249a BS |
4021 | gen_op_stfsr(); |
4022 | gen_op_ldst(stf); | |
4023 | break; | |
1f587329 BS |
4024 | case 0x26: |
4025 | #ifdef TARGET_SPARC64 | |
4026 | #if defined(CONFIG_USER_ONLY) | |
4027 | /* V9 stqf, store quad fpreg */ | |
4028 | gen_op_check_align_T0_7(); | |
4029 | gen_op_load_fpr_QT0(QFPREG(rd)); | |
4030 | gen_op_ldst(stqf); | |
4031 | break; | |
4032 | #else | |
4033 | goto nfpu_insn; | |
4034 | #endif | |
4035 | #else /* !TARGET_SPARC64 */ | |
4036 | /* stdfq, store floating point queue */ | |
4037 | #if defined(CONFIG_USER_ONLY) | |
4038 | goto illegal_insn; | |
4039 | #else | |
0f8a249a BS |
4040 | if (!supervisor(dc)) |
4041 | goto priv_insn; | |
4042 | if (gen_trap_ifnofpu(dc)) | |
4043 | goto jmp_insn; | |
4044 | goto nfq_insn; | |
1f587329 | 4045 | #endif |
0f8a249a BS |
4046 | #endif |
4047 | case 0x27: | |
6ea4a6c8 | 4048 | gen_op_check_align_T0_7(); |
3475187d | 4049 | gen_op_load_fpr_DT0(DFPREG(rd)); |
0f8a249a BS |
4050 | gen_op_ldst(stdf); |
4051 | break; | |
4052 | default: | |
4053 | goto illegal_insn; | |
4054 | } | |
4055 | } else if (xop > 0x33 && xop < 0x3f) { | |
4056 | switch (xop) { | |
a4d17f19 | 4057 | #ifdef TARGET_SPARC64 |
0f8a249a | 4058 | case 0x34: /* V9 stfa */ |
6ea4a6c8 | 4059 | gen_op_check_align_T0_3(); |
3391c818 | 4060 | gen_op_load_fpr_FT0(rd); |
2382dc6b | 4061 | gen_stf_asi(insn, 4, rd); |
0f8a249a | 4062 | break; |
1f587329 BS |
4063 | case 0x36: /* V9 stqfa */ |
4064 | #if defined(CONFIG_USER_ONLY) | |
4065 | gen_op_check_align_T0_7(); | |
4066 | gen_op_load_fpr_QT0(QFPREG(rd)); | |
2382dc6b | 4067 | gen_stf_asi(insn, 16, QFPREG(rd)); |
1f587329 BS |
4068 | break; |
4069 | #else | |
4070 | goto nfpu_insn; | |
4071 | #endif | |
0f8a249a | 4072 | case 0x37: /* V9 stdfa */ |
3391c818 BS |
4073 | gen_op_check_align_T0_3(); |
4074 | gen_op_load_fpr_DT0(DFPREG(rd)); | |
2382dc6b | 4075 | gen_stf_asi(insn, 8, DFPREG(rd)); |
0f8a249a BS |
4076 | break; |
4077 | case 0x3c: /* V9 casa */ | |
6ea4a6c8 | 4078 | gen_op_check_align_T0_3(); |
1a2fb1c0 | 4079 | gen_cas_asi(insn, rd); |
81ad8ba2 | 4080 | gen_movl_T1_reg(rd); |
0f8a249a BS |
4081 | break; |
4082 | case 0x3e: /* V9 casxa */ | |
6ea4a6c8 | 4083 | gen_op_check_align_T0_7(); |
1a2fb1c0 | 4084 | gen_casx_asi(insn, rd); |
81ad8ba2 | 4085 | gen_movl_T1_reg(rd); |
0f8a249a | 4086 | break; |
a4d17f19 | 4087 | #else |
0f8a249a BS |
4088 | case 0x34: /* stc */ |
4089 | case 0x35: /* stcsr */ | |
4090 | case 0x36: /* stdcq */ | |
4091 | case 0x37: /* stdc */ | |
4092 | goto ncp_insn; | |
4093 | #endif | |
4094 | default: | |
4095 | goto illegal_insn; | |
4096 | } | |
e8af50a3 | 4097 | } |
0f8a249a BS |
4098 | else |
4099 | goto illegal_insn; | |
4100 | } | |
4101 | break; | |
cf495bcf FB |
4102 | } |
4103 | /* default case for non jump instructions */ | |
72cbca10 | 4104 | if (dc->npc == DYNAMIC_PC) { |
0f8a249a BS |
4105 | dc->pc = DYNAMIC_PC; |
4106 | gen_op_next_insn(); | |
72cbca10 FB |
4107 | } else if (dc->npc == JUMP_PC) { |
4108 | /* we can do a static jump */ | |
19f329ad | 4109 | gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]); |
72cbca10 FB |
4110 | dc->is_br = 1; |
4111 | } else { | |
0f8a249a BS |
4112 | dc->pc = dc->npc; |
4113 | dc->npc = dc->npc + 4; | |
cf495bcf | 4114 | } |
e80cfcfc | 4115 | jmp_insn: |
cf495bcf FB |
4116 | return; |
4117 | illegal_insn: | |
72cbca10 | 4118 | save_state(dc); |
cf495bcf FB |
4119 | gen_op_exception(TT_ILL_INSN); |
4120 | dc->is_br = 1; | |
e8af50a3 | 4121 | return; |
e80cfcfc | 4122 | #if !defined(CONFIG_USER_ONLY) |
e8af50a3 FB |
4123 | priv_insn: |
4124 | save_state(dc); | |
4125 | gen_op_exception(TT_PRIV_INSN); | |
4126 | dc->is_br = 1; | |
e80cfcfc | 4127 | return; |
e80cfcfc FB |
4128 | nfpu_insn: |
4129 | save_state(dc); | |
4130 | gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); | |
4131 | dc->is_br = 1; | |
fcc72045 | 4132 | return; |
1f587329 | 4133 | #ifndef TARGET_SPARC64 |
9143e598 BS |
4134 | nfq_insn: |
4135 | save_state(dc); | |
4136 | gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); | |
4137 | dc->is_br = 1; | |
4138 | return; | |
4139 | #endif | |
1f587329 | 4140 | #endif |
fcc72045 BS |
4141 | #ifndef TARGET_SPARC64 |
4142 | ncp_insn: | |
4143 | save_state(dc); | |
4144 | gen_op_exception(TT_NCP_INSN); | |
4145 | dc->is_br = 1; | |
4146 | return; | |
4147 | #endif | |
7a3f1944 FB |
4148 | } |
4149 | ||
1a2fb1c0 BS |
4150 | static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args) |
4151 | { | |
4152 | } | |
4153 | ||
cf495bcf | 4154 | static inline int gen_intermediate_code_internal(TranslationBlock * tb, |
0f8a249a | 4155 | int spc, CPUSPARCState *env) |
7a3f1944 | 4156 | { |
72cbca10 | 4157 | target_ulong pc_start, last_pc; |
cf495bcf FB |
4158 | uint16_t *gen_opc_end; |
4159 | DisasContext dc1, *dc = &dc1; | |
e8af50a3 | 4160 | int j, lj = -1; |
cf495bcf FB |
4161 | |
4162 | memset(dc, 0, sizeof(DisasContext)); | |
cf495bcf | 4163 | dc->tb = tb; |
72cbca10 | 4164 | pc_start = tb->pc; |
cf495bcf | 4165 | dc->pc = pc_start; |
e80cfcfc | 4166 | last_pc = dc->pc; |
72cbca10 | 4167 | dc->npc = (target_ulong) tb->cs_base; |
6f27aba6 BS |
4168 | dc->mem_idx = cpu_mmu_index(env); |
4169 | dc->fpu_enabled = cpu_fpu_enabled(env); | |
cf495bcf | 4170 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
cf495bcf | 4171 | |
1a2fb1c0 | 4172 | cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL); |
1a2fb1c0 | 4173 | |
cf495bcf | 4174 | do { |
e8af50a3 FB |
4175 | if (env->nb_breakpoints > 0) { |
4176 | for(j = 0; j < env->nb_breakpoints; j++) { | |
4177 | if (env->breakpoints[j] == dc->pc) { | |
0f8a249a BS |
4178 | if (dc->pc != pc_start) |
4179 | save_state(dc); | |
1a2fb1c0 | 4180 | tcg_gen_helper_0_0(helper_debug); |
57fec1fe | 4181 | tcg_gen_exit_tb(0); |
0f8a249a | 4182 | dc->is_br = 1; |
e80cfcfc | 4183 | goto exit_gen_loop; |
e8af50a3 FB |
4184 | } |
4185 | } | |
4186 | } | |
4187 | if (spc) { | |
4188 | if (loglevel > 0) | |
4189 | fprintf(logfile, "Search PC...\n"); | |
4190 | j = gen_opc_ptr - gen_opc_buf; | |
4191 | if (lj < j) { | |
4192 | lj++; | |
4193 | while (lj < j) | |
4194 | gen_opc_instr_start[lj++] = 0; | |
4195 | gen_opc_pc[lj] = dc->pc; | |
4196 | gen_opc_npc[lj] = dc->npc; | |
4197 | gen_opc_instr_start[lj] = 1; | |
4198 | } | |
4199 | } | |
0f8a249a BS |
4200 | last_pc = dc->pc; |
4201 | disas_sparc_insn(dc); | |
4202 | ||
4203 | if (dc->is_br) | |
4204 | break; | |
4205 | /* if the next PC is different, we abort now */ | |
4206 | if (dc->pc != (last_pc + 4)) | |
4207 | break; | |
d39c0b99 FB |
4208 | /* if we reach a page boundary, we stop generation so that the |
4209 | PC of a TT_TFAULT exception is always in the right page */ | |
4210 | if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) | |
4211 | break; | |
e80cfcfc FB |
4212 | /* if single step mode, we generate only one instruction and |
4213 | generate an exception */ | |
4214 | if (env->singlestep_enabled) { | |
3475187d | 4215 | gen_jmp_im(dc->pc); |
57fec1fe | 4216 | tcg_gen_exit_tb(0); |
e80cfcfc FB |
4217 | break; |
4218 | } | |
cf495bcf | 4219 | } while ((gen_opc_ptr < gen_opc_end) && |
0f8a249a | 4220 | (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32)); |
e80cfcfc FB |
4221 | |
4222 | exit_gen_loop: | |
72cbca10 | 4223 | if (!dc->is_br) { |
5fafdf24 | 4224 | if (dc->pc != DYNAMIC_PC && |
72cbca10 FB |
4225 | (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { |
4226 | /* static PC and NPC: we can use direct chaining */ | |
46525e1f | 4227 | gen_branch(dc, dc->pc, dc->npc); |
72cbca10 FB |
4228 | } else { |
4229 | if (dc->pc != DYNAMIC_PC) | |
3475187d | 4230 | gen_jmp_im(dc->pc); |
72cbca10 | 4231 | save_npc(dc); |
57fec1fe | 4232 | tcg_gen_exit_tb(0); |
72cbca10 FB |
4233 | } |
4234 | } | |
cf495bcf | 4235 | *gen_opc_ptr = INDEX_op_end; |
e8af50a3 FB |
4236 | if (spc) { |
4237 | j = gen_opc_ptr - gen_opc_buf; | |
4238 | lj++; | |
4239 | while (lj <= j) | |
4240 | gen_opc_instr_start[lj++] = 0; | |
e8af50a3 FB |
4241 | #if 0 |
4242 | if (loglevel > 0) { | |
4243 | page_dump(logfile); | |
4244 | } | |
4245 | #endif | |
c3278b7b FB |
4246 | gen_opc_jump_pc[0] = dc->jump_pc[0]; |
4247 | gen_opc_jump_pc[1] = dc->jump_pc[1]; | |
e8af50a3 | 4248 | } else { |
e80cfcfc | 4249 | tb->size = last_pc + 4 - pc_start; |
e8af50a3 | 4250 | } |
7a3f1944 | 4251 | #ifdef DEBUG_DISAS |
e19e89a5 | 4252 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
0f8a249a BS |
4253 | fprintf(logfile, "--------------\n"); |
4254 | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start)); | |
4255 | target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0); | |
4256 | fprintf(logfile, "\n"); | |
cf495bcf | 4257 | } |
7a3f1944 | 4258 | #endif |
cf495bcf | 4259 | return 0; |
7a3f1944 FB |
4260 | } |
4261 | ||
cf495bcf | 4262 | int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb) |
7a3f1944 | 4263 | { |
e8af50a3 | 4264 | return gen_intermediate_code_internal(tb, 0, env); |
7a3f1944 FB |
4265 | } |
4266 | ||
cf495bcf | 4267 | int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb) |
7a3f1944 | 4268 | { |
e8af50a3 | 4269 | return gen_intermediate_code_internal(tb, 1, env); |
7a3f1944 FB |
4270 | } |
4271 | ||
e80cfcfc FB |
4272 | void cpu_reset(CPUSPARCState *env) |
4273 | { | |
bb05683b | 4274 | tlb_flush(env, 1); |
cf495bcf FB |
4275 | env->cwp = 0; |
4276 | env->wim = 1; | |
4277 | env->regwptr = env->regbase + (env->cwp * 16); | |
e8af50a3 | 4278 | #if defined(CONFIG_USER_ONLY) |
cf495bcf | 4279 | env->user_mode_only = 1; |
5ef54116 | 4280 | #ifdef TARGET_SPARC64 |
6ef905f6 BS |
4281 | env->cleanwin = NWINDOWS - 2; |
4282 | env->cansave = NWINDOWS - 2; | |
4283 | env->pstate = PS_RMO | PS_PEF | PS_IE; | |
4284 | env->asi = 0x82; // Primary no-fault | |
5ef54116 | 4285 | #endif |
e8af50a3 | 4286 | #else |
32af58f9 | 4287 | env->psret = 0; |
e8af50a3 | 4288 | env->psrs = 1; |
0bee699e | 4289 | env->psrps = 1; |
3475187d | 4290 | #ifdef TARGET_SPARC64 |
83469015 | 4291 | env->pstate = PS_PRIV; |
6f27aba6 | 4292 | env->hpstate = HS_PRIV; |
83469015 | 4293 | env->pc = 0x1fff0000000ULL; |
375ee38b | 4294 | env->tsptr = &env->ts[env->tl]; |
3475187d | 4295 | #else |
40ce0a9a | 4296 | env->pc = 0; |
32af58f9 | 4297 | env->mmuregs[0] &= ~(MMU_E | MMU_NF); |
6d5f237a | 4298 | env->mmuregs[0] |= env->mmu_bm; |
3475187d | 4299 | #endif |
83469015 | 4300 | env->npc = env->pc + 4; |
e8af50a3 | 4301 | #endif |
e80cfcfc FB |
4302 | } |
4303 | ||
aaed909a | 4304 | CPUSPARCState *cpu_sparc_init(const char *cpu_model) |
e80cfcfc FB |
4305 | { |
4306 | CPUSPARCState *env; | |
aaed909a | 4307 | const sparc_def_t *def; |
1a2fb1c0 | 4308 | static int inited; |
aaed909a FB |
4309 | |
4310 | def = cpu_sparc_find_by_name(cpu_model); | |
4311 | if (!def) | |
4312 | return NULL; | |
e80cfcfc | 4313 | |
c68ea704 FB |
4314 | env = qemu_mallocz(sizeof(CPUSPARCState)); |
4315 | if (!env) | |
0f8a249a | 4316 | return NULL; |
c68ea704 | 4317 | cpu_exec_init(env); |
01ba9816 | 4318 | env->cpu_model_str = cpu_model; |
aaed909a FB |
4319 | env->version = def->iu_version; |
4320 | env->fsr = def->fpu_version; | |
4321 | #if !defined(TARGET_SPARC64) | |
4322 | env->mmu_bm = def->mmu_bm; | |
3deaeab7 BS |
4323 | env->mmu_ctpr_mask = def->mmu_ctpr_mask; |
4324 | env->mmu_cxr_mask = def->mmu_cxr_mask; | |
4325 | env->mmu_sfsr_mask = def->mmu_sfsr_mask; | |
4326 | env->mmu_trcr_mask = def->mmu_trcr_mask; | |
aaed909a FB |
4327 | env->mmuregs[0] |= def->mmu_version; |
4328 | cpu_sparc_set_id(env, 0); | |
4329 | #endif | |
1a2fb1c0 BS |
4330 | |
4331 | /* init various static tables */ | |
4332 | if (!inited) { | |
4333 | inited = 1; | |
4334 | ||
4335 | tcg_set_macro_func(&tcg_ctx, tcg_macro_func); | |
4336 | cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env"); | |
db4a4ea4 BS |
4337 | cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0, |
4338 | offsetof(CPUState, regwptr), | |
4339 | "regwptr"); | |
1a2fb1c0 BS |
4340 | //#if TARGET_LONG_BITS > HOST_LONG_BITS |
4341 | #ifdef TARGET_SPARC64 | |
4342 | cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL, | |
4343 | TCG_AREG0, offsetof(CPUState, t0), "T0"); | |
4344 | cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL, | |
4345 | TCG_AREG0, offsetof(CPUState, t1), "T1"); | |
4346 | cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL, | |
4347 | TCG_AREG0, offsetof(CPUState, t2), "T2"); | |
4348 | #else | |
4349 | cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0"); | |
4350 | cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1"); | |
4351 | cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2"); | |
4352 | #endif | |
4353 | } | |
4354 | ||
aaed909a FB |
4355 | cpu_reset(env); |
4356 | ||
4357 | return env; | |
4358 | } | |
4359 | ||
4360 | void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) | |
4361 | { | |
4362 | #if !defined(TARGET_SPARC64) | |
4363 | env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; | |
4364 | #endif | |
7a3f1944 FB |
4365 | } |
4366 | ||
62724a37 BS |
4367 | static const sparc_def_t sparc_defs[] = { |
4368 | #ifdef TARGET_SPARC64 | |
7d77bf20 BS |
4369 | { |
4370 | .name = "Fujitsu Sparc64", | |
4371 | .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24) | |
4372 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4373 | .fpu_version = 0x00000000, | |
4374 | .mmu_version = 0, | |
4375 | }, | |
4376 | { | |
4377 | .name = "Fujitsu Sparc64 III", | |
4378 | .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24) | |
4379 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4380 | .fpu_version = 0x00000000, | |
4381 | .mmu_version = 0, | |
4382 | }, | |
4383 | { | |
4384 | .name = "Fujitsu Sparc64 IV", | |
4385 | .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24) | |
4386 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4387 | .fpu_version = 0x00000000, | |
4388 | .mmu_version = 0, | |
4389 | }, | |
4390 | { | |
4391 | .name = "Fujitsu Sparc64 V", | |
4392 | .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24) | |
4393 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4394 | .fpu_version = 0x00000000, | |
4395 | .mmu_version = 0, | |
4396 | }, | |
4397 | { | |
4398 | .name = "TI UltraSparc I", | |
4399 | .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) | |
4400 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4401 | .fpu_version = 0x00000000, | |
4402 | .mmu_version = 0, | |
4403 | }, | |
62724a37 BS |
4404 | { |
4405 | .name = "TI UltraSparc II", | |
7d77bf20 BS |
4406 | .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24) |
4407 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4408 | .fpu_version = 0x00000000, | |
4409 | .mmu_version = 0, | |
4410 | }, | |
4411 | { | |
4412 | .name = "TI UltraSparc IIi", | |
4413 | .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24) | |
4414 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4415 | .fpu_version = 0x00000000, | |
4416 | .mmu_version = 0, | |
4417 | }, | |
4418 | { | |
4419 | .name = "TI UltraSparc IIe", | |
4420 | .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24) | |
4421 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4422 | .fpu_version = 0x00000000, | |
4423 | .mmu_version = 0, | |
4424 | }, | |
4425 | { | |
4426 | .name = "Sun UltraSparc III", | |
4427 | .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24) | |
4428 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4429 | .fpu_version = 0x00000000, | |
4430 | .mmu_version = 0, | |
4431 | }, | |
4432 | { | |
4433 | .name = "Sun UltraSparc III Cu", | |
4434 | .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24) | |
4435 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4436 | .fpu_version = 0x00000000, | |
4437 | .mmu_version = 0, | |
4438 | }, | |
4439 | { | |
4440 | .name = "Sun UltraSparc IIIi", | |
4441 | .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24) | |
4442 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4443 | .fpu_version = 0x00000000, | |
4444 | .mmu_version = 0, | |
4445 | }, | |
4446 | { | |
4447 | .name = "Sun UltraSparc IV", | |
4448 | .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24) | |
4449 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4450 | .fpu_version = 0x00000000, | |
4451 | .mmu_version = 0, | |
4452 | }, | |
4453 | { | |
4454 | .name = "Sun UltraSparc IV+", | |
4455 | .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24) | |
4456 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4457 | .fpu_version = 0x00000000, | |
4458 | .mmu_version = 0, | |
4459 | }, | |
4460 | { | |
4461 | .name = "Sun UltraSparc IIIi+", | |
4462 | .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24) | |
4463 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4464 | .fpu_version = 0x00000000, | |
4465 | .mmu_version = 0, | |
4466 | }, | |
4467 | { | |
4468 | .name = "NEC UltraSparc I", | |
4469 | .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) | |
62724a37 BS |
4470 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4471 | .fpu_version = 0x00000000, | |
4472 | .mmu_version = 0, | |
4473 | }, | |
4474 | #else | |
406f82e8 BS |
4475 | { |
4476 | .name = "Fujitsu MB86900", | |
4477 | .iu_version = 0x00 << 24, /* Impl 0, ver 0 */ | |
4478 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
4479 | .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */ | |
4480 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
4481 | .mmu_ctpr_mask = 0x007ffff0, |
4482 | .mmu_cxr_mask = 0x0000003f, | |
4483 | .mmu_sfsr_mask = 0xffffffff, | |
4484 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 | 4485 | }, |
62724a37 BS |
4486 | { |
4487 | .name = "Fujitsu MB86904", | |
4488 | .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ | |
4489 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
4490 | .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ | |
6d5f237a | 4491 | .mmu_bm = 0x00004000, |
3deaeab7 BS |
4492 | .mmu_ctpr_mask = 0x00ffffc0, |
4493 | .mmu_cxr_mask = 0x000000ff, | |
4494 | .mmu_sfsr_mask = 0x00016fff, | |
4495 | .mmu_trcr_mask = 0x00ffffff, | |
62724a37 | 4496 | }, |
e0353fe2 | 4497 | { |
5ef62c5c BS |
4498 | .name = "Fujitsu MB86907", |
4499 | .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ | |
4500 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
4501 | .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ | |
6d5f237a | 4502 | .mmu_bm = 0x00004000, |
3deaeab7 BS |
4503 | .mmu_ctpr_mask = 0xffffffc0, |
4504 | .mmu_cxr_mask = 0x000000ff, | |
4505 | .mmu_sfsr_mask = 0x00016fff, | |
4506 | .mmu_trcr_mask = 0xffffffff, | |
5ef62c5c | 4507 | }, |
406f82e8 BS |
4508 | { |
4509 | .name = "LSI L64811", | |
4510 | .iu_version = 0x10 << 24, /* Impl 1, ver 0 */ | |
4511 | .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */ | |
4512 | .mmu_version = 0x10 << 24, | |
4513 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
4514 | .mmu_ctpr_mask = 0x007ffff0, |
4515 | .mmu_cxr_mask = 0x0000003f, | |
4516 | .mmu_sfsr_mask = 0xffffffff, | |
4517 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 BS |
4518 | }, |
4519 | { | |
4520 | .name = "Cypress CY7C601", | |
4521 | .iu_version = 0x11 << 24, /* Impl 1, ver 1 */ | |
4522 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ | |
4523 | .mmu_version = 0x10 << 24, | |
4524 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
4525 | .mmu_ctpr_mask = 0x007ffff0, |
4526 | .mmu_cxr_mask = 0x0000003f, | |
4527 | .mmu_sfsr_mask = 0xffffffff, | |
4528 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 BS |
4529 | }, |
4530 | { | |
4531 | .name = "Cypress CY7C611", | |
4532 | .iu_version = 0x13 << 24, /* Impl 1, ver 3 */ | |
4533 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ | |
4534 | .mmu_version = 0x10 << 24, | |
4535 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
4536 | .mmu_ctpr_mask = 0x007ffff0, |
4537 | .mmu_cxr_mask = 0x0000003f, | |
4538 | .mmu_sfsr_mask = 0xffffffff, | |
4539 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 BS |
4540 | }, |
4541 | { | |
4542 | .name = "TI SuperSparc II", | |
4543 | .iu_version = 0x40000000, | |
4544 | .fpu_version = 0 << 17, | |
4545 | .mmu_version = 0x04000000, | |
4546 | .mmu_bm = 0x00002000, | |
3deaeab7 BS |
4547 | .mmu_ctpr_mask = 0xffffffc0, |
4548 | .mmu_cxr_mask = 0x0000ffff, | |
4549 | .mmu_sfsr_mask = 0xffffffff, | |
4550 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 | 4551 | }, |
5ef62c5c BS |
4552 | { |
4553 | .name = "TI MicroSparc I", | |
4554 | .iu_version = 0x41000000, | |
4555 | .fpu_version = 4 << 17, | |
4556 | .mmu_version = 0x41000000, | |
6d5f237a | 4557 | .mmu_bm = 0x00004000, |
3deaeab7 BS |
4558 | .mmu_ctpr_mask = 0x007ffff0, |
4559 | .mmu_cxr_mask = 0x0000003f, | |
4560 | .mmu_sfsr_mask = 0x00016fff, | |
4561 | .mmu_trcr_mask = 0x0000003f, | |
5ef62c5c BS |
4562 | }, |
4563 | { | |
406f82e8 BS |
4564 | .name = "TI MicroSparc II", |
4565 | .iu_version = 0x42000000, | |
4566 | .fpu_version = 4 << 17, | |
4567 | .mmu_version = 0x02000000, | |
4568 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
4569 | .mmu_ctpr_mask = 0x00ffffc0, |
4570 | .mmu_cxr_mask = 0x000000ff, | |
a3ffaf30 | 4571 | .mmu_sfsr_mask = 0x00016fff, |
3deaeab7 | 4572 | .mmu_trcr_mask = 0x00ffffff, |
406f82e8 BS |
4573 | }, |
4574 | { | |
4575 | .name = "TI MicroSparc IIep", | |
4576 | .iu_version = 0x42000000, | |
4577 | .fpu_version = 4 << 17, | |
4578 | .mmu_version = 0x04000000, | |
4579 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
4580 | .mmu_ctpr_mask = 0x00ffffc0, |
4581 | .mmu_cxr_mask = 0x000000ff, | |
4582 | .mmu_sfsr_mask = 0x00016bff, | |
4583 | .mmu_trcr_mask = 0x00ffffff, | |
406f82e8 BS |
4584 | }, |
4585 | { | |
4586 | .name = "TI SuperSparc 51", | |
4587 | .iu_version = 0x43000000, | |
5ef62c5c BS |
4588 | .fpu_version = 0 << 17, |
4589 | .mmu_version = 0x04000000, | |
6d5f237a | 4590 | .mmu_bm = 0x00002000, |
3deaeab7 BS |
4591 | .mmu_ctpr_mask = 0xffffffc0, |
4592 | .mmu_cxr_mask = 0x0000ffff, | |
4593 | .mmu_sfsr_mask = 0xffffffff, | |
4594 | .mmu_trcr_mask = 0xffffffff, | |
5ef62c5c BS |
4595 | }, |
4596 | { | |
406f82e8 BS |
4597 | .name = "TI SuperSparc 61", |
4598 | .iu_version = 0x44000000, | |
4599 | .fpu_version = 0 << 17, | |
4600 | .mmu_version = 0x04000000, | |
4601 | .mmu_bm = 0x00002000, | |
3deaeab7 BS |
4602 | .mmu_ctpr_mask = 0xffffffc0, |
4603 | .mmu_cxr_mask = 0x0000ffff, | |
4604 | .mmu_sfsr_mask = 0xffffffff, | |
4605 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 BS |
4606 | }, |
4607 | { | |
4608 | .name = "Ross RT625", | |
5ef62c5c BS |
4609 | .iu_version = 0x1e000000, |
4610 | .fpu_version = 1 << 17, | |
406f82e8 BS |
4611 | .mmu_version = 0x1e000000, |
4612 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
4613 | .mmu_ctpr_mask = 0x007ffff0, |
4614 | .mmu_cxr_mask = 0x0000003f, | |
4615 | .mmu_sfsr_mask = 0xffffffff, | |
4616 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 BS |
4617 | }, |
4618 | { | |
4619 | .name = "Ross RT620", | |
4620 | .iu_version = 0x1f000000, | |
4621 | .fpu_version = 1 << 17, | |
4622 | .mmu_version = 0x1f000000, | |
4623 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
4624 | .mmu_ctpr_mask = 0x007ffff0, |
4625 | .mmu_cxr_mask = 0x0000003f, | |
4626 | .mmu_sfsr_mask = 0xffffffff, | |
4627 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 BS |
4628 | }, |
4629 | { | |
4630 | .name = "BIT B5010", | |
4631 | .iu_version = 0x20000000, | |
4632 | .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */ | |
4633 | .mmu_version = 0x20000000, | |
4634 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
4635 | .mmu_ctpr_mask = 0x007ffff0, |
4636 | .mmu_cxr_mask = 0x0000003f, | |
4637 | .mmu_sfsr_mask = 0xffffffff, | |
4638 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 BS |
4639 | }, |
4640 | { | |
4641 | .name = "Matsushita MN10501", | |
4642 | .iu_version = 0x50000000, | |
4643 | .fpu_version = 0 << 17, | |
4644 | .mmu_version = 0x50000000, | |
4645 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
4646 | .mmu_ctpr_mask = 0x007ffff0, |
4647 | .mmu_cxr_mask = 0x0000003f, | |
4648 | .mmu_sfsr_mask = 0xffffffff, | |
4649 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 BS |
4650 | }, |
4651 | { | |
4652 | .name = "Weitek W8601", | |
4653 | .iu_version = 0x90 << 24, /* Impl 9, ver 0 */ | |
4654 | .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */ | |
4655 | .mmu_version = 0x10 << 24, | |
4656 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
4657 | .mmu_ctpr_mask = 0x007ffff0, |
4658 | .mmu_cxr_mask = 0x0000003f, | |
4659 | .mmu_sfsr_mask = 0xffffffff, | |
4660 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 BS |
4661 | }, |
4662 | { | |
4663 | .name = "LEON2", | |
4664 | .iu_version = 0xf2000000, | |
4665 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
4666 | .mmu_version = 0xf2000000, | |
4667 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
4668 | .mmu_ctpr_mask = 0x007ffff0, |
4669 | .mmu_cxr_mask = 0x0000003f, | |
4670 | .mmu_sfsr_mask = 0xffffffff, | |
4671 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 BS |
4672 | }, |
4673 | { | |
4674 | .name = "LEON3", | |
4675 | .iu_version = 0xf3000000, | |
4676 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
4677 | .mmu_version = 0xf3000000, | |
6d5f237a | 4678 | .mmu_bm = 0x00004000, |
3deaeab7 BS |
4679 | .mmu_ctpr_mask = 0x007ffff0, |
4680 | .mmu_cxr_mask = 0x0000003f, | |
4681 | .mmu_sfsr_mask = 0xffffffff, | |
4682 | .mmu_trcr_mask = 0xffffffff, | |
e0353fe2 | 4683 | }, |
62724a37 BS |
4684 | #endif |
4685 | }; | |
4686 | ||
aaed909a | 4687 | static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name) |
62724a37 | 4688 | { |
62724a37 BS |
4689 | unsigned int i; |
4690 | ||
62724a37 BS |
4691 | for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
4692 | if (strcasecmp(name, sparc_defs[i].name) == 0) { | |
aaed909a | 4693 | return &sparc_defs[i]; |
62724a37 BS |
4694 | } |
4695 | } | |
aaed909a | 4696 | return NULL; |
62724a37 BS |
4697 | } |
4698 | ||
4699 | void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) | |
4700 | { | |
4701 | unsigned int i; | |
4702 | ||
4703 | for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { | |
4704 | (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n", | |
4705 | sparc_defs[i].name, | |
4706 | sparc_defs[i].iu_version, | |
4707 | sparc_defs[i].fpu_version, | |
4708 | sparc_defs[i].mmu_version); | |
4709 | } | |
4710 | } | |
4711 | ||
7a3f1944 FB |
4712 | #define GET_FLAG(a,b) ((env->psr & a)?b:'-') |
4713 | ||
5fafdf24 | 4714 | void cpu_dump_state(CPUState *env, FILE *f, |
7fe48483 FB |
4715 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
4716 | int flags) | |
7a3f1944 | 4717 | { |
cf495bcf FB |
4718 | int i, x; |
4719 | ||
af7bf89b | 4720 | cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc); |
7fe48483 | 4721 | cpu_fprintf(f, "General Registers:\n"); |
cf495bcf | 4722 | for (i = 0; i < 4; i++) |
0f8a249a | 4723 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
7fe48483 | 4724 | cpu_fprintf(f, "\n"); |
cf495bcf | 4725 | for (; i < 8; i++) |
0f8a249a | 4726 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
7fe48483 | 4727 | cpu_fprintf(f, "\nCurrent Register Window:\n"); |
cf495bcf | 4728 | for (x = 0; x < 3; x++) { |
0f8a249a BS |
4729 | for (i = 0; i < 4; i++) |
4730 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", | |
4731 | (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i, | |
4732 | env->regwptr[i + x * 8]); | |
4733 | cpu_fprintf(f, "\n"); | |
4734 | for (; i < 8; i++) | |
4735 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", | |
4736 | (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i, | |
4737 | env->regwptr[i + x * 8]); | |
4738 | cpu_fprintf(f, "\n"); | |
cf495bcf | 4739 | } |
7fe48483 | 4740 | cpu_fprintf(f, "\nFloating Point Registers:\n"); |
e8af50a3 FB |
4741 | for (i = 0; i < 32; i++) { |
4742 | if ((i & 3) == 0) | |
7fe48483 FB |
4743 | cpu_fprintf(f, "%%f%02d:", i); |
4744 | cpu_fprintf(f, " %016lf", env->fpr[i]); | |
e8af50a3 | 4745 | if ((i & 3) == 3) |
7fe48483 | 4746 | cpu_fprintf(f, "\n"); |
e8af50a3 | 4747 | } |
ded3ab80 | 4748 | #ifdef TARGET_SPARC64 |
3299908c | 4749 | cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n", |
0f8a249a | 4750 | env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs); |
ded3ab80 | 4751 | cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n", |
0f8a249a BS |
4752 | env->cansave, env->canrestore, env->otherwin, env->wstate, |
4753 | env->cleanwin, NWINDOWS - 1 - env->cwp); | |
ded3ab80 | 4754 | #else |
7fe48483 | 4755 | cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env), |
0f8a249a BS |
4756 | GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), |
4757 | GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), | |
4758 | env->psrs?'S':'-', env->psrps?'P':'-', | |
4759 | env->psret?'E':'-', env->wim); | |
ded3ab80 | 4760 | #endif |
3475187d | 4761 | cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env)); |
7a3f1944 | 4762 | } |
edfcbd99 | 4763 | |
e80cfcfc | 4764 | #if defined(CONFIG_USER_ONLY) |
9b3c35e0 | 4765 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
edfcbd99 FB |
4766 | { |
4767 | return addr; | |
4768 | } | |
658138bc | 4769 | |
e80cfcfc | 4770 | #else |
af7bf89b FB |
4771 | extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot, |
4772 | int *access_index, target_ulong address, int rw, | |
6ebbf390 | 4773 | int mmu_idx); |
0fa85d43 | 4774 | |
9b3c35e0 | 4775 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
e80cfcfc | 4776 | { |
af7bf89b | 4777 | target_phys_addr_t phys_addr; |
e80cfcfc FB |
4778 | int prot, access_index; |
4779 | ||
9e31b9e2 BS |
4780 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, |
4781 | MMU_KERNEL_IDX) != 0) | |
4782 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, | |
4783 | 0, MMU_KERNEL_IDX) != 0) | |
6b1575b7 | 4784 | return -1; |
6c36d3fa BS |
4785 | if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED) |
4786 | return -1; | |
e80cfcfc FB |
4787 | return phys_addr; |
4788 | } | |
4789 | #endif | |
4790 | ||
658138bc FB |
4791 | void helper_flush(target_ulong addr) |
4792 | { | |
4793 | addr &= ~7; | |
4794 | tb_invalidate_page_range(addr, addr + 8); | |
4795 | } |