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[qemu.git] / target-sparc / translate.c
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7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
7a3f1944
FB		 23 TODO-list:
24
3475187d 25 Rest of V9 instructions, VIS instructions
bd497938 26 NPC/PC static optimisations (use JUMP_TB when possible)
7a3f1944 27 Optimize synthetic instructions
bd497938 28*/
7a3f1944
FB		 29
30#include <stdarg.h>
31#include <stdlib.h>
32#include <stdio.h>
33#include <string.h>
34#include <inttypes.h>
35
36#include "cpu.h"
37#include "exec-all.h"
38#include "disas.h"
1a2fb1c0 39#include "helper.h"
57fec1fe 40#include "tcg-op.h"
7a3f1944
FB		 41
42#define DEBUG_DISAS
43
72cbca10
FB		 44#define DYNAMIC_PC 1 /* dynamic pc value */
45#define JUMP_PC 2 /* dynamic pc value which takes only two values
46 according to jump_pc[T2] */
47
1a2fb1c0 48/* global register indexes */
d9bdab86 49static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
48d5c82b 50static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
6ae20372 51static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
dc99a3f2
BS		 52#ifdef TARGET_SPARC64
53static TCGv cpu_xcc;
54#endif
1a2fb1c0 55/* local register indexes (only used inside old micro ops) */
8911f501 56static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
1a2fb1c0 57
7a3f1944 58typedef struct DisasContext {
0f8a249a
BS		 59 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
60 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 61 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 62 int is_br;
e8af50a3 63 int mem_idx;
a80dde08 64 int fpu_enabled;
cf495bcf 65 struct TranslationBlock *tb;
7a3f1944
FB		 66} DisasContext;
67
7a3f1944
FB		 68extern FILE *logfile;
69extern int loglevel;
70
3475187d 71// This function uses non-native bit order
7a3f1944
FB		 72#define GET_FIELD(X, FROM, TO) \
73 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
74
3475187d
FB		 75// This function uses the order in the manuals, i.e. bit 0 is 2^0
76#define GET_FIELD_SP(X, FROM, TO) \
77 GET_FIELD(X, 31 - (TO), 31 - (FROM))
78
79#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 80#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 81
82#ifdef TARGET_SPARC64
19f329ad 83#define FFPREG(r) (r)
0387d928 84#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 85#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 86#else
19f329ad 87#define FFPREG(r) (r)
c185970a 88#define DFPREG(r) (r & 0x1e)
1f587329 89#define QFPREG(r) (r & 0x1c)
3475187d
FB		 90#endif
91
92static int sign_extend(int x, int len)
93{
94 len = 32 - len;
95 return (x << len) >> len;
96}
97
7a3f1944
FB		 98#define IS_IMM (insn & (1<<13))
99
ff07ec83
BS		 100/* floating point registers moves */
101static void gen_op_load_fpr_FT0(unsigned int src)
102{
8911f501
BS		 103 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
104 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
3475187d 105}
ff07ec83
BS		 106
107static void gen_op_load_fpr_FT1(unsigned int src)
108{
8911f501
BS		 109 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
110 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
e8af50a3
FB		 111}
112
ff07ec83
BS		 113static void gen_op_store_FT0_fpr(unsigned int dst)
114{
8911f501
BS		 115 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
116 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
ff07ec83
BS		 117}
118
119static void gen_op_load_fpr_DT0(unsigned int src)
120{
8911f501
BS		 121 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
122 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
123 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
124 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
ff07ec83
BS		 125}
126
127static void gen_op_load_fpr_DT1(unsigned int src)
128{
8911f501
BS		 129 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
130 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.upper));
131 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
132 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.lower));
ff07ec83
BS		 133}
134
135static void gen_op_store_DT0_fpr(unsigned int dst)
136{
8911f501
BS		 137 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
138 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
139 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
140 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
ff07ec83
BS		 141}
142
143#ifdef CONFIG_USER_ONLY
144static void gen_op_load_fpr_QT0(unsigned int src)
145{
8911f501
BS		 146 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
147 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
148 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
149 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
150 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
151 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
152 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
153 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
ff07ec83
BS		 154}
155
156static void gen_op_load_fpr_QT1(unsigned int src)
157{
8911f501
BS		 158 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
159 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost));
160 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
161 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper));
162 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
163 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower));
164 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
165 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest));
ff07ec83
BS		 166}
167
168static void gen_op_store_QT0_fpr(unsigned int dst)
169{
8911f501
BS		 170 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
171 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
172 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
173 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
174 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
175 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
176 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
177 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
ff07ec83 178}
1f587329
BS		 179#endif
180
81ad8ba2
BS		 181/* moves */
182#ifdef CONFIG_USER_ONLY
3475187d 183#define supervisor(dc) 0
81ad8ba2 184#ifdef TARGET_SPARC64
e9ebed4d 185#define hypervisor(dc) 0
81ad8ba2 186#endif
3475187d 187#else
6f27aba6 188#define supervisor(dc) (dc->mem_idx >= 1)
81ad8ba2
BS		 189#ifdef TARGET_SPARC64
190#define hypervisor(dc) (dc->mem_idx == 2)
6f27aba6 191#else
3475187d 192#endif
81ad8ba2
BS		 193#endif
194
1a2fb1c0 195#ifdef TARGET_ABI32
8911f501 196#define ABI32_MASK(addr) tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
1a2fb1c0
BS		 197#else
198#define ABI32_MASK(addr)
199#endif
3391c818 200
1a2fb1c0 201static inline void gen_movl_reg_TN(int reg, TCGv tn)
81ad8ba2 202{
1a2fb1c0
BS		 203 if (reg == 0)
204 tcg_gen_movi_tl(tn, 0);
205 else if (reg < 8)
f5069b26 206 tcg_gen_mov_tl(tn, cpu_gregs[reg]);
1a2fb1c0 207 else {
1a2fb1c0 208 tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
81ad8ba2
BS		 209 }
210}
211
1a2fb1c0 212static inline void gen_movl_TN_reg(int reg, TCGv tn)
81ad8ba2 213{
1a2fb1c0
BS		 214 if (reg == 0)
215 return;
216 else if (reg < 8)
f5069b26 217 tcg_gen_mov_tl(cpu_gregs[reg], tn);
1a2fb1c0 218 else {
1a2fb1c0 219 tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
81ad8ba2
BS		 220 }
221}
222
5fafdf24 223static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 224 target_ulong pc, target_ulong npc)
225{
226 TranslationBlock *tb;
227
228 tb = s->tb;
229 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
230 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
231 /* jump to same page: we can use a direct jump */
57fec1fe 232 tcg_gen_goto_tb(tb_num);
2f5680ee
BS		 233 tcg_gen_movi_tl(cpu_pc, pc);
234 tcg_gen_movi_tl(cpu_npc, npc);
57fec1fe 235 tcg_gen_exit_tb((long)tb + tb_num);
6e256c93
FB		 236 } else {
237 /* jump to another page: currently not optimized */
2f5680ee
BS		 238 tcg_gen_movi_tl(cpu_pc, pc);
239 tcg_gen_movi_tl(cpu_npc, npc);
57fec1fe 240 tcg_gen_exit_tb(0);
6e256c93
FB		 241 }
242}
243
19f329ad
BS		 244// XXX suboptimal
245static inline void gen_mov_reg_N(TCGv reg, TCGv src)
246{
8911f501 247 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 248 tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
19f329ad
BS		 249 tcg_gen_andi_tl(reg, reg, 0x1);
250}
251
252static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
253{
8911f501 254 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 255 tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
19f329ad
BS		 256 tcg_gen_andi_tl(reg, reg, 0x1);
257}
258
259static inline void gen_mov_reg_V(TCGv reg, TCGv src)
260{
8911f501 261 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 262 tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
19f329ad
BS		 263 tcg_gen_andi_tl(reg, reg, 0x1);
264}
265
266static inline void gen_mov_reg_C(TCGv reg, TCGv src)
267{
8911f501 268 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 269 tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
19f329ad
BS		 270 tcg_gen_andi_tl(reg, reg, 0x1);
271}
272
ce5b3c3d 273static inline void gen_cc_clear_icc(void)
dc99a3f2
BS		 274{
275 tcg_gen_movi_i32(cpu_psr, 0);
ce5b3c3d
BS		 276}
277
dc99a3f2 278#ifdef TARGET_SPARC64
ce5b3c3d
BS		 279static inline void gen_cc_clear_xcc(void)
280{
dc99a3f2 281 tcg_gen_movi_i32(cpu_xcc, 0);
dc99a3f2 282}
ce5b3c3d 283#endif
dc99a3f2
BS		 284
285/* old op:
286 if (!T0)
287 env->psr |= PSR_ZERO;
288 if ((int32_t) T0 < 0)
289 env->psr |= PSR_NEG;
290*/
ce5b3c3d 291static inline void gen_cc_NZ_icc(TCGv dst)
dc99a3f2 292{
8911f501 293 TCGv r_temp;
dc99a3f2 294 int l1, l2;
dc99a3f2
BS		 295
296 l1 = gen_new_label();
297 l2 = gen_new_label();
8911f501
BS		 298 r_temp = tcg_temp_new(TCG_TYPE_TL);
299 tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
300 tcg_gen_brcond_tl(TCG_COND_NE, r_temp, tcg_const_tl(0), l1);
dc99a3f2
BS		 301 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
302 gen_set_label(l1);
bdf46ea2 303 tcg_gen_ext_i32_tl(r_temp, dst);
8911f501 304 tcg_gen_brcond_tl(TCG_COND_GE, r_temp, tcg_const_tl(0), l2);
dc99a3f2
BS		 305 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
306 gen_set_label(l2);
ce5b3c3d
BS		 307}
308
dc99a3f2 309#ifdef TARGET_SPARC64
ce5b3c3d
BS		 310static inline void gen_cc_NZ_xcc(TCGv dst)
311{
312 int l1, l2;
313
314 l1 = gen_new_label();
315 l2 = gen_new_label();
316 tcg_gen_brcond_tl(TCG_COND_NE, dst, tcg_const_tl(0), l1);
317 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
318 gen_set_label(l1);
319 tcg_gen_brcond_tl(TCG_COND_GE, dst, tcg_const_tl(0), l2);
320 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
321 gen_set_label(l2);
dc99a3f2 322}
ce5b3c3d 323#endif
dc99a3f2
BS		 324
325/* old op:
326 if (T0 < src1)
327 env->psr |= PSR_CARRY;
328*/
ce5b3c3d 329static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
dc99a3f2 330{
8911f501 331 TCGv r_temp;
dc99a3f2
BS		 332 int l1;
333
334 l1 = gen_new_label();
8911f501
BS		 335 r_temp = tcg_temp_new(TCG_TYPE_TL);
336 tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
337 tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
dc99a3f2
BS		 338 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
339 gen_set_label(l1);
ce5b3c3d
BS		 340}
341
dc99a3f2 342#ifdef TARGET_SPARC64
ce5b3c3d
BS		 343static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
344{
345 int l1;
dc99a3f2 346
ce5b3c3d
BS		 347 l1 = gen_new_label();
348 tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
349 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
350 gen_set_label(l1);
dc99a3f2 351}
ce5b3c3d 352#endif
dc99a3f2
BS		 353
354/* old op:
355 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
356 env->psr |= PSR_OVF;
357*/
ce5b3c3d 358static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 359{
0425bee5 360 TCGv r_temp;
dc99a3f2
BS		 361
362 r_temp = tcg_temp_new(TCG_TYPE_TL);
dc99a3f2
BS		 363 tcg_gen_xor_tl(r_temp, src1, src2);
364 tcg_gen_xori_tl(r_temp, r_temp, -1);
0425bee5
BS		 365 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
366 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
367 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
653ccb80
BS		 368 tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
369 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
370 tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
ce5b3c3d
BS		 371}
372
dc99a3f2 373#ifdef TARGET_SPARC64
ce5b3c3d
BS		 374static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
375{
376 TCGv r_temp;
ce5b3c3d
BS		 377
378 r_temp = tcg_temp_new(TCG_TYPE_TL);
379 tcg_gen_xor_tl(r_temp, src1, src2);
380 tcg_gen_xori_tl(r_temp, r_temp, -1);
381 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
382 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
383 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
653ccb80
BS		 384 tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
385 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
386 tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
dc99a3f2 387}
ce5b3c3d 388#endif
dc99a3f2
BS		 389
390static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
391{
0425bee5 392 TCGv r_temp;
dc99a3f2
BS		 393 int l1;
394
395 l1 = gen_new_label();
396
397 r_temp = tcg_temp_new(TCG_TYPE_TL);
dc99a3f2
BS		 398 tcg_gen_xor_tl(r_temp, src1, src2);
399 tcg_gen_xori_tl(r_temp, r_temp, -1);
0425bee5
BS		 400 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
401 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
402 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
8911f501 403 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
2f5680ee 404 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
dc99a3f2 405 gen_set_label(l1);
dc99a3f2
BS		 406}
407
408static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
409{
410 int l1;
dc99a3f2
BS		 411
412 l1 = gen_new_label();
0425bee5
BS		 413 tcg_gen_or_tl(cpu_tmp0, src1, src2);
414 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
415 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
dc99a3f2
BS		 416 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
417 gen_set_label(l1);
418}
419
420static inline void gen_tag_tv(TCGv src1, TCGv src2)
421{
422 int l1;
dc99a3f2
BS		 423
424 l1 = gen_new_label();
0425bee5
BS		 425 tcg_gen_or_tl(cpu_tmp0, src1, src2);
426 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
427 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
2f5680ee 428 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
dc99a3f2
BS		 429 gen_set_label(l1);
430}
431
4af984a7 432static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 433{
4af984a7 434 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 435 tcg_gen_mov_tl(cpu_cc_src2, src2);
4af984a7 436 tcg_gen_add_tl(dst, src1, src2);
ba28189b 437 tcg_gen_mov_tl(cpu_cc_dst, dst);
ce5b3c3d 438 gen_cc_clear_icc();
ba28189b
BS		 439 gen_cc_NZ_icc(cpu_cc_dst);
440 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
441 gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d
BS		 442#ifdef TARGET_SPARC64
443 gen_cc_clear_xcc();
ba28189b
BS		 444 gen_cc_NZ_xcc(cpu_cc_dst);
445 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
446 gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 447#endif
dc99a3f2
BS		 448}
449
4af984a7 450static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 451{
4af984a7 452 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 453 tcg_gen_mov_tl(cpu_cc_src2, src2);
dc99a3f2 454 gen_mov_reg_C(cpu_tmp0, cpu_psr);
4af984a7 455 tcg_gen_add_tl(dst, src1, cpu_tmp0);
ce5b3c3d 456 gen_cc_clear_icc();
4af984a7 457 gen_cc_C_add_icc(dst, cpu_cc_src);
ce5b3c3d
BS		 458#ifdef TARGET_SPARC64
459 gen_cc_clear_xcc();
4af984a7 460 gen_cc_C_add_xcc(dst, cpu_cc_src);
ce5b3c3d 461#endif
6f551262 462 tcg_gen_add_tl(dst, dst, cpu_cc_src2);
ba28189b
BS		 463 tcg_gen_mov_tl(cpu_cc_dst, dst);
464 gen_cc_NZ_icc(cpu_cc_dst);
465 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
466 gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 467#ifdef TARGET_SPARC64
ba28189b
BS		 468 gen_cc_NZ_xcc(cpu_cc_dst);
469 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
470 gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 471#endif
dc99a3f2
BS		 472}
473
4af984a7 474static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 475{
4af984a7 476 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 477 tcg_gen_mov_tl(cpu_cc_src2, src2);
4af984a7 478 tcg_gen_add_tl(dst, src1, src2);
ba28189b 479 tcg_gen_mov_tl(cpu_cc_dst, dst);
ce5b3c3d 480 gen_cc_clear_icc();
ba28189b
BS		 481 gen_cc_NZ_icc(cpu_cc_dst);
482 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
483 gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
6f551262 484 gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
ce5b3c3d
BS		 485#ifdef TARGET_SPARC64
486 gen_cc_clear_xcc();
ba28189b
BS		 487 gen_cc_NZ_xcc(cpu_cc_dst);
488 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
489 gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 490#endif
dc99a3f2
BS		 491}
492
4af984a7 493static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 494{
4af984a7 495 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262
BS		 496 tcg_gen_mov_tl(cpu_cc_src2, src2);
497 gen_tag_tv(cpu_cc_src, cpu_cc_src2);
4af984a7 498 tcg_gen_add_tl(dst, src1, src2);
ba28189b 499 tcg_gen_mov_tl(cpu_cc_dst, dst);
6f551262 500 gen_add_tv(dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 501 gen_cc_clear_icc();
ba28189b
BS		 502 gen_cc_NZ_icc(cpu_cc_dst);
503 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
ce5b3c3d
BS		 504#ifdef TARGET_SPARC64
505 gen_cc_clear_xcc();
ba28189b
BS		 506 gen_cc_NZ_xcc(cpu_cc_dst);
507 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
508 gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 509#endif
dc99a3f2
BS		 510}
511
512/* old op:
513 if (src1 < T1)
514 env->psr |= PSR_CARRY;
515*/
ce5b3c3d 516static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
dc99a3f2 517{
8911f501 518 TCGv r_temp1, r_temp2;
dc99a3f2
BS		 519 int l1;
520
521 l1 = gen_new_label();
8911f501
BS		 522 r_temp1 = tcg_temp_new(TCG_TYPE_TL);
523 r_temp2 = tcg_temp_new(TCG_TYPE_TL);
524 tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
525 tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
526 tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
dc99a3f2
BS		 527 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
528 gen_set_label(l1);
ce5b3c3d
BS		 529}
530
dc99a3f2 531#ifdef TARGET_SPARC64
ce5b3c3d
BS		 532static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
533{
534 int l1;
dc99a3f2 535
ce5b3c3d
BS		 536 l1 = gen_new_label();
537 tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
538 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
539 gen_set_label(l1);
dc99a3f2 540}
ce5b3c3d 541#endif
dc99a3f2
BS		 542
543/* old op:
544 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
545 env->psr |= PSR_OVF;
546*/
ce5b3c3d 547static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 548{
0425bee5 549 TCGv r_temp;
dc99a3f2
BS		 550
551 r_temp = tcg_temp_new(TCG_TYPE_TL);
dc99a3f2 552 tcg_gen_xor_tl(r_temp, src1, src2);
0425bee5
BS		 553 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
554 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
555 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
653ccb80
BS		 556 tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
557 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
558 tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
ce5b3c3d
BS		 559}
560
dc99a3f2 561#ifdef TARGET_SPARC64
ce5b3c3d
BS		 562static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
563{
564 TCGv r_temp;
ce5b3c3d
BS		 565
566 r_temp = tcg_temp_new(TCG_TYPE_TL);
567 tcg_gen_xor_tl(r_temp, src1, src2);
568 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
569 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
570 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
653ccb80
BS		 571 tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
572 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
573 tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
dc99a3f2 574}
ce5b3c3d 575#endif
dc99a3f2
BS		 576
577static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
578{
0425bee5 579 TCGv r_temp;
dc99a3f2
BS		 580 int l1;
581
582 l1 = gen_new_label();
583
584 r_temp = tcg_temp_new(TCG_TYPE_TL);
dc99a3f2 585 tcg_gen_xor_tl(r_temp, src1, src2);
0425bee5
BS		 586 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
587 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
588 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
8911f501 589 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
2f5680ee 590 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
dc99a3f2 591 gen_set_label(l1);
dc99a3f2
BS		 592}
593
4af984a7 594static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 595{
4af984a7 596 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 597 tcg_gen_mov_tl(cpu_cc_src2, src2);
4af984a7 598 tcg_gen_sub_tl(dst, src1, src2);
ba28189b 599 tcg_gen_mov_tl(cpu_cc_dst, dst);
ce5b3c3d 600 gen_cc_clear_icc();
ba28189b 601 gen_cc_NZ_icc(cpu_cc_dst);
6f551262 602 gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
ba28189b 603 gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d
BS		 604#ifdef TARGET_SPARC64
605 gen_cc_clear_xcc();
ba28189b 606 gen_cc_NZ_xcc(cpu_cc_dst);
6f551262 607 gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
ba28189b 608 gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 609#endif
dc99a3f2
BS		 610}
611
4af984a7 612static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 613{
4af984a7 614 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 615 tcg_gen_mov_tl(cpu_cc_src2, src2);
dc99a3f2 616 gen_mov_reg_C(cpu_tmp0, cpu_psr);
4af984a7 617 tcg_gen_sub_tl(dst, src1, cpu_tmp0);
ce5b3c3d 618 gen_cc_clear_icc();
4af984a7 619 gen_cc_C_sub_icc(dst, cpu_cc_src);
ce5b3c3d
BS		 620#ifdef TARGET_SPARC64
621 gen_cc_clear_xcc();
4af984a7 622 gen_cc_C_sub_xcc(dst, cpu_cc_src);
ce5b3c3d 623#endif
6f551262 624 tcg_gen_sub_tl(dst, dst, cpu_cc_src2);
ba28189b
BS		 625 tcg_gen_mov_tl(cpu_cc_dst, dst);
626 gen_cc_NZ_icc(cpu_cc_dst);
627 gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
628 gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 629#ifdef TARGET_SPARC64
ba28189b
BS		 630 gen_cc_NZ_xcc(cpu_cc_dst);
631 gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
632 gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 633#endif
dc99a3f2
BS		 634}
635
4af984a7 636static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 637{
4af984a7 638 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 639 tcg_gen_mov_tl(cpu_cc_src2, src2);
4af984a7 640 tcg_gen_sub_tl(dst, src1, src2);
ba28189b 641 tcg_gen_mov_tl(cpu_cc_dst, dst);
ce5b3c3d 642 gen_cc_clear_icc();
ba28189b 643 gen_cc_NZ_icc(cpu_cc_dst);
6f551262 644 gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
ba28189b 645 gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
6f551262 646 gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
ce5b3c3d
BS		 647#ifdef TARGET_SPARC64
648 gen_cc_clear_xcc();
ba28189b 649 gen_cc_NZ_xcc(cpu_cc_dst);
6f551262 650 gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
ba28189b 651 gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 652#endif
dc99a3f2
BS		 653}
654
4af984a7 655static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 656{
4af984a7 657 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262
BS		 658 tcg_gen_mov_tl(cpu_cc_src2, src2);
659 gen_tag_tv(cpu_cc_src, cpu_cc_src2);
4af984a7 660 tcg_gen_sub_tl(dst, src1, src2);
ba28189b 661 tcg_gen_mov_tl(cpu_cc_dst, dst);
6f551262 662 gen_sub_tv(dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 663 gen_cc_clear_icc();
ba28189b 664 gen_cc_NZ_icc(cpu_cc_dst);
6f551262 665 gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
ce5b3c3d
BS		 666#ifdef TARGET_SPARC64
667 gen_cc_clear_xcc();
ba28189b 668 gen_cc_NZ_xcc(cpu_cc_dst);
6f551262 669 gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
ba28189b 670 gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 671#endif
dc99a3f2
BS		 672}
673
4af984a7 674static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
d9bdab86 675{
7127fe84 676 TCGv r_temp, r_temp2;
6f551262 677 int l1;
d9bdab86
BS		 678
679 l1 = gen_new_label();
d9bdab86 680 r_temp = tcg_temp_new(TCG_TYPE_TL);
7127fe84 681 r_temp2 = tcg_temp_new(TCG_TYPE_I32);
d9bdab86
BS		 682
683 /* old op:
684 if (!(env->y & 1))
685 T1 = 0;
686 */
6f551262 687 tcg_gen_mov_tl(cpu_cc_src, src1);
7127fe84
BS		 688 tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
689 tcg_gen_trunc_tl_i32(r_temp2, r_temp);
690 tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
4af984a7 691 tcg_gen_mov_tl(cpu_cc_src2, src2);
6f551262 692 tcg_gen_brcond_i32(TCG_COND_NE, r_temp2, tcg_const_i32(0), l1);
d9bdab86 693 tcg_gen_movi_tl(cpu_cc_src2, 0);
6f551262 694 gen_set_label(l1);
d9bdab86
BS		 695
696 // b2 = T0 & 1;
697 // env->y = (b2 << 31) | (env->y >> 1);
6f551262 698 tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src);
7127fe84
BS		 699 tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
700 tcg_gen_shli_i32(r_temp2, r_temp2, 31);
8911f501
BS		 701 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
702 tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
7127fe84 703 tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
8911f501 704 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
d9bdab86
BS		 705
706 // b1 = N ^ V;
707 gen_mov_reg_N(cpu_tmp0, cpu_psr);
708 gen_mov_reg_V(r_temp, cpu_psr);
709 tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
710
711 // T0 = (b1 << 31) | (T0 >> 1);
712 // src1 = T0;
713 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
6f551262 714 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
d9bdab86
BS		 715 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
716
717 /* do addition and update flags */
4af984a7 718 tcg_gen_add_tl(dst, cpu_cc_src, cpu_cc_src2);
ba28189b 719 tcg_gen_mov_tl(cpu_cc_dst, dst);
d9bdab86 720
ce5b3c3d 721 gen_cc_clear_icc();
ba28189b
BS		 722 gen_cc_NZ_icc(cpu_cc_dst);
723 gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
724 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
d9bdab86
BS		 725}
726
4af984a7 727static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
8879d139
BS		 728{
729 TCGv r_temp, r_temp2;
730
731 r_temp = tcg_temp_new(TCG_TYPE_I64);
732 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
733
4af984a7
BS		 734 tcg_gen_extu_tl_i64(r_temp, src2);
735 tcg_gen_extu_tl_i64(r_temp2, src1);
8879d139
BS		 736 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
737
738 tcg_gen_shri_i64(r_temp, r_temp2, 32);
739 tcg_gen_trunc_i64_i32(r_temp, r_temp);
740 tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
741#ifdef TARGET_SPARC64
4af984a7 742 tcg_gen_mov_i64(dst, r_temp2);
8879d139 743#else
4af984a7 744 tcg_gen_trunc_i64_tl(dst, r_temp2);
8879d139 745#endif
8879d139
BS		 746}
747
4af984a7 748static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
8879d139
BS		 749{
750 TCGv r_temp, r_temp2;
751
752 r_temp = tcg_temp_new(TCG_TYPE_I64);
753 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
754
4af984a7
BS		 755 tcg_gen_ext_tl_i64(r_temp, src2);
756 tcg_gen_ext_tl_i64(r_temp2, src1);
8879d139
BS		 757 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
758
759 tcg_gen_shri_i64(r_temp, r_temp2, 32);
760 tcg_gen_trunc_i64_i32(r_temp, r_temp);
761 tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
762#ifdef TARGET_SPARC64
4af984a7 763 tcg_gen_mov_i64(dst, r_temp2);
8879d139 764#else
4af984a7 765 tcg_gen_trunc_i64_tl(dst, r_temp2);
8879d139 766#endif
8879d139
BS		 767}
768
1a7b60e7 769#ifdef TARGET_SPARC64
8911f501 770static inline void gen_trap_ifdivzero_tl(TCGv divisor)
1a7b60e7
BS		 771{
772 int l1;
773
774 l1 = gen_new_label();
8911f501 775 tcg_gen_brcond_tl(TCG_COND_NE, divisor, tcg_const_tl(0), l1);
2f5680ee 776 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_DIV_ZERO));
1a7b60e7
BS		 777 gen_set_label(l1);
778}
779
4af984a7 780static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
1a7b60e7
BS		 781{
782 int l1, l2;
783
784 l1 = gen_new_label();
785 l2 = gen_new_label();
6f551262
BS		 786 tcg_gen_mov_tl(cpu_cc_src, src1);
787 tcg_gen_mov_tl(cpu_cc_src2, src2);
4af984a7 788 gen_trap_ifdivzero_tl(src2);
6f551262
BS		 789 tcg_gen_brcond_tl(TCG_COND_NE, cpu_cc_src, tcg_const_tl(INT64_MIN), l1);
790 tcg_gen_brcond_tl(TCG_COND_NE, cpu_cc_src2, tcg_const_tl(-1), l1);
4af984a7 791 tcg_gen_movi_i64(dst, INT64_MIN);
06b3e1b3 792 tcg_gen_br(l2);
1a7b60e7 793 gen_set_label(l1);
6f551262 794 tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
1a7b60e7
BS		 795 gen_set_label(l2);
796}
797#endif
798
4af984a7 799static inline void gen_op_div_cc(TCGv dst)
dc99a3f2
BS		 800{
801 int l1;
dc99a3f2 802
ba28189b 803 tcg_gen_mov_tl(cpu_cc_dst, dst);
ce5b3c3d 804 gen_cc_clear_icc();
ba28189b 805 gen_cc_NZ_icc(cpu_cc_dst);
dc99a3f2 806 l1 = gen_new_label();
3b89f26c
BS		 807 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2));
808 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
dc99a3f2
BS		 809 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
810 gen_set_label(l1);
811}
812
4af984a7 813static inline void gen_op_logic_cc(TCGv dst)
dc99a3f2 814{
ba28189b
BS		 815 tcg_gen_mov_tl(cpu_cc_dst, dst);
816
ce5b3c3d 817 gen_cc_clear_icc();
ba28189b 818 gen_cc_NZ_icc(cpu_cc_dst);
ce5b3c3d
BS		 819#ifdef TARGET_SPARC64
820 gen_cc_clear_xcc();
ba28189b 821 gen_cc_NZ_xcc(cpu_cc_dst);
ce5b3c3d 822#endif
dc99a3f2
BS		 823}
824
19f329ad
BS		 825// 1
826static inline void gen_op_eval_ba(TCGv dst)
827{
828 tcg_gen_movi_tl(dst, 1);
829}
830
831// Z
832static inline void gen_op_eval_be(TCGv dst, TCGv src)
833{
834 gen_mov_reg_Z(dst, src);
835}
836
837// Z | (N ^ V)
838static inline void gen_op_eval_ble(TCGv dst, TCGv src)
839{
0425bee5 840 gen_mov_reg_N(cpu_tmp0, src);
19f329ad 841 gen_mov_reg_V(dst, src);
0425bee5
BS		 842 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
843 gen_mov_reg_Z(cpu_tmp0, src);
844 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 845}
846
847// N ^ V
848static inline void gen_op_eval_bl(TCGv dst, TCGv src)
849{
0425bee5 850 gen_mov_reg_V(cpu_tmp0, src);
19f329ad 851 gen_mov_reg_N(dst, src);
0425bee5 852 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 853}
854
855// C | Z
856static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
857{
0425bee5 858 gen_mov_reg_Z(cpu_tmp0, src);
19f329ad 859 gen_mov_reg_C(dst, src);
0425bee5 860 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 861}
862
863// C
864static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
865{
866 gen_mov_reg_C(dst, src);
867}
868
869// V
870static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
871{
872 gen_mov_reg_V(dst, src);
873}
874
875// 0
876static inline void gen_op_eval_bn(TCGv dst)
877{
878 tcg_gen_movi_tl(dst, 0);
879}
880
881// N
882static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
883{
884 gen_mov_reg_N(dst, src);
885}
886
887// !Z
888static inline void gen_op_eval_bne(TCGv dst, TCGv src)
889{
890 gen_mov_reg_Z(dst, src);
891 tcg_gen_xori_tl(dst, dst, 0x1);
892}
893
894// !(Z | (N ^ V))
895static inline void gen_op_eval_bg(TCGv dst, TCGv src)
896{
0425bee5 897 gen_mov_reg_N(cpu_tmp0, src);
19f329ad 898 gen_mov_reg_V(dst, src);
0425bee5
BS		 899 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
900 gen_mov_reg_Z(cpu_tmp0, src);
901 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 902 tcg_gen_xori_tl(dst, dst, 0x1);
903}
904
905// !(N ^ V)
906static inline void gen_op_eval_bge(TCGv dst, TCGv src)
907{
0425bee5 908 gen_mov_reg_V(cpu_tmp0, src);
19f329ad 909 gen_mov_reg_N(dst, src);
0425bee5 910 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 911 tcg_gen_xori_tl(dst, dst, 0x1);
912}
913
914// !(C | Z)
915static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
916{
0425bee5 917 gen_mov_reg_Z(cpu_tmp0, src);
19f329ad 918 gen_mov_reg_C(dst, src);
0425bee5 919 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 920 tcg_gen_xori_tl(dst, dst, 0x1);
921}
922
923// !C
924static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
925{
926 gen_mov_reg_C(dst, src);
927 tcg_gen_xori_tl(dst, dst, 0x1);
928}
929
930// !N
931static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
932{
933 gen_mov_reg_N(dst, src);
934 tcg_gen_xori_tl(dst, dst, 0x1);
935}
936
937// !V
938static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
939{
940 gen_mov_reg_V(dst, src);
941 tcg_gen_xori_tl(dst, dst, 0x1);
942}
943
944/*
945 FPSR bit field FCC1 | FCC0:
946 0 =
947 1 <
948 2 >
949 3 unordered
950*/
951static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
952 unsigned int fcc_offset)
953{
8911f501 954 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 955 tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset);
19f329ad
BS		 956 tcg_gen_andi_tl(reg, reg, 0x1);
957}
958
959static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
960 unsigned int fcc_offset)
961{
8911f501 962 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 963 tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset);
19f329ad
BS		 964 tcg_gen_andi_tl(reg, reg, 0x1);
965}
966
967// !0: FCC0 | FCC1
968static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
969 unsigned int fcc_offset)
970{
19f329ad 971 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 972 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
973 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 974}
975
976// 1 or 2: FCC0 ^ FCC1
977static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
978 unsigned int fcc_offset)
979{
19f329ad 980 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 981 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
982 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 983}
984
985// 1 or 3: FCC0
986static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
987 unsigned int fcc_offset)
988{
989 gen_mov_reg_FCC0(dst, src, fcc_offset);
990}
991
992// 1: FCC0 & !FCC1
993static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
994 unsigned int fcc_offset)
995{
19f329ad 996 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 997 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
998 tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
999 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1000}
1001
1002// 2 or 3: FCC1
1003static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1004 unsigned int fcc_offset)
1005{
1006 gen_mov_reg_FCC1(dst, src, fcc_offset);
1007}
1008
1009// 2: !FCC0 & FCC1
1010static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1011 unsigned int fcc_offset)
1012{
19f329ad
BS		 1013 gen_mov_reg_FCC0(dst, src, fcc_offset);
1014 tcg_gen_xori_tl(dst, dst, 0x1);
0425bee5
BS		 1015 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1016 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1017}
1018
1019// 3: FCC0 & FCC1
1020static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1021 unsigned int fcc_offset)
1022{
19f329ad 1023 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1024 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1025 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1026}
1027
1028// 0: !(FCC0 | FCC1)
1029static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1030 unsigned int fcc_offset)
1031{
19f329ad 1032 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1033 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1034 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1035 tcg_gen_xori_tl(dst, dst, 0x1);
1036}
1037
1038// 0 or 3: !(FCC0 ^ FCC1)
1039static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1040 unsigned int fcc_offset)
1041{
19f329ad 1042 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1043 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1044 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1045 tcg_gen_xori_tl(dst, dst, 0x1);
1046}
1047
1048// 0 or 2: !FCC0
1049static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1050 unsigned int fcc_offset)
1051{
1052 gen_mov_reg_FCC0(dst, src, fcc_offset);
1053 tcg_gen_xori_tl(dst, dst, 0x1);
1054}
1055
1056// !1: !(FCC0 & !FCC1)
1057static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1058 unsigned int fcc_offset)
1059{
19f329ad 1060 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1061 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1062 tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1063 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1064 tcg_gen_xori_tl(dst, dst, 0x1);
1065}
1066
1067// 0 or 1: !FCC1
1068static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1069 unsigned int fcc_offset)
1070{
1071 gen_mov_reg_FCC1(dst, src, fcc_offset);
1072 tcg_gen_xori_tl(dst, dst, 0x1);
1073}
1074
1075// !2: !(!FCC0 & FCC1)
1076static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1077 unsigned int fcc_offset)
1078{
19f329ad
BS		 1079 gen_mov_reg_FCC0(dst, src, fcc_offset);
1080 tcg_gen_xori_tl(dst, dst, 0x1);
0425bee5
BS		 1081 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1082 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1083 tcg_gen_xori_tl(dst, dst, 0x1);
1084}
1085
1086// !3: !(FCC0 & FCC1)
1087static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1088 unsigned int fcc_offset)
1089{
19f329ad 1090 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1091 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1092 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1093 tcg_gen_xori_tl(dst, dst, 0x1);
1094}
1095
46525e1f 1096static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
19f329ad 1097 target_ulong pc2, TCGv r_cond)
83469015
FB		 1098{
1099 int l1;
1100
1101 l1 = gen_new_label();
1102
0425bee5 1103 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
83469015 1104
6e256c93 1105 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 1106
1107 gen_set_label(l1);
6e256c93 1108 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 1109}
1110
46525e1f 1111static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
19f329ad 1112 target_ulong pc2, TCGv r_cond)
83469015
FB		 1113{
1114 int l1;
1115
1116 l1 = gen_new_label();
1117
0425bee5 1118 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
83469015 1119
6e256c93 1120 gen_goto_tb(dc, 0, pc2, pc1);
83469015
FB		 1121
1122 gen_set_label(l1);
6e256c93 1123 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
83469015
FB		 1124}
1125
19f329ad
BS		 1126static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1127 TCGv r_cond)
83469015
FB		 1128{
1129 int l1, l2;
1130
1131 l1 = gen_new_label();
1132 l2 = gen_new_label();
19f329ad 1133
0425bee5 1134 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
83469015 1135
2f5680ee 1136 tcg_gen_movi_tl(cpu_npc, npc1);
06b3e1b3 1137 tcg_gen_br(l2);
83469015
FB		 1138
1139 gen_set_label(l1);
2f5680ee 1140 tcg_gen_movi_tl(cpu_npc, npc2);
83469015
FB		 1141 gen_set_label(l2);
1142}
1143
4af984a7
BS		 1144/* call this function before using the condition register as it may
1145 have been set for a jump */
1146static inline void flush_cond(DisasContext *dc, TCGv cond)
83469015
FB		 1147{
1148 if (dc->npc == JUMP_PC) {
4af984a7 1149 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
83469015
FB		 1150 dc->npc = DYNAMIC_PC;
1151 }
1152}
1153
4af984a7 1154static inline void save_npc(DisasContext *dc, TCGv cond)
72cbca10
FB		 1155{
1156 if (dc->npc == JUMP_PC) {
4af984a7 1157 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
72cbca10
FB		 1158 dc->npc = DYNAMIC_PC;
1159 } else if (dc->npc != DYNAMIC_PC) {
2f5680ee 1160 tcg_gen_movi_tl(cpu_npc, dc->npc);
72cbca10
FB		 1161 }
1162}
1163
4af984a7 1164static inline void save_state(DisasContext *dc, TCGv cond)
72cbca10 1165{
2f5680ee 1166 tcg_gen_movi_tl(cpu_pc, dc->pc);
4af984a7 1167 save_npc(dc, cond);
72cbca10
FB		 1168}
1169
4af984a7 1170static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
0bee699e
FB		 1171{
1172 if (dc->npc == JUMP_PC) {
4af984a7 1173 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
48d5c82b 1174 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1175 dc->pc = DYNAMIC_PC;
1176 } else if (dc->npc == DYNAMIC_PC) {
48d5c82b 1177 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1178 dc->pc = DYNAMIC_PC;
1179 } else {
1180 dc->pc = dc->npc;
1181 }
1182}
1183
38bc628b
BS		 1184static inline void gen_op_next_insn(void)
1185{
48d5c82b
BS		 1186 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1187 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
38bc628b
BS		 1188}
1189
19f329ad
BS		 1190static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1191{
1192 TCGv r_src;
3475187d 1193
3475187d 1194#ifdef TARGET_SPARC64
19f329ad 1195 if (cc)
dc99a3f2 1196 r_src = cpu_xcc;
19f329ad 1197 else
dc99a3f2 1198 r_src = cpu_psr;
3475187d 1199#else
dc99a3f2 1200 r_src = cpu_psr;
3475187d 1201#endif
19f329ad
BS		 1202 switch (cond) {
1203 case 0x0:
1204 gen_op_eval_bn(r_dst);
1205 break;
1206 case 0x1:
1207 gen_op_eval_be(r_dst, r_src);
1208 break;
1209 case 0x2:
1210 gen_op_eval_ble(r_dst, r_src);
1211 break;
1212 case 0x3:
1213 gen_op_eval_bl(r_dst, r_src);
1214 break;
1215 case 0x4:
1216 gen_op_eval_bleu(r_dst, r_src);
1217 break;
1218 case 0x5:
1219 gen_op_eval_bcs(r_dst, r_src);
1220 break;
1221 case 0x6:
1222 gen_op_eval_bneg(r_dst, r_src);
1223 break;
1224 case 0x7:
1225 gen_op_eval_bvs(r_dst, r_src);
1226 break;
1227 case 0x8:
1228 gen_op_eval_ba(r_dst);
1229 break;
1230 case 0x9:
1231 gen_op_eval_bne(r_dst, r_src);
1232 break;
1233 case 0xa:
1234 gen_op_eval_bg(r_dst, r_src);
1235 break;
1236 case 0xb:
1237 gen_op_eval_bge(r_dst, r_src);
1238 break;
1239 case 0xc:
1240 gen_op_eval_bgu(r_dst, r_src);
1241 break;
1242 case 0xd:
1243 gen_op_eval_bcc(r_dst, r_src);
1244 break;
1245 case 0xe:
1246 gen_op_eval_bpos(r_dst, r_src);
1247 break;
1248 case 0xf:
1249 gen_op_eval_bvc(r_dst, r_src);
1250 break;
1251 }
1252}
7a3f1944 1253
19f329ad 1254static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
e8af50a3 1255{
19f329ad
BS		 1256 unsigned int offset;
1257
19f329ad
BS		 1258 switch (cc) {
1259 default:
1260 case 0x0:
1261 offset = 0;
1262 break;
1263 case 0x1:
1264 offset = 32 - 10;
1265 break;
1266 case 0x2:
1267 offset = 34 - 10;
1268 break;
1269 case 0x3:
1270 offset = 36 - 10;
1271 break;
1272 }
1273
1274 switch (cond) {
1275 case 0x0:
1276 gen_op_eval_bn(r_dst);
1277 break;
1278 case 0x1:
87e92502 1279 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
19f329ad
BS		 1280 break;
1281 case 0x2:
87e92502 1282 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1283 break;
1284 case 0x3:
87e92502 1285 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
19f329ad
BS		 1286 break;
1287 case 0x4:
87e92502 1288 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
19f329ad
BS		 1289 break;
1290 case 0x5:
87e92502 1291 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
19f329ad
BS		 1292 break;
1293 case 0x6:
87e92502 1294 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1295 break;
1296 case 0x7:
87e92502 1297 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
19f329ad
BS		 1298 break;
1299 case 0x8:
1300 gen_op_eval_ba(r_dst);
1301 break;
1302 case 0x9:
87e92502 1303 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
19f329ad
BS		 1304 break;
1305 case 0xa:
87e92502 1306 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
19f329ad
BS		 1307 break;
1308 case 0xb:
87e92502 1309 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1310 break;
1311 case 0xc:
87e92502 1312 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1313 break;
1314 case 0xd:
87e92502 1315 gen_op_eval_fble(r_dst, cpu_fsr, offset);
19f329ad
BS		 1316 break;
1317 case 0xe:
87e92502 1318 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
19f329ad
BS		 1319 break;
1320 case 0xf:
87e92502 1321 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
19f329ad
BS		 1322 break;
1323 }
e8af50a3 1324}
00f219bf 1325
19f329ad 1326#ifdef TARGET_SPARC64
00f219bf
BS		 1327// Inverted logic
1328static const int gen_tcg_cond_reg[8] = {
1329 -1,
1330 TCG_COND_NE,
1331 TCG_COND_GT,
1332 TCG_COND_GE,
1333 -1,
1334 TCG_COND_EQ,
1335 TCG_COND_LE,
1336 TCG_COND_LT,
1337};
19f329ad 1338
4af984a7 1339static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
19f329ad 1340{
19f329ad
BS		 1341 int l1;
1342
1343 l1 = gen_new_label();
0425bee5 1344 tcg_gen_movi_tl(r_dst, 0);
4af984a7 1345 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], r_src, tcg_const_tl(0), l1);
19f329ad
BS		 1346 tcg_gen_movi_tl(r_dst, 1);
1347 gen_set_label(l1);
1348}
3475187d 1349#endif
cf495bcf 1350
0bee699e 1351/* XXX: potentially incorrect if dynamic npc */
4af984a7
BS		 1352static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1353 TCGv r_cond)
7a3f1944 1354{
cf495bcf 1355 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 1356 target_ulong target = dc->pc + offset;
5fafdf24 1357
cf495bcf 1358 if (cond == 0x0) {
0f8a249a
BS		 1359 /* unconditional not taken */
1360 if (a) {
1361 dc->pc = dc->npc + 4;
1362 dc->npc = dc->pc + 4;
1363 } else {
1364 dc->pc = dc->npc;
1365 dc->npc = dc->pc + 4;
1366 }
cf495bcf 1367 } else if (cond == 0x8) {
0f8a249a
BS		 1368 /* unconditional taken */
1369 if (a) {
1370 dc->pc = target;
1371 dc->npc = dc->pc + 4;
1372 } else {
1373 dc->pc = dc->npc;
1374 dc->npc = target;
1375 }
cf495bcf 1376 } else {
4af984a7
BS		 1377 flush_cond(dc, r_cond);
1378 gen_cond(r_cond, cc, cond);
0f8a249a 1379 if (a) {
4af984a7 1380 gen_branch_a(dc, target, dc->npc, r_cond);
cf495bcf 1381 dc->is_br = 1;
0f8a249a 1382 } else {
cf495bcf 1383 dc->pc = dc->npc;
72cbca10
FB		 1384 dc->jump_pc[0] = target;
1385 dc->jump_pc[1] = dc->npc + 4;
1386 dc->npc = JUMP_PC;
0f8a249a 1387 }
cf495bcf 1388 }
7a3f1944
FB		 1389}
1390
0bee699e 1391/* XXX: potentially incorrect if dynamic npc */
4af984a7
BS		 1392static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1393 TCGv r_cond)
e8af50a3
FB		 1394{
1395 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 1396 target_ulong target = dc->pc + offset;
1397
e8af50a3 1398 if (cond == 0x0) {
0f8a249a
BS		 1399 /* unconditional not taken */
1400 if (a) {
1401 dc->pc = dc->npc + 4;
1402 dc->npc = dc->pc + 4;
1403 } else {
1404 dc->pc = dc->npc;
1405 dc->npc = dc->pc + 4;
1406 }
e8af50a3 1407 } else if (cond == 0x8) {
0f8a249a
BS		 1408 /* unconditional taken */
1409 if (a) {
1410 dc->pc = target;
1411 dc->npc = dc->pc + 4;
1412 } else {
1413 dc->pc = dc->npc;
1414 dc->npc = target;
1415 }
e8af50a3 1416 } else {
4af984a7
BS		 1417 flush_cond(dc, r_cond);
1418 gen_fcond(r_cond, cc, cond);
0f8a249a 1419 if (a) {
4af984a7 1420 gen_branch_a(dc, target, dc->npc, r_cond);
e8af50a3 1421 dc->is_br = 1;
0f8a249a 1422 } else {
e8af50a3
FB		 1423 dc->pc = dc->npc;
1424 dc->jump_pc[0] = target;
1425 dc->jump_pc[1] = dc->npc + 4;
1426 dc->npc = JUMP_PC;
0f8a249a 1427 }
e8af50a3
FB		 1428 }
1429}
1430
3475187d
FB		 1431#ifdef TARGET_SPARC64
1432/* XXX: potentially incorrect if dynamic npc */
4af984a7
BS		 1433static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1434 TCGv r_cond, TCGv r_reg)
7a3f1944 1435{
3475187d
FB		 1436 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1437 target_ulong target = dc->pc + offset;
1438
4af984a7
BS		 1439 flush_cond(dc, r_cond);
1440 gen_cond_reg(r_cond, cond, r_reg);
3475187d 1441 if (a) {
4af984a7 1442 gen_branch_a(dc, target, dc->npc, r_cond);
0f8a249a 1443 dc->is_br = 1;
3475187d 1444 } else {
0f8a249a
BS		 1445 dc->pc = dc->npc;
1446 dc->jump_pc[0] = target;
1447 dc->jump_pc[1] = dc->npc + 4;
1448 dc->npc = JUMP_PC;
3475187d 1449 }
7a3f1944
FB		 1450}
1451
3475187d 1452static GenOpFunc * const gen_fcmps[4] = {
7e8c2b6c
BS		 1453 helper_fcmps,
1454 helper_fcmps_fcc1,
1455 helper_fcmps_fcc2,
1456 helper_fcmps_fcc3,
3475187d
FB		 1457};
1458
1459static GenOpFunc * const gen_fcmpd[4] = {
7e8c2b6c
BS		 1460 helper_fcmpd,
1461 helper_fcmpd_fcc1,
1462 helper_fcmpd_fcc2,
1463 helper_fcmpd_fcc3,
3475187d 1464};
417454b0 1465
1f587329
BS		 1466#if defined(CONFIG_USER_ONLY)
1467static GenOpFunc * const gen_fcmpq[4] = {
7e8c2b6c
BS		 1468 helper_fcmpq,
1469 helper_fcmpq_fcc1,
1470 helper_fcmpq_fcc2,
1471 helper_fcmpq_fcc3,
1f587329
BS		 1472};
1473#endif
1474
417454b0 1475static GenOpFunc * const gen_fcmpes[4] = {
7e8c2b6c
BS		 1476 helper_fcmpes,
1477 helper_fcmpes_fcc1,
1478 helper_fcmpes_fcc2,
1479 helper_fcmpes_fcc3,
417454b0
BS		 1480};
1481
1482static GenOpFunc * const gen_fcmped[4] = {
7e8c2b6c
BS		 1483 helper_fcmped,
1484 helper_fcmped_fcc1,
1485 helper_fcmped_fcc2,
1486 helper_fcmped_fcc3,
417454b0
BS		 1487};
1488
1f587329
BS		 1489#if defined(CONFIG_USER_ONLY)
1490static GenOpFunc * const gen_fcmpeq[4] = {
7e8c2b6c
BS		 1491 helper_fcmpeq,
1492 helper_fcmpeq_fcc1,
1493 helper_fcmpeq_fcc2,
1494 helper_fcmpeq_fcc3,
1f587329
BS		 1495};
1496#endif
7e8c2b6c
BS		 1497
1498static inline void gen_op_fcmps(int fccno)
1499{
1500 tcg_gen_helper_0_0(gen_fcmps[fccno]);
1501}
1502
1503static inline void gen_op_fcmpd(int fccno)
1504{
1505 tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1506}
1507
1508#if defined(CONFIG_USER_ONLY)
1509static inline void gen_op_fcmpq(int fccno)
1510{
1511 tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1512}
1513#endif
1514
1515static inline void gen_op_fcmpes(int fccno)
1516{
1517 tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1518}
1519
1520static inline void gen_op_fcmped(int fccno)
1521{
1522 tcg_gen_helper_0_0(gen_fcmped[fccno]);
1523}
1524
1525#if defined(CONFIG_USER_ONLY)
1526static inline void gen_op_fcmpeq(int fccno)
1527{
1528 tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1529}
1530#endif
1531
1532#else
1533
1534static inline void gen_op_fcmps(int fccno)
1535{
1536 tcg_gen_helper_0_0(helper_fcmps);
1537}
1538
1539static inline void gen_op_fcmpd(int fccno)
1540{
1541 tcg_gen_helper_0_0(helper_fcmpd);
1542}
1543
1544#if defined(CONFIG_USER_ONLY)
1545static inline void gen_op_fcmpq(int fccno)
1546{
1547 tcg_gen_helper_0_0(helper_fcmpq);
1548}
1549#endif
1550
1551static inline void gen_op_fcmpes(int fccno)
1552{
1553 tcg_gen_helper_0_0(helper_fcmpes);
1554}
1555
1556static inline void gen_op_fcmped(int fccno)
1557{
1558 tcg_gen_helper_0_0(helper_fcmped);
1559}
1560
1561#if defined(CONFIG_USER_ONLY)
1562static inline void gen_op_fcmpeq(int fccno)
1563{
1564 tcg_gen_helper_0_0(helper_fcmpeq);
1565}
1566#endif
1567
3475187d
FB		 1568#endif
1569
134d77a1
BS		 1570static inline void gen_op_fpexception_im(int fsr_flags)
1571{
87e92502
BS		 1572 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1573 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
2f5680ee 1574 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_FP_EXCP));
134d77a1
BS		 1575}
1576
4af984a7 1577static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
a80dde08
FB		 1578{
1579#if !defined(CONFIG_USER_ONLY)
1580 if (!dc->fpu_enabled) {
4af984a7 1581 save_state(dc, r_cond);
2f5680ee 1582 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NFPU_INSN));
a80dde08
FB		 1583 dc->is_br = 1;
1584 return 1;
1585 }
1586#endif
1587 return 0;
1588}
1589
7e8c2b6c
BS		 1590static inline void gen_op_clear_ieee_excp_and_FTT(void)
1591{
87e92502 1592 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
7e8c2b6c
BS		 1593}
1594
1595static inline void gen_clear_float_exceptions(void)
1596{
1597 tcg_gen_helper_0_0(helper_clear_float_exceptions);
1598}
1599
1a2fb1c0
BS		 1600/* asi moves */
1601#ifdef TARGET_SPARC64
0425bee5 1602static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1a2fb1c0
BS		 1603{
1604 int asi, offset;
0425bee5 1605 TCGv r_asi;
1a2fb1c0 1606
1a2fb1c0 1607 if (IS_IMM) {
0425bee5 1608 r_asi = tcg_temp_new(TCG_TYPE_I32);
1a2fb1c0 1609 offset = GET_FIELD(insn, 25, 31);
0425bee5
BS		 1610 tcg_gen_addi_tl(r_addr, r_addr, offset);
1611 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1a2fb1c0
BS		 1612 } else {
1613 asi = GET_FIELD(insn, 19, 26);
0425bee5 1614 r_asi = tcg_const_i32(asi);
1a2fb1c0 1615 }
0425bee5
BS		 1616 return r_asi;
1617}
1618
4af984a7 1619static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
0425bee5
BS		 1620{
1621 TCGv r_asi;
1622
4af984a7
BS		 1623 r_asi = gen_get_asi(insn, addr);
1624 tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi,
0425bee5 1625 tcg_const_i32(size), tcg_const_i32(sign));
1a2fb1c0
BS		 1626}
1627
4af984a7 1628static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1a2fb1c0 1629{
0425bee5 1630 TCGv r_asi;
1a2fb1c0 1631
4af984a7
BS		 1632 r_asi = gen_get_asi(insn, addr);
1633 tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, tcg_const_i32(size));
1a2fb1c0
BS		 1634}
1635
4af984a7 1636static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1a2fb1c0 1637{
0425bee5 1638 TCGv r_asi;
1a2fb1c0 1639
4af984a7
BS		 1640 r_asi = gen_get_asi(insn, addr);
1641 tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, tcg_const_i32(size),
0425bee5 1642 tcg_const_i32(rd));
1a2fb1c0
BS		 1643}
1644
4af984a7 1645static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1a2fb1c0 1646{
0425bee5 1647 TCGv r_asi;
1a2fb1c0 1648
31741a27
BS		 1649 r_asi = gen_get_asi(insn, addr);
1650 tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, tcg_const_i32(size),
0425bee5 1651 tcg_const_i32(rd));
1a2fb1c0
BS		 1652}
1653
4af984a7 1654static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1a2fb1c0 1655{
0425bee5 1656 TCGv r_temp, r_asi;
1a2fb1c0 1657
1a2fb1c0 1658 r_temp = tcg_temp_new(TCG_TYPE_I32);
4af984a7
BS		 1659 r_asi = gen_get_asi(insn, addr);
1660 tcg_gen_helper_1_4(helper_ld_asi, r_temp, addr, r_asi,
0425bee5 1661 tcg_const_i32(4), tcg_const_i32(0));
4af984a7 1662 tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi,
0425bee5 1663 tcg_const_i32(4));
4af984a7 1664 tcg_gen_extu_i32_tl(dst, r_temp);
1a2fb1c0
BS		 1665}
1666
4af984a7 1667static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1a2fb1c0 1668{
8911f501 1669 TCGv r_asi;
1a2fb1c0 1670
4af984a7
BS		 1671 r_asi = gen_get_asi(insn, addr);
1672 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi,
0425bee5 1673 tcg_const_i32(8), tcg_const_i32(0));
4af984a7 1674 tcg_gen_andi_i64(lo, cpu_tmp64, 0xffffffffULL);
8911f501 1675 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4af984a7 1676 tcg_gen_andi_i64(hi, cpu_tmp64, 0xffffffffULL);
0425bee5
BS		 1677}
1678
4af984a7 1679static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
0425bee5 1680{
8911f501 1681 TCGv r_temp, r_asi;
0425bee5 1682
0425bee5
BS		 1683 r_temp = tcg_temp_new(TCG_TYPE_I32);
1684 gen_movl_reg_TN(rd + 1, r_temp);
4af984a7 1685 tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
0425bee5 1686 r_temp);
4af984a7
BS		 1687 r_asi = gen_get_asi(insn, addr);
1688 tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi,
0425bee5 1689 tcg_const_i32(8));
1a2fb1c0
BS		 1690}
1691
4af984a7 1692static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
1a2fb1c0 1693{
1a2fb1c0
BS		 1694 TCGv r_val1, r_asi;
1695
1696 r_val1 = tcg_temp_new(TCG_TYPE_I32);
1a2fb1c0 1697 gen_movl_reg_TN(rd, r_val1);
4af984a7
BS		 1698 r_asi = gen_get_asi(insn, addr);
1699 tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1a2fb1c0
BS		 1700}
1701
4af984a7 1702static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
1a2fb1c0 1703{
8911f501 1704 TCGv r_asi;
1a2fb1c0 1705
8911f501 1706 gen_movl_reg_TN(rd, cpu_tmp64);
4af984a7
BS		 1707 r_asi = gen_get_asi(insn, addr);
1708 tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1a2fb1c0
BS		 1709}
1710
1711#elif !defined(CONFIG_USER_ONLY)
1712
4af984a7 1713static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
1a2fb1c0
BS		 1714{
1715 int asi;
1a2fb1c0 1716
1a2fb1c0 1717 asi = GET_FIELD(insn, 19, 26);
4af984a7 1718 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi),
0425bee5 1719 tcg_const_i32(size), tcg_const_i32(sign));
4af984a7 1720 tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1a2fb1c0
BS		 1721}
1722
4af984a7 1723static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1a2fb1c0
BS		 1724{
1725 int asi;
1a2fb1c0 1726
4af984a7 1727 tcg_gen_extu_tl_i64(cpu_tmp64, src);
1a2fb1c0 1728 asi = GET_FIELD(insn, 19, 26);
4af984a7 1729 tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi),
0425bee5 1730 tcg_const_i32(size));
1a2fb1c0
BS		 1731}
1732
4af984a7 1733static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1a2fb1c0
BS		 1734{
1735 int asi;
0425bee5 1736 TCGv r_temp;
1a2fb1c0 1737
1a2fb1c0 1738 r_temp = tcg_temp_new(TCG_TYPE_I32);
1a2fb1c0 1739 asi = GET_FIELD(insn, 19, 26);
4af984a7 1740 tcg_gen_helper_1_4(helper_ld_asi, r_temp, addr, tcg_const_i32(asi),
0425bee5 1741 tcg_const_i32(4), tcg_const_i32(0));
4af984a7 1742 tcg_gen_helper_0_4(helper_st_asi, addr, dst, tcg_const_i32(asi),
0425bee5 1743 tcg_const_i32(4));
4af984a7 1744 tcg_gen_extu_i32_tl(dst, r_temp);
1a2fb1c0
BS		 1745}
1746
4af984a7 1747static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1a2fb1c0
BS		 1748{
1749 int asi;
1a2fb1c0 1750
1a2fb1c0 1751 asi = GET_FIELD(insn, 19, 26);
4af984a7 1752 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi),
0425bee5 1753 tcg_const_i32(8), tcg_const_i32(0));
4af984a7 1754 tcg_gen_trunc_i64_tl(lo, cpu_tmp64);
8911f501 1755 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4af984a7 1756 tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
0425bee5
BS		 1757}
1758
4af984a7 1759static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
0425bee5
BS		 1760{
1761 int asi;
8911f501 1762 TCGv r_temp;
0425bee5 1763
0425bee5
BS		 1764 r_temp = tcg_temp_new(TCG_TYPE_I32);
1765 gen_movl_reg_TN(rd + 1, r_temp);
4af984a7 1766 tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
0425bee5 1767 asi = GET_FIELD(insn, 19, 26);
4af984a7 1768 tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi),
0425bee5 1769 tcg_const_i32(8));
1a2fb1c0
BS		 1770}
1771#endif
1772
1773#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4af984a7 1774static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1a2fb1c0
BS		 1775{
1776 int asi;
1a2fb1c0 1777
4af984a7 1778 gen_ld_asi(dst, addr, insn, 1, 0);
1a2fb1c0 1779
1a2fb1c0 1780 asi = GET_FIELD(insn, 19, 26);
4af984a7 1781 tcg_gen_helper_0_4(helper_st_asi, addr, tcg_const_i64(0xffULL),
0425bee5 1782 tcg_const_i32(asi), tcg_const_i32(1));
1a2fb1c0
BS		 1783}
1784#endif
1785
9322a4bf
BS		 1786static inline TCGv get_src1(unsigned int insn, TCGv def)
1787{
1788 TCGv r_rs1 = def;
1789 unsigned int rs1;
1790
1791 rs1 = GET_FIELD(insn, 13, 17);
1792 if (rs1 == 0)
1793 //r_rs1 = tcg_const_tl(0);
1794 tcg_gen_movi_tl(def, 0);
1795 else if (rs1 < 8)
1796 //r_rs1 = cpu_gregs[rs1];
1797 tcg_gen_mov_tl(def, cpu_gregs[rs1]);
1798 else
1799 tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1800 return r_rs1;
1801}
1802
a49d9390
BS		 1803static inline TCGv get_src2(unsigned int insn, TCGv def)
1804{
1805 TCGv r_rs2 = def;
1806 unsigned int rs2;
1807
1808 if (IS_IMM) { /* immediate */
1809 rs2 = GET_FIELDs(insn, 19, 31);
1810 r_rs2 = tcg_const_tl((int)rs2);
1811 } else { /* register */
1812 rs2 = GET_FIELD(insn, 27, 31);
1813 if (rs2 == 0)
1814 r_rs2 = tcg_const_tl(0);
1815 else if (rs2 < 8)
1816 r_rs2 = cpu_gregs[rs2];
1817 else
1818 tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1819 }
1820 return r_rs2;
1821}
1822
0bee699e 1823/* before an instruction, dc->pc must be static */
cf495bcf
FB		 1824static void disas_sparc_insn(DisasContext * dc)
1825{
1826 unsigned int insn, opc, rs1, rs2, rd;
7a3f1944 1827
0fa85d43 1828 insn = ldl_code(dc->pc);
cf495bcf 1829 opc = GET_FIELD(insn, 0, 1);
7a3f1944 1830
cf495bcf 1831 rd = GET_FIELD(insn, 2, 6);
6ae20372
BS		 1832
1833 cpu_dst = cpu_T[0];
1834 cpu_src1 = cpu_T[0]; // const
1835 cpu_src2 = cpu_T[1]; // const
1836
1837 // loads and stores
1838 cpu_addr = cpu_T[0];
1839 cpu_val = cpu_T[1];
1840
cf495bcf 1841 switch (opc) {
0f8a249a
BS		 1842 case 0: /* branches/sethi */
1843 {
1844 unsigned int xop = GET_FIELD(insn, 7, 9);
1845 int32_t target;
1846 switch (xop) {
3475187d 1847#ifdef TARGET_SPARC64
0f8a249a
BS		 1848 case 0x1: /* V9 BPcc */
1849 {
1850 int cc;
1851
1852 target = GET_FIELD_SP(insn, 0, 18);
1853 target = sign_extend(target, 18);
1854 target <<= 2;
1855 cc = GET_FIELD_SP(insn, 20, 21);
1856 if (cc == 0)
6ae20372 1857 do_branch(dc, target, insn, 0, cpu_cond);
0f8a249a 1858 else if (cc == 2)
6ae20372 1859 do_branch(dc, target, insn, 1, cpu_cond);
0f8a249a
BS		 1860 else
1861 goto illegal_insn;
1862 goto jmp_insn;
1863 }
1864 case 0x3: /* V9 BPr */
1865 {
1866 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 1867 (GET_FIELD_SP(insn, 20, 21) << 14);
0f8a249a
BS		 1868 target = sign_extend(target, 16);
1869 target <<= 2;
9322a4bf 1870 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372 1871 do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
0f8a249a
BS		 1872 goto jmp_insn;
1873 }
1874 case 0x5: /* V9 FBPcc */
1875 {
1876 int cc = GET_FIELD_SP(insn, 20, 21);
6ae20372 1877 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 1878 goto jmp_insn;
0f8a249a
BS		 1879 target = GET_FIELD_SP(insn, 0, 18);
1880 target = sign_extend(target, 19);
1881 target <<= 2;
6ae20372 1882 do_fbranch(dc, target, insn, cc, cpu_cond);
0f8a249a
BS		 1883 goto jmp_insn;
1884 }
a4d17f19 1885#else
0f8a249a
BS		 1886 case 0x7: /* CBN+x */
1887 {
1888 goto ncp_insn;
1889 }
1890#endif
1891 case 0x2: /* BN+x */
1892 {
1893 target = GET_FIELD(insn, 10, 31);
1894 target = sign_extend(target, 22);
1895 target <<= 2;
6ae20372 1896 do_branch(dc, target, insn, 0, cpu_cond);
0f8a249a
BS		 1897 goto jmp_insn;
1898 }
1899 case 0x6: /* FBN+x */
1900 {
6ae20372 1901 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 1902 goto jmp_insn;
0f8a249a
BS		 1903 target = GET_FIELD(insn, 10, 31);
1904 target = sign_extend(target, 22);
1905 target <<= 2;
6ae20372 1906 do_fbranch(dc, target, insn, 0, cpu_cond);
0f8a249a
BS		 1907 goto jmp_insn;
1908 }
1909 case 0x4: /* SETHI */
0f8a249a 1910 if (rd) { // nop
0f8a249a 1911 uint32_t value = GET_FIELD(insn, 10, 31);
9c6c6662 1912 gen_movl_TN_reg(rd, tcg_const_tl(value << 10));
0f8a249a 1913 }
0f8a249a
BS		 1914 break;
1915 case 0x0: /* UNIMPL */
1916 default:
3475187d 1917 goto illegal_insn;
0f8a249a
BS		 1918 }
1919 break;
1920 }
1921 break;
cf495bcf 1922 case 1:
0f8a249a
BS		 1923 /*CALL*/ {
1924 target_long target = GET_FIELDs(insn, 2, 31) << 2;
cf495bcf 1925
48d5c82b 1926 gen_movl_TN_reg(15, tcg_const_tl(dc->pc));
0f8a249a 1927 target += dc->pc;
6ae20372 1928 gen_mov_pc_npc(dc, cpu_cond);
0f8a249a
BS		 1929 dc->npc = target;
1930 }
1931 goto jmp_insn;
1932 case 2: /* FPU & Logical Operations */
1933 {
1934 unsigned int xop = GET_FIELD(insn, 7, 12);
1935 if (xop == 0x3a) { /* generate trap */
cf495bcf 1936 int cond;
3475187d 1937
9322a4bf 1938 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a
BS		 1939 if (IS_IMM) {
1940 rs2 = GET_FIELD(insn, 25, 31);
6ae20372 1941 tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
cf495bcf
FB		 1942 } else {
1943 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 1944 if (rs2 != 0) {
6ae20372
BS		 1945 gen_movl_reg_TN(rs2, cpu_src2);
1946 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
6f551262
BS		 1947 } else
1948 tcg_gen_mov_tl(cpu_dst, cpu_src1);
cf495bcf 1949 }
cf495bcf
FB		 1950 cond = GET_FIELD(insn, 3, 6);
1951 if (cond == 0x8) {
6ae20372
BS		 1952 save_state(dc, cpu_cond);
1953 tcg_gen_helper_0_1(helper_trap, cpu_dst);
af7bf89b 1954 } else if (cond != 0) {
748b9d8e 1955 TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
3475187d 1956#ifdef TARGET_SPARC64
0f8a249a
BS		 1957 /* V9 icc/xcc */
1958 int cc = GET_FIELD_SP(insn, 11, 12);
748b9d8e 1959
6ae20372 1960 save_state(dc, cpu_cond);
0f8a249a 1961 if (cc == 0)
748b9d8e 1962 gen_cond(r_cond, 0, cond);
0f8a249a 1963 else if (cc == 2)
748b9d8e 1964 gen_cond(r_cond, 1, cond);
0f8a249a
BS		 1965 else
1966 goto illegal_insn;
3475187d 1967#else
6ae20372 1968 save_state(dc, cpu_cond);
748b9d8e 1969 gen_cond(r_cond, 0, cond);
3475187d 1970#endif
6ae20372 1971 tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
cf495bcf 1972 }
a80dde08 1973 gen_op_next_insn();
57fec1fe 1974 tcg_gen_exit_tb(0);
a80dde08
FB		 1975 dc->is_br = 1;
1976 goto jmp_insn;
cf495bcf
FB		 1977 } else if (xop == 0x28) {
1978 rs1 = GET_FIELD(insn, 13, 17);
1979 switch(rs1) {
1980 case 0: /* rdy */
65fe7b09
BS		 1981#ifndef TARGET_SPARC64
1982 case 0x01 ... 0x0e: /* undefined in the SPARCv8
1983 manual, rdy on the microSPARC
1984 II */
1985 case 0x0f: /* stbar in the SPARCv8 manual,
1986 rdy on the microSPARC II */
1987 case 0x10 ... 0x1f: /* implementation-dependent in the
1988 SPARCv8 manual, rdy on the
1989 microSPARC II */
1990#endif
6ae20372
BS		 1991 tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, y));
1992 gen_movl_TN_reg(rd, cpu_dst);
cf495bcf 1993 break;
3475187d 1994#ifdef TARGET_SPARC64
0f8a249a 1995 case 0x2: /* V9 rdccr */
6ae20372
BS		 1996 tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
1997 gen_movl_TN_reg(rd, cpu_dst);
3475187d 1998 break;
0f8a249a 1999 case 0x3: /* V9 rdasi */
2f5680ee 2000 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
6ae20372
BS		 2001 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2002 gen_movl_TN_reg(rd, cpu_dst);
3475187d 2003 break;
0f8a249a 2004 case 0x4: /* V9 rdtick */
ccd4a219
BS		 2005 {
2006 TCGv r_tickptr;
2007
2008 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2009 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2010 offsetof(CPUState, tick));
6ae20372 2011 tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
ccd4a219 2012 r_tickptr);
6ae20372 2013 gen_movl_TN_reg(rd, cpu_dst);
ccd4a219 2014 }
3475187d 2015 break;
0f8a249a 2016 case 0x5: /* V9 rdpc */
9c6c6662 2017 gen_movl_TN_reg(rd, tcg_const_tl(dc->pc));
0f8a249a
BS		 2018 break;
2019 case 0x6: /* V9 rdfprs */
2f5680ee 2020 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
6ae20372
BS		 2021 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2022 gen_movl_TN_reg(rd, cpu_dst);
3475187d 2023 break;
65fe7b09
BS		 2024 case 0xf: /* V9 membar */
2025 break; /* no effect */
0f8a249a 2026 case 0x13: /* Graphics Status */
6ae20372 2027 if (gen_trap_ifnofpu(dc, cpu_cond))
725cb90b 2028 goto jmp_insn;
6ae20372
BS		 2029 tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, gsr));
2030 gen_movl_TN_reg(rd, cpu_dst);
725cb90b 2031 break;
0f8a249a 2032 case 0x17: /* Tick compare */
6ae20372
BS		 2033 tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tick_cmpr));
2034 gen_movl_TN_reg(rd, cpu_dst);
83469015 2035 break;
0f8a249a 2036 case 0x18: /* System tick */
ccd4a219
BS		 2037 {
2038 TCGv r_tickptr;
2039
2040 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2041 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2042 offsetof(CPUState, stick));
6ae20372 2043 tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
ccd4a219 2044 r_tickptr);
6ae20372 2045 gen_movl_TN_reg(rd, cpu_dst);
ccd4a219 2046 }
83469015 2047 break;
0f8a249a 2048 case 0x19: /* System tick compare */
6ae20372
BS		 2049 tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, stick_cmpr));
2050 gen_movl_TN_reg(rd, cpu_dst);
83469015 2051 break;
0f8a249a
BS		 2052 case 0x10: /* Performance Control */
2053 case 0x11: /* Performance Instrumentation Counter */
2054 case 0x12: /* Dispatch Control */
2055 case 0x14: /* Softint set, WO */
2056 case 0x15: /* Softint clear, WO */
2057 case 0x16: /* Softint write */
3475187d
FB		 2058#endif
2059 default:
cf495bcf
FB		 2060 goto illegal_insn;
2061 }
e8af50a3 2062#if !defined(CONFIG_USER_ONLY)
e9ebed4d 2063 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 2064#ifndef TARGET_SPARC64
0f8a249a
BS		 2065 if (!supervisor(dc))
2066 goto priv_insn;
6ae20372 2067 tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
e9ebed4d
BS		 2068#else
2069 if (!hypervisor(dc))
2070 goto priv_insn;
2071 rs1 = GET_FIELD(insn, 13, 17);
2072 switch (rs1) {
2073 case 0: // hpstate
2074 // gen_op_rdhpstate();
2075 break;
2076 case 1: // htstate
2077 // gen_op_rdhtstate();
2078 break;
2079 case 3: // hintp
2f5680ee 2080 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
6ae20372 2081 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
e9ebed4d
BS		 2082 break;
2083 case 5: // htba
2f5680ee 2084 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
6ae20372 2085 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
e9ebed4d
BS		 2086 break;
2087 case 6: // hver
2f5680ee 2088 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hver));
6ae20372 2089 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
e9ebed4d
BS		 2090 break;
2091 case 31: // hstick_cmpr
6ae20372 2092 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 2093 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hstick_cmpr));
e9ebed4d
BS		 2094 break;
2095 default:
2096 goto illegal_insn;
2097 }
2098#endif
6ae20372 2099 gen_movl_TN_reg(rd, cpu_dst);
e8af50a3 2100 break;
3475187d 2101 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
0f8a249a
BS		 2102 if (!supervisor(dc))
2103 goto priv_insn;
3475187d
FB		 2104#ifdef TARGET_SPARC64
2105 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2106 switch (rs1) {
2107 case 0: // tpc
375ee38b
BS		 2108 {
2109 TCGv r_tsptr;
2110
2111 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2112 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2113 offsetof(CPUState, tsptr));
6ae20372 2114 tcg_gen_ld_tl(cpu_dst, r_tsptr,
375ee38b
BS		 2115 offsetof(trap_state, tpc));
2116 }
0f8a249a
BS		 2117 break;
2118 case 1: // tnpc
375ee38b
BS		 2119 {
2120 TCGv r_tsptr;
2121
2122 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2123 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2124 offsetof(CPUState, tsptr));
6ae20372 2125 tcg_gen_ld_tl(cpu_dst, r_tsptr,
375ee38b
BS		 2126 offsetof(trap_state, tnpc));
2127 }
0f8a249a
BS		 2128 break;
2129 case 2: // tstate
375ee38b
BS		 2130 {
2131 TCGv r_tsptr;
2132
2133 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2134 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2135 offsetof(CPUState, tsptr));
6ae20372 2136 tcg_gen_ld_tl(cpu_dst, r_tsptr,
375ee38b
BS		 2137 offsetof(trap_state, tstate));
2138 }
0f8a249a
BS		 2139 break;
2140 case 3: // tt
375ee38b
BS		 2141 {
2142 TCGv r_tsptr;
2143
2144 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2145 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2146 offsetof(CPUState, tsptr));
6ae20372 2147 tcg_gen_ld_i32(cpu_dst, r_tsptr,
375ee38b
BS		 2148 offsetof(trap_state, tt));
2149 }
0f8a249a
BS		 2150 break;
2151 case 4: // tick
ccd4a219
BS		 2152 {
2153 TCGv r_tickptr;
2154
2155 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2156 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2157 offsetof(CPUState, tick));
6ae20372 2158 tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
ccd4a219 2159 r_tickptr);
6ae20372 2160 gen_movl_TN_reg(rd, cpu_dst);
ccd4a219 2161 }
0f8a249a
BS		 2162 break;
2163 case 5: // tba
6ae20372 2164 tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
0f8a249a
BS		 2165 break;
2166 case 6: // pstate
2f5680ee 2167 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, pstate));
6ae20372 2168 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
0f8a249a
BS		 2169 break;
2170 case 7: // tl
2f5680ee 2171 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
6ae20372 2172 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
0f8a249a
BS		 2173 break;
2174 case 8: // pil
2f5680ee 2175 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
6ae20372 2176 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
0f8a249a
BS		 2177 break;
2178 case 9: // cwp
6ae20372 2179 tcg_gen_helper_1_0(helper_rdcwp, cpu_dst);
0f8a249a
BS		 2180 break;
2181 case 10: // cansave
2f5680ee 2182 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
6ae20372 2183 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
0f8a249a
BS		 2184 break;
2185 case 11: // canrestore
2f5680ee 2186 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
6ae20372 2187 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
0f8a249a
BS		 2188 break;
2189 case 12: // cleanwin
2f5680ee 2190 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
6ae20372 2191 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
0f8a249a
BS		 2192 break;
2193 case 13: // otherwin
2f5680ee 2194 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
6ae20372 2195 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
0f8a249a
BS		 2196 break;
2197 case 14: // wstate
2f5680ee 2198 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
6ae20372 2199 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
0f8a249a 2200 break;
e9ebed4d 2201 case 16: // UA2005 gl
2f5680ee 2202 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
6ae20372 2203 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
e9ebed4d
BS		 2204 break;
2205 case 26: // UA2005 strand status
2206 if (!hypervisor(dc))
2207 goto priv_insn;
2f5680ee 2208 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
6ae20372 2209 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
e9ebed4d 2210 break;
0f8a249a 2211 case 31: // ver
6ae20372 2212 tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, version));
0f8a249a
BS		 2213 break;
2214 case 15: // fq
2215 default:
2216 goto illegal_insn;
2217 }
3475187d 2218#else
2f5680ee 2219 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
6ae20372 2220 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
3475187d 2221#endif
6ae20372 2222 gen_movl_TN_reg(rd, cpu_dst);
e8af50a3 2223 break;
3475187d
FB		 2224 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2225#ifdef TARGET_SPARC64
72a9747b 2226 tcg_gen_helper_0_0(helper_flushw);
3475187d 2227#else
0f8a249a
BS		 2228 if (!supervisor(dc))
2229 goto priv_insn;
6ae20372
BS		 2230 tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
2231 gen_movl_TN_reg(rd, cpu_dst);
3475187d 2232#endif
e8af50a3
FB		 2233 break;
2234#endif
0f8a249a 2235 } else if (xop == 0x34) { /* FPU Operations */
6ae20372 2236 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 2237 goto jmp_insn;
0f8a249a 2238 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 2239 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2240 rs2 = GET_FIELD(insn, 27, 31);
2241 xop = GET_FIELD(insn, 18, 26);
2242 switch (xop) {
2243 case 0x1: /* fmovs */
2244 gen_op_load_fpr_FT0(rs2);
2245 gen_op_store_FT0_fpr(rd);
2246 break;
2247 case 0x5: /* fnegs */
2248 gen_op_load_fpr_FT1(rs2);
44e7757c 2249 tcg_gen_helper_0_0(helper_fnegs);
0f8a249a
BS		 2250 gen_op_store_FT0_fpr(rd);
2251 break;
2252 case 0x9: /* fabss */
2253 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2254 tcg_gen_helper_0_0(helper_fabss);
0f8a249a
BS		 2255 gen_op_store_FT0_fpr(rd);
2256 break;
2257 case 0x29: /* fsqrts */
2258 gen_op_load_fpr_FT1(rs2);
7e8c2b6c
BS		 2259 gen_clear_float_exceptions();
2260 tcg_gen_helper_0_0(helper_fsqrts);
2261 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2262 gen_op_store_FT0_fpr(rd);
2263 break;
2264 case 0x2a: /* fsqrtd */
2265 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c
BS		 2266 gen_clear_float_exceptions();
2267 tcg_gen_helper_0_0(helper_fsqrtd);
2268 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2269 gen_op_store_DT0_fpr(DFPREG(rd));
2270 break;
2271 case 0x2b: /* fsqrtq */
1f587329
BS		 2272#if defined(CONFIG_USER_ONLY)
2273 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c
BS		 2274 gen_clear_float_exceptions();
2275 tcg_gen_helper_0_0(helper_fsqrtq);
2276 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2277 gen_op_store_QT0_fpr(QFPREG(rd));
2278 break;
2279#else
0f8a249a 2280 goto nfpu_insn;
1f587329 2281#endif
0f8a249a
BS		 2282 case 0x41:
2283 gen_op_load_fpr_FT0(rs1);
2284 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2285 gen_clear_float_exceptions();
44e7757c 2286 tcg_gen_helper_0_0(helper_fadds);
7e8c2b6c 2287 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2288 gen_op_store_FT0_fpr(rd);
2289 break;
2290 case 0x42:
2291 gen_op_load_fpr_DT0(DFPREG(rs1));
2292 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2293 gen_clear_float_exceptions();
44e7757c 2294 tcg_gen_helper_0_0(helper_faddd);
7e8c2b6c 2295 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2296 gen_op_store_DT0_fpr(DFPREG(rd));
2297 break;
2298 case 0x43: /* faddq */
1f587329
BS		 2299#if defined(CONFIG_USER_ONLY)
2300 gen_op_load_fpr_QT0(QFPREG(rs1));
2301 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2302 gen_clear_float_exceptions();
44e7757c 2303 tcg_gen_helper_0_0(helper_faddq);
7e8c2b6c 2304 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2305 gen_op_store_QT0_fpr(QFPREG(rd));
2306 break;
2307#else
0f8a249a 2308 goto nfpu_insn;
1f587329 2309#endif
0f8a249a
BS		 2310 case 0x45:
2311 gen_op_load_fpr_FT0(rs1);
2312 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2313 gen_clear_float_exceptions();
44e7757c 2314 tcg_gen_helper_0_0(helper_fsubs);
7e8c2b6c 2315 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2316 gen_op_store_FT0_fpr(rd);
2317 break;
2318 case 0x46:
2319 gen_op_load_fpr_DT0(DFPREG(rs1));
2320 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2321 gen_clear_float_exceptions();
44e7757c 2322 tcg_gen_helper_0_0(helper_fsubd);
7e8c2b6c 2323 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2324 gen_op_store_DT0_fpr(DFPREG(rd));
2325 break;
2326 case 0x47: /* fsubq */
1f587329
BS		 2327#if defined(CONFIG_USER_ONLY)
2328 gen_op_load_fpr_QT0(QFPREG(rs1));
2329 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2330 gen_clear_float_exceptions();
44e7757c 2331 tcg_gen_helper_0_0(helper_fsubq);
7e8c2b6c 2332 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2333 gen_op_store_QT0_fpr(QFPREG(rd));
2334 break;
2335#else
0f8a249a 2336 goto nfpu_insn;
1f587329 2337#endif
0f8a249a
BS		 2338 case 0x49:
2339 gen_op_load_fpr_FT0(rs1);
2340 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2341 gen_clear_float_exceptions();
44e7757c 2342 tcg_gen_helper_0_0(helper_fmuls);
7e8c2b6c 2343 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2344 gen_op_store_FT0_fpr(rd);
2345 break;
2346 case 0x4a:
2347 gen_op_load_fpr_DT0(DFPREG(rs1));
2348 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2349 gen_clear_float_exceptions();
44e7757c 2350 tcg_gen_helper_0_0(helper_fmuld);
7e8c2b6c 2351 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2382dc6b 2352 gen_op_store_DT0_fpr(DFPREG(rd));
0f8a249a
BS		 2353 break;
2354 case 0x4b: /* fmulq */
1f587329
BS		 2355#if defined(CONFIG_USER_ONLY)
2356 gen_op_load_fpr_QT0(QFPREG(rs1));
2357 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2358 gen_clear_float_exceptions();
44e7757c 2359 tcg_gen_helper_0_0(helper_fmulq);
7e8c2b6c 2360 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2361 gen_op_store_QT0_fpr(QFPREG(rd));
2362 break;
2363#else
0f8a249a 2364 goto nfpu_insn;
1f587329 2365#endif
0f8a249a
BS		 2366 case 0x4d:
2367 gen_op_load_fpr_FT0(rs1);
2368 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2369 gen_clear_float_exceptions();
44e7757c 2370 tcg_gen_helper_0_0(helper_fdivs);
7e8c2b6c 2371 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2372 gen_op_store_FT0_fpr(rd);
2373 break;
2374 case 0x4e:
2375 gen_op_load_fpr_DT0(DFPREG(rs1));
2376 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2377 gen_clear_float_exceptions();
44e7757c 2378 tcg_gen_helper_0_0(helper_fdivd);
7e8c2b6c 2379 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2380 gen_op_store_DT0_fpr(DFPREG(rd));
2381 break;
2382 case 0x4f: /* fdivq */
1f587329
BS		 2383#if defined(CONFIG_USER_ONLY)
2384 gen_op_load_fpr_QT0(QFPREG(rs1));
2385 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2386 gen_clear_float_exceptions();
44e7757c 2387 tcg_gen_helper_0_0(helper_fdivq);
7e8c2b6c 2388 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2389 gen_op_store_QT0_fpr(QFPREG(rd));
2390 break;
2391#else
0f8a249a 2392 goto nfpu_insn;
1f587329 2393#endif
0f8a249a
BS		 2394 case 0x69:
2395 gen_op_load_fpr_FT0(rs1);
2396 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2397 gen_clear_float_exceptions();
44e7757c 2398 tcg_gen_helper_0_0(helper_fsmuld);
7e8c2b6c 2399 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2400 gen_op_store_DT0_fpr(DFPREG(rd));
2401 break;
2402 case 0x6e: /* fdmulq */
1f587329
BS		 2403#if defined(CONFIG_USER_ONLY)
2404 gen_op_load_fpr_DT0(DFPREG(rs1));
2405 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2406 gen_clear_float_exceptions();
44e7757c 2407 tcg_gen_helper_0_0(helper_fdmulq);
7e8c2b6c 2408 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2409 gen_op_store_QT0_fpr(QFPREG(rd));
2410 break;
2411#else
0f8a249a 2412 goto nfpu_insn;
1f587329 2413#endif
0f8a249a
BS		 2414 case 0xc4:
2415 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2416 gen_clear_float_exceptions();
44e7757c 2417 tcg_gen_helper_0_0(helper_fitos);
7e8c2b6c 2418 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2419 gen_op_store_FT0_fpr(rd);
2420 break;
2421 case 0xc6:
2422 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2423 gen_clear_float_exceptions();
44e7757c 2424 tcg_gen_helper_0_0(helper_fdtos);
7e8c2b6c 2425 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2426 gen_op_store_FT0_fpr(rd);
2427 break;
2428 case 0xc7: /* fqtos */
1f587329
BS		 2429#if defined(CONFIG_USER_ONLY)
2430 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2431 gen_clear_float_exceptions();
44e7757c 2432 tcg_gen_helper_0_0(helper_fqtos);
7e8c2b6c 2433 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2434 gen_op_store_FT0_fpr(rd);
2435 break;
2436#else
0f8a249a 2437 goto nfpu_insn;
1f587329 2438#endif
0f8a249a
BS		 2439 case 0xc8:
2440 gen_op_load_fpr_FT1(rs2);
44e7757c 2441 tcg_gen_helper_0_0(helper_fitod);
0f8a249a
BS		 2442 gen_op_store_DT0_fpr(DFPREG(rd));
2443 break;
2444 case 0xc9:
2445 gen_op_load_fpr_FT1(rs2);
44e7757c 2446 tcg_gen_helper_0_0(helper_fstod);
0f8a249a
BS		 2447 gen_op_store_DT0_fpr(DFPREG(rd));
2448 break;
2449 case 0xcb: /* fqtod */
1f587329
BS		 2450#if defined(CONFIG_USER_ONLY)
2451 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2452 gen_clear_float_exceptions();
44e7757c 2453 tcg_gen_helper_0_0(helper_fqtod);
7e8c2b6c 2454 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2455 gen_op_store_DT0_fpr(DFPREG(rd));
2456 break;
2457#else
0f8a249a 2458 goto nfpu_insn;
1f587329 2459#endif
0f8a249a 2460 case 0xcc: /* fitoq */
1f587329
BS		 2461#if defined(CONFIG_USER_ONLY)
2462 gen_op_load_fpr_FT1(rs2);
44e7757c 2463 tcg_gen_helper_0_0(helper_fitoq);
1f587329
BS		 2464 gen_op_store_QT0_fpr(QFPREG(rd));
2465 break;
2466#else
0f8a249a 2467 goto nfpu_insn;
1f587329 2468#endif
0f8a249a 2469 case 0xcd: /* fstoq */
1f587329
BS		 2470#if defined(CONFIG_USER_ONLY)
2471 gen_op_load_fpr_FT1(rs2);
44e7757c 2472 tcg_gen_helper_0_0(helper_fstoq);
1f587329
BS		 2473 gen_op_store_QT0_fpr(QFPREG(rd));
2474 break;
2475#else
0f8a249a 2476 goto nfpu_insn;
1f587329 2477#endif
0f8a249a 2478 case 0xce: /* fdtoq */
1f587329
BS		 2479#if defined(CONFIG_USER_ONLY)
2480 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 2481 tcg_gen_helper_0_0(helper_fdtoq);
1f587329
BS		 2482 gen_op_store_QT0_fpr(QFPREG(rd));
2483 break;
2484#else
0f8a249a 2485 goto nfpu_insn;
1f587329 2486#endif
0f8a249a
BS		 2487 case 0xd1:
2488 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2489 gen_clear_float_exceptions();
44e7757c 2490 tcg_gen_helper_0_0(helper_fstoi);
7e8c2b6c 2491 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2492 gen_op_store_FT0_fpr(rd);
2493 break;
2494 case 0xd2:
2382dc6b 2495 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2496 gen_clear_float_exceptions();
44e7757c 2497 tcg_gen_helper_0_0(helper_fdtoi);
7e8c2b6c 2498 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2499 gen_op_store_FT0_fpr(rd);
2500 break;
2501 case 0xd3: /* fqtoi */
1f587329
BS		 2502#if defined(CONFIG_USER_ONLY)
2503 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2504 gen_clear_float_exceptions();
44e7757c 2505 tcg_gen_helper_0_0(helper_fqtoi);
7e8c2b6c 2506 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2507 gen_op_store_FT0_fpr(rd);
2508 break;
2509#else
0f8a249a 2510 goto nfpu_insn;
1f587329 2511#endif
3475187d 2512#ifdef TARGET_SPARC64
0f8a249a
BS		 2513 case 0x2: /* V9 fmovd */
2514 gen_op_load_fpr_DT0(DFPREG(rs2));
2515 gen_op_store_DT0_fpr(DFPREG(rd));
2516 break;
1f587329
BS		 2517 case 0x3: /* V9 fmovq */
2518#if defined(CONFIG_USER_ONLY)
2519 gen_op_load_fpr_QT0(QFPREG(rs2));
2520 gen_op_store_QT0_fpr(QFPREG(rd));
2521 break;
2522#else
2523 goto nfpu_insn;
2524#endif
0f8a249a
BS		 2525 case 0x6: /* V9 fnegd */
2526 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 2527 tcg_gen_helper_0_0(helper_fnegd);
0f8a249a
BS		 2528 gen_op_store_DT0_fpr(DFPREG(rd));
2529 break;
1f587329
BS		 2530 case 0x7: /* V9 fnegq */
2531#if defined(CONFIG_USER_ONLY)
2532 gen_op_load_fpr_QT1(QFPREG(rs2));
44e7757c 2533 tcg_gen_helper_0_0(helper_fnegq);
1f587329
BS		 2534 gen_op_store_QT0_fpr(QFPREG(rd));
2535 break;
2536#else
2537 goto nfpu_insn;
2538#endif
0f8a249a
BS		 2539 case 0xa: /* V9 fabsd */
2540 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2541 tcg_gen_helper_0_0(helper_fabsd);
0f8a249a
BS		 2542 gen_op_store_DT0_fpr(DFPREG(rd));
2543 break;
1f587329
BS		 2544 case 0xb: /* V9 fabsq */
2545#if defined(CONFIG_USER_ONLY)
2546 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2547 tcg_gen_helper_0_0(helper_fabsq);
1f587329
BS		 2548 gen_op_store_QT0_fpr(QFPREG(rd));
2549 break;
2550#else
2551 goto nfpu_insn;
2552#endif
0f8a249a
BS		 2553 case 0x81: /* V9 fstox */
2554 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2555 gen_clear_float_exceptions();
44e7757c 2556 tcg_gen_helper_0_0(helper_fstox);
7e8c2b6c 2557 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2558 gen_op_store_DT0_fpr(DFPREG(rd));
2559 break;
2560 case 0x82: /* V9 fdtox */
2561 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2562 gen_clear_float_exceptions();
44e7757c 2563 tcg_gen_helper_0_0(helper_fdtox);
7e8c2b6c 2564 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2565 gen_op_store_DT0_fpr(DFPREG(rd));
2566 break;
1f587329
BS		 2567 case 0x83: /* V9 fqtox */
2568#if defined(CONFIG_USER_ONLY)
2569 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2570 gen_clear_float_exceptions();
44e7757c 2571 tcg_gen_helper_0_0(helper_fqtox);
7e8c2b6c 2572 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2573 gen_op_store_DT0_fpr(DFPREG(rd));
2574 break;
2575#else
2576 goto nfpu_insn;
2577#endif
0f8a249a
BS		 2578 case 0x84: /* V9 fxtos */
2579 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2580 gen_clear_float_exceptions();
44e7757c 2581 tcg_gen_helper_0_0(helper_fxtos);
7e8c2b6c 2582 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2583 gen_op_store_FT0_fpr(rd);
2584 break;
2585 case 0x88: /* V9 fxtod */
2586 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2587 gen_clear_float_exceptions();
44e7757c 2588 tcg_gen_helper_0_0(helper_fxtod);
7e8c2b6c 2589 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2590 gen_op_store_DT0_fpr(DFPREG(rd));
2591 break;
0f8a249a 2592 case 0x8c: /* V9 fxtoq */
1f587329
BS		 2593#if defined(CONFIG_USER_ONLY)
2594 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2595 gen_clear_float_exceptions();
44e7757c 2596 tcg_gen_helper_0_0(helper_fxtoq);
7e8c2b6c 2597 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2598 gen_op_store_QT0_fpr(QFPREG(rd));
2599 break;
2600#else
0f8a249a 2601 goto nfpu_insn;
1f587329 2602#endif
0f8a249a
BS		 2603#endif
2604 default:
2605 goto illegal_insn;
2606 }
2607 } else if (xop == 0x35) { /* FPU Operations */
3475187d 2608#ifdef TARGET_SPARC64
0f8a249a 2609 int cond;
3475187d 2610#endif
6ae20372 2611 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 2612 goto jmp_insn;
0f8a249a 2613 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 2614 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2615 rs2 = GET_FIELD(insn, 27, 31);
2616 xop = GET_FIELD(insn, 18, 26);
3475187d 2617#ifdef TARGET_SPARC64
0f8a249a 2618 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
dcf24905
BS		 2619 int l1;
2620
2621 l1 = gen_new_label();
0f8a249a 2622 cond = GET_FIELD_SP(insn, 14, 17);
9322a4bf 2623 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372 2624 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
0425bee5 2625 tcg_const_tl(0), l1);
19f329ad 2626 gen_op_load_fpr_FT0(rs2);
0f8a249a 2627 gen_op_store_FT0_fpr(rd);
dcf24905 2628 gen_set_label(l1);
0f8a249a
BS		 2629 break;
2630 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
dcf24905
BS		 2631 int l1;
2632
2633 l1 = gen_new_label();
0f8a249a 2634 cond = GET_FIELD_SP(insn, 14, 17);
9322a4bf 2635 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372 2636 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
0425bee5 2637 tcg_const_tl(0), l1);
19f329ad 2638 gen_op_load_fpr_DT0(DFPREG(rs2));
2382dc6b 2639 gen_op_store_DT0_fpr(DFPREG(rd));
dcf24905 2640 gen_set_label(l1);
0f8a249a
BS		 2641 break;
2642 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1f587329 2643#if defined(CONFIG_USER_ONLY)
dcf24905
BS		 2644 int l1;
2645
2646 l1 = gen_new_label();
1f587329 2647 cond = GET_FIELD_SP(insn, 14, 17);
9322a4bf 2648 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372 2649 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
0425bee5 2650 tcg_const_tl(0), l1);
19f329ad 2651 gen_op_load_fpr_QT0(QFPREG(rs2));
1f587329 2652 gen_op_store_QT0_fpr(QFPREG(rd));
dcf24905 2653 gen_set_label(l1);
1f587329
BS		 2654 break;
2655#else
0f8a249a 2656 goto nfpu_insn;
1f587329 2657#endif
0f8a249a
BS		 2658 }
2659#endif
2660 switch (xop) {
3475187d 2661#ifdef TARGET_SPARC64
19f329ad
BS		 2662#define FMOVCC(size_FDQ, fcc) \
2663 { \
0425bee5 2664 TCGv r_cond; \
19f329ad
BS		 2665 int l1; \
2666 \
2667 l1 = gen_new_label(); \
19f329ad 2668 r_cond = tcg_temp_new(TCG_TYPE_TL); \
19f329ad
BS		 2669 cond = GET_FIELD_SP(insn, 14, 17); \
2670 gen_fcond(r_cond, fcc, cond); \
0425bee5
BS		 2671 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \
2672 tcg_const_tl(0), l1); \
19f329ad
BS		 2673 glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2674 glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2675 gen_set_label(l1); \
2676 }
0f8a249a 2677 case 0x001: /* V9 fmovscc %fcc0 */
19f329ad 2678 FMOVCC(F, 0);
0f8a249a
BS		 2679 break;
2680 case 0x002: /* V9 fmovdcc %fcc0 */
19f329ad 2681 FMOVCC(D, 0);
0f8a249a
BS		 2682 break;
2683 case 0x003: /* V9 fmovqcc %fcc0 */
1f587329 2684#if defined(CONFIG_USER_ONLY)
19f329ad 2685 FMOVCC(Q, 0);
1f587329
BS		 2686 break;
2687#else
0f8a249a 2688 goto nfpu_insn;
1f587329 2689#endif
0f8a249a 2690 case 0x041: /* V9 fmovscc %fcc1 */
19f329ad 2691 FMOVCC(F, 1);
0f8a249a
BS		 2692 break;
2693 case 0x042: /* V9 fmovdcc %fcc1 */
19f329ad 2694 FMOVCC(D, 1);
0f8a249a
BS		 2695 break;
2696 case 0x043: /* V9 fmovqcc %fcc1 */
1f587329 2697#if defined(CONFIG_USER_ONLY)
19f329ad 2698 FMOVCC(Q, 1);
1f587329
BS		 2699 break;
2700#else
0f8a249a 2701 goto nfpu_insn;
1f587329 2702#endif
0f8a249a 2703 case 0x081: /* V9 fmovscc %fcc2 */
19f329ad 2704 FMOVCC(F, 2);
0f8a249a
BS		 2705 break;
2706 case 0x082: /* V9 fmovdcc %fcc2 */
19f329ad 2707 FMOVCC(D, 2);
0f8a249a
BS		 2708 break;
2709 case 0x083: /* V9 fmovqcc %fcc2 */
1f587329 2710#if defined(CONFIG_USER_ONLY)
19f329ad 2711 FMOVCC(Q, 2);
1f587329
BS		 2712 break;
2713#else
0f8a249a 2714 goto nfpu_insn;
1f587329 2715#endif
0f8a249a 2716 case 0x0c1: /* V9 fmovscc %fcc3 */
19f329ad 2717 FMOVCC(F, 3);
0f8a249a
BS		 2718 break;
2719 case 0x0c2: /* V9 fmovdcc %fcc3 */
19f329ad 2720 FMOVCC(D, 3);
0f8a249a
BS		 2721 break;
2722 case 0x0c3: /* V9 fmovqcc %fcc3 */
1f587329 2723#if defined(CONFIG_USER_ONLY)
19f329ad 2724 FMOVCC(Q, 3);
1f587329
BS		 2725 break;
2726#else
0f8a249a 2727 goto nfpu_insn;
1f587329 2728#endif
19f329ad
BS		 2729#undef FMOVCC
2730#define FMOVCC(size_FDQ, icc) \
2731 { \
0425bee5 2732 TCGv r_cond; \
19f329ad
BS		 2733 int l1; \
2734 \
2735 l1 = gen_new_label(); \
19f329ad 2736 r_cond = tcg_temp_new(TCG_TYPE_TL); \
19f329ad
BS		 2737 cond = GET_FIELD_SP(insn, 14, 17); \
2738 gen_cond(r_cond, icc, cond); \
0425bee5
BS		 2739 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \
2740 tcg_const_tl(0), l1); \
19f329ad
BS		 2741 glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2742 glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2743 gen_set_label(l1); \
2744 }
2745
0f8a249a 2746 case 0x101: /* V9 fmovscc %icc */
19f329ad 2747 FMOVCC(F, 0);
0f8a249a
BS		 2748 break;
2749 case 0x102: /* V9 fmovdcc %icc */
19f329ad 2750 FMOVCC(D, 0);
0f8a249a 2751 case 0x103: /* V9 fmovqcc %icc */
1f587329 2752#if defined(CONFIG_USER_ONLY)
19f329ad 2753 FMOVCC(D, 0);
1f587329
BS		 2754 break;
2755#else
0f8a249a 2756 goto nfpu_insn;
1f587329 2757#endif
0f8a249a 2758 case 0x181: /* V9 fmovscc %xcc */
19f329ad 2759 FMOVCC(F, 1);
0f8a249a
BS		 2760 break;
2761 case 0x182: /* V9 fmovdcc %xcc */
19f329ad 2762 FMOVCC(D, 1);
0f8a249a
BS		 2763 break;
2764 case 0x183: /* V9 fmovqcc %xcc */
1f587329 2765#if defined(CONFIG_USER_ONLY)
19f329ad 2766 FMOVCC(Q, 1);
1f587329
BS		 2767 break;
2768#else
0f8a249a
BS		 2769 goto nfpu_insn;
2770#endif
19f329ad 2771#undef FMOVCC
1f587329
BS		 2772#endif
2773 case 0x51: /* fcmps, V9 %fcc */
0f8a249a
BS		 2774 gen_op_load_fpr_FT0(rs1);
2775 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2776 gen_op_fcmps(rd & 3);
0f8a249a 2777 break;
1f587329 2778 case 0x52: /* fcmpd, V9 %fcc */
0f8a249a
BS		 2779 gen_op_load_fpr_DT0(DFPREG(rs1));
2780 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2781 gen_op_fcmpd(rd & 3);
0f8a249a 2782 break;
1f587329
BS		 2783 case 0x53: /* fcmpq, V9 %fcc */
2784#if defined(CONFIG_USER_ONLY)
2785 gen_op_load_fpr_QT0(QFPREG(rs1));
2786 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2787 gen_op_fcmpq(rd & 3);
1f587329
BS		 2788 break;
2789#else /* !defined(CONFIG_USER_ONLY) */
0f8a249a 2790 goto nfpu_insn;
1f587329 2791#endif
0f8a249a
BS		 2792 case 0x55: /* fcmpes, V9 %fcc */
2793 gen_op_load_fpr_FT0(rs1);
2794 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2795 gen_op_fcmpes(rd & 3);
0f8a249a
BS		 2796 break;
2797 case 0x56: /* fcmped, V9 %fcc */
2798 gen_op_load_fpr_DT0(DFPREG(rs1));
2799 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2800 gen_op_fcmped(rd & 3);
0f8a249a 2801 break;
1f587329
BS		 2802 case 0x57: /* fcmpeq, V9 %fcc */
2803#if defined(CONFIG_USER_ONLY)
2804 gen_op_load_fpr_QT0(QFPREG(rs1));
2805 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2806 gen_op_fcmpeq(rd & 3);
1f587329
BS		 2807 break;
2808#else/* !defined(CONFIG_USER_ONLY) */
0f8a249a 2809 goto nfpu_insn;
1f587329 2810#endif
0f8a249a
BS		 2811 default:
2812 goto illegal_insn;
2813 }
0f8a249a
BS		 2814 } else if (xop == 0x2) {
2815 // clr/mov shortcut
e80cfcfc
FB		 2816
2817 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 2818 if (rs1 == 0) {
1a2fb1c0 2819 // or %g0, x, y -> mov T0, x; mov y, T0
0f8a249a
BS		 2820 if (IS_IMM) { /* immediate */
2821 rs2 = GET_FIELDs(insn, 19, 31);
9c6c6662 2822 gen_movl_TN_reg(rd, tcg_const_tl((int)rs2));
0f8a249a
BS		 2823 } else { /* register */
2824 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 2825 gen_movl_reg_TN(rs2, cpu_dst);
9c6c6662 2826 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a 2827 }
0f8a249a 2828 } else {
9322a4bf 2829 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a 2830 if (IS_IMM) { /* immediate */
0f8a249a 2831 rs2 = GET_FIELDs(insn, 19, 31);
6ae20372 2832 tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
9c6c6662 2833 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 2834 } else { /* register */
2835 // or x, %g0, y -> mov T1, x; mov y, T1
2836 rs2 = GET_FIELD(insn, 27, 31);
2837 if (rs2 != 0) {
6ae20372
BS		 2838 gen_movl_reg_TN(rs2, cpu_src2);
2839 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
9c6c6662 2840 gen_movl_TN_reg(rd, cpu_dst);
6f551262 2841 } else
9c6c6662 2842 gen_movl_TN_reg(rd, cpu_src1);
0f8a249a 2843 }
0f8a249a 2844 }
83469015 2845#ifdef TARGET_SPARC64
0f8a249a 2846 } else if (xop == 0x25) { /* sll, V9 sllx */
9322a4bf 2847 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a 2848 if (IS_IMM) { /* immediate */
83469015 2849 rs2 = GET_FIELDs(insn, 20, 31);
1a2fb1c0 2850 if (insn & (1 << 12)) {
6ae20372 2851 tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
1a2fb1c0 2852 } else {
6ae20372
BS		 2853 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2854 tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
1a2fb1c0 2855 }
0f8a249a 2856 } else { /* register */
83469015 2857 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 2858 gen_movl_reg_TN(rs2, cpu_src2);
1a2fb1c0 2859 if (insn & (1 << 12)) {
6ae20372
BS		 2860 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2861 tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 2862 } else {
6ae20372
BS		 2863 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2864 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2865 tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 2866 }
83469015 2867 }
6ae20372 2868 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a 2869 } else if (xop == 0x26) { /* srl, V9 srlx */
9322a4bf 2870 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a 2871 if (IS_IMM) { /* immediate */
83469015 2872 rs2 = GET_FIELDs(insn, 20, 31);
1a2fb1c0 2873 if (insn & (1 << 12)) {
6ae20372 2874 tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
1a2fb1c0 2875 } else {
6ae20372
BS		 2876 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2877 tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
1a2fb1c0 2878 }
0f8a249a 2879 } else { /* register */
83469015 2880 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 2881 gen_movl_reg_TN(rs2, cpu_src2);
1a2fb1c0 2882 if (insn & (1 << 12)) {
6ae20372
BS		 2883 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2884 tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 2885 } else {
6ae20372
BS		 2886 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2887 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2888 tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 2889 }
83469015 2890 }
6ae20372 2891 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a 2892 } else if (xop == 0x27) { /* sra, V9 srax */
9322a4bf 2893 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a 2894 if (IS_IMM) { /* immediate */
83469015 2895 rs2 = GET_FIELDs(insn, 20, 31);
1a2fb1c0 2896 if (insn & (1 << 12)) {
6ae20372 2897 tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
1a2fb1c0 2898 } else {
6ae20372
BS		 2899 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2900 tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2901 tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
1a2fb1c0 2902 }
0f8a249a 2903 } else { /* register */
83469015 2904 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 2905 gen_movl_reg_TN(rs2, cpu_src2);
1a2fb1c0 2906 if (insn & (1 << 12)) {
6ae20372
BS		 2907 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2908 tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 2909 } else {
6ae20372
BS		 2910 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2911 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2912 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 2913 }
83469015 2914 }
6ae20372 2915 gen_movl_TN_reg(rd, cpu_dst);
e80cfcfc 2916#endif
fcc72045 2917 } else if (xop < 0x36) {
9322a4bf 2918 cpu_src1 = get_src1(insn, cpu_src1);
a49d9390 2919 cpu_src2 = get_src2(insn, cpu_src2);
cf495bcf
FB		 2920 if (xop < 0x20) {
2921 switch (xop & ~0x10) {
2922 case 0x0:
2923 if (xop & 0x10)
6ae20372 2924 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
cf495bcf 2925 else
6ae20372 2926 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
cf495bcf
FB		 2927 break;
2928 case 0x1:
6ae20372 2929 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
cf495bcf 2930 if (xop & 0x10)
6ae20372 2931 gen_op_logic_cc(cpu_dst);
cf495bcf
FB		 2932 break;
2933 case 0x2:
6ae20372 2934 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
0f8a249a 2935 if (xop & 0x10)
6ae20372 2936 gen_op_logic_cc(cpu_dst);
0f8a249a 2937 break;
cf495bcf 2938 case 0x3:
6ae20372 2939 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
cf495bcf 2940 if (xop & 0x10)
6ae20372 2941 gen_op_logic_cc(cpu_dst);
cf495bcf
FB		 2942 break;
2943 case 0x4:
2944 if (xop & 0x10)
6ae20372 2945 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
cf495bcf 2946 else
6ae20372 2947 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
cf495bcf
FB		 2948 break;
2949 case 0x5:
6ae20372
BS		 2950 tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2951 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
cf495bcf 2952 if (xop & 0x10)
6ae20372 2953 gen_op_logic_cc(cpu_dst);
cf495bcf
FB		 2954 break;
2955 case 0x6:
6ae20372
BS		 2956 tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2957 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
cf495bcf 2958 if (xop & 0x10)
6ae20372 2959 gen_op_logic_cc(cpu_dst);
cf495bcf
FB		 2960 break;
2961 case 0x7:
6ae20372
BS		 2962 tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2963 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
cf495bcf 2964 if (xop & 0x10)
6ae20372 2965 gen_op_logic_cc(cpu_dst);
cf495bcf
FB		 2966 break;
2967 case 0x8:
cf495bcf 2968 if (xop & 0x10)
6ae20372 2969 gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
38bc628b 2970 else {
dc99a3f2 2971 gen_mov_reg_C(cpu_tmp0, cpu_psr);
6ae20372
BS		 2972 tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
2973 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
38bc628b 2974 }
cf495bcf 2975 break;
ded3ab80 2976#ifdef TARGET_SPARC64
0f8a249a 2977 case 0x9: /* V9 mulx */
6ae20372 2978 tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
ded3ab80
PB		 2979 break;
2980#endif
cf495bcf 2981 case 0xa:
6ae20372 2982 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
cf495bcf 2983 if (xop & 0x10)
6ae20372 2984 gen_op_logic_cc(cpu_dst);
cf495bcf
FB		 2985 break;
2986 case 0xb:
6ae20372 2987 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
cf495bcf 2988 if (xop & 0x10)
6ae20372 2989 gen_op_logic_cc(cpu_dst);
cf495bcf
FB		 2990 break;
2991 case 0xc:
cf495bcf 2992 if (xop & 0x10)
6ae20372 2993 gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
38bc628b 2994 else {
dc99a3f2 2995 gen_mov_reg_C(cpu_tmp0, cpu_psr);
6ae20372
BS		 2996 tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
2997 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
38bc628b 2998 }
cf495bcf 2999 break;
ded3ab80 3000#ifdef TARGET_SPARC64
0f8a249a 3001 case 0xd: /* V9 udivx */
6ae20372
BS		 3002 gen_trap_ifdivzero_tl(cpu_src2);
3003 tcg_gen_divu_i64(cpu_dst, cpu_src1, cpu_src2);
ded3ab80
PB		 3004 break;
3005#endif
cf495bcf 3006 case 0xe:
6ae20372 3007 tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1, cpu_src2);
cf495bcf 3008 if (xop & 0x10)
6ae20372 3009 gen_op_div_cc(cpu_dst);
cf495bcf
FB		 3010 break;
3011 case 0xf:
6ae20372 3012 tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1, cpu_src2);
cf495bcf 3013 if (xop & 0x10)
6ae20372 3014 gen_op_div_cc(cpu_dst);
cf495bcf
FB		 3015 break;
3016 default:
3017 goto illegal_insn;
3018 }
6ae20372 3019 gen_movl_TN_reg(rd, cpu_dst);
cf495bcf
FB		 3020 } else {
3021 switch (xop) {
0f8a249a 3022 case 0x20: /* taddcc */
6ae20372
BS		 3023 gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3024 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 3025 break;
3026 case 0x21: /* tsubcc */
6ae20372
BS		 3027 gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3028 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 3029 break;
3030 case 0x22: /* taddcctv */
6ae20372
BS		 3031 save_state(dc, cpu_cond);
3032 gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3033 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 3034 break;
3035 case 0x23: /* tsubcctv */
6ae20372
BS		 3036 save_state(dc, cpu_cond);
3037 gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3038 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a 3039 break;
cf495bcf 3040 case 0x24: /* mulscc */
6ae20372
BS		 3041 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3042 gen_movl_TN_reg(rd, cpu_dst);
cf495bcf 3043 break;
83469015 3044#ifndef TARGET_SPARC64
0f8a249a 3045 case 0x25: /* sll */
6ae20372
BS		 3046 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3047 tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3048 gen_movl_TN_reg(rd, cpu_dst);
cf495bcf 3049 break;
83469015 3050 case 0x26: /* srl */
6ae20372
BS		 3051 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3052 tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3053 gen_movl_TN_reg(rd, cpu_dst);
cf495bcf 3054 break;
83469015 3055 case 0x27: /* sra */
6ae20372
BS		 3056 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3057 tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3058 gen_movl_TN_reg(rd, cpu_dst);
cf495bcf 3059 break;
83469015 3060#endif
cf495bcf
FB		 3061 case 0x30:
3062 {
cf495bcf 3063 switch(rd) {
3475187d 3064 case 0: /* wry */
6ae20372
BS		 3065 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3066 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, y));
cf495bcf 3067 break;
65fe7b09
BS		 3068#ifndef TARGET_SPARC64
3069 case 0x01 ... 0x0f: /* undefined in the
3070 SPARCv8 manual, nop
3071 on the microSPARC
3072 II */
3073 case 0x10 ... 0x1f: /* implementation-dependent
3074 in the SPARCv8
3075 manual, nop on the
3076 microSPARC II */
3077 break;
3078#else
0f8a249a 3079 case 0x2: /* V9 wrccr */
6ae20372
BS		 3080 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3081 tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
0f8a249a
BS		 3082 break;
3083 case 0x3: /* V9 wrasi */
6ae20372
BS		 3084 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3085 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3086 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
0f8a249a
BS		 3087 break;
3088 case 0x6: /* V9 wrfprs */
6ae20372
BS		 3089 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3090 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3091 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
6ae20372 3092 save_state(dc, cpu_cond);
3299908c 3093 gen_op_next_insn();
57fec1fe 3094 tcg_gen_exit_tb(0);
3299908c 3095 dc->is_br = 1;
0f8a249a
BS		 3096 break;
3097 case 0xf: /* V9 sir, nop if user */
3475187d 3098#if !defined(CONFIG_USER_ONLY)
0f8a249a 3099 if (supervisor(dc))
1a2fb1c0 3100 ; // XXX
3475187d 3101#endif
0f8a249a
BS		 3102 break;
3103 case 0x13: /* Graphics Status */
6ae20372 3104 if (gen_trap_ifnofpu(dc, cpu_cond))
725cb90b 3105 goto jmp_insn;
6ae20372
BS		 3106 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3107 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, gsr));
0f8a249a
BS		 3108 break;
3109 case 0x17: /* Tick compare */
83469015 3110#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3111 if (!supervisor(dc))
3112 goto illegal_insn;
83469015 3113#endif
ccd4a219
BS		 3114 {
3115 TCGv r_tickptr;
3116
6ae20372
BS		 3117 tcg_gen_xor_tl(cpu_dst, cpu_src1,
3118 cpu_src2);
3119 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
ccd4a219
BS		 3120 tick_cmpr));
3121 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3122 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3123 offsetof(CPUState, tick));
3124 tcg_gen_helper_0_2(helper_tick_set_limit,
6ae20372 3125 r_tickptr, cpu_dst);
ccd4a219 3126 }
0f8a249a
BS		 3127 break;
3128 case 0x18: /* System tick */
83469015 3129#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3130 if (!supervisor(dc))
3131 goto illegal_insn;
83469015 3132#endif
ccd4a219
BS		 3133 {
3134 TCGv r_tickptr;
3135
6ae20372
BS		 3136 tcg_gen_xor_tl(cpu_dst, cpu_src1,
3137 cpu_src2);
ccd4a219
BS		 3138 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3139 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3140 offsetof(CPUState, stick));
3141 tcg_gen_helper_0_2(helper_tick_set_count,
6ae20372 3142 r_tickptr, cpu_dst);
ccd4a219 3143 }
0f8a249a
BS		 3144 break;
3145 case 0x19: /* System tick compare */
83469015 3146#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3147 if (!supervisor(dc))
3148 goto illegal_insn;
3475187d 3149#endif
ccd4a219
BS		 3150 {
3151 TCGv r_tickptr;
3152
6ae20372
BS		 3153 tcg_gen_xor_tl(cpu_dst, cpu_src1,
3154 cpu_src2);
3155 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
ccd4a219
BS		 3156 stick_cmpr));
3157 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3158 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3159 offsetof(CPUState, stick));
3160 tcg_gen_helper_0_2(helper_tick_set_limit,
6ae20372 3161 r_tickptr, cpu_dst);
ccd4a219 3162 }
0f8a249a 3163 break;
83469015 3164
0f8a249a
BS		 3165 case 0x10: /* Performance Control */
3166 case 0x11: /* Performance Instrumentation Counter */
3167 case 0x12: /* Dispatch Control */
3168 case 0x14: /* Softint set */
3169 case 0x15: /* Softint clear */
3170 case 0x16: /* Softint write */
83469015 3171#endif
3475187d 3172 default:
cf495bcf
FB		 3173 goto illegal_insn;
3174 }
3175 }
3176 break;
e8af50a3 3177#if !defined(CONFIG_USER_ONLY)
af7bf89b 3178 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3 3179 {
0f8a249a
BS		 3180 if (!supervisor(dc))
3181 goto priv_insn;
3475187d 3182#ifdef TARGET_SPARC64
0f8a249a
BS		 3183 switch (rd) {
3184 case 0:
72a9747b 3185 tcg_gen_helper_0_0(helper_saved);
0f8a249a
BS		 3186 break;
3187 case 1:
72a9747b 3188 tcg_gen_helper_0_0(helper_restored);
0f8a249a 3189 break;
e9ebed4d
BS		 3190 case 2: /* UA2005 allclean */
3191 case 3: /* UA2005 otherw */
3192 case 4: /* UA2005 normalw */
3193 case 5: /* UA2005 invalw */
3194 // XXX
0f8a249a 3195 default:
3475187d
FB		 3196 goto illegal_insn;
3197 }
3198#else
6ae20372
BS		 3199 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3200 tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3201 save_state(dc, cpu_cond);
9e61bde5 3202 gen_op_next_insn();
57fec1fe 3203 tcg_gen_exit_tb(0);
0f8a249a 3204 dc->is_br = 1;
3475187d 3205#endif
e8af50a3
FB		 3206 }
3207 break;
af7bf89b 3208 case 0x32: /* wrwim, V9 wrpr */
e8af50a3 3209 {
0f8a249a
BS		 3210 if (!supervisor(dc))
3211 goto priv_insn;
6ae20372 3212 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3475187d 3213#ifdef TARGET_SPARC64
0f8a249a
BS		 3214 switch (rd) {
3215 case 0: // tpc
375ee38b
BS		 3216 {
3217 TCGv r_tsptr;
3218
3219 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3220 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3221 offsetof(CPUState, tsptr));
6ae20372 3222 tcg_gen_st_tl(cpu_dst, r_tsptr,
375ee38b
BS		 3223 offsetof(trap_state, tpc));
3224 }
0f8a249a
BS		 3225 break;
3226 case 1: // tnpc
375ee38b
BS		 3227 {
3228 TCGv r_tsptr;
3229
3230 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3231 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3232 offsetof(CPUState, tsptr));
6ae20372 3233 tcg_gen_st_tl(cpu_dst, r_tsptr,
375ee38b
BS		 3234 offsetof(trap_state, tnpc));
3235 }
0f8a249a
BS		 3236 break;
3237 case 2: // tstate
375ee38b
BS		 3238 {
3239 TCGv r_tsptr;
3240
3241 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3242 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3243 offsetof(CPUState, tsptr));
6ae20372 3244 tcg_gen_st_tl(cpu_dst, r_tsptr,
375ee38b
BS		 3245 offsetof(trap_state, tstate));
3246 }
0f8a249a
BS		 3247 break;
3248 case 3: // tt
375ee38b
BS		 3249 {
3250 TCGv r_tsptr;
3251
3252 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3253 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3254 offsetof(CPUState, tsptr));
6ae20372 3255 tcg_gen_st_i32(cpu_dst, r_tsptr,
375ee38b
BS		 3256 offsetof(trap_state, tt));
3257 }
0f8a249a
BS		 3258 break;
3259 case 4: // tick
ccd4a219
BS		 3260 {
3261 TCGv r_tickptr;
3262
3263 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3264 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3265 offsetof(CPUState, tick));
3266 tcg_gen_helper_0_2(helper_tick_set_count,
6ae20372 3267 r_tickptr, cpu_dst);
ccd4a219 3268 }
0f8a249a
BS		 3269 break;
3270 case 5: // tba
6ae20372 3271 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
0f8a249a
BS		 3272 break;
3273 case 6: // pstate
6ae20372
BS		 3274 save_state(dc, cpu_cond);
3275 tcg_gen_helper_0_1(helper_wrpstate, cpu_dst);
ded3ab80 3276 gen_op_next_insn();
57fec1fe 3277 tcg_gen_exit_tb(0);
ded3ab80 3278 dc->is_br = 1;
0f8a249a
BS		 3279 break;
3280 case 7: // tl
6ae20372 3281 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3282 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
0f8a249a
BS		 3283 break;
3284 case 8: // pil
6ae20372 3285 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3286 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
0f8a249a
BS		 3287 break;
3288 case 9: // cwp
6ae20372 3289 tcg_gen_helper_0_1(helper_wrcwp, cpu_dst);
0f8a249a
BS		 3290 break;
3291 case 10: // cansave
6ae20372 3292 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3293 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
0f8a249a
BS		 3294 break;
3295 case 11: // canrestore
6ae20372 3296 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3297 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
0f8a249a
BS		 3298 break;
3299 case 12: // cleanwin
6ae20372 3300 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3301 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
0f8a249a
BS		 3302 break;
3303 case 13: // otherwin
6ae20372 3304 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3305 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
0f8a249a
BS		 3306 break;
3307 case 14: // wstate
6ae20372 3308 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3309 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
0f8a249a 3310 break;
e9ebed4d 3311 case 16: // UA2005 gl
6ae20372 3312 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3313 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 3314 break;
3315 case 26: // UA2005 strand status
3316 if (!hypervisor(dc))
3317 goto priv_insn;
6ae20372 3318 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3319 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
e9ebed4d 3320 break;
0f8a249a
BS		 3321 default:
3322 goto illegal_insn;
3323 }
3475187d 3324#else
6ae20372
BS		 3325 tcg_gen_andi_tl(cpu_dst, cpu_dst, ((1 << NWINDOWS) - 1));
3326 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3327 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
3475187d 3328#endif
e8af50a3
FB		 3329 }
3330 break;
e9ebed4d 3331 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 3332 {
e9ebed4d 3333#ifndef TARGET_SPARC64
0f8a249a
BS		 3334 if (!supervisor(dc))
3335 goto priv_insn;
6ae20372
BS		 3336 tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
3337 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
e9ebed4d
BS		 3338#else
3339 if (!hypervisor(dc))
3340 goto priv_insn;
6ae20372 3341 tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
e9ebed4d
BS		 3342 switch (rd) {
3343 case 0: // hpstate
3344 // XXX gen_op_wrhpstate();
6ae20372 3345 save_state(dc, cpu_cond);
e9ebed4d 3346 gen_op_next_insn();
57fec1fe 3347 tcg_gen_exit_tb(0);
e9ebed4d
BS		 3348 dc->is_br = 1;
3349 break;
3350 case 1: // htstate
3351 // XXX gen_op_wrhtstate();
3352 break;
3353 case 3: // hintp
6ae20372 3354 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3355 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
e9ebed4d
BS		 3356 break;
3357 case 5: // htba
6ae20372 3358 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3359 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
e9ebed4d
BS		 3360 break;
3361 case 31: // hstick_cmpr
ccd4a219
BS		 3362 {
3363 TCGv r_tickptr;
3364
6ae20372 3365 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
ccd4a219
BS		 3366 hstick_cmpr));
3367 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3368 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3369 offsetof(CPUState, hstick));
3370 tcg_gen_helper_0_2(helper_tick_set_limit,
6ae20372 3371 r_tickptr, cpu_dst);
ccd4a219 3372 }
e9ebed4d
BS		 3373 break;
3374 case 6: // hver readonly
3375 default:
3376 goto illegal_insn;
3377 }
3378#endif
e8af50a3
FB		 3379 }
3380 break;
3381#endif
3475187d 3382#ifdef TARGET_SPARC64
0f8a249a
BS		 3383 case 0x2c: /* V9 movcc */
3384 {
3385 int cc = GET_FIELD_SP(insn, 11, 12);
3386 int cond = GET_FIELD_SP(insn, 14, 17);
748b9d8e 3387 TCGv r_cond;
00f219bf
BS		 3388 int l1;
3389
748b9d8e 3390 r_cond = tcg_temp_new(TCG_TYPE_TL);
0f8a249a
BS		 3391 if (insn & (1 << 18)) {
3392 if (cc == 0)
748b9d8e 3393 gen_cond(r_cond, 0, cond);
0f8a249a 3394 else if (cc == 2)
748b9d8e 3395 gen_cond(r_cond, 1, cond);
0f8a249a
BS		 3396 else
3397 goto illegal_insn;
3398 } else {
748b9d8e 3399 gen_fcond(r_cond, cc, cond);
0f8a249a 3400 }
00f219bf
BS		 3401
3402 l1 = gen_new_label();
3403
748b9d8e
BS		 3404 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond,
3405 tcg_const_tl(0), l1);
00f219bf
BS		 3406 if (IS_IMM) { /* immediate */
3407 rs2 = GET_FIELD_SPs(insn, 0, 10);
9c6c6662 3408 gen_movl_TN_reg(rd, tcg_const_tl((int)rs2));
00f219bf
BS		 3409 } else {
3410 rs2 = GET_FIELD_SP(insn, 0, 4);
9c6c6662
BS		 3411 gen_movl_reg_TN(rs2, cpu_tmp0);
3412 gen_movl_TN_reg(rd, cpu_tmp0);
00f219bf 3413 }
00f219bf 3414 gen_set_label(l1);
0f8a249a
BS		 3415 break;
3416 }
3417 case 0x2d: /* V9 sdivx */
6ae20372
BS		 3418 gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3419 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 3420 break;
3421 case 0x2e: /* V9 popc */
3422 {
a49d9390 3423 cpu_src2 = get_src2(insn, cpu_src2);
6ae20372
BS		 3424 tcg_gen_helper_1_1(helper_popc, cpu_dst,
3425 cpu_src2);
3426 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 3427 }
3428 case 0x2f: /* V9 movr */
3429 {
3430 int cond = GET_FIELD_SP(insn, 10, 12);
00f219bf
BS		 3431 int l1;
3432
9322a4bf 3433 cpu_src1 = get_src1(insn, cpu_src1);
00f219bf
BS		 3434
3435 l1 = gen_new_label();
3436
6ae20372 3437 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
0425bee5 3438 tcg_const_tl(0), l1);
0f8a249a
BS		 3439 if (IS_IMM) { /* immediate */
3440 rs2 = GET_FIELD_SPs(insn, 0, 9);
9c6c6662 3441 gen_movl_TN_reg(rd, tcg_const_tl((int)rs2));
00f219bf 3442 } else {
0f8a249a 3443 rs2 = GET_FIELD_SP(insn, 0, 4);
9c6c6662
BS		 3444 gen_movl_reg_TN(rs2, cpu_tmp0);
3445 gen_movl_TN_reg(rd, cpu_tmp0);
0f8a249a 3446 }
00f219bf 3447 gen_set_label(l1);
0f8a249a
BS		 3448 break;
3449 }
3450#endif
3451 default:
3452 goto illegal_insn;
3453 }
3454 }
3299908c
BS		 3455 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3456#ifdef TARGET_SPARC64
3457 int opf = GET_FIELD_SP(insn, 5, 13);
3458 rs1 = GET_FIELD(insn, 13, 17);
3459 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 3460 if (gen_trap_ifnofpu(dc, cpu_cond))
e9ebed4d 3461 goto jmp_insn;
3299908c
BS		 3462
3463 switch (opf) {
e9ebed4d
BS		 3464 case 0x000: /* VIS I edge8cc */
3465 case 0x001: /* VIS II edge8n */
3466 case 0x002: /* VIS I edge8lcc */
3467 case 0x003: /* VIS II edge8ln */
3468 case 0x004: /* VIS I edge16cc */
3469 case 0x005: /* VIS II edge16n */
3470 case 0x006: /* VIS I edge16lcc */
3471 case 0x007: /* VIS II edge16ln */
3472 case 0x008: /* VIS I edge32cc */
3473 case 0x009: /* VIS II edge32n */
3474 case 0x00a: /* VIS I edge32lcc */
3475 case 0x00b: /* VIS II edge32ln */
3476 // XXX
3477 goto illegal_insn;
3478 case 0x010: /* VIS I array8 */
9322a4bf 3479 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372
BS		 3480 gen_movl_reg_TN(rs2, cpu_src2);
3481 tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3482 cpu_src2);
3483 gen_movl_TN_reg(rd, cpu_dst);
e9ebed4d
BS		 3484 break;
3485 case 0x012: /* VIS I array16 */
9322a4bf 3486 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372
BS		 3487 gen_movl_reg_TN(rs2, cpu_src2);
3488 tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3489 cpu_src2);
3490 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3491 gen_movl_TN_reg(rd, cpu_dst);
e9ebed4d
BS		 3492 break;
3493 case 0x014: /* VIS I array32 */
9322a4bf 3494 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372
BS		 3495 gen_movl_reg_TN(rs2, cpu_src2);
3496 tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3497 cpu_src2);
3498 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3499 gen_movl_TN_reg(rd, cpu_dst);
e9ebed4d 3500 break;
3299908c 3501 case 0x018: /* VIS I alignaddr */
9322a4bf 3502 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372
BS		 3503 gen_movl_reg_TN(rs2, cpu_src2);
3504 tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3505 cpu_src2);
3506 gen_movl_TN_reg(rd, cpu_dst);
3299908c 3507 break;
e9ebed4d 3508 case 0x019: /* VIS II bmask */
3299908c 3509 case 0x01a: /* VIS I alignaddrl */
3299908c 3510 // XXX
e9ebed4d
BS		 3511 goto illegal_insn;
3512 case 0x020: /* VIS I fcmple16 */
2382dc6b
BS		 3513 gen_op_load_fpr_DT0(DFPREG(rs1));
3514 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3515 tcg_gen_helper_0_0(helper_fcmple16);
2382dc6b 3516 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3517 break;
3518 case 0x022: /* VIS I fcmpne16 */
2382dc6b
BS		 3519 gen_op_load_fpr_DT0(DFPREG(rs1));
3520 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3521 tcg_gen_helper_0_0(helper_fcmpne16);
2382dc6b 3522 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c 3523 break;
e9ebed4d 3524 case 0x024: /* VIS I fcmple32 */
2382dc6b
BS		 3525 gen_op_load_fpr_DT0(DFPREG(rs1));
3526 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3527 tcg_gen_helper_0_0(helper_fcmple32);
2382dc6b 3528 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3529 break;
3530 case 0x026: /* VIS I fcmpne32 */
2382dc6b
BS		 3531 gen_op_load_fpr_DT0(DFPREG(rs1));
3532 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3533 tcg_gen_helper_0_0(helper_fcmpne32);
2382dc6b 3534 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3535 break;
3536 case 0x028: /* VIS I fcmpgt16 */
2382dc6b
BS		 3537 gen_op_load_fpr_DT0(DFPREG(rs1));
3538 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3539 tcg_gen_helper_0_0(helper_fcmpgt16);
2382dc6b 3540 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3541 break;
3542 case 0x02a: /* VIS I fcmpeq16 */
2382dc6b
BS		 3543 gen_op_load_fpr_DT0(DFPREG(rs1));
3544 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3545 tcg_gen_helper_0_0(helper_fcmpeq16);
2382dc6b 3546 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3547 break;
3548 case 0x02c: /* VIS I fcmpgt32 */
2382dc6b
BS		 3549 gen_op_load_fpr_DT0(DFPREG(rs1));
3550 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3551 tcg_gen_helper_0_0(helper_fcmpgt32);
2382dc6b 3552 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3553 break;
3554 case 0x02e: /* VIS I fcmpeq32 */
2382dc6b
BS		 3555 gen_op_load_fpr_DT0(DFPREG(rs1));
3556 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3557 tcg_gen_helper_0_0(helper_fcmpeq32);
2382dc6b 3558 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3559 break;
3560 case 0x031: /* VIS I fmul8x16 */
2382dc6b
BS		 3561 gen_op_load_fpr_DT0(DFPREG(rs1));
3562 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3563 tcg_gen_helper_0_0(helper_fmul8x16);
2382dc6b 3564 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3565 break;
3566 case 0x033: /* VIS I fmul8x16au */
2382dc6b
BS		 3567 gen_op_load_fpr_DT0(DFPREG(rs1));
3568 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3569 tcg_gen_helper_0_0(helper_fmul8x16au);
2382dc6b 3570 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3571 break;
3572 case 0x035: /* VIS I fmul8x16al */
2382dc6b
BS		 3573 gen_op_load_fpr_DT0(DFPREG(rs1));
3574 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3575 tcg_gen_helper_0_0(helper_fmul8x16al);
2382dc6b 3576 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3577 break;
3578 case 0x036: /* VIS I fmul8sux16 */
2382dc6b
BS		 3579 gen_op_load_fpr_DT0(DFPREG(rs1));
3580 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3581 tcg_gen_helper_0_0(helper_fmul8sux16);
2382dc6b 3582 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3583 break;
3584 case 0x037: /* VIS I fmul8ulx16 */
2382dc6b
BS		 3585 gen_op_load_fpr_DT0(DFPREG(rs1));
3586 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3587 tcg_gen_helper_0_0(helper_fmul8ulx16);
2382dc6b 3588 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3589 break;
3590 case 0x038: /* VIS I fmuld8sux16 */
2382dc6b
BS		 3591 gen_op_load_fpr_DT0(DFPREG(rs1));
3592 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3593 tcg_gen_helper_0_0(helper_fmuld8sux16);
2382dc6b 3594 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3595 break;
3596 case 0x039: /* VIS I fmuld8ulx16 */
2382dc6b
BS		 3597 gen_op_load_fpr_DT0(DFPREG(rs1));
3598 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3599 tcg_gen_helper_0_0(helper_fmuld8ulx16);
2382dc6b 3600 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3601 break;
3602 case 0x03a: /* VIS I fpack32 */
3603 case 0x03b: /* VIS I fpack16 */
3604 case 0x03d: /* VIS I fpackfix */
3605 case 0x03e: /* VIS I pdist */
3606 // XXX
3607 goto illegal_insn;
3299908c 3608 case 0x048: /* VIS I faligndata */
2382dc6b
BS		 3609 gen_op_load_fpr_DT0(DFPREG(rs1));
3610 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3611 tcg_gen_helper_0_0(helper_faligndata);
2382dc6b 3612 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c 3613 break;
e9ebed4d 3614 case 0x04b: /* VIS I fpmerge */
2382dc6b
BS		 3615 gen_op_load_fpr_DT0(DFPREG(rs1));
3616 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3617 tcg_gen_helper_0_0(helper_fpmerge);
2382dc6b 3618 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3619 break;
3620 case 0x04c: /* VIS II bshuffle */
3621 // XXX
3622 goto illegal_insn;
3623 case 0x04d: /* VIS I fexpand */
2382dc6b
BS		 3624 gen_op_load_fpr_DT0(DFPREG(rs1));
3625 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3626 tcg_gen_helper_0_0(helper_fexpand);
2382dc6b 3627 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3628 break;
3629 case 0x050: /* VIS I fpadd16 */
2382dc6b
BS		 3630 gen_op_load_fpr_DT0(DFPREG(rs1));
3631 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3632 tcg_gen_helper_0_0(helper_fpadd16);
2382dc6b 3633 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3634 break;
3635 case 0x051: /* VIS I fpadd16s */
3636 gen_op_load_fpr_FT0(rs1);
3637 gen_op_load_fpr_FT1(rs2);
44e7757c 3638 tcg_gen_helper_0_0(helper_fpadd16s);
e9ebed4d
BS		 3639 gen_op_store_FT0_fpr(rd);
3640 break;
3641 case 0x052: /* VIS I fpadd32 */
2382dc6b
BS		 3642 gen_op_load_fpr_DT0(DFPREG(rs1));
3643 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3644 tcg_gen_helper_0_0(helper_fpadd32);
2382dc6b 3645 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3646 break;
3647 case 0x053: /* VIS I fpadd32s */
3648 gen_op_load_fpr_FT0(rs1);
3649 gen_op_load_fpr_FT1(rs2);
44e7757c 3650 tcg_gen_helper_0_0(helper_fpadd32s);
e9ebed4d
BS		 3651 gen_op_store_FT0_fpr(rd);
3652 break;
3653 case 0x054: /* VIS I fpsub16 */
2382dc6b
BS		 3654 gen_op_load_fpr_DT0(DFPREG(rs1));
3655 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3656 tcg_gen_helper_0_0(helper_fpsub16);
2382dc6b 3657 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3658 break;
3659 case 0x055: /* VIS I fpsub16s */
3660 gen_op_load_fpr_FT0(rs1);
3661 gen_op_load_fpr_FT1(rs2);
44e7757c 3662 tcg_gen_helper_0_0(helper_fpsub16s);
e9ebed4d
BS		 3663 gen_op_store_FT0_fpr(rd);
3664 break;
3665 case 0x056: /* VIS I fpsub32 */
2382dc6b
BS		 3666 gen_op_load_fpr_DT0(DFPREG(rs1));
3667 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3668 tcg_gen_helper_0_0(helper_fpadd32);
2382dc6b 3669 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3670 break;
3671 case 0x057: /* VIS I fpsub32s */
3672 gen_op_load_fpr_FT0(rs1);
3673 gen_op_load_fpr_FT1(rs2);
44e7757c 3674 tcg_gen_helper_0_0(helper_fpsub32s);
e9ebed4d
BS		 3675 gen_op_store_FT0_fpr(rd);
3676 break;
3299908c 3677 case 0x060: /* VIS I fzero */
44e7757c 3678 tcg_gen_helper_0_0(helper_movl_DT0_0);
2382dc6b 3679 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3680 break;
3681 case 0x061: /* VIS I fzeros */
44e7757c 3682 tcg_gen_helper_0_0(helper_movl_FT0_0);
3299908c
BS		 3683 gen_op_store_FT0_fpr(rd);
3684 break;
e9ebed4d 3685 case 0x062: /* VIS I fnor */
2382dc6b
BS		 3686 gen_op_load_fpr_DT0(DFPREG(rs1));
3687 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3688 tcg_gen_helper_0_0(helper_fnor);
2382dc6b 3689 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3690 break;
3691 case 0x063: /* VIS I fnors */
3692 gen_op_load_fpr_FT0(rs1);
3693 gen_op_load_fpr_FT1(rs2);
44e7757c 3694 tcg_gen_helper_0_0(helper_fnors);
e9ebed4d
BS		 3695 gen_op_store_FT0_fpr(rd);
3696 break;
3697 case 0x064: /* VIS I fandnot2 */
2382dc6b
BS		 3698 gen_op_load_fpr_DT1(DFPREG(rs1));
3699 gen_op_load_fpr_DT0(DFPREG(rs2));
44e7757c 3700 tcg_gen_helper_0_0(helper_fandnot);
2382dc6b 3701 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3702 break;
3703 case 0x065: /* VIS I fandnot2s */
3704 gen_op_load_fpr_FT1(rs1);
3705 gen_op_load_fpr_FT0(rs2);
44e7757c 3706 tcg_gen_helper_0_0(helper_fandnots);
e9ebed4d
BS		 3707 gen_op_store_FT0_fpr(rd);
3708 break;
3709 case 0x066: /* VIS I fnot2 */
2382dc6b 3710 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3711 tcg_gen_helper_0_0(helper_fnot);
2382dc6b 3712 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3713 break;
3714 case 0x067: /* VIS I fnot2s */
3715 gen_op_load_fpr_FT1(rs2);
44e7757c 3716 tcg_gen_helper_0_0(helper_fnot);
e9ebed4d
BS		 3717 gen_op_store_FT0_fpr(rd);
3718 break;
3719 case 0x068: /* VIS I fandnot1 */
2382dc6b
BS		 3720 gen_op_load_fpr_DT0(DFPREG(rs1));
3721 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3722 tcg_gen_helper_0_0(helper_fandnot);
2382dc6b 3723 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3724 break;
3725 case 0x069: /* VIS I fandnot1s */
3726 gen_op_load_fpr_FT0(rs1);
3727 gen_op_load_fpr_FT1(rs2);
44e7757c 3728 tcg_gen_helper_0_0(helper_fandnots);
e9ebed4d
BS		 3729 gen_op_store_FT0_fpr(rd);
3730 break;
3731 case 0x06a: /* VIS I fnot1 */
2382dc6b 3732 gen_op_load_fpr_DT1(DFPREG(rs1));
44e7757c 3733 tcg_gen_helper_0_0(helper_fnot);
2382dc6b 3734 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3735 break;
3736 case 0x06b: /* VIS I fnot1s */
3737 gen_op_load_fpr_FT1(rs1);
44e7757c 3738 tcg_gen_helper_0_0(helper_fnot);
e9ebed4d
BS		 3739 gen_op_store_FT0_fpr(rd);
3740 break;
3741 case 0x06c: /* VIS I fxor */
2382dc6b
BS		 3742 gen_op_load_fpr_DT0(DFPREG(rs1));
3743 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3744 tcg_gen_helper_0_0(helper_fxor);
2382dc6b 3745 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3746 break;
3747 case 0x06d: /* VIS I fxors */
3748 gen_op_load_fpr_FT0(rs1);
3749 gen_op_load_fpr_FT1(rs2);
44e7757c 3750 tcg_gen_helper_0_0(helper_fxors);
e9ebed4d
BS		 3751 gen_op_store_FT0_fpr(rd);
3752 break;
3753 case 0x06e: /* VIS I fnand */
2382dc6b
BS		 3754 gen_op_load_fpr_DT0(DFPREG(rs1));
3755 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3756 tcg_gen_helper_0_0(helper_fnand);
2382dc6b 3757 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3758 break;
3759 case 0x06f: /* VIS I fnands */
3760 gen_op_load_fpr_FT0(rs1);
3761 gen_op_load_fpr_FT1(rs2);
44e7757c 3762 tcg_gen_helper_0_0(helper_fnands);
e9ebed4d
BS		 3763 gen_op_store_FT0_fpr(rd);
3764 break;
3765 case 0x070: /* VIS I fand */
2382dc6b
BS		 3766 gen_op_load_fpr_DT0(DFPREG(rs1));
3767 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3768 tcg_gen_helper_0_0(helper_fand);
2382dc6b 3769 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3770 break;
3771 case 0x071: /* VIS I fands */
3772 gen_op_load_fpr_FT0(rs1);
3773 gen_op_load_fpr_FT1(rs2);
44e7757c 3774 tcg_gen_helper_0_0(helper_fands);
e9ebed4d
BS		 3775 gen_op_store_FT0_fpr(rd);
3776 break;
3777 case 0x072: /* VIS I fxnor */
2382dc6b
BS		 3778 gen_op_load_fpr_DT0(DFPREG(rs1));
3779 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3780 tcg_gen_helper_0_0(helper_fxnor);
2382dc6b 3781 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3782 break;
3783 case 0x073: /* VIS I fxnors */
3784 gen_op_load_fpr_FT0(rs1);
3785 gen_op_load_fpr_FT1(rs2);
44e7757c 3786 tcg_gen_helper_0_0(helper_fxnors);
e9ebed4d
BS		 3787 gen_op_store_FT0_fpr(rd);
3788 break;
3299908c 3789 case 0x074: /* VIS I fsrc1 */
2382dc6b
BS		 3790 gen_op_load_fpr_DT0(DFPREG(rs1));
3791 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3792 break;
3793 case 0x075: /* VIS I fsrc1s */
3299908c
BS		 3794 gen_op_load_fpr_FT0(rs1);
3795 gen_op_store_FT0_fpr(rd);
3796 break;
e9ebed4d 3797 case 0x076: /* VIS I fornot2 */
2382dc6b
BS		 3798 gen_op_load_fpr_DT1(DFPREG(rs1));
3799 gen_op_load_fpr_DT0(DFPREG(rs2));
44e7757c 3800 tcg_gen_helper_0_0(helper_fornot);
2382dc6b 3801 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3802 break;
3803 case 0x077: /* VIS I fornot2s */
3804 gen_op_load_fpr_FT1(rs1);
3805 gen_op_load_fpr_FT0(rs2);
44e7757c 3806 tcg_gen_helper_0_0(helper_fornots);
e9ebed4d
BS		 3807 gen_op_store_FT0_fpr(rd);
3808 break;
3299908c 3809 case 0x078: /* VIS I fsrc2 */
2382dc6b
BS		 3810 gen_op_load_fpr_DT0(DFPREG(rs2));
3811 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3812 break;
3813 case 0x079: /* VIS I fsrc2s */
3299908c
BS		 3814 gen_op_load_fpr_FT0(rs2);
3815 gen_op_store_FT0_fpr(rd);
3816 break;
e9ebed4d 3817 case 0x07a: /* VIS I fornot1 */
2382dc6b
BS		 3818 gen_op_load_fpr_DT0(DFPREG(rs1));
3819 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3820 tcg_gen_helper_0_0(helper_fornot);
2382dc6b 3821 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3822 break;
3823 case 0x07b: /* VIS I fornot1s */
3824 gen_op_load_fpr_FT0(rs1);
3825 gen_op_load_fpr_FT1(rs2);
44e7757c 3826 tcg_gen_helper_0_0(helper_fornots);
e9ebed4d
BS		 3827 gen_op_store_FT0_fpr(rd);
3828 break;
3829 case 0x07c: /* VIS I for */
2382dc6b
BS		 3830 gen_op_load_fpr_DT0(DFPREG(rs1));
3831 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3832 tcg_gen_helper_0_0(helper_for);
2382dc6b 3833 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3834 break;
3835 case 0x07d: /* VIS I fors */
3836 gen_op_load_fpr_FT0(rs1);
3837 gen_op_load_fpr_FT1(rs2);
44e7757c 3838 tcg_gen_helper_0_0(helper_fors);
e9ebed4d
BS		 3839 gen_op_store_FT0_fpr(rd);
3840 break;
3299908c 3841 case 0x07e: /* VIS I fone */
44e7757c 3842 tcg_gen_helper_0_0(helper_movl_DT0_1);
2382dc6b 3843 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3844 break;
3845 case 0x07f: /* VIS I fones */
44e7757c 3846 tcg_gen_helper_0_0(helper_movl_FT0_1);
3299908c
BS		 3847 gen_op_store_FT0_fpr(rd);
3848 break;
e9ebed4d
BS		 3849 case 0x080: /* VIS I shutdown */
3850 case 0x081: /* VIS II siam */
3851 // XXX
3852 goto illegal_insn;
3299908c
BS		 3853 default:
3854 goto illegal_insn;
3855 }
3856#else
0f8a249a 3857 goto ncp_insn;
3299908c
BS		 3858#endif
3859 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045 3860#ifdef TARGET_SPARC64
0f8a249a 3861 goto illegal_insn;
fcc72045 3862#else
0f8a249a 3863 goto ncp_insn;
fcc72045 3864#endif
3475187d 3865#ifdef TARGET_SPARC64
0f8a249a 3866 } else if (xop == 0x39) { /* V9 return */
6ae20372 3867 save_state(dc, cpu_cond);
9322a4bf 3868 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a
BS		 3869 if (IS_IMM) { /* immediate */
3870 rs2 = GET_FIELDs(insn, 19, 31);
6ae20372 3871 tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
0f8a249a 3872 } else { /* register */
3475187d 3873 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 3874 if (rs2) {
6ae20372
BS		 3875 gen_movl_reg_TN(rs2, cpu_src2);
3876 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
6f551262
BS		 3877 } else
3878 tcg_gen_mov_tl(cpu_dst, cpu_src1);
3475187d 3879 }
72a9747b 3880 tcg_gen_helper_0_0(helper_restore);
6ae20372
BS		 3881 gen_mov_pc_npc(dc, cpu_cond);
3882 tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
3883 tcg_gen_mov_tl(cpu_npc, cpu_dst);
0f8a249a
BS		 3884 dc->npc = DYNAMIC_PC;
3885 goto jmp_insn;
3475187d 3886#endif
0f8a249a 3887 } else {
9322a4bf 3888 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a
BS		 3889 if (IS_IMM) { /* immediate */
3890 rs2 = GET_FIELDs(insn, 19, 31);
6ae20372 3891 tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
0f8a249a 3892 } else { /* register */
e80cfcfc 3893 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 3894 if (rs2) {
6ae20372
BS		 3895 gen_movl_reg_TN(rs2, cpu_src2);
3896 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
6f551262
BS		 3897 } else
3898 tcg_gen_mov_tl(cpu_dst, cpu_src1);
cf495bcf 3899 }
0f8a249a
BS		 3900 switch (xop) {
3901 case 0x38: /* jmpl */
3902 {
9c6c6662 3903 gen_movl_TN_reg(rd, tcg_const_tl(dc->pc));
6ae20372
BS		 3904 gen_mov_pc_npc(dc, cpu_cond);
3905 tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
3906 tcg_gen_mov_tl(cpu_npc, cpu_dst);
0f8a249a
BS		 3907 dc->npc = DYNAMIC_PC;
3908 }
3909 goto jmp_insn;
3475187d 3910#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
0f8a249a
BS		 3911 case 0x39: /* rett, V9 return */
3912 {
3913 if (!supervisor(dc))
3914 goto priv_insn;
6ae20372
BS		 3915 gen_mov_pc_npc(dc, cpu_cond);
3916 tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
3917 tcg_gen_mov_tl(cpu_npc, cpu_dst);
0f8a249a 3918 dc->npc = DYNAMIC_PC;
1a2fb1c0 3919 tcg_gen_helper_0_0(helper_rett);
0f8a249a
BS		 3920 }
3921 goto jmp_insn;
3922#endif
3923 case 0x3b: /* flush */
6ae20372 3924 tcg_gen_helper_0_1(helper_flush, cpu_dst);
0f8a249a
BS		 3925 break;
3926 case 0x3c: /* save */
6ae20372 3927 save_state(dc, cpu_cond);
72a9747b 3928 tcg_gen_helper_0_0(helper_save);
6ae20372 3929 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 3930 break;
3931 case 0x3d: /* restore */
6ae20372 3932 save_state(dc, cpu_cond);
72a9747b 3933 tcg_gen_helper_0_0(helper_restore);
6ae20372 3934 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a 3935 break;
3475187d 3936#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
0f8a249a
BS		 3937 case 0x3e: /* V9 done/retry */
3938 {
3939 switch (rd) {
3940 case 0:
3941 if (!supervisor(dc))
3942 goto priv_insn;
3943 dc->npc = DYNAMIC_PC;
3944 dc->pc = DYNAMIC_PC;
1a2fb1c0 3945 tcg_gen_helper_0_0(helper_done);
0f8a249a
BS		 3946 goto jmp_insn;
3947 case 1:
3948 if (!supervisor(dc))
3949 goto priv_insn;
3950 dc->npc = DYNAMIC_PC;
3951 dc->pc = DYNAMIC_PC;
1a2fb1c0 3952 tcg_gen_helper_0_0(helper_retry);
0f8a249a
BS		 3953 goto jmp_insn;
3954 default:
3955 goto illegal_insn;
3956 }
3957 }
3958 break;
3959#endif
3960 default:
3961 goto illegal_insn;
3962 }
cf495bcf 3963 }
0f8a249a
BS		 3964 break;
3965 }
3966 break;
3967 case 3: /* load/store instructions */
3968 {
3969 unsigned int xop = GET_FIELD(insn, 7, 12);
9322a4bf 3970
6ae20372 3971 save_state(dc, cpu_cond);
9322a4bf 3972 cpu_src1 = get_src1(insn, cpu_src1);
81ad8ba2
BS		 3973 if (xop == 0x3c || xop == 0x3e)
3974 {
3975 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 3976 gen_movl_reg_TN(rs2, cpu_src2);
81ad8ba2
BS		 3977 }
3978 else if (IS_IMM) { /* immediate */
0f8a249a 3979 rs2 = GET_FIELDs(insn, 19, 31);
6ae20372 3980 tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
0f8a249a
BS		 3981 } else { /* register */
3982 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 3983 if (rs2 != 0) {
6ae20372
BS		 3984 gen_movl_reg_TN(rs2, cpu_src2);
3985 tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
6f551262
BS		 3986 } else
3987 tcg_gen_mov_tl(cpu_addr, cpu_src1);
0f8a249a 3988 }
2f2ecb83
BS		 3989 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
3990 (xop > 0x17 && xop <= 0x1d ) ||
3991 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
0f8a249a 3992 switch (xop) {
1a2fb1c0 3993 case 0x0: /* load unsigned word */
6ae20372
BS		 3994 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
3995 ABI32_MASK(cpu_addr);
3996 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 3997 break;
3998 case 0x1: /* load unsigned byte */
6ae20372
BS		 3999 ABI32_MASK(cpu_addr);
4000 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4001 break;
4002 case 0x2: /* load unsigned halfword */
6ae20372
BS		 4003 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4004 ABI32_MASK(cpu_addr);
4005 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4006 break;
4007 case 0x3: /* load double word */
0f8a249a 4008 if (rd & 1)
d4218d99 4009 goto illegal_insn;
1a2fb1c0 4010 else {
6ae20372
BS		 4011 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4012 ABI32_MASK(cpu_addr);
4013 tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
32b6c812
BS		 4014 tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4015 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4016 gen_movl_TN_reg(rd + 1, cpu_tmp0);
8911f501 4017 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
6ae20372
BS		 4018 tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4019 tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
1a2fb1c0 4020 }
0f8a249a
BS		 4021 break;
4022 case 0x9: /* load signed byte */
6ae20372
BS		 4023 ABI32_MASK(cpu_addr);
4024 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4025 break;
4026 case 0xa: /* load signed halfword */
6ae20372
BS		 4027 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4028 ABI32_MASK(cpu_addr);
4029 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4030 break;
4031 case 0xd: /* ldstub -- XXX: should be atomically */
6ae20372
BS		 4032 ABI32_MASK(cpu_addr);
4033 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4034 tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_addr, dc->mem_idx);
0f8a249a
BS		 4035 break;
4036 case 0x0f: /* swap register with memory. Also atomically */
6ae20372
BS		 4037 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4038 gen_movl_reg_TN(rd, cpu_val);
4039 ABI32_MASK(cpu_addr);
4040 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4041 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4042 tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
0f8a249a 4043 break;
3475187d 4044#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 4045 case 0x10: /* load word alternate */
3475187d 4046#ifndef TARGET_SPARC64
0f8a249a
BS		 4047 if (IS_IMM)
4048 goto illegal_insn;
4049 if (!supervisor(dc))
4050 goto priv_insn;
6ea4a6c8 4051#endif
6ae20372
BS		 4052 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4053 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
0f8a249a
BS		 4054 break;
4055 case 0x11: /* load unsigned byte alternate */
3475187d 4056#ifndef TARGET_SPARC64
0f8a249a
BS		 4057 if (IS_IMM)
4058 goto illegal_insn;
4059 if (!supervisor(dc))
4060 goto priv_insn;
4061#endif
6ae20372 4062 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
0f8a249a
BS		 4063 break;
4064 case 0x12: /* load unsigned halfword alternate */
3475187d 4065#ifndef TARGET_SPARC64
0f8a249a
BS		 4066 if (IS_IMM)
4067 goto illegal_insn;
4068 if (!supervisor(dc))
4069 goto priv_insn;
3475187d 4070#endif
6ae20372
BS		 4071 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4072 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
0f8a249a
BS		 4073 break;
4074 case 0x13: /* load double word alternate */
3475187d 4075#ifndef TARGET_SPARC64
0f8a249a
BS		 4076 if (IS_IMM)
4077 goto illegal_insn;
4078 if (!supervisor(dc))
4079 goto priv_insn;
3475187d 4080#endif
0f8a249a 4081 if (rd & 1)
d4218d99 4082 goto illegal_insn;
6ae20372
BS		 4083 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4084 gen_ldda_asi(cpu_tmp0, cpu_val, cpu_addr, insn);
32b6c812 4085 gen_movl_TN_reg(rd + 1, cpu_tmp0);
0f8a249a
BS		 4086 break;
4087 case 0x19: /* load signed byte alternate */
3475187d 4088#ifndef TARGET_SPARC64
0f8a249a
BS		 4089 if (IS_IMM)
4090 goto illegal_insn;
4091 if (!supervisor(dc))
4092 goto priv_insn;
4093#endif
6ae20372 4094 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
0f8a249a
BS		 4095 break;
4096 case 0x1a: /* load signed halfword alternate */
3475187d 4097#ifndef TARGET_SPARC64
0f8a249a
BS		 4098 if (IS_IMM)
4099 goto illegal_insn;
4100 if (!supervisor(dc))
4101 goto priv_insn;
3475187d 4102#endif
6ae20372
BS		 4103 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4104 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
0f8a249a
BS		 4105 break;
4106 case 0x1d: /* ldstuba -- XXX: should be atomically */
3475187d 4107#ifndef TARGET_SPARC64
0f8a249a
BS		 4108 if (IS_IMM)
4109 goto illegal_insn;
4110 if (!supervisor(dc))
4111 goto priv_insn;
4112#endif
6ae20372 4113 gen_ldstub_asi(cpu_val, cpu_addr, insn);
0f8a249a
BS		 4114 break;
4115 case 0x1f: /* swap reg with alt. memory. Also atomically */
3475187d 4116#ifndef TARGET_SPARC64
0f8a249a
BS		 4117 if (IS_IMM)
4118 goto illegal_insn;
4119 if (!supervisor(dc))
4120 goto priv_insn;
6ea4a6c8 4121#endif
6ae20372
BS		 4122 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4123 gen_movl_reg_TN(rd, cpu_val);
4124 gen_swap_asi(cpu_val, cpu_addr, insn);
0f8a249a 4125 break;
3475187d
FB		 4126
4127#ifndef TARGET_SPARC64
0f8a249a
BS		 4128 case 0x30: /* ldc */
4129 case 0x31: /* ldcsr */
4130 case 0x33: /* lddc */
4131 goto ncp_insn;
3475187d
FB		 4132#endif
4133#endif
4134#ifdef TARGET_SPARC64
0f8a249a 4135 case 0x08: /* V9 ldsw */
6ae20372
BS		 4136 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4137 ABI32_MASK(cpu_addr);
4138 tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4139 break;
4140 case 0x0b: /* V9 ldx */
6ae20372
BS		 4141 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4142 ABI32_MASK(cpu_addr);
4143 tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4144 break;
4145 case 0x18: /* V9 ldswa */
6ae20372
BS		 4146 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4147 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
0f8a249a
BS		 4148 break;
4149 case 0x1b: /* V9 ldxa */
6ae20372
BS		 4150 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4151 gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
0f8a249a
BS		 4152 break;
4153 case 0x2d: /* V9 prefetch, no effect */
4154 goto skip_move;
4155 case 0x30: /* V9 ldfa */
6ae20372
BS		 4156 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4157 gen_ldf_asi(cpu_addr, insn, 4, rd);
81ad8ba2 4158 goto skip_move;
0f8a249a 4159 case 0x33: /* V9 lddfa */
6ae20372
BS		 4160 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4161 gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
81ad8ba2 4162 goto skip_move;
0f8a249a
BS		 4163 case 0x3d: /* V9 prefetcha, no effect */
4164 goto skip_move;
4165 case 0x32: /* V9 ldqfa */
1f587329 4166#if defined(CONFIG_USER_ONLY)
6ae20372
BS		 4167 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4168 gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
1f587329
BS		 4169 goto skip_move;
4170#else
0f8a249a 4171 goto nfpu_insn;
1f587329 4172#endif
0f8a249a
BS		 4173#endif
4174 default:
4175 goto illegal_insn;
4176 }
6ae20372 4177 gen_movl_TN_reg(rd, cpu_val);
3475187d 4178#ifdef TARGET_SPARC64
0f8a249a 4179 skip_move: ;
3475187d 4180#endif
0f8a249a 4181 } else if (xop >= 0x20 && xop < 0x24) {
6ae20372 4182 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 4183 goto jmp_insn;
0f8a249a
BS		 4184 switch (xop) {
4185 case 0x20: /* load fpreg */
6ae20372
BS		 4186 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4187 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
ce8536e2
BS		 4188 tcg_gen_st_i32(cpu_tmp32, cpu_env,
4189 offsetof(CPUState, fpr[rd]));
0f8a249a
BS		 4190 break;
4191 case 0x21: /* load fsr */
6ae20372
BS		 4192 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4193 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
ce8536e2
BS		 4194 tcg_gen_st_i32(cpu_tmp32, cpu_env,
4195 offsetof(CPUState, ft0));
7e8c2b6c 4196 tcg_gen_helper_0_0(helper_ldfsr);
0f8a249a
BS		 4197 break;
4198 case 0x22: /* load quad fpreg */
1f587329 4199#if defined(CONFIG_USER_ONLY)
7fa76c0b
BS		 4200 tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4201 tcg_const_i32(7));
4202 tcg_gen_helper_0_1(helper_ldqf, cpu_addr);
1f587329
BS		 4203 gen_op_store_QT0_fpr(QFPREG(rd));
4204 break;
4205#else
0f8a249a 4206 goto nfpu_insn;
1f587329 4207#endif
0f8a249a 4208 case 0x23: /* load double fpreg */
7fa76c0b
BS		 4209 tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4210 tcg_const_i32(7));
4211 tcg_gen_helper_0_2(helper_lddf, cpu_addr,
4212 tcg_const_i32(dc->mem_idx));
0f8a249a
BS		 4213 gen_op_store_DT0_fpr(DFPREG(rd));
4214 break;
4215 default:
4216 goto illegal_insn;
4217 }
4218 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4219 xop == 0xe || xop == 0x1e) {
6ae20372 4220 gen_movl_reg_TN(rd, cpu_val);
0f8a249a 4221 switch (xop) {
1a2fb1c0 4222 case 0x4: /* store word */
6ae20372
BS		 4223 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4224 ABI32_MASK(cpu_addr);
4225 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4226 break;
1a2fb1c0 4227 case 0x5: /* store byte */
6ae20372
BS		 4228 ABI32_MASK(cpu_addr);
4229 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4230 break;
1a2fb1c0 4231 case 0x6: /* store halfword */
6ae20372
BS		 4232 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4233 ABI32_MASK(cpu_addr);
4234 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4235 break;
1a2fb1c0 4236 case 0x7: /* store double word */
0f8a249a 4237 if (rd & 1)
d4218d99 4238 goto illegal_insn;
1a2fb1c0 4239 else {
8911f501 4240 TCGv r_low;
1a2fb1c0 4241
6ae20372 4242 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
1a2fb1c0
BS		 4243 r_low = tcg_temp_new(TCG_TYPE_I32);
4244 gen_movl_reg_TN(rd + 1, r_low);
7fa76c0b 4245#ifndef __i386__
6ae20372 4246 tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
1a2fb1c0 4247 r_low);
6ae20372 4248 tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
b25deda7 4249#else /* __i386__ */
7fa76c0b
BS		 4250 tcg_gen_st_tl(cpu_val, cpu_env, offsetof(CPUState, t1));
4251 tcg_gen_st_tl(r_low, cpu_env, offsetof(CPUState, t2));
4252 tcg_gen_helper_0_2(helper_std_i386, cpu_addr,
4253 tcg_const_i32(dc->mem_idx));
b25deda7 4254#endif /* __i386__ */
7fa76c0b 4255 }
0f8a249a 4256 break;
3475187d 4257#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1a2fb1c0 4258 case 0x14: /* store word alternate */
3475187d 4259#ifndef TARGET_SPARC64
0f8a249a
BS		 4260 if (IS_IMM)
4261 goto illegal_insn;
4262 if (!supervisor(dc))
4263 goto priv_insn;
6ea4a6c8 4264#endif
6ae20372
BS		 4265 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4266 gen_st_asi(cpu_val, cpu_addr, insn, 4);
d39c0b99 4267 break;
1a2fb1c0 4268 case 0x15: /* store byte alternate */
3475187d 4269#ifndef TARGET_SPARC64
0f8a249a
BS		 4270 if (IS_IMM)
4271 goto illegal_insn;
4272 if (!supervisor(dc))
4273 goto priv_insn;
3475187d 4274#endif
6ae20372 4275 gen_st_asi(cpu_val, cpu_addr, insn, 1);
d39c0b99 4276 break;
1a2fb1c0 4277 case 0x16: /* store halfword alternate */
3475187d 4278#ifndef TARGET_SPARC64
0f8a249a
BS		 4279 if (IS_IMM)
4280 goto illegal_insn;
4281 if (!supervisor(dc))
4282 goto priv_insn;
6ea4a6c8 4283#endif
6ae20372
BS		 4284 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4285 gen_st_asi(cpu_val, cpu_addr, insn, 2);
d39c0b99 4286 break;
1a2fb1c0 4287 case 0x17: /* store double word alternate */
3475187d 4288#ifndef TARGET_SPARC64
0f8a249a
BS		 4289 if (IS_IMM)
4290 goto illegal_insn;
4291 if (!supervisor(dc))
4292 goto priv_insn;
3475187d 4293#endif
0f8a249a 4294 if (rd & 1)
d4218d99 4295 goto illegal_insn;
1a2fb1c0 4296 else {
6ae20372
BS		 4297 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4298 gen_stda_asi(cpu_val, cpu_addr, insn, rd);
1a2fb1c0 4299 }
d39c0b99 4300 break;
e80cfcfc 4301#endif
3475187d 4302#ifdef TARGET_SPARC64
0f8a249a 4303 case 0x0e: /* V9 stx */
6ae20372
BS		 4304 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4305 ABI32_MASK(cpu_addr);
4306 tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4307 break;
4308 case 0x1e: /* V9 stxa */
6ae20372
BS		 4309 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4310 gen_st_asi(cpu_val, cpu_addr, insn, 8);
0f8a249a 4311 break;
3475187d 4312#endif
0f8a249a
BS		 4313 default:
4314 goto illegal_insn;
4315 }
4316 } else if (xop > 0x23 && xop < 0x28) {
6ae20372 4317 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 4318 goto jmp_insn;
0f8a249a 4319 switch (xop) {
ce8536e2 4320 case 0x24: /* store fpreg */
6ae20372 4321 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
ce8536e2
BS		 4322 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4323 offsetof(CPUState, fpr[rd]));
6ae20372 4324 tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4325 break;
4326 case 0x25: /* stfsr, V9 stxfsr */
6ea4a6c8 4327#ifdef CONFIG_USER_ONLY
6ae20372 4328 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
6ea4a6c8 4329#endif
bb5529bb 4330 tcg_gen_helper_0_0(helper_stfsr);
ce8536e2
BS		 4331 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4332 offsetof(CPUState, ft0));
6ae20372 4333 tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
0f8a249a 4334 break;
1f587329
BS		 4335 case 0x26:
4336#ifdef TARGET_SPARC64
4337#if defined(CONFIG_USER_ONLY)
4338 /* V9 stqf, store quad fpreg */
7fa76c0b
BS		 4339 tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4340 tcg_const_i32(7));
1f587329 4341 gen_op_load_fpr_QT0(QFPREG(rd));
7fa76c0b 4342 tcg_gen_helper_0_1(helper_stqf, cpu_addr);
1f587329
BS		 4343 break;
4344#else
4345 goto nfpu_insn;
4346#endif
4347#else /* !TARGET_SPARC64 */
4348 /* stdfq, store floating point queue */
4349#if defined(CONFIG_USER_ONLY)
4350 goto illegal_insn;
4351#else
0f8a249a
BS		 4352 if (!supervisor(dc))
4353 goto priv_insn;
6ae20372 4354 if (gen_trap_ifnofpu(dc, cpu_cond))
0f8a249a
BS		 4355 goto jmp_insn;
4356 goto nfq_insn;
1f587329 4357#endif
0f8a249a 4358#endif
7fa76c0b
BS		 4359 case 0x27: /* store double fpreg */
4360 tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4361 tcg_const_i32(7));
3475187d 4362 gen_op_load_fpr_DT0(DFPREG(rd));
7fa76c0b
BS		 4363 tcg_gen_helper_0_2(helper_stdf, cpu_addr,
4364 tcg_const_i32(dc->mem_idx));
0f8a249a
BS		 4365 break;
4366 default:
4367 goto illegal_insn;
4368 }
4369 } else if (xop > 0x33 && xop < 0x3f) {
4370 switch (xop) {
a4d17f19 4371#ifdef TARGET_SPARC64
0f8a249a 4372 case 0x34: /* V9 stfa */
6ae20372 4373 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
3391c818 4374 gen_op_load_fpr_FT0(rd);
6ae20372 4375 gen_stf_asi(cpu_addr, insn, 4, rd);
0f8a249a 4376 break;
1f587329
BS		 4377 case 0x36: /* V9 stqfa */
4378#if defined(CONFIG_USER_ONLY)
6ae20372 4379 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
1f587329 4380 gen_op_load_fpr_QT0(QFPREG(rd));
6ae20372 4381 gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
1f587329
BS		 4382 break;
4383#else
4384 goto nfpu_insn;
4385#endif
0f8a249a 4386 case 0x37: /* V9 stdfa */
6ae20372 4387 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
3391c818 4388 gen_op_load_fpr_DT0(DFPREG(rd));
6ae20372 4389 gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
0f8a249a
BS		 4390 break;
4391 case 0x3c: /* V9 casa */
6ae20372
BS		 4392 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4393 gen_cas_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4394 gen_movl_TN_reg(rd, cpu_val);
0f8a249a
BS		 4395 break;
4396 case 0x3e: /* V9 casxa */
6ae20372
BS		 4397 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4398 gen_casx_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4399 gen_movl_TN_reg(rd, cpu_val);
0f8a249a 4400 break;
a4d17f19 4401#else
0f8a249a
BS		 4402 case 0x34: /* stc */
4403 case 0x35: /* stcsr */
4404 case 0x36: /* stdcq */
4405 case 0x37: /* stdc */
4406 goto ncp_insn;
4407#endif
4408 default:
4409 goto illegal_insn;
4410 }
e8af50a3 4411 }
0f8a249a
BS		 4412 else
4413 goto illegal_insn;
4414 }
4415 break;
cf495bcf
FB		 4416 }
4417 /* default case for non jump instructions */
72cbca10 4418 if (dc->npc == DYNAMIC_PC) {
0f8a249a
BS		 4419 dc->pc = DYNAMIC_PC;
4420 gen_op_next_insn();
72cbca10
FB		 4421 } else if (dc->npc == JUMP_PC) {
4422 /* we can do a static jump */
6ae20372 4423 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
72cbca10
FB		 4424 dc->is_br = 1;
4425 } else {
0f8a249a
BS		 4426 dc->pc = dc->npc;
4427 dc->npc = dc->npc + 4;
cf495bcf 4428 }
e80cfcfc 4429 jmp_insn:
cf495bcf
FB		 4430 return;
4431 illegal_insn:
6ae20372 4432 save_state(dc, cpu_cond);
2f5680ee 4433 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_ILL_INSN));
cf495bcf 4434 dc->is_br = 1;
e8af50a3 4435 return;
e80cfcfc 4436#if !defined(CONFIG_USER_ONLY)
e8af50a3 4437 priv_insn:
6ae20372 4438 save_state(dc, cpu_cond);
2f5680ee 4439 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_PRIV_INSN));
e8af50a3 4440 dc->is_br = 1;
e80cfcfc 4441 return;
e80cfcfc 4442 nfpu_insn:
6ae20372 4443 save_state(dc, cpu_cond);
e80cfcfc
FB		 4444 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4445 dc->is_br = 1;
fcc72045 4446 return;
1f587329 4447#ifndef TARGET_SPARC64
9143e598 4448 nfq_insn:
6ae20372 4449 save_state(dc, cpu_cond);
9143e598
BS		 4450 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4451 dc->is_br = 1;
4452 return;
4453#endif
1f587329 4454#endif
fcc72045
BS		 4455#ifndef TARGET_SPARC64
4456 ncp_insn:
6ae20372 4457 save_state(dc, cpu_cond);
2f5680ee 4458 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NCP_INSN));
fcc72045
BS		 4459 dc->is_br = 1;
4460 return;
4461#endif
7a3f1944
FB		 4462}
4463
1a2fb1c0
BS		 4464static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
4465{
4466}
4467
cf495bcf 4468static inline int gen_intermediate_code_internal(TranslationBlock * tb,
0f8a249a 4469 int spc, CPUSPARCState *env)
7a3f1944 4470{
72cbca10 4471 target_ulong pc_start, last_pc;
cf495bcf
FB		 4472 uint16_t *gen_opc_end;
4473 DisasContext dc1, *dc = &dc1;
e8af50a3 4474 int j, lj = -1;
cf495bcf
FB		 4475
4476 memset(dc, 0, sizeof(DisasContext));
cf495bcf 4477 dc->tb = tb;
72cbca10 4478 pc_start = tb->pc;
cf495bcf 4479 dc->pc = pc_start;
e80cfcfc 4480 last_pc = dc->pc;
72cbca10 4481 dc->npc = (target_ulong) tb->cs_base;
6f27aba6
BS		 4482 dc->mem_idx = cpu_mmu_index(env);
4483 dc->fpu_enabled = cpu_fpu_enabled(env);
cf495bcf 4484 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
cf495bcf 4485
1a2fb1c0 4486 cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
8911f501
BS		 4487 cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4488 cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
1a2fb1c0 4489
6ae20372
BS		 4490 cpu_cond = cpu_T[2];
4491
cf495bcf 4492 do {
e8af50a3
FB		 4493 if (env->nb_breakpoints > 0) {
4494 for(j = 0; j < env->nb_breakpoints; j++) {
4495 if (env->breakpoints[j] == dc->pc) {
0f8a249a 4496 if (dc->pc != pc_start)
6ae20372 4497 save_state(dc, cpu_cond);
1a2fb1c0 4498 tcg_gen_helper_0_0(helper_debug);
57fec1fe 4499 tcg_gen_exit_tb(0);
0f8a249a 4500 dc->is_br = 1;
e80cfcfc 4501 goto exit_gen_loop;
e8af50a3
FB		 4502 }
4503 }
4504 }
4505 if (spc) {
4506 if (loglevel > 0)
4507 fprintf(logfile, "Search PC...\n");
4508 j = gen_opc_ptr - gen_opc_buf;
4509 if (lj < j) {
4510 lj++;
4511 while (lj < j)
4512 gen_opc_instr_start[lj++] = 0;
4513 gen_opc_pc[lj] = dc->pc;
4514 gen_opc_npc[lj] = dc->npc;
4515 gen_opc_instr_start[lj] = 1;
4516 }
4517 }
0f8a249a
BS		 4518 last_pc = dc->pc;
4519 disas_sparc_insn(dc);
4520
4521 if (dc->is_br)
4522 break;
4523 /* if the next PC is different, we abort now */
4524 if (dc->pc != (last_pc + 4))
4525 break;
d39c0b99
FB		 4526 /* if we reach a page boundary, we stop generation so that the
4527 PC of a TT_TFAULT exception is always in the right page */
4528 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4529 break;
e80cfcfc
FB		 4530 /* if single step mode, we generate only one instruction and
4531 generate an exception */
4532 if (env->singlestep_enabled) {
2f5680ee 4533 tcg_gen_movi_tl(cpu_pc, dc->pc);
57fec1fe 4534 tcg_gen_exit_tb(0);
e80cfcfc
FB		 4535 break;
4536 }
cf495bcf 4537 } while ((gen_opc_ptr < gen_opc_end) &&
0f8a249a 4538 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
e80cfcfc
FB		 4539
4540 exit_gen_loop:
72cbca10 4541 if (!dc->is_br) {
5fafdf24 4542 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 4543 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4544 /* static PC and NPC: we can use direct chaining */
2f5680ee 4545 gen_goto_tb(dc, 0, dc->pc, dc->npc);
72cbca10
FB		 4546 } else {
4547 if (dc->pc != DYNAMIC_PC)
2f5680ee 4548 tcg_gen_movi_tl(cpu_pc, dc->pc);
6ae20372 4549 save_npc(dc, cpu_cond);
57fec1fe 4550 tcg_gen_exit_tb(0);
72cbca10
FB		 4551 }
4552 }
cf495bcf 4553 *gen_opc_ptr = INDEX_op_end;
e8af50a3
FB		 4554 if (spc) {
4555 j = gen_opc_ptr - gen_opc_buf;
4556 lj++;
4557 while (lj <= j)
4558 gen_opc_instr_start[lj++] = 0;
e8af50a3
FB		 4559#if 0
4560 if (loglevel > 0) {
4561 page_dump(logfile);
4562 }
4563#endif
c3278b7b
FB		 4564 gen_opc_jump_pc[0] = dc->jump_pc[0];
4565 gen_opc_jump_pc[1] = dc->jump_pc[1];
e8af50a3 4566 } else {
e80cfcfc 4567 tb->size = last_pc + 4 - pc_start;
e8af50a3 4568 }
7a3f1944 4569#ifdef DEBUG_DISAS
e19e89a5 4570 if (loglevel & CPU_LOG_TB_IN_ASM) {
0f8a249a
BS		 4571 fprintf(logfile, "--------------\n");
4572 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4573 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4574 fprintf(logfile, "\n");
cf495bcf 4575 }
7a3f1944 4576#endif
cf495bcf 4577 return 0;
7a3f1944
FB		 4578}
4579
cf495bcf 4580int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 4581{
e8af50a3 4582 return gen_intermediate_code_internal(tb, 0, env);
7a3f1944
FB		 4583}
4584
cf495bcf 4585int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 4586{
e8af50a3 4587 return gen_intermediate_code_internal(tb, 1, env);
7a3f1944
FB		 4588}
4589
c48fcb47 4590void gen_intermediate_code_init(CPUSPARCState *env)
e80cfcfc 4591{
f5069b26 4592 unsigned int i;
c48fcb47 4593 static int inited;
f5069b26
BS		 4594 static const char * const gregnames[8] = {
4595 NULL, // g0 not used
4596 "g1",
4597 "g2",
4598 "g3",
4599 "g4",
4600 "g5",
4601 "g6",
4602 "g7",
4603 };
aaed909a 4604
1a2fb1c0
BS		 4605 /* init various static tables */
4606 if (!inited) {
4607 inited = 1;
4608
4609 tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
4610 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
db4a4ea4
BS		 4611 cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4612 offsetof(CPUState, regwptr),
4613 "regwptr");
1a2fb1c0
BS		 4614 //#if TARGET_LONG_BITS > HOST_LONG_BITS
4615#ifdef TARGET_SPARC64
4616 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
4617 TCG_AREG0, offsetof(CPUState, t0), "T0");
4618 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
4619 TCG_AREG0, offsetof(CPUState, t1), "T1");
4620 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
4621 TCG_AREG0, offsetof(CPUState, t2), "T2");
dc99a3f2
BS		 4622 cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4623 TCG_AREG0, offsetof(CPUState, xcc),
4624 "xcc");
1a2fb1c0
BS		 4625#else
4626 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
4627 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
4628 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
4629#endif
dc99a3f2
BS		 4630 cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4631 TCG_AREG0, offsetof(CPUState, cc_src),
4632 "cc_src");
d9bdab86
BS		 4633 cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4634 offsetof(CPUState, cc_src2),
4635 "cc_src2");
dc99a3f2
BS		 4636 cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4637 TCG_AREG0, offsetof(CPUState, cc_dst),
4638 "cc_dst");
4639 cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4640 TCG_AREG0, offsetof(CPUState, psr),
4641 "psr");
87e92502
BS		 4642 cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4643 TCG_AREG0, offsetof(CPUState, fsr),
4644 "fsr");
48d5c82b
BS		 4645 cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,
4646 TCG_AREG0, offsetof(CPUState, pc),
4647 "pc");
4648 cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
4649 TCG_AREG0, offsetof(CPUState, npc),
4650 "npc");
f5069b26
BS		 4651 for (i = 1; i < 8; i++)
4652 cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4653 offsetof(CPUState, gregs[i]),
4654 gregnames[i]);
1a2fb1c0 4655 }
658138bc 4656}
d2856f1a
AJ		 4657
4658void gen_pc_load(CPUState *env, TranslationBlock *tb,
4659 unsigned long searched_pc, int pc_pos, void *puc)
4660{
4661 target_ulong npc;
4662 env->pc = gen_opc_pc[pc_pos];
4663 npc = gen_opc_npc[pc_pos];
4664 if (npc == 1) {
4665 /* dynamic NPC: already stored */
4666 } else if (npc == 2) {
4667 target_ulong t2 = (target_ulong)(unsigned long)puc;
4668 /* jump PC: use T2 and the jump targets of the translation */
4669 if (t2)
4670 env->npc = gen_opc_jump_pc[0];
4671 else
4672 env->npc = gen_opc_jump_pc[1];
4673 } else {
4674 env->npc = npc;
4675 }
4676}
Qemu copy for testing