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Rework ASI instructions (Aurelien Jarno)
[qemu.git] / target-sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
7a3f1944
FB		 23 TODO-list:
24
3475187d 25 Rest of V9 instructions, VIS instructions
bd497938 26 NPC/PC static optimisations (use JUMP_TB when possible)
7a3f1944 27 Optimize synthetic instructions
3475187d 28 128-bit float
bd497938 29*/
7a3f1944
FB		 30
31#include <stdarg.h>
32#include <stdlib.h>
33#include <stdio.h>
34#include <string.h>
35#include <inttypes.h>
36
37#include "cpu.h"
38#include "exec-all.h"
39#include "disas.h"
40
41#define DEBUG_DISAS
42
72cbca10
FB		 43#define DYNAMIC_PC 1 /* dynamic pc value */
44#define JUMP_PC 2 /* dynamic pc value which takes only two values
45 according to jump_pc[T2] */
46
7a3f1944 47typedef struct DisasContext {
0f8a249a
BS		 48 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
49 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 50 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 51 int is_br;
e8af50a3 52 int mem_idx;
a80dde08 53 int fpu_enabled;
cf495bcf 54 struct TranslationBlock *tb;
7a3f1944
FB		 55} DisasContext;
56
62724a37
BS		 57struct sparc_def_t {
58 const unsigned char *name;
59 target_ulong iu_version;
60 uint32_t fpu_version;
61 uint32_t mmu_version;
62};
63
7a3f1944
FB		 64static uint16_t *gen_opc_ptr;
65static uint32_t *gen_opparam_ptr;
66extern FILE *logfile;
67extern int loglevel;
68
69enum {
70#define DEF(s,n,copy_size) INDEX_op_ ## s,
71#include "opc.h"
72#undef DEF
cf495bcf 73 NB_OPS
7a3f1944
FB		 74};
75
76#include "gen-op.h"
77
3475187d 78// This function uses non-native bit order
7a3f1944
FB		 79#define GET_FIELD(X, FROM, TO) \
80 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
81
3475187d
FB		 82// This function uses the order in the manuals, i.e. bit 0 is 2^0
83#define GET_FIELD_SP(X, FROM, TO) \
84 GET_FIELD(X, 31 - (TO), 31 - (FROM))
85
86#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 87#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 88
89#ifdef TARGET_SPARC64
90#define DFPREG(r) (((r & 1) << 6) | (r & 0x1e))
91#else
c185970a 92#define DFPREG(r) (r & 0x1e)
3475187d
FB		 93#endif
94
83469015
FB		 95#ifdef USE_DIRECT_JUMP
96#define TBPARAM(x)
97#else
98#define TBPARAM(x) (long)(x)
99#endif
100
3475187d
FB		 101static int sign_extend(int x, int len)
102{
103 len = 32 - len;
104 return (x << len) >> len;
105}
106
7a3f1944
FB		 107#define IS_IMM (insn & (1<<13))
108
cf495bcf 109static void disas_sparc_insn(DisasContext * dc);
7a3f1944 110
a68156d0 111static GenOpFunc * const gen_op_movl_TN_reg[2][32] = {
cf495bcf
FB		 112 {
113 gen_op_movl_g0_T0,
114 gen_op_movl_g1_T0,
115 gen_op_movl_g2_T0,
116 gen_op_movl_g3_T0,
117 gen_op_movl_g4_T0,
118 gen_op_movl_g5_T0,
119 gen_op_movl_g6_T0,
120 gen_op_movl_g7_T0,
121 gen_op_movl_o0_T0,
122 gen_op_movl_o1_T0,
123 gen_op_movl_o2_T0,
124 gen_op_movl_o3_T0,
125 gen_op_movl_o4_T0,
126 gen_op_movl_o5_T0,
127 gen_op_movl_o6_T0,
128 gen_op_movl_o7_T0,
129 gen_op_movl_l0_T0,
130 gen_op_movl_l1_T0,
131 gen_op_movl_l2_T0,
132 gen_op_movl_l3_T0,
133 gen_op_movl_l4_T0,
134 gen_op_movl_l5_T0,
135 gen_op_movl_l6_T0,
136 gen_op_movl_l7_T0,
137 gen_op_movl_i0_T0,
138 gen_op_movl_i1_T0,
139 gen_op_movl_i2_T0,
140 gen_op_movl_i3_T0,
141 gen_op_movl_i4_T0,
142 gen_op_movl_i5_T0,
143 gen_op_movl_i6_T0,
144 gen_op_movl_i7_T0,
145 },
146 {
147 gen_op_movl_g0_T1,
148 gen_op_movl_g1_T1,
149 gen_op_movl_g2_T1,
150 gen_op_movl_g3_T1,
151 gen_op_movl_g4_T1,
152 gen_op_movl_g5_T1,
153 gen_op_movl_g6_T1,
154 gen_op_movl_g7_T1,
155 gen_op_movl_o0_T1,
156 gen_op_movl_o1_T1,
157 gen_op_movl_o2_T1,
158 gen_op_movl_o3_T1,
159 gen_op_movl_o4_T1,
160 gen_op_movl_o5_T1,
161 gen_op_movl_o6_T1,
162 gen_op_movl_o7_T1,
163 gen_op_movl_l0_T1,
164 gen_op_movl_l1_T1,
165 gen_op_movl_l2_T1,
166 gen_op_movl_l3_T1,
167 gen_op_movl_l4_T1,
168 gen_op_movl_l5_T1,
169 gen_op_movl_l6_T1,
170 gen_op_movl_l7_T1,
171 gen_op_movl_i0_T1,
172 gen_op_movl_i1_T1,
173 gen_op_movl_i2_T1,
174 gen_op_movl_i3_T1,
175 gen_op_movl_i4_T1,
176 gen_op_movl_i5_T1,
177 gen_op_movl_i6_T1,
178 gen_op_movl_i7_T1,
179 }
7a3f1944
FB		 180};
181
a68156d0 182static GenOpFunc * const gen_op_movl_reg_TN[3][32] = {
cf495bcf
FB		 183 {
184 gen_op_movl_T0_g0,
185 gen_op_movl_T0_g1,
186 gen_op_movl_T0_g2,
187 gen_op_movl_T0_g3,
188 gen_op_movl_T0_g4,
189 gen_op_movl_T0_g5,
190 gen_op_movl_T0_g6,
191 gen_op_movl_T0_g7,
192 gen_op_movl_T0_o0,
193 gen_op_movl_T0_o1,
194 gen_op_movl_T0_o2,
195 gen_op_movl_T0_o3,
196 gen_op_movl_T0_o4,
197 gen_op_movl_T0_o5,
198 gen_op_movl_T0_o6,
199 gen_op_movl_T0_o7,
200 gen_op_movl_T0_l0,
201 gen_op_movl_T0_l1,
202 gen_op_movl_T0_l2,
203 gen_op_movl_T0_l3,
204 gen_op_movl_T0_l4,
205 gen_op_movl_T0_l5,
206 gen_op_movl_T0_l6,
207 gen_op_movl_T0_l7,
208 gen_op_movl_T0_i0,
209 gen_op_movl_T0_i1,
210 gen_op_movl_T0_i2,
211 gen_op_movl_T0_i3,
212 gen_op_movl_T0_i4,
213 gen_op_movl_T0_i5,
214 gen_op_movl_T0_i6,
215 gen_op_movl_T0_i7,
216 },
217 {
218 gen_op_movl_T1_g0,
219 gen_op_movl_T1_g1,
220 gen_op_movl_T1_g2,
221 gen_op_movl_T1_g3,
222 gen_op_movl_T1_g4,
223 gen_op_movl_T1_g5,
224 gen_op_movl_T1_g6,
225 gen_op_movl_T1_g7,
226 gen_op_movl_T1_o0,
227 gen_op_movl_T1_o1,
228 gen_op_movl_T1_o2,
229 gen_op_movl_T1_o3,
230 gen_op_movl_T1_o4,
231 gen_op_movl_T1_o5,
232 gen_op_movl_T1_o6,
233 gen_op_movl_T1_o7,
234 gen_op_movl_T1_l0,
235 gen_op_movl_T1_l1,
236 gen_op_movl_T1_l2,
237 gen_op_movl_T1_l3,
238 gen_op_movl_T1_l4,
239 gen_op_movl_T1_l5,
240 gen_op_movl_T1_l6,
241 gen_op_movl_T1_l7,
242 gen_op_movl_T1_i0,
243 gen_op_movl_T1_i1,
244 gen_op_movl_T1_i2,
245 gen_op_movl_T1_i3,
246 gen_op_movl_T1_i4,
247 gen_op_movl_T1_i5,
248 gen_op_movl_T1_i6,
249 gen_op_movl_T1_i7,
250 },
251 {
252 gen_op_movl_T2_g0,
253 gen_op_movl_T2_g1,
254 gen_op_movl_T2_g2,
255 gen_op_movl_T2_g3,
256 gen_op_movl_T2_g4,
257 gen_op_movl_T2_g5,
258 gen_op_movl_T2_g6,
259 gen_op_movl_T2_g7,
260 gen_op_movl_T2_o0,
261 gen_op_movl_T2_o1,
262 gen_op_movl_T2_o2,
263 gen_op_movl_T2_o3,
264 gen_op_movl_T2_o4,
265 gen_op_movl_T2_o5,
266 gen_op_movl_T2_o6,
267 gen_op_movl_T2_o7,
268 gen_op_movl_T2_l0,
269 gen_op_movl_T2_l1,
270 gen_op_movl_T2_l2,
271 gen_op_movl_T2_l3,
272 gen_op_movl_T2_l4,
273 gen_op_movl_T2_l5,
274 gen_op_movl_T2_l6,
275 gen_op_movl_T2_l7,
276 gen_op_movl_T2_i0,
277 gen_op_movl_T2_i1,
278 gen_op_movl_T2_i2,
279 gen_op_movl_T2_i3,
280 gen_op_movl_T2_i4,
281 gen_op_movl_T2_i5,
282 gen_op_movl_T2_i6,
283 gen_op_movl_T2_i7,
284 }
7a3f1944
FB		 285};
286
a68156d0 287static GenOpFunc1 * const gen_op_movl_TN_im[3] = {
cf495bcf
FB		 288 gen_op_movl_T0_im,
289 gen_op_movl_T1_im,
290 gen_op_movl_T2_im
7a3f1944
FB		 291};
292
3475187d
FB		 293// Sign extending version
294static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {
295 gen_op_movl_T0_sim,
296 gen_op_movl_T1_sim,
297 gen_op_movl_T2_sim
298};
299
300#ifdef TARGET_SPARC64
301#define GEN32(func, NAME) \
a68156d0 302static GenOpFunc * const NAME ## _table [64] = { \
3475187d
FB		 303NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
304NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
305NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
306NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
307NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
308NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
309NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
310NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
311NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
312NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
313NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
314NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
315}; \
316static inline void func(int n) \
317{ \
318 NAME ## _table[n](); \
319}
320#else
e8af50a3 321#define GEN32(func, NAME) \
a68156d0 322static GenOpFunc *const NAME ## _table [32] = { \
e8af50a3
FB		 323NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
324NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
325NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
326NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
327NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
328NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
329NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
330NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
331}; \
332static inline void func(int n) \
333{ \
334 NAME ## _table[n](); \
335}
3475187d 336#endif
e8af50a3
FB		 337
338/* floating point registers moves */
339GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
340GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
e8af50a3
FB		 341GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
342GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
e8af50a3
FB		 343
344GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
345GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
e8af50a3
FB		 346GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
347GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
e8af50a3 348
6ea4a6c8
BS		 349#ifdef ALIGN_7_BUGS_FIXED
350#else
351#ifndef CONFIG_USER_ONLY
352#define gen_op_check_align_T0_7()
353#endif
354#endif
355
81ad8ba2
BS		 356/* moves */
357#ifdef CONFIG_USER_ONLY
3475187d 358#define supervisor(dc) 0
81ad8ba2 359#ifdef TARGET_SPARC64
e9ebed4d 360#define hypervisor(dc) 0
81ad8ba2 361#endif
3475187d 362#define gen_op_ldst(name) gen_op_##name##_raw()
3475187d 363#else
81ad8ba2
BS		 364#define supervisor(dc) (dc->mem_idx == 1)
365#ifdef TARGET_SPARC64
366#define hypervisor(dc) (dc->mem_idx == 2)
367#endif
3475187d 368#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
0f8a249a 369#define OP_LD_TABLE(width) \
a68156d0 370 static GenOpFunc * const gen_op_##width[] = { \
0f8a249a
BS		 371 &gen_op_##width##_user, \
372 &gen_op_##width##_kernel, \
81ad8ba2 373 };
3475187d 374#endif
e8af50a3 375
81ad8ba2 376#ifndef CONFIG_USER_ONLY
e8af50a3
FB		 377OP_LD_TABLE(ld);
378OP_LD_TABLE(st);
379OP_LD_TABLE(ldub);
380OP_LD_TABLE(lduh);
381OP_LD_TABLE(ldsb);
382OP_LD_TABLE(ldsh);
383OP_LD_TABLE(stb);
384OP_LD_TABLE(sth);
385OP_LD_TABLE(std);
386OP_LD_TABLE(ldstub);
387OP_LD_TABLE(swap);
388OP_LD_TABLE(ldd);
389OP_LD_TABLE(stf);
390OP_LD_TABLE(stdf);
391OP_LD_TABLE(ldf);
392OP_LD_TABLE(lddf);
393
3475187d 394#ifdef TARGET_SPARC64
dc011987 395OP_LD_TABLE(lduw);
3475187d
FB		 396OP_LD_TABLE(ldsw);
397OP_LD_TABLE(ldx);
398OP_LD_TABLE(stx);
81ad8ba2
BS		 399#endif
400#endif
401
402/* asi moves */
403#ifdef TARGET_SPARC64
404static inline void gen_ld_asi(int insn, int size, int sign)
405{
406 int asi, offset;
407
408 if (IS_IMM) {
409 offset = GET_FIELD(insn, 25, 31);
410 gen_op_ld_asi_reg(offset, size, sign);
411 } else {
412 asi = GET_FIELD(insn, 19, 26);
413 gen_op_ld_asi(asi, size, sign);
414 }
415}
416
417static inline void gen_st_asi(int insn, int size)
418{
419 int asi, offset;
420
421 if (IS_IMM) {
422 offset = GET_FIELD(insn, 25, 31);
423 gen_op_st_asi_reg(offset, size);
424 } else {
425 asi = GET_FIELD(insn, 19, 26);
426 gen_op_st_asi(asi, size);
427 }
428}
429
430static inline void gen_swap_asi(int insn)
431{
432 int asi, offset;
433
434 if (IS_IMM) {
435 offset = GET_FIELD(insn, 25, 31);
436 gen_op_swap_asi_reg(offset);
437 } else {
438 asi = GET_FIELD(insn, 19, 26);
439 gen_op_swap_asi(asi);
440 }
441}
442
443static inline void gen_ldstub_asi(int insn)
444{
445 int asi, offset;
446
447 if (IS_IMM) {
448 offset = GET_FIELD(insn, 25, 31);
449 gen_op_ldstub_asi_reg(offset);
450 } else {
451 asi = GET_FIELD(insn, 19, 26);
452 gen_op_ldstub_asi(asi);
453 }
454}
455
456static inline void gen_ldda_asi(int insn)
457{
458 int asi, offset;
459
460 if (IS_IMM) {
461 offset = GET_FIELD(insn, 25, 31);
462 gen_op_ldda_asi_reg(offset);
463 } else {
464 asi = GET_FIELD(insn, 19, 26);
465 gen_op_ldda_asi(asi);
466 }
467}
468
469static inline void gen_stda_asi(int insn)
470{
471 int asi, offset;
472
473 if (IS_IMM) {
474 offset = GET_FIELD(insn, 25, 31);
475 gen_op_stda_asi_reg(offset);
476 } else {
477 asi = GET_FIELD(insn, 19, 26);
478 gen_op_stda_asi(asi);
479 }
480}
481
482static inline void gen_cas_asi(int insn)
483{
484 int asi, offset;
485
486 if (IS_IMM) {
487 offset = GET_FIELD(insn, 25, 31);
488 gen_op_cas_asi_reg(offset);
489 } else {
490 asi = GET_FIELD(insn, 19, 26);
491 gen_op_cas_asi(asi);
492 }
493}
494
495static inline void gen_casx_asi(int insn)
496{
497 int asi, offset;
498
499 if (IS_IMM) {
500 offset = GET_FIELD(insn, 25, 31);
501 gen_op_casx_asi_reg(offset);
502 } else {
503 asi = GET_FIELD(insn, 19, 26);
504 gen_op_casx_asi(asi);
505 }
506}
507
508#elif !defined(CONFIG_USER_ONLY)
509
510static inline void gen_ld_asi(int insn, int size, int sign)
511{
512 int asi;
513
514 asi = GET_FIELD(insn, 19, 26);
515 gen_op_ld_asi(asi, size, sign);
516}
517
518static inline void gen_st_asi(int insn, int size)
519{
520 int asi;
521
522 asi = GET_FIELD(insn, 19, 26);
523 gen_op_st_asi(asi, size);
524}
525
526static inline void gen_ldstub_asi(int insn)
527{
528 int asi;
529
530 asi = GET_FIELD(insn, 19, 26);
531 gen_op_ldstub_asi(asi);
532}
533
534static inline void gen_swap_asi(int insn)
535{
536 int asi;
537
538 asi = GET_FIELD(insn, 19, 26);
539 gen_op_swap_asi(asi);
540}
541
542static inline void gen_ldda_asi(int insn)
543{
544 int asi;
545
546 asi = GET_FIELD(insn, 19, 26);
547 gen_op_ld_asi(asi, 8, 0);
548}
549
550static inline void gen_stda_asi(int insn)
551{
552 int asi;
553
554 asi = GET_FIELD(insn, 19, 26);
555 gen_op_st_asi(asi, 8);
556}
3475187d
FB		 557#endif
558
559static inline void gen_movl_imm_TN(int reg, uint32_t imm)
7a3f1944 560{
83469015 561 gen_op_movl_TN_im[reg](imm);
7a3f1944
FB		 562}
563
3475187d 564static inline void gen_movl_imm_T1(uint32_t val)
7a3f1944 565{
cf495bcf 566 gen_movl_imm_TN(1, val);
7a3f1944
FB		 567}
568
3475187d 569static inline void gen_movl_imm_T0(uint32_t val)
7a3f1944 570{
cf495bcf 571 gen_movl_imm_TN(0, val);
7a3f1944
FB		 572}
573
3475187d
FB		 574static inline void gen_movl_simm_TN(int reg, int32_t imm)
575{
576 gen_op_movl_TN_sim[reg](imm);
577}
578
579static inline void gen_movl_simm_T1(int32_t val)
580{
581 gen_movl_simm_TN(1, val);
582}
583
584static inline void gen_movl_simm_T0(int32_t val)
585{
586 gen_movl_simm_TN(0, val);
587}
588
cf495bcf 589static inline void gen_movl_reg_TN(int reg, int t)
7a3f1944 590{
cf495bcf 591 if (reg)
0f8a249a 592 gen_op_movl_reg_TN[t][reg] ();
cf495bcf 593 else
0f8a249a 594 gen_movl_imm_TN(t, 0);
7a3f1944
FB		 595}
596
cf495bcf 597static inline void gen_movl_reg_T0(int reg)
7a3f1944 598{
cf495bcf 599 gen_movl_reg_TN(reg, 0);
7a3f1944
FB		 600}
601
cf495bcf 602static inline void gen_movl_reg_T1(int reg)
7a3f1944 603{
cf495bcf 604 gen_movl_reg_TN(reg, 1);
7a3f1944
FB		 605}
606
cf495bcf 607static inline void gen_movl_reg_T2(int reg)
7a3f1944 608{
cf495bcf 609 gen_movl_reg_TN(reg, 2);
7a3f1944
FB		 610}
611
cf495bcf 612static inline void gen_movl_TN_reg(int reg, int t)
7a3f1944 613{
cf495bcf 614 if (reg)
0f8a249a 615 gen_op_movl_TN_reg[t][reg] ();
7a3f1944
FB		 616}
617
cf495bcf 618static inline void gen_movl_T0_reg(int reg)
7a3f1944 619{
cf495bcf 620 gen_movl_TN_reg(reg, 0);
7a3f1944
FB		 621}
622
cf495bcf 623static inline void gen_movl_T1_reg(int reg)
7a3f1944 624{
cf495bcf 625 gen_movl_TN_reg(reg, 1);
7a3f1944
FB		 626}
627
3475187d
FB		 628static inline void gen_jmp_im(target_ulong pc)
629{
630#ifdef TARGET_SPARC64
631 if (pc == (uint32_t)pc) {
632 gen_op_jmp_im(pc);
633 } else {
634 gen_op_jmp_im64(pc >> 32, pc);
635 }
636#else
637 gen_op_jmp_im(pc);
638#endif
639}
640
641static inline void gen_movl_npc_im(target_ulong npc)
642{
643#ifdef TARGET_SPARC64
644 if (npc == (uint32_t)npc) {
645 gen_op_movl_npc_im(npc);
646 } else {
647 gen_op_movq_npc_im64(npc >> 32, npc);
648 }
649#else
650 gen_op_movl_npc_im(npc);
651#endif
652}
653
5fafdf24 654static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 655 target_ulong pc, target_ulong npc)
656{
657 TranslationBlock *tb;
658
659 tb = s->tb;
660 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
661 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
662 /* jump to same page: we can use a direct jump */
663 if (tb_num == 0)
664 gen_op_goto_tb0(TBPARAM(tb));
665 else
666 gen_op_goto_tb1(TBPARAM(tb));
667 gen_jmp_im(pc);
668 gen_movl_npc_im(npc);
669 gen_op_movl_T0_im((long)tb + tb_num);
670 gen_op_exit_tb();
671 } else {
672 /* jump to another page: currently not optimized */
673 gen_jmp_im(pc);
674 gen_movl_npc_im(npc);
675 gen_op_movl_T0_0();
676 gen_op_exit_tb();
677 }
678}
679
46525e1f
BS		 680static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
681 target_ulong pc2)
83469015
FB		 682{
683 int l1;
684
685 l1 = gen_new_label();
686
687 gen_op_jz_T2_label(l1);
688
6e256c93 689 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 690
691 gen_set_label(l1);
6e256c93 692 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 693}
694
46525e1f
BS		 695static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
696 target_ulong pc2)
83469015
FB		 697{
698 int l1;
699
700 l1 = gen_new_label();
701
702 gen_op_jz_T2_label(l1);
703
6e256c93 704 gen_goto_tb(dc, 0, pc2, pc1);
83469015
FB		 705
706 gen_set_label(l1);
6e256c93 707 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
83469015
FB		 708}
709
46525e1f
BS		 710static inline void gen_branch(DisasContext *dc, target_ulong pc,
711 target_ulong npc)
83469015 712{
6e256c93 713 gen_goto_tb(dc, 0, pc, npc);
83469015
FB		 714}
715
46525e1f 716static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2)
83469015
FB		 717{
718 int l1, l2;
719
720 l1 = gen_new_label();
721 l2 = gen_new_label();
722 gen_op_jz_T2_label(l1);
723
724 gen_movl_npc_im(npc1);
725 gen_op_jmp_label(l2);
726
727 gen_set_label(l1);
728 gen_movl_npc_im(npc2);
729 gen_set_label(l2);
730}
731
732/* call this function before using T2 as it may have been set for a jump */
733static inline void flush_T2(DisasContext * dc)
734{
735 if (dc->npc == JUMP_PC) {
46525e1f 736 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
83469015
FB		 737 dc->npc = DYNAMIC_PC;
738 }
739}
740
72cbca10
FB		 741static inline void save_npc(DisasContext * dc)
742{
743 if (dc->npc == JUMP_PC) {
46525e1f 744 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
72cbca10
FB		 745 dc->npc = DYNAMIC_PC;
746 } else if (dc->npc != DYNAMIC_PC) {
3475187d 747 gen_movl_npc_im(dc->npc);
72cbca10
FB		 748 }
749}
750
751static inline void save_state(DisasContext * dc)
752{
3475187d 753 gen_jmp_im(dc->pc);
72cbca10
FB		 754 save_npc(dc);
755}
756
0bee699e
FB		 757static inline void gen_mov_pc_npc(DisasContext * dc)
758{
759 if (dc->npc == JUMP_PC) {
46525e1f 760 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
0bee699e
FB		 761 gen_op_mov_pc_npc();
762 dc->pc = DYNAMIC_PC;
763 } else if (dc->npc == DYNAMIC_PC) {
764 gen_op_mov_pc_npc();
765 dc->pc = DYNAMIC_PC;
766 } else {
767 dc->pc = dc->npc;
768 }
769}
770
3475187d
FB		 771static GenOpFunc * const gen_cond[2][16] = {
772 {
0f8a249a
BS		 773 gen_op_eval_bn,
774 gen_op_eval_be,
775 gen_op_eval_ble,
776 gen_op_eval_bl,
777 gen_op_eval_bleu,
778 gen_op_eval_bcs,
779 gen_op_eval_bneg,
780 gen_op_eval_bvs,
781 gen_op_eval_ba,
782 gen_op_eval_bne,
783 gen_op_eval_bg,
784 gen_op_eval_bge,
785 gen_op_eval_bgu,
786 gen_op_eval_bcc,
787 gen_op_eval_bpos,
788 gen_op_eval_bvc,
3475187d
FB		 789 },
790 {
791#ifdef TARGET_SPARC64
0f8a249a
BS		 792 gen_op_eval_bn,
793 gen_op_eval_xbe,
794 gen_op_eval_xble,
795 gen_op_eval_xbl,
796 gen_op_eval_xbleu,
797 gen_op_eval_xbcs,
798 gen_op_eval_xbneg,
799 gen_op_eval_xbvs,
800 gen_op_eval_ba,
801 gen_op_eval_xbne,
802 gen_op_eval_xbg,
803 gen_op_eval_xbge,
804 gen_op_eval_xbgu,
805 gen_op_eval_xbcc,
806 gen_op_eval_xbpos,
807 gen_op_eval_xbvc,
3475187d
FB		 808#endif
809 },
810};
811
812static GenOpFunc * const gen_fcond[4][16] = {
813 {
0f8a249a
BS		 814 gen_op_eval_bn,
815 gen_op_eval_fbne,
816 gen_op_eval_fblg,
817 gen_op_eval_fbul,
818 gen_op_eval_fbl,
819 gen_op_eval_fbug,
820 gen_op_eval_fbg,
821 gen_op_eval_fbu,
822 gen_op_eval_ba,
823 gen_op_eval_fbe,
824 gen_op_eval_fbue,
825 gen_op_eval_fbge,
826 gen_op_eval_fbuge,
827 gen_op_eval_fble,
828 gen_op_eval_fbule,
829 gen_op_eval_fbo,
3475187d
FB		 830 },
831#ifdef TARGET_SPARC64
832 {
0f8a249a
BS		 833 gen_op_eval_bn,
834 gen_op_eval_fbne_fcc1,
835 gen_op_eval_fblg_fcc1,
836 gen_op_eval_fbul_fcc1,
837 gen_op_eval_fbl_fcc1,
838 gen_op_eval_fbug_fcc1,
839 gen_op_eval_fbg_fcc1,
840 gen_op_eval_fbu_fcc1,
841 gen_op_eval_ba,
842 gen_op_eval_fbe_fcc1,
843 gen_op_eval_fbue_fcc1,
844 gen_op_eval_fbge_fcc1,
845 gen_op_eval_fbuge_fcc1,
846 gen_op_eval_fble_fcc1,
847 gen_op_eval_fbule_fcc1,
848 gen_op_eval_fbo_fcc1,
3475187d
FB		 849 },
850 {
0f8a249a
BS		 851 gen_op_eval_bn,
852 gen_op_eval_fbne_fcc2,
853 gen_op_eval_fblg_fcc2,
854 gen_op_eval_fbul_fcc2,
855 gen_op_eval_fbl_fcc2,
856 gen_op_eval_fbug_fcc2,
857 gen_op_eval_fbg_fcc2,
858 gen_op_eval_fbu_fcc2,
859 gen_op_eval_ba,
860 gen_op_eval_fbe_fcc2,
861 gen_op_eval_fbue_fcc2,
862 gen_op_eval_fbge_fcc2,
863 gen_op_eval_fbuge_fcc2,
864 gen_op_eval_fble_fcc2,
865 gen_op_eval_fbule_fcc2,
866 gen_op_eval_fbo_fcc2,
3475187d
FB		 867 },
868 {
0f8a249a
BS		 869 gen_op_eval_bn,
870 gen_op_eval_fbne_fcc3,
871 gen_op_eval_fblg_fcc3,
872 gen_op_eval_fbul_fcc3,
873 gen_op_eval_fbl_fcc3,
874 gen_op_eval_fbug_fcc3,
875 gen_op_eval_fbg_fcc3,
876 gen_op_eval_fbu_fcc3,
877 gen_op_eval_ba,
878 gen_op_eval_fbe_fcc3,
879 gen_op_eval_fbue_fcc3,
880 gen_op_eval_fbge_fcc3,
881 gen_op_eval_fbuge_fcc3,
882 gen_op_eval_fble_fcc3,
883 gen_op_eval_fbule_fcc3,
884 gen_op_eval_fbo_fcc3,
3475187d
FB		 885 },
886#else
887 {}, {}, {},
888#endif
889};
7a3f1944 890
3475187d
FB		 891#ifdef TARGET_SPARC64
892static void gen_cond_reg(int cond)
e8af50a3 893{
0f8a249a
BS		 894 switch (cond) {
895 case 0x1:
896 gen_op_eval_brz();
897 break;
898 case 0x2:
899 gen_op_eval_brlez();
900 break;
901 case 0x3:
902 gen_op_eval_brlz();
903 break;
904 case 0x5:
905 gen_op_eval_brnz();
906 break;
907 case 0x6:
908 gen_op_eval_brgz();
909 break;
e8af50a3 910 default:
0f8a249a
BS		 911 case 0x7:
912 gen_op_eval_brgez();
913 break;
914 }
e8af50a3 915}
3475187d 916#endif
cf495bcf 917
0bee699e 918/* XXX: potentially incorrect if dynamic npc */
3475187d 919static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 920{
cf495bcf 921 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 922 target_ulong target = dc->pc + offset;
5fafdf24 923
cf495bcf 924 if (cond == 0x0) {
0f8a249a
BS		 925 /* unconditional not taken */
926 if (a) {
927 dc->pc = dc->npc + 4;
928 dc->npc = dc->pc + 4;
929 } else {
930 dc->pc = dc->npc;
931 dc->npc = dc->pc + 4;
932 }
cf495bcf 933 } else if (cond == 0x8) {
0f8a249a
BS		 934 /* unconditional taken */
935 if (a) {
936 dc->pc = target;
937 dc->npc = dc->pc + 4;
938 } else {
939 dc->pc = dc->npc;
940 dc->npc = target;
941 }
cf495bcf 942 } else {
72cbca10 943 flush_T2(dc);
3475187d 944 gen_cond[cc][cond]();
0f8a249a
BS		 945 if (a) {
946 gen_branch_a(dc, target, dc->npc);
cf495bcf 947 dc->is_br = 1;
0f8a249a 948 } else {
cf495bcf 949 dc->pc = dc->npc;
72cbca10
FB		 950 dc->jump_pc[0] = target;
951 dc->jump_pc[1] = dc->npc + 4;
952 dc->npc = JUMP_PC;
0f8a249a 953 }
cf495bcf 954 }
7a3f1944
FB		 955}
956
0bee699e 957/* XXX: potentially incorrect if dynamic npc */
3475187d 958static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 959{
960 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 961 target_ulong target = dc->pc + offset;
962
e8af50a3 963 if (cond == 0x0) {
0f8a249a
BS		 964 /* unconditional not taken */
965 if (a) {
966 dc->pc = dc->npc + 4;
967 dc->npc = dc->pc + 4;
968 } else {
969 dc->pc = dc->npc;
970 dc->npc = dc->pc + 4;
971 }
e8af50a3 972 } else if (cond == 0x8) {
0f8a249a
BS		 973 /* unconditional taken */
974 if (a) {
975 dc->pc = target;
976 dc->npc = dc->pc + 4;
977 } else {
978 dc->pc = dc->npc;
979 dc->npc = target;
980 }
e8af50a3
FB		 981 } else {
982 flush_T2(dc);
3475187d 983 gen_fcond[cc][cond]();
0f8a249a
BS		 984 if (a) {
985 gen_branch_a(dc, target, dc->npc);
e8af50a3 986 dc->is_br = 1;
0f8a249a 987 } else {
e8af50a3
FB		 988 dc->pc = dc->npc;
989 dc->jump_pc[0] = target;
990 dc->jump_pc[1] = dc->npc + 4;
991 dc->npc = JUMP_PC;
0f8a249a 992 }
e8af50a3
FB		 993 }
994}
995
3475187d
FB		 996#ifdef TARGET_SPARC64
997/* XXX: potentially incorrect if dynamic npc */
998static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
7a3f1944 999{
3475187d
FB		 1000 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1001 target_ulong target = dc->pc + offset;
1002
1003 flush_T2(dc);
1004 gen_cond_reg(cond);
1005 if (a) {
0f8a249a
BS		 1006 gen_branch_a(dc, target, dc->npc);
1007 dc->is_br = 1;
3475187d 1008 } else {
0f8a249a
BS		 1009 dc->pc = dc->npc;
1010 dc->jump_pc[0] = target;
1011 dc->jump_pc[1] = dc->npc + 4;
1012 dc->npc = JUMP_PC;
3475187d 1013 }
7a3f1944
FB		 1014}
1015
3475187d
FB		 1016static GenOpFunc * const gen_fcmps[4] = {
1017 gen_op_fcmps,
1018 gen_op_fcmps_fcc1,
1019 gen_op_fcmps_fcc2,
1020 gen_op_fcmps_fcc3,
1021};
1022
1023static GenOpFunc * const gen_fcmpd[4] = {
1024 gen_op_fcmpd,
1025 gen_op_fcmpd_fcc1,
1026 gen_op_fcmpd_fcc2,
1027 gen_op_fcmpd_fcc3,
1028};
417454b0
BS		 1029
1030static GenOpFunc * const gen_fcmpes[4] = {
1031 gen_op_fcmpes,
1032 gen_op_fcmpes_fcc1,
1033 gen_op_fcmpes_fcc2,
1034 gen_op_fcmpes_fcc3,
1035};
1036
1037static GenOpFunc * const gen_fcmped[4] = {
1038 gen_op_fcmped,
1039 gen_op_fcmped_fcc1,
1040 gen_op_fcmped_fcc2,
1041 gen_op_fcmped_fcc3,
1042};
1043
3475187d
FB		 1044#endif
1045
a80dde08
FB		 1046static int gen_trap_ifnofpu(DisasContext * dc)
1047{
1048#if !defined(CONFIG_USER_ONLY)
1049 if (!dc->fpu_enabled) {
1050 save_state(dc);
1051 gen_op_exception(TT_NFPU_INSN);
1052 dc->is_br = 1;
1053 return 1;
1054 }
1055#endif
1056 return 0;
1057}
1058
0bee699e 1059/* before an instruction, dc->pc must be static */
cf495bcf
FB		 1060static void disas_sparc_insn(DisasContext * dc)
1061{
1062 unsigned int insn, opc, rs1, rs2, rd;
7a3f1944 1063
0fa85d43 1064 insn = ldl_code(dc->pc);
cf495bcf 1065 opc = GET_FIELD(insn, 0, 1);
7a3f1944 1066
cf495bcf
FB		 1067 rd = GET_FIELD(insn, 2, 6);
1068 switch (opc) {
0f8a249a
BS		 1069 case 0: /* branches/sethi */
1070 {
1071 unsigned int xop = GET_FIELD(insn, 7, 9);
1072 int32_t target;
1073 switch (xop) {
3475187d 1074#ifdef TARGET_SPARC64
0f8a249a
BS		 1075 case 0x1: /* V9 BPcc */
1076 {
1077 int cc;
1078
1079 target = GET_FIELD_SP(insn, 0, 18);
1080 target = sign_extend(target, 18);
1081 target <<= 2;
1082 cc = GET_FIELD_SP(insn, 20, 21);
1083 if (cc == 0)
1084 do_branch(dc, target, insn, 0);
1085 else if (cc == 2)
1086 do_branch(dc, target, insn, 1);
1087 else
1088 goto illegal_insn;
1089 goto jmp_insn;
1090 }
1091 case 0x3: /* V9 BPr */
1092 {
1093 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 1094 (GET_FIELD_SP(insn, 20, 21) << 14);
0f8a249a
BS		 1095 target = sign_extend(target, 16);
1096 target <<= 2;
1097 rs1 = GET_FIELD(insn, 13, 17);
1098 gen_movl_reg_T0(rs1);
1099 do_branch_reg(dc, target, insn);
1100 goto jmp_insn;
1101 }
1102 case 0x5: /* V9 FBPcc */
1103 {
1104 int cc = GET_FIELD_SP(insn, 20, 21);
a80dde08
FB		 1105 if (gen_trap_ifnofpu(dc))
1106 goto jmp_insn;
0f8a249a
BS		 1107 target = GET_FIELD_SP(insn, 0, 18);
1108 target = sign_extend(target, 19);
1109 target <<= 2;
1110 do_fbranch(dc, target, insn, cc);
1111 goto jmp_insn;
1112 }
a4d17f19 1113#else
0f8a249a
BS		 1114 case 0x7: /* CBN+x */
1115 {
1116 goto ncp_insn;
1117 }
1118#endif
1119 case 0x2: /* BN+x */
1120 {
1121 target = GET_FIELD(insn, 10, 31);
1122 target = sign_extend(target, 22);
1123 target <<= 2;
1124 do_branch(dc, target, insn, 0);
1125 goto jmp_insn;
1126 }
1127 case 0x6: /* FBN+x */
1128 {
a80dde08
FB		 1129 if (gen_trap_ifnofpu(dc))
1130 goto jmp_insn;
0f8a249a
BS		 1131 target = GET_FIELD(insn, 10, 31);
1132 target = sign_extend(target, 22);
1133 target <<= 2;
1134 do_fbranch(dc, target, insn, 0);
1135 goto jmp_insn;
1136 }
1137 case 0x4: /* SETHI */
e80cfcfc
FB		 1138#define OPTIM
1139#if defined(OPTIM)
0f8a249a 1140 if (rd) { // nop
e80cfcfc 1141#endif
0f8a249a
BS		 1142 uint32_t value = GET_FIELD(insn, 10, 31);
1143 gen_movl_imm_T0(value << 10);
1144 gen_movl_T0_reg(rd);
e80cfcfc 1145#if defined(OPTIM)
0f8a249a 1146 }
e80cfcfc 1147#endif
0f8a249a
BS		 1148 break;
1149 case 0x0: /* UNIMPL */
1150 default:
3475187d 1151 goto illegal_insn;
0f8a249a
BS		 1152 }
1153 break;
1154 }
1155 break;
cf495bcf 1156 case 1:
0f8a249a
BS		 1157 /*CALL*/ {
1158 target_long target = GET_FIELDs(insn, 2, 31) << 2;
cf495bcf 1159
83469015 1160#ifdef TARGET_SPARC64
0f8a249a
BS		 1161 if (dc->pc == (uint32_t)dc->pc) {
1162 gen_op_movl_T0_im(dc->pc);
1163 } else {
1164 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1165 }
83469015 1166#else
0f8a249a 1167 gen_op_movl_T0_im(dc->pc);
83469015 1168#endif
0f8a249a
BS		 1169 gen_movl_T0_reg(15);
1170 target += dc->pc;
0bee699e 1171 gen_mov_pc_npc(dc);
0f8a249a
BS		 1172 dc->npc = target;
1173 }
1174 goto jmp_insn;
1175 case 2: /* FPU & Logical Operations */
1176 {
1177 unsigned int xop = GET_FIELD(insn, 7, 12);
1178 if (xop == 0x3a) { /* generate trap */
cf495bcf 1179 int cond;
3475187d 1180
cf495bcf
FB		 1181 rs1 = GET_FIELD(insn, 13, 17);
1182 gen_movl_reg_T0(rs1);
0f8a249a
BS		 1183 if (IS_IMM) {
1184 rs2 = GET_FIELD(insn, 25, 31);
e80cfcfc 1185#if defined(OPTIM)
0f8a249a 1186 if (rs2 != 0) {
e80cfcfc 1187#endif
0f8a249a
BS		 1188 gen_movl_simm_T1(rs2);
1189 gen_op_add_T1_T0();
e80cfcfc 1190#if defined(OPTIM)
0f8a249a 1191 }
e80cfcfc 1192#endif
cf495bcf
FB		 1193 } else {
1194 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc 1195#if defined(OPTIM)
0f8a249a 1196 if (rs2 != 0) {
e80cfcfc 1197#endif
0f8a249a
BS		 1198 gen_movl_reg_T1(rs2);
1199 gen_op_add_T1_T0();
e80cfcfc 1200#if defined(OPTIM)
0f8a249a 1201 }
e80cfcfc 1202#endif
cf495bcf 1203 }
cf495bcf
FB		 1204 cond = GET_FIELD(insn, 3, 6);
1205 if (cond == 0x8) {
a80dde08 1206 save_state(dc);
cf495bcf 1207 gen_op_trap_T0();
af7bf89b 1208 } else if (cond != 0) {
3475187d 1209#ifdef TARGET_SPARC64
0f8a249a
BS		 1210 /* V9 icc/xcc */
1211 int cc = GET_FIELD_SP(insn, 11, 12);
1212 flush_T2(dc);
a80dde08 1213 save_state(dc);
0f8a249a
BS		 1214 if (cc == 0)
1215 gen_cond[0][cond]();
1216 else if (cc == 2)
1217 gen_cond[1][cond]();
1218 else
1219 goto illegal_insn;
3475187d 1220#else
0f8a249a 1221 flush_T2(dc);
a80dde08 1222 save_state(dc);
0f8a249a 1223 gen_cond[0][cond]();
3475187d 1224#endif
cf495bcf
FB		 1225 gen_op_trapcc_T0();
1226 }
a80dde08
FB		 1227 gen_op_next_insn();
1228 gen_op_movl_T0_0();
1229 gen_op_exit_tb();
1230 dc->is_br = 1;
1231 goto jmp_insn;
cf495bcf
FB		 1232 } else if (xop == 0x28) {
1233 rs1 = GET_FIELD(insn, 13, 17);
1234 switch(rs1) {
1235 case 0: /* rdy */
65fe7b09
BS		 1236#ifndef TARGET_SPARC64
1237 case 0x01 ... 0x0e: /* undefined in the SPARCv8
1238 manual, rdy on the microSPARC
1239 II */
1240 case 0x0f: /* stbar in the SPARCv8 manual,
1241 rdy on the microSPARC II */
1242 case 0x10 ... 0x1f: /* implementation-dependent in the
1243 SPARCv8 manual, rdy on the
1244 microSPARC II */
1245#endif
1246 gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
cf495bcf
FB		 1247 gen_movl_T0_reg(rd);
1248 break;
3475187d 1249#ifdef TARGET_SPARC64
0f8a249a 1250 case 0x2: /* V9 rdccr */
3475187d
FB		 1251 gen_op_rdccr();
1252 gen_movl_T0_reg(rd);
1253 break;
0f8a249a
BS		 1254 case 0x3: /* V9 rdasi */
1255 gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
3475187d
FB		 1256 gen_movl_T0_reg(rd);
1257 break;
0f8a249a 1258 case 0x4: /* V9 rdtick */
3475187d
FB		 1259 gen_op_rdtick();
1260 gen_movl_T0_reg(rd);
1261 break;
0f8a249a
BS		 1262 case 0x5: /* V9 rdpc */
1263 if (dc->pc == (uint32_t)dc->pc) {
1264 gen_op_movl_T0_im(dc->pc);
1265 } else {
1266 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1267 }
1268 gen_movl_T0_reg(rd);
1269 break;
1270 case 0x6: /* V9 rdfprs */
1271 gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
3475187d
FB		 1272 gen_movl_T0_reg(rd);
1273 break;
65fe7b09
BS		 1274 case 0xf: /* V9 membar */
1275 break; /* no effect */
0f8a249a 1276 case 0x13: /* Graphics Status */
725cb90b
FB		 1277 if (gen_trap_ifnofpu(dc))
1278 goto jmp_insn;
0f8a249a 1279 gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
725cb90b
FB		 1280 gen_movl_T0_reg(rd);
1281 break;
0f8a249a
BS		 1282 case 0x17: /* Tick compare */
1283 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
83469015
FB		 1284 gen_movl_T0_reg(rd);
1285 break;
0f8a249a 1286 case 0x18: /* System tick */
20c9f095 1287 gen_op_rdstick();
83469015
FB		 1288 gen_movl_T0_reg(rd);
1289 break;
0f8a249a
BS		 1290 case 0x19: /* System tick compare */
1291 gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
83469015
FB		 1292 gen_movl_T0_reg(rd);
1293 break;
0f8a249a
BS		 1294 case 0x10: /* Performance Control */
1295 case 0x11: /* Performance Instrumentation Counter */
1296 case 0x12: /* Dispatch Control */
1297 case 0x14: /* Softint set, WO */
1298 case 0x15: /* Softint clear, WO */
1299 case 0x16: /* Softint write */
3475187d
FB		 1300#endif
1301 default:
cf495bcf
FB		 1302 goto illegal_insn;
1303 }
e8af50a3 1304#if !defined(CONFIG_USER_ONLY)
e9ebed4d 1305 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 1306#ifndef TARGET_SPARC64
0f8a249a
BS		 1307 if (!supervisor(dc))
1308 goto priv_insn;
e8af50a3 1309 gen_op_rdpsr();
e9ebed4d
BS		 1310#else
1311 if (!hypervisor(dc))
1312 goto priv_insn;
1313 rs1 = GET_FIELD(insn, 13, 17);
1314 switch (rs1) {
1315 case 0: // hpstate
1316 // gen_op_rdhpstate();
1317 break;
1318 case 1: // htstate
1319 // gen_op_rdhtstate();
1320 break;
1321 case 3: // hintp
1322 gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp));
1323 break;
1324 case 5: // htba
1325 gen_op_movl_T0_env(offsetof(CPUSPARCState, htba));
1326 break;
1327 case 6: // hver
1328 gen_op_movl_T0_env(offsetof(CPUSPARCState, hver));
1329 break;
1330 case 31: // hstick_cmpr
1331 gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
1332 break;
1333 default:
1334 goto illegal_insn;
1335 }
1336#endif
e8af50a3
FB		 1337 gen_movl_T0_reg(rd);
1338 break;
3475187d 1339 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
0f8a249a
BS		 1340 if (!supervisor(dc))
1341 goto priv_insn;
3475187d
FB		 1342#ifdef TARGET_SPARC64
1343 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 1344 switch (rs1) {
1345 case 0: // tpc
1346 gen_op_rdtpc();
1347 break;
1348 case 1: // tnpc
1349 gen_op_rdtnpc();
1350 break;
1351 case 2: // tstate
1352 gen_op_rdtstate();
1353 break;
1354 case 3: // tt
1355 gen_op_rdtt();
1356 break;
1357 case 4: // tick
1358 gen_op_rdtick();
1359 break;
1360 case 5: // tba
1361 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1362 break;
1363 case 6: // pstate
1364 gen_op_rdpstate();
1365 break;
1366 case 7: // tl
1367 gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1368 break;
1369 case 8: // pil
1370 gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1371 break;
1372 case 9: // cwp
1373 gen_op_rdcwp();
1374 break;
1375 case 10: // cansave
1376 gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1377 break;
1378 case 11: // canrestore
1379 gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1380 break;
1381 case 12: // cleanwin
1382 gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1383 break;
1384 case 13: // otherwin
1385 gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1386 break;
1387 case 14: // wstate
1388 gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1389 break;
e9ebed4d
BS		 1390 case 16: // UA2005 gl
1391 gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
1392 break;
1393 case 26: // UA2005 strand status
1394 if (!hypervisor(dc))
1395 goto priv_insn;
1396 gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
1397 break;
0f8a249a
BS		 1398 case 31: // ver
1399 gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1400 break;
1401 case 15: // fq
1402 default:
1403 goto illegal_insn;
1404 }
3475187d 1405#else
0f8a249a 1406 gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
3475187d 1407#endif
e8af50a3
FB		 1408 gen_movl_T0_reg(rd);
1409 break;
3475187d
FB		 1410 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1411#ifdef TARGET_SPARC64
0f8a249a 1412 gen_op_flushw();
3475187d 1413#else
0f8a249a
BS		 1414 if (!supervisor(dc))
1415 goto priv_insn;
1416 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
e8af50a3 1417 gen_movl_T0_reg(rd);
3475187d 1418#endif
e8af50a3
FB		 1419 break;
1420#endif
0f8a249a 1421 } else if (xop == 0x34) { /* FPU Operations */
a80dde08
FB		 1422 if (gen_trap_ifnofpu(dc))
1423 goto jmp_insn;
0f8a249a 1424 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 1425 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 1426 rs2 = GET_FIELD(insn, 27, 31);
1427 xop = GET_FIELD(insn, 18, 26);
1428 switch (xop) {
1429 case 0x1: /* fmovs */
1430 gen_op_load_fpr_FT0(rs2);
1431 gen_op_store_FT0_fpr(rd);
1432 break;
1433 case 0x5: /* fnegs */
1434 gen_op_load_fpr_FT1(rs2);
1435 gen_op_fnegs();
1436 gen_op_store_FT0_fpr(rd);
1437 break;
1438 case 0x9: /* fabss */
1439 gen_op_load_fpr_FT1(rs2);
1440 gen_op_fabss();
1441 gen_op_store_FT0_fpr(rd);
1442 break;
1443 case 0x29: /* fsqrts */
1444 gen_op_load_fpr_FT1(rs2);
1445 gen_op_fsqrts();
1446 gen_op_store_FT0_fpr(rd);
1447 break;
1448 case 0x2a: /* fsqrtd */
1449 gen_op_load_fpr_DT1(DFPREG(rs2));
1450 gen_op_fsqrtd();
1451 gen_op_store_DT0_fpr(DFPREG(rd));
1452 break;
1453 case 0x2b: /* fsqrtq */
1454 goto nfpu_insn;
1455 case 0x41:
1456 gen_op_load_fpr_FT0(rs1);
1457 gen_op_load_fpr_FT1(rs2);
1458 gen_op_fadds();
1459 gen_op_store_FT0_fpr(rd);
1460 break;
1461 case 0x42:
1462 gen_op_load_fpr_DT0(DFPREG(rs1));
1463 gen_op_load_fpr_DT1(DFPREG(rs2));
1464 gen_op_faddd();
1465 gen_op_store_DT0_fpr(DFPREG(rd));
1466 break;
1467 case 0x43: /* faddq */
1468 goto nfpu_insn;
1469 case 0x45:
1470 gen_op_load_fpr_FT0(rs1);
1471 gen_op_load_fpr_FT1(rs2);
1472 gen_op_fsubs();
1473 gen_op_store_FT0_fpr(rd);
1474 break;
1475 case 0x46:
1476 gen_op_load_fpr_DT0(DFPREG(rs1));
1477 gen_op_load_fpr_DT1(DFPREG(rs2));
1478 gen_op_fsubd();
1479 gen_op_store_DT0_fpr(DFPREG(rd));
1480 break;
1481 case 0x47: /* fsubq */
1482 goto nfpu_insn;
1483 case 0x49:
1484 gen_op_load_fpr_FT0(rs1);
1485 gen_op_load_fpr_FT1(rs2);
1486 gen_op_fmuls();
1487 gen_op_store_FT0_fpr(rd);
1488 break;
1489 case 0x4a:
1490 gen_op_load_fpr_DT0(DFPREG(rs1));
1491 gen_op_load_fpr_DT1(DFPREG(rs2));
1492 gen_op_fmuld();
1493 gen_op_store_DT0_fpr(rd);
1494 break;
1495 case 0x4b: /* fmulq */
1496 goto nfpu_insn;
1497 case 0x4d:
1498 gen_op_load_fpr_FT0(rs1);
1499 gen_op_load_fpr_FT1(rs2);
1500 gen_op_fdivs();
1501 gen_op_store_FT0_fpr(rd);
1502 break;
1503 case 0x4e:
1504 gen_op_load_fpr_DT0(DFPREG(rs1));
1505 gen_op_load_fpr_DT1(DFPREG(rs2));
1506 gen_op_fdivd();
1507 gen_op_store_DT0_fpr(DFPREG(rd));
1508 break;
1509 case 0x4f: /* fdivq */
1510 goto nfpu_insn;
1511 case 0x69:
1512 gen_op_load_fpr_FT0(rs1);
1513 gen_op_load_fpr_FT1(rs2);
1514 gen_op_fsmuld();
1515 gen_op_store_DT0_fpr(DFPREG(rd));
1516 break;
1517 case 0x6e: /* fdmulq */
1518 goto nfpu_insn;
1519 case 0xc4:
1520 gen_op_load_fpr_FT1(rs2);
1521 gen_op_fitos();
1522 gen_op_store_FT0_fpr(rd);
1523 break;
1524 case 0xc6:
1525 gen_op_load_fpr_DT1(DFPREG(rs2));
1526 gen_op_fdtos();
1527 gen_op_store_FT0_fpr(rd);
1528 break;
1529 case 0xc7: /* fqtos */
1530 goto nfpu_insn;
1531 case 0xc8:
1532 gen_op_load_fpr_FT1(rs2);
1533 gen_op_fitod();
1534 gen_op_store_DT0_fpr(DFPREG(rd));
1535 break;
1536 case 0xc9:
1537 gen_op_load_fpr_FT1(rs2);
1538 gen_op_fstod();
1539 gen_op_store_DT0_fpr(DFPREG(rd));
1540 break;
1541 case 0xcb: /* fqtod */
1542 goto nfpu_insn;
1543 case 0xcc: /* fitoq */
1544 goto nfpu_insn;
1545 case 0xcd: /* fstoq */
1546 goto nfpu_insn;
1547 case 0xce: /* fdtoq */
1548 goto nfpu_insn;
1549 case 0xd1:
1550 gen_op_load_fpr_FT1(rs2);
1551 gen_op_fstoi();
1552 gen_op_store_FT0_fpr(rd);
1553 break;
1554 case 0xd2:
1555 gen_op_load_fpr_DT1(rs2);
1556 gen_op_fdtoi();
1557 gen_op_store_FT0_fpr(rd);
1558 break;
1559 case 0xd3: /* fqtoi */
1560 goto nfpu_insn;
3475187d 1561#ifdef TARGET_SPARC64
0f8a249a
BS		 1562 case 0x2: /* V9 fmovd */
1563 gen_op_load_fpr_DT0(DFPREG(rs2));
1564 gen_op_store_DT0_fpr(DFPREG(rd));
1565 break;
1566 case 0x6: /* V9 fnegd */
1567 gen_op_load_fpr_DT1(DFPREG(rs2));
1568 gen_op_fnegd();
1569 gen_op_store_DT0_fpr(DFPREG(rd));
1570 break;
1571 case 0xa: /* V9 fabsd */
1572 gen_op_load_fpr_DT1(DFPREG(rs2));
1573 gen_op_fabsd();
1574 gen_op_store_DT0_fpr(DFPREG(rd));
1575 break;
1576 case 0x81: /* V9 fstox */
1577 gen_op_load_fpr_FT1(rs2);
1578 gen_op_fstox();
1579 gen_op_store_DT0_fpr(DFPREG(rd));
1580 break;
1581 case 0x82: /* V9 fdtox */
1582 gen_op_load_fpr_DT1(DFPREG(rs2));
1583 gen_op_fdtox();
1584 gen_op_store_DT0_fpr(DFPREG(rd));
1585 break;
1586 case 0x84: /* V9 fxtos */
1587 gen_op_load_fpr_DT1(DFPREG(rs2));
1588 gen_op_fxtos();
1589 gen_op_store_FT0_fpr(rd);
1590 break;
1591 case 0x88: /* V9 fxtod */
1592 gen_op_load_fpr_DT1(DFPREG(rs2));
1593 gen_op_fxtod();
1594 gen_op_store_DT0_fpr(DFPREG(rd));
1595 break;
1596 case 0x3: /* V9 fmovq */
1597 case 0x7: /* V9 fnegq */
1598 case 0xb: /* V9 fabsq */
1599 case 0x83: /* V9 fqtox */
1600 case 0x8c: /* V9 fxtoq */
1601 goto nfpu_insn;
1602#endif
1603 default:
1604 goto illegal_insn;
1605 }
1606 } else if (xop == 0x35) { /* FPU Operations */
3475187d 1607#ifdef TARGET_SPARC64
0f8a249a 1608 int cond;
3475187d 1609#endif
a80dde08
FB		 1610 if (gen_trap_ifnofpu(dc))
1611 goto jmp_insn;
0f8a249a 1612 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 1613 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 1614 rs2 = GET_FIELD(insn, 27, 31);
1615 xop = GET_FIELD(insn, 18, 26);
3475187d 1616#ifdef TARGET_SPARC64
0f8a249a
BS		 1617 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
1618 cond = GET_FIELD_SP(insn, 14, 17);
1619 gen_op_load_fpr_FT0(rd);
1620 gen_op_load_fpr_FT1(rs2);
1621 rs1 = GET_FIELD(insn, 13, 17);
1622 gen_movl_reg_T0(rs1);
1623 flush_T2(dc);
1624 gen_cond_reg(cond);
1625 gen_op_fmovs_cc();
1626 gen_op_store_FT0_fpr(rd);
1627 break;
1628 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
1629 cond = GET_FIELD_SP(insn, 14, 17);
1630 gen_op_load_fpr_DT0(rd);
1631 gen_op_load_fpr_DT1(rs2);
1632 flush_T2(dc);
1633 rs1 = GET_FIELD(insn, 13, 17);
1634 gen_movl_reg_T0(rs1);
1635 gen_cond_reg(cond);
1636 gen_op_fmovs_cc();
1637 gen_op_store_DT0_fpr(rd);
1638 break;
1639 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1640 goto nfpu_insn;
1641 }
1642#endif
1643 switch (xop) {
3475187d 1644#ifdef TARGET_SPARC64
0f8a249a
BS		 1645 case 0x001: /* V9 fmovscc %fcc0 */
1646 cond = GET_FIELD_SP(insn, 14, 17);
1647 gen_op_load_fpr_FT0(rd);
1648 gen_op_load_fpr_FT1(rs2);
1649 flush_T2(dc);
1650 gen_fcond[0][cond]();
1651 gen_op_fmovs_cc();
1652 gen_op_store_FT0_fpr(rd);
1653 break;
1654 case 0x002: /* V9 fmovdcc %fcc0 */
1655 cond = GET_FIELD_SP(insn, 14, 17);
1656 gen_op_load_fpr_DT0(rd);
1657 gen_op_load_fpr_DT1(rs2);
1658 flush_T2(dc);
1659 gen_fcond[0][cond]();
1660 gen_op_fmovd_cc();
1661 gen_op_store_DT0_fpr(rd);
1662 break;
1663 case 0x003: /* V9 fmovqcc %fcc0 */
1664 goto nfpu_insn;
1665 case 0x041: /* V9 fmovscc %fcc1 */
1666 cond = GET_FIELD_SP(insn, 14, 17);
1667 gen_op_load_fpr_FT0(rd);
1668 gen_op_load_fpr_FT1(rs2);
1669 flush_T2(dc);
1670 gen_fcond[1][cond]();
1671 gen_op_fmovs_cc();
1672 gen_op_store_FT0_fpr(rd);
1673 break;
1674 case 0x042: /* V9 fmovdcc %fcc1 */
1675 cond = GET_FIELD_SP(insn, 14, 17);
1676 gen_op_load_fpr_DT0(rd);
1677 gen_op_load_fpr_DT1(rs2);
1678 flush_T2(dc);
1679 gen_fcond[1][cond]();
1680 gen_op_fmovd_cc();
1681 gen_op_store_DT0_fpr(rd);
1682 break;
1683 case 0x043: /* V9 fmovqcc %fcc1 */
1684 goto nfpu_insn;
1685 case 0x081: /* V9 fmovscc %fcc2 */
1686 cond = GET_FIELD_SP(insn, 14, 17);
1687 gen_op_load_fpr_FT0(rd);
1688 gen_op_load_fpr_FT1(rs2);
1689 flush_T2(dc);
1690 gen_fcond[2][cond]();
1691 gen_op_fmovs_cc();
1692 gen_op_store_FT0_fpr(rd);
1693 break;
1694 case 0x082: /* V9 fmovdcc %fcc2 */
1695 cond = GET_FIELD_SP(insn, 14, 17);
1696 gen_op_load_fpr_DT0(rd);
1697 gen_op_load_fpr_DT1(rs2);
1698 flush_T2(dc);
1699 gen_fcond[2][cond]();
1700 gen_op_fmovd_cc();
1701 gen_op_store_DT0_fpr(rd);
1702 break;
1703 case 0x083: /* V9 fmovqcc %fcc2 */
1704 goto nfpu_insn;
1705 case 0x0c1: /* V9 fmovscc %fcc3 */
1706 cond = GET_FIELD_SP(insn, 14, 17);
1707 gen_op_load_fpr_FT0(rd);
1708 gen_op_load_fpr_FT1(rs2);
1709 flush_T2(dc);
1710 gen_fcond[3][cond]();
1711 gen_op_fmovs_cc();
1712 gen_op_store_FT0_fpr(rd);
1713 break;
1714 case 0x0c2: /* V9 fmovdcc %fcc3 */
1715 cond = GET_FIELD_SP(insn, 14, 17);
1716 gen_op_load_fpr_DT0(rd);
1717 gen_op_load_fpr_DT1(rs2);
1718 flush_T2(dc);
1719 gen_fcond[3][cond]();
1720 gen_op_fmovd_cc();
1721 gen_op_store_DT0_fpr(rd);
1722 break;
1723 case 0x0c3: /* V9 fmovqcc %fcc3 */
1724 goto nfpu_insn;
1725 case 0x101: /* V9 fmovscc %icc */
1726 cond = GET_FIELD_SP(insn, 14, 17);
1727 gen_op_load_fpr_FT0(rd);
1728 gen_op_load_fpr_FT1(rs2);
1729 flush_T2(dc);
1730 gen_cond[0][cond]();
1731 gen_op_fmovs_cc();
1732 gen_op_store_FT0_fpr(rd);
1733 break;
1734 case 0x102: /* V9 fmovdcc %icc */
1735 cond = GET_FIELD_SP(insn, 14, 17);
1736 gen_op_load_fpr_DT0(rd);
1737 gen_op_load_fpr_DT1(rs2);
1738 flush_T2(dc);
1739 gen_cond[0][cond]();
1740 gen_op_fmovd_cc();
1741 gen_op_store_DT0_fpr(rd);
1742 break;
1743 case 0x103: /* V9 fmovqcc %icc */
1744 goto nfpu_insn;
1745 case 0x181: /* V9 fmovscc %xcc */
1746 cond = GET_FIELD_SP(insn, 14, 17);
1747 gen_op_load_fpr_FT0(rd);
1748 gen_op_load_fpr_FT1(rs2);
1749 flush_T2(dc);
1750 gen_cond[1][cond]();
1751 gen_op_fmovs_cc();
1752 gen_op_store_FT0_fpr(rd);
1753 break;
1754 case 0x182: /* V9 fmovdcc %xcc */
1755 cond = GET_FIELD_SP(insn, 14, 17);
1756 gen_op_load_fpr_DT0(rd);
1757 gen_op_load_fpr_DT1(rs2);
1758 flush_T2(dc);
1759 gen_cond[1][cond]();
1760 gen_op_fmovd_cc();
1761 gen_op_store_DT0_fpr(rd);
1762 break;
1763 case 0x183: /* V9 fmovqcc %xcc */
1764 goto nfpu_insn;
1765#endif
1766 case 0x51: /* V9 %fcc */
1767 gen_op_load_fpr_FT0(rs1);
1768 gen_op_load_fpr_FT1(rs2);
3475187d 1769#ifdef TARGET_SPARC64
0f8a249a 1770 gen_fcmps[rd & 3]();
3475187d 1771#else
0f8a249a 1772 gen_op_fcmps();
3475187d 1773#endif
0f8a249a
BS		 1774 break;
1775 case 0x52: /* V9 %fcc */
1776 gen_op_load_fpr_DT0(DFPREG(rs1));
1777 gen_op_load_fpr_DT1(DFPREG(rs2));
3475187d 1778#ifdef TARGET_SPARC64
0f8a249a 1779 gen_fcmpd[rd & 3]();
3475187d 1780#else
0f8a249a
BS		 1781 gen_op_fcmpd();
1782#endif
1783 break;
1784 case 0x53: /* fcmpq */
1785 goto nfpu_insn;
1786 case 0x55: /* fcmpes, V9 %fcc */
1787 gen_op_load_fpr_FT0(rs1);
1788 gen_op_load_fpr_FT1(rs2);
3475187d 1789#ifdef TARGET_SPARC64
0f8a249a 1790 gen_fcmpes[rd & 3]();
3475187d 1791#else
0f8a249a 1792 gen_op_fcmpes();
3475187d 1793#endif
0f8a249a
BS		 1794 break;
1795 case 0x56: /* fcmped, V9 %fcc */
1796 gen_op_load_fpr_DT0(DFPREG(rs1));
1797 gen_op_load_fpr_DT1(DFPREG(rs2));
3475187d 1798#ifdef TARGET_SPARC64
0f8a249a 1799 gen_fcmped[rd & 3]();
3475187d 1800#else
0f8a249a
BS		 1801 gen_op_fcmped();
1802#endif
1803 break;
1804 case 0x57: /* fcmpeq */
1805 goto nfpu_insn;
1806 default:
1807 goto illegal_insn;
1808 }
e80cfcfc 1809#if defined(OPTIM)
0f8a249a
BS		 1810 } else if (xop == 0x2) {
1811 // clr/mov shortcut
e80cfcfc
FB		 1812
1813 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 1814 if (rs1 == 0) {
1815 // or %g0, x, y -> mov T1, x; mov y, T1
1816 if (IS_IMM) { /* immediate */
1817 rs2 = GET_FIELDs(insn, 19, 31);
1818 gen_movl_simm_T1(rs2);
1819 } else { /* register */
1820 rs2 = GET_FIELD(insn, 27, 31);
1821 gen_movl_reg_T1(rs2);
1822 }
1823 gen_movl_T1_reg(rd);
1824 } else {
1825 gen_movl_reg_T0(rs1);
1826 if (IS_IMM) { /* immediate */
1827 // or x, #0, y -> mov T1, x; mov y, T1
1828 rs2 = GET_FIELDs(insn, 19, 31);
1829 if (rs2 != 0) {
1830 gen_movl_simm_T1(rs2);
1831 gen_op_or_T1_T0();
1832 }
1833 } else { /* register */
1834 // or x, %g0, y -> mov T1, x; mov y, T1
1835 rs2 = GET_FIELD(insn, 27, 31);
1836 if (rs2 != 0) {
1837 gen_movl_reg_T1(rs2);
1838 gen_op_or_T1_T0();
1839 }
1840 }
1841 gen_movl_T0_reg(rd);
1842 }
83469015
FB		 1843#endif
1844#ifdef TARGET_SPARC64
0f8a249a 1845 } else if (xop == 0x25) { /* sll, V9 sllx */
83469015 1846 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 1847 gen_movl_reg_T0(rs1);
1848 if (IS_IMM) { /* immediate */
83469015
FB		 1849 rs2 = GET_FIELDs(insn, 20, 31);
1850 gen_movl_simm_T1(rs2);
0f8a249a 1851 } else { /* register */
83469015
FB		 1852 rs2 = GET_FIELD(insn, 27, 31);
1853 gen_movl_reg_T1(rs2);
1854 }
0f8a249a
BS		 1855 if (insn & (1 << 12))
1856 gen_op_sllx();
1857 else
1858 gen_op_sll();
1859 gen_movl_T0_reg(rd);
1860 } else if (xop == 0x26) { /* srl, V9 srlx */
83469015 1861 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 1862 gen_movl_reg_T0(rs1);
1863 if (IS_IMM) { /* immediate */
83469015
FB		 1864 rs2 = GET_FIELDs(insn, 20, 31);
1865 gen_movl_simm_T1(rs2);
0f8a249a 1866 } else { /* register */
83469015
FB		 1867 rs2 = GET_FIELD(insn, 27, 31);
1868 gen_movl_reg_T1(rs2);
1869 }
0f8a249a
BS		 1870 if (insn & (1 << 12))
1871 gen_op_srlx();
1872 else
1873 gen_op_srl();
1874 gen_movl_T0_reg(rd);
1875 } else if (xop == 0x27) { /* sra, V9 srax */
83469015 1876 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 1877 gen_movl_reg_T0(rs1);
1878 if (IS_IMM) { /* immediate */
83469015
FB		 1879 rs2 = GET_FIELDs(insn, 20, 31);
1880 gen_movl_simm_T1(rs2);
0f8a249a 1881 } else { /* register */
83469015
FB		 1882 rs2 = GET_FIELD(insn, 27, 31);
1883 gen_movl_reg_T1(rs2);
1884 }
0f8a249a
BS		 1885 if (insn & (1 << 12))
1886 gen_op_srax();
1887 else
1888 gen_op_sra();
1889 gen_movl_T0_reg(rd);
e80cfcfc 1890#endif
fcc72045 1891 } else if (xop < 0x36) {
e80cfcfc 1892 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 1893 gen_movl_reg_T0(rs1);
1894 if (IS_IMM) { /* immediate */
cf495bcf 1895 rs2 = GET_FIELDs(insn, 19, 31);
3475187d 1896 gen_movl_simm_T1(rs2);
0f8a249a 1897 } else { /* register */
cf495bcf
FB		 1898 rs2 = GET_FIELD(insn, 27, 31);
1899 gen_movl_reg_T1(rs2);
1900 }
1901 if (xop < 0x20) {
1902 switch (xop & ~0x10) {
1903 case 0x0:
1904 if (xop & 0x10)
1905 gen_op_add_T1_T0_cc();
1906 else
1907 gen_op_add_T1_T0();
1908 break;
1909 case 0x1:
1910 gen_op_and_T1_T0();
1911 if (xop & 0x10)
1912 gen_op_logic_T0_cc();
1913 break;
1914 case 0x2:
0f8a249a
BS		 1915 gen_op_or_T1_T0();
1916 if (xop & 0x10)
1917 gen_op_logic_T0_cc();
1918 break;
cf495bcf
FB		 1919 case 0x3:
1920 gen_op_xor_T1_T0();
1921 if (xop & 0x10)
1922 gen_op_logic_T0_cc();
1923 break;
1924 case 0x4:
1925 if (xop & 0x10)
1926 gen_op_sub_T1_T0_cc();
1927 else
1928 gen_op_sub_T1_T0();
1929 break;
1930 case 0x5:
1931 gen_op_andn_T1_T0();
1932 if (xop & 0x10)
1933 gen_op_logic_T0_cc();
1934 break;
1935 case 0x6:
1936 gen_op_orn_T1_T0();
1937 if (xop & 0x10)
1938 gen_op_logic_T0_cc();
1939 break;
1940 case 0x7:
1941 gen_op_xnor_T1_T0();
1942 if (xop & 0x10)
1943 gen_op_logic_T0_cc();
1944 break;
1945 case 0x8:
cf495bcf 1946 if (xop & 0x10)
af7bf89b
FB		 1947 gen_op_addx_T1_T0_cc();
1948 else
1949 gen_op_addx_T1_T0();
cf495bcf 1950 break;
ded3ab80 1951#ifdef TARGET_SPARC64
0f8a249a 1952 case 0x9: /* V9 mulx */
ded3ab80
PB		 1953 gen_op_mulx_T1_T0();
1954 break;
1955#endif
cf495bcf
FB		 1956 case 0xa:
1957 gen_op_umul_T1_T0();
1958 if (xop & 0x10)
1959 gen_op_logic_T0_cc();
1960 break;
1961 case 0xb:
1962 gen_op_smul_T1_T0();
1963 if (xop & 0x10)
1964 gen_op_logic_T0_cc();
1965 break;
1966 case 0xc:
cf495bcf 1967 if (xop & 0x10)
af7bf89b
FB		 1968 gen_op_subx_T1_T0_cc();
1969 else
1970 gen_op_subx_T1_T0();
cf495bcf 1971 break;
ded3ab80 1972#ifdef TARGET_SPARC64
0f8a249a 1973 case 0xd: /* V9 udivx */
ded3ab80
PB		 1974 gen_op_udivx_T1_T0();
1975 break;
1976#endif
cf495bcf
FB		 1977 case 0xe:
1978 gen_op_udiv_T1_T0();
1979 if (xop & 0x10)
1980 gen_op_div_cc();
1981 break;
1982 case 0xf:
1983 gen_op_sdiv_T1_T0();
1984 if (xop & 0x10)
1985 gen_op_div_cc();
1986 break;
1987 default:
1988 goto illegal_insn;
1989 }
0f8a249a 1990 gen_movl_T0_reg(rd);
cf495bcf
FB		 1991 } else {
1992 switch (xop) {
0f8a249a
BS		 1993 case 0x20: /* taddcc */
1994 gen_op_tadd_T1_T0_cc();
1995 gen_movl_T0_reg(rd);
1996 break;
1997 case 0x21: /* tsubcc */
1998 gen_op_tsub_T1_T0_cc();
1999 gen_movl_T0_reg(rd);
2000 break;
2001 case 0x22: /* taddcctv */
2002 gen_op_tadd_T1_T0_ccTV();
2003 gen_movl_T0_reg(rd);
2004 break;
2005 case 0x23: /* tsubcctv */
2006 gen_op_tsub_T1_T0_ccTV();
2007 gen_movl_T0_reg(rd);
2008 break;
cf495bcf
FB		 2009 case 0x24: /* mulscc */
2010 gen_op_mulscc_T1_T0();
2011 gen_movl_T0_reg(rd);
2012 break;
83469015 2013#ifndef TARGET_SPARC64
0f8a249a
BS		 2014 case 0x25: /* sll */
2015 gen_op_sll();
cf495bcf
FB		 2016 gen_movl_T0_reg(rd);
2017 break;
83469015 2018 case 0x26: /* srl */
0f8a249a 2019 gen_op_srl();
cf495bcf
FB		 2020 gen_movl_T0_reg(rd);
2021 break;
83469015 2022 case 0x27: /* sra */
0f8a249a 2023 gen_op_sra();
cf495bcf
FB		 2024 gen_movl_T0_reg(rd);
2025 break;
83469015 2026#endif
cf495bcf
FB		 2027 case 0x30:
2028 {
cf495bcf 2029 switch(rd) {
3475187d 2030 case 0: /* wry */
0f8a249a
BS		 2031 gen_op_xor_T1_T0();
2032 gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
cf495bcf 2033 break;
65fe7b09
BS		 2034#ifndef TARGET_SPARC64
2035 case 0x01 ... 0x0f: /* undefined in the
2036 SPARCv8 manual, nop
2037 on the microSPARC
2038 II */
2039 case 0x10 ... 0x1f: /* implementation-dependent
2040 in the SPARCv8
2041 manual, nop on the
2042 microSPARC II */
2043 break;
2044#else
0f8a249a 2045 case 0x2: /* V9 wrccr */
3475187d 2046 gen_op_wrccr();
0f8a249a
BS		 2047 break;
2048 case 0x3: /* V9 wrasi */
2049 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
2050 break;
2051 case 0x6: /* V9 wrfprs */
2052 gen_op_xor_T1_T0();
2053 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
3299908c
BS		 2054 save_state(dc);
2055 gen_op_next_insn();
2056 gen_op_movl_T0_0();
2057 gen_op_exit_tb();
2058 dc->is_br = 1;
0f8a249a
BS		 2059 break;
2060 case 0xf: /* V9 sir, nop if user */
3475187d 2061#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 2062 if (supervisor(dc))
2063 gen_op_sir();
3475187d 2064#endif
0f8a249a
BS		 2065 break;
2066 case 0x13: /* Graphics Status */
725cb90b
FB		 2067 if (gen_trap_ifnofpu(dc))
2068 goto jmp_insn;
0f8a249a
BS		 2069 gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
2070 break;
2071 case 0x17: /* Tick compare */
83469015 2072#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 2073 if (!supervisor(dc))
2074 goto illegal_insn;
83469015 2075#endif
20c9f095
BS		 2076 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
2077 gen_op_wrtick_cmpr();
0f8a249a
BS		 2078 break;
2079 case 0x18: /* System tick */
83469015 2080#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 2081 if (!supervisor(dc))
2082 goto illegal_insn;
83469015 2083#endif
20c9f095 2084 gen_op_wrstick();
0f8a249a
BS		 2085 break;
2086 case 0x19: /* System tick compare */
83469015 2087#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 2088 if (!supervisor(dc))
2089 goto illegal_insn;
3475187d 2090#endif
20c9f095
BS		 2091 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
2092 gen_op_wrstick_cmpr();
0f8a249a 2093 break;
83469015 2094
0f8a249a
BS		 2095 case 0x10: /* Performance Control */
2096 case 0x11: /* Performance Instrumentation Counter */
2097 case 0x12: /* Dispatch Control */
2098 case 0x14: /* Softint set */
2099 case 0x15: /* Softint clear */
2100 case 0x16: /* Softint write */
83469015 2101#endif
3475187d 2102 default:
cf495bcf
FB		 2103 goto illegal_insn;
2104 }
2105 }
2106 break;
e8af50a3 2107#if !defined(CONFIG_USER_ONLY)
af7bf89b 2108 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3 2109 {
0f8a249a
BS		 2110 if (!supervisor(dc))
2111 goto priv_insn;
3475187d 2112#ifdef TARGET_SPARC64
0f8a249a
BS		 2113 switch (rd) {
2114 case 0:
2115 gen_op_saved();
2116 break;
2117 case 1:
2118 gen_op_restored();
2119 break;
e9ebed4d
BS		 2120 case 2: /* UA2005 allclean */
2121 case 3: /* UA2005 otherw */
2122 case 4: /* UA2005 normalw */
2123 case 5: /* UA2005 invalw */
2124 // XXX
0f8a249a 2125 default:
3475187d
FB		 2126 goto illegal_insn;
2127 }
2128#else
e8af50a3
FB		 2129 gen_op_xor_T1_T0();
2130 gen_op_wrpsr();
9e61bde5
FB		 2131 save_state(dc);
2132 gen_op_next_insn();
0f8a249a
BS		 2133 gen_op_movl_T0_0();
2134 gen_op_exit_tb();
2135 dc->is_br = 1;
3475187d 2136#endif
e8af50a3
FB		 2137 }
2138 break;
af7bf89b 2139 case 0x32: /* wrwim, V9 wrpr */
e8af50a3 2140 {
0f8a249a
BS		 2141 if (!supervisor(dc))
2142 goto priv_insn;
e8af50a3 2143 gen_op_xor_T1_T0();
3475187d 2144#ifdef TARGET_SPARC64
0f8a249a
BS		 2145 switch (rd) {
2146 case 0: // tpc
2147 gen_op_wrtpc();
2148 break;
2149 case 1: // tnpc
2150 gen_op_wrtnpc();
2151 break;
2152 case 2: // tstate
2153 gen_op_wrtstate();
2154 break;
2155 case 3: // tt
2156 gen_op_wrtt();
2157 break;
2158 case 4: // tick
2159 gen_op_wrtick();
2160 break;
2161 case 5: // tba
2162 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2163 break;
2164 case 6: // pstate
2165 gen_op_wrpstate();
ded3ab80
PB		 2166 save_state(dc);
2167 gen_op_next_insn();
2168 gen_op_movl_T0_0();
2169 gen_op_exit_tb();
2170 dc->is_br = 1;
0f8a249a
BS		 2171 break;
2172 case 7: // tl
2173 gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
2174 break;
2175 case 8: // pil
2176 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
2177 break;
2178 case 9: // cwp
2179 gen_op_wrcwp();
2180 break;
2181 case 10: // cansave
2182 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
2183 break;
2184 case 11: // canrestore
2185 gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
2186 break;
2187 case 12: // cleanwin
2188 gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
2189 break;
2190 case 13: // otherwin
2191 gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
2192 break;
2193 case 14: // wstate
2194 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
2195 break;
e9ebed4d
BS		 2196 case 16: // UA2005 gl
2197 gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
2198 break;
2199 case 26: // UA2005 strand status
2200 if (!hypervisor(dc))
2201 goto priv_insn;
2202 gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
2203 break;
0f8a249a
BS		 2204 default:
2205 goto illegal_insn;
2206 }
3475187d 2207#else
0f8a249a 2208 gen_op_wrwim();
3475187d 2209#endif
e8af50a3
FB		 2210 }
2211 break;
e9ebed4d 2212 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 2213 {
e9ebed4d 2214#ifndef TARGET_SPARC64
0f8a249a
BS		 2215 if (!supervisor(dc))
2216 goto priv_insn;
e8af50a3 2217 gen_op_xor_T1_T0();
e9ebed4d
BS		 2218 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2219#else
2220 if (!hypervisor(dc))
2221 goto priv_insn;
2222 gen_op_xor_T1_T0();
2223 switch (rd) {
2224 case 0: // hpstate
2225 // XXX gen_op_wrhpstate();
2226 save_state(dc);
2227 gen_op_next_insn();
2228 gen_op_movl_T0_0();
2229 gen_op_exit_tb();
2230 dc->is_br = 1;
2231 break;
2232 case 1: // htstate
2233 // XXX gen_op_wrhtstate();
2234 break;
2235 case 3: // hintp
2236 gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp));
2237 break;
2238 case 5: // htba
2239 gen_op_movl_env_T0(offsetof(CPUSPARCState, htba));
2240 break;
2241 case 31: // hstick_cmpr
20c9f095
BS		 2242 gen_op_movtl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
2243 gen_op_wrhstick_cmpr();
e9ebed4d
BS		 2244 break;
2245 case 6: // hver readonly
2246 default:
2247 goto illegal_insn;
2248 }
2249#endif
e8af50a3
FB		 2250 }
2251 break;
2252#endif
3475187d 2253#ifdef TARGET_SPARC64
0f8a249a
BS		 2254 case 0x2c: /* V9 movcc */
2255 {
2256 int cc = GET_FIELD_SP(insn, 11, 12);
2257 int cond = GET_FIELD_SP(insn, 14, 17);
2258 if (IS_IMM) { /* immediate */
2259 rs2 = GET_FIELD_SPs(insn, 0, 10);
2260 gen_movl_simm_T1(rs2);
2261 }
2262 else {
2263 rs2 = GET_FIELD_SP(insn, 0, 4);
2264 gen_movl_reg_T1(rs2);
2265 }
2266 gen_movl_reg_T0(rd);
2267 flush_T2(dc);
2268 if (insn & (1 << 18)) {
2269 if (cc == 0)
2270 gen_cond[0][cond]();
2271 else if (cc == 2)
2272 gen_cond[1][cond]();
2273 else
2274 goto illegal_insn;
2275 } else {
2276 gen_fcond[cc][cond]();
2277 }
2278 gen_op_mov_cc();
2279 gen_movl_T0_reg(rd);
2280 break;
2281 }
2282 case 0x2d: /* V9 sdivx */
3475187d 2283 gen_op_sdivx_T1_T0();
0f8a249a
BS		 2284 gen_movl_T0_reg(rd);
2285 break;
2286 case 0x2e: /* V9 popc */
2287 {
2288 if (IS_IMM) { /* immediate */
2289 rs2 = GET_FIELD_SPs(insn, 0, 12);
2290 gen_movl_simm_T1(rs2);
2291 // XXX optimize: popc(constant)
2292 }
2293 else {
2294 rs2 = GET_FIELD_SP(insn, 0, 4);
2295 gen_movl_reg_T1(rs2);
2296 }
2297 gen_op_popc();
2298 gen_movl_T0_reg(rd);
2299 }
2300 case 0x2f: /* V9 movr */
2301 {
2302 int cond = GET_FIELD_SP(insn, 10, 12);
2303 rs1 = GET_FIELD(insn, 13, 17);
2304 flush_T2(dc);
2305 gen_movl_reg_T0(rs1);
2306 gen_cond_reg(cond);
2307 if (IS_IMM) { /* immediate */
2308 rs2 = GET_FIELD_SPs(insn, 0, 9);
2309 gen_movl_simm_T1(rs2);
2310 }
2311 else {
2312 rs2 = GET_FIELD_SP(insn, 0, 4);
2313 gen_movl_reg_T1(rs2);
2314 }
2315 gen_movl_reg_T0(rd);
2316 gen_op_mov_cc();
2317 gen_movl_T0_reg(rd);
2318 break;
2319 }
2320#endif
2321 default:
2322 goto illegal_insn;
2323 }
2324 }
3299908c
BS		 2325 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
2326#ifdef TARGET_SPARC64
2327 int opf = GET_FIELD_SP(insn, 5, 13);
2328 rs1 = GET_FIELD(insn, 13, 17);
2329 rs2 = GET_FIELD(insn, 27, 31);
e9ebed4d
BS		 2330 if (gen_trap_ifnofpu(dc))
2331 goto jmp_insn;
3299908c
BS		 2332
2333 switch (opf) {
e9ebed4d
BS		 2334 case 0x000: /* VIS I edge8cc */
2335 case 0x001: /* VIS II edge8n */
2336 case 0x002: /* VIS I edge8lcc */
2337 case 0x003: /* VIS II edge8ln */
2338 case 0x004: /* VIS I edge16cc */
2339 case 0x005: /* VIS II edge16n */
2340 case 0x006: /* VIS I edge16lcc */
2341 case 0x007: /* VIS II edge16ln */
2342 case 0x008: /* VIS I edge32cc */
2343 case 0x009: /* VIS II edge32n */
2344 case 0x00a: /* VIS I edge32lcc */
2345 case 0x00b: /* VIS II edge32ln */
2346 // XXX
2347 goto illegal_insn;
2348 case 0x010: /* VIS I array8 */
2349 gen_movl_reg_T0(rs1);
2350 gen_movl_reg_T1(rs2);
2351 gen_op_array8();
2352 gen_movl_T0_reg(rd);
2353 break;
2354 case 0x012: /* VIS I array16 */
2355 gen_movl_reg_T0(rs1);
2356 gen_movl_reg_T1(rs2);
2357 gen_op_array16();
2358 gen_movl_T0_reg(rd);
2359 break;
2360 case 0x014: /* VIS I array32 */
2361 gen_movl_reg_T0(rs1);
2362 gen_movl_reg_T1(rs2);
2363 gen_op_array32();
2364 gen_movl_T0_reg(rd);
2365 break;
3299908c 2366 case 0x018: /* VIS I alignaddr */
3299908c
BS		 2367 gen_movl_reg_T0(rs1);
2368 gen_movl_reg_T1(rs2);
2369 gen_op_alignaddr();
2370 gen_movl_T0_reg(rd);
2371 break;
e9ebed4d 2372 case 0x019: /* VIS II bmask */
3299908c 2373 case 0x01a: /* VIS I alignaddrl */
3299908c 2374 // XXX
e9ebed4d
BS		 2375 goto illegal_insn;
2376 case 0x020: /* VIS I fcmple16 */
2377 gen_op_load_fpr_DT0(rs1);
2378 gen_op_load_fpr_DT1(rs2);
2379 gen_op_fcmple16();
2380 gen_op_store_DT0_fpr(rd);
2381 break;
2382 case 0x022: /* VIS I fcmpne16 */
2383 gen_op_load_fpr_DT0(rs1);
2384 gen_op_load_fpr_DT1(rs2);
2385 gen_op_fcmpne16();
2386 gen_op_store_DT0_fpr(rd);
3299908c 2387 break;
e9ebed4d
BS		 2388 case 0x024: /* VIS I fcmple32 */
2389 gen_op_load_fpr_DT0(rs1);
2390 gen_op_load_fpr_DT1(rs2);
2391 gen_op_fcmple32();
2392 gen_op_store_DT0_fpr(rd);
2393 break;
2394 case 0x026: /* VIS I fcmpne32 */
2395 gen_op_load_fpr_DT0(rs1);
2396 gen_op_load_fpr_DT1(rs2);
2397 gen_op_fcmpne32();
2398 gen_op_store_DT0_fpr(rd);
2399 break;
2400 case 0x028: /* VIS I fcmpgt16 */
2401 gen_op_load_fpr_DT0(rs1);
2402 gen_op_load_fpr_DT1(rs2);
2403 gen_op_fcmpgt16();
2404 gen_op_store_DT0_fpr(rd);
2405 break;
2406 case 0x02a: /* VIS I fcmpeq16 */
2407 gen_op_load_fpr_DT0(rs1);
2408 gen_op_load_fpr_DT1(rs2);
2409 gen_op_fcmpeq16();
2410 gen_op_store_DT0_fpr(rd);
2411 break;
2412 case 0x02c: /* VIS I fcmpgt32 */
2413 gen_op_load_fpr_DT0(rs1);
2414 gen_op_load_fpr_DT1(rs2);
2415 gen_op_fcmpgt32();
2416 gen_op_store_DT0_fpr(rd);
2417 break;
2418 case 0x02e: /* VIS I fcmpeq32 */
2419 gen_op_load_fpr_DT0(rs1);
2420 gen_op_load_fpr_DT1(rs2);
2421 gen_op_fcmpeq32();
2422 gen_op_store_DT0_fpr(rd);
2423 break;
2424 case 0x031: /* VIS I fmul8x16 */
2425 gen_op_load_fpr_DT0(rs1);
2426 gen_op_load_fpr_DT1(rs2);
2427 gen_op_fmul8x16();
2428 gen_op_store_DT0_fpr(rd);
2429 break;
2430 case 0x033: /* VIS I fmul8x16au */
2431 gen_op_load_fpr_DT0(rs1);
2432 gen_op_load_fpr_DT1(rs2);
2433 gen_op_fmul8x16au();
2434 gen_op_store_DT0_fpr(rd);
2435 break;
2436 case 0x035: /* VIS I fmul8x16al */
2437 gen_op_load_fpr_DT0(rs1);
2438 gen_op_load_fpr_DT1(rs2);
2439 gen_op_fmul8x16al();
2440 gen_op_store_DT0_fpr(rd);
2441 break;
2442 case 0x036: /* VIS I fmul8sux16 */
2443 gen_op_load_fpr_DT0(rs1);
2444 gen_op_load_fpr_DT1(rs2);
2445 gen_op_fmul8sux16();
2446 gen_op_store_DT0_fpr(rd);
2447 break;
2448 case 0x037: /* VIS I fmul8ulx16 */
2449 gen_op_load_fpr_DT0(rs1);
2450 gen_op_load_fpr_DT1(rs2);
2451 gen_op_fmul8ulx16();
2452 gen_op_store_DT0_fpr(rd);
2453 break;
2454 case 0x038: /* VIS I fmuld8sux16 */
2455 gen_op_load_fpr_DT0(rs1);
2456 gen_op_load_fpr_DT1(rs2);
2457 gen_op_fmuld8sux16();
2458 gen_op_store_DT0_fpr(rd);
2459 break;
2460 case 0x039: /* VIS I fmuld8ulx16 */
2461 gen_op_load_fpr_DT0(rs1);
2462 gen_op_load_fpr_DT1(rs2);
2463 gen_op_fmuld8ulx16();
2464 gen_op_store_DT0_fpr(rd);
2465 break;
2466 case 0x03a: /* VIS I fpack32 */
2467 case 0x03b: /* VIS I fpack16 */
2468 case 0x03d: /* VIS I fpackfix */
2469 case 0x03e: /* VIS I pdist */
2470 // XXX
2471 goto illegal_insn;
3299908c 2472 case 0x048: /* VIS I faligndata */
3299908c
BS		 2473 gen_op_load_fpr_DT0(rs1);
2474 gen_op_load_fpr_DT1(rs2);
2475 gen_op_faligndata();
2476 gen_op_store_DT0_fpr(rd);
2477 break;
e9ebed4d
BS		 2478 case 0x04b: /* VIS I fpmerge */
2479 gen_op_load_fpr_DT0(rs1);
2480 gen_op_load_fpr_DT1(rs2);
2481 gen_op_fpmerge();
2482 gen_op_store_DT0_fpr(rd);
2483 break;
2484 case 0x04c: /* VIS II bshuffle */
2485 // XXX
2486 goto illegal_insn;
2487 case 0x04d: /* VIS I fexpand */
2488 gen_op_load_fpr_DT0(rs1);
2489 gen_op_load_fpr_DT1(rs2);
2490 gen_op_fexpand();
2491 gen_op_store_DT0_fpr(rd);
2492 break;
2493 case 0x050: /* VIS I fpadd16 */
2494 gen_op_load_fpr_DT0(rs1);
2495 gen_op_load_fpr_DT1(rs2);
2496 gen_op_fpadd16();
2497 gen_op_store_DT0_fpr(rd);
2498 break;
2499 case 0x051: /* VIS I fpadd16s */
2500 gen_op_load_fpr_FT0(rs1);
2501 gen_op_load_fpr_FT1(rs2);
2502 gen_op_fpadd16s();
2503 gen_op_store_FT0_fpr(rd);
2504 break;
2505 case 0x052: /* VIS I fpadd32 */
2506 gen_op_load_fpr_DT0(rs1);
2507 gen_op_load_fpr_DT1(rs2);
2508 gen_op_fpadd32();
2509 gen_op_store_DT0_fpr(rd);
2510 break;
2511 case 0x053: /* VIS I fpadd32s */
2512 gen_op_load_fpr_FT0(rs1);
2513 gen_op_load_fpr_FT1(rs2);
2514 gen_op_fpadd32s();
2515 gen_op_store_FT0_fpr(rd);
2516 break;
2517 case 0x054: /* VIS I fpsub16 */
2518 gen_op_load_fpr_DT0(rs1);
2519 gen_op_load_fpr_DT1(rs2);
2520 gen_op_fpsub16();
2521 gen_op_store_DT0_fpr(rd);
2522 break;
2523 case 0x055: /* VIS I fpsub16s */
2524 gen_op_load_fpr_FT0(rs1);
2525 gen_op_load_fpr_FT1(rs2);
2526 gen_op_fpsub16s();
2527 gen_op_store_FT0_fpr(rd);
2528 break;
2529 case 0x056: /* VIS I fpsub32 */
2530 gen_op_load_fpr_DT0(rs1);
2531 gen_op_load_fpr_DT1(rs2);
2532 gen_op_fpadd32();
2533 gen_op_store_DT0_fpr(rd);
2534 break;
2535 case 0x057: /* VIS I fpsub32s */
2536 gen_op_load_fpr_FT0(rs1);
2537 gen_op_load_fpr_FT1(rs2);
2538 gen_op_fpsub32s();
2539 gen_op_store_FT0_fpr(rd);
2540 break;
3299908c 2541 case 0x060: /* VIS I fzero */
3299908c
BS		 2542 gen_op_movl_DT0_0();
2543 gen_op_store_DT0_fpr(rd);
2544 break;
2545 case 0x061: /* VIS I fzeros */
3299908c
BS		 2546 gen_op_movl_FT0_0();
2547 gen_op_store_FT0_fpr(rd);
2548 break;
e9ebed4d
BS		 2549 case 0x062: /* VIS I fnor */
2550 gen_op_load_fpr_DT0(rs1);
2551 gen_op_load_fpr_DT1(rs2);
2552 gen_op_fnor();
2553 gen_op_store_DT0_fpr(rd);
2554 break;
2555 case 0x063: /* VIS I fnors */
2556 gen_op_load_fpr_FT0(rs1);
2557 gen_op_load_fpr_FT1(rs2);
2558 gen_op_fnors();
2559 gen_op_store_FT0_fpr(rd);
2560 break;
2561 case 0x064: /* VIS I fandnot2 */
2562 gen_op_load_fpr_DT1(rs1);
2563 gen_op_load_fpr_DT0(rs2);
2564 gen_op_fandnot();
2565 gen_op_store_DT0_fpr(rd);
2566 break;
2567 case 0x065: /* VIS I fandnot2s */
2568 gen_op_load_fpr_FT1(rs1);
2569 gen_op_load_fpr_FT0(rs2);
2570 gen_op_fandnots();
2571 gen_op_store_FT0_fpr(rd);
2572 break;
2573 case 0x066: /* VIS I fnot2 */
2574 gen_op_load_fpr_DT1(rs2);
2575 gen_op_fnot();
2576 gen_op_store_DT0_fpr(rd);
2577 break;
2578 case 0x067: /* VIS I fnot2s */
2579 gen_op_load_fpr_FT1(rs2);
2580 gen_op_fnot();
2581 gen_op_store_FT0_fpr(rd);
2582 break;
2583 case 0x068: /* VIS I fandnot1 */
2584 gen_op_load_fpr_DT0(rs1);
2585 gen_op_load_fpr_DT1(rs2);
2586 gen_op_fandnot();
2587 gen_op_store_DT0_fpr(rd);
2588 break;
2589 case 0x069: /* VIS I fandnot1s */
2590 gen_op_load_fpr_FT0(rs1);
2591 gen_op_load_fpr_FT1(rs2);
2592 gen_op_fandnots();
2593 gen_op_store_FT0_fpr(rd);
2594 break;
2595 case 0x06a: /* VIS I fnot1 */
2596 gen_op_load_fpr_DT1(rs1);
2597 gen_op_fnot();
2598 gen_op_store_DT0_fpr(rd);
2599 break;
2600 case 0x06b: /* VIS I fnot1s */
2601 gen_op_load_fpr_FT1(rs1);
2602 gen_op_fnot();
2603 gen_op_store_FT0_fpr(rd);
2604 break;
2605 case 0x06c: /* VIS I fxor */
2606 gen_op_load_fpr_DT0(rs1);
2607 gen_op_load_fpr_DT1(rs2);
2608 gen_op_fxor();
2609 gen_op_store_DT0_fpr(rd);
2610 break;
2611 case 0x06d: /* VIS I fxors */
2612 gen_op_load_fpr_FT0(rs1);
2613 gen_op_load_fpr_FT1(rs2);
2614 gen_op_fxors();
2615 gen_op_store_FT0_fpr(rd);
2616 break;
2617 case 0x06e: /* VIS I fnand */
2618 gen_op_load_fpr_DT0(rs1);
2619 gen_op_load_fpr_DT1(rs2);
2620 gen_op_fnand();
2621 gen_op_store_DT0_fpr(rd);
2622 break;
2623 case 0x06f: /* VIS I fnands */
2624 gen_op_load_fpr_FT0(rs1);
2625 gen_op_load_fpr_FT1(rs2);
2626 gen_op_fnands();
2627 gen_op_store_FT0_fpr(rd);
2628 break;
2629 case 0x070: /* VIS I fand */
2630 gen_op_load_fpr_DT0(rs1);
2631 gen_op_load_fpr_DT1(rs2);
2632 gen_op_fand();
2633 gen_op_store_DT0_fpr(rd);
2634 break;
2635 case 0x071: /* VIS I fands */
2636 gen_op_load_fpr_FT0(rs1);
2637 gen_op_load_fpr_FT1(rs2);
2638 gen_op_fands();
2639 gen_op_store_FT0_fpr(rd);
2640 break;
2641 case 0x072: /* VIS I fxnor */
2642 gen_op_load_fpr_DT0(rs1);
2643 gen_op_load_fpr_DT1(rs2);
2644 gen_op_fxnor();
2645 gen_op_store_DT0_fpr(rd);
2646 break;
2647 case 0x073: /* VIS I fxnors */
2648 gen_op_load_fpr_FT0(rs1);
2649 gen_op_load_fpr_FT1(rs2);
2650 gen_op_fxnors();
2651 gen_op_store_FT0_fpr(rd);
2652 break;
3299908c 2653 case 0x074: /* VIS I fsrc1 */
3299908c
BS		 2654 gen_op_load_fpr_DT0(rs1);
2655 gen_op_store_DT0_fpr(rd);
2656 break;
2657 case 0x075: /* VIS I fsrc1s */
3299908c
BS		 2658 gen_op_load_fpr_FT0(rs1);
2659 gen_op_store_FT0_fpr(rd);
2660 break;
e9ebed4d
BS		 2661 case 0x076: /* VIS I fornot2 */
2662 gen_op_load_fpr_DT1(rs1);
2663 gen_op_load_fpr_DT0(rs2);
2664 gen_op_fornot();
2665 gen_op_store_DT0_fpr(rd);
2666 break;
2667 case 0x077: /* VIS I fornot2s */
2668 gen_op_load_fpr_FT1(rs1);
2669 gen_op_load_fpr_FT0(rs2);
2670 gen_op_fornots();
2671 gen_op_store_FT0_fpr(rd);
2672 break;
3299908c 2673 case 0x078: /* VIS I fsrc2 */
3299908c
BS		 2674 gen_op_load_fpr_DT0(rs2);
2675 gen_op_store_DT0_fpr(rd);
2676 break;
2677 case 0x079: /* VIS I fsrc2s */
3299908c
BS		 2678 gen_op_load_fpr_FT0(rs2);
2679 gen_op_store_FT0_fpr(rd);
2680 break;
e9ebed4d
BS		 2681 case 0x07a: /* VIS I fornot1 */
2682 gen_op_load_fpr_DT0(rs1);
2683 gen_op_load_fpr_DT1(rs2);
2684 gen_op_fornot();
2685 gen_op_store_DT0_fpr(rd);
2686 break;
2687 case 0x07b: /* VIS I fornot1s */
2688 gen_op_load_fpr_FT0(rs1);
2689 gen_op_load_fpr_FT1(rs2);
2690 gen_op_fornots();
2691 gen_op_store_FT0_fpr(rd);
2692 break;
2693 case 0x07c: /* VIS I for */
2694 gen_op_load_fpr_DT0(rs1);
2695 gen_op_load_fpr_DT1(rs2);
2696 gen_op_for();
2697 gen_op_store_DT0_fpr(rd);
2698 break;
2699 case 0x07d: /* VIS I fors */
2700 gen_op_load_fpr_FT0(rs1);
2701 gen_op_load_fpr_FT1(rs2);
2702 gen_op_fors();
2703 gen_op_store_FT0_fpr(rd);
2704 break;
3299908c 2705 case 0x07e: /* VIS I fone */
3299908c
BS		 2706 gen_op_movl_DT0_1();
2707 gen_op_store_DT0_fpr(rd);
2708 break;
2709 case 0x07f: /* VIS I fones */
3299908c
BS		 2710 gen_op_movl_FT0_1();
2711 gen_op_store_FT0_fpr(rd);
2712 break;
e9ebed4d
BS		 2713 case 0x080: /* VIS I shutdown */
2714 case 0x081: /* VIS II siam */
2715 // XXX
2716 goto illegal_insn;
3299908c
BS		 2717 default:
2718 goto illegal_insn;
2719 }
2720#else
0f8a249a 2721 goto ncp_insn;
3299908c
BS		 2722#endif
2723 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045 2724#ifdef TARGET_SPARC64
0f8a249a 2725 goto illegal_insn;
fcc72045 2726#else
0f8a249a 2727 goto ncp_insn;
fcc72045 2728#endif
3475187d 2729#ifdef TARGET_SPARC64
0f8a249a 2730 } else if (xop == 0x39) { /* V9 return */
3475187d 2731 rs1 = GET_FIELD(insn, 13, 17);
1ad21e69 2732 save_state(dc);
0f8a249a
BS		 2733 gen_movl_reg_T0(rs1);
2734 if (IS_IMM) { /* immediate */
2735 rs2 = GET_FIELDs(insn, 19, 31);
3475187d 2736#if defined(OPTIM)
0f8a249a 2737 if (rs2) {
3475187d 2738#endif
0f8a249a
BS		 2739 gen_movl_simm_T1(rs2);
2740 gen_op_add_T1_T0();
3475187d 2741#if defined(OPTIM)
0f8a249a 2742 }
3475187d 2743#endif
0f8a249a 2744 } else { /* register */
3475187d
FB		 2745 rs2 = GET_FIELD(insn, 27, 31);
2746#if defined(OPTIM)
0f8a249a 2747 if (rs2) {
3475187d 2748#endif
0f8a249a
BS		 2749 gen_movl_reg_T1(rs2);
2750 gen_op_add_T1_T0();
3475187d 2751#if defined(OPTIM)
0f8a249a 2752 }
3475187d
FB		 2753#endif
2754 }
0f8a249a
BS		 2755 gen_op_restore();
2756 gen_mov_pc_npc(dc);
6ea4a6c8 2757 gen_op_check_align_T0_3();
0f8a249a
BS		 2758 gen_op_movl_npc_T0();
2759 dc->npc = DYNAMIC_PC;
2760 goto jmp_insn;
3475187d 2761#endif
0f8a249a 2762 } else {
e80cfcfc 2763 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2764 gen_movl_reg_T0(rs1);
2765 if (IS_IMM) { /* immediate */
2766 rs2 = GET_FIELDs(insn, 19, 31);
e80cfcfc 2767#if defined(OPTIM)
0f8a249a 2768 if (rs2) {
e8af50a3 2769#endif
0f8a249a
BS		 2770 gen_movl_simm_T1(rs2);
2771 gen_op_add_T1_T0();
e80cfcfc 2772#if defined(OPTIM)
0f8a249a 2773 }
e8af50a3 2774#endif
0f8a249a 2775 } else { /* register */
e80cfcfc
FB		 2776 rs2 = GET_FIELD(insn, 27, 31);
2777#if defined(OPTIM)
0f8a249a 2778 if (rs2) {
e80cfcfc 2779#endif
0f8a249a
BS		 2780 gen_movl_reg_T1(rs2);
2781 gen_op_add_T1_T0();
e80cfcfc 2782#if defined(OPTIM)
0f8a249a 2783 }
e8af50a3 2784#endif
cf495bcf 2785 }
0f8a249a
BS		 2786 switch (xop) {
2787 case 0x38: /* jmpl */
2788 {
2789 if (rd != 0) {
ded3ab80
PB		 2790#ifdef TARGET_SPARC64
2791 if (dc->pc == (uint32_t)dc->pc) {
2792 gen_op_movl_T1_im(dc->pc);
2793 } else {
2794 gen_op_movq_T1_im64(dc->pc >> 32, dc->pc);
2795 }
2796#else
0f8a249a 2797 gen_op_movl_T1_im(dc->pc);
ded3ab80 2798#endif
0f8a249a
BS		 2799 gen_movl_T1_reg(rd);
2800 }
0bee699e 2801 gen_mov_pc_npc(dc);
6ea4a6c8 2802 gen_op_check_align_T0_3();
0f8a249a
BS		 2803 gen_op_movl_npc_T0();
2804 dc->npc = DYNAMIC_PC;
2805 }
2806 goto jmp_insn;
3475187d 2807#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
0f8a249a
BS		 2808 case 0x39: /* rett, V9 return */
2809 {
2810 if (!supervisor(dc))
2811 goto priv_insn;
0bee699e 2812 gen_mov_pc_npc(dc);
6ea4a6c8 2813 gen_op_check_align_T0_3();
0f8a249a
BS		 2814 gen_op_movl_npc_T0();
2815 dc->npc = DYNAMIC_PC;
2816 gen_op_rett();
2817 }
2818 goto jmp_insn;
2819#endif
2820 case 0x3b: /* flush */
2821 gen_op_flush_T0();
2822 break;
2823 case 0x3c: /* save */
2824 save_state(dc);
2825 gen_op_save();
2826 gen_movl_T0_reg(rd);
2827 break;
2828 case 0x3d: /* restore */
2829 save_state(dc);
2830 gen_op_restore();
2831 gen_movl_T0_reg(rd);
2832 break;
3475187d 2833#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
0f8a249a
BS		 2834 case 0x3e: /* V9 done/retry */
2835 {
2836 switch (rd) {
2837 case 0:
2838 if (!supervisor(dc))
2839 goto priv_insn;
2840 dc->npc = DYNAMIC_PC;
2841 dc->pc = DYNAMIC_PC;
2842 gen_op_done();
2843 goto jmp_insn;
2844 case 1:
2845 if (!supervisor(dc))
2846 goto priv_insn;
2847 dc->npc = DYNAMIC_PC;
2848 dc->pc = DYNAMIC_PC;
2849 gen_op_retry();
2850 goto jmp_insn;
2851 default:
2852 goto illegal_insn;
2853 }
2854 }
2855 break;
2856#endif
2857 default:
2858 goto illegal_insn;
2859 }
cf495bcf 2860 }
0f8a249a
BS		 2861 break;
2862 }
2863 break;
2864 case 3: /* load/store instructions */
2865 {
2866 unsigned int xop = GET_FIELD(insn, 7, 12);
2867 rs1 = GET_FIELD(insn, 13, 17);
2371aaa2 2868 save_state(dc);
0f8a249a 2869 gen_movl_reg_T0(rs1);
81ad8ba2
BS		 2870 if (xop == 0x3c || xop == 0x3e)
2871 {
2872 rs2 = GET_FIELD(insn, 27, 31);
2873 gen_movl_reg_T1(rs2);
2874 }
2875 else if (IS_IMM) { /* immediate */
0f8a249a 2876 rs2 = GET_FIELDs(insn, 19, 31);
e80cfcfc 2877#if defined(OPTIM)
0f8a249a 2878 if (rs2 != 0) {
e80cfcfc 2879#endif
0f8a249a
BS		 2880 gen_movl_simm_T1(rs2);
2881 gen_op_add_T1_T0();
e80cfcfc 2882#if defined(OPTIM)
0f8a249a 2883 }
e80cfcfc 2884#endif
0f8a249a
BS		 2885 } else { /* register */
2886 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc 2887#if defined(OPTIM)
0f8a249a 2888 if (rs2 != 0) {
e80cfcfc 2889#endif
0f8a249a
BS		 2890 gen_movl_reg_T1(rs2);
2891 gen_op_add_T1_T0();
e80cfcfc 2892#if defined(OPTIM)
0f8a249a 2893 }
e80cfcfc 2894#endif
0f8a249a 2895 }
2f2ecb83
BS		 2896 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
2897 (xop > 0x17 && xop <= 0x1d ) ||
2898 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
0f8a249a
BS		 2899 switch (xop) {
2900 case 0x0: /* load word */
6ea4a6c8
BS		 2901#ifdef CONFIG_USER_ONLY
2902 gen_op_check_align_T0_3();
2903#endif
dc011987 2904#ifndef TARGET_SPARC64
0f8a249a 2905 gen_op_ldst(ld);
dc011987
BS		 2906#else
2907 gen_op_ldst(lduw);
2908#endif
0f8a249a
BS		 2909 break;
2910 case 0x1: /* load unsigned byte */
2911 gen_op_ldst(ldub);
2912 break;
2913 case 0x2: /* load unsigned halfword */
6ea4a6c8
BS		 2914#ifdef CONFIG_USER_ONLY
2915 gen_op_check_align_T0_1();
2916#endif
0f8a249a
BS		 2917 gen_op_ldst(lduh);
2918 break;
2919 case 0x3: /* load double word */
6ea4a6c8 2920 gen_op_check_align_T0_7();
0f8a249a 2921 if (rd & 1)
d4218d99 2922 goto illegal_insn;
0f8a249a
BS		 2923 gen_op_ldst(ldd);
2924 gen_movl_T0_reg(rd + 1);
2925 break;
2926 case 0x9: /* load signed byte */
2927 gen_op_ldst(ldsb);
2928 break;
2929 case 0xa: /* load signed halfword */
6ea4a6c8
BS		 2930#ifdef CONFIG_USER_ONLY
2931 gen_op_check_align_T0_1();
2932#endif
0f8a249a
BS		 2933 gen_op_ldst(ldsh);
2934 break;
2935 case 0xd: /* ldstub -- XXX: should be atomically */
2936 gen_op_ldst(ldstub);
2937 break;
2938 case 0x0f: /* swap register with memory. Also atomically */
6ea4a6c8
BS		 2939#ifdef CONFIG_USER_ONLY
2940 gen_op_check_align_T0_3();
2941#endif
0f8a249a
BS		 2942 gen_movl_reg_T1(rd);
2943 gen_op_ldst(swap);
2944 break;
3475187d 2945#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 2946 case 0x10: /* load word alternate */
3475187d 2947#ifndef TARGET_SPARC64
0f8a249a
BS		 2948 if (IS_IMM)
2949 goto illegal_insn;
2950 if (!supervisor(dc))
2951 goto priv_insn;
81ad8ba2 2952#elif CONFIG_USER_ONLY
6ea4a6c8
BS		 2953 gen_op_check_align_T0_3();
2954#endif
81ad8ba2 2955 gen_ld_asi(insn, 4, 0);
0f8a249a
BS		 2956 break;
2957 case 0x11: /* load unsigned byte alternate */
3475187d 2958#ifndef TARGET_SPARC64
0f8a249a
BS		 2959 if (IS_IMM)
2960 goto illegal_insn;
2961 if (!supervisor(dc))
2962 goto priv_insn;
2963#endif
81ad8ba2 2964 gen_ld_asi(insn, 1, 0);
0f8a249a
BS		 2965 break;
2966 case 0x12: /* load unsigned halfword alternate */
3475187d 2967#ifndef TARGET_SPARC64
0f8a249a
BS		 2968 if (IS_IMM)
2969 goto illegal_insn;
2970 if (!supervisor(dc))
2971 goto priv_insn;
81ad8ba2 2972#elif CONFIG_USER_ONLY
6ea4a6c8 2973 gen_op_check_align_T0_1();
3475187d 2974#endif
81ad8ba2 2975 gen_ld_asi(insn, 2, 0);
0f8a249a
BS		 2976 break;
2977 case 0x13: /* load double word alternate */
3475187d 2978#ifndef TARGET_SPARC64
0f8a249a
BS		 2979 if (IS_IMM)
2980 goto illegal_insn;
2981 if (!supervisor(dc))
2982 goto priv_insn;
3475187d 2983#endif
0f8a249a 2984 if (rd & 1)
d4218d99 2985 goto illegal_insn;
6ea4a6c8 2986 gen_op_check_align_T0_7();
81ad8ba2 2987 gen_ldda_asi(insn);
0f8a249a
BS		 2988 gen_movl_T0_reg(rd + 1);
2989 break;
2990 case 0x19: /* load signed byte alternate */
3475187d 2991#ifndef TARGET_SPARC64
0f8a249a
BS		 2992 if (IS_IMM)
2993 goto illegal_insn;
2994 if (!supervisor(dc))
2995 goto priv_insn;
2996#endif
81ad8ba2 2997 gen_ld_asi(insn, 1, 1);
0f8a249a
BS		 2998 break;
2999 case 0x1a: /* load signed halfword alternate */
3475187d 3000#ifndef TARGET_SPARC64
0f8a249a
BS		 3001 if (IS_IMM)
3002 goto illegal_insn;
3003 if (!supervisor(dc))
3004 goto priv_insn;
81ad8ba2 3005#elif CONFIG_USER_ONLY
6ea4a6c8 3006 gen_op_check_align_T0_1();
3475187d 3007#endif
81ad8ba2 3008 gen_ld_asi(insn, 2, 1);
0f8a249a
BS		 3009 break;
3010 case 0x1d: /* ldstuba -- XXX: should be atomically */
3475187d 3011#ifndef TARGET_SPARC64
0f8a249a
BS		 3012 if (IS_IMM)
3013 goto illegal_insn;
3014 if (!supervisor(dc))
3015 goto priv_insn;
3016#endif
81ad8ba2 3017 gen_ldstub_asi(insn);
0f8a249a
BS		 3018 break;
3019 case 0x1f: /* swap reg with alt. memory. Also atomically */
3475187d 3020#ifndef TARGET_SPARC64
0f8a249a
BS		 3021 if (IS_IMM)
3022 goto illegal_insn;
3023 if (!supervisor(dc))
3024 goto priv_insn;
81ad8ba2 3025#elif CONFIG_USER_ONLY
6ea4a6c8
BS		 3026 gen_op_check_align_T0_3();
3027#endif
81ad8ba2
BS		 3028 gen_movl_reg_T1(rd);
3029 gen_swap_asi(insn);
0f8a249a 3030 break;
3475187d
FB		 3031
3032#ifndef TARGET_SPARC64
0f8a249a
BS		 3033 case 0x30: /* ldc */
3034 case 0x31: /* ldcsr */
3035 case 0x33: /* lddc */
3036 goto ncp_insn;
3475187d
FB		 3037#endif
3038#endif
3039#ifdef TARGET_SPARC64
0f8a249a 3040 case 0x08: /* V9 ldsw */
6ea4a6c8
BS		 3041#ifdef CONFIG_USER_ONLY
3042 gen_op_check_align_T0_3();
3043#endif
0f8a249a
BS		 3044 gen_op_ldst(ldsw);
3045 break;
3046 case 0x0b: /* V9 ldx */
6ea4a6c8 3047 gen_op_check_align_T0_7();
0f8a249a
BS		 3048 gen_op_ldst(ldx);
3049 break;
3050 case 0x18: /* V9 ldswa */
6ea4a6c8
BS		 3051#ifdef CONFIG_USER_ONLY
3052 gen_op_check_align_T0_3();
3053#endif
81ad8ba2 3054 gen_ld_asi(insn, 4, 1);
0f8a249a
BS		 3055 break;
3056 case 0x1b: /* V9 ldxa */
6ea4a6c8 3057 gen_op_check_align_T0_7();
81ad8ba2 3058 gen_ld_asi(insn, 8, 0);
0f8a249a
BS		 3059 break;
3060 case 0x2d: /* V9 prefetch, no effect */
3061 goto skip_move;
3062 case 0x30: /* V9 ldfa */
6ea4a6c8
BS		 3063#ifdef CONFIG_USER_ONLY
3064 gen_op_check_align_T0_3();
3065#endif
81ad8ba2
BS		 3066 gen_ld_asi(insn, 8, 0); // XXX
3067 goto skip_move;
0f8a249a 3068 case 0x33: /* V9 lddfa */
6ea4a6c8 3069 gen_op_check_align_T0_7();
81ad8ba2
BS		 3070 gen_ld_asi(insn, 8, 0); // XXX
3071 goto skip_move;
0f8a249a
BS		 3072 case 0x3d: /* V9 prefetcha, no effect */
3073 goto skip_move;
3074 case 0x32: /* V9 ldqfa */
3075 goto nfpu_insn;
3076#endif
3077 default:
3078 goto illegal_insn;
3079 }
3080 gen_movl_T1_reg(rd);
3475187d 3081#ifdef TARGET_SPARC64
0f8a249a 3082 skip_move: ;
3475187d 3083#endif
0f8a249a 3084 } else if (xop >= 0x20 && xop < 0x24) {
a80dde08
FB		 3085 if (gen_trap_ifnofpu(dc))
3086 goto jmp_insn;
0f8a249a
BS		 3087 switch (xop) {
3088 case 0x20: /* load fpreg */
6ea4a6c8
BS		 3089#ifdef CONFIG_USER_ONLY
3090 gen_op_check_align_T0_3();
3091#endif
0f8a249a
BS		 3092 gen_op_ldst(ldf);
3093 gen_op_store_FT0_fpr(rd);
3094 break;
3095 case 0x21: /* load fsr */
6ea4a6c8
BS		 3096#ifdef CONFIG_USER_ONLY
3097 gen_op_check_align_T0_3();
3098#endif
0f8a249a
BS		 3099 gen_op_ldst(ldf);
3100 gen_op_ldfsr();
3101 break;
3102 case 0x22: /* load quad fpreg */
3103 goto nfpu_insn;
3104 case 0x23: /* load double fpreg */
6ea4a6c8 3105 gen_op_check_align_T0_7();
0f8a249a
BS		 3106 gen_op_ldst(lddf);
3107 gen_op_store_DT0_fpr(DFPREG(rd));
3108 break;
3109 default:
3110 goto illegal_insn;
3111 }
3112 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
3113 xop == 0xe || xop == 0x1e) {
3114 gen_movl_reg_T1(rd);
3115 switch (xop) {
3116 case 0x4:
6ea4a6c8
BS		 3117#ifdef CONFIG_USER_ONLY
3118 gen_op_check_align_T0_3();
3119#endif
0f8a249a
BS		 3120 gen_op_ldst(st);
3121 break;
3122 case 0x5:
3123 gen_op_ldst(stb);
3124 break;
3125 case 0x6:
6ea4a6c8
BS		 3126#ifdef CONFIG_USER_ONLY
3127 gen_op_check_align_T0_1();
3128#endif
0f8a249a
BS		 3129 gen_op_ldst(sth);
3130 break;
3131 case 0x7:
3132 if (rd & 1)
d4218d99 3133 goto illegal_insn;
6ea4a6c8 3134 gen_op_check_align_T0_7();
72cbca10 3135 flush_T2(dc);
0f8a249a
BS		 3136 gen_movl_reg_T2(rd + 1);
3137 gen_op_ldst(std);
3138 break;
3475187d 3139#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 3140 case 0x14:
3475187d 3141#ifndef TARGET_SPARC64
0f8a249a
BS		 3142 if (IS_IMM)
3143 goto illegal_insn;
3144 if (!supervisor(dc))
3145 goto priv_insn;
6ea4a6c8
BS		 3146#endif
3147#ifdef CONFIG_USER_ONLY
3148 gen_op_check_align_T0_3();
3475187d 3149#endif
81ad8ba2 3150 gen_st_asi(insn, 4);
d39c0b99 3151 break;
0f8a249a 3152 case 0x15:
3475187d 3153#ifndef TARGET_SPARC64
0f8a249a
BS		 3154 if (IS_IMM)
3155 goto illegal_insn;
3156 if (!supervisor(dc))
3157 goto priv_insn;
3475187d 3158#endif
81ad8ba2 3159 gen_st_asi(insn, 1);
d39c0b99 3160 break;
0f8a249a 3161 case 0x16:
3475187d 3162#ifndef TARGET_SPARC64
0f8a249a
BS		 3163 if (IS_IMM)
3164 goto illegal_insn;
3165 if (!supervisor(dc))
3166 goto priv_insn;
6ea4a6c8
BS		 3167#endif
3168#ifdef CONFIG_USER_ONLY
3169 gen_op_check_align_T0_1();
3475187d 3170#endif
81ad8ba2 3171 gen_st_asi(insn, 2);
d39c0b99 3172 break;
0f8a249a 3173 case 0x17:
3475187d 3174#ifndef TARGET_SPARC64
0f8a249a
BS		 3175 if (IS_IMM)
3176 goto illegal_insn;
3177 if (!supervisor(dc))
3178 goto priv_insn;
3475187d 3179#endif
0f8a249a 3180 if (rd & 1)
d4218d99 3181 goto illegal_insn;
6ea4a6c8 3182 gen_op_check_align_T0_7();
e8af50a3 3183 flush_T2(dc);
0f8a249a 3184 gen_movl_reg_T2(rd + 1);
81ad8ba2 3185 gen_stda_asi(insn);
d39c0b99 3186 break;
e80cfcfc 3187#endif
3475187d 3188#ifdef TARGET_SPARC64
0f8a249a 3189 case 0x0e: /* V9 stx */
6ea4a6c8 3190 gen_op_check_align_T0_7();
0f8a249a
BS		 3191 gen_op_ldst(stx);
3192 break;
3193 case 0x1e: /* V9 stxa */
6ea4a6c8 3194 gen_op_check_align_T0_7();
81ad8ba2 3195 gen_st_asi(insn, 8);
0f8a249a 3196 break;
3475187d 3197#endif
0f8a249a
BS		 3198 default:
3199 goto illegal_insn;
3200 }
3201 } else if (xop > 0x23 && xop < 0x28) {
a80dde08
FB		 3202 if (gen_trap_ifnofpu(dc))
3203 goto jmp_insn;
0f8a249a
BS		 3204 switch (xop) {
3205 case 0x24:
6ea4a6c8
BS		 3206#ifdef CONFIG_USER_ONLY
3207 gen_op_check_align_T0_3();
3208#endif
e8af50a3 3209 gen_op_load_fpr_FT0(rd);
0f8a249a
BS		 3210 gen_op_ldst(stf);
3211 break;
3212 case 0x25: /* stfsr, V9 stxfsr */
6ea4a6c8
BS		 3213#ifdef CONFIG_USER_ONLY
3214 gen_op_check_align_T0_3();
3215#endif
0f8a249a
BS		 3216 gen_op_stfsr();
3217 gen_op_ldst(stf);
3218 break;
9143e598 3219#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3220 case 0x26: /* stdfq */
3221 if (!supervisor(dc))
3222 goto priv_insn;
3223 if (gen_trap_ifnofpu(dc))
3224 goto jmp_insn;
3225 goto nfq_insn;
3226#endif
3227 case 0x27:
6ea4a6c8 3228 gen_op_check_align_T0_7();
3475187d 3229 gen_op_load_fpr_DT0(DFPREG(rd));
0f8a249a
BS		 3230 gen_op_ldst(stdf);
3231 break;
3232 default:
3233 goto illegal_insn;
3234 }
3235 } else if (xop > 0x33 && xop < 0x3f) {
3236 switch (xop) {
a4d17f19 3237#ifdef TARGET_SPARC64
0f8a249a 3238 case 0x34: /* V9 stfa */
6ea4a6c8
BS		 3239#ifdef CONFIG_USER_ONLY
3240 gen_op_check_align_T0_3();
3241#endif
81ad8ba2 3242 gen_st_asi(insn, 0); // XXX
0f8a249a
BS		 3243 break;
3244 case 0x37: /* V9 stdfa */
6ea4a6c8 3245 gen_op_check_align_T0_7();
81ad8ba2 3246 gen_st_asi(insn, 0); // XXX
0f8a249a
BS		 3247 break;
3248 case 0x3c: /* V9 casa */
6ea4a6c8
BS		 3249#ifdef CONFIG_USER_ONLY
3250 gen_op_check_align_T0_3();
3251#endif
81ad8ba2
BS		 3252 flush_T2(dc);
3253 gen_movl_reg_T2(rd);
3254 gen_cas_asi(insn);
3255 gen_movl_T1_reg(rd);
0f8a249a
BS		 3256 break;
3257 case 0x3e: /* V9 casxa */
6ea4a6c8 3258 gen_op_check_align_T0_7();
81ad8ba2
BS		 3259 flush_T2(dc);
3260 gen_movl_reg_T2(rd);
3261 gen_casx_asi(insn);
3262 gen_movl_T1_reg(rd);
0f8a249a
BS		 3263 break;
3264 case 0x36: /* V9 stqfa */
3265 goto nfpu_insn;
a4d17f19 3266#else
0f8a249a
BS		 3267 case 0x34: /* stc */
3268 case 0x35: /* stcsr */
3269 case 0x36: /* stdcq */
3270 case 0x37: /* stdc */
3271 goto ncp_insn;
3272#endif
3273 default:
3274 goto illegal_insn;
3275 }
e8af50a3 3276 }
0f8a249a
BS		 3277 else
3278 goto illegal_insn;
3279 }
3280 break;
cf495bcf
FB		 3281 }
3282 /* default case for non jump instructions */
72cbca10 3283 if (dc->npc == DYNAMIC_PC) {
0f8a249a
BS		 3284 dc->pc = DYNAMIC_PC;
3285 gen_op_next_insn();
72cbca10
FB		 3286 } else if (dc->npc == JUMP_PC) {
3287 /* we can do a static jump */
46525e1f 3288 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1]);
72cbca10
FB		 3289 dc->is_br = 1;
3290 } else {
0f8a249a
BS		 3291 dc->pc = dc->npc;
3292 dc->npc = dc->npc + 4;
cf495bcf 3293 }
e80cfcfc 3294 jmp_insn:
cf495bcf
FB		 3295 return;
3296 illegal_insn:
72cbca10 3297 save_state(dc);
cf495bcf
FB		 3298 gen_op_exception(TT_ILL_INSN);
3299 dc->is_br = 1;
e8af50a3 3300 return;
e80cfcfc 3301#if !defined(CONFIG_USER_ONLY)
e8af50a3
FB		 3302 priv_insn:
3303 save_state(dc);
3304 gen_op_exception(TT_PRIV_INSN);
3305 dc->is_br = 1;
e80cfcfc
FB		 3306 return;
3307#endif
3308 nfpu_insn:
3309 save_state(dc);
3310 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
3311 dc->is_br = 1;
fcc72045 3312 return;
9143e598
BS		 3313#if !defined(CONFIG_USER_ONLY)
3314 nfq_insn:
3315 save_state(dc);
3316 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
3317 dc->is_br = 1;
3318 return;
3319#endif
fcc72045
BS		 3320#ifndef TARGET_SPARC64
3321 ncp_insn:
3322 save_state(dc);
3323 gen_op_exception(TT_NCP_INSN);
3324 dc->is_br = 1;
3325 return;
3326#endif
7a3f1944
FB		 3327}
3328
cf495bcf 3329static inline int gen_intermediate_code_internal(TranslationBlock * tb,
0f8a249a 3330 int spc, CPUSPARCState *env)
7a3f1944 3331{
72cbca10 3332 target_ulong pc_start, last_pc;
cf495bcf
FB		 3333 uint16_t *gen_opc_end;
3334 DisasContext dc1, *dc = &dc1;
e8af50a3 3335 int j, lj = -1;
cf495bcf
FB		 3336
3337 memset(dc, 0, sizeof(DisasContext));
cf495bcf 3338 dc->tb = tb;
72cbca10 3339 pc_start = tb->pc;
cf495bcf 3340 dc->pc = pc_start;
e80cfcfc 3341 last_pc = dc->pc;
72cbca10 3342 dc->npc = (target_ulong) tb->cs_base;
e8af50a3
FB		 3343#if defined(CONFIG_USER_ONLY)
3344 dc->mem_idx = 0;
a80dde08 3345 dc->fpu_enabled = 1;
e8af50a3
FB		 3346#else
3347 dc->mem_idx = ((env->psrs) != 0);
a80dde08
FB		 3348#ifdef TARGET_SPARC64
3349 dc->fpu_enabled = (((env->pstate & PS_PEF) != 0) && ((env->fprs & FPRS_FEF) != 0));
3350#else
3351 dc->fpu_enabled = ((env->psref) != 0);
3352#endif
e8af50a3 3353#endif
cf495bcf
FB		 3354 gen_opc_ptr = gen_opc_buf;
3355 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3356 gen_opparam_ptr = gen_opparam_buf;
83469015 3357 nb_gen_labels = 0;
cf495bcf
FB		 3358
3359 do {
e8af50a3
FB		 3360 if (env->nb_breakpoints > 0) {
3361 for(j = 0; j < env->nb_breakpoints; j++) {
3362 if (env->breakpoints[j] == dc->pc) {
0f8a249a
BS		 3363 if (dc->pc != pc_start)
3364 save_state(dc);
e80cfcfc 3365 gen_op_debug();
0f8a249a
BS		 3366 gen_op_movl_T0_0();
3367 gen_op_exit_tb();
3368 dc->is_br = 1;
e80cfcfc 3369 goto exit_gen_loop;
e8af50a3
FB		 3370 }
3371 }
3372 }
3373 if (spc) {
3374 if (loglevel > 0)
3375 fprintf(logfile, "Search PC...\n");
3376 j = gen_opc_ptr - gen_opc_buf;
3377 if (lj < j) {
3378 lj++;
3379 while (lj < j)
3380 gen_opc_instr_start[lj++] = 0;
3381 gen_opc_pc[lj] = dc->pc;
3382 gen_opc_npc[lj] = dc->npc;
3383 gen_opc_instr_start[lj] = 1;
3384 }
3385 }
0f8a249a
BS		 3386 last_pc = dc->pc;
3387 disas_sparc_insn(dc);
3388
3389 if (dc->is_br)
3390 break;
3391 /* if the next PC is different, we abort now */
3392 if (dc->pc != (last_pc + 4))
3393 break;
d39c0b99
FB		 3394 /* if we reach a page boundary, we stop generation so that the
3395 PC of a TT_TFAULT exception is always in the right page */
3396 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
3397 break;
e80cfcfc
FB		 3398 /* if single step mode, we generate only one instruction and
3399 generate an exception */
3400 if (env->singlestep_enabled) {
3475187d 3401 gen_jmp_im(dc->pc);
e80cfcfc
FB		 3402 gen_op_movl_T0_0();
3403 gen_op_exit_tb();
3404 break;
3405 }
cf495bcf 3406 } while ((gen_opc_ptr < gen_opc_end) &&
0f8a249a 3407 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
e80cfcfc
FB		 3408
3409 exit_gen_loop:
72cbca10 3410 if (!dc->is_br) {
5fafdf24 3411 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 3412 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
3413 /* static PC and NPC: we can use direct chaining */
46525e1f 3414 gen_branch(dc, dc->pc, dc->npc);
72cbca10
FB		 3415 } else {
3416 if (dc->pc != DYNAMIC_PC)
3475187d 3417 gen_jmp_im(dc->pc);
72cbca10
FB		 3418 save_npc(dc);
3419 gen_op_movl_T0_0();
3420 gen_op_exit_tb();
3421 }
3422 }
cf495bcf 3423 *gen_opc_ptr = INDEX_op_end;
e8af50a3
FB		 3424 if (spc) {
3425 j = gen_opc_ptr - gen_opc_buf;
3426 lj++;
3427 while (lj <= j)
3428 gen_opc_instr_start[lj++] = 0;
e8af50a3
FB		 3429#if 0
3430 if (loglevel > 0) {
3431 page_dump(logfile);
3432 }
3433#endif
c3278b7b
FB		 3434 gen_opc_jump_pc[0] = dc->jump_pc[0];
3435 gen_opc_jump_pc[1] = dc->jump_pc[1];
e8af50a3 3436 } else {
e80cfcfc 3437 tb->size = last_pc + 4 - pc_start;
e8af50a3 3438 }
7a3f1944 3439#ifdef DEBUG_DISAS
e19e89a5 3440 if (loglevel & CPU_LOG_TB_IN_ASM) {
0f8a249a
BS		 3441 fprintf(logfile, "--------------\n");
3442 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3443 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
3444 fprintf(logfile, "\n");
e19e89a5
FB		 3445 if (loglevel & CPU_LOG_TB_OP) {
3446 fprintf(logfile, "OP:\n");
3447 dump_ops(gen_opc_buf, gen_opparam_buf);
3448 fprintf(logfile, "\n");
3449 }
cf495bcf 3450 }
7a3f1944 3451#endif
cf495bcf 3452 return 0;
7a3f1944
FB		 3453}
3454
cf495bcf 3455int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 3456{
e8af50a3 3457 return gen_intermediate_code_internal(tb, 0, env);
7a3f1944
FB		 3458}
3459
cf495bcf 3460int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 3461{
e8af50a3 3462 return gen_intermediate_code_internal(tb, 1, env);
7a3f1944
FB		 3463}
3464
e80cfcfc 3465extern int ram_size;
cf495bcf 3466
e80cfcfc
FB		 3467void cpu_reset(CPUSPARCState *env)
3468{
bb05683b 3469 tlb_flush(env, 1);
cf495bcf
FB		 3470 env->cwp = 0;
3471 env->wim = 1;
3472 env->regwptr = env->regbase + (env->cwp * 16);
e8af50a3 3473#if defined(CONFIG_USER_ONLY)
cf495bcf 3474 env->user_mode_only = 1;
5ef54116 3475#ifdef TARGET_SPARC64
6ef905f6
BS		 3476 env->cleanwin = NWINDOWS - 2;
3477 env->cansave = NWINDOWS - 2;
3478 env->pstate = PS_RMO | PS_PEF | PS_IE;
3479 env->asi = 0x82; // Primary no-fault
5ef54116 3480#endif
e8af50a3 3481#else
32af58f9 3482 env->psret = 0;
e8af50a3 3483 env->psrs = 1;
0bee699e 3484 env->psrps = 1;
3475187d 3485#ifdef TARGET_SPARC64
83469015 3486 env->pstate = PS_PRIV;
83469015 3487 env->pc = 0x1fff0000000ULL;
3475187d 3488#else
83469015 3489 env->pc = 0xffd00000;
32af58f9 3490 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
3475187d 3491#endif
83469015 3492 env->npc = env->pc + 4;
e8af50a3 3493#endif
e80cfcfc
FB		 3494}
3495
3496CPUSPARCState *cpu_sparc_init(void)
3497{
3498 CPUSPARCState *env;
3499
c68ea704
FB		 3500 env = qemu_mallocz(sizeof(CPUSPARCState));
3501 if (!env)
0f8a249a 3502 return NULL;
c68ea704 3503 cpu_exec_init(env);
e80cfcfc 3504 cpu_reset(env);
cf495bcf 3505 return (env);
7a3f1944
FB		 3506}
3507
62724a37
BS		 3508static const sparc_def_t sparc_defs[] = {
3509#ifdef TARGET_SPARC64
3510 {
3511 .name = "TI UltraSparc II",
3512 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0 << 24)
3513 | (MAXTL << 8) | (NWINDOWS - 1)),
3514 .fpu_version = 0x00000000,
3515 .mmu_version = 0,
3516 },
3517#else
3518 {
3519 .name = "Fujitsu MB86904",
3520 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
3521 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3522 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
3523 },
e0353fe2 3524 {
5ef62c5c
BS		 3525 .name = "Fujitsu MB86907",
3526 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
3527 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3528 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
3529 },
3530 {
3531 .name = "TI MicroSparc I",
3532 .iu_version = 0x41000000,
3533 .fpu_version = 4 << 17,
3534 .mmu_version = 0x41000000,
3535 },
3536 {
e0353fe2
BS		 3537 .name = "TI SuperSparc II",
3538 .iu_version = 0x40000000,
5ef62c5c
BS		 3539 .fpu_version = 0 << 17,
3540 .mmu_version = 0x04000000,
3541 },
3542 {
3543 .name = "Ross RT620",
3544 .iu_version = 0x1e000000,
3545 .fpu_version = 1 << 17,
3546 .mmu_version = 0x17000000,
e0353fe2 3547 },
62724a37
BS		 3548#endif
3549};
3550
3551int sparc_find_by_name(const unsigned char *name, const sparc_def_t **def)
3552{
3553 int ret;
3554 unsigned int i;
3555
3556 ret = -1;
3557 *def = NULL;
3558 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
3559 if (strcasecmp(name, sparc_defs[i].name) == 0) {
3560 *def = &sparc_defs[i];
3561 ret = 0;
3562 break;
3563 }
3564 }
3565
3566 return ret;
3567}
3568
3569void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3570{
3571 unsigned int i;
3572
3573 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
3574 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n",
3575 sparc_defs[i].name,
3576 sparc_defs[i].iu_version,
3577 sparc_defs[i].fpu_version,
3578 sparc_defs[i].mmu_version);
3579 }
3580}
3581
3582int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def)
3583{
3584 env->version = def->iu_version;
3585 env->fsr = def->fpu_version;
3586#if !defined(TARGET_SPARC64)
3587 env->mmuregs[0] = def->mmu_version;
3588#endif
3589 return 0;
3590}
3591
7a3f1944
FB		 3592#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
3593
5fafdf24 3594void cpu_dump_state(CPUState *env, FILE *f,
7fe48483
FB		 3595 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
3596 int flags)
7a3f1944 3597{
cf495bcf
FB		 3598 int i, x;
3599
af7bf89b 3600 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
7fe48483 3601 cpu_fprintf(f, "General Registers:\n");
cf495bcf 3602 for (i = 0; i < 4; i++)
0f8a249a 3603 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 3604 cpu_fprintf(f, "\n");
cf495bcf 3605 for (; i < 8; i++)
0f8a249a 3606 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 3607 cpu_fprintf(f, "\nCurrent Register Window:\n");
cf495bcf 3608 for (x = 0; x < 3; x++) {
0f8a249a
BS		 3609 for (i = 0; i < 4; i++)
3610 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
3611 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
3612 env->regwptr[i + x * 8]);
3613 cpu_fprintf(f, "\n");
3614 for (; i < 8; i++)
3615 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
3616 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
3617 env->regwptr[i + x * 8]);
3618 cpu_fprintf(f, "\n");
cf495bcf 3619 }
7fe48483 3620 cpu_fprintf(f, "\nFloating Point Registers:\n");
e8af50a3
FB		 3621 for (i = 0; i < 32; i++) {
3622 if ((i & 3) == 0)
7fe48483
FB		 3623 cpu_fprintf(f, "%%f%02d:", i);
3624 cpu_fprintf(f, " %016lf", env->fpr[i]);
e8af50a3 3625 if ((i & 3) == 3)
7fe48483 3626 cpu_fprintf(f, "\n");
e8af50a3 3627 }
ded3ab80 3628#ifdef TARGET_SPARC64
3299908c 3629 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
0f8a249a 3630 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
ded3ab80 3631 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
0f8a249a
BS		 3632 env->cansave, env->canrestore, env->otherwin, env->wstate,
3633 env->cleanwin, NWINDOWS - 1 - env->cwp);
ded3ab80 3634#else
7fe48483 3635 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
0f8a249a
BS		 3636 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
3637 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
3638 env->psrs?'S':'-', env->psrps?'P':'-',
3639 env->psret?'E':'-', env->wim);
ded3ab80 3640#endif
3475187d 3641 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
7a3f1944 3642}
edfcbd99 3643
e80cfcfc 3644#if defined(CONFIG_USER_ONLY)
9b3c35e0 3645target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
edfcbd99
FB		 3646{
3647 return addr;
3648}
658138bc 3649
e80cfcfc 3650#else
af7bf89b
FB		 3651extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
3652 int *access_index, target_ulong address, int rw,
0fa85d43
FB		 3653 int is_user);
3654
9b3c35e0 3655target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
e80cfcfc 3656{
af7bf89b 3657 target_phys_addr_t phys_addr;
e80cfcfc
FB		 3658 int prot, access_index;
3659
3660 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
6b1575b7
FB		 3661 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 0, 0) != 0)
3662 return -1;
6c36d3fa
BS		 3663 if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
3664 return -1;
e80cfcfc
FB		 3665 return phys_addr;
3666}
3667#endif
3668
658138bc
FB		 3669void helper_flush(target_ulong addr)
3670{
3671 addr &= ~7;
3672 tb_invalidate_page_range(addr, addr + 8);
3673}
Qemu copy for testing