]>
Commit | Line | Data |
---|---|---|
7a3f1944 FB |
1 | /* |
2 | SPARC translation | |
3 | ||
4 | Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at> | |
3475187d | 5 | Copyright (C) 2003-2005 Fabrice Bellard |
7a3f1944 FB |
6 | |
7 | This library is free software; you can redistribute it and/or | |
8 | modify it under the terms of the GNU Lesser General Public | |
9 | License as published by the Free Software Foundation; either | |
10 | version 2 of the License, or (at your option) any later version. | |
11 | ||
12 | This library is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | Lesser General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU Lesser General Public | |
18 | License along with this library; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
7a3f1944 FB |
22 | #include <stdarg.h> |
23 | #include <stdlib.h> | |
24 | #include <stdio.h> | |
25 | #include <string.h> | |
26 | #include <inttypes.h> | |
27 | ||
28 | #include "cpu.h" | |
29 | #include "exec-all.h" | |
30 | #include "disas.h" | |
1a2fb1c0 | 31 | #include "helper.h" |
57fec1fe | 32 | #include "tcg-op.h" |
7a3f1944 FB |
33 | |
34 | #define DEBUG_DISAS | |
35 | ||
72cbca10 FB |
36 | #define DYNAMIC_PC 1 /* dynamic pc value */ |
37 | #define JUMP_PC 2 /* dynamic pc value which takes only two values | |
38 | according to jump_pc[T2] */ | |
39 | ||
1a2fb1c0 | 40 | /* global register indexes */ |
d987963a | 41 | static TCGv cpu_env, cpu_regwptr; |
77f193da | 42 | static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst; |
48d5c82b | 43 | static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; |
6ae20372 | 44 | static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val; |
dc99a3f2 BS |
45 | #ifdef TARGET_SPARC64 |
46 | static TCGv cpu_xcc; | |
47 | #endif | |
1a2fb1c0 | 48 | /* local register indexes (only used inside old micro ops) */ |
8911f501 | 49 | static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64; |
1a2fb1c0 | 50 | |
2e70f6ef PB |
51 | #include "gen-icount.h" |
52 | ||
7a3f1944 | 53 | typedef struct DisasContext { |
0f8a249a BS |
54 | target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */ |
55 | target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */ | |
72cbca10 | 56 | target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ |
cf495bcf | 57 | int is_br; |
e8af50a3 | 58 | int mem_idx; |
a80dde08 | 59 | int fpu_enabled; |
2cade6a3 | 60 | int address_mask_32bit; |
cf495bcf | 61 | struct TranslationBlock *tb; |
64a88d5d | 62 | uint32_t features; |
7a3f1944 FB |
63 | } DisasContext; |
64 | ||
3475187d | 65 | // This function uses non-native bit order |
7a3f1944 FB |
66 | #define GET_FIELD(X, FROM, TO) \ |
67 | ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) | |
68 | ||
3475187d FB |
69 | // This function uses the order in the manuals, i.e. bit 0 is 2^0 |
70 | #define GET_FIELD_SP(X, FROM, TO) \ | |
71 | GET_FIELD(X, 31 - (TO), 31 - (FROM)) | |
72 | ||
73 | #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) | |
46d38ba8 | 74 | #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1)) |
3475187d FB |
75 | |
76 | #ifdef TARGET_SPARC64 | |
19f329ad | 77 | #define FFPREG(r) (r) |
0387d928 | 78 | #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e)) |
1f587329 | 79 | #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c)) |
3475187d | 80 | #else |
19f329ad | 81 | #define FFPREG(r) (r) |
c185970a | 82 | #define DFPREG(r) (r & 0x1e) |
1f587329 | 83 | #define QFPREG(r) (r & 0x1c) |
3475187d FB |
84 | #endif |
85 | ||
86 | static int sign_extend(int x, int len) | |
87 | { | |
88 | len = 32 - len; | |
89 | return (x << len) >> len; | |
90 | } | |
91 | ||
7a3f1944 FB |
92 | #define IS_IMM (insn & (1<<13)) |
93 | ||
ff07ec83 BS |
94 | /* floating point registers moves */ |
95 | static void gen_op_load_fpr_FT0(unsigned int src) | |
96 | { | |
8911f501 BS |
97 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
98 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0)); | |
3475187d | 99 | } |
ff07ec83 BS |
100 | |
101 | static void gen_op_load_fpr_FT1(unsigned int src) | |
102 | { | |
8911f501 BS |
103 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
104 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1)); | |
e8af50a3 FB |
105 | } |
106 | ||
ff07ec83 BS |
107 | static void gen_op_store_FT0_fpr(unsigned int dst) |
108 | { | |
8911f501 BS |
109 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0)); |
110 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst])); | |
ff07ec83 BS |
111 | } |
112 | ||
113 | static void gen_op_load_fpr_DT0(unsigned int src) | |
114 | { | |
8911f501 | 115 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
77f193da BS |
116 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + |
117 | offsetof(CPU_DoubleU, l.upper)); | |
8911f501 | 118 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1])); |
77f193da BS |
119 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + |
120 | offsetof(CPU_DoubleU, l.lower)); | |
ff07ec83 BS |
121 | } |
122 | ||
123 | static void gen_op_load_fpr_DT1(unsigned int src) | |
124 | { | |
8911f501 | 125 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
77f193da BS |
126 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + |
127 | offsetof(CPU_DoubleU, l.upper)); | |
8911f501 | 128 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1])); |
77f193da BS |
129 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + |
130 | offsetof(CPU_DoubleU, l.lower)); | |
ff07ec83 BS |
131 | } |
132 | ||
133 | static void gen_op_store_DT0_fpr(unsigned int dst) | |
134 | { | |
77f193da BS |
135 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + |
136 | offsetof(CPU_DoubleU, l.upper)); | |
8911f501 | 137 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst])); |
77f193da BS |
138 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + |
139 | offsetof(CPU_DoubleU, l.lower)); | |
8911f501 | 140 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1])); |
ff07ec83 BS |
141 | } |
142 | ||
ff07ec83 BS |
143 | static void gen_op_load_fpr_QT0(unsigned int src) |
144 | { | |
8911f501 | 145 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
77f193da BS |
146 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
147 | offsetof(CPU_QuadU, l.upmost)); | |
8911f501 | 148 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1])); |
77f193da BS |
149 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
150 | offsetof(CPU_QuadU, l.upper)); | |
8911f501 | 151 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2])); |
77f193da BS |
152 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
153 | offsetof(CPU_QuadU, l.lower)); | |
8911f501 | 154 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3])); |
77f193da BS |
155 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
156 | offsetof(CPU_QuadU, l.lowest)); | |
ff07ec83 BS |
157 | } |
158 | ||
159 | static void gen_op_load_fpr_QT1(unsigned int src) | |
160 | { | |
8911f501 | 161 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
77f193da BS |
162 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + |
163 | offsetof(CPU_QuadU, l.upmost)); | |
8911f501 | 164 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1])); |
77f193da BS |
165 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + |
166 | offsetof(CPU_QuadU, l.upper)); | |
8911f501 | 167 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2])); |
77f193da BS |
168 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + |
169 | offsetof(CPU_QuadU, l.lower)); | |
8911f501 | 170 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3])); |
77f193da BS |
171 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + |
172 | offsetof(CPU_QuadU, l.lowest)); | |
ff07ec83 BS |
173 | } |
174 | ||
175 | static void gen_op_store_QT0_fpr(unsigned int dst) | |
176 | { | |
77f193da BS |
177 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
178 | offsetof(CPU_QuadU, l.upmost)); | |
8911f501 | 179 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst])); |
77f193da BS |
180 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
181 | offsetof(CPU_QuadU, l.upper)); | |
8911f501 | 182 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1])); |
77f193da BS |
183 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
184 | offsetof(CPU_QuadU, l.lower)); | |
8911f501 | 185 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2])); |
77f193da BS |
186 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
187 | offsetof(CPU_QuadU, l.lowest)); | |
8911f501 | 188 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3])); |
ff07ec83 | 189 | } |
1f587329 | 190 | |
81ad8ba2 BS |
191 | /* moves */ |
192 | #ifdef CONFIG_USER_ONLY | |
3475187d | 193 | #define supervisor(dc) 0 |
81ad8ba2 | 194 | #ifdef TARGET_SPARC64 |
e9ebed4d | 195 | #define hypervisor(dc) 0 |
81ad8ba2 | 196 | #endif |
3475187d | 197 | #else |
6f27aba6 | 198 | #define supervisor(dc) (dc->mem_idx >= 1) |
81ad8ba2 BS |
199 | #ifdef TARGET_SPARC64 |
200 | #define hypervisor(dc) (dc->mem_idx == 2) | |
6f27aba6 | 201 | #else |
3475187d | 202 | #endif |
81ad8ba2 BS |
203 | #endif |
204 | ||
2cade6a3 BS |
205 | #ifdef TARGET_SPARC64 |
206 | #ifndef TARGET_ABI32 | |
207 | #define AM_CHECK(dc) ((dc)->address_mask_32bit) | |
1a2fb1c0 | 208 | #else |
2cade6a3 BS |
209 | #define AM_CHECK(dc) (1) |
210 | #endif | |
1a2fb1c0 | 211 | #endif |
3391c818 | 212 | |
2cade6a3 BS |
213 | static inline void gen_address_mask(DisasContext *dc, TCGv addr) |
214 | { | |
215 | #ifdef TARGET_SPARC64 | |
216 | if (AM_CHECK(dc)) | |
217 | tcg_gen_andi_tl(addr, addr, 0xffffffffULL); | |
218 | #endif | |
219 | } | |
220 | ||
1a2fb1c0 | 221 | static inline void gen_movl_reg_TN(int reg, TCGv tn) |
81ad8ba2 | 222 | { |
1a2fb1c0 BS |
223 | if (reg == 0) |
224 | tcg_gen_movi_tl(tn, 0); | |
225 | else if (reg < 8) | |
f5069b26 | 226 | tcg_gen_mov_tl(tn, cpu_gregs[reg]); |
1a2fb1c0 | 227 | else { |
1a2fb1c0 | 228 | tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
81ad8ba2 BS |
229 | } |
230 | } | |
231 | ||
1a2fb1c0 | 232 | static inline void gen_movl_TN_reg(int reg, TCGv tn) |
81ad8ba2 | 233 | { |
1a2fb1c0 BS |
234 | if (reg == 0) |
235 | return; | |
236 | else if (reg < 8) | |
f5069b26 | 237 | tcg_gen_mov_tl(cpu_gregs[reg], tn); |
1a2fb1c0 | 238 | else { |
1a2fb1c0 | 239 | tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
81ad8ba2 BS |
240 | } |
241 | } | |
242 | ||
5fafdf24 | 243 | static inline void gen_goto_tb(DisasContext *s, int tb_num, |
6e256c93 FB |
244 | target_ulong pc, target_ulong npc) |
245 | { | |
246 | TranslationBlock *tb; | |
247 | ||
248 | tb = s->tb; | |
249 | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) && | |
250 | (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) { | |
251 | /* jump to same page: we can use a direct jump */ | |
57fec1fe | 252 | tcg_gen_goto_tb(tb_num); |
2f5680ee BS |
253 | tcg_gen_movi_tl(cpu_pc, pc); |
254 | tcg_gen_movi_tl(cpu_npc, npc); | |
57fec1fe | 255 | tcg_gen_exit_tb((long)tb + tb_num); |
6e256c93 FB |
256 | } else { |
257 | /* jump to another page: currently not optimized */ | |
2f5680ee BS |
258 | tcg_gen_movi_tl(cpu_pc, pc); |
259 | tcg_gen_movi_tl(cpu_npc, npc); | |
57fec1fe | 260 | tcg_gen_exit_tb(0); |
6e256c93 FB |
261 | } |
262 | } | |
263 | ||
19f329ad BS |
264 | // XXX suboptimal |
265 | static inline void gen_mov_reg_N(TCGv reg, TCGv src) | |
266 | { | |
8911f501 | 267 | tcg_gen_extu_i32_tl(reg, src); |
4b8b8b76 | 268 | tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT); |
19f329ad BS |
269 | tcg_gen_andi_tl(reg, reg, 0x1); |
270 | } | |
271 | ||
272 | static inline void gen_mov_reg_Z(TCGv reg, TCGv src) | |
273 | { | |
8911f501 | 274 | tcg_gen_extu_i32_tl(reg, src); |
4b8b8b76 | 275 | tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT); |
19f329ad BS |
276 | tcg_gen_andi_tl(reg, reg, 0x1); |
277 | } | |
278 | ||
279 | static inline void gen_mov_reg_V(TCGv reg, TCGv src) | |
280 | { | |
8911f501 | 281 | tcg_gen_extu_i32_tl(reg, src); |
4b8b8b76 | 282 | tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT); |
19f329ad BS |
283 | tcg_gen_andi_tl(reg, reg, 0x1); |
284 | } | |
285 | ||
286 | static inline void gen_mov_reg_C(TCGv reg, TCGv src) | |
287 | { | |
8911f501 | 288 | tcg_gen_extu_i32_tl(reg, src); |
4b8b8b76 | 289 | tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT); |
19f329ad BS |
290 | tcg_gen_andi_tl(reg, reg, 0x1); |
291 | } | |
292 | ||
ce5b3c3d | 293 | static inline void gen_cc_clear_icc(void) |
dc99a3f2 BS |
294 | { |
295 | tcg_gen_movi_i32(cpu_psr, 0); | |
ce5b3c3d BS |
296 | } |
297 | ||
dc99a3f2 | 298 | #ifdef TARGET_SPARC64 |
ce5b3c3d BS |
299 | static inline void gen_cc_clear_xcc(void) |
300 | { | |
dc99a3f2 | 301 | tcg_gen_movi_i32(cpu_xcc, 0); |
dc99a3f2 | 302 | } |
ce5b3c3d | 303 | #endif |
dc99a3f2 BS |
304 | |
305 | /* old op: | |
306 | if (!T0) | |
307 | env->psr |= PSR_ZERO; | |
308 | if ((int32_t) T0 < 0) | |
309 | env->psr |= PSR_NEG; | |
310 | */ | |
ce5b3c3d | 311 | static inline void gen_cc_NZ_icc(TCGv dst) |
dc99a3f2 | 312 | { |
8911f501 | 313 | TCGv r_temp; |
dc99a3f2 | 314 | int l1, l2; |
dc99a3f2 BS |
315 | |
316 | l1 = gen_new_label(); | |
317 | l2 = gen_new_label(); | |
8911f501 BS |
318 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
319 | tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL); | |
cb63669a | 320 | tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1); |
dc99a3f2 BS |
321 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO); |
322 | gen_set_label(l1); | |
bdf46ea2 | 323 | tcg_gen_ext_i32_tl(r_temp, dst); |
cb63669a | 324 | tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2); |
dc99a3f2 BS |
325 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG); |
326 | gen_set_label(l2); | |
2ea815ca | 327 | tcg_temp_free(r_temp); |
ce5b3c3d BS |
328 | } |
329 | ||
dc99a3f2 | 330 | #ifdef TARGET_SPARC64 |
ce5b3c3d BS |
331 | static inline void gen_cc_NZ_xcc(TCGv dst) |
332 | { | |
333 | int l1, l2; | |
334 | ||
335 | l1 = gen_new_label(); | |
336 | l2 = gen_new_label(); | |
cb63669a | 337 | tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1); |
ce5b3c3d BS |
338 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO); |
339 | gen_set_label(l1); | |
cb63669a | 340 | tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2); |
ce5b3c3d BS |
341 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG); |
342 | gen_set_label(l2); | |
dc99a3f2 | 343 | } |
ce5b3c3d | 344 | #endif |
dc99a3f2 BS |
345 | |
346 | /* old op: | |
347 | if (T0 < src1) | |
348 | env->psr |= PSR_CARRY; | |
349 | */ | |
ce5b3c3d | 350 | static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1) |
dc99a3f2 | 351 | { |
8911f501 | 352 | TCGv r_temp; |
dc99a3f2 BS |
353 | int l1; |
354 | ||
355 | l1 = gen_new_label(); | |
8911f501 BS |
356 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
357 | tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL); | |
358 | tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1); | |
dc99a3f2 BS |
359 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
360 | gen_set_label(l1); | |
2ea815ca | 361 | tcg_temp_free(r_temp); |
ce5b3c3d BS |
362 | } |
363 | ||
dc99a3f2 | 364 | #ifdef TARGET_SPARC64 |
ce5b3c3d BS |
365 | static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1) |
366 | { | |
367 | int l1; | |
dc99a3f2 | 368 | |
ce5b3c3d BS |
369 | l1 = gen_new_label(); |
370 | tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1); | |
371 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); | |
372 | gen_set_label(l1); | |
dc99a3f2 | 373 | } |
ce5b3c3d | 374 | #endif |
dc99a3f2 BS |
375 | |
376 | /* old op: | |
377 | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31)) | |
378 | env->psr |= PSR_OVF; | |
379 | */ | |
ce5b3c3d | 380 | static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 381 | { |
0425bee5 | 382 | TCGv r_temp; |
dc99a3f2 BS |
383 | |
384 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
dc99a3f2 BS |
385 | tcg_gen_xor_tl(r_temp, src1, src2); |
386 | tcg_gen_xori_tl(r_temp, r_temp, -1); | |
0425bee5 BS |
387 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
388 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
389 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); | |
653ccb80 BS |
390 | tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT); |
391 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); | |
2ea815ca | 392 | tcg_temp_free(r_temp); |
653ccb80 | 393 | tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32); |
ce5b3c3d BS |
394 | } |
395 | ||
dc99a3f2 | 396 | #ifdef TARGET_SPARC64 |
ce5b3c3d BS |
397 | static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2) |
398 | { | |
399 | TCGv r_temp; | |
ce5b3c3d BS |
400 | |
401 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
402 | tcg_gen_xor_tl(r_temp, src1, src2); | |
403 | tcg_gen_xori_tl(r_temp, r_temp, -1); | |
404 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); | |
405 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
406 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | |
653ccb80 BS |
407 | tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT); |
408 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); | |
2ea815ca | 409 | tcg_temp_free(r_temp); |
653ccb80 | 410 | tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32); |
dc99a3f2 | 411 | } |
ce5b3c3d | 412 | #endif |
dc99a3f2 BS |
413 | |
414 | static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) | |
415 | { | |
2ea815ca | 416 | TCGv r_temp, r_const; |
dc99a3f2 BS |
417 | int l1; |
418 | ||
419 | l1 = gen_new_label(); | |
420 | ||
421 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
dc99a3f2 BS |
422 | tcg_gen_xor_tl(r_temp, src1, src2); |
423 | tcg_gen_xori_tl(r_temp, r_temp, -1); | |
0425bee5 BS |
424 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
425 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
426 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); | |
cb63669a | 427 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1); |
2ea815ca BS |
428 | r_const = tcg_const_i32(TT_TOVF); |
429 | tcg_gen_helper_0_1(raise_exception, r_const); | |
430 | tcg_temp_free(r_const); | |
dc99a3f2 | 431 | gen_set_label(l1); |
2ea815ca | 432 | tcg_temp_free(r_temp); |
dc99a3f2 BS |
433 | } |
434 | ||
435 | static inline void gen_cc_V_tag(TCGv src1, TCGv src2) | |
436 | { | |
437 | int l1; | |
dc99a3f2 BS |
438 | |
439 | l1 = gen_new_label(); | |
0425bee5 BS |
440 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
441 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3); | |
cb63669a | 442 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1); |
dc99a3f2 BS |
443 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
444 | gen_set_label(l1); | |
445 | } | |
446 | ||
447 | static inline void gen_tag_tv(TCGv src1, TCGv src2) | |
448 | { | |
449 | int l1; | |
2ea815ca | 450 | TCGv r_const; |
dc99a3f2 BS |
451 | |
452 | l1 = gen_new_label(); | |
0425bee5 BS |
453 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
454 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3); | |
cb63669a | 455 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1); |
2ea815ca BS |
456 | r_const = tcg_const_i32(TT_TOVF); |
457 | tcg_gen_helper_0_1(raise_exception, r_const); | |
458 | tcg_temp_free(r_const); | |
dc99a3f2 BS |
459 | gen_set_label(l1); |
460 | } | |
461 | ||
4af984a7 | 462 | static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 463 | { |
4af984a7 | 464 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 | 465 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
5c6a0628 | 466 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d | 467 | gen_cc_clear_icc(); |
ba28189b BS |
468 | gen_cc_NZ_icc(cpu_cc_dst); |
469 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); | |
470 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d BS |
471 | #ifdef TARGET_SPARC64 |
472 | gen_cc_clear_xcc(); | |
ba28189b BS |
473 | gen_cc_NZ_xcc(cpu_cc_dst); |
474 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); | |
475 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 476 | #endif |
5c6a0628 | 477 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
dc99a3f2 BS |
478 | } |
479 | ||
4af984a7 | 480 | static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 481 | { |
4af984a7 | 482 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 | 483 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
dc99a3f2 | 484 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
5c6a0628 | 485 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
ce5b3c3d | 486 | gen_cc_clear_icc(); |
5c6a0628 | 487 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
ce5b3c3d BS |
488 | #ifdef TARGET_SPARC64 |
489 | gen_cc_clear_xcc(); | |
5c6a0628 | 490 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); |
ce5b3c3d | 491 | #endif |
5c6a0628 | 492 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); |
ba28189b BS |
493 | gen_cc_NZ_icc(cpu_cc_dst); |
494 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); | |
495 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 496 | #ifdef TARGET_SPARC64 |
ba28189b BS |
497 | gen_cc_NZ_xcc(cpu_cc_dst); |
498 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); | |
499 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 500 | #endif |
5c6a0628 | 501 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
dc99a3f2 BS |
502 | } |
503 | ||
4af984a7 | 504 | static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 505 | { |
4af984a7 | 506 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 | 507 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
5c6a0628 | 508 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d | 509 | gen_cc_clear_icc(); |
ba28189b BS |
510 | gen_cc_NZ_icc(cpu_cc_dst); |
511 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); | |
512 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
6f551262 | 513 | gen_cc_V_tag(cpu_cc_src, cpu_cc_src2); |
ce5b3c3d BS |
514 | #ifdef TARGET_SPARC64 |
515 | gen_cc_clear_xcc(); | |
ba28189b BS |
516 | gen_cc_NZ_xcc(cpu_cc_dst); |
517 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); | |
518 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 519 | #endif |
5c6a0628 | 520 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
dc99a3f2 BS |
521 | } |
522 | ||
4af984a7 | 523 | static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 524 | { |
4af984a7 | 525 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 BS |
526 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
527 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); | |
5c6a0628 BS |
528 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
529 | gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 530 | gen_cc_clear_icc(); |
ba28189b BS |
531 | gen_cc_NZ_icc(cpu_cc_dst); |
532 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); | |
ce5b3c3d BS |
533 | #ifdef TARGET_SPARC64 |
534 | gen_cc_clear_xcc(); | |
ba28189b BS |
535 | gen_cc_NZ_xcc(cpu_cc_dst); |
536 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); | |
537 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 538 | #endif |
5c6a0628 | 539 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
dc99a3f2 BS |
540 | } |
541 | ||
542 | /* old op: | |
543 | if (src1 < T1) | |
544 | env->psr |= PSR_CARRY; | |
545 | */ | |
ce5b3c3d | 546 | static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2) |
dc99a3f2 | 547 | { |
8911f501 | 548 | TCGv r_temp1, r_temp2; |
dc99a3f2 BS |
549 | int l1; |
550 | ||
551 | l1 = gen_new_label(); | |
8911f501 BS |
552 | r_temp1 = tcg_temp_new(TCG_TYPE_TL); |
553 | r_temp2 = tcg_temp_new(TCG_TYPE_TL); | |
554 | tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL); | |
555 | tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL); | |
556 | tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1); | |
dc99a3f2 BS |
557 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
558 | gen_set_label(l1); | |
2ea815ca BS |
559 | tcg_temp_free(r_temp1); |
560 | tcg_temp_free(r_temp2); | |
ce5b3c3d BS |
561 | } |
562 | ||
dc99a3f2 | 563 | #ifdef TARGET_SPARC64 |
ce5b3c3d BS |
564 | static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2) |
565 | { | |
566 | int l1; | |
dc99a3f2 | 567 | |
ce5b3c3d BS |
568 | l1 = gen_new_label(); |
569 | tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1); | |
570 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); | |
571 | gen_set_label(l1); | |
dc99a3f2 | 572 | } |
ce5b3c3d | 573 | #endif |
dc99a3f2 BS |
574 | |
575 | /* old op: | |
576 | if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31)) | |
577 | env->psr |= PSR_OVF; | |
578 | */ | |
ce5b3c3d | 579 | static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 580 | { |
0425bee5 | 581 | TCGv r_temp; |
dc99a3f2 BS |
582 | |
583 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
dc99a3f2 | 584 | tcg_gen_xor_tl(r_temp, src1, src2); |
0425bee5 BS |
585 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
586 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
587 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); | |
653ccb80 BS |
588 | tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT); |
589 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); | |
590 | tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32); | |
2ea815ca | 591 | tcg_temp_free(r_temp); |
ce5b3c3d BS |
592 | } |
593 | ||
dc99a3f2 | 594 | #ifdef TARGET_SPARC64 |
ce5b3c3d BS |
595 | static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2) |
596 | { | |
597 | TCGv r_temp; | |
ce5b3c3d BS |
598 | |
599 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
600 | tcg_gen_xor_tl(r_temp, src1, src2); | |
601 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); | |
602 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
603 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | |
653ccb80 BS |
604 | tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT); |
605 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); | |
606 | tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32); | |
2ea815ca | 607 | tcg_temp_free(r_temp); |
dc99a3f2 | 608 | } |
ce5b3c3d | 609 | #endif |
dc99a3f2 BS |
610 | |
611 | static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) | |
612 | { | |
2ea815ca | 613 | TCGv r_temp, r_const; |
dc99a3f2 BS |
614 | int l1; |
615 | ||
616 | l1 = gen_new_label(); | |
617 | ||
618 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
dc99a3f2 | 619 | tcg_gen_xor_tl(r_temp, src1, src2); |
0425bee5 BS |
620 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
621 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
622 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); | |
cb63669a | 623 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1); |
2ea815ca BS |
624 | r_const = tcg_const_i32(TT_TOVF); |
625 | tcg_gen_helper_0_1(raise_exception, r_const); | |
626 | tcg_temp_free(r_const); | |
dc99a3f2 | 627 | gen_set_label(l1); |
2ea815ca | 628 | tcg_temp_free(r_temp); |
dc99a3f2 BS |
629 | } |
630 | ||
4af984a7 | 631 | static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 632 | { |
4af984a7 | 633 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 | 634 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
5c6a0628 | 635 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d | 636 | gen_cc_clear_icc(); |
ba28189b | 637 | gen_cc_NZ_icc(cpu_cc_dst); |
6f551262 | 638 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
ba28189b | 639 | gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d BS |
640 | #ifdef TARGET_SPARC64 |
641 | gen_cc_clear_xcc(); | |
ba28189b | 642 | gen_cc_NZ_xcc(cpu_cc_dst); |
6f551262 | 643 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
ba28189b | 644 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d | 645 | #endif |
5c6a0628 | 646 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
dc99a3f2 BS |
647 | } |
648 | ||
4af984a7 | 649 | static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 650 | { |
4af984a7 | 651 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 | 652 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
dc99a3f2 | 653 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
5c6a0628 | 654 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
ce5b3c3d | 655 | gen_cc_clear_icc(); |
5c6a0628 | 656 | gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); |
ce5b3c3d BS |
657 | #ifdef TARGET_SPARC64 |
658 | gen_cc_clear_xcc(); | |
5c6a0628 | 659 | gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); |
ce5b3c3d | 660 | #endif |
5c6a0628 | 661 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); |
ba28189b BS |
662 | gen_cc_NZ_icc(cpu_cc_dst); |
663 | gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); | |
664 | gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 665 | #ifdef TARGET_SPARC64 |
ba28189b BS |
666 | gen_cc_NZ_xcc(cpu_cc_dst); |
667 | gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); | |
668 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 669 | #endif |
5c6a0628 | 670 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
dc99a3f2 BS |
671 | } |
672 | ||
4af984a7 | 673 | static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 674 | { |
4af984a7 | 675 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 | 676 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
5c6a0628 | 677 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d | 678 | gen_cc_clear_icc(); |
ba28189b | 679 | gen_cc_NZ_icc(cpu_cc_dst); |
6f551262 | 680 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
ba28189b | 681 | gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
6f551262 | 682 | gen_cc_V_tag(cpu_cc_src, cpu_cc_src2); |
ce5b3c3d BS |
683 | #ifdef TARGET_SPARC64 |
684 | gen_cc_clear_xcc(); | |
ba28189b | 685 | gen_cc_NZ_xcc(cpu_cc_dst); |
6f551262 | 686 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
ba28189b | 687 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d | 688 | #endif |
5c6a0628 | 689 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
dc99a3f2 BS |
690 | } |
691 | ||
4af984a7 | 692 | static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 693 | { |
4af984a7 | 694 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 BS |
695 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
696 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); | |
5c6a0628 BS |
697 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
698 | gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 699 | gen_cc_clear_icc(); |
ba28189b | 700 | gen_cc_NZ_icc(cpu_cc_dst); |
6f551262 | 701 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
ce5b3c3d BS |
702 | #ifdef TARGET_SPARC64 |
703 | gen_cc_clear_xcc(); | |
ba28189b | 704 | gen_cc_NZ_xcc(cpu_cc_dst); |
6f551262 | 705 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
ba28189b | 706 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d | 707 | #endif |
5c6a0628 | 708 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
dc99a3f2 BS |
709 | } |
710 | ||
4af984a7 | 711 | static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) |
d9bdab86 | 712 | { |
7127fe84 | 713 | TCGv r_temp, r_temp2; |
6f551262 | 714 | int l1; |
d9bdab86 BS |
715 | |
716 | l1 = gen_new_label(); | |
d9bdab86 | 717 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
7127fe84 | 718 | r_temp2 = tcg_temp_new(TCG_TYPE_I32); |
d9bdab86 BS |
719 | |
720 | /* old op: | |
721 | if (!(env->y & 1)) | |
722 | T1 = 0; | |
723 | */ | |
6f551262 | 724 | tcg_gen_mov_tl(cpu_cc_src, src1); |
7127fe84 BS |
725 | tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y)); |
726 | tcg_gen_trunc_tl_i32(r_temp2, r_temp); | |
727 | tcg_gen_andi_i32(r_temp2, r_temp2, 0x1); | |
4af984a7 | 728 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
cb63669a | 729 | tcg_gen_brcondi_i32(TCG_COND_NE, r_temp2, 0, l1); |
d9bdab86 | 730 | tcg_gen_movi_tl(cpu_cc_src2, 0); |
6f551262 | 731 | gen_set_label(l1); |
d9bdab86 BS |
732 | |
733 | // b2 = T0 & 1; | |
734 | // env->y = (b2 << 31) | (env->y >> 1); | |
6f551262 | 735 | tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src); |
7127fe84 BS |
736 | tcg_gen_andi_i32(r_temp2, r_temp2, 0x1); |
737 | tcg_gen_shli_i32(r_temp2, r_temp2, 31); | |
8911f501 BS |
738 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y)); |
739 | tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1); | |
7127fe84 | 740 | tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2); |
2ea815ca | 741 | tcg_temp_free(r_temp2); |
8911f501 | 742 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y)); |
d9bdab86 BS |
743 | |
744 | // b1 = N ^ V; | |
745 | gen_mov_reg_N(cpu_tmp0, cpu_psr); | |
746 | gen_mov_reg_V(r_temp, cpu_psr); | |
747 | tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp); | |
2ea815ca | 748 | tcg_temp_free(r_temp); |
d9bdab86 BS |
749 | |
750 | // T0 = (b1 << 31) | (T0 >> 1); | |
751 | // src1 = T0; | |
752 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31); | |
6f551262 | 753 | tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1); |
d9bdab86 BS |
754 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); |
755 | ||
756 | /* do addition and update flags */ | |
5c6a0628 | 757 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
d9bdab86 | 758 | |
ce5b3c3d | 759 | gen_cc_clear_icc(); |
ba28189b BS |
760 | gen_cc_NZ_icc(cpu_cc_dst); |
761 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
762 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); | |
5c6a0628 | 763 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
d9bdab86 BS |
764 | } |
765 | ||
4af984a7 | 766 | static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) |
8879d139 BS |
767 | { |
768 | TCGv r_temp, r_temp2; | |
769 | ||
770 | r_temp = tcg_temp_new(TCG_TYPE_I64); | |
771 | r_temp2 = tcg_temp_new(TCG_TYPE_I64); | |
772 | ||
4af984a7 BS |
773 | tcg_gen_extu_tl_i64(r_temp, src2); |
774 | tcg_gen_extu_tl_i64(r_temp2, src1); | |
8879d139 BS |
775 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
776 | ||
777 | tcg_gen_shri_i64(r_temp, r_temp2, 32); | |
778 | tcg_gen_trunc_i64_i32(r_temp, r_temp); | |
779 | tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); | |
2ea815ca | 780 | tcg_temp_free(r_temp); |
8879d139 | 781 | #ifdef TARGET_SPARC64 |
4af984a7 | 782 | tcg_gen_mov_i64(dst, r_temp2); |
8879d139 | 783 | #else |
4af984a7 | 784 | tcg_gen_trunc_i64_tl(dst, r_temp2); |
8879d139 | 785 | #endif |
2ea815ca | 786 | tcg_temp_free(r_temp2); |
8879d139 BS |
787 | } |
788 | ||
4af984a7 | 789 | static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) |
8879d139 BS |
790 | { |
791 | TCGv r_temp, r_temp2; | |
792 | ||
793 | r_temp = tcg_temp_new(TCG_TYPE_I64); | |
794 | r_temp2 = tcg_temp_new(TCG_TYPE_I64); | |
795 | ||
4af984a7 BS |
796 | tcg_gen_ext_tl_i64(r_temp, src2); |
797 | tcg_gen_ext_tl_i64(r_temp2, src1); | |
8879d139 BS |
798 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
799 | ||
800 | tcg_gen_shri_i64(r_temp, r_temp2, 32); | |
801 | tcg_gen_trunc_i64_i32(r_temp, r_temp); | |
802 | tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); | |
2ea815ca | 803 | tcg_temp_free(r_temp); |
8879d139 | 804 | #ifdef TARGET_SPARC64 |
4af984a7 | 805 | tcg_gen_mov_i64(dst, r_temp2); |
8879d139 | 806 | #else |
4af984a7 | 807 | tcg_gen_trunc_i64_tl(dst, r_temp2); |
8879d139 | 808 | #endif |
2ea815ca | 809 | tcg_temp_free(r_temp2); |
8879d139 BS |
810 | } |
811 | ||
1a7b60e7 | 812 | #ifdef TARGET_SPARC64 |
8911f501 | 813 | static inline void gen_trap_ifdivzero_tl(TCGv divisor) |
1a7b60e7 | 814 | { |
2ea815ca | 815 | TCGv r_const; |
1a7b60e7 BS |
816 | int l1; |
817 | ||
818 | l1 = gen_new_label(); | |
cb63669a | 819 | tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1); |
2ea815ca BS |
820 | r_const = tcg_const_i32(TT_DIV_ZERO); |
821 | tcg_gen_helper_0_1(raise_exception, r_const); | |
822 | tcg_temp_free(r_const); | |
1a7b60e7 BS |
823 | gen_set_label(l1); |
824 | } | |
825 | ||
4af984a7 | 826 | static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2) |
1a7b60e7 BS |
827 | { |
828 | int l1, l2; | |
829 | ||
830 | l1 = gen_new_label(); | |
831 | l2 = gen_new_label(); | |
6f551262 BS |
832 | tcg_gen_mov_tl(cpu_cc_src, src1); |
833 | tcg_gen_mov_tl(cpu_cc_src2, src2); | |
5c6a0628 | 834 | gen_trap_ifdivzero_tl(cpu_cc_src2); |
cb63669a PB |
835 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1); |
836 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1); | |
4af984a7 | 837 | tcg_gen_movi_i64(dst, INT64_MIN); |
06b3e1b3 | 838 | tcg_gen_br(l2); |
1a7b60e7 | 839 | gen_set_label(l1); |
6f551262 | 840 | tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2); |
1a7b60e7 BS |
841 | gen_set_label(l2); |
842 | } | |
843 | #endif | |
844 | ||
4af984a7 | 845 | static inline void gen_op_div_cc(TCGv dst) |
dc99a3f2 BS |
846 | { |
847 | int l1; | |
dc99a3f2 | 848 | |
ba28189b | 849 | tcg_gen_mov_tl(cpu_cc_dst, dst); |
ce5b3c3d | 850 | gen_cc_clear_icc(); |
ba28189b | 851 | gen_cc_NZ_icc(cpu_cc_dst); |
dc99a3f2 | 852 | l1 = gen_new_label(); |
5c6a0628 | 853 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1); |
dc99a3f2 BS |
854 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
855 | gen_set_label(l1); | |
856 | } | |
857 | ||
4af984a7 | 858 | static inline void gen_op_logic_cc(TCGv dst) |
dc99a3f2 | 859 | { |
ba28189b BS |
860 | tcg_gen_mov_tl(cpu_cc_dst, dst); |
861 | ||
ce5b3c3d | 862 | gen_cc_clear_icc(); |
ba28189b | 863 | gen_cc_NZ_icc(cpu_cc_dst); |
ce5b3c3d BS |
864 | #ifdef TARGET_SPARC64 |
865 | gen_cc_clear_xcc(); | |
ba28189b | 866 | gen_cc_NZ_xcc(cpu_cc_dst); |
ce5b3c3d | 867 | #endif |
dc99a3f2 BS |
868 | } |
869 | ||
19f329ad BS |
870 | // 1 |
871 | static inline void gen_op_eval_ba(TCGv dst) | |
872 | { | |
873 | tcg_gen_movi_tl(dst, 1); | |
874 | } | |
875 | ||
876 | // Z | |
877 | static inline void gen_op_eval_be(TCGv dst, TCGv src) | |
878 | { | |
879 | gen_mov_reg_Z(dst, src); | |
880 | } | |
881 | ||
882 | // Z | (N ^ V) | |
883 | static inline void gen_op_eval_ble(TCGv dst, TCGv src) | |
884 | { | |
0425bee5 | 885 | gen_mov_reg_N(cpu_tmp0, src); |
19f329ad | 886 | gen_mov_reg_V(dst, src); |
0425bee5 BS |
887 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
888 | gen_mov_reg_Z(cpu_tmp0, src); | |
889 | tcg_gen_or_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
890 | } |
891 | ||
892 | // N ^ V | |
893 | static inline void gen_op_eval_bl(TCGv dst, TCGv src) | |
894 | { | |
0425bee5 | 895 | gen_mov_reg_V(cpu_tmp0, src); |
19f329ad | 896 | gen_mov_reg_N(dst, src); |
0425bee5 | 897 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
19f329ad BS |
898 | } |
899 | ||
900 | // C | Z | |
901 | static inline void gen_op_eval_bleu(TCGv dst, TCGv src) | |
902 | { | |
0425bee5 | 903 | gen_mov_reg_Z(cpu_tmp0, src); |
19f329ad | 904 | gen_mov_reg_C(dst, src); |
0425bee5 | 905 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
19f329ad BS |
906 | } |
907 | ||
908 | // C | |
909 | static inline void gen_op_eval_bcs(TCGv dst, TCGv src) | |
910 | { | |
911 | gen_mov_reg_C(dst, src); | |
912 | } | |
913 | ||
914 | // V | |
915 | static inline void gen_op_eval_bvs(TCGv dst, TCGv src) | |
916 | { | |
917 | gen_mov_reg_V(dst, src); | |
918 | } | |
919 | ||
920 | // 0 | |
921 | static inline void gen_op_eval_bn(TCGv dst) | |
922 | { | |
923 | tcg_gen_movi_tl(dst, 0); | |
924 | } | |
925 | ||
926 | // N | |
927 | static inline void gen_op_eval_bneg(TCGv dst, TCGv src) | |
928 | { | |
929 | gen_mov_reg_N(dst, src); | |
930 | } | |
931 | ||
932 | // !Z | |
933 | static inline void gen_op_eval_bne(TCGv dst, TCGv src) | |
934 | { | |
935 | gen_mov_reg_Z(dst, src); | |
936 | tcg_gen_xori_tl(dst, dst, 0x1); | |
937 | } | |
938 | ||
939 | // !(Z | (N ^ V)) | |
940 | static inline void gen_op_eval_bg(TCGv dst, TCGv src) | |
941 | { | |
0425bee5 | 942 | gen_mov_reg_N(cpu_tmp0, src); |
19f329ad | 943 | gen_mov_reg_V(dst, src); |
0425bee5 BS |
944 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
945 | gen_mov_reg_Z(cpu_tmp0, src); | |
946 | tcg_gen_or_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
947 | tcg_gen_xori_tl(dst, dst, 0x1); |
948 | } | |
949 | ||
950 | // !(N ^ V) | |
951 | static inline void gen_op_eval_bge(TCGv dst, TCGv src) | |
952 | { | |
0425bee5 | 953 | gen_mov_reg_V(cpu_tmp0, src); |
19f329ad | 954 | gen_mov_reg_N(dst, src); |
0425bee5 | 955 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
19f329ad BS |
956 | tcg_gen_xori_tl(dst, dst, 0x1); |
957 | } | |
958 | ||
959 | // !(C | Z) | |
960 | static inline void gen_op_eval_bgu(TCGv dst, TCGv src) | |
961 | { | |
0425bee5 | 962 | gen_mov_reg_Z(cpu_tmp0, src); |
19f329ad | 963 | gen_mov_reg_C(dst, src); |
0425bee5 | 964 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
19f329ad BS |
965 | tcg_gen_xori_tl(dst, dst, 0x1); |
966 | } | |
967 | ||
968 | // !C | |
969 | static inline void gen_op_eval_bcc(TCGv dst, TCGv src) | |
970 | { | |
971 | gen_mov_reg_C(dst, src); | |
972 | tcg_gen_xori_tl(dst, dst, 0x1); | |
973 | } | |
974 | ||
975 | // !N | |
976 | static inline void gen_op_eval_bpos(TCGv dst, TCGv src) | |
977 | { | |
978 | gen_mov_reg_N(dst, src); | |
979 | tcg_gen_xori_tl(dst, dst, 0x1); | |
980 | } | |
981 | ||
982 | // !V | |
983 | static inline void gen_op_eval_bvc(TCGv dst, TCGv src) | |
984 | { | |
985 | gen_mov_reg_V(dst, src); | |
986 | tcg_gen_xori_tl(dst, dst, 0x1); | |
987 | } | |
988 | ||
989 | /* | |
990 | FPSR bit field FCC1 | FCC0: | |
991 | 0 = | |
992 | 1 < | |
993 | 2 > | |
994 | 3 unordered | |
995 | */ | |
996 | static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, | |
997 | unsigned int fcc_offset) | |
998 | { | |
8911f501 | 999 | tcg_gen_extu_i32_tl(reg, src); |
4b8b8b76 | 1000 | tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset); |
19f329ad BS |
1001 | tcg_gen_andi_tl(reg, reg, 0x1); |
1002 | } | |
1003 | ||
1004 | static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, | |
1005 | unsigned int fcc_offset) | |
1006 | { | |
8911f501 | 1007 | tcg_gen_extu_i32_tl(reg, src); |
4b8b8b76 | 1008 | tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset); |
19f329ad BS |
1009 | tcg_gen_andi_tl(reg, reg, 0x1); |
1010 | } | |
1011 | ||
1012 | // !0: FCC0 | FCC1 | |
1013 | static inline void gen_op_eval_fbne(TCGv dst, TCGv src, | |
1014 | unsigned int fcc_offset) | |
1015 | { | |
19f329ad | 1016 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1017 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1018 | tcg_gen_or_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1019 | } |
1020 | ||
1021 | // 1 or 2: FCC0 ^ FCC1 | |
1022 | static inline void gen_op_eval_fblg(TCGv dst, TCGv src, | |
1023 | unsigned int fcc_offset) | |
1024 | { | |
19f329ad | 1025 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1026 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1027 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1028 | } |
1029 | ||
1030 | // 1 or 3: FCC0 | |
1031 | static inline void gen_op_eval_fbul(TCGv dst, TCGv src, | |
1032 | unsigned int fcc_offset) | |
1033 | { | |
1034 | gen_mov_reg_FCC0(dst, src, fcc_offset); | |
1035 | } | |
1036 | ||
1037 | // 1: FCC0 & !FCC1 | |
1038 | static inline void gen_op_eval_fbl(TCGv dst, TCGv src, | |
1039 | unsigned int fcc_offset) | |
1040 | { | |
19f329ad | 1041 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1042 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1043 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1); | |
1044 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1045 | } |
1046 | ||
1047 | // 2 or 3: FCC1 | |
1048 | static inline void gen_op_eval_fbug(TCGv dst, TCGv src, | |
1049 | unsigned int fcc_offset) | |
1050 | { | |
1051 | gen_mov_reg_FCC1(dst, src, fcc_offset); | |
1052 | } | |
1053 | ||
1054 | // 2: !FCC0 & FCC1 | |
1055 | static inline void gen_op_eval_fbg(TCGv dst, TCGv src, | |
1056 | unsigned int fcc_offset) | |
1057 | { | |
19f329ad BS |
1058 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1059 | tcg_gen_xori_tl(dst, dst, 0x1); | |
0425bee5 BS |
1060 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1061 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1062 | } |
1063 | ||
1064 | // 3: FCC0 & FCC1 | |
1065 | static inline void gen_op_eval_fbu(TCGv dst, TCGv src, | |
1066 | unsigned int fcc_offset) | |
1067 | { | |
19f329ad | 1068 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1069 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1070 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1071 | } |
1072 | ||
1073 | // 0: !(FCC0 | FCC1) | |
1074 | static inline void gen_op_eval_fbe(TCGv dst, TCGv src, | |
1075 | unsigned int fcc_offset) | |
1076 | { | |
19f329ad | 1077 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1078 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1079 | tcg_gen_or_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1080 | tcg_gen_xori_tl(dst, dst, 0x1); |
1081 | } | |
1082 | ||
1083 | // 0 or 3: !(FCC0 ^ FCC1) | |
1084 | static inline void gen_op_eval_fbue(TCGv dst, TCGv src, | |
1085 | unsigned int fcc_offset) | |
1086 | { | |
19f329ad | 1087 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1088 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1089 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1090 | tcg_gen_xori_tl(dst, dst, 0x1); |
1091 | } | |
1092 | ||
1093 | // 0 or 2: !FCC0 | |
1094 | static inline void gen_op_eval_fbge(TCGv dst, TCGv src, | |
1095 | unsigned int fcc_offset) | |
1096 | { | |
1097 | gen_mov_reg_FCC0(dst, src, fcc_offset); | |
1098 | tcg_gen_xori_tl(dst, dst, 0x1); | |
1099 | } | |
1100 | ||
1101 | // !1: !(FCC0 & !FCC1) | |
1102 | static inline void gen_op_eval_fbuge(TCGv dst, TCGv src, | |
1103 | unsigned int fcc_offset) | |
1104 | { | |
19f329ad | 1105 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1106 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1107 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1); | |
1108 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1109 | tcg_gen_xori_tl(dst, dst, 0x1); |
1110 | } | |
1111 | ||
1112 | // 0 or 1: !FCC1 | |
1113 | static inline void gen_op_eval_fble(TCGv dst, TCGv src, | |
1114 | unsigned int fcc_offset) | |
1115 | { | |
1116 | gen_mov_reg_FCC1(dst, src, fcc_offset); | |
1117 | tcg_gen_xori_tl(dst, dst, 0x1); | |
1118 | } | |
1119 | ||
1120 | // !2: !(!FCC0 & FCC1) | |
1121 | static inline void gen_op_eval_fbule(TCGv dst, TCGv src, | |
1122 | unsigned int fcc_offset) | |
1123 | { | |
19f329ad BS |
1124 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1125 | tcg_gen_xori_tl(dst, dst, 0x1); | |
0425bee5 BS |
1126 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1127 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1128 | tcg_gen_xori_tl(dst, dst, 0x1); |
1129 | } | |
1130 | ||
1131 | // !3: !(FCC0 & FCC1) | |
1132 | static inline void gen_op_eval_fbo(TCGv dst, TCGv src, | |
1133 | unsigned int fcc_offset) | |
1134 | { | |
19f329ad | 1135 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1136 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1137 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1138 | tcg_gen_xori_tl(dst, dst, 0x1); |
1139 | } | |
1140 | ||
46525e1f | 1141 | static inline void gen_branch2(DisasContext *dc, target_ulong pc1, |
19f329ad | 1142 | target_ulong pc2, TCGv r_cond) |
83469015 FB |
1143 | { |
1144 | int l1; | |
1145 | ||
1146 | l1 = gen_new_label(); | |
1147 | ||
cb63669a | 1148 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1); |
83469015 | 1149 | |
6e256c93 | 1150 | gen_goto_tb(dc, 0, pc1, pc1 + 4); |
83469015 FB |
1151 | |
1152 | gen_set_label(l1); | |
6e256c93 | 1153 | gen_goto_tb(dc, 1, pc2, pc2 + 4); |
83469015 FB |
1154 | } |
1155 | ||
46525e1f | 1156 | static inline void gen_branch_a(DisasContext *dc, target_ulong pc1, |
19f329ad | 1157 | target_ulong pc2, TCGv r_cond) |
83469015 FB |
1158 | { |
1159 | int l1; | |
1160 | ||
1161 | l1 = gen_new_label(); | |
1162 | ||
cb63669a | 1163 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1); |
83469015 | 1164 | |
6e256c93 | 1165 | gen_goto_tb(dc, 0, pc2, pc1); |
83469015 FB |
1166 | |
1167 | gen_set_label(l1); | |
6e256c93 | 1168 | gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8); |
83469015 FB |
1169 | } |
1170 | ||
19f329ad BS |
1171 | static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2, |
1172 | TCGv r_cond) | |
83469015 FB |
1173 | { |
1174 | int l1, l2; | |
1175 | ||
1176 | l1 = gen_new_label(); | |
1177 | l2 = gen_new_label(); | |
19f329ad | 1178 | |
cb63669a | 1179 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1); |
83469015 | 1180 | |
2f5680ee | 1181 | tcg_gen_movi_tl(cpu_npc, npc1); |
06b3e1b3 | 1182 | tcg_gen_br(l2); |
83469015 FB |
1183 | |
1184 | gen_set_label(l1); | |
2f5680ee | 1185 | tcg_gen_movi_tl(cpu_npc, npc2); |
83469015 FB |
1186 | gen_set_label(l2); |
1187 | } | |
1188 | ||
4af984a7 BS |
1189 | /* call this function before using the condition register as it may |
1190 | have been set for a jump */ | |
1191 | static inline void flush_cond(DisasContext *dc, TCGv cond) | |
83469015 FB |
1192 | { |
1193 | if (dc->npc == JUMP_PC) { | |
4af984a7 | 1194 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
83469015 FB |
1195 | dc->npc = DYNAMIC_PC; |
1196 | } | |
1197 | } | |
1198 | ||
4af984a7 | 1199 | static inline void save_npc(DisasContext *dc, TCGv cond) |
72cbca10 FB |
1200 | { |
1201 | if (dc->npc == JUMP_PC) { | |
4af984a7 | 1202 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
72cbca10 FB |
1203 | dc->npc = DYNAMIC_PC; |
1204 | } else if (dc->npc != DYNAMIC_PC) { | |
2f5680ee | 1205 | tcg_gen_movi_tl(cpu_npc, dc->npc); |
72cbca10 FB |
1206 | } |
1207 | } | |
1208 | ||
4af984a7 | 1209 | static inline void save_state(DisasContext *dc, TCGv cond) |
72cbca10 | 1210 | { |
2f5680ee | 1211 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
4af984a7 | 1212 | save_npc(dc, cond); |
72cbca10 FB |
1213 | } |
1214 | ||
4af984a7 | 1215 | static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond) |
0bee699e FB |
1216 | { |
1217 | if (dc->npc == JUMP_PC) { | |
4af984a7 | 1218 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
48d5c82b | 1219 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
0bee699e FB |
1220 | dc->pc = DYNAMIC_PC; |
1221 | } else if (dc->npc == DYNAMIC_PC) { | |
48d5c82b | 1222 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
0bee699e FB |
1223 | dc->pc = DYNAMIC_PC; |
1224 | } else { | |
1225 | dc->pc = dc->npc; | |
1226 | } | |
1227 | } | |
1228 | ||
38bc628b BS |
1229 | static inline void gen_op_next_insn(void) |
1230 | { | |
48d5c82b BS |
1231 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1232 | tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); | |
38bc628b BS |
1233 | } |
1234 | ||
19f329ad BS |
1235 | static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond) |
1236 | { | |
1237 | TCGv r_src; | |
3475187d | 1238 | |
3475187d | 1239 | #ifdef TARGET_SPARC64 |
19f329ad | 1240 | if (cc) |
dc99a3f2 | 1241 | r_src = cpu_xcc; |
19f329ad | 1242 | else |
dc99a3f2 | 1243 | r_src = cpu_psr; |
3475187d | 1244 | #else |
dc99a3f2 | 1245 | r_src = cpu_psr; |
3475187d | 1246 | #endif |
19f329ad BS |
1247 | switch (cond) { |
1248 | case 0x0: | |
1249 | gen_op_eval_bn(r_dst); | |
1250 | break; | |
1251 | case 0x1: | |
1252 | gen_op_eval_be(r_dst, r_src); | |
1253 | break; | |
1254 | case 0x2: | |
1255 | gen_op_eval_ble(r_dst, r_src); | |
1256 | break; | |
1257 | case 0x3: | |
1258 | gen_op_eval_bl(r_dst, r_src); | |
1259 | break; | |
1260 | case 0x4: | |
1261 | gen_op_eval_bleu(r_dst, r_src); | |
1262 | break; | |
1263 | case 0x5: | |
1264 | gen_op_eval_bcs(r_dst, r_src); | |
1265 | break; | |
1266 | case 0x6: | |
1267 | gen_op_eval_bneg(r_dst, r_src); | |
1268 | break; | |
1269 | case 0x7: | |
1270 | gen_op_eval_bvs(r_dst, r_src); | |
1271 | break; | |
1272 | case 0x8: | |
1273 | gen_op_eval_ba(r_dst); | |
1274 | break; | |
1275 | case 0x9: | |
1276 | gen_op_eval_bne(r_dst, r_src); | |
1277 | break; | |
1278 | case 0xa: | |
1279 | gen_op_eval_bg(r_dst, r_src); | |
1280 | break; | |
1281 | case 0xb: | |
1282 | gen_op_eval_bge(r_dst, r_src); | |
1283 | break; | |
1284 | case 0xc: | |
1285 | gen_op_eval_bgu(r_dst, r_src); | |
1286 | break; | |
1287 | case 0xd: | |
1288 | gen_op_eval_bcc(r_dst, r_src); | |
1289 | break; | |
1290 | case 0xe: | |
1291 | gen_op_eval_bpos(r_dst, r_src); | |
1292 | break; | |
1293 | case 0xf: | |
1294 | gen_op_eval_bvc(r_dst, r_src); | |
1295 | break; | |
1296 | } | |
1297 | } | |
7a3f1944 | 1298 | |
19f329ad | 1299 | static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) |
e8af50a3 | 1300 | { |
19f329ad BS |
1301 | unsigned int offset; |
1302 | ||
19f329ad BS |
1303 | switch (cc) { |
1304 | default: | |
1305 | case 0x0: | |
1306 | offset = 0; | |
1307 | break; | |
1308 | case 0x1: | |
1309 | offset = 32 - 10; | |
1310 | break; | |
1311 | case 0x2: | |
1312 | offset = 34 - 10; | |
1313 | break; | |
1314 | case 0x3: | |
1315 | offset = 36 - 10; | |
1316 | break; | |
1317 | } | |
1318 | ||
1319 | switch (cond) { | |
1320 | case 0x0: | |
1321 | gen_op_eval_bn(r_dst); | |
1322 | break; | |
1323 | case 0x1: | |
87e92502 | 1324 | gen_op_eval_fbne(r_dst, cpu_fsr, offset); |
19f329ad BS |
1325 | break; |
1326 | case 0x2: | |
87e92502 | 1327 | gen_op_eval_fblg(r_dst, cpu_fsr, offset); |
19f329ad BS |
1328 | break; |
1329 | case 0x3: | |
87e92502 | 1330 | gen_op_eval_fbul(r_dst, cpu_fsr, offset); |
19f329ad BS |
1331 | break; |
1332 | case 0x4: | |
87e92502 | 1333 | gen_op_eval_fbl(r_dst, cpu_fsr, offset); |
19f329ad BS |
1334 | break; |
1335 | case 0x5: | |
87e92502 | 1336 | gen_op_eval_fbug(r_dst, cpu_fsr, offset); |
19f329ad BS |
1337 | break; |
1338 | case 0x6: | |
87e92502 | 1339 | gen_op_eval_fbg(r_dst, cpu_fsr, offset); |
19f329ad BS |
1340 | break; |
1341 | case 0x7: | |
87e92502 | 1342 | gen_op_eval_fbu(r_dst, cpu_fsr, offset); |
19f329ad BS |
1343 | break; |
1344 | case 0x8: | |
1345 | gen_op_eval_ba(r_dst); | |
1346 | break; | |
1347 | case 0x9: | |
87e92502 | 1348 | gen_op_eval_fbe(r_dst, cpu_fsr, offset); |
19f329ad BS |
1349 | break; |
1350 | case 0xa: | |
87e92502 | 1351 | gen_op_eval_fbue(r_dst, cpu_fsr, offset); |
19f329ad BS |
1352 | break; |
1353 | case 0xb: | |
87e92502 | 1354 | gen_op_eval_fbge(r_dst, cpu_fsr, offset); |
19f329ad BS |
1355 | break; |
1356 | case 0xc: | |
87e92502 | 1357 | gen_op_eval_fbuge(r_dst, cpu_fsr, offset); |
19f329ad BS |
1358 | break; |
1359 | case 0xd: | |
87e92502 | 1360 | gen_op_eval_fble(r_dst, cpu_fsr, offset); |
19f329ad BS |
1361 | break; |
1362 | case 0xe: | |
87e92502 | 1363 | gen_op_eval_fbule(r_dst, cpu_fsr, offset); |
19f329ad BS |
1364 | break; |
1365 | case 0xf: | |
87e92502 | 1366 | gen_op_eval_fbo(r_dst, cpu_fsr, offset); |
19f329ad BS |
1367 | break; |
1368 | } | |
e8af50a3 | 1369 | } |
00f219bf | 1370 | |
19f329ad | 1371 | #ifdef TARGET_SPARC64 |
00f219bf BS |
1372 | // Inverted logic |
1373 | static const int gen_tcg_cond_reg[8] = { | |
1374 | -1, | |
1375 | TCG_COND_NE, | |
1376 | TCG_COND_GT, | |
1377 | TCG_COND_GE, | |
1378 | -1, | |
1379 | TCG_COND_EQ, | |
1380 | TCG_COND_LE, | |
1381 | TCG_COND_LT, | |
1382 | }; | |
19f329ad | 1383 | |
4af984a7 | 1384 | static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src) |
19f329ad | 1385 | { |
19f329ad BS |
1386 | int l1; |
1387 | ||
1388 | l1 = gen_new_label(); | |
0425bee5 | 1389 | tcg_gen_movi_tl(r_dst, 0); |
cb63669a | 1390 | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1); |
19f329ad BS |
1391 | tcg_gen_movi_tl(r_dst, 1); |
1392 | gen_set_label(l1); | |
1393 | } | |
3475187d | 1394 | #endif |
cf495bcf | 1395 | |
0bee699e | 1396 | /* XXX: potentially incorrect if dynamic npc */ |
4af984a7 BS |
1397 | static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc, |
1398 | TCGv r_cond) | |
7a3f1944 | 1399 | { |
cf495bcf | 1400 | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
af7bf89b | 1401 | target_ulong target = dc->pc + offset; |
5fafdf24 | 1402 | |
cf495bcf | 1403 | if (cond == 0x0) { |
0f8a249a BS |
1404 | /* unconditional not taken */ |
1405 | if (a) { | |
1406 | dc->pc = dc->npc + 4; | |
1407 | dc->npc = dc->pc + 4; | |
1408 | } else { | |
1409 | dc->pc = dc->npc; | |
1410 | dc->npc = dc->pc + 4; | |
1411 | } | |
cf495bcf | 1412 | } else if (cond == 0x8) { |
0f8a249a BS |
1413 | /* unconditional taken */ |
1414 | if (a) { | |
1415 | dc->pc = target; | |
1416 | dc->npc = dc->pc + 4; | |
1417 | } else { | |
1418 | dc->pc = dc->npc; | |
1419 | dc->npc = target; | |
1420 | } | |
cf495bcf | 1421 | } else { |
4af984a7 BS |
1422 | flush_cond(dc, r_cond); |
1423 | gen_cond(r_cond, cc, cond); | |
0f8a249a | 1424 | if (a) { |
4af984a7 | 1425 | gen_branch_a(dc, target, dc->npc, r_cond); |
cf495bcf | 1426 | dc->is_br = 1; |
0f8a249a | 1427 | } else { |
cf495bcf | 1428 | dc->pc = dc->npc; |
72cbca10 FB |
1429 | dc->jump_pc[0] = target; |
1430 | dc->jump_pc[1] = dc->npc + 4; | |
1431 | dc->npc = JUMP_PC; | |
0f8a249a | 1432 | } |
cf495bcf | 1433 | } |
7a3f1944 FB |
1434 | } |
1435 | ||
0bee699e | 1436 | /* XXX: potentially incorrect if dynamic npc */ |
4af984a7 BS |
1437 | static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc, |
1438 | TCGv r_cond) | |
e8af50a3 FB |
1439 | { |
1440 | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); | |
af7bf89b FB |
1441 | target_ulong target = dc->pc + offset; |
1442 | ||
e8af50a3 | 1443 | if (cond == 0x0) { |
0f8a249a BS |
1444 | /* unconditional not taken */ |
1445 | if (a) { | |
1446 | dc->pc = dc->npc + 4; | |
1447 | dc->npc = dc->pc + 4; | |
1448 | } else { | |
1449 | dc->pc = dc->npc; | |
1450 | dc->npc = dc->pc + 4; | |
1451 | } | |
e8af50a3 | 1452 | } else if (cond == 0x8) { |
0f8a249a BS |
1453 | /* unconditional taken */ |
1454 | if (a) { | |
1455 | dc->pc = target; | |
1456 | dc->npc = dc->pc + 4; | |
1457 | } else { | |
1458 | dc->pc = dc->npc; | |
1459 | dc->npc = target; | |
1460 | } | |
e8af50a3 | 1461 | } else { |
4af984a7 BS |
1462 | flush_cond(dc, r_cond); |
1463 | gen_fcond(r_cond, cc, cond); | |
0f8a249a | 1464 | if (a) { |
4af984a7 | 1465 | gen_branch_a(dc, target, dc->npc, r_cond); |
e8af50a3 | 1466 | dc->is_br = 1; |
0f8a249a | 1467 | } else { |
e8af50a3 FB |
1468 | dc->pc = dc->npc; |
1469 | dc->jump_pc[0] = target; | |
1470 | dc->jump_pc[1] = dc->npc + 4; | |
1471 | dc->npc = JUMP_PC; | |
0f8a249a | 1472 | } |
e8af50a3 FB |
1473 | } |
1474 | } | |
1475 | ||
3475187d FB |
1476 | #ifdef TARGET_SPARC64 |
1477 | /* XXX: potentially incorrect if dynamic npc */ | |
4af984a7 BS |
1478 | static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn, |
1479 | TCGv r_cond, TCGv r_reg) | |
7a3f1944 | 1480 | { |
3475187d FB |
1481 | unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); |
1482 | target_ulong target = dc->pc + offset; | |
1483 | ||
4af984a7 BS |
1484 | flush_cond(dc, r_cond); |
1485 | gen_cond_reg(r_cond, cond, r_reg); | |
3475187d | 1486 | if (a) { |
4af984a7 | 1487 | gen_branch_a(dc, target, dc->npc, r_cond); |
0f8a249a | 1488 | dc->is_br = 1; |
3475187d | 1489 | } else { |
0f8a249a BS |
1490 | dc->pc = dc->npc; |
1491 | dc->jump_pc[0] = target; | |
1492 | dc->jump_pc[1] = dc->npc + 4; | |
1493 | dc->npc = JUMP_PC; | |
3475187d | 1494 | } |
7a3f1944 FB |
1495 | } |
1496 | ||
3475187d | 1497 | static GenOpFunc * const gen_fcmps[4] = { |
7e8c2b6c BS |
1498 | helper_fcmps, |
1499 | helper_fcmps_fcc1, | |
1500 | helper_fcmps_fcc2, | |
1501 | helper_fcmps_fcc3, | |
3475187d FB |
1502 | }; |
1503 | ||
1504 | static GenOpFunc * const gen_fcmpd[4] = { | |
7e8c2b6c BS |
1505 | helper_fcmpd, |
1506 | helper_fcmpd_fcc1, | |
1507 | helper_fcmpd_fcc2, | |
1508 | helper_fcmpd_fcc3, | |
3475187d | 1509 | }; |
417454b0 | 1510 | |
1f587329 | 1511 | static GenOpFunc * const gen_fcmpq[4] = { |
7e8c2b6c BS |
1512 | helper_fcmpq, |
1513 | helper_fcmpq_fcc1, | |
1514 | helper_fcmpq_fcc2, | |
1515 | helper_fcmpq_fcc3, | |
1f587329 | 1516 | }; |
1f587329 | 1517 | |
417454b0 | 1518 | static GenOpFunc * const gen_fcmpes[4] = { |
7e8c2b6c BS |
1519 | helper_fcmpes, |
1520 | helper_fcmpes_fcc1, | |
1521 | helper_fcmpes_fcc2, | |
1522 | helper_fcmpes_fcc3, | |
417454b0 BS |
1523 | }; |
1524 | ||
1525 | static GenOpFunc * const gen_fcmped[4] = { | |
7e8c2b6c BS |
1526 | helper_fcmped, |
1527 | helper_fcmped_fcc1, | |
1528 | helper_fcmped_fcc2, | |
1529 | helper_fcmped_fcc3, | |
417454b0 BS |
1530 | }; |
1531 | ||
1f587329 | 1532 | static GenOpFunc * const gen_fcmpeq[4] = { |
7e8c2b6c BS |
1533 | helper_fcmpeq, |
1534 | helper_fcmpeq_fcc1, | |
1535 | helper_fcmpeq_fcc2, | |
1536 | helper_fcmpeq_fcc3, | |
1f587329 | 1537 | }; |
7e8c2b6c BS |
1538 | |
1539 | static inline void gen_op_fcmps(int fccno) | |
1540 | { | |
1541 | tcg_gen_helper_0_0(gen_fcmps[fccno]); | |
1542 | } | |
1543 | ||
1544 | static inline void gen_op_fcmpd(int fccno) | |
1545 | { | |
1546 | tcg_gen_helper_0_0(gen_fcmpd[fccno]); | |
1547 | } | |
1548 | ||
7e8c2b6c BS |
1549 | static inline void gen_op_fcmpq(int fccno) |
1550 | { | |
1551 | tcg_gen_helper_0_0(gen_fcmpq[fccno]); | |
1552 | } | |
7e8c2b6c BS |
1553 | |
1554 | static inline void gen_op_fcmpes(int fccno) | |
1555 | { | |
1556 | tcg_gen_helper_0_0(gen_fcmpes[fccno]); | |
1557 | } | |
1558 | ||
1559 | static inline void gen_op_fcmped(int fccno) | |
1560 | { | |
1561 | tcg_gen_helper_0_0(gen_fcmped[fccno]); | |
1562 | } | |
1563 | ||
7e8c2b6c BS |
1564 | static inline void gen_op_fcmpeq(int fccno) |
1565 | { | |
1566 | tcg_gen_helper_0_0(gen_fcmpeq[fccno]); | |
1567 | } | |
7e8c2b6c BS |
1568 | |
1569 | #else | |
1570 | ||
1571 | static inline void gen_op_fcmps(int fccno) | |
1572 | { | |
1573 | tcg_gen_helper_0_0(helper_fcmps); | |
1574 | } | |
1575 | ||
1576 | static inline void gen_op_fcmpd(int fccno) | |
1577 | { | |
1578 | tcg_gen_helper_0_0(helper_fcmpd); | |
1579 | } | |
1580 | ||
7e8c2b6c BS |
1581 | static inline void gen_op_fcmpq(int fccno) |
1582 | { | |
1583 | tcg_gen_helper_0_0(helper_fcmpq); | |
1584 | } | |
7e8c2b6c BS |
1585 | |
1586 | static inline void gen_op_fcmpes(int fccno) | |
1587 | { | |
1588 | tcg_gen_helper_0_0(helper_fcmpes); | |
1589 | } | |
1590 | ||
1591 | static inline void gen_op_fcmped(int fccno) | |
1592 | { | |
1593 | tcg_gen_helper_0_0(helper_fcmped); | |
1594 | } | |
1595 | ||
7e8c2b6c BS |
1596 | static inline void gen_op_fcmpeq(int fccno) |
1597 | { | |
1598 | tcg_gen_helper_0_0(helper_fcmpeq); | |
1599 | } | |
1600 | #endif | |
1601 | ||
134d77a1 BS |
1602 | static inline void gen_op_fpexception_im(int fsr_flags) |
1603 | { | |
2ea815ca BS |
1604 | TCGv r_const; |
1605 | ||
87e92502 BS |
1606 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK); |
1607 | tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); | |
2ea815ca BS |
1608 | r_const = tcg_const_i32(TT_FP_EXCP); |
1609 | tcg_gen_helper_0_1(raise_exception, r_const); | |
1610 | tcg_temp_free(r_const); | |
134d77a1 BS |
1611 | } |
1612 | ||
4af984a7 | 1613 | static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond) |
a80dde08 FB |
1614 | { |
1615 | #if !defined(CONFIG_USER_ONLY) | |
1616 | if (!dc->fpu_enabled) { | |
2ea815ca BS |
1617 | TCGv r_const; |
1618 | ||
4af984a7 | 1619 | save_state(dc, r_cond); |
2ea815ca BS |
1620 | r_const = tcg_const_i32(TT_NFPU_INSN); |
1621 | tcg_gen_helper_0_1(raise_exception, r_const); | |
1622 | tcg_temp_free(r_const); | |
a80dde08 FB |
1623 | dc->is_br = 1; |
1624 | return 1; | |
1625 | } | |
1626 | #endif | |
1627 | return 0; | |
1628 | } | |
1629 | ||
7e8c2b6c BS |
1630 | static inline void gen_op_clear_ieee_excp_and_FTT(void) |
1631 | { | |
87e92502 | 1632 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK)); |
7e8c2b6c BS |
1633 | } |
1634 | ||
1635 | static inline void gen_clear_float_exceptions(void) | |
1636 | { | |
1637 | tcg_gen_helper_0_0(helper_clear_float_exceptions); | |
1638 | } | |
1639 | ||
1a2fb1c0 BS |
1640 | /* asi moves */ |
1641 | #ifdef TARGET_SPARC64 | |
0425bee5 | 1642 | static inline TCGv gen_get_asi(int insn, TCGv r_addr) |
1a2fb1c0 BS |
1643 | { |
1644 | int asi, offset; | |
0425bee5 | 1645 | TCGv r_asi; |
1a2fb1c0 | 1646 | |
1a2fb1c0 | 1647 | if (IS_IMM) { |
0425bee5 | 1648 | r_asi = tcg_temp_new(TCG_TYPE_I32); |
1a2fb1c0 | 1649 | offset = GET_FIELD(insn, 25, 31); |
0425bee5 BS |
1650 | tcg_gen_addi_tl(r_addr, r_addr, offset); |
1651 | tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi)); | |
1a2fb1c0 BS |
1652 | } else { |
1653 | asi = GET_FIELD(insn, 19, 26); | |
0425bee5 | 1654 | r_asi = tcg_const_i32(asi); |
1a2fb1c0 | 1655 | } |
0425bee5 BS |
1656 | return r_asi; |
1657 | } | |
1658 | ||
77f193da BS |
1659 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
1660 | int sign) | |
0425bee5 | 1661 | { |
2ea815ca | 1662 | TCGv r_asi, r_size, r_sign; |
0425bee5 | 1663 | |
4af984a7 | 1664 | r_asi = gen_get_asi(insn, addr); |
2ea815ca BS |
1665 | r_size = tcg_const_i32(size); |
1666 | r_sign = tcg_const_i32(sign); | |
1667 | tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign); | |
1668 | tcg_temp_free(r_sign); | |
1669 | tcg_temp_free(r_size); | |
1670 | tcg_temp_free(r_asi); | |
1a2fb1c0 BS |
1671 | } |
1672 | ||
4af984a7 | 1673 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
1a2fb1c0 | 1674 | { |
2ea815ca | 1675 | TCGv r_asi, r_size; |
1a2fb1c0 | 1676 | |
4af984a7 | 1677 | r_asi = gen_get_asi(insn, addr); |
2ea815ca BS |
1678 | r_size = tcg_const_i32(size); |
1679 | tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size); | |
1680 | tcg_temp_free(r_size); | |
1681 | tcg_temp_free(r_asi); | |
1a2fb1c0 BS |
1682 | } |
1683 | ||
4af984a7 | 1684 | static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd) |
1a2fb1c0 | 1685 | { |
2ea815ca | 1686 | TCGv r_asi, r_size, r_rd; |
1a2fb1c0 | 1687 | |
4af984a7 | 1688 | r_asi = gen_get_asi(insn, addr); |
2ea815ca BS |
1689 | r_size = tcg_const_i32(size); |
1690 | r_rd = tcg_const_i32(rd); | |
1691 | tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd); | |
1692 | tcg_temp_free(r_rd); | |
1693 | tcg_temp_free(r_size); | |
1694 | tcg_temp_free(r_asi); | |
1a2fb1c0 BS |
1695 | } |
1696 | ||
4af984a7 | 1697 | static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd) |
1a2fb1c0 | 1698 | { |
2ea815ca | 1699 | TCGv r_asi, r_size, r_rd; |
1a2fb1c0 | 1700 | |
31741a27 | 1701 | r_asi = gen_get_asi(insn, addr); |
2ea815ca BS |
1702 | r_size = tcg_const_i32(size); |
1703 | r_rd = tcg_const_i32(rd); | |
1704 | tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd); | |
1705 | tcg_temp_free(r_rd); | |
1706 | tcg_temp_free(r_size); | |
1707 | tcg_temp_free(r_asi); | |
1a2fb1c0 BS |
1708 | } |
1709 | ||
4af984a7 | 1710 | static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
1a2fb1c0 | 1711 | { |
2ea815ca | 1712 | TCGv r_asi, r_size, r_sign; |
1a2fb1c0 | 1713 | |
4af984a7 | 1714 | r_asi = gen_get_asi(insn, addr); |
2ea815ca BS |
1715 | r_size = tcg_const_i32(4); |
1716 | r_sign = tcg_const_i32(0); | |
1717 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); | |
1718 | tcg_temp_free(r_sign); | |
1719 | tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size); | |
1720 | tcg_temp_free(r_size); | |
1721 | tcg_temp_free(r_asi); | |
8d96d209 | 1722 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1a2fb1c0 BS |
1723 | } |
1724 | ||
4af984a7 | 1725 | static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn) |
1a2fb1c0 | 1726 | { |
2ea815ca | 1727 | TCGv r_asi, r_size, r_sign; |
1a2fb1c0 | 1728 | |
4af984a7 | 1729 | r_asi = gen_get_asi(insn, addr); |
2ea815ca BS |
1730 | r_size = tcg_const_i32(8); |
1731 | r_sign = tcg_const_i32(0); | |
1732 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); | |
1733 | tcg_temp_free(r_sign); | |
1734 | tcg_temp_free(r_size); | |
1735 | tcg_temp_free(r_asi); | |
4af984a7 | 1736 | tcg_gen_andi_i64(lo, cpu_tmp64, 0xffffffffULL); |
8911f501 | 1737 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32); |
4af984a7 | 1738 | tcg_gen_andi_i64(hi, cpu_tmp64, 0xffffffffULL); |
0425bee5 BS |
1739 | } |
1740 | ||
4af984a7 | 1741 | static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
0425bee5 | 1742 | { |
2ea815ca | 1743 | TCGv r_temp, r_asi, r_size; |
0425bee5 | 1744 | |
8d96d209 | 1745 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
0425bee5 | 1746 | gen_movl_reg_TN(rd + 1, r_temp); |
4af984a7 | 1747 | tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, |
0425bee5 | 1748 | r_temp); |
2ea815ca | 1749 | tcg_temp_free(r_temp); |
4af984a7 | 1750 | r_asi = gen_get_asi(insn, addr); |
2ea815ca BS |
1751 | r_size = tcg_const_i32(8); |
1752 | tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size); | |
1753 | tcg_temp_free(r_size); | |
1754 | tcg_temp_free(r_asi); | |
1a2fb1c0 BS |
1755 | } |
1756 | ||
77f193da BS |
1757 | static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
1758 | int rd) | |
1a2fb1c0 | 1759 | { |
1a2fb1c0 BS |
1760 | TCGv r_val1, r_asi; |
1761 | ||
ef28fd86 | 1762 | r_val1 = tcg_temp_new(TCG_TYPE_TL); |
1a2fb1c0 | 1763 | gen_movl_reg_TN(rd, r_val1); |
4af984a7 BS |
1764 | r_asi = gen_get_asi(insn, addr); |
1765 | tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi); | |
2ea815ca BS |
1766 | tcg_temp_free(r_asi); |
1767 | tcg_temp_free(r_val1); | |
1a2fb1c0 BS |
1768 | } |
1769 | ||
77f193da BS |
1770 | static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
1771 | int rd) | |
1a2fb1c0 | 1772 | { |
8911f501 | 1773 | TCGv r_asi; |
1a2fb1c0 | 1774 | |
8911f501 | 1775 | gen_movl_reg_TN(rd, cpu_tmp64); |
4af984a7 BS |
1776 | r_asi = gen_get_asi(insn, addr); |
1777 | tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi); | |
2ea815ca | 1778 | tcg_temp_free(r_asi); |
1a2fb1c0 BS |
1779 | } |
1780 | ||
1781 | #elif !defined(CONFIG_USER_ONLY) | |
1782 | ||
77f193da BS |
1783 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
1784 | int sign) | |
1a2fb1c0 | 1785 | { |
2ea815ca | 1786 | TCGv r_asi, r_size, r_sign; |
1a2fb1c0 | 1787 | |
2ea815ca BS |
1788 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1789 | r_size = tcg_const_i32(size); | |
1790 | r_sign = tcg_const_i32(sign); | |
1791 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); | |
1792 | tcg_temp_free(r_sign); | |
1793 | tcg_temp_free(r_size); | |
1794 | tcg_temp_free(r_asi); | |
4af984a7 | 1795 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1a2fb1c0 BS |
1796 | } |
1797 | ||
4af984a7 | 1798 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
1a2fb1c0 | 1799 | { |
2ea815ca | 1800 | TCGv r_asi, r_size; |
1a2fb1c0 | 1801 | |
4af984a7 | 1802 | tcg_gen_extu_tl_i64(cpu_tmp64, src); |
2ea815ca BS |
1803 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1804 | r_size = tcg_const_i32(size); | |
1805 | tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size); | |
1806 | tcg_temp_free(r_size); | |
1807 | tcg_temp_free(r_asi); | |
1a2fb1c0 BS |
1808 | } |
1809 | ||
4af984a7 | 1810 | static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
1a2fb1c0 | 1811 | { |
2ea815ca | 1812 | TCGv r_asi, r_size, r_sign; |
1a2fb1c0 | 1813 | |
2ea815ca BS |
1814 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1815 | r_size = tcg_const_i32(4); | |
1816 | r_sign = tcg_const_i32(0); | |
1817 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); | |
1818 | tcg_temp_free(r_sign); | |
1819 | tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size); | |
1820 | tcg_temp_free(r_size); | |
1821 | tcg_temp_free(r_asi); | |
8d96d209 | 1822 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1a2fb1c0 BS |
1823 | } |
1824 | ||
4af984a7 | 1825 | static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn) |
1a2fb1c0 | 1826 | { |
2ea815ca | 1827 | TCGv r_asi, r_size, r_sign; |
1a2fb1c0 | 1828 | |
2ea815ca BS |
1829 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1830 | r_size = tcg_const_i32(8); | |
1831 | r_sign = tcg_const_i32(0); | |
1832 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); | |
1833 | tcg_temp_free(r_sign); | |
1834 | tcg_temp_free(r_size); | |
1835 | tcg_temp_free(r_asi); | |
4af984a7 | 1836 | tcg_gen_trunc_i64_tl(lo, cpu_tmp64); |
8911f501 | 1837 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32); |
4af984a7 | 1838 | tcg_gen_trunc_i64_tl(hi, cpu_tmp64); |
0425bee5 BS |
1839 | } |
1840 | ||
4af984a7 | 1841 | static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
0425bee5 | 1842 | { |
2ea815ca | 1843 | TCGv r_temp, r_asi, r_size; |
0425bee5 | 1844 | |
8d96d209 | 1845 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
0425bee5 | 1846 | gen_movl_reg_TN(rd + 1, r_temp); |
4af984a7 | 1847 | tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp); |
2ea815ca BS |
1848 | tcg_temp_free(r_temp); |
1849 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); | |
1850 | r_size = tcg_const_i32(8); | |
1851 | tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size); | |
1852 | tcg_temp_free(r_size); | |
1853 | tcg_temp_free(r_asi); | |
1a2fb1c0 BS |
1854 | } |
1855 | #endif | |
1856 | ||
1857 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) | |
4af984a7 | 1858 | static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn) |
1a2fb1c0 | 1859 | { |
2ea815ca | 1860 | TCGv r_val, r_asi, r_size; |
1a2fb1c0 | 1861 | |
4af984a7 | 1862 | gen_ld_asi(dst, addr, insn, 1, 0); |
1a2fb1c0 | 1863 | |
2ea815ca BS |
1864 | r_val = tcg_const_i64(0xffULL); |
1865 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); | |
1866 | r_size = tcg_const_i32(1); | |
1867 | tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size); | |
1868 | tcg_temp_free(r_size); | |
1869 | tcg_temp_free(r_asi); | |
1870 | tcg_temp_free(r_val); | |
1a2fb1c0 BS |
1871 | } |
1872 | #endif | |
1873 | ||
9322a4bf BS |
1874 | static inline TCGv get_src1(unsigned int insn, TCGv def) |
1875 | { | |
1876 | TCGv r_rs1 = def; | |
1877 | unsigned int rs1; | |
1878 | ||
1879 | rs1 = GET_FIELD(insn, 13, 17); | |
1880 | if (rs1 == 0) | |
5c6a0628 | 1881 | r_rs1 = tcg_const_tl(0); // XXX how to free? |
9322a4bf | 1882 | else if (rs1 < 8) |
5c6a0628 | 1883 | r_rs1 = cpu_gregs[rs1]; |
9322a4bf BS |
1884 | else |
1885 | tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong)); | |
1886 | return r_rs1; | |
1887 | } | |
1888 | ||
a49d9390 BS |
1889 | static inline TCGv get_src2(unsigned int insn, TCGv def) |
1890 | { | |
1891 | TCGv r_rs2 = def; | |
1892 | unsigned int rs2; | |
1893 | ||
1894 | if (IS_IMM) { /* immediate */ | |
1895 | rs2 = GET_FIELDs(insn, 19, 31); | |
2ea815ca | 1896 | r_rs2 = tcg_const_tl((int)rs2); // XXX how to free? |
a49d9390 BS |
1897 | } else { /* register */ |
1898 | rs2 = GET_FIELD(insn, 27, 31); | |
1899 | if (rs2 == 0) | |
2ea815ca | 1900 | r_rs2 = tcg_const_tl(0); // XXX how to free? |
a49d9390 BS |
1901 | else if (rs2 < 8) |
1902 | r_rs2 = cpu_gregs[rs2]; | |
1903 | else | |
1904 | tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong)); | |
1905 | } | |
1906 | return r_rs2; | |
1907 | } | |
1908 | ||
64a88d5d BS |
1909 | #define CHECK_IU_FEATURE(dc, FEATURE) \ |
1910 | if (!((dc)->features & CPU_FEATURE_ ## FEATURE)) \ | |
1911 | goto illegal_insn; | |
1912 | #define CHECK_FPU_FEATURE(dc, FEATURE) \ | |
1913 | if (!((dc)->features & CPU_FEATURE_ ## FEATURE)) \ | |
1914 | goto nfpu_insn; | |
1915 | ||
0bee699e | 1916 | /* before an instruction, dc->pc must be static */ |
cf495bcf FB |
1917 | static void disas_sparc_insn(DisasContext * dc) |
1918 | { | |
1919 | unsigned int insn, opc, rs1, rs2, rd; | |
7a3f1944 | 1920 | |
a8c768c0 BS |
1921 | if (unlikely(loglevel & CPU_LOG_TB_OP)) |
1922 | tcg_gen_debug_insn_start(dc->pc); | |
0fa85d43 | 1923 | insn = ldl_code(dc->pc); |
cf495bcf | 1924 | opc = GET_FIELD(insn, 0, 1); |
7a3f1944 | 1925 | |
cf495bcf | 1926 | rd = GET_FIELD(insn, 2, 6); |
6ae20372 | 1927 | |
5c6a0628 BS |
1928 | cpu_src1 = tcg_temp_new(TCG_TYPE_TL); // const |
1929 | cpu_src2 = tcg_temp_new(TCG_TYPE_TL); // const | |
6ae20372 | 1930 | |
cf495bcf | 1931 | switch (opc) { |
0f8a249a BS |
1932 | case 0: /* branches/sethi */ |
1933 | { | |
1934 | unsigned int xop = GET_FIELD(insn, 7, 9); | |
1935 | int32_t target; | |
1936 | switch (xop) { | |
3475187d | 1937 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
1938 | case 0x1: /* V9 BPcc */ |
1939 | { | |
1940 | int cc; | |
1941 | ||
1942 | target = GET_FIELD_SP(insn, 0, 18); | |
1943 | target = sign_extend(target, 18); | |
1944 | target <<= 2; | |
1945 | cc = GET_FIELD_SP(insn, 20, 21); | |
1946 | if (cc == 0) | |
6ae20372 | 1947 | do_branch(dc, target, insn, 0, cpu_cond); |
0f8a249a | 1948 | else if (cc == 2) |
6ae20372 | 1949 | do_branch(dc, target, insn, 1, cpu_cond); |
0f8a249a BS |
1950 | else |
1951 | goto illegal_insn; | |
1952 | goto jmp_insn; | |
1953 | } | |
1954 | case 0x3: /* V9 BPr */ | |
1955 | { | |
1956 | target = GET_FIELD_SP(insn, 0, 13) | | |
13846e70 | 1957 | (GET_FIELD_SP(insn, 20, 21) << 14); |
0f8a249a BS |
1958 | target = sign_extend(target, 16); |
1959 | target <<= 2; | |
9322a4bf | 1960 | cpu_src1 = get_src1(insn, cpu_src1); |
6ae20372 | 1961 | do_branch_reg(dc, target, insn, cpu_cond, cpu_src1); |
0f8a249a BS |
1962 | goto jmp_insn; |
1963 | } | |
1964 | case 0x5: /* V9 FBPcc */ | |
1965 | { | |
1966 | int cc = GET_FIELD_SP(insn, 20, 21); | |
6ae20372 | 1967 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
a80dde08 | 1968 | goto jmp_insn; |
0f8a249a BS |
1969 | target = GET_FIELD_SP(insn, 0, 18); |
1970 | target = sign_extend(target, 19); | |
1971 | target <<= 2; | |
6ae20372 | 1972 | do_fbranch(dc, target, insn, cc, cpu_cond); |
0f8a249a BS |
1973 | goto jmp_insn; |
1974 | } | |
a4d17f19 | 1975 | #else |
0f8a249a BS |
1976 | case 0x7: /* CBN+x */ |
1977 | { | |
1978 | goto ncp_insn; | |
1979 | } | |
1980 | #endif | |
1981 | case 0x2: /* BN+x */ | |
1982 | { | |
1983 | target = GET_FIELD(insn, 10, 31); | |
1984 | target = sign_extend(target, 22); | |
1985 | target <<= 2; | |
6ae20372 | 1986 | do_branch(dc, target, insn, 0, cpu_cond); |
0f8a249a BS |
1987 | goto jmp_insn; |
1988 | } | |
1989 | case 0x6: /* FBN+x */ | |
1990 | { | |
6ae20372 | 1991 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
a80dde08 | 1992 | goto jmp_insn; |
0f8a249a BS |
1993 | target = GET_FIELD(insn, 10, 31); |
1994 | target = sign_extend(target, 22); | |
1995 | target <<= 2; | |
6ae20372 | 1996 | do_fbranch(dc, target, insn, 0, cpu_cond); |
0f8a249a BS |
1997 | goto jmp_insn; |
1998 | } | |
1999 | case 0x4: /* SETHI */ | |
0f8a249a | 2000 | if (rd) { // nop |
0f8a249a | 2001 | uint32_t value = GET_FIELD(insn, 10, 31); |
2ea815ca BS |
2002 | TCGv r_const; |
2003 | ||
2004 | r_const = tcg_const_tl(value << 10); | |
2005 | gen_movl_TN_reg(rd, r_const); | |
2006 | tcg_temp_free(r_const); | |
0f8a249a | 2007 | } |
0f8a249a BS |
2008 | break; |
2009 | case 0x0: /* UNIMPL */ | |
2010 | default: | |
3475187d | 2011 | goto illegal_insn; |
0f8a249a BS |
2012 | } |
2013 | break; | |
2014 | } | |
2015 | break; | |
cf495bcf | 2016 | case 1: |
0f8a249a BS |
2017 | /*CALL*/ { |
2018 | target_long target = GET_FIELDs(insn, 2, 31) << 2; | |
2ea815ca | 2019 | TCGv r_const; |
cf495bcf | 2020 | |
2ea815ca BS |
2021 | r_const = tcg_const_tl(dc->pc); |
2022 | gen_movl_TN_reg(15, r_const); | |
2023 | tcg_temp_free(r_const); | |
0f8a249a | 2024 | target += dc->pc; |
6ae20372 | 2025 | gen_mov_pc_npc(dc, cpu_cond); |
0f8a249a BS |
2026 | dc->npc = target; |
2027 | } | |
2028 | goto jmp_insn; | |
2029 | case 2: /* FPU & Logical Operations */ | |
2030 | { | |
2031 | unsigned int xop = GET_FIELD(insn, 7, 12); | |
2032 | if (xop == 0x3a) { /* generate trap */ | |
cf495bcf | 2033 | int cond; |
3475187d | 2034 | |
9322a4bf | 2035 | cpu_src1 = get_src1(insn, cpu_src1); |
0f8a249a BS |
2036 | if (IS_IMM) { |
2037 | rs2 = GET_FIELD(insn, 25, 31); | |
6ae20372 | 2038 | tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2); |
cf495bcf FB |
2039 | } else { |
2040 | rs2 = GET_FIELD(insn, 27, 31); | |
0f8a249a | 2041 | if (rs2 != 0) { |
6ae20372 BS |
2042 | gen_movl_reg_TN(rs2, cpu_src2); |
2043 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); | |
6f551262 BS |
2044 | } else |
2045 | tcg_gen_mov_tl(cpu_dst, cpu_src1); | |
cf495bcf | 2046 | } |
cf495bcf FB |
2047 | cond = GET_FIELD(insn, 3, 6); |
2048 | if (cond == 0x8) { | |
6ae20372 BS |
2049 | save_state(dc, cpu_cond); |
2050 | tcg_gen_helper_0_1(helper_trap, cpu_dst); | |
af7bf89b | 2051 | } else if (cond != 0) { |
748b9d8e | 2052 | TCGv r_cond = tcg_temp_new(TCG_TYPE_TL); |
3475187d | 2053 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
2054 | /* V9 icc/xcc */ |
2055 | int cc = GET_FIELD_SP(insn, 11, 12); | |
748b9d8e | 2056 | |
6ae20372 | 2057 | save_state(dc, cpu_cond); |
0f8a249a | 2058 | if (cc == 0) |
748b9d8e | 2059 | gen_cond(r_cond, 0, cond); |
0f8a249a | 2060 | else if (cc == 2) |
748b9d8e | 2061 | gen_cond(r_cond, 1, cond); |
0f8a249a BS |
2062 | else |
2063 | goto illegal_insn; | |
3475187d | 2064 | #else |
6ae20372 | 2065 | save_state(dc, cpu_cond); |
748b9d8e | 2066 | gen_cond(r_cond, 0, cond); |
3475187d | 2067 | #endif |
6ae20372 | 2068 | tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond); |
2ea815ca | 2069 | tcg_temp_free(r_cond); |
cf495bcf | 2070 | } |
a80dde08 | 2071 | gen_op_next_insn(); |
57fec1fe | 2072 | tcg_gen_exit_tb(0); |
a80dde08 FB |
2073 | dc->is_br = 1; |
2074 | goto jmp_insn; | |
cf495bcf FB |
2075 | } else if (xop == 0x28) { |
2076 | rs1 = GET_FIELD(insn, 13, 17); | |
2077 | switch(rs1) { | |
2078 | case 0: /* rdy */ | |
65fe7b09 BS |
2079 | #ifndef TARGET_SPARC64 |
2080 | case 0x01 ... 0x0e: /* undefined in the SPARCv8 | |
2081 | manual, rdy on the microSPARC | |
2082 | II */ | |
2083 | case 0x0f: /* stbar in the SPARCv8 manual, | |
2084 | rdy on the microSPARC II */ | |
2085 | case 0x10 ... 0x1f: /* implementation-dependent in the | |
2086 | SPARCv8 manual, rdy on the | |
2087 | microSPARC II */ | |
2088 | #endif | |
ece43b8d | 2089 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, |
77f193da | 2090 | offsetof(CPUSPARCState, y)); |
ece43b8d | 2091 | gen_movl_TN_reg(rd, cpu_tmp0); |
cf495bcf | 2092 | break; |
3475187d | 2093 | #ifdef TARGET_SPARC64 |
0f8a249a | 2094 | case 0x2: /* V9 rdccr */ |
6ae20372 BS |
2095 | tcg_gen_helper_1_0(helper_rdccr, cpu_dst); |
2096 | gen_movl_TN_reg(rd, cpu_dst); | |
3475187d | 2097 | break; |
0f8a249a | 2098 | case 0x3: /* V9 rdasi */ |
77f193da BS |
2099 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2100 | offsetof(CPUSPARCState, asi)); | |
6ae20372 BS |
2101 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
2102 | gen_movl_TN_reg(rd, cpu_dst); | |
3475187d | 2103 | break; |
0f8a249a | 2104 | case 0x4: /* V9 rdtick */ |
ccd4a219 BS |
2105 | { |
2106 | TCGv r_tickptr; | |
2107 | ||
2108 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
2109 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
2110 | offsetof(CPUState, tick)); | |
6ae20372 | 2111 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst, |
ccd4a219 | 2112 | r_tickptr); |
2ea815ca | 2113 | tcg_temp_free(r_tickptr); |
6ae20372 | 2114 | gen_movl_TN_reg(rd, cpu_dst); |
ccd4a219 | 2115 | } |
3475187d | 2116 | break; |
0f8a249a | 2117 | case 0x5: /* V9 rdpc */ |
2ea815ca BS |
2118 | { |
2119 | TCGv r_const; | |
2120 | ||
2121 | r_const = tcg_const_tl(dc->pc); | |
2122 | gen_movl_TN_reg(rd, r_const); | |
2123 | tcg_temp_free(r_const); | |
2124 | } | |
0f8a249a BS |
2125 | break; |
2126 | case 0x6: /* V9 rdfprs */ | |
77f193da BS |
2127 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2128 | offsetof(CPUSPARCState, fprs)); | |
6ae20372 BS |
2129 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
2130 | gen_movl_TN_reg(rd, cpu_dst); | |
3475187d | 2131 | break; |
65fe7b09 BS |
2132 | case 0xf: /* V9 membar */ |
2133 | break; /* no effect */ | |
0f8a249a | 2134 | case 0x13: /* Graphics Status */ |
6ae20372 | 2135 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
725cb90b | 2136 | goto jmp_insn; |
ece43b8d | 2137 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, |
77f193da | 2138 | offsetof(CPUSPARCState, gsr)); |
ece43b8d | 2139 | gen_movl_TN_reg(rd, cpu_tmp0); |
725cb90b | 2140 | break; |
0f8a249a | 2141 | case 0x17: /* Tick compare */ |
ece43b8d | 2142 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, |
77f193da | 2143 | offsetof(CPUSPARCState, tick_cmpr)); |
ece43b8d | 2144 | gen_movl_TN_reg(rd, cpu_tmp0); |
83469015 | 2145 | break; |
0f8a249a | 2146 | case 0x18: /* System tick */ |
ccd4a219 BS |
2147 | { |
2148 | TCGv r_tickptr; | |
2149 | ||
2150 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
2151 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
2152 | offsetof(CPUState, stick)); | |
6ae20372 | 2153 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst, |
ccd4a219 | 2154 | r_tickptr); |
2ea815ca | 2155 | tcg_temp_free(r_tickptr); |
6ae20372 | 2156 | gen_movl_TN_reg(rd, cpu_dst); |
ccd4a219 | 2157 | } |
83469015 | 2158 | break; |
0f8a249a | 2159 | case 0x19: /* System tick compare */ |
ece43b8d | 2160 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, |
77f193da | 2161 | offsetof(CPUSPARCState, stick_cmpr)); |
ece43b8d | 2162 | gen_movl_TN_reg(rd, cpu_tmp0); |
83469015 | 2163 | break; |
0f8a249a BS |
2164 | case 0x10: /* Performance Control */ |
2165 | case 0x11: /* Performance Instrumentation Counter */ | |
2166 | case 0x12: /* Dispatch Control */ | |
2167 | case 0x14: /* Softint set, WO */ | |
2168 | case 0x15: /* Softint clear, WO */ | |
2169 | case 0x16: /* Softint write */ | |
3475187d FB |
2170 | #endif |
2171 | default: | |
cf495bcf FB |
2172 | goto illegal_insn; |
2173 | } | |
e8af50a3 | 2174 | #if !defined(CONFIG_USER_ONLY) |
e9ebed4d | 2175 | } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ |
3475187d | 2176 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
2177 | if (!supervisor(dc)) |
2178 | goto priv_insn; | |
6ae20372 | 2179 | tcg_gen_helper_1_0(helper_rdpsr, cpu_dst); |
e9ebed4d BS |
2180 | #else |
2181 | if (!hypervisor(dc)) | |
2182 | goto priv_insn; | |
2183 | rs1 = GET_FIELD(insn, 13, 17); | |
2184 | switch (rs1) { | |
2185 | case 0: // hpstate | |
2186 | // gen_op_rdhpstate(); | |
2187 | break; | |
2188 | case 1: // htstate | |
2189 | // gen_op_rdhtstate(); | |
2190 | break; | |
2191 | case 3: // hintp | |
77f193da BS |
2192 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2193 | offsetof(CPUSPARCState, hintp)); | |
6ae20372 | 2194 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
e9ebed4d BS |
2195 | break; |
2196 | case 5: // htba | |
77f193da BS |
2197 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2198 | offsetof(CPUSPARCState, htba)); | |
6ae20372 | 2199 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
e9ebed4d BS |
2200 | break; |
2201 | case 6: // hver | |
77f193da BS |
2202 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2203 | offsetof(CPUSPARCState, hver)); | |
6ae20372 | 2204 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
e9ebed4d BS |
2205 | break; |
2206 | case 31: // hstick_cmpr | |
8d7d8c4b BS |
2207 | tcg_gen_ld_tl(cpu_dst, cpu_env, |
2208 | offsetof(CPUSPARCState, hstick_cmpr)); | |
e9ebed4d BS |
2209 | break; |
2210 | default: | |
2211 | goto illegal_insn; | |
2212 | } | |
2213 | #endif | |
6ae20372 | 2214 | gen_movl_TN_reg(rd, cpu_dst); |
e8af50a3 | 2215 | break; |
3475187d | 2216 | } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ |
0f8a249a BS |
2217 | if (!supervisor(dc)) |
2218 | goto priv_insn; | |
3475187d FB |
2219 | #ifdef TARGET_SPARC64 |
2220 | rs1 = GET_FIELD(insn, 13, 17); | |
0f8a249a BS |
2221 | switch (rs1) { |
2222 | case 0: // tpc | |
375ee38b BS |
2223 | { |
2224 | TCGv r_tsptr; | |
2225 | ||
2226 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
2227 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
2228 | offsetof(CPUState, tsptr)); | |
ece43b8d | 2229 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
375ee38b | 2230 | offsetof(trap_state, tpc)); |
2ea815ca | 2231 | tcg_temp_free(r_tsptr); |
375ee38b | 2232 | } |
0f8a249a BS |
2233 | break; |
2234 | case 1: // tnpc | |
375ee38b BS |
2235 | { |
2236 | TCGv r_tsptr; | |
2237 | ||
2238 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
2239 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
2240 | offsetof(CPUState, tsptr)); | |
ece43b8d | 2241 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
375ee38b | 2242 | offsetof(trap_state, tnpc)); |
2ea815ca | 2243 | tcg_temp_free(r_tsptr); |
375ee38b | 2244 | } |
0f8a249a BS |
2245 | break; |
2246 | case 2: // tstate | |
375ee38b BS |
2247 | { |
2248 | TCGv r_tsptr; | |
2249 | ||
2250 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
2251 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
2252 | offsetof(CPUState, tsptr)); | |
ece43b8d | 2253 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
375ee38b | 2254 | offsetof(trap_state, tstate)); |
2ea815ca | 2255 | tcg_temp_free(r_tsptr); |
375ee38b | 2256 | } |
0f8a249a BS |
2257 | break; |
2258 | case 3: // tt | |
375ee38b BS |
2259 | { |
2260 | TCGv r_tsptr; | |
2261 | ||
2262 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
2263 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
2264 | offsetof(CPUState, tsptr)); | |
ece43b8d | 2265 | tcg_gen_ld_i32(cpu_tmp0, r_tsptr, |
375ee38b | 2266 | offsetof(trap_state, tt)); |
2ea815ca | 2267 | tcg_temp_free(r_tsptr); |
375ee38b | 2268 | } |
0f8a249a BS |
2269 | break; |
2270 | case 4: // tick | |
ccd4a219 BS |
2271 | { |
2272 | TCGv r_tickptr; | |
2273 | ||
2274 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
2275 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
2276 | offsetof(CPUState, tick)); | |
ece43b8d | 2277 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_tmp0, |
ccd4a219 | 2278 | r_tickptr); |
ece43b8d | 2279 | gen_movl_TN_reg(rd, cpu_tmp0); |
2ea815ca | 2280 | tcg_temp_free(r_tickptr); |
ccd4a219 | 2281 | } |
0f8a249a BS |
2282 | break; |
2283 | case 5: // tba | |
ece43b8d | 2284 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, |
77f193da | 2285 | offsetof(CPUSPARCState, tbr)); |
0f8a249a BS |
2286 | break; |
2287 | case 6: // pstate | |
77f193da BS |
2288 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2289 | offsetof(CPUSPARCState, pstate)); | |
ece43b8d | 2290 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
0f8a249a BS |
2291 | break; |
2292 | case 7: // tl | |
77f193da BS |
2293 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2294 | offsetof(CPUSPARCState, tl)); | |
ece43b8d | 2295 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
0f8a249a BS |
2296 | break; |
2297 | case 8: // pil | |
77f193da BS |
2298 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2299 | offsetof(CPUSPARCState, psrpil)); | |
ece43b8d | 2300 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
0f8a249a BS |
2301 | break; |
2302 | case 9: // cwp | |
ece43b8d | 2303 | tcg_gen_helper_1_0(helper_rdcwp, cpu_tmp0); |
0f8a249a BS |
2304 | break; |
2305 | case 10: // cansave | |
77f193da BS |
2306 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2307 | offsetof(CPUSPARCState, cansave)); | |
ece43b8d | 2308 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
0f8a249a BS |
2309 | break; |
2310 | case 11: // canrestore | |
77f193da BS |
2311 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2312 | offsetof(CPUSPARCState, canrestore)); | |
ece43b8d | 2313 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
0f8a249a BS |
2314 | break; |
2315 | case 12: // cleanwin | |
77f193da BS |
2316 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2317 | offsetof(CPUSPARCState, cleanwin)); | |
ece43b8d | 2318 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
0f8a249a BS |
2319 | break; |
2320 | case 13: // otherwin | |
77f193da BS |
2321 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2322 | offsetof(CPUSPARCState, otherwin)); | |
ece43b8d | 2323 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
0f8a249a BS |
2324 | break; |
2325 | case 14: // wstate | |
77f193da BS |
2326 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2327 | offsetof(CPUSPARCState, wstate)); | |
ece43b8d | 2328 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
0f8a249a | 2329 | break; |
e9ebed4d | 2330 | case 16: // UA2005 gl |
77f193da BS |
2331 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2332 | offsetof(CPUSPARCState, gl)); | |
ece43b8d | 2333 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
e9ebed4d BS |
2334 | break; |
2335 | case 26: // UA2005 strand status | |
2336 | if (!hypervisor(dc)) | |
2337 | goto priv_insn; | |
77f193da BS |
2338 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2339 | offsetof(CPUSPARCState, ssr)); | |
ece43b8d | 2340 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
e9ebed4d | 2341 | break; |
0f8a249a | 2342 | case 31: // ver |
ece43b8d | 2343 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, |
77f193da | 2344 | offsetof(CPUSPARCState, version)); |
0f8a249a BS |
2345 | break; |
2346 | case 15: // fq | |
2347 | default: | |
2348 | goto illegal_insn; | |
2349 | } | |
3475187d | 2350 | #else |
77f193da BS |
2351 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2352 | offsetof(CPUSPARCState, wim)); | |
ece43b8d | 2353 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
3475187d | 2354 | #endif |
ece43b8d | 2355 | gen_movl_TN_reg(rd, cpu_tmp0); |
e8af50a3 | 2356 | break; |
3475187d FB |
2357 | } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ |
2358 | #ifdef TARGET_SPARC64 | |
c5f2f668 | 2359 | save_state(dc, cpu_cond); |
72a9747b | 2360 | tcg_gen_helper_0_0(helper_flushw); |
3475187d | 2361 | #else |
0f8a249a BS |
2362 | if (!supervisor(dc)) |
2363 | goto priv_insn; | |
ece43b8d BS |
2364 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, tbr)); |
2365 | gen_movl_TN_reg(rd, cpu_tmp0); | |
3475187d | 2366 | #endif |
e8af50a3 FB |
2367 | break; |
2368 | #endif | |
0f8a249a | 2369 | } else if (xop == 0x34) { /* FPU Operations */ |
6ae20372 | 2370 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
a80dde08 | 2371 | goto jmp_insn; |
0f8a249a | 2372 | gen_op_clear_ieee_excp_and_FTT(); |
e8af50a3 | 2373 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a BS |
2374 | rs2 = GET_FIELD(insn, 27, 31); |
2375 | xop = GET_FIELD(insn, 18, 26); | |
2376 | switch (xop) { | |
2377 | case 0x1: /* fmovs */ | |
2378 | gen_op_load_fpr_FT0(rs2); | |
2379 | gen_op_store_FT0_fpr(rd); | |
2380 | break; | |
2381 | case 0x5: /* fnegs */ | |
2382 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 2383 | tcg_gen_helper_0_0(helper_fnegs); |
0f8a249a BS |
2384 | gen_op_store_FT0_fpr(rd); |
2385 | break; | |
2386 | case 0x9: /* fabss */ | |
2387 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2388 | tcg_gen_helper_0_0(helper_fabss); |
0f8a249a BS |
2389 | gen_op_store_FT0_fpr(rd); |
2390 | break; | |
2391 | case 0x29: /* fsqrts */ | |
64a88d5d | 2392 | CHECK_FPU_FEATURE(dc, FSQRT); |
0f8a249a | 2393 | gen_op_load_fpr_FT1(rs2); |
7e8c2b6c BS |
2394 | gen_clear_float_exceptions(); |
2395 | tcg_gen_helper_0_0(helper_fsqrts); | |
2396 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); | |
0f8a249a BS |
2397 | gen_op_store_FT0_fpr(rd); |
2398 | break; | |
2399 | case 0x2a: /* fsqrtd */ | |
64a88d5d | 2400 | CHECK_FPU_FEATURE(dc, FSQRT); |
0f8a249a | 2401 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
7e8c2b6c BS |
2402 | gen_clear_float_exceptions(); |
2403 | tcg_gen_helper_0_0(helper_fsqrtd); | |
2404 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); | |
0f8a249a BS |
2405 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2406 | break; | |
2407 | case 0x2b: /* fsqrtq */ | |
64a88d5d | 2408 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2409 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
7e8c2b6c BS |
2410 | gen_clear_float_exceptions(); |
2411 | tcg_gen_helper_0_0(helper_fsqrtq); | |
2412 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); | |
1f587329 BS |
2413 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2414 | break; | |
0f8a249a BS |
2415 | case 0x41: |
2416 | gen_op_load_fpr_FT0(rs1); | |
2417 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2418 | gen_clear_float_exceptions(); |
44e7757c | 2419 | tcg_gen_helper_0_0(helper_fadds); |
7e8c2b6c | 2420 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2421 | gen_op_store_FT0_fpr(rd); |
2422 | break; | |
2423 | case 0x42: | |
2424 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
2425 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2426 | gen_clear_float_exceptions(); |
44e7757c | 2427 | tcg_gen_helper_0_0(helper_faddd); |
7e8c2b6c | 2428 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2429 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2430 | break; | |
2431 | case 0x43: /* faddq */ | |
64a88d5d | 2432 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 BS |
2433 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2434 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2435 | gen_clear_float_exceptions(); |
44e7757c | 2436 | tcg_gen_helper_0_0(helper_faddq); |
7e8c2b6c | 2437 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2438 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2439 | break; | |
0f8a249a BS |
2440 | case 0x45: |
2441 | gen_op_load_fpr_FT0(rs1); | |
2442 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2443 | gen_clear_float_exceptions(); |
44e7757c | 2444 | tcg_gen_helper_0_0(helper_fsubs); |
7e8c2b6c | 2445 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2446 | gen_op_store_FT0_fpr(rd); |
2447 | break; | |
2448 | case 0x46: | |
2449 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
2450 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2451 | gen_clear_float_exceptions(); |
44e7757c | 2452 | tcg_gen_helper_0_0(helper_fsubd); |
7e8c2b6c | 2453 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2454 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2455 | break; | |
2456 | case 0x47: /* fsubq */ | |
64a88d5d | 2457 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 BS |
2458 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2459 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2460 | gen_clear_float_exceptions(); |
44e7757c | 2461 | tcg_gen_helper_0_0(helper_fsubq); |
7e8c2b6c | 2462 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2463 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2464 | break; | |
64a88d5d BS |
2465 | case 0x49: /* fmuls */ |
2466 | CHECK_FPU_FEATURE(dc, FMUL); | |
0f8a249a BS |
2467 | gen_op_load_fpr_FT0(rs1); |
2468 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2469 | gen_clear_float_exceptions(); |
44e7757c | 2470 | tcg_gen_helper_0_0(helper_fmuls); |
7e8c2b6c | 2471 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2472 | gen_op_store_FT0_fpr(rd); |
2473 | break; | |
64a88d5d BS |
2474 | case 0x4a: /* fmuld */ |
2475 | CHECK_FPU_FEATURE(dc, FMUL); | |
0f8a249a BS |
2476 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2477 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2478 | gen_clear_float_exceptions(); |
44e7757c | 2479 | tcg_gen_helper_0_0(helper_fmuld); |
7e8c2b6c | 2480 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2382dc6b | 2481 | gen_op_store_DT0_fpr(DFPREG(rd)); |
0f8a249a BS |
2482 | break; |
2483 | case 0x4b: /* fmulq */ | |
64a88d5d BS |
2484 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2485 | CHECK_FPU_FEATURE(dc, FMUL); | |
1f587329 BS |
2486 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2487 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2488 | gen_clear_float_exceptions(); |
44e7757c | 2489 | tcg_gen_helper_0_0(helper_fmulq); |
7e8c2b6c | 2490 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2491 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2492 | break; | |
0f8a249a BS |
2493 | case 0x4d: |
2494 | gen_op_load_fpr_FT0(rs1); | |
2495 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2496 | gen_clear_float_exceptions(); |
44e7757c | 2497 | tcg_gen_helper_0_0(helper_fdivs); |
7e8c2b6c | 2498 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2499 | gen_op_store_FT0_fpr(rd); |
2500 | break; | |
2501 | case 0x4e: | |
2502 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
2503 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2504 | gen_clear_float_exceptions(); |
44e7757c | 2505 | tcg_gen_helper_0_0(helper_fdivd); |
7e8c2b6c | 2506 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2507 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2508 | break; | |
2509 | case 0x4f: /* fdivq */ | |
64a88d5d | 2510 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 BS |
2511 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2512 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2513 | gen_clear_float_exceptions(); |
44e7757c | 2514 | tcg_gen_helper_0_0(helper_fdivq); |
7e8c2b6c | 2515 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2516 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2517 | break; | |
0f8a249a | 2518 | case 0x69: |
e30b4678 | 2519 | CHECK_FPU_FEATURE(dc, FSMULD); |
0f8a249a BS |
2520 | gen_op_load_fpr_FT0(rs1); |
2521 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2522 | gen_clear_float_exceptions(); |
44e7757c | 2523 | tcg_gen_helper_0_0(helper_fsmuld); |
7e8c2b6c | 2524 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2525 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2526 | break; | |
2527 | case 0x6e: /* fdmulq */ | |
64a88d5d | 2528 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 BS |
2529 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2530 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2531 | gen_clear_float_exceptions(); |
44e7757c | 2532 | tcg_gen_helper_0_0(helper_fdmulq); |
7e8c2b6c | 2533 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2534 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2535 | break; | |
0f8a249a BS |
2536 | case 0xc4: |
2537 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2538 | gen_clear_float_exceptions(); |
44e7757c | 2539 | tcg_gen_helper_0_0(helper_fitos); |
7e8c2b6c | 2540 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2541 | gen_op_store_FT0_fpr(rd); |
2542 | break; | |
2543 | case 0xc6: | |
2544 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2545 | gen_clear_float_exceptions(); |
44e7757c | 2546 | tcg_gen_helper_0_0(helper_fdtos); |
7e8c2b6c | 2547 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2548 | gen_op_store_FT0_fpr(rd); |
2549 | break; | |
2550 | case 0xc7: /* fqtos */ | |
64a88d5d | 2551 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2552 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
7e8c2b6c | 2553 | gen_clear_float_exceptions(); |
44e7757c | 2554 | tcg_gen_helper_0_0(helper_fqtos); |
7e8c2b6c | 2555 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2556 | gen_op_store_FT0_fpr(rd); |
2557 | break; | |
0f8a249a BS |
2558 | case 0xc8: |
2559 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 2560 | tcg_gen_helper_0_0(helper_fitod); |
0f8a249a BS |
2561 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2562 | break; | |
2563 | case 0xc9: | |
2564 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 2565 | tcg_gen_helper_0_0(helper_fstod); |
0f8a249a BS |
2566 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2567 | break; | |
2568 | case 0xcb: /* fqtod */ | |
64a88d5d | 2569 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2570 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
7e8c2b6c | 2571 | gen_clear_float_exceptions(); |
44e7757c | 2572 | tcg_gen_helper_0_0(helper_fqtod); |
7e8c2b6c | 2573 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2574 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2575 | break; | |
0f8a249a | 2576 | case 0xcc: /* fitoq */ |
64a88d5d | 2577 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2578 | gen_op_load_fpr_FT1(rs2); |
44e7757c | 2579 | tcg_gen_helper_0_0(helper_fitoq); |
1f587329 BS |
2580 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2581 | break; | |
0f8a249a | 2582 | case 0xcd: /* fstoq */ |
64a88d5d | 2583 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2584 | gen_op_load_fpr_FT1(rs2); |
44e7757c | 2585 | tcg_gen_helper_0_0(helper_fstoq); |
1f587329 BS |
2586 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2587 | break; | |
0f8a249a | 2588 | case 0xce: /* fdtoq */ |
64a88d5d | 2589 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2590 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
44e7757c | 2591 | tcg_gen_helper_0_0(helper_fdtoq); |
1f587329 BS |
2592 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2593 | break; | |
0f8a249a BS |
2594 | case 0xd1: |
2595 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2596 | gen_clear_float_exceptions(); |
44e7757c | 2597 | tcg_gen_helper_0_0(helper_fstoi); |
7e8c2b6c | 2598 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2599 | gen_op_store_FT0_fpr(rd); |
2600 | break; | |
2601 | case 0xd2: | |
2382dc6b | 2602 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
7e8c2b6c | 2603 | gen_clear_float_exceptions(); |
44e7757c | 2604 | tcg_gen_helper_0_0(helper_fdtoi); |
7e8c2b6c | 2605 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2606 | gen_op_store_FT0_fpr(rd); |
2607 | break; | |
2608 | case 0xd3: /* fqtoi */ | |
64a88d5d | 2609 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2610 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
7e8c2b6c | 2611 | gen_clear_float_exceptions(); |
44e7757c | 2612 | tcg_gen_helper_0_0(helper_fqtoi); |
7e8c2b6c | 2613 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2614 | gen_op_store_FT0_fpr(rd); |
2615 | break; | |
3475187d | 2616 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
2617 | case 0x2: /* V9 fmovd */ |
2618 | gen_op_load_fpr_DT0(DFPREG(rs2)); | |
2619 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
2620 | break; | |
1f587329 | 2621 | case 0x3: /* V9 fmovq */ |
64a88d5d | 2622 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 BS |
2623 | gen_op_load_fpr_QT0(QFPREG(rs2)); |
2624 | gen_op_store_QT0_fpr(QFPREG(rd)); | |
2625 | break; | |
0f8a249a BS |
2626 | case 0x6: /* V9 fnegd */ |
2627 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 2628 | tcg_gen_helper_0_0(helper_fnegd); |
0f8a249a BS |
2629 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2630 | break; | |
1f587329 | 2631 | case 0x7: /* V9 fnegq */ |
64a88d5d | 2632 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2633 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
44e7757c | 2634 | tcg_gen_helper_0_0(helper_fnegq); |
1f587329 BS |
2635 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2636 | break; | |
0f8a249a BS |
2637 | case 0xa: /* V9 fabsd */ |
2638 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2639 | tcg_gen_helper_0_0(helper_fabsd); |
0f8a249a BS |
2640 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2641 | break; | |
1f587329 | 2642 | case 0xb: /* V9 fabsq */ |
64a88d5d | 2643 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2644 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
7e8c2b6c | 2645 | tcg_gen_helper_0_0(helper_fabsq); |
1f587329 BS |
2646 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2647 | break; | |
0f8a249a BS |
2648 | case 0x81: /* V9 fstox */ |
2649 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2650 | gen_clear_float_exceptions(); |
44e7757c | 2651 | tcg_gen_helper_0_0(helper_fstox); |
7e8c2b6c | 2652 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2653 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2654 | break; | |
2655 | case 0x82: /* V9 fdtox */ | |
2656 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2657 | gen_clear_float_exceptions(); |
44e7757c | 2658 | tcg_gen_helper_0_0(helper_fdtox); |
7e8c2b6c | 2659 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2660 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2661 | break; | |
1f587329 | 2662 | case 0x83: /* V9 fqtox */ |
64a88d5d | 2663 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2664 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
7e8c2b6c | 2665 | gen_clear_float_exceptions(); |
44e7757c | 2666 | tcg_gen_helper_0_0(helper_fqtox); |
7e8c2b6c | 2667 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2668 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2669 | break; | |
0f8a249a BS |
2670 | case 0x84: /* V9 fxtos */ |
2671 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2672 | gen_clear_float_exceptions(); |
44e7757c | 2673 | tcg_gen_helper_0_0(helper_fxtos); |
7e8c2b6c | 2674 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2675 | gen_op_store_FT0_fpr(rd); |
2676 | break; | |
2677 | case 0x88: /* V9 fxtod */ | |
2678 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2679 | gen_clear_float_exceptions(); |
44e7757c | 2680 | tcg_gen_helper_0_0(helper_fxtod); |
7e8c2b6c | 2681 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2682 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2683 | break; | |
0f8a249a | 2684 | case 0x8c: /* V9 fxtoq */ |
64a88d5d | 2685 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2686 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
7e8c2b6c | 2687 | gen_clear_float_exceptions(); |
44e7757c | 2688 | tcg_gen_helper_0_0(helper_fxtoq); |
7e8c2b6c | 2689 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2690 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2691 | break; | |
0f8a249a BS |
2692 | #endif |
2693 | default: | |
2694 | goto illegal_insn; | |
2695 | } | |
2696 | } else if (xop == 0x35) { /* FPU Operations */ | |
3475187d | 2697 | #ifdef TARGET_SPARC64 |
0f8a249a | 2698 | int cond; |
3475187d | 2699 | #endif |
6ae20372 | 2700 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
a80dde08 | 2701 | goto jmp_insn; |
0f8a249a | 2702 | gen_op_clear_ieee_excp_and_FTT(); |
cf495bcf | 2703 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a BS |
2704 | rs2 = GET_FIELD(insn, 27, 31); |
2705 | xop = GET_FIELD(insn, 18, 26); | |
3475187d | 2706 | #ifdef TARGET_SPARC64 |
0f8a249a | 2707 | if ((xop & 0x11f) == 0x005) { // V9 fmovsr |
dcf24905 BS |
2708 | int l1; |
2709 | ||
2710 | l1 = gen_new_label(); | |
0f8a249a | 2711 | cond = GET_FIELD_SP(insn, 14, 17); |
9322a4bf | 2712 | cpu_src1 = get_src1(insn, cpu_src1); |
cb63669a PB |
2713 | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2714 | 0, l1); | |
19f329ad | 2715 | gen_op_load_fpr_FT0(rs2); |
0f8a249a | 2716 | gen_op_store_FT0_fpr(rd); |
dcf24905 | 2717 | gen_set_label(l1); |
0f8a249a BS |
2718 | break; |
2719 | } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr | |
dcf24905 BS |
2720 | int l1; |
2721 | ||
2722 | l1 = gen_new_label(); | |
0f8a249a | 2723 | cond = GET_FIELD_SP(insn, 14, 17); |
9322a4bf | 2724 | cpu_src1 = get_src1(insn, cpu_src1); |
cb63669a PB |
2725 | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2726 | 0, l1); | |
19f329ad | 2727 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
2382dc6b | 2728 | gen_op_store_DT0_fpr(DFPREG(rd)); |
dcf24905 | 2729 | gen_set_label(l1); |
0f8a249a BS |
2730 | break; |
2731 | } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr | |
dcf24905 BS |
2732 | int l1; |
2733 | ||
64a88d5d | 2734 | CHECK_FPU_FEATURE(dc, FLOAT128); |
dcf24905 | 2735 | l1 = gen_new_label(); |
1f587329 | 2736 | cond = GET_FIELD_SP(insn, 14, 17); |
9322a4bf | 2737 | cpu_src1 = get_src1(insn, cpu_src1); |
cb63669a PB |
2738 | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2739 | 0, l1); | |
19f329ad | 2740 | gen_op_load_fpr_QT0(QFPREG(rs2)); |
1f587329 | 2741 | gen_op_store_QT0_fpr(QFPREG(rd)); |
dcf24905 | 2742 | gen_set_label(l1); |
1f587329 | 2743 | break; |
0f8a249a BS |
2744 | } |
2745 | #endif | |
2746 | switch (xop) { | |
3475187d | 2747 | #ifdef TARGET_SPARC64 |
19f329ad BS |
2748 | #define FMOVCC(size_FDQ, fcc) \ |
2749 | { \ | |
0425bee5 | 2750 | TCGv r_cond; \ |
19f329ad BS |
2751 | int l1; \ |
2752 | \ | |
2753 | l1 = gen_new_label(); \ | |
19f329ad | 2754 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ |
19f329ad BS |
2755 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2756 | gen_fcond(r_cond, fcc, cond); \ | |
cb63669a PB |
2757 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2758 | 0, l1); \ | |
77f193da BS |
2759 | glue(glue(gen_op_load_fpr_, size_FDQ), T0) \ |
2760 | (glue(size_FDQ, FPREG(rs2))); \ | |
2761 | glue(glue(gen_op_store_, size_FDQ), T0_fpr) \ | |
2762 | (glue(size_FDQ, FPREG(rd))); \ | |
19f329ad | 2763 | gen_set_label(l1); \ |
2ea815ca | 2764 | tcg_temp_free(r_cond); \ |
19f329ad | 2765 | } |
0f8a249a | 2766 | case 0x001: /* V9 fmovscc %fcc0 */ |
19f329ad | 2767 | FMOVCC(F, 0); |
0f8a249a BS |
2768 | break; |
2769 | case 0x002: /* V9 fmovdcc %fcc0 */ | |
19f329ad | 2770 | FMOVCC(D, 0); |
0f8a249a BS |
2771 | break; |
2772 | case 0x003: /* V9 fmovqcc %fcc0 */ | |
64a88d5d | 2773 | CHECK_FPU_FEATURE(dc, FLOAT128); |
19f329ad | 2774 | FMOVCC(Q, 0); |
1f587329 | 2775 | break; |
0f8a249a | 2776 | case 0x041: /* V9 fmovscc %fcc1 */ |
19f329ad | 2777 | FMOVCC(F, 1); |
0f8a249a BS |
2778 | break; |
2779 | case 0x042: /* V9 fmovdcc %fcc1 */ | |
19f329ad | 2780 | FMOVCC(D, 1); |
0f8a249a BS |
2781 | break; |
2782 | case 0x043: /* V9 fmovqcc %fcc1 */ | |
64a88d5d | 2783 | CHECK_FPU_FEATURE(dc, FLOAT128); |
19f329ad | 2784 | FMOVCC(Q, 1); |
1f587329 | 2785 | break; |
0f8a249a | 2786 | case 0x081: /* V9 fmovscc %fcc2 */ |
19f329ad | 2787 | FMOVCC(F, 2); |
0f8a249a BS |
2788 | break; |
2789 | case 0x082: /* V9 fmovdcc %fcc2 */ | |
19f329ad | 2790 | FMOVCC(D, 2); |
0f8a249a BS |
2791 | break; |
2792 | case 0x083: /* V9 fmovqcc %fcc2 */ | |
64a88d5d | 2793 | CHECK_FPU_FEATURE(dc, FLOAT128); |
19f329ad | 2794 | FMOVCC(Q, 2); |
1f587329 | 2795 | break; |
0f8a249a | 2796 | case 0x0c1: /* V9 fmovscc %fcc3 */ |
19f329ad | 2797 | FMOVCC(F, 3); |
0f8a249a BS |
2798 | break; |
2799 | case 0x0c2: /* V9 fmovdcc %fcc3 */ | |
19f329ad | 2800 | FMOVCC(D, 3); |
0f8a249a BS |
2801 | break; |
2802 | case 0x0c3: /* V9 fmovqcc %fcc3 */ | |
64a88d5d | 2803 | CHECK_FPU_FEATURE(dc, FLOAT128); |
19f329ad | 2804 | FMOVCC(Q, 3); |
1f587329 | 2805 | break; |
19f329ad BS |
2806 | #undef FMOVCC |
2807 | #define FMOVCC(size_FDQ, icc) \ | |
2808 | { \ | |
0425bee5 | 2809 | TCGv r_cond; \ |
19f329ad BS |
2810 | int l1; \ |
2811 | \ | |
2812 | l1 = gen_new_label(); \ | |
19f329ad | 2813 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ |
19f329ad BS |
2814 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2815 | gen_cond(r_cond, icc, cond); \ | |
cb63669a PB |
2816 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2817 | 0, l1); \ | |
77f193da BS |
2818 | glue(glue(gen_op_load_fpr_, size_FDQ), T0) \ |
2819 | (glue(size_FDQ, FPREG(rs2))); \ | |
2820 | glue(glue(gen_op_store_, size_FDQ), T0_fpr) \ | |
2821 | (glue(size_FDQ, FPREG(rd))); \ | |
19f329ad | 2822 | gen_set_label(l1); \ |
2ea815ca | 2823 | tcg_temp_free(r_cond); \ |
19f329ad BS |
2824 | } |
2825 | ||
0f8a249a | 2826 | case 0x101: /* V9 fmovscc %icc */ |
19f329ad | 2827 | FMOVCC(F, 0); |
0f8a249a BS |
2828 | break; |
2829 | case 0x102: /* V9 fmovdcc %icc */ | |
19f329ad | 2830 | FMOVCC(D, 0); |
0f8a249a | 2831 | case 0x103: /* V9 fmovqcc %icc */ |
64a88d5d BS |
2832 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2833 | FMOVCC(Q, 0); | |
1f587329 | 2834 | break; |
0f8a249a | 2835 | case 0x181: /* V9 fmovscc %xcc */ |
19f329ad | 2836 | FMOVCC(F, 1); |
0f8a249a BS |
2837 | break; |
2838 | case 0x182: /* V9 fmovdcc %xcc */ | |
19f329ad | 2839 | FMOVCC(D, 1); |
0f8a249a BS |
2840 | break; |
2841 | case 0x183: /* V9 fmovqcc %xcc */ | |
64a88d5d | 2842 | CHECK_FPU_FEATURE(dc, FLOAT128); |
19f329ad | 2843 | FMOVCC(Q, 1); |
1f587329 | 2844 | break; |
19f329ad | 2845 | #undef FMOVCC |
1f587329 BS |
2846 | #endif |
2847 | case 0x51: /* fcmps, V9 %fcc */ | |
0f8a249a BS |
2848 | gen_op_load_fpr_FT0(rs1); |
2849 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2850 | gen_op_fcmps(rd & 3); |
0f8a249a | 2851 | break; |
1f587329 | 2852 | case 0x52: /* fcmpd, V9 %fcc */ |
0f8a249a BS |
2853 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2854 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2855 | gen_op_fcmpd(rd & 3); |
0f8a249a | 2856 | break; |
1f587329 | 2857 | case 0x53: /* fcmpq, V9 %fcc */ |
64a88d5d | 2858 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 BS |
2859 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2860 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2861 | gen_op_fcmpq(rd & 3); |
1f587329 | 2862 | break; |
0f8a249a BS |
2863 | case 0x55: /* fcmpes, V9 %fcc */ |
2864 | gen_op_load_fpr_FT0(rs1); | |
2865 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2866 | gen_op_fcmpes(rd & 3); |
0f8a249a BS |
2867 | break; |
2868 | case 0x56: /* fcmped, V9 %fcc */ | |
2869 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
2870 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2871 | gen_op_fcmped(rd & 3); |
0f8a249a | 2872 | break; |
1f587329 | 2873 | case 0x57: /* fcmpeq, V9 %fcc */ |
64a88d5d | 2874 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 BS |
2875 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2876 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2877 | gen_op_fcmpeq(rd & 3); |
1f587329 | 2878 | break; |
0f8a249a BS |
2879 | default: |
2880 | goto illegal_insn; | |
2881 | } | |
0f8a249a BS |
2882 | } else if (xop == 0x2) { |
2883 | // clr/mov shortcut | |
e80cfcfc FB |
2884 | |
2885 | rs1 = GET_FIELD(insn, 13, 17); | |
0f8a249a | 2886 | if (rs1 == 0) { |
1a2fb1c0 | 2887 | // or %g0, x, y -> mov T0, x; mov y, T0 |
0f8a249a | 2888 | if (IS_IMM) { /* immediate */ |
2ea815ca BS |
2889 | TCGv r_const; |
2890 | ||
0f8a249a | 2891 | rs2 = GET_FIELDs(insn, 19, 31); |
2ea815ca BS |
2892 | r_const = tcg_const_tl((int)rs2); |
2893 | gen_movl_TN_reg(rd, r_const); | |
2894 | tcg_temp_free(r_const); | |
0f8a249a BS |
2895 | } else { /* register */ |
2896 | rs2 = GET_FIELD(insn, 27, 31); | |
6ae20372 | 2897 | gen_movl_reg_TN(rs2, cpu_dst); |
9c6c6662 | 2898 | gen_movl_TN_reg(rd, cpu_dst); |
0f8a249a | 2899 | } |
0f8a249a | 2900 | } else { |
9322a4bf | 2901 | cpu_src1 = get_src1(insn, cpu_src1); |
0f8a249a | 2902 | if (IS_IMM) { /* immediate */ |
0f8a249a | 2903 | rs2 = GET_FIELDs(insn, 19, 31); |
6ae20372 | 2904 | tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2); |
9c6c6662 | 2905 | gen_movl_TN_reg(rd, cpu_dst); |
0f8a249a BS |
2906 | } else { /* register */ |
2907 | // or x, %g0, y -> mov T1, x; mov y, T1 | |
2908 | rs2 = GET_FIELD(insn, 27, 31); | |
2909 | if (rs2 != 0) { | |
6ae20372 BS |
2910 | gen_movl_reg_TN(rs2, cpu_src2); |
2911 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); | |
9c6c6662 | 2912 | gen_movl_TN_reg(rd, cpu_dst); |
6f551262 | 2913 | } else |
9c6c6662 | 2914 | gen_movl_TN_reg(rd, cpu_src1); |
0f8a249a | 2915 | } |
0f8a249a | 2916 | } |
83469015 | 2917 | #ifdef TARGET_SPARC64 |
0f8a249a | 2918 | } else if (xop == 0x25) { /* sll, V9 sllx */ |
9322a4bf | 2919 | cpu_src1 = get_src1(insn, cpu_src1); |
0f8a249a | 2920 | if (IS_IMM) { /* immediate */ |
83469015 | 2921 | rs2 = GET_FIELDs(insn, 20, 31); |
1a2fb1c0 | 2922 | if (insn & (1 << 12)) { |
6ae20372 | 2923 | tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f); |
1a2fb1c0 | 2924 | } else { |
6ae20372 BS |
2925 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); |
2926 | tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f); | |
1a2fb1c0 | 2927 | } |
0f8a249a | 2928 | } else { /* register */ |
83469015 | 2929 | rs2 = GET_FIELD(insn, 27, 31); |
6ae20372 | 2930 | gen_movl_reg_TN(rs2, cpu_src2); |
1a2fb1c0 | 2931 | if (insn & (1 << 12)) { |
6ae20372 BS |
2932 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); |
2933 | tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0); | |
1a2fb1c0 | 2934 | } else { |
6ae20372 BS |
2935 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); |
2936 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); | |
2937 | tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0); | |
1a2fb1c0 | 2938 | } |
83469015 | 2939 | } |
6ae20372 | 2940 | gen_movl_TN_reg(rd, cpu_dst); |
0f8a249a | 2941 | } else if (xop == 0x26) { /* srl, V9 srlx */ |
9322a4bf | 2942 | cpu_src1 = get_src1(insn, cpu_src1); |
0f8a249a | 2943 | if (IS_IMM) { /* immediate */ |
83469015 | 2944 | rs2 = GET_FIELDs(insn, 20, 31); |
1a2fb1c0 | 2945 | if (insn & (1 << 12)) { |
6ae20372 | 2946 | tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f); |
1a2fb1c0 | 2947 | } else { |
6ae20372 BS |
2948 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); |
2949 | tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f); | |
1a2fb1c0 | 2950 | } |
0f8a249a | 2951 | } else { /* register */ |
83469015 | 2952 | rs2 = GET_FIELD(insn, 27, 31); |
6ae20372 | 2953 | gen_movl_reg_TN(rs2, cpu_src2); |
1a2fb1c0 | 2954 | if (insn & (1 << 12)) { |
6ae20372 BS |
2955 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); |
2956 | tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0); | |
1a2fb1c0 | 2957 | } else { |
6ae20372 BS |
2958 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); |
2959 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); | |
2960 | tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0); | |
1a2fb1c0 | 2961 | } |
83469015 | 2962 | } |
6ae20372 | 2963 | gen_movl_TN_reg(rd, cpu_dst); |
0f8a249a | 2964 | } else if (xop == 0x27) { /* sra, V9 srax */ |
9322a4bf | 2965 | cpu_src1 = get_src1(insn, cpu_src1); |
0f8a249a | 2966 | if (IS_IMM) { /* immediate */ |
83469015 | 2967 | rs2 = GET_FIELDs(insn, 20, 31); |
1a2fb1c0 | 2968 | if (insn & (1 << 12)) { |
6ae20372 | 2969 | tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f); |
1a2fb1c0 | 2970 | } else { |
6ae20372 BS |
2971 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); |
2972 | tcg_gen_ext_i32_i64(cpu_dst, cpu_dst); | |
2973 | tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f); | |
1a2fb1c0 | 2974 | } |
0f8a249a | 2975 | } else { /* register */ |
83469015 | 2976 | rs2 = GET_FIELD(insn, 27, 31); |
6ae20372 | 2977 | gen_movl_reg_TN(rs2, cpu_src2); |
1a2fb1c0 | 2978 | if (insn & (1 << 12)) { |
6ae20372 BS |
2979 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); |
2980 | tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0); | |
1a2fb1c0 | 2981 | } else { |
6ae20372 BS |
2982 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); |
2983 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); | |
2984 | tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0); | |
1a2fb1c0 | 2985 | } |
83469015 | 2986 | } |
6ae20372 | 2987 | gen_movl_TN_reg(rd, cpu_dst); |
e80cfcfc | 2988 | #endif |
fcc72045 | 2989 | } else if (xop < 0x36) { |
9322a4bf | 2990 | cpu_src1 = get_src1(insn, cpu_src1); |
a49d9390 | 2991 | cpu_src2 = get_src2(insn, cpu_src2); |
cf495bcf FB |
2992 | if (xop < 0x20) { |
2993 | switch (xop & ~0x10) { | |
2994 | case 0x0: | |
2995 | if (xop & 0x10) | |
6ae20372 | 2996 | gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf | 2997 | else |
6ae20372 | 2998 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf FB |
2999 | break; |
3000 | case 0x1: | |
6ae20372 | 3001 | tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf | 3002 | if (xop & 0x10) |
6ae20372 | 3003 | gen_op_logic_cc(cpu_dst); |
cf495bcf FB |
3004 | break; |
3005 | case 0x2: | |
6ae20372 | 3006 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); |
0f8a249a | 3007 | if (xop & 0x10) |
6ae20372 | 3008 | gen_op_logic_cc(cpu_dst); |
0f8a249a | 3009 | break; |
cf495bcf | 3010 | case 0x3: |
6ae20372 | 3011 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf | 3012 | if (xop & 0x10) |
6ae20372 | 3013 | gen_op_logic_cc(cpu_dst); |
cf495bcf FB |
3014 | break; |
3015 | case 0x4: | |
3016 | if (xop & 0x10) | |
6ae20372 | 3017 | gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf | 3018 | else |
6ae20372 | 3019 | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf FB |
3020 | break; |
3021 | case 0x5: | |
6ae20372 BS |
3022 | tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1); |
3023 | tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
cf495bcf | 3024 | if (xop & 0x10) |
6ae20372 | 3025 | gen_op_logic_cc(cpu_dst); |
cf495bcf FB |
3026 | break; |
3027 | case 0x6: | |
6ae20372 BS |
3028 | tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1); |
3029 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
cf495bcf | 3030 | if (xop & 0x10) |
6ae20372 | 3031 | gen_op_logic_cc(cpu_dst); |
cf495bcf FB |
3032 | break; |
3033 | case 0x7: | |
6ae20372 BS |
3034 | tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1); |
3035 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
cf495bcf | 3036 | if (xop & 0x10) |
6ae20372 | 3037 | gen_op_logic_cc(cpu_dst); |
cf495bcf FB |
3038 | break; |
3039 | case 0x8: | |
cf495bcf | 3040 | if (xop & 0x10) |
6ae20372 | 3041 | gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2); |
38bc628b | 3042 | else { |
dc99a3f2 | 3043 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
6ae20372 BS |
3044 | tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0); |
3045 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
38bc628b | 3046 | } |
cf495bcf | 3047 | break; |
ded3ab80 | 3048 | #ifdef TARGET_SPARC64 |
0f8a249a | 3049 | case 0x9: /* V9 mulx */ |
6ae20372 | 3050 | tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2); |
ded3ab80 PB |
3051 | break; |
3052 | #endif | |
cf495bcf | 3053 | case 0xa: |
64a88d5d | 3054 | CHECK_IU_FEATURE(dc, MUL); |
6ae20372 | 3055 | gen_op_umul(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf | 3056 | if (xop & 0x10) |
6ae20372 | 3057 | gen_op_logic_cc(cpu_dst); |
cf495bcf FB |
3058 | break; |
3059 | case 0xb: | |
64a88d5d | 3060 | CHECK_IU_FEATURE(dc, MUL); |
6ae20372 | 3061 | gen_op_smul(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf | 3062 | if (xop & 0x10) |
6ae20372 | 3063 | gen_op_logic_cc(cpu_dst); |
cf495bcf FB |
3064 | break; |
3065 | case 0xc: | |
cf495bcf | 3066 | if (xop & 0x10) |
6ae20372 | 3067 | gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2); |
38bc628b | 3068 | else { |
dc99a3f2 | 3069 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
6ae20372 BS |
3070 | tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0); |
3071 | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
38bc628b | 3072 | } |
cf495bcf | 3073 | break; |
ded3ab80 | 3074 | #ifdef TARGET_SPARC64 |
0f8a249a | 3075 | case 0xd: /* V9 udivx */ |
07bf2857 BS |
3076 | tcg_gen_mov_tl(cpu_cc_src, cpu_src1); |
3077 | tcg_gen_mov_tl(cpu_cc_src2, cpu_src2); | |
3078 | gen_trap_ifdivzero_tl(cpu_cc_src2); | |
3079 | tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2); | |
ded3ab80 PB |
3080 | break; |
3081 | #endif | |
cf495bcf | 3082 | case 0xe: |
64a88d5d | 3083 | CHECK_IU_FEATURE(dc, DIV); |
77f193da BS |
3084 | tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1, |
3085 | cpu_src2); | |
cf495bcf | 3086 | if (xop & 0x10) |
6ae20372 | 3087 | gen_op_div_cc(cpu_dst); |
cf495bcf FB |
3088 | break; |
3089 | case 0xf: | |
64a88d5d | 3090 | CHECK_IU_FEATURE(dc, DIV); |
77f193da BS |
3091 | tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1, |
3092 | cpu_src2); | |
cf495bcf | 3093 | if (xop & 0x10) |
6ae20372 | 3094 | gen_op_div_cc(cpu_dst); |
cf495bcf FB |
3095 | break; |
3096 | default: | |
3097 | goto illegal_insn; | |
3098 | } | |
6ae20372 | 3099 | gen_movl_TN_reg(rd, cpu_dst); |
cf495bcf FB |
3100 | } else { |
3101 | switch (xop) { | |
0f8a249a | 3102 | case 0x20: /* taddcc */ |
6ae20372 BS |
3103 | gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2); |
3104 | gen_movl_TN_reg(rd, cpu_dst); | |
0f8a249a BS |
3105 | break; |
3106 | case 0x21: /* tsubcc */ | |
6ae20372 BS |
3107 | gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2); |
3108 | gen_movl_TN_reg(rd, cpu_dst); | |
0f8a249a BS |
3109 | break; |
3110 | case 0x22: /* taddcctv */ | |
6ae20372 BS |
3111 | save_state(dc, cpu_cond); |
3112 | gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2); | |
3113 | gen_movl_TN_reg(rd, cpu_dst); | |
0f8a249a BS |
3114 | break; |
3115 | case 0x23: /* tsubcctv */ | |
6ae20372 BS |
3116 | save_state(dc, cpu_cond); |
3117 | gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2); | |
3118 | gen_movl_TN_reg(rd, cpu_dst); | |
0f8a249a | 3119 | break; |
cf495bcf | 3120 | case 0x24: /* mulscc */ |
6ae20372 BS |
3121 | gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2); |
3122 | gen_movl_TN_reg(rd, cpu_dst); | |
cf495bcf | 3123 | break; |
83469015 | 3124 | #ifndef TARGET_SPARC64 |
0f8a249a | 3125 | case 0x25: /* sll */ |
e35298cd BS |
3126 | if (IS_IMM) { /* immediate */ |
3127 | rs2 = GET_FIELDs(insn, 20, 31); | |
3128 | tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f); | |
3129 | } else { /* register */ | |
3130 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); | |
3131 | tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
3132 | } | |
6ae20372 | 3133 | gen_movl_TN_reg(rd, cpu_dst); |
cf495bcf | 3134 | break; |
83469015 | 3135 | case 0x26: /* srl */ |
e35298cd BS |
3136 | if (IS_IMM) { /* immediate */ |
3137 | rs2 = GET_FIELDs(insn, 20, 31); | |
3138 | tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f); | |
3139 | } else { /* register */ | |
3140 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); | |
3141 | tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
3142 | } | |
6ae20372 | 3143 | gen_movl_TN_reg(rd, cpu_dst); |
cf495bcf | 3144 | break; |
83469015 | 3145 | case 0x27: /* sra */ |
e35298cd BS |
3146 | if (IS_IMM) { /* immediate */ |
3147 | rs2 = GET_FIELDs(insn, 20, 31); | |
3148 | tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f); | |
3149 | } else { /* register */ | |
3150 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); | |
3151 | tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
3152 | } | |
6ae20372 | 3153 | gen_movl_TN_reg(rd, cpu_dst); |
cf495bcf | 3154 | break; |
83469015 | 3155 | #endif |
cf495bcf FB |
3156 | case 0x30: |
3157 | { | |
cf495bcf | 3158 | switch(rd) { |
3475187d | 3159 | case 0: /* wry */ |
ece43b8d BS |
3160 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3161 | tcg_gen_st_tl(cpu_tmp0, cpu_env, | |
77f193da | 3162 | offsetof(CPUSPARCState, y)); |
cf495bcf | 3163 | break; |
65fe7b09 BS |
3164 | #ifndef TARGET_SPARC64 |
3165 | case 0x01 ... 0x0f: /* undefined in the | |
3166 | SPARCv8 manual, nop | |
3167 | on the microSPARC | |
3168 | II */ | |
3169 | case 0x10 ... 0x1f: /* implementation-dependent | |
3170 | in the SPARCv8 | |
3171 | manual, nop on the | |
3172 | microSPARC II */ | |
3173 | break; | |
3174 | #else | |
0f8a249a | 3175 | case 0x2: /* V9 wrccr */ |
6ae20372 BS |
3176 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3177 | tcg_gen_helper_0_1(helper_wrccr, cpu_dst); | |
0f8a249a BS |
3178 | break; |
3179 | case 0x3: /* V9 wrasi */ | |
6ae20372 BS |
3180 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3181 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); | |
77f193da BS |
3182 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3183 | offsetof(CPUSPARCState, asi)); | |
0f8a249a BS |
3184 | break; |
3185 | case 0x6: /* V9 wrfprs */ | |
6ae20372 BS |
3186 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3187 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); | |
77f193da BS |
3188 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3189 | offsetof(CPUSPARCState, fprs)); | |
6ae20372 | 3190 | save_state(dc, cpu_cond); |
3299908c | 3191 | gen_op_next_insn(); |
57fec1fe | 3192 | tcg_gen_exit_tb(0); |
3299908c | 3193 | dc->is_br = 1; |
0f8a249a BS |
3194 | break; |
3195 | case 0xf: /* V9 sir, nop if user */ | |
3475187d | 3196 | #if !defined(CONFIG_USER_ONLY) |
0f8a249a | 3197 | if (supervisor(dc)) |
1a2fb1c0 | 3198 | ; // XXX |
3475187d | 3199 | #endif |
0f8a249a BS |
3200 | break; |
3201 | case 0x13: /* Graphics Status */ | |
6ae20372 | 3202 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
725cb90b | 3203 | goto jmp_insn; |
ece43b8d BS |
3204 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3205 | tcg_gen_st_tl(cpu_tmp0, cpu_env, | |
77f193da | 3206 | offsetof(CPUSPARCState, gsr)); |
0f8a249a BS |
3207 | break; |
3208 | case 0x17: /* Tick compare */ | |
83469015 | 3209 | #if !defined(CONFIG_USER_ONLY) |
0f8a249a BS |
3210 | if (!supervisor(dc)) |
3211 | goto illegal_insn; | |
83469015 | 3212 | #endif |
ccd4a219 BS |
3213 | { |
3214 | TCGv r_tickptr; | |
3215 | ||
ece43b8d | 3216 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, |
6ae20372 | 3217 | cpu_src2); |
ece43b8d | 3218 | tcg_gen_st_tl(cpu_tmp0, cpu_env, |
77f193da BS |
3219 | offsetof(CPUSPARCState, |
3220 | tick_cmpr)); | |
ccd4a219 BS |
3221 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3222 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
3223 | offsetof(CPUState, tick)); | |
3224 | tcg_gen_helper_0_2(helper_tick_set_limit, | |
ece43b8d | 3225 | r_tickptr, cpu_tmp0); |
2ea815ca | 3226 | tcg_temp_free(r_tickptr); |
ccd4a219 | 3227 | } |
0f8a249a BS |
3228 | break; |
3229 | case 0x18: /* System tick */ | |
83469015 | 3230 | #if !defined(CONFIG_USER_ONLY) |
0f8a249a BS |
3231 | if (!supervisor(dc)) |
3232 | goto illegal_insn; | |
83469015 | 3233 | #endif |
ccd4a219 BS |
3234 | { |
3235 | TCGv r_tickptr; | |
3236 | ||
6ae20372 BS |
3237 | tcg_gen_xor_tl(cpu_dst, cpu_src1, |
3238 | cpu_src2); | |
ccd4a219 BS |
3239 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3240 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
3241 | offsetof(CPUState, stick)); | |
3242 | tcg_gen_helper_0_2(helper_tick_set_count, | |
6ae20372 | 3243 | r_tickptr, cpu_dst); |
2ea815ca | 3244 | tcg_temp_free(r_tickptr); |
ccd4a219 | 3245 | } |
0f8a249a BS |
3246 | break; |
3247 | case 0x19: /* System tick compare */ | |
83469015 | 3248 | #if !defined(CONFIG_USER_ONLY) |
0f8a249a BS |
3249 | if (!supervisor(dc)) |
3250 | goto illegal_insn; | |
3475187d | 3251 | #endif |
ccd4a219 BS |
3252 | { |
3253 | TCGv r_tickptr; | |
3254 | ||
ece43b8d | 3255 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, |
6ae20372 | 3256 | cpu_src2); |
ece43b8d | 3257 | tcg_gen_st_tl(cpu_tmp0, cpu_env, |
77f193da BS |
3258 | offsetof(CPUSPARCState, |
3259 | stick_cmpr)); | |
ccd4a219 BS |
3260 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3261 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
3262 | offsetof(CPUState, stick)); | |
3263 | tcg_gen_helper_0_2(helper_tick_set_limit, | |
ece43b8d | 3264 | r_tickptr, cpu_tmp0); |
2ea815ca | 3265 | tcg_temp_free(r_tickptr); |
ccd4a219 | 3266 | } |
0f8a249a | 3267 | break; |
83469015 | 3268 | |
0f8a249a | 3269 | case 0x10: /* Performance Control */ |
77f193da BS |
3270 | case 0x11: /* Performance Instrumentation |
3271 | Counter */ | |
0f8a249a BS |
3272 | case 0x12: /* Dispatch Control */ |
3273 | case 0x14: /* Softint set */ | |
3274 | case 0x15: /* Softint clear */ | |
3275 | case 0x16: /* Softint write */ | |
83469015 | 3276 | #endif |
3475187d | 3277 | default: |
cf495bcf FB |
3278 | goto illegal_insn; |
3279 | } | |
3280 | } | |
3281 | break; | |
e8af50a3 | 3282 | #if !defined(CONFIG_USER_ONLY) |
af7bf89b | 3283 | case 0x31: /* wrpsr, V9 saved, restored */ |
e8af50a3 | 3284 | { |
0f8a249a BS |
3285 | if (!supervisor(dc)) |
3286 | goto priv_insn; | |
3475187d | 3287 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
3288 | switch (rd) { |
3289 | case 0: | |
72a9747b | 3290 | tcg_gen_helper_0_0(helper_saved); |
0f8a249a BS |
3291 | break; |
3292 | case 1: | |
72a9747b | 3293 | tcg_gen_helper_0_0(helper_restored); |
0f8a249a | 3294 | break; |
e9ebed4d BS |
3295 | case 2: /* UA2005 allclean */ |
3296 | case 3: /* UA2005 otherw */ | |
3297 | case 4: /* UA2005 normalw */ | |
3298 | case 5: /* UA2005 invalw */ | |
3299 | // XXX | |
0f8a249a | 3300 | default: |
3475187d FB |
3301 | goto illegal_insn; |
3302 | } | |
3303 | #else | |
6ae20372 BS |
3304 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3305 | tcg_gen_helper_0_1(helper_wrpsr, cpu_dst); | |
3306 | save_state(dc, cpu_cond); | |
9e61bde5 | 3307 | gen_op_next_insn(); |
57fec1fe | 3308 | tcg_gen_exit_tb(0); |
0f8a249a | 3309 | dc->is_br = 1; |
3475187d | 3310 | #endif |
e8af50a3 FB |
3311 | } |
3312 | break; | |
af7bf89b | 3313 | case 0x32: /* wrwim, V9 wrpr */ |
e8af50a3 | 3314 | { |
0f8a249a BS |
3315 | if (!supervisor(dc)) |
3316 | goto priv_insn; | |
ece43b8d | 3317 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3475187d | 3318 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
3319 | switch (rd) { |
3320 | case 0: // tpc | |
375ee38b BS |
3321 | { |
3322 | TCGv r_tsptr; | |
3323 | ||
3324 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
3325 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
3326 | offsetof(CPUState, tsptr)); | |
ece43b8d | 3327 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
375ee38b | 3328 | offsetof(trap_state, tpc)); |
2ea815ca | 3329 | tcg_temp_free(r_tsptr); |
375ee38b | 3330 | } |
0f8a249a BS |
3331 | break; |
3332 | case 1: // tnpc | |
375ee38b BS |
3333 | { |
3334 | TCGv r_tsptr; | |
3335 | ||
3336 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
3337 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
3338 | offsetof(CPUState, tsptr)); | |
ece43b8d | 3339 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
375ee38b | 3340 | offsetof(trap_state, tnpc)); |
2ea815ca | 3341 | tcg_temp_free(r_tsptr); |
375ee38b | 3342 | } |
0f8a249a BS |
3343 | break; |
3344 | case 2: // tstate | |
375ee38b BS |
3345 | { |
3346 | TCGv r_tsptr; | |
3347 | ||
3348 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
3349 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
3350 | offsetof(CPUState, tsptr)); | |
ece43b8d | 3351 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
77f193da BS |
3352 | offsetof(trap_state, |
3353 | tstate)); | |
2ea815ca | 3354 | tcg_temp_free(r_tsptr); |
375ee38b | 3355 | } |
0f8a249a BS |
3356 | break; |
3357 | case 3: // tt | |
375ee38b BS |
3358 | { |
3359 | TCGv r_tsptr; | |
3360 | ||
3361 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
3362 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
3363 | offsetof(CPUState, tsptr)); | |
ece43b8d | 3364 | tcg_gen_st_i32(cpu_tmp0, r_tsptr, |
375ee38b | 3365 | offsetof(trap_state, tt)); |
2ea815ca | 3366 | tcg_temp_free(r_tsptr); |
375ee38b | 3367 | } |
0f8a249a BS |
3368 | break; |
3369 | case 4: // tick | |
ccd4a219 BS |
3370 | { |
3371 | TCGv r_tickptr; | |
3372 | ||
3373 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
3374 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
3375 | offsetof(CPUState, tick)); | |
3376 | tcg_gen_helper_0_2(helper_tick_set_count, | |
ece43b8d | 3377 | r_tickptr, cpu_tmp0); |
2ea815ca | 3378 | tcg_temp_free(r_tickptr); |
ccd4a219 | 3379 | } |
0f8a249a BS |
3380 | break; |
3381 | case 5: // tba | |
ece43b8d | 3382 | tcg_gen_st_tl(cpu_tmp0, cpu_env, |
77f193da | 3383 | offsetof(CPUSPARCState, tbr)); |
0f8a249a BS |
3384 | break; |
3385 | case 6: // pstate | |
6ae20372 | 3386 | save_state(dc, cpu_cond); |
ece43b8d | 3387 | tcg_gen_helper_0_1(helper_wrpstate, cpu_tmp0); |
ded3ab80 | 3388 | gen_op_next_insn(); |
57fec1fe | 3389 | tcg_gen_exit_tb(0); |
ded3ab80 | 3390 | dc->is_br = 1; |
0f8a249a BS |
3391 | break; |
3392 | case 7: // tl | |
ece43b8d | 3393 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
77f193da BS |
3394 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3395 | offsetof(CPUSPARCState, tl)); | |
0f8a249a BS |
3396 | break; |
3397 | case 8: // pil | |
ece43b8d | 3398 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
77f193da BS |
3399 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3400 | offsetof(CPUSPARCState, | |
3401 | psrpil)); | |
0f8a249a BS |
3402 | break; |
3403 | case 9: // cwp | |
ece43b8d | 3404 | tcg_gen_helper_0_1(helper_wrcwp, cpu_tmp0); |
0f8a249a BS |
3405 | break; |
3406 | case 10: // cansave | |
ece43b8d | 3407 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
77f193da BS |
3408 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3409 | offsetof(CPUSPARCState, | |
3410 | cansave)); | |
0f8a249a BS |
3411 | break; |
3412 | case 11: // canrestore | |
ece43b8d | 3413 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
77f193da BS |
3414 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3415 | offsetof(CPUSPARCState, | |
3416 | canrestore)); | |
0f8a249a BS |
3417 | break; |
3418 | case 12: // cleanwin | |
ece43b8d | 3419 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
77f193da BS |
3420 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3421 | offsetof(CPUSPARCState, | |
3422 | cleanwin)); | |
0f8a249a BS |
3423 | break; |
3424 | case 13: // otherwin | |
ece43b8d | 3425 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
77f193da BS |
3426 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3427 | offsetof(CPUSPARCState, | |
3428 | otherwin)); | |
0f8a249a BS |
3429 | break; |
3430 | case 14: // wstate | |
ece43b8d | 3431 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
77f193da BS |
3432 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3433 | offsetof(CPUSPARCState, | |
3434 | wstate)); | |
0f8a249a | 3435 | break; |
e9ebed4d | 3436 | case 16: // UA2005 gl |
ece43b8d | 3437 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
77f193da BS |
3438 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3439 | offsetof(CPUSPARCState, gl)); | |
e9ebed4d BS |
3440 | break; |
3441 | case 26: // UA2005 strand status | |
3442 | if (!hypervisor(dc)) | |
3443 | goto priv_insn; | |
ece43b8d | 3444 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
77f193da BS |
3445 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3446 | offsetof(CPUSPARCState, ssr)); | |
e9ebed4d | 3447 | break; |
0f8a249a BS |
3448 | default: |
3449 | goto illegal_insn; | |
3450 | } | |
3475187d | 3451 | #else |
ece43b8d | 3452 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
77f193da BS |
3453 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3454 | offsetof(CPUSPARCState, wim)); | |
3475187d | 3455 | #endif |
e8af50a3 FB |
3456 | } |
3457 | break; | |
e9ebed4d | 3458 | case 0x33: /* wrtbr, UA2005 wrhpr */ |
e8af50a3 | 3459 | { |
e9ebed4d | 3460 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
3461 | if (!supervisor(dc)) |
3462 | goto priv_insn; | |
ece43b8d BS |
3463 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3464 | tcg_gen_st_tl(cpu_tmp0, cpu_env, | |
77f193da | 3465 | offsetof(CPUSPARCState, tbr)); |
e9ebed4d BS |
3466 | #else |
3467 | if (!hypervisor(dc)) | |
3468 | goto priv_insn; | |
ece43b8d | 3469 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
e9ebed4d BS |
3470 | switch (rd) { |
3471 | case 0: // hpstate | |
3472 | // XXX gen_op_wrhpstate(); | |
6ae20372 | 3473 | save_state(dc, cpu_cond); |
e9ebed4d | 3474 | gen_op_next_insn(); |
57fec1fe | 3475 | tcg_gen_exit_tb(0); |
e9ebed4d BS |
3476 | dc->is_br = 1; |
3477 | break; | |
3478 | case 1: // htstate | |
3479 | // XXX gen_op_wrhtstate(); | |
3480 | break; | |
3481 | case 3: // hintp | |
ece43b8d | 3482 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
77f193da BS |
3483 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3484 | offsetof(CPUSPARCState, hintp)); | |
e9ebed4d BS |
3485 | break; |
3486 | case 5: // htba | |
ece43b8d | 3487 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
77f193da BS |
3488 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3489 | offsetof(CPUSPARCState, htba)); | |
e9ebed4d BS |
3490 | break; |
3491 | case 31: // hstick_cmpr | |
ccd4a219 BS |
3492 | { |
3493 | TCGv r_tickptr; | |
3494 | ||
ece43b8d | 3495 | tcg_gen_st_tl(cpu_tmp0, cpu_env, |
77f193da BS |
3496 | offsetof(CPUSPARCState, |
3497 | hstick_cmpr)); | |
ccd4a219 BS |
3498 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3499 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
3500 | offsetof(CPUState, hstick)); | |
3501 | tcg_gen_helper_0_2(helper_tick_set_limit, | |
ece43b8d | 3502 | r_tickptr, cpu_tmp0); |
2ea815ca | 3503 | tcg_temp_free(r_tickptr); |
ccd4a219 | 3504 | } |
e9ebed4d BS |
3505 | break; |
3506 | case 6: // hver readonly | |
3507 | default: | |
3508 | goto illegal_insn; | |
3509 | } | |
3510 | #endif | |
e8af50a3 FB |
3511 | } |
3512 | break; | |
3513 | #endif | |
3475187d | 3514 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
3515 | case 0x2c: /* V9 movcc */ |
3516 | { | |
3517 | int cc = GET_FIELD_SP(insn, 11, 12); | |
3518 | int cond = GET_FIELD_SP(insn, 14, 17); | |
748b9d8e | 3519 | TCGv r_cond; |
00f219bf BS |
3520 | int l1; |
3521 | ||
748b9d8e | 3522 | r_cond = tcg_temp_new(TCG_TYPE_TL); |
0f8a249a BS |
3523 | if (insn & (1 << 18)) { |
3524 | if (cc == 0) | |
748b9d8e | 3525 | gen_cond(r_cond, 0, cond); |
0f8a249a | 3526 | else if (cc == 2) |
748b9d8e | 3527 | gen_cond(r_cond, 1, cond); |
0f8a249a BS |
3528 | else |
3529 | goto illegal_insn; | |
3530 | } else { | |
748b9d8e | 3531 | gen_fcond(r_cond, cc, cond); |
0f8a249a | 3532 | } |
00f219bf BS |
3533 | |
3534 | l1 = gen_new_label(); | |
3535 | ||
cb63669a | 3536 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1); |
00f219bf | 3537 | if (IS_IMM) { /* immediate */ |
2ea815ca BS |
3538 | TCGv r_const; |
3539 | ||
00f219bf | 3540 | rs2 = GET_FIELD_SPs(insn, 0, 10); |
2ea815ca BS |
3541 | r_const = tcg_const_tl((int)rs2); |
3542 | gen_movl_TN_reg(rd, r_const); | |
3543 | tcg_temp_free(r_const); | |
00f219bf BS |
3544 | } else { |
3545 | rs2 = GET_FIELD_SP(insn, 0, 4); | |
9c6c6662 BS |
3546 | gen_movl_reg_TN(rs2, cpu_tmp0); |
3547 | gen_movl_TN_reg(rd, cpu_tmp0); | |
00f219bf | 3548 | } |
00f219bf | 3549 | gen_set_label(l1); |
2ea815ca | 3550 | tcg_temp_free(r_cond); |
0f8a249a BS |
3551 | break; |
3552 | } | |
3553 | case 0x2d: /* V9 sdivx */ | |
6ae20372 BS |
3554 | gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2); |
3555 | gen_movl_TN_reg(rd, cpu_dst); | |
0f8a249a BS |
3556 | break; |
3557 | case 0x2e: /* V9 popc */ | |
3558 | { | |
a49d9390 | 3559 | cpu_src2 = get_src2(insn, cpu_src2); |
6ae20372 BS |
3560 | tcg_gen_helper_1_1(helper_popc, cpu_dst, |
3561 | cpu_src2); | |
3562 | gen_movl_TN_reg(rd, cpu_dst); | |
0f8a249a BS |
3563 | } |
3564 | case 0x2f: /* V9 movr */ | |
3565 | { | |
3566 | int cond = GET_FIELD_SP(insn, 10, 12); | |
00f219bf BS |
3567 | int l1; |
3568 | ||
9322a4bf | 3569 | cpu_src1 = get_src1(insn, cpu_src1); |
00f219bf BS |
3570 | |
3571 | l1 = gen_new_label(); | |
3572 | ||
cb63669a PB |
3573 | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], |
3574 | cpu_src1, 0, l1); | |
0f8a249a | 3575 | if (IS_IMM) { /* immediate */ |
2ea815ca BS |
3576 | TCGv r_const; |
3577 | ||
0f8a249a | 3578 | rs2 = GET_FIELD_SPs(insn, 0, 9); |
2ea815ca BS |
3579 | r_const = tcg_const_tl((int)rs2); |
3580 | gen_movl_TN_reg(rd, r_const); | |
3581 | tcg_temp_free(r_const); | |
00f219bf | 3582 | } else { |
0f8a249a | 3583 | rs2 = GET_FIELD_SP(insn, 0, 4); |
9c6c6662 BS |
3584 | gen_movl_reg_TN(rs2, cpu_tmp0); |
3585 | gen_movl_TN_reg(rd, cpu_tmp0); | |
0f8a249a | 3586 | } |
00f219bf | 3587 | gen_set_label(l1); |
0f8a249a BS |
3588 | break; |
3589 | } | |
3590 | #endif | |
3591 | default: | |
3592 | goto illegal_insn; | |
3593 | } | |
3594 | } | |
3299908c BS |
3595 | } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ |
3596 | #ifdef TARGET_SPARC64 | |
3597 | int opf = GET_FIELD_SP(insn, 5, 13); | |
3598 | rs1 = GET_FIELD(insn, 13, 17); | |
3599 | rs2 = GET_FIELD(insn, 27, 31); | |
6ae20372 | 3600 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
e9ebed4d | 3601 | goto jmp_insn; |
3299908c BS |
3602 | |
3603 | switch (opf) { | |
e9ebed4d BS |
3604 | case 0x000: /* VIS I edge8cc */ |
3605 | case 0x001: /* VIS II edge8n */ | |
3606 | case 0x002: /* VIS I edge8lcc */ | |
3607 | case 0x003: /* VIS II edge8ln */ | |
3608 | case 0x004: /* VIS I edge16cc */ | |
3609 | case 0x005: /* VIS II edge16n */ | |
3610 | case 0x006: /* VIS I edge16lcc */ | |
3611 | case 0x007: /* VIS II edge16ln */ | |
3612 | case 0x008: /* VIS I edge32cc */ | |
3613 | case 0x009: /* VIS II edge32n */ | |
3614 | case 0x00a: /* VIS I edge32lcc */ | |
3615 | case 0x00b: /* VIS II edge32ln */ | |
3616 | // XXX | |
3617 | goto illegal_insn; | |
3618 | case 0x010: /* VIS I array8 */ | |
64a88d5d | 3619 | CHECK_FPU_FEATURE(dc, VIS1); |
9322a4bf | 3620 | cpu_src1 = get_src1(insn, cpu_src1); |
6ae20372 BS |
3621 | gen_movl_reg_TN(rs2, cpu_src2); |
3622 | tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1, | |
3623 | cpu_src2); | |
3624 | gen_movl_TN_reg(rd, cpu_dst); | |
e9ebed4d BS |
3625 | break; |
3626 | case 0x012: /* VIS I array16 */ | |
64a88d5d | 3627 | CHECK_FPU_FEATURE(dc, VIS1); |
9322a4bf | 3628 | cpu_src1 = get_src1(insn, cpu_src1); |
6ae20372 BS |
3629 | gen_movl_reg_TN(rs2, cpu_src2); |
3630 | tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1, | |
3631 | cpu_src2); | |
3632 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 1); | |
3633 | gen_movl_TN_reg(rd, cpu_dst); | |
e9ebed4d BS |
3634 | break; |
3635 | case 0x014: /* VIS I array32 */ | |
64a88d5d | 3636 | CHECK_FPU_FEATURE(dc, VIS1); |
9322a4bf | 3637 | cpu_src1 = get_src1(insn, cpu_src1); |
6ae20372 BS |
3638 | gen_movl_reg_TN(rs2, cpu_src2); |
3639 | tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1, | |
3640 | cpu_src2); | |
3641 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 2); | |
3642 | gen_movl_TN_reg(rd, cpu_dst); | |
e9ebed4d | 3643 | break; |
3299908c | 3644 | case 0x018: /* VIS I alignaddr */ |
64a88d5d | 3645 | CHECK_FPU_FEATURE(dc, VIS1); |
9322a4bf | 3646 | cpu_src1 = get_src1(insn, cpu_src1); |
6ae20372 BS |
3647 | gen_movl_reg_TN(rs2, cpu_src2); |
3648 | tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1, | |
3649 | cpu_src2); | |
3650 | gen_movl_TN_reg(rd, cpu_dst); | |
3299908c | 3651 | break; |
e9ebed4d | 3652 | case 0x019: /* VIS II bmask */ |
3299908c | 3653 | case 0x01a: /* VIS I alignaddrl */ |
3299908c | 3654 | // XXX |
e9ebed4d BS |
3655 | goto illegal_insn; |
3656 | case 0x020: /* VIS I fcmple16 */ | |
64a88d5d | 3657 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3658 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3659 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3660 | tcg_gen_helper_0_0(helper_fcmple16); |
2382dc6b | 3661 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3662 | break; |
3663 | case 0x022: /* VIS I fcmpne16 */ | |
64a88d5d | 3664 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3665 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3666 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3667 | tcg_gen_helper_0_0(helper_fcmpne16); |
2382dc6b | 3668 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3299908c | 3669 | break; |
e9ebed4d | 3670 | case 0x024: /* VIS I fcmple32 */ |
64a88d5d | 3671 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3672 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3673 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3674 | tcg_gen_helper_0_0(helper_fcmple32); |
2382dc6b | 3675 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3676 | break; |
3677 | case 0x026: /* VIS I fcmpne32 */ | |
64a88d5d | 3678 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3679 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3680 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3681 | tcg_gen_helper_0_0(helper_fcmpne32); |
2382dc6b | 3682 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3683 | break; |
3684 | case 0x028: /* VIS I fcmpgt16 */ | |
64a88d5d | 3685 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3686 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3687 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3688 | tcg_gen_helper_0_0(helper_fcmpgt16); |
2382dc6b | 3689 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3690 | break; |
3691 | case 0x02a: /* VIS I fcmpeq16 */ | |
64a88d5d | 3692 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3693 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3694 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3695 | tcg_gen_helper_0_0(helper_fcmpeq16); |
2382dc6b | 3696 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3697 | break; |
3698 | case 0x02c: /* VIS I fcmpgt32 */ | |
64a88d5d | 3699 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3700 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3701 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3702 | tcg_gen_helper_0_0(helper_fcmpgt32); |
2382dc6b | 3703 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3704 | break; |
3705 | case 0x02e: /* VIS I fcmpeq32 */ | |
64a88d5d | 3706 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3707 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3708 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3709 | tcg_gen_helper_0_0(helper_fcmpeq32); |
2382dc6b | 3710 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3711 | break; |
3712 | case 0x031: /* VIS I fmul8x16 */ | |
64a88d5d | 3713 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3714 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3715 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3716 | tcg_gen_helper_0_0(helper_fmul8x16); |
2382dc6b | 3717 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3718 | break; |
3719 | case 0x033: /* VIS I fmul8x16au */ | |
64a88d5d | 3720 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3721 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3722 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3723 | tcg_gen_helper_0_0(helper_fmul8x16au); |
2382dc6b | 3724 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3725 | break; |
3726 | case 0x035: /* VIS I fmul8x16al */ | |
64a88d5d | 3727 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3728 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3729 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3730 | tcg_gen_helper_0_0(helper_fmul8x16al); |
2382dc6b | 3731 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3732 | break; |
3733 | case 0x036: /* VIS I fmul8sux16 */ | |
64a88d5d | 3734 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3735 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3736 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3737 | tcg_gen_helper_0_0(helper_fmul8sux16); |
2382dc6b | 3738 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3739 | break; |
3740 | case 0x037: /* VIS I fmul8ulx16 */ | |
64a88d5d | 3741 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3742 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3743 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3744 | tcg_gen_helper_0_0(helper_fmul8ulx16); |
2382dc6b | 3745 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3746 | break; |
3747 | case 0x038: /* VIS I fmuld8sux16 */ | |
64a88d5d | 3748 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3749 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3750 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3751 | tcg_gen_helper_0_0(helper_fmuld8sux16); |
2382dc6b | 3752 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3753 | break; |
3754 | case 0x039: /* VIS I fmuld8ulx16 */ | |
64a88d5d | 3755 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3756 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3757 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3758 | tcg_gen_helper_0_0(helper_fmuld8ulx16); |
2382dc6b | 3759 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3760 | break; |
3761 | case 0x03a: /* VIS I fpack32 */ | |
3762 | case 0x03b: /* VIS I fpack16 */ | |
3763 | case 0x03d: /* VIS I fpackfix */ | |
3764 | case 0x03e: /* VIS I pdist */ | |
3765 | // XXX | |
3766 | goto illegal_insn; | |
3299908c | 3767 | case 0x048: /* VIS I faligndata */ |
64a88d5d | 3768 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3769 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3770 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3771 | tcg_gen_helper_0_0(helper_faligndata); |
2382dc6b | 3772 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3299908c | 3773 | break; |
e9ebed4d | 3774 | case 0x04b: /* VIS I fpmerge */ |
64a88d5d | 3775 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3776 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3777 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3778 | tcg_gen_helper_0_0(helper_fpmerge); |
2382dc6b | 3779 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3780 | break; |
3781 | case 0x04c: /* VIS II bshuffle */ | |
3782 | // XXX | |
3783 | goto illegal_insn; | |
3784 | case 0x04d: /* VIS I fexpand */ | |
64a88d5d | 3785 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3786 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3787 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3788 | tcg_gen_helper_0_0(helper_fexpand); |
2382dc6b | 3789 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3790 | break; |
3791 | case 0x050: /* VIS I fpadd16 */ | |
64a88d5d | 3792 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3793 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3794 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3795 | tcg_gen_helper_0_0(helper_fpadd16); |
2382dc6b | 3796 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3797 | break; |
3798 | case 0x051: /* VIS I fpadd16s */ | |
64a88d5d | 3799 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3800 | gen_op_load_fpr_FT0(rs1); |
3801 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3802 | tcg_gen_helper_0_0(helper_fpadd16s); |
e9ebed4d BS |
3803 | gen_op_store_FT0_fpr(rd); |
3804 | break; | |
3805 | case 0x052: /* VIS I fpadd32 */ | |
64a88d5d | 3806 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3807 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3808 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3809 | tcg_gen_helper_0_0(helper_fpadd32); |
2382dc6b | 3810 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3811 | break; |
3812 | case 0x053: /* VIS I fpadd32s */ | |
64a88d5d | 3813 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3814 | gen_op_load_fpr_FT0(rs1); |
3815 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3816 | tcg_gen_helper_0_0(helper_fpadd32s); |
e9ebed4d BS |
3817 | gen_op_store_FT0_fpr(rd); |
3818 | break; | |
3819 | case 0x054: /* VIS I fpsub16 */ | |
64a88d5d | 3820 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3821 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3822 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3823 | tcg_gen_helper_0_0(helper_fpsub16); |
2382dc6b | 3824 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3825 | break; |
3826 | case 0x055: /* VIS I fpsub16s */ | |
64a88d5d | 3827 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3828 | gen_op_load_fpr_FT0(rs1); |
3829 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3830 | tcg_gen_helper_0_0(helper_fpsub16s); |
e9ebed4d BS |
3831 | gen_op_store_FT0_fpr(rd); |
3832 | break; | |
3833 | case 0x056: /* VIS I fpsub32 */ | |
64a88d5d | 3834 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3835 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3836 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3837 | tcg_gen_helper_0_0(helper_fpadd32); |
2382dc6b | 3838 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3839 | break; |
3840 | case 0x057: /* VIS I fpsub32s */ | |
64a88d5d | 3841 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3842 | gen_op_load_fpr_FT0(rs1); |
3843 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3844 | tcg_gen_helper_0_0(helper_fpsub32s); |
e9ebed4d BS |
3845 | gen_op_store_FT0_fpr(rd); |
3846 | break; | |
3299908c | 3847 | case 0x060: /* VIS I fzero */ |
64a88d5d | 3848 | CHECK_FPU_FEATURE(dc, VIS1); |
44e7757c | 3849 | tcg_gen_helper_0_0(helper_movl_DT0_0); |
2382dc6b | 3850 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3299908c BS |
3851 | break; |
3852 | case 0x061: /* VIS I fzeros */ | |
64a88d5d | 3853 | CHECK_FPU_FEATURE(dc, VIS1); |
44e7757c | 3854 | tcg_gen_helper_0_0(helper_movl_FT0_0); |
3299908c BS |
3855 | gen_op_store_FT0_fpr(rd); |
3856 | break; | |
e9ebed4d | 3857 | case 0x062: /* VIS I fnor */ |
64a88d5d | 3858 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3859 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3860 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3861 | tcg_gen_helper_0_0(helper_fnor); |
2382dc6b | 3862 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3863 | break; |
3864 | case 0x063: /* VIS I fnors */ | |
64a88d5d | 3865 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3866 | gen_op_load_fpr_FT0(rs1); |
3867 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3868 | tcg_gen_helper_0_0(helper_fnors); |
e9ebed4d BS |
3869 | gen_op_store_FT0_fpr(rd); |
3870 | break; | |
3871 | case 0x064: /* VIS I fandnot2 */ | |
64a88d5d | 3872 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3873 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
3874 | gen_op_load_fpr_DT0(DFPREG(rs2)); | |
44e7757c | 3875 | tcg_gen_helper_0_0(helper_fandnot); |
2382dc6b | 3876 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3877 | break; |
3878 | case 0x065: /* VIS I fandnot2s */ | |
64a88d5d | 3879 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3880 | gen_op_load_fpr_FT1(rs1); |
3881 | gen_op_load_fpr_FT0(rs2); | |
44e7757c | 3882 | tcg_gen_helper_0_0(helper_fandnots); |
e9ebed4d BS |
3883 | gen_op_store_FT0_fpr(rd); |
3884 | break; | |
3885 | case 0x066: /* VIS I fnot2 */ | |
64a88d5d | 3886 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b | 3887 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
44e7757c | 3888 | tcg_gen_helper_0_0(helper_fnot); |
2382dc6b | 3889 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3890 | break; |
3891 | case 0x067: /* VIS I fnot2s */ | |
64a88d5d | 3892 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d | 3893 | gen_op_load_fpr_FT1(rs2); |
44e7757c | 3894 | tcg_gen_helper_0_0(helper_fnot); |
e9ebed4d BS |
3895 | gen_op_store_FT0_fpr(rd); |
3896 | break; | |
3897 | case 0x068: /* VIS I fandnot1 */ | |
64a88d5d | 3898 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3899 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3900 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3901 | tcg_gen_helper_0_0(helper_fandnot); |
2382dc6b | 3902 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3903 | break; |
3904 | case 0x069: /* VIS I fandnot1s */ | |
64a88d5d | 3905 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3906 | gen_op_load_fpr_FT0(rs1); |
3907 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3908 | tcg_gen_helper_0_0(helper_fandnots); |
e9ebed4d BS |
3909 | gen_op_store_FT0_fpr(rd); |
3910 | break; | |
3911 | case 0x06a: /* VIS I fnot1 */ | |
64a88d5d | 3912 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b | 3913 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
44e7757c | 3914 | tcg_gen_helper_0_0(helper_fnot); |
2382dc6b | 3915 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3916 | break; |
3917 | case 0x06b: /* VIS I fnot1s */ | |
64a88d5d | 3918 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d | 3919 | gen_op_load_fpr_FT1(rs1); |
44e7757c | 3920 | tcg_gen_helper_0_0(helper_fnot); |
e9ebed4d BS |
3921 | gen_op_store_FT0_fpr(rd); |
3922 | break; | |
3923 | case 0x06c: /* VIS I fxor */ | |
64a88d5d | 3924 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3925 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3926 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3927 | tcg_gen_helper_0_0(helper_fxor); |
2382dc6b | 3928 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3929 | break; |
3930 | case 0x06d: /* VIS I fxors */ | |
64a88d5d | 3931 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3932 | gen_op_load_fpr_FT0(rs1); |
3933 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3934 | tcg_gen_helper_0_0(helper_fxors); |
e9ebed4d BS |
3935 | gen_op_store_FT0_fpr(rd); |
3936 | break; | |
3937 | case 0x06e: /* VIS I fnand */ | |
64a88d5d | 3938 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3939 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3940 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3941 | tcg_gen_helper_0_0(helper_fnand); |
2382dc6b | 3942 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3943 | break; |
3944 | case 0x06f: /* VIS I fnands */ | |
64a88d5d | 3945 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3946 | gen_op_load_fpr_FT0(rs1); |
3947 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3948 | tcg_gen_helper_0_0(helper_fnands); |
e9ebed4d BS |
3949 | gen_op_store_FT0_fpr(rd); |
3950 | break; | |
3951 | case 0x070: /* VIS I fand */ | |
64a88d5d | 3952 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3953 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3954 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3955 | tcg_gen_helper_0_0(helper_fand); |
2382dc6b | 3956 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3957 | break; |
3958 | case 0x071: /* VIS I fands */ | |
64a88d5d | 3959 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3960 | gen_op_load_fpr_FT0(rs1); |
3961 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3962 | tcg_gen_helper_0_0(helper_fands); |
e9ebed4d BS |
3963 | gen_op_store_FT0_fpr(rd); |
3964 | break; | |
3965 | case 0x072: /* VIS I fxnor */ | |
64a88d5d | 3966 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3967 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3968 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3969 | tcg_gen_helper_0_0(helper_fxnor); |
2382dc6b | 3970 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3971 | break; |
3972 | case 0x073: /* VIS I fxnors */ | |
64a88d5d | 3973 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3974 | gen_op_load_fpr_FT0(rs1); |
3975 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3976 | tcg_gen_helper_0_0(helper_fxnors); |
e9ebed4d BS |
3977 | gen_op_store_FT0_fpr(rd); |
3978 | break; | |
3299908c | 3979 | case 0x074: /* VIS I fsrc1 */ |
64a88d5d | 3980 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3981 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3982 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
3299908c BS |
3983 | break; |
3984 | case 0x075: /* VIS I fsrc1s */ | |
64a88d5d | 3985 | CHECK_FPU_FEATURE(dc, VIS1); |
3299908c BS |
3986 | gen_op_load_fpr_FT0(rs1); |
3987 | gen_op_store_FT0_fpr(rd); | |
3988 | break; | |
e9ebed4d | 3989 | case 0x076: /* VIS I fornot2 */ |
64a88d5d | 3990 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3991 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
3992 | gen_op_load_fpr_DT0(DFPREG(rs2)); | |
44e7757c | 3993 | tcg_gen_helper_0_0(helper_fornot); |
2382dc6b | 3994 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3995 | break; |
3996 | case 0x077: /* VIS I fornot2s */ | |
64a88d5d | 3997 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3998 | gen_op_load_fpr_FT1(rs1); |
3999 | gen_op_load_fpr_FT0(rs2); | |
44e7757c | 4000 | tcg_gen_helper_0_0(helper_fornots); |
e9ebed4d BS |
4001 | gen_op_store_FT0_fpr(rd); |
4002 | break; | |
3299908c | 4003 | case 0x078: /* VIS I fsrc2 */ |
64a88d5d | 4004 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
4005 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
4006 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
3299908c BS |
4007 | break; |
4008 | case 0x079: /* VIS I fsrc2s */ | |
64a88d5d | 4009 | CHECK_FPU_FEATURE(dc, VIS1); |
3299908c BS |
4010 | gen_op_load_fpr_FT0(rs2); |
4011 | gen_op_store_FT0_fpr(rd); | |
4012 | break; | |
e9ebed4d | 4013 | case 0x07a: /* VIS I fornot1 */ |
64a88d5d | 4014 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
4015 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
4016 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 4017 | tcg_gen_helper_0_0(helper_fornot); |
2382dc6b | 4018 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
4019 | break; |
4020 | case 0x07b: /* VIS I fornot1s */ | |
64a88d5d | 4021 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
4022 | gen_op_load_fpr_FT0(rs1); |
4023 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 4024 | tcg_gen_helper_0_0(helper_fornots); |
e9ebed4d BS |
4025 | gen_op_store_FT0_fpr(rd); |
4026 | break; | |
4027 | case 0x07c: /* VIS I for */ | |
64a88d5d | 4028 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
4029 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
4030 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 4031 | tcg_gen_helper_0_0(helper_for); |
2382dc6b | 4032 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
4033 | break; |
4034 | case 0x07d: /* VIS I fors */ | |
64a88d5d | 4035 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
4036 | gen_op_load_fpr_FT0(rs1); |
4037 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 4038 | tcg_gen_helper_0_0(helper_fors); |
e9ebed4d BS |
4039 | gen_op_store_FT0_fpr(rd); |
4040 | break; | |
3299908c | 4041 | case 0x07e: /* VIS I fone */ |
64a88d5d | 4042 | CHECK_FPU_FEATURE(dc, VIS1); |
44e7757c | 4043 | tcg_gen_helper_0_0(helper_movl_DT0_1); |
2382dc6b | 4044 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3299908c BS |
4045 | break; |
4046 | case 0x07f: /* VIS I fones */ | |
64a88d5d | 4047 | CHECK_FPU_FEATURE(dc, VIS1); |
44e7757c | 4048 | tcg_gen_helper_0_0(helper_movl_FT0_1); |
3299908c BS |
4049 | gen_op_store_FT0_fpr(rd); |
4050 | break; | |
e9ebed4d BS |
4051 | case 0x080: /* VIS I shutdown */ |
4052 | case 0x081: /* VIS II siam */ | |
4053 | // XXX | |
4054 | goto illegal_insn; | |
3299908c BS |
4055 | default: |
4056 | goto illegal_insn; | |
4057 | } | |
4058 | #else | |
0f8a249a | 4059 | goto ncp_insn; |
3299908c BS |
4060 | #endif |
4061 | } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ | |
fcc72045 | 4062 | #ifdef TARGET_SPARC64 |
0f8a249a | 4063 | goto illegal_insn; |
fcc72045 | 4064 | #else |
0f8a249a | 4065 | goto ncp_insn; |
fcc72045 | 4066 | #endif |
3475187d | 4067 | #ifdef TARGET_SPARC64 |
0f8a249a | 4068 | } else if (xop == 0x39) { /* V9 return */ |
2ea815ca BS |
4069 | TCGv r_const; |
4070 | ||
6ae20372 | 4071 | save_state(dc, cpu_cond); |
9322a4bf | 4072 | cpu_src1 = get_src1(insn, cpu_src1); |
0f8a249a BS |
4073 | if (IS_IMM) { /* immediate */ |
4074 | rs2 = GET_FIELDs(insn, 19, 31); | |
6ae20372 | 4075 | tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2); |
0f8a249a | 4076 | } else { /* register */ |
3475187d | 4077 | rs2 = GET_FIELD(insn, 27, 31); |
0f8a249a | 4078 | if (rs2) { |
6ae20372 BS |
4079 | gen_movl_reg_TN(rs2, cpu_src2); |
4080 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); | |
6f551262 BS |
4081 | } else |
4082 | tcg_gen_mov_tl(cpu_dst, cpu_src1); | |
3475187d | 4083 | } |
72a9747b | 4084 | tcg_gen_helper_0_0(helper_restore); |
6ae20372 | 4085 | gen_mov_pc_npc(dc, cpu_cond); |
2ea815ca BS |
4086 | r_const = tcg_const_i32(3); |
4087 | tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const); | |
4088 | tcg_temp_free(r_const); | |
6ae20372 | 4089 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
0f8a249a BS |
4090 | dc->npc = DYNAMIC_PC; |
4091 | goto jmp_insn; | |
3475187d | 4092 | #endif |
0f8a249a | 4093 | } else { |
9322a4bf | 4094 | cpu_src1 = get_src1(insn, cpu_src1); |
0f8a249a BS |
4095 | if (IS_IMM) { /* immediate */ |
4096 | rs2 = GET_FIELDs(insn, 19, 31); | |
6ae20372 | 4097 | tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2); |
0f8a249a | 4098 | } else { /* register */ |
e80cfcfc | 4099 | rs2 = GET_FIELD(insn, 27, 31); |
0f8a249a | 4100 | if (rs2) { |
6ae20372 BS |
4101 | gen_movl_reg_TN(rs2, cpu_src2); |
4102 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); | |
6f551262 BS |
4103 | } else |
4104 | tcg_gen_mov_tl(cpu_dst, cpu_src1); | |
cf495bcf | 4105 | } |
0f8a249a BS |
4106 | switch (xop) { |
4107 | case 0x38: /* jmpl */ | |
4108 | { | |
2ea815ca BS |
4109 | TCGv r_const; |
4110 | ||
4111 | r_const = tcg_const_tl(dc->pc); | |
4112 | gen_movl_TN_reg(rd, r_const); | |
4113 | tcg_temp_free(r_const); | |
6ae20372 | 4114 | gen_mov_pc_npc(dc, cpu_cond); |
2ea815ca | 4115 | r_const = tcg_const_i32(3); |
77f193da | 4116 | tcg_gen_helper_0_2(helper_check_align, cpu_dst, |
2ea815ca BS |
4117 | r_const); |
4118 | tcg_temp_free(r_const); | |
6ae20372 | 4119 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
0f8a249a BS |
4120 | dc->npc = DYNAMIC_PC; |
4121 | } | |
4122 | goto jmp_insn; | |
3475187d | 4123 | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) |
0f8a249a BS |
4124 | case 0x39: /* rett, V9 return */ |
4125 | { | |
2ea815ca BS |
4126 | TCGv r_const; |
4127 | ||
0f8a249a BS |
4128 | if (!supervisor(dc)) |
4129 | goto priv_insn; | |
6ae20372 | 4130 | gen_mov_pc_npc(dc, cpu_cond); |
2ea815ca | 4131 | r_const = tcg_const_i32(3); |
77f193da | 4132 | tcg_gen_helper_0_2(helper_check_align, cpu_dst, |
2ea815ca BS |
4133 | r_const); |
4134 | tcg_temp_free(r_const); | |
6ae20372 | 4135 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
0f8a249a | 4136 | dc->npc = DYNAMIC_PC; |
1a2fb1c0 | 4137 | tcg_gen_helper_0_0(helper_rett); |
0f8a249a BS |
4138 | } |
4139 | goto jmp_insn; | |
4140 | #endif | |
4141 | case 0x3b: /* flush */ | |
64a88d5d BS |
4142 | if (!((dc)->features & CPU_FEATURE_FLUSH)) |
4143 | goto unimp_flush; | |
6ae20372 | 4144 | tcg_gen_helper_0_1(helper_flush, cpu_dst); |
0f8a249a BS |
4145 | break; |
4146 | case 0x3c: /* save */ | |
6ae20372 | 4147 | save_state(dc, cpu_cond); |
72a9747b | 4148 | tcg_gen_helper_0_0(helper_save); |
6ae20372 | 4149 | gen_movl_TN_reg(rd, cpu_dst); |
0f8a249a BS |
4150 | break; |
4151 | case 0x3d: /* restore */ | |
6ae20372 | 4152 | save_state(dc, cpu_cond); |
72a9747b | 4153 | tcg_gen_helper_0_0(helper_restore); |
6ae20372 | 4154 | gen_movl_TN_reg(rd, cpu_dst); |
0f8a249a | 4155 | break; |
3475187d | 4156 | #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64) |
0f8a249a BS |
4157 | case 0x3e: /* V9 done/retry */ |
4158 | { | |
4159 | switch (rd) { | |
4160 | case 0: | |
4161 | if (!supervisor(dc)) | |
4162 | goto priv_insn; | |
4163 | dc->npc = DYNAMIC_PC; | |
4164 | dc->pc = DYNAMIC_PC; | |
1a2fb1c0 | 4165 | tcg_gen_helper_0_0(helper_done); |
0f8a249a BS |
4166 | goto jmp_insn; |
4167 | case 1: | |
4168 | if (!supervisor(dc)) | |
4169 | goto priv_insn; | |
4170 | dc->npc = DYNAMIC_PC; | |
4171 | dc->pc = DYNAMIC_PC; | |
1a2fb1c0 | 4172 | tcg_gen_helper_0_0(helper_retry); |
0f8a249a BS |
4173 | goto jmp_insn; |
4174 | default: | |
4175 | goto illegal_insn; | |
4176 | } | |
4177 | } | |
4178 | break; | |
4179 | #endif | |
4180 | default: | |
4181 | goto illegal_insn; | |
4182 | } | |
cf495bcf | 4183 | } |
0f8a249a BS |
4184 | break; |
4185 | } | |
4186 | break; | |
4187 | case 3: /* load/store instructions */ | |
4188 | { | |
4189 | unsigned int xop = GET_FIELD(insn, 7, 12); | |
9322a4bf | 4190 | |
9322a4bf | 4191 | cpu_src1 = get_src1(insn, cpu_src1); |
71817e48 | 4192 | if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa |
81ad8ba2 | 4193 | rs2 = GET_FIELD(insn, 27, 31); |
6ae20372 | 4194 | gen_movl_reg_TN(rs2, cpu_src2); |
71817e48 BS |
4195 | tcg_gen_mov_tl(cpu_addr, cpu_src1); |
4196 | } else if (IS_IMM) { /* immediate */ | |
0f8a249a | 4197 | rs2 = GET_FIELDs(insn, 19, 31); |
6ae20372 | 4198 | tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2); |
0f8a249a BS |
4199 | } else { /* register */ |
4200 | rs2 = GET_FIELD(insn, 27, 31); | |
0f8a249a | 4201 | if (rs2 != 0) { |
6ae20372 BS |
4202 | gen_movl_reg_TN(rs2, cpu_src2); |
4203 | tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2); | |
6f551262 BS |
4204 | } else |
4205 | tcg_gen_mov_tl(cpu_addr, cpu_src1); | |
0f8a249a | 4206 | } |
2f2ecb83 BS |
4207 | if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || |
4208 | (xop > 0x17 && xop <= 0x1d ) || | |
4209 | (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { | |
0f8a249a | 4210 | switch (xop) { |
1a2fb1c0 | 4211 | case 0x0: /* load unsigned word */ |
2cade6a3 | 4212 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4213 | tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a BS |
4214 | break; |
4215 | case 0x1: /* load unsigned byte */ | |
2cade6a3 | 4216 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4217 | tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a BS |
4218 | break; |
4219 | case 0x2: /* load unsigned halfword */ | |
2cade6a3 | 4220 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4221 | tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a BS |
4222 | break; |
4223 | case 0x3: /* load double word */ | |
0f8a249a | 4224 | if (rd & 1) |
d4218d99 | 4225 | goto illegal_insn; |
1a2fb1c0 | 4226 | else { |
2ea815ca BS |
4227 | TCGv r_const; |
4228 | ||
c2bc0e38 | 4229 | save_state(dc, cpu_cond); |
2ea815ca | 4230 | r_const = tcg_const_i32(7); |
d987963a | 4231 | tcg_gen_helper_0_2(helper_check_align, cpu_addr, |
2ea815ca BS |
4232 | r_const); // XXX remove |
4233 | tcg_temp_free(r_const); | |
2cade6a3 | 4234 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4235 | tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); |
32b6c812 BS |
4236 | tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64); |
4237 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL); | |
4238 | gen_movl_TN_reg(rd + 1, cpu_tmp0); | |
8911f501 | 4239 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32); |
6ae20372 BS |
4240 | tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64); |
4241 | tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL); | |
1a2fb1c0 | 4242 | } |
0f8a249a BS |
4243 | break; |
4244 | case 0x9: /* load signed byte */ | |
2cade6a3 | 4245 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4246 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a BS |
4247 | break; |
4248 | case 0xa: /* load signed halfword */ | |
2cade6a3 | 4249 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4250 | tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a BS |
4251 | break; |
4252 | case 0xd: /* ldstub -- XXX: should be atomically */ | |
2ea815ca BS |
4253 | { |
4254 | TCGv r_const; | |
4255 | ||
2cade6a3 | 4256 | gen_address_mask(dc, cpu_addr); |
2ea815ca BS |
4257 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
4258 | r_const = tcg_const_tl(0xff); | |
4259 | tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx); | |
4260 | tcg_temp_free(r_const); | |
4261 | } | |
0f8a249a | 4262 | break; |
77f193da BS |
4263 | case 0x0f: /* swap register with memory. Also |
4264 | atomically */ | |
64a88d5d | 4265 | CHECK_IU_FEATURE(dc, SWAP); |
6ae20372 | 4266 | gen_movl_reg_TN(rd, cpu_val); |
2cade6a3 | 4267 | gen_address_mask(dc, cpu_addr); |
6ae20372 BS |
4268 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); |
4269 | tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); | |
4270 | tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32); | |
0f8a249a | 4271 | break; |
3475187d | 4272 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) |
0f8a249a | 4273 | case 0x10: /* load word alternate */ |
3475187d | 4274 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4275 | if (IS_IMM) |
4276 | goto illegal_insn; | |
4277 | if (!supervisor(dc)) | |
4278 | goto priv_insn; | |
6ea4a6c8 | 4279 | #endif |
c2bc0e38 | 4280 | save_state(dc, cpu_cond); |
6ae20372 | 4281 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0); |
0f8a249a BS |
4282 | break; |
4283 | case 0x11: /* load unsigned byte alternate */ | |
3475187d | 4284 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4285 | if (IS_IMM) |
4286 | goto illegal_insn; | |
4287 | if (!supervisor(dc)) | |
4288 | goto priv_insn; | |
4289 | #endif | |
c2bc0e38 | 4290 | save_state(dc, cpu_cond); |
6ae20372 | 4291 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0); |
0f8a249a BS |
4292 | break; |
4293 | case 0x12: /* load unsigned halfword alternate */ | |
3475187d | 4294 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4295 | if (IS_IMM) |
4296 | goto illegal_insn; | |
4297 | if (!supervisor(dc)) | |
4298 | goto priv_insn; | |
3475187d | 4299 | #endif |
c2bc0e38 | 4300 | save_state(dc, cpu_cond); |
6ae20372 | 4301 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0); |
0f8a249a BS |
4302 | break; |
4303 | case 0x13: /* load double word alternate */ | |
3475187d | 4304 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4305 | if (IS_IMM) |
4306 | goto illegal_insn; | |
4307 | if (!supervisor(dc)) | |
4308 | goto priv_insn; | |
3475187d | 4309 | #endif |
0f8a249a | 4310 | if (rd & 1) |
d4218d99 | 4311 | goto illegal_insn; |
c2bc0e38 | 4312 | save_state(dc, cpu_cond); |
6ae20372 | 4313 | gen_ldda_asi(cpu_tmp0, cpu_val, cpu_addr, insn); |
32b6c812 | 4314 | gen_movl_TN_reg(rd + 1, cpu_tmp0); |
0f8a249a BS |
4315 | break; |
4316 | case 0x19: /* load signed byte alternate */ | |
3475187d | 4317 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4318 | if (IS_IMM) |
4319 | goto illegal_insn; | |
4320 | if (!supervisor(dc)) | |
4321 | goto priv_insn; | |
4322 | #endif | |
c2bc0e38 | 4323 | save_state(dc, cpu_cond); |
6ae20372 | 4324 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1); |
0f8a249a BS |
4325 | break; |
4326 | case 0x1a: /* load signed halfword alternate */ | |
3475187d | 4327 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4328 | if (IS_IMM) |
4329 | goto illegal_insn; | |
4330 | if (!supervisor(dc)) | |
4331 | goto priv_insn; | |
3475187d | 4332 | #endif |
c2bc0e38 | 4333 | save_state(dc, cpu_cond); |
6ae20372 | 4334 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1); |
0f8a249a BS |
4335 | break; |
4336 | case 0x1d: /* ldstuba -- XXX: should be atomically */ | |
3475187d | 4337 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4338 | if (IS_IMM) |
4339 | goto illegal_insn; | |
4340 | if (!supervisor(dc)) | |
4341 | goto priv_insn; | |
4342 | #endif | |
c2bc0e38 | 4343 | save_state(dc, cpu_cond); |
6ae20372 | 4344 | gen_ldstub_asi(cpu_val, cpu_addr, insn); |
0f8a249a | 4345 | break; |
77f193da BS |
4346 | case 0x1f: /* swap reg with alt. memory. Also |
4347 | atomically */ | |
64a88d5d | 4348 | CHECK_IU_FEATURE(dc, SWAP); |
3475187d | 4349 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4350 | if (IS_IMM) |
4351 | goto illegal_insn; | |
4352 | if (!supervisor(dc)) | |
4353 | goto priv_insn; | |
6ea4a6c8 | 4354 | #endif |
c2bc0e38 | 4355 | save_state(dc, cpu_cond); |
6ae20372 BS |
4356 | gen_movl_reg_TN(rd, cpu_val); |
4357 | gen_swap_asi(cpu_val, cpu_addr, insn); | |
0f8a249a | 4358 | break; |
3475187d FB |
4359 | |
4360 | #ifndef TARGET_SPARC64 | |
0f8a249a BS |
4361 | case 0x30: /* ldc */ |
4362 | case 0x31: /* ldcsr */ | |
4363 | case 0x33: /* lddc */ | |
4364 | goto ncp_insn; | |
3475187d FB |
4365 | #endif |
4366 | #endif | |
4367 | #ifdef TARGET_SPARC64 | |
0f8a249a | 4368 | case 0x08: /* V9 ldsw */ |
2cade6a3 | 4369 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4370 | tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a BS |
4371 | break; |
4372 | case 0x0b: /* V9 ldx */ | |
2cade6a3 | 4373 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4374 | tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a BS |
4375 | break; |
4376 | case 0x18: /* V9 ldswa */ | |
c2bc0e38 | 4377 | save_state(dc, cpu_cond); |
6ae20372 | 4378 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1); |
0f8a249a BS |
4379 | break; |
4380 | case 0x1b: /* V9 ldxa */ | |
c2bc0e38 | 4381 | save_state(dc, cpu_cond); |
6ae20372 | 4382 | gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0); |
0f8a249a BS |
4383 | break; |
4384 | case 0x2d: /* V9 prefetch, no effect */ | |
4385 | goto skip_move; | |
4386 | case 0x30: /* V9 ldfa */ | |
c2bc0e38 | 4387 | save_state(dc, cpu_cond); |
6ae20372 | 4388 | gen_ldf_asi(cpu_addr, insn, 4, rd); |
81ad8ba2 | 4389 | goto skip_move; |
0f8a249a | 4390 | case 0x33: /* V9 lddfa */ |
c2bc0e38 | 4391 | save_state(dc, cpu_cond); |
6ae20372 | 4392 | gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd)); |
81ad8ba2 | 4393 | goto skip_move; |
0f8a249a BS |
4394 | case 0x3d: /* V9 prefetcha, no effect */ |
4395 | goto skip_move; | |
4396 | case 0x32: /* V9 ldqfa */ | |
64a88d5d | 4397 | CHECK_FPU_FEATURE(dc, FLOAT128); |
c2bc0e38 | 4398 | save_state(dc, cpu_cond); |
6ae20372 | 4399 | gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd)); |
1f587329 | 4400 | goto skip_move; |
0f8a249a BS |
4401 | #endif |
4402 | default: | |
4403 | goto illegal_insn; | |
4404 | } | |
6ae20372 | 4405 | gen_movl_TN_reg(rd, cpu_val); |
3475187d | 4406 | #ifdef TARGET_SPARC64 |
0f8a249a | 4407 | skip_move: ; |
3475187d | 4408 | #endif |
0f8a249a | 4409 | } else if (xop >= 0x20 && xop < 0x24) { |
6ae20372 | 4410 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
a80dde08 | 4411 | goto jmp_insn; |
c2bc0e38 | 4412 | save_state(dc, cpu_cond); |
0f8a249a BS |
4413 | switch (xop) { |
4414 | case 0x20: /* load fpreg */ | |
2cade6a3 | 4415 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4416 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); |
ce8536e2 BS |
4417 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
4418 | offsetof(CPUState, fpr[rd])); | |
0f8a249a BS |
4419 | break; |
4420 | case 0x21: /* load fsr */ | |
2cade6a3 | 4421 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4422 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); |
ce8536e2 BS |
4423 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
4424 | offsetof(CPUState, ft0)); | |
7e8c2b6c | 4425 | tcg_gen_helper_0_0(helper_ldfsr); |
0f8a249a BS |
4426 | break; |
4427 | case 0x22: /* load quad fpreg */ | |
2ea815ca BS |
4428 | { |
4429 | TCGv r_const; | |
4430 | ||
4431 | CHECK_FPU_FEATURE(dc, FLOAT128); | |
4432 | r_const = tcg_const_i32(dc->mem_idx); | |
4433 | tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const); | |
4434 | tcg_temp_free(r_const); | |
4435 | gen_op_store_QT0_fpr(QFPREG(rd)); | |
4436 | } | |
1f587329 | 4437 | break; |
0f8a249a | 4438 | case 0x23: /* load double fpreg */ |
2ea815ca BS |
4439 | { |
4440 | TCGv r_const; | |
4441 | ||
4442 | r_const = tcg_const_i32(dc->mem_idx); | |
4443 | tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const); | |
4444 | tcg_temp_free(r_const); | |
4445 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
4446 | } | |
0f8a249a BS |
4447 | break; |
4448 | default: | |
4449 | goto illegal_insn; | |
4450 | } | |
4451 | } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \ | |
4452 | xop == 0xe || xop == 0x1e) { | |
6ae20372 | 4453 | gen_movl_reg_TN(rd, cpu_val); |
0f8a249a | 4454 | switch (xop) { |
1a2fb1c0 | 4455 | case 0x4: /* store word */ |
2cade6a3 | 4456 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4457 | tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a | 4458 | break; |
1a2fb1c0 | 4459 | case 0x5: /* store byte */ |
2cade6a3 | 4460 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4461 | tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a | 4462 | break; |
1a2fb1c0 | 4463 | case 0x6: /* store halfword */ |
2cade6a3 | 4464 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4465 | tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a | 4466 | break; |
1a2fb1c0 | 4467 | case 0x7: /* store double word */ |
0f8a249a | 4468 | if (rd & 1) |
d4218d99 | 4469 | goto illegal_insn; |
1a2fb1c0 | 4470 | else { |
2ea815ca | 4471 | TCGv r_low, r_const; |
1a2fb1c0 | 4472 | |
c2bc0e38 | 4473 | save_state(dc, cpu_cond); |
2cade6a3 | 4474 | gen_address_mask(dc, cpu_addr); |
2ea815ca | 4475 | r_const = tcg_const_i32(7); |
c2bc0e38 | 4476 | tcg_gen_helper_0_2(helper_check_align, cpu_addr, |
2ea815ca BS |
4477 | r_const); // XXX remove |
4478 | tcg_temp_free(r_const); | |
8d96d209 | 4479 | r_low = tcg_temp_new(TCG_TYPE_TL); |
1a2fb1c0 | 4480 | gen_movl_reg_TN(rd + 1, r_low); |
6ae20372 | 4481 | tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val, |
1a2fb1c0 | 4482 | r_low); |
2ea815ca | 4483 | tcg_temp_free(r_low); |
6ae20372 | 4484 | tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); |
7fa76c0b | 4485 | } |
0f8a249a | 4486 | break; |
3475187d | 4487 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) |
1a2fb1c0 | 4488 | case 0x14: /* store word alternate */ |
3475187d | 4489 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4490 | if (IS_IMM) |
4491 | goto illegal_insn; | |
4492 | if (!supervisor(dc)) | |
4493 | goto priv_insn; | |
6ea4a6c8 | 4494 | #endif |
c2bc0e38 | 4495 | save_state(dc, cpu_cond); |
6ae20372 | 4496 | gen_st_asi(cpu_val, cpu_addr, insn, 4); |
d39c0b99 | 4497 | break; |
1a2fb1c0 | 4498 | case 0x15: /* store byte alternate */ |
3475187d | 4499 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4500 | if (IS_IMM) |
4501 | goto illegal_insn; | |
4502 | if (!supervisor(dc)) | |
4503 | goto priv_insn; | |
3475187d | 4504 | #endif |
c2bc0e38 | 4505 | save_state(dc, cpu_cond); |
6ae20372 | 4506 | gen_st_asi(cpu_val, cpu_addr, insn, 1); |
d39c0b99 | 4507 | break; |
1a2fb1c0 | 4508 | case 0x16: /* store halfword alternate */ |
3475187d | 4509 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4510 | if (IS_IMM) |
4511 | goto illegal_insn; | |
4512 | if (!supervisor(dc)) | |
4513 | goto priv_insn; | |
6ea4a6c8 | 4514 | #endif |
c2bc0e38 | 4515 | save_state(dc, cpu_cond); |
6ae20372 | 4516 | gen_st_asi(cpu_val, cpu_addr, insn, 2); |
d39c0b99 | 4517 | break; |
1a2fb1c0 | 4518 | case 0x17: /* store double word alternate */ |
3475187d | 4519 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4520 | if (IS_IMM) |
4521 | goto illegal_insn; | |
4522 | if (!supervisor(dc)) | |
4523 | goto priv_insn; | |
3475187d | 4524 | #endif |
0f8a249a | 4525 | if (rd & 1) |
d4218d99 | 4526 | goto illegal_insn; |
1a2fb1c0 | 4527 | else { |
c2bc0e38 | 4528 | save_state(dc, cpu_cond); |
6ae20372 | 4529 | gen_stda_asi(cpu_val, cpu_addr, insn, rd); |
1a2fb1c0 | 4530 | } |
d39c0b99 | 4531 | break; |
e80cfcfc | 4532 | #endif |
3475187d | 4533 | #ifdef TARGET_SPARC64 |
0f8a249a | 4534 | case 0x0e: /* V9 stx */ |
2cade6a3 | 4535 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4536 | tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a BS |
4537 | break; |
4538 | case 0x1e: /* V9 stxa */ | |
c2bc0e38 | 4539 | save_state(dc, cpu_cond); |
6ae20372 | 4540 | gen_st_asi(cpu_val, cpu_addr, insn, 8); |
0f8a249a | 4541 | break; |
3475187d | 4542 | #endif |
0f8a249a BS |
4543 | default: |
4544 | goto illegal_insn; | |
4545 | } | |
4546 | } else if (xop > 0x23 && xop < 0x28) { | |
6ae20372 | 4547 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
a80dde08 | 4548 | goto jmp_insn; |
c2bc0e38 | 4549 | save_state(dc, cpu_cond); |
0f8a249a | 4550 | switch (xop) { |
ce8536e2 | 4551 | case 0x24: /* store fpreg */ |
2cade6a3 | 4552 | gen_address_mask(dc, cpu_addr); |
ce8536e2 BS |
4553 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
4554 | offsetof(CPUState, fpr[rd])); | |
6ae20372 | 4555 | tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx); |
0f8a249a BS |
4556 | break; |
4557 | case 0x25: /* stfsr, V9 stxfsr */ | |
2cade6a3 | 4558 | gen_address_mask(dc, cpu_addr); |
bb5529bb | 4559 | tcg_gen_helper_0_0(helper_stfsr); |
ce8536e2 BS |
4560 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
4561 | offsetof(CPUState, ft0)); | |
6ae20372 | 4562 | tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx); |
0f8a249a | 4563 | break; |
1f587329 BS |
4564 | case 0x26: |
4565 | #ifdef TARGET_SPARC64 | |
1f587329 | 4566 | /* V9 stqf, store quad fpreg */ |
2ea815ca BS |
4567 | { |
4568 | TCGv r_const; | |
4569 | ||
4570 | CHECK_FPU_FEATURE(dc, FLOAT128); | |
4571 | gen_op_load_fpr_QT0(QFPREG(rd)); | |
4572 | r_const = tcg_const_i32(dc->mem_idx); | |
4573 | tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const); | |
4574 | tcg_temp_free(r_const); | |
4575 | } | |
1f587329 | 4576 | break; |
1f587329 BS |
4577 | #else /* !TARGET_SPARC64 */ |
4578 | /* stdfq, store floating point queue */ | |
4579 | #if defined(CONFIG_USER_ONLY) | |
4580 | goto illegal_insn; | |
4581 | #else | |
0f8a249a BS |
4582 | if (!supervisor(dc)) |
4583 | goto priv_insn; | |
6ae20372 | 4584 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
0f8a249a BS |
4585 | goto jmp_insn; |
4586 | goto nfq_insn; | |
1f587329 | 4587 | #endif |
0f8a249a | 4588 | #endif |
7fa76c0b | 4589 | case 0x27: /* store double fpreg */ |
2ea815ca BS |
4590 | { |
4591 | TCGv r_const; | |
4592 | ||
4593 | gen_op_load_fpr_DT0(DFPREG(rd)); | |
4594 | r_const = tcg_const_i32(dc->mem_idx); | |
4595 | tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const); | |
4596 | tcg_temp_free(r_const); | |
4597 | } | |
0f8a249a BS |
4598 | break; |
4599 | default: | |
4600 | goto illegal_insn; | |
4601 | } | |
4602 | } else if (xop > 0x33 && xop < 0x3f) { | |
c2bc0e38 | 4603 | save_state(dc, cpu_cond); |
0f8a249a | 4604 | switch (xop) { |
a4d17f19 | 4605 | #ifdef TARGET_SPARC64 |
0f8a249a | 4606 | case 0x34: /* V9 stfa */ |
3391c818 | 4607 | gen_op_load_fpr_FT0(rd); |
6ae20372 | 4608 | gen_stf_asi(cpu_addr, insn, 4, rd); |
0f8a249a | 4609 | break; |
1f587329 | 4610 | case 0x36: /* V9 stqfa */ |
2ea815ca BS |
4611 | { |
4612 | TCGv r_const; | |
4613 | ||
4614 | CHECK_FPU_FEATURE(dc, FLOAT128); | |
4615 | r_const = tcg_const_i32(7); | |
4616 | tcg_gen_helper_0_2(helper_check_align, cpu_addr, | |
4617 | r_const); | |
4618 | tcg_temp_free(r_const); | |
4619 | gen_op_load_fpr_QT0(QFPREG(rd)); | |
4620 | gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd)); | |
4621 | } | |
1f587329 | 4622 | break; |
0f8a249a | 4623 | case 0x37: /* V9 stdfa */ |
3391c818 | 4624 | gen_op_load_fpr_DT0(DFPREG(rd)); |
6ae20372 | 4625 | gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd)); |
0f8a249a BS |
4626 | break; |
4627 | case 0x3c: /* V9 casa */ | |
71817e48 | 4628 | gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd); |
6ae20372 | 4629 | gen_movl_TN_reg(rd, cpu_val); |
0f8a249a BS |
4630 | break; |
4631 | case 0x3e: /* V9 casxa */ | |
71817e48 | 4632 | gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd); |
6ae20372 | 4633 | gen_movl_TN_reg(rd, cpu_val); |
0f8a249a | 4634 | break; |
a4d17f19 | 4635 | #else |
0f8a249a BS |
4636 | case 0x34: /* stc */ |
4637 | case 0x35: /* stcsr */ | |
4638 | case 0x36: /* stdcq */ | |
4639 | case 0x37: /* stdc */ | |
4640 | goto ncp_insn; | |
4641 | #endif | |
4642 | default: | |
4643 | goto illegal_insn; | |
4644 | } | |
e8af50a3 | 4645 | } |
0f8a249a BS |
4646 | else |
4647 | goto illegal_insn; | |
4648 | } | |
4649 | break; | |
cf495bcf FB |
4650 | } |
4651 | /* default case for non jump instructions */ | |
72cbca10 | 4652 | if (dc->npc == DYNAMIC_PC) { |
0f8a249a BS |
4653 | dc->pc = DYNAMIC_PC; |
4654 | gen_op_next_insn(); | |
72cbca10 FB |
4655 | } else if (dc->npc == JUMP_PC) { |
4656 | /* we can do a static jump */ | |
6ae20372 | 4657 | gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); |
72cbca10 FB |
4658 | dc->is_br = 1; |
4659 | } else { | |
0f8a249a BS |
4660 | dc->pc = dc->npc; |
4661 | dc->npc = dc->npc + 4; | |
cf495bcf | 4662 | } |
e80cfcfc | 4663 | jmp_insn: |
cf495bcf FB |
4664 | return; |
4665 | illegal_insn: | |
2ea815ca BS |
4666 | { |
4667 | TCGv r_const; | |
4668 | ||
4669 | save_state(dc, cpu_cond); | |
4670 | r_const = tcg_const_i32(TT_ILL_INSN); | |
4671 | tcg_gen_helper_0_1(raise_exception, r_const); | |
4672 | tcg_temp_free(r_const); | |
4673 | dc->is_br = 1; | |
4674 | } | |
e8af50a3 | 4675 | return; |
64a88d5d | 4676 | unimp_flush: |
2ea815ca BS |
4677 | { |
4678 | TCGv r_const; | |
4679 | ||
4680 | save_state(dc, cpu_cond); | |
4681 | r_const = tcg_const_i32(TT_UNIMP_FLUSH); | |
4682 | tcg_gen_helper_0_1(raise_exception, r_const); | |
4683 | tcg_temp_free(r_const); | |
4684 | dc->is_br = 1; | |
4685 | } | |
64a88d5d | 4686 | return; |
e80cfcfc | 4687 | #if !defined(CONFIG_USER_ONLY) |
e8af50a3 | 4688 | priv_insn: |
2ea815ca BS |
4689 | { |
4690 | TCGv r_const; | |
4691 | ||
4692 | save_state(dc, cpu_cond); | |
4693 | r_const = tcg_const_i32(TT_PRIV_INSN); | |
4694 | tcg_gen_helper_0_1(raise_exception, r_const); | |
4695 | tcg_temp_free(r_const); | |
4696 | dc->is_br = 1; | |
4697 | } | |
e80cfcfc | 4698 | return; |
64a88d5d | 4699 | #endif |
e80cfcfc | 4700 | nfpu_insn: |
6ae20372 | 4701 | save_state(dc, cpu_cond); |
e80cfcfc FB |
4702 | gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); |
4703 | dc->is_br = 1; | |
fcc72045 | 4704 | return; |
64a88d5d | 4705 | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) |
9143e598 | 4706 | nfq_insn: |
6ae20372 | 4707 | save_state(dc, cpu_cond); |
9143e598 BS |
4708 | gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); |
4709 | dc->is_br = 1; | |
4710 | return; | |
4711 | #endif | |
fcc72045 BS |
4712 | #ifndef TARGET_SPARC64 |
4713 | ncp_insn: | |
2ea815ca BS |
4714 | { |
4715 | TCGv r_const; | |
4716 | ||
4717 | save_state(dc, cpu_cond); | |
4718 | r_const = tcg_const_i32(TT_NCP_INSN); | |
4719 | tcg_gen_helper_0_1(raise_exception, r_const); | |
4720 | tcg_temp_free(r_const); | |
4721 | dc->is_br = 1; | |
4722 | } | |
fcc72045 BS |
4723 | return; |
4724 | #endif | |
7a3f1944 FB |
4725 | } |
4726 | ||
2cfc5f17 TS |
4727 | static inline void gen_intermediate_code_internal(TranslationBlock * tb, |
4728 | int spc, CPUSPARCState *env) | |
7a3f1944 | 4729 | { |
72cbca10 | 4730 | target_ulong pc_start, last_pc; |
cf495bcf FB |
4731 | uint16_t *gen_opc_end; |
4732 | DisasContext dc1, *dc = &dc1; | |
e8af50a3 | 4733 | int j, lj = -1; |
2e70f6ef PB |
4734 | int num_insns; |
4735 | int max_insns; | |
cf495bcf FB |
4736 | |
4737 | memset(dc, 0, sizeof(DisasContext)); | |
cf495bcf | 4738 | dc->tb = tb; |
72cbca10 | 4739 | pc_start = tb->pc; |
cf495bcf | 4740 | dc->pc = pc_start; |
e80cfcfc | 4741 | last_pc = dc->pc; |
72cbca10 | 4742 | dc->npc = (target_ulong) tb->cs_base; |
6f27aba6 | 4743 | dc->mem_idx = cpu_mmu_index(env); |
64a88d5d BS |
4744 | dc->features = env->features; |
4745 | if ((dc->features & CPU_FEATURE_FLOAT)) { | |
4746 | dc->fpu_enabled = cpu_fpu_enabled(env); | |
4747 | #if defined(CONFIG_USER_ONLY) | |
4748 | dc->features |= CPU_FEATURE_FLOAT128; | |
4749 | #endif | |
4750 | } else | |
4751 | dc->fpu_enabled = 0; | |
2cade6a3 BS |
4752 | #ifdef TARGET_SPARC64 |
4753 | dc->address_mask_32bit = env->pstate & PS_AM; | |
4754 | #endif | |
cf495bcf | 4755 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
cf495bcf | 4756 | |
1a2fb1c0 | 4757 | cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL); |
8911f501 BS |
4758 | cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32); |
4759 | cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64); | |
d987963a BS |
4760 | |
4761 | cpu_dst = tcg_temp_local_new(TCG_TYPE_TL); | |
4762 | ||
4763 | // loads and stores | |
3f0436fe | 4764 | cpu_val = tcg_temp_local_new(TCG_TYPE_TL); |
d987963a | 4765 | cpu_addr = tcg_temp_local_new(TCG_TYPE_TL); |
1a2fb1c0 | 4766 | |
2e70f6ef PB |
4767 | num_insns = 0; |
4768 | max_insns = tb->cflags & CF_COUNT_MASK; | |
4769 | if (max_insns == 0) | |
4770 | max_insns = CF_COUNT_MASK; | |
4771 | gen_icount_start(); | |
cf495bcf | 4772 | do { |
e8af50a3 FB |
4773 | if (env->nb_breakpoints > 0) { |
4774 | for(j = 0; j < env->nb_breakpoints; j++) { | |
4775 | if (env->breakpoints[j] == dc->pc) { | |
0f8a249a | 4776 | if (dc->pc != pc_start) |
6ae20372 | 4777 | save_state(dc, cpu_cond); |
1a2fb1c0 | 4778 | tcg_gen_helper_0_0(helper_debug); |
57fec1fe | 4779 | tcg_gen_exit_tb(0); |
0f8a249a | 4780 | dc->is_br = 1; |
e80cfcfc | 4781 | goto exit_gen_loop; |
e8af50a3 FB |
4782 | } |
4783 | } | |
4784 | } | |
4785 | if (spc) { | |
4786 | if (loglevel > 0) | |
4787 | fprintf(logfile, "Search PC...\n"); | |
4788 | j = gen_opc_ptr - gen_opc_buf; | |
4789 | if (lj < j) { | |
4790 | lj++; | |
4791 | while (lj < j) | |
4792 | gen_opc_instr_start[lj++] = 0; | |
4793 | gen_opc_pc[lj] = dc->pc; | |
4794 | gen_opc_npc[lj] = dc->npc; | |
4795 | gen_opc_instr_start[lj] = 1; | |
2e70f6ef | 4796 | gen_opc_icount[lj] = num_insns; |
e8af50a3 FB |
4797 | } |
4798 | } | |
2e70f6ef PB |
4799 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
4800 | gen_io_start(); | |
0f8a249a BS |
4801 | last_pc = dc->pc; |
4802 | disas_sparc_insn(dc); | |
2e70f6ef | 4803 | num_insns++; |
0f8a249a BS |
4804 | |
4805 | if (dc->is_br) | |
4806 | break; | |
4807 | /* if the next PC is different, we abort now */ | |
4808 | if (dc->pc != (last_pc + 4)) | |
4809 | break; | |
d39c0b99 FB |
4810 | /* if we reach a page boundary, we stop generation so that the |
4811 | PC of a TT_TFAULT exception is always in the right page */ | |
4812 | if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) | |
4813 | break; | |
e80cfcfc FB |
4814 | /* if single step mode, we generate only one instruction and |
4815 | generate an exception */ | |
4816 | if (env->singlestep_enabled) { | |
2f5680ee | 4817 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
57fec1fe | 4818 | tcg_gen_exit_tb(0); |
e80cfcfc FB |
4819 | break; |
4820 | } | |
cf495bcf | 4821 | } while ((gen_opc_ptr < gen_opc_end) && |
2e70f6ef PB |
4822 | (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) && |
4823 | num_insns < max_insns); | |
e80cfcfc FB |
4824 | |
4825 | exit_gen_loop: | |
d987963a | 4826 | tcg_temp_free(cpu_addr); |
3f0436fe | 4827 | tcg_temp_free(cpu_val); |
d987963a | 4828 | tcg_temp_free(cpu_dst); |
2ea815ca BS |
4829 | tcg_temp_free(cpu_tmp64); |
4830 | tcg_temp_free(cpu_tmp32); | |
4831 | tcg_temp_free(cpu_tmp0); | |
2e70f6ef PB |
4832 | if (tb->cflags & CF_LAST_IO) |
4833 | gen_io_end(); | |
72cbca10 | 4834 | if (!dc->is_br) { |
5fafdf24 | 4835 | if (dc->pc != DYNAMIC_PC && |
72cbca10 FB |
4836 | (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { |
4837 | /* static PC and NPC: we can use direct chaining */ | |
2f5680ee | 4838 | gen_goto_tb(dc, 0, dc->pc, dc->npc); |
72cbca10 FB |
4839 | } else { |
4840 | if (dc->pc != DYNAMIC_PC) | |
2f5680ee | 4841 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
6ae20372 | 4842 | save_npc(dc, cpu_cond); |
57fec1fe | 4843 | tcg_gen_exit_tb(0); |
72cbca10 FB |
4844 | } |
4845 | } | |
2e70f6ef | 4846 | gen_icount_end(tb, num_insns); |
cf495bcf | 4847 | *gen_opc_ptr = INDEX_op_end; |
e8af50a3 FB |
4848 | if (spc) { |
4849 | j = gen_opc_ptr - gen_opc_buf; | |
4850 | lj++; | |
4851 | while (lj <= j) | |
4852 | gen_opc_instr_start[lj++] = 0; | |
e8af50a3 FB |
4853 | #if 0 |
4854 | if (loglevel > 0) { | |
4855 | page_dump(logfile); | |
4856 | } | |
4857 | #endif | |
c3278b7b FB |
4858 | gen_opc_jump_pc[0] = dc->jump_pc[0]; |
4859 | gen_opc_jump_pc[1] = dc->jump_pc[1]; | |
e8af50a3 | 4860 | } else { |
e80cfcfc | 4861 | tb->size = last_pc + 4 - pc_start; |
2e70f6ef | 4862 | tb->icount = num_insns; |
e8af50a3 | 4863 | } |
7a3f1944 | 4864 | #ifdef DEBUG_DISAS |
e19e89a5 | 4865 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
0f8a249a BS |
4866 | fprintf(logfile, "--------------\n"); |
4867 | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start)); | |
4868 | target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0); | |
4869 | fprintf(logfile, "\n"); | |
cf495bcf | 4870 | } |
7a3f1944 | 4871 | #endif |
7a3f1944 FB |
4872 | } |
4873 | ||
2cfc5f17 | 4874 | void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb) |
7a3f1944 | 4875 | { |
2cfc5f17 | 4876 | gen_intermediate_code_internal(tb, 0, env); |
7a3f1944 FB |
4877 | } |
4878 | ||
2cfc5f17 | 4879 | void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb) |
7a3f1944 | 4880 | { |
2cfc5f17 | 4881 | gen_intermediate_code_internal(tb, 1, env); |
7a3f1944 FB |
4882 | } |
4883 | ||
c48fcb47 | 4884 | void gen_intermediate_code_init(CPUSPARCState *env) |
e80cfcfc | 4885 | { |
f5069b26 | 4886 | unsigned int i; |
c48fcb47 | 4887 | static int inited; |
f5069b26 BS |
4888 | static const char * const gregnames[8] = { |
4889 | NULL, // g0 not used | |
4890 | "g1", | |
4891 | "g2", | |
4892 | "g3", | |
4893 | "g4", | |
4894 | "g5", | |
4895 | "g6", | |
4896 | "g7", | |
4897 | }; | |
aaed909a | 4898 | |
1a2fb1c0 BS |
4899 | /* init various static tables */ |
4900 | if (!inited) { | |
4901 | inited = 1; | |
4902 | ||
1a2fb1c0 | 4903 | cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env"); |
db4a4ea4 BS |
4904 | cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0, |
4905 | offsetof(CPUState, regwptr), | |
4906 | "regwptr"); | |
1a2fb1c0 | 4907 | #ifdef TARGET_SPARC64 |
dc99a3f2 BS |
4908 | cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32, |
4909 | TCG_AREG0, offsetof(CPUState, xcc), | |
4910 | "xcc"); | |
1a2fb1c0 | 4911 | #endif |
7c60cc4b | 4912 | cpu_cond = tcg_global_mem_new(TCG_TYPE_TL, |
77f193da BS |
4913 | TCG_AREG0, offsetof(CPUState, cond), |
4914 | "cond"); | |
dc99a3f2 BS |
4915 | cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL, |
4916 | TCG_AREG0, offsetof(CPUState, cc_src), | |
4917 | "cc_src"); | |
d9bdab86 BS |
4918 | cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
4919 | offsetof(CPUState, cc_src2), | |
4920 | "cc_src2"); | |
dc99a3f2 BS |
4921 | cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL, |
4922 | TCG_AREG0, offsetof(CPUState, cc_dst), | |
4923 | "cc_dst"); | |
4924 | cpu_psr = tcg_global_mem_new(TCG_TYPE_I32, | |
4925 | TCG_AREG0, offsetof(CPUState, psr), | |
4926 | "psr"); | |
87e92502 BS |
4927 | cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL, |
4928 | TCG_AREG0, offsetof(CPUState, fsr), | |
4929 | "fsr"); | |
48d5c82b BS |
4930 | cpu_pc = tcg_global_mem_new(TCG_TYPE_TL, |
4931 | TCG_AREG0, offsetof(CPUState, pc), | |
4932 | "pc"); | |
4933 | cpu_npc = tcg_global_mem_new(TCG_TYPE_TL, | |
4934 | TCG_AREG0, offsetof(CPUState, npc), | |
4935 | "npc"); | |
f5069b26 BS |
4936 | for (i = 1; i < 8; i++) |
4937 | cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, | |
4938 | offsetof(CPUState, gregs[i]), | |
4939 | gregnames[i]); | |
c9e03d8f BS |
4940 | /* register helpers */ |
4941 | ||
4942 | #undef DEF_HELPER | |
4943 | #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); | |
4944 | #include "helper.h" | |
1a2fb1c0 | 4945 | } |
658138bc | 4946 | } |
d2856f1a AJ |
4947 | |
4948 | void gen_pc_load(CPUState *env, TranslationBlock *tb, | |
4949 | unsigned long searched_pc, int pc_pos, void *puc) | |
4950 | { | |
4951 | target_ulong npc; | |
4952 | env->pc = gen_opc_pc[pc_pos]; | |
4953 | npc = gen_opc_npc[pc_pos]; | |
4954 | if (npc == 1) { | |
4955 | /* dynamic NPC: already stored */ | |
4956 | } else if (npc == 2) { | |
4957 | target_ulong t2 = (target_ulong)(unsigned long)puc; | |
4958 | /* jump PC: use T2 and the jump targets of the translation */ | |
4959 | if (t2) | |
4960 | env->npc = gen_opc_jump_pc[0]; | |
4961 | else | |
4962 | env->npc = gen_opc_jump_pc[1]; | |
4963 | } else { | |
4964 | env->npc = npc; | |
4965 | } | |
4966 | } |