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7a3f1944
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1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
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6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
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23 TODO-list:
24
3475187d 25 Rest of V9 instructions, VIS instructions
bd497938 26 NPC/PC static optimisations (use JUMP_TB when possible)
7a3f1944 27 Optimize synthetic instructions
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28 Optional alignment check
29 128-bit float
30 Tagged add/sub
bd497938 31*/
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32
33#include <stdarg.h>
34#include <stdlib.h>
35#include <stdio.h>
36#include <string.h>
37#include <inttypes.h>
38
39#include "cpu.h"
40#include "exec-all.h"
41#include "disas.h"
42
43#define DEBUG_DISAS
44
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45#define DYNAMIC_PC 1 /* dynamic pc value */
46#define JUMP_PC 2 /* dynamic pc value which takes only two values
47 according to jump_pc[T2] */
48
7a3f1944 49typedef struct DisasContext {
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50 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
51 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
52 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 53 int is_br;
e8af50a3 54 int mem_idx;
cf495bcf 55 struct TranslationBlock *tb;
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56} DisasContext;
57
58static uint16_t *gen_opc_ptr;
59static uint32_t *gen_opparam_ptr;
60extern FILE *logfile;
61extern int loglevel;
62
63enum {
64#define DEF(s,n,copy_size) INDEX_op_ ## s,
65#include "opc.h"
66#undef DEF
cf495bcf 67 NB_OPS
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68};
69
70#include "gen-op.h"
71
3475187d 72// This function uses non-native bit order
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73#define GET_FIELD(X, FROM, TO) \
74 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
75
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76// This function uses the order in the manuals, i.e. bit 0 is 2^0
77#define GET_FIELD_SP(X, FROM, TO) \
78 GET_FIELD(X, 31 - (TO), 31 - (FROM))
79
80#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
81#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), 32 - ((b) - (a) + 1))
82
83#ifdef TARGET_SPARC64
84#define DFPREG(r) (((r & 1) << 6) | (r & 0x1e))
85#else
86#define DFPREG(r) (r)
87#endif
88
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89#ifdef USE_DIRECT_JUMP
90#define TBPARAM(x)
91#else
92#define TBPARAM(x) (long)(x)
93#endif
94
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95static int sign_extend(int x, int len)
96{
97 len = 32 - len;
98 return (x << len) >> len;
99}
100
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101#define IS_IMM (insn & (1<<13))
102
cf495bcf 103static void disas_sparc_insn(DisasContext * dc);
7a3f1944 104
7a3f1944 105static GenOpFunc *gen_op_movl_TN_reg[2][32] = {
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106 {
107 gen_op_movl_g0_T0,
108 gen_op_movl_g1_T0,
109 gen_op_movl_g2_T0,
110 gen_op_movl_g3_T0,
111 gen_op_movl_g4_T0,
112 gen_op_movl_g5_T0,
113 gen_op_movl_g6_T0,
114 gen_op_movl_g7_T0,
115 gen_op_movl_o0_T0,
116 gen_op_movl_o1_T0,
117 gen_op_movl_o2_T0,
118 gen_op_movl_o3_T0,
119 gen_op_movl_o4_T0,
120 gen_op_movl_o5_T0,
121 gen_op_movl_o6_T0,
122 gen_op_movl_o7_T0,
123 gen_op_movl_l0_T0,
124 gen_op_movl_l1_T0,
125 gen_op_movl_l2_T0,
126 gen_op_movl_l3_T0,
127 gen_op_movl_l4_T0,
128 gen_op_movl_l5_T0,
129 gen_op_movl_l6_T0,
130 gen_op_movl_l7_T0,
131 gen_op_movl_i0_T0,
132 gen_op_movl_i1_T0,
133 gen_op_movl_i2_T0,
134 gen_op_movl_i3_T0,
135 gen_op_movl_i4_T0,
136 gen_op_movl_i5_T0,
137 gen_op_movl_i6_T0,
138 gen_op_movl_i7_T0,
139 },
140 {
141 gen_op_movl_g0_T1,
142 gen_op_movl_g1_T1,
143 gen_op_movl_g2_T1,
144 gen_op_movl_g3_T1,
145 gen_op_movl_g4_T1,
146 gen_op_movl_g5_T1,
147 gen_op_movl_g6_T1,
148 gen_op_movl_g7_T1,
149 gen_op_movl_o0_T1,
150 gen_op_movl_o1_T1,
151 gen_op_movl_o2_T1,
152 gen_op_movl_o3_T1,
153 gen_op_movl_o4_T1,
154 gen_op_movl_o5_T1,
155 gen_op_movl_o6_T1,
156 gen_op_movl_o7_T1,
157 gen_op_movl_l0_T1,
158 gen_op_movl_l1_T1,
159 gen_op_movl_l2_T1,
160 gen_op_movl_l3_T1,
161 gen_op_movl_l4_T1,
162 gen_op_movl_l5_T1,
163 gen_op_movl_l6_T1,
164 gen_op_movl_l7_T1,
165 gen_op_movl_i0_T1,
166 gen_op_movl_i1_T1,
167 gen_op_movl_i2_T1,
168 gen_op_movl_i3_T1,
169 gen_op_movl_i4_T1,
170 gen_op_movl_i5_T1,
171 gen_op_movl_i6_T1,
172 gen_op_movl_i7_T1,
173 }
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174};
175
176static GenOpFunc *gen_op_movl_reg_TN[3][32] = {
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177 {
178 gen_op_movl_T0_g0,
179 gen_op_movl_T0_g1,
180 gen_op_movl_T0_g2,
181 gen_op_movl_T0_g3,
182 gen_op_movl_T0_g4,
183 gen_op_movl_T0_g5,
184 gen_op_movl_T0_g6,
185 gen_op_movl_T0_g7,
186 gen_op_movl_T0_o0,
187 gen_op_movl_T0_o1,
188 gen_op_movl_T0_o2,
189 gen_op_movl_T0_o3,
190 gen_op_movl_T0_o4,
191 gen_op_movl_T0_o5,
192 gen_op_movl_T0_o6,
193 gen_op_movl_T0_o7,
194 gen_op_movl_T0_l0,
195 gen_op_movl_T0_l1,
196 gen_op_movl_T0_l2,
197 gen_op_movl_T0_l3,
198 gen_op_movl_T0_l4,
199 gen_op_movl_T0_l5,
200 gen_op_movl_T0_l6,
201 gen_op_movl_T0_l7,
202 gen_op_movl_T0_i0,
203 gen_op_movl_T0_i1,
204 gen_op_movl_T0_i2,
205 gen_op_movl_T0_i3,
206 gen_op_movl_T0_i4,
207 gen_op_movl_T0_i5,
208 gen_op_movl_T0_i6,
209 gen_op_movl_T0_i7,
210 },
211 {
212 gen_op_movl_T1_g0,
213 gen_op_movl_T1_g1,
214 gen_op_movl_T1_g2,
215 gen_op_movl_T1_g3,
216 gen_op_movl_T1_g4,
217 gen_op_movl_T1_g5,
218 gen_op_movl_T1_g6,
219 gen_op_movl_T1_g7,
220 gen_op_movl_T1_o0,
221 gen_op_movl_T1_o1,
222 gen_op_movl_T1_o2,
223 gen_op_movl_T1_o3,
224 gen_op_movl_T1_o4,
225 gen_op_movl_T1_o5,
226 gen_op_movl_T1_o6,
227 gen_op_movl_T1_o7,
228 gen_op_movl_T1_l0,
229 gen_op_movl_T1_l1,
230 gen_op_movl_T1_l2,
231 gen_op_movl_T1_l3,
232 gen_op_movl_T1_l4,
233 gen_op_movl_T1_l5,
234 gen_op_movl_T1_l6,
235 gen_op_movl_T1_l7,
236 gen_op_movl_T1_i0,
237 gen_op_movl_T1_i1,
238 gen_op_movl_T1_i2,
239 gen_op_movl_T1_i3,
240 gen_op_movl_T1_i4,
241 gen_op_movl_T1_i5,
242 gen_op_movl_T1_i6,
243 gen_op_movl_T1_i7,
244 },
245 {
246 gen_op_movl_T2_g0,
247 gen_op_movl_T2_g1,
248 gen_op_movl_T2_g2,
249 gen_op_movl_T2_g3,
250 gen_op_movl_T2_g4,
251 gen_op_movl_T2_g5,
252 gen_op_movl_T2_g6,
253 gen_op_movl_T2_g7,
254 gen_op_movl_T2_o0,
255 gen_op_movl_T2_o1,
256 gen_op_movl_T2_o2,
257 gen_op_movl_T2_o3,
258 gen_op_movl_T2_o4,
259 gen_op_movl_T2_o5,
260 gen_op_movl_T2_o6,
261 gen_op_movl_T2_o7,
262 gen_op_movl_T2_l0,
263 gen_op_movl_T2_l1,
264 gen_op_movl_T2_l2,
265 gen_op_movl_T2_l3,
266 gen_op_movl_T2_l4,
267 gen_op_movl_T2_l5,
268 gen_op_movl_T2_l6,
269 gen_op_movl_T2_l7,
270 gen_op_movl_T2_i0,
271 gen_op_movl_T2_i1,
272 gen_op_movl_T2_i2,
273 gen_op_movl_T2_i3,
274 gen_op_movl_T2_i4,
275 gen_op_movl_T2_i5,
276 gen_op_movl_T2_i6,
277 gen_op_movl_T2_i7,
278 }
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279};
280
281static GenOpFunc1 *gen_op_movl_TN_im[3] = {
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282 gen_op_movl_T0_im,
283 gen_op_movl_T1_im,
284 gen_op_movl_T2_im
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285};
286
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287// Sign extending version
288static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {
289 gen_op_movl_T0_sim,
290 gen_op_movl_T1_sim,
291 gen_op_movl_T2_sim
292};
293
294#ifdef TARGET_SPARC64
295#define GEN32(func, NAME) \
296static GenOpFunc *NAME ## _table [64] = { \
297NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
298NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
299NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
300NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
301NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
302NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
303NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
304NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
305NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
306NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
307NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
308NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
309}; \
310static inline void func(int n) \
311{ \
312 NAME ## _table[n](); \
313}
314#else
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315#define GEN32(func, NAME) \
316static GenOpFunc *NAME ## _table [32] = { \
317NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
318NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
319NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
320NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
321NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
322NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
323NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
324NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
325}; \
326static inline void func(int n) \
327{ \
328 NAME ## _table[n](); \
329}
3475187d 330#endif
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331
332/* floating point registers moves */
333GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
334GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
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335GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
336GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
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337
338GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
339GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
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340GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
341GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
e8af50a3 342
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343#ifdef TARGET_SPARC64
344// 'a' versions allowed to user depending on asi
345#if defined(CONFIG_USER_ONLY)
346#define supervisor(dc) 0
347#define gen_op_ldst(name) gen_op_##name##_raw()
348#define OP_LD_TABLE(width) \
349 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
350 { \
351 int asi, offset; \
352 \
353 if (IS_IMM) { \
354 offset = GET_FIELD(insn, 25, 31); \
355 if (is_ld) \
356 gen_op_ld_asi_reg(offset, size, sign); \
357 else \
358 gen_op_st_asi_reg(offset, size, sign); \
359 return; \
360 } \
361 asi = GET_FIELD(insn, 19, 26); \
362 switch (asi) { \
363 case 0x80: /* Primary address space */ \
364 gen_op_##width##_raw(); \
365 break; \
366 default: \
367 break; \
368 } \
369 }
370
371#else
372#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
373#define OP_LD_TABLE(width) \
374 static GenOpFunc *gen_op_##width[] = { \
375 &gen_op_##width##_user, \
376 &gen_op_##width##_kernel, \
377 }; \
378 \
379 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
380 { \
381 int asi, offset; \
382 \
383 if (IS_IMM) { \
384 offset = GET_FIELD(insn, 25, 31); \
385 if (is_ld) \
386 gen_op_ld_asi_reg(offset, size, sign); \
387 else \
388 gen_op_st_asi_reg(offset, size, sign); \
389 return; \
390 } \
391 asi = GET_FIELD(insn, 19, 26); \
392 if (is_ld) \
393 gen_op_ld_asi(asi, size, sign); \
394 else \
395 gen_op_st_asi(asi, size, sign); \
396 }
397
398#define supervisor(dc) (dc->mem_idx == 1)
399#endif
400#else
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401#if defined(CONFIG_USER_ONLY)
402#define gen_op_ldst(name) gen_op_##name##_raw()
0fa85d43 403#define OP_LD_TABLE(width)
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404#define supervisor(dc) 0
405#else
406#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
407#define OP_LD_TABLE(width) \
408static GenOpFunc *gen_op_##width[] = { \
409 &gen_op_##width##_user, \
410 &gen_op_##width##_kernel, \
411}; \
412 \
413static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
414{ \
415 int asi; \
416 \
417 asi = GET_FIELD(insn, 19, 26); \
418 switch (asi) { \
419 case 10: /* User data access */ \
420 gen_op_##width##_user(); \
421 break; \
422 case 11: /* Supervisor data access */ \
423 gen_op_##width##_kernel(); \
424 break; \
425 case 0x20 ... 0x2f: /* MMU passthrough */ \
426 if (is_ld) \
427 gen_op_ld_asi(asi, size, sign); \
428 else \
429 gen_op_st_asi(asi, size, sign); \
430 break; \
431 default: \
432 if (is_ld) \
433 gen_op_ld_asi(asi, size, sign); \
434 else \
435 gen_op_st_asi(asi, size, sign); \
436 break; \
437 } \
438}
439
440#define supervisor(dc) (dc->mem_idx == 1)
441#endif
3475187d 442#endif
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443
444OP_LD_TABLE(ld);
445OP_LD_TABLE(st);
446OP_LD_TABLE(ldub);
447OP_LD_TABLE(lduh);
448OP_LD_TABLE(ldsb);
449OP_LD_TABLE(ldsh);
450OP_LD_TABLE(stb);
451OP_LD_TABLE(sth);
452OP_LD_TABLE(std);
453OP_LD_TABLE(ldstub);
454OP_LD_TABLE(swap);
455OP_LD_TABLE(ldd);
456OP_LD_TABLE(stf);
457OP_LD_TABLE(stdf);
458OP_LD_TABLE(ldf);
459OP_LD_TABLE(lddf);
460
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461#ifdef TARGET_SPARC64
462OP_LD_TABLE(ldsw);
463OP_LD_TABLE(ldx);
464OP_LD_TABLE(stx);
465OP_LD_TABLE(cas);
466OP_LD_TABLE(casx);
467#endif
468
469static inline void gen_movl_imm_TN(int reg, uint32_t imm)
7a3f1944 470{
83469015 471 gen_op_movl_TN_im[reg](imm);
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472}
473
3475187d 474static inline void gen_movl_imm_T1(uint32_t val)
7a3f1944 475{
cf495bcf 476 gen_movl_imm_TN(1, val);
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477}
478
3475187d 479static inline void gen_movl_imm_T0(uint32_t val)
7a3f1944 480{
cf495bcf 481 gen_movl_imm_TN(0, val);
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482}
483
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484static inline void gen_movl_simm_TN(int reg, int32_t imm)
485{
486 gen_op_movl_TN_sim[reg](imm);
487}
488
489static inline void gen_movl_simm_T1(int32_t val)
490{
491 gen_movl_simm_TN(1, val);
492}
493
494static inline void gen_movl_simm_T0(int32_t val)
495{
496 gen_movl_simm_TN(0, val);
497}
498
cf495bcf 499static inline void gen_movl_reg_TN(int reg, int t)
7a3f1944 500{
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501 if (reg)
502 gen_op_movl_reg_TN[t][reg] ();
503 else
504 gen_movl_imm_TN(t, 0);
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505}
506
cf495bcf 507static inline void gen_movl_reg_T0(int reg)
7a3f1944 508{
cf495bcf 509 gen_movl_reg_TN(reg, 0);
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510}
511
cf495bcf 512static inline void gen_movl_reg_T1(int reg)
7a3f1944 513{
cf495bcf 514 gen_movl_reg_TN(reg, 1);
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515}
516
cf495bcf 517static inline void gen_movl_reg_T2(int reg)
7a3f1944 518{
cf495bcf 519 gen_movl_reg_TN(reg, 2);
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520}
521
cf495bcf 522static inline void gen_movl_TN_reg(int reg, int t)
7a3f1944 523{
cf495bcf
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524 if (reg)
525 gen_op_movl_TN_reg[t][reg] ();
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526}
527
cf495bcf 528static inline void gen_movl_T0_reg(int reg)
7a3f1944 529{
cf495bcf 530 gen_movl_TN_reg(reg, 0);
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531}
532
cf495bcf 533static inline void gen_movl_T1_reg(int reg)
7a3f1944 534{
cf495bcf 535 gen_movl_TN_reg(reg, 1);
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536}
537
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538static inline void gen_jmp_im(target_ulong pc)
539{
540#ifdef TARGET_SPARC64
541 if (pc == (uint32_t)pc) {
542 gen_op_jmp_im(pc);
543 } else {
544 gen_op_jmp_im64(pc >> 32, pc);
545 }
546#else
547 gen_op_jmp_im(pc);
548#endif
549}
550
551static inline void gen_movl_npc_im(target_ulong npc)
552{
553#ifdef TARGET_SPARC64
554 if (npc == (uint32_t)npc) {
555 gen_op_movl_npc_im(npc);
556 } else {
557 gen_op_movq_npc_im64(npc >> 32, npc);
558 }
559#else
560 gen_op_movl_npc_im(npc);
561#endif
562}
563
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564static inline void gen_goto_tb(DisasContext *s, int tb_num,
565 target_ulong pc, target_ulong npc)
566{
567 TranslationBlock *tb;
568
569 tb = s->tb;
570 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
571 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
572 /* jump to same page: we can use a direct jump */
573 if (tb_num == 0)
574 gen_op_goto_tb0(TBPARAM(tb));
575 else
576 gen_op_goto_tb1(TBPARAM(tb));
577 gen_jmp_im(pc);
578 gen_movl_npc_im(npc);
579 gen_op_movl_T0_im((long)tb + tb_num);
580 gen_op_exit_tb();
581 } else {
582 /* jump to another page: currently not optimized */
583 gen_jmp_im(pc);
584 gen_movl_npc_im(npc);
585 gen_op_movl_T0_0();
586 gen_op_exit_tb();
587 }
588}
589
83469015
FB
590static inline void gen_branch2(DisasContext *dc, long tb, target_ulong pc1, target_ulong pc2)
591{
592 int l1;
593
594 l1 = gen_new_label();
595
596 gen_op_jz_T2_label(l1);
597
6e256c93 598 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB
599
600 gen_set_label(l1);
6e256c93 601 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB
602}
603
604static inline void gen_branch_a(DisasContext *dc, long tb, target_ulong pc1, target_ulong pc2)
605{
606 int l1;
607
608 l1 = gen_new_label();
609
610 gen_op_jz_T2_label(l1);
611
6e256c93 612 gen_goto_tb(dc, 0, pc2, pc1);
83469015
FB
613
614 gen_set_label(l1);
6e256c93 615 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
83469015
FB
616}
617
618static inline void gen_branch(DisasContext *dc, long tb, target_ulong pc, target_ulong npc)
619{
6e256c93 620 gen_goto_tb(dc, 0, pc, npc);
83469015
FB
621}
622
623static inline void gen_generic_branch(DisasContext *dc, target_ulong npc1, target_ulong npc2)
624{
625 int l1, l2;
626
627 l1 = gen_new_label();
628 l2 = gen_new_label();
629 gen_op_jz_T2_label(l1);
630
631 gen_movl_npc_im(npc1);
632 gen_op_jmp_label(l2);
633
634 gen_set_label(l1);
635 gen_movl_npc_im(npc2);
636 gen_set_label(l2);
637}
638
639/* call this function before using T2 as it may have been set for a jump */
640static inline void flush_T2(DisasContext * dc)
641{
642 if (dc->npc == JUMP_PC) {
643 gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
644 dc->npc = DYNAMIC_PC;
645 }
646}
647
72cbca10
FB
648static inline void save_npc(DisasContext * dc)
649{
650 if (dc->npc == JUMP_PC) {
83469015 651 gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
72cbca10
FB
652 dc->npc = DYNAMIC_PC;
653 } else if (dc->npc != DYNAMIC_PC) {
3475187d 654 gen_movl_npc_im(dc->npc);
72cbca10
FB
655 }
656}
657
658static inline void save_state(DisasContext * dc)
659{
3475187d 660 gen_jmp_im(dc->pc);
72cbca10
FB
661 save_npc(dc);
662}
663
0bee699e
FB
664static inline void gen_mov_pc_npc(DisasContext * dc)
665{
666 if (dc->npc == JUMP_PC) {
83469015 667 gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
0bee699e
FB
668 gen_op_mov_pc_npc();
669 dc->pc = DYNAMIC_PC;
670 } else if (dc->npc == DYNAMIC_PC) {
671 gen_op_mov_pc_npc();
672 dc->pc = DYNAMIC_PC;
673 } else {
674 dc->pc = dc->npc;
675 }
676}
677
3475187d
FB
678static GenOpFunc * const gen_cond[2][16] = {
679 {
680 gen_op_eval_ba,
681 gen_op_eval_be,
682 gen_op_eval_ble,
683 gen_op_eval_bl,
684 gen_op_eval_bleu,
685 gen_op_eval_bcs,
686 gen_op_eval_bneg,
687 gen_op_eval_bvs,
688 gen_op_eval_bn,
689 gen_op_eval_bne,
690 gen_op_eval_bg,
691 gen_op_eval_bge,
692 gen_op_eval_bgu,
693 gen_op_eval_bcc,
694 gen_op_eval_bpos,
695 gen_op_eval_bvc,
696 },
697 {
698#ifdef TARGET_SPARC64
699 gen_op_eval_ba,
700 gen_op_eval_xbe,
701 gen_op_eval_xble,
702 gen_op_eval_xbl,
703 gen_op_eval_xbleu,
704 gen_op_eval_xbcs,
705 gen_op_eval_xbneg,
706 gen_op_eval_xbvs,
707 gen_op_eval_bn,
708 gen_op_eval_xbne,
709 gen_op_eval_xbg,
710 gen_op_eval_xbge,
711 gen_op_eval_xbgu,
712 gen_op_eval_xbcc,
713 gen_op_eval_xbpos,
714 gen_op_eval_xbvc,
715#endif
716 },
717};
718
719static GenOpFunc * const gen_fcond[4][16] = {
720 {
721 gen_op_eval_ba,
722 gen_op_eval_fbne,
723 gen_op_eval_fblg,
724 gen_op_eval_fbul,
725 gen_op_eval_fbl,
726 gen_op_eval_fbug,
727 gen_op_eval_fbg,
728 gen_op_eval_fbu,
729 gen_op_eval_bn,
730 gen_op_eval_fbe,
731 gen_op_eval_fbue,
732 gen_op_eval_fbge,
733 gen_op_eval_fbuge,
734 gen_op_eval_fble,
735 gen_op_eval_fbule,
736 gen_op_eval_fbo,
737 },
738#ifdef TARGET_SPARC64
739 {
740 gen_op_eval_ba,
741 gen_op_eval_fbne_fcc1,
742 gen_op_eval_fblg_fcc1,
743 gen_op_eval_fbul_fcc1,
744 gen_op_eval_fbl_fcc1,
745 gen_op_eval_fbug_fcc1,
746 gen_op_eval_fbg_fcc1,
747 gen_op_eval_fbu_fcc1,
748 gen_op_eval_bn,
749 gen_op_eval_fbe_fcc1,
750 gen_op_eval_fbue_fcc1,
751 gen_op_eval_fbge_fcc1,
752 gen_op_eval_fbuge_fcc1,
753 gen_op_eval_fble_fcc1,
754 gen_op_eval_fbule_fcc1,
755 gen_op_eval_fbo_fcc1,
756 },
757 {
758 gen_op_eval_ba,
759 gen_op_eval_fbne_fcc2,
760 gen_op_eval_fblg_fcc2,
761 gen_op_eval_fbul_fcc2,
762 gen_op_eval_fbl_fcc2,
763 gen_op_eval_fbug_fcc2,
764 gen_op_eval_fbg_fcc2,
765 gen_op_eval_fbu_fcc2,
766 gen_op_eval_bn,
767 gen_op_eval_fbe_fcc2,
768 gen_op_eval_fbue_fcc2,
769 gen_op_eval_fbge_fcc2,
770 gen_op_eval_fbuge_fcc2,
771 gen_op_eval_fble_fcc2,
772 gen_op_eval_fbule_fcc2,
773 gen_op_eval_fbo_fcc2,
774 },
775 {
776 gen_op_eval_ba,
777 gen_op_eval_fbne_fcc3,
778 gen_op_eval_fblg_fcc3,
779 gen_op_eval_fbul_fcc3,
780 gen_op_eval_fbl_fcc3,
781 gen_op_eval_fbug_fcc3,
782 gen_op_eval_fbg_fcc3,
783 gen_op_eval_fbu_fcc3,
784 gen_op_eval_bn,
785 gen_op_eval_fbe_fcc3,
786 gen_op_eval_fbue_fcc3,
787 gen_op_eval_fbge_fcc3,
788 gen_op_eval_fbuge_fcc3,
789 gen_op_eval_fble_fcc3,
790 gen_op_eval_fbule_fcc3,
791 gen_op_eval_fbo_fcc3,
792 },
793#else
794 {}, {}, {},
795#endif
796};
7a3f1944 797
3475187d
FB
798#ifdef TARGET_SPARC64
799static void gen_cond_reg(int cond)
e8af50a3
FB
800{
801 switch (cond) {
e8af50a3 802 case 0x1:
3475187d 803 gen_op_eval_brz();
e8af50a3
FB
804 break;
805 case 0x2:
3475187d 806 gen_op_eval_brlez();
e8af50a3
FB
807 break;
808 case 0x3:
3475187d 809 gen_op_eval_brlz();
e8af50a3
FB
810 break;
811 case 0x5:
3475187d 812 gen_op_eval_brnz();
e8af50a3
FB
813 break;
814 case 0x6:
3475187d 815 gen_op_eval_brgz();
e8af50a3
FB
816 break;
817 default:
3475187d
FB
818 case 0x7:
819 gen_op_eval_brgez();
e8af50a3
FB
820 break;
821 }
822}
3475187d 823#endif
cf495bcf 824
0bee699e 825/* XXX: potentially incorrect if dynamic npc */
3475187d 826static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 827{
cf495bcf 828 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 829 target_ulong target = dc->pc + offset;
3475187d 830
cf495bcf
FB
831 if (cond == 0x0) {
832 /* unconditional not taken */
833 if (a) {
0bee699e 834 dc->pc = dc->npc + 4;
cf495bcf
FB
835 dc->npc = dc->pc + 4;
836 } else {
837 dc->pc = dc->npc;
838 dc->npc = dc->pc + 4;
839 }
840 } else if (cond == 0x8) {
841 /* unconditional taken */
842 if (a) {
72cbca10 843 dc->pc = target;
cf495bcf
FB
844 dc->npc = dc->pc + 4;
845 } else {
846 dc->pc = dc->npc;
72cbca10 847 dc->npc = target;
cf495bcf
FB
848 }
849 } else {
72cbca10 850 flush_T2(dc);
3475187d 851 gen_cond[cc][cond]();
cf495bcf 852 if (a) {
83469015 853 gen_branch_a(dc, (long)dc->tb, target, dc->npc);
cf495bcf 854 dc->is_br = 1;
cf495bcf
FB
855 } else {
856 dc->pc = dc->npc;
72cbca10
FB
857 dc->jump_pc[0] = target;
858 dc->jump_pc[1] = dc->npc + 4;
859 dc->npc = JUMP_PC;
cf495bcf
FB
860 }
861 }
7a3f1944
FB
862}
863
0bee699e 864/* XXX: potentially incorrect if dynamic npc */
3475187d 865static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB
866{
867 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB
868 target_ulong target = dc->pc + offset;
869
e8af50a3
FB
870 if (cond == 0x0) {
871 /* unconditional not taken */
872 if (a) {
873 dc->pc = dc->npc + 4;
874 dc->npc = dc->pc + 4;
875 } else {
876 dc->pc = dc->npc;
877 dc->npc = dc->pc + 4;
878 }
879 } else if (cond == 0x8) {
880 /* unconditional taken */
881 if (a) {
882 dc->pc = target;
883 dc->npc = dc->pc + 4;
884 } else {
885 dc->pc = dc->npc;
886 dc->npc = target;
887 }
888 } else {
889 flush_T2(dc);
3475187d 890 gen_fcond[cc][cond]();
e8af50a3 891 if (a) {
83469015 892 gen_branch_a(dc, (long)dc->tb, target, dc->npc);
e8af50a3
FB
893 dc->is_br = 1;
894 } else {
895 dc->pc = dc->npc;
896 dc->jump_pc[0] = target;
897 dc->jump_pc[1] = dc->npc + 4;
898 dc->npc = JUMP_PC;
899 }
900 }
901}
902
3475187d
FB
903#ifdef TARGET_SPARC64
904/* XXX: potentially incorrect if dynamic npc */
905static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
7a3f1944 906{
3475187d
FB
907 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
908 target_ulong target = dc->pc + offset;
909
910 flush_T2(dc);
911 gen_cond_reg(cond);
912 if (a) {
83469015 913 gen_branch_a(dc, (long)dc->tb, target, dc->npc);
3475187d
FB
914 dc->is_br = 1;
915 } else {
916 dc->pc = dc->npc;
917 dc->jump_pc[0] = target;
918 dc->jump_pc[1] = dc->npc + 4;
919 dc->npc = JUMP_PC;
920 }
7a3f1944
FB
921}
922
3475187d
FB
923static GenOpFunc * const gen_fcmps[4] = {
924 gen_op_fcmps,
925 gen_op_fcmps_fcc1,
926 gen_op_fcmps_fcc2,
927 gen_op_fcmps_fcc3,
928};
929
930static GenOpFunc * const gen_fcmpd[4] = {
931 gen_op_fcmpd,
932 gen_op_fcmpd_fcc1,
933 gen_op_fcmpd_fcc2,
934 gen_op_fcmpd_fcc3,
935};
936#endif
937
0bee699e 938/* before an instruction, dc->pc must be static */
cf495bcf
FB
939static void disas_sparc_insn(DisasContext * dc)
940{
941 unsigned int insn, opc, rs1, rs2, rd;
7a3f1944 942
0fa85d43 943 insn = ldl_code(dc->pc);
cf495bcf 944 opc = GET_FIELD(insn, 0, 1);
7a3f1944 945
cf495bcf
FB
946 rd = GET_FIELD(insn, 2, 6);
947 switch (opc) {
948 case 0: /* branches/sethi */
949 {
950 unsigned int xop = GET_FIELD(insn, 7, 9);
af7bf89b 951 int32_t target;
cf495bcf 952 switch (xop) {
3475187d 953#ifdef TARGET_SPARC64
af7bf89b 954 case 0x1: /* V9 BPcc */
3475187d
FB
955 {
956 int cc;
957
958 target = GET_FIELD_SP(insn, 0, 18);
959 target <<= 2;
960 target = sign_extend(target, 18);
961 cc = GET_FIELD_SP(insn, 20, 21);
962 if (cc == 0)
963 do_branch(dc, target, insn, 0);
964 else if (cc == 2)
965 do_branch(dc, target, insn, 1);
966 else
967 goto illegal_insn;
968 goto jmp_insn;
969 }
af7bf89b 970 case 0x3: /* V9 BPr */
3475187d
FB
971 {
972 target = GET_FIELD_SP(insn, 0, 13) |
973 (GET_FIELD_SP(insn, 20, 21) >> 7);
974 target <<= 2;
975 target = sign_extend(target, 16);
976 rs1 = GET_FIELD(insn, 13, 17);
83469015 977 gen_movl_reg_T0(rs1);
3475187d
FB
978 do_branch_reg(dc, target, insn);
979 goto jmp_insn;
980 }
af7bf89b 981 case 0x5: /* V9 FBPcc */
3475187d
FB
982 {
983 int cc = GET_FIELD_SP(insn, 20, 21);
984#if !defined(CONFIG_USER_ONLY)
55e4f664 985 save_state(dc);
3475187d
FB
986 gen_op_trap_ifnofpu();
987#endif
988 target = GET_FIELD_SP(insn, 0, 18);
989 target <<= 2;
990 target = sign_extend(target, 19);
991 do_fbranch(dc, target, insn, cc);
992 goto jmp_insn;
993 }
994#endif
cf495bcf 995 case 0x2: /* BN+x */
7a3f1944 996 {
3475187d 997 target = GET_FIELD(insn, 10, 31);
cf495bcf
FB
998 target <<= 2;
999 target = sign_extend(target, 22);
3475187d 1000 do_branch(dc, target, insn, 0);
cf495bcf 1001 goto jmp_insn;
7a3f1944 1002 }
e8af50a3
FB
1003 case 0x6: /* FBN+x */
1004 {
e80cfcfc 1005#if !defined(CONFIG_USER_ONLY)
55e4f664 1006 save_state(dc);
e80cfcfc
FB
1007 gen_op_trap_ifnofpu();
1008#endif
3475187d 1009 target = GET_FIELD(insn, 10, 31);
e8af50a3
FB
1010 target <<= 2;
1011 target = sign_extend(target, 22);
3475187d 1012 do_fbranch(dc, target, insn, 0);
e8af50a3
FB
1013 goto jmp_insn;
1014 }
cf495bcf 1015 case 0x4: /* SETHI */
e80cfcfc
FB
1016#define OPTIM
1017#if defined(OPTIM)
1018 if (rd) { // nop
1019#endif
3475187d
FB
1020 uint32_t value = GET_FIELD(insn, 10, 31);
1021 gen_movl_imm_T0(value << 10);
e80cfcfc
FB
1022 gen_movl_T0_reg(rd);
1023#if defined(OPTIM)
1024 }
1025#endif
cf495bcf 1026 break;
3475187d
FB
1027 case 0x0: /* UNIMPL */
1028 default:
1029 goto illegal_insn;
cf495bcf
FB
1030 }
1031 break;
1032 }
af7bf89b 1033 break;
cf495bcf
FB
1034 case 1:
1035 /*CALL*/ {
af7bf89b 1036 target_long target = GET_FIELDs(insn, 2, 31) << 2;
cf495bcf 1037
83469015
FB
1038#ifdef TARGET_SPARC64
1039 if (dc->pc == (uint32_t)dc->pc) {
1040 gen_op_movl_T0_im(dc->pc);
1041 } else {
1042 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1043 }
1044#else
af7bf89b 1045 gen_op_movl_T0_im(dc->pc);
83469015 1046#endif
cf495bcf 1047 gen_movl_T0_reg(15);
af7bf89b 1048 target += dc->pc;
0bee699e 1049 gen_mov_pc_npc(dc);
72cbca10 1050 dc->npc = target;
cf495bcf
FB
1051 }
1052 goto jmp_insn;
1053 case 2: /* FPU & Logical Operations */
1054 {
1055 unsigned int xop = GET_FIELD(insn, 7, 12);
1056 if (xop == 0x3a) { /* generate trap */
1057 int cond;
3475187d 1058
cf495bcf
FB
1059 rs1 = GET_FIELD(insn, 13, 17);
1060 gen_movl_reg_T0(rs1);
1061 if (IS_IMM) {
e8af50a3 1062 rs2 = GET_FIELD(insn, 25, 31);
e80cfcfc 1063#if defined(OPTIM)
e8af50a3 1064 if (rs2 != 0) {
e80cfcfc 1065#endif
3475187d 1066 gen_movl_simm_T1(rs2);
e80cfcfc
FB
1067 gen_op_add_T1_T0();
1068#if defined(OPTIM)
e8af50a3 1069 }
e80cfcfc 1070#endif
cf495bcf
FB
1071 } else {
1072 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc
FB
1073#if defined(OPTIM)
1074 if (rs2 != 0) {
1075#endif
1076 gen_movl_reg_T1(rs2);
1077 gen_op_add_T1_T0();
1078#if defined(OPTIM)
1079 }
1080#endif
cf495bcf 1081 }
cf495bcf
FB
1082 save_state(dc);
1083 cond = GET_FIELD(insn, 3, 6);
1084 if (cond == 0x8) {
1085 gen_op_trap_T0();
1086 dc->is_br = 1;
1087 goto jmp_insn;
af7bf89b 1088 } else if (cond != 0) {
3475187d
FB
1089#ifdef TARGET_SPARC64
1090 /* V9 icc/xcc */
1091 int cc = GET_FIELD_SP(insn, 11, 12);
1092 if (cc == 0)
1093 gen_cond[0][cond]();
1094 else if (cc == 2)
1095 gen_cond[1][cond]();
1096 else
1097 goto illegal_insn;
1098#else
1099 gen_cond[0][cond]();
1100#endif
cf495bcf
FB
1101 gen_op_trapcc_T0();
1102 }
1103 } else if (xop == 0x28) {
1104 rs1 = GET_FIELD(insn, 13, 17);
1105 switch(rs1) {
1106 case 0: /* rdy */
3475187d 1107 gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
cf495bcf
FB
1108 gen_movl_T0_reg(rd);
1109 break;
af7bf89b 1110 case 15: /* stbar / V9 membar */
e8af50a3 1111 break; /* no effect? */
3475187d 1112#ifdef TARGET_SPARC64
af7bf89b 1113 case 0x2: /* V9 rdccr */
3475187d
FB
1114 gen_op_rdccr();
1115 gen_movl_T0_reg(rd);
1116 break;
af7bf89b 1117 case 0x3: /* V9 rdasi */
3475187d
FB
1118 gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
1119 gen_movl_T0_reg(rd);
1120 break;
af7bf89b 1121 case 0x4: /* V9 rdtick */
3475187d
FB
1122 gen_op_rdtick();
1123 gen_movl_T0_reg(rd);
1124 break;
af7bf89b 1125 case 0x5: /* V9 rdpc */
3475187d
FB
1126 gen_op_movl_T0_im(dc->pc);
1127 gen_movl_T0_reg(rd);
1128 break;
af7bf89b 1129 case 0x6: /* V9 rdfprs */
3475187d
FB
1130 gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
1131 gen_movl_T0_reg(rd);
1132 break;
83469015
FB
1133 case 0x17: /* Tick compare */
1134 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
1135 gen_movl_T0_reg(rd);
1136 break;
1137 case 0x18: /* System tick */
1138 gen_op_rdtick(); // XXX
1139 gen_movl_T0_reg(rd);
1140 break;
1141 case 0x19: /* System tick compare */
1142 gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
1143 gen_movl_T0_reg(rd);
1144 break;
1145 case 0x10: /* Performance Control */
1146 case 0x11: /* Performance Instrumentation Counter */
1147 case 0x12: /* Dispatch Control */
1148 case 0x13: /* Graphics Status */
1149 case 0x14: /* Softint set, WO */
1150 case 0x15: /* Softint clear, WO */
1151 case 0x16: /* Softint write */
3475187d
FB
1152#endif
1153 default:
cf495bcf
FB
1154 goto illegal_insn;
1155 }
e8af50a3 1156#if !defined(CONFIG_USER_ONLY)
3475187d
FB
1157#ifndef TARGET_SPARC64
1158 } else if (xop == 0x29) { /* rdpsr / V9 unimp */
e8af50a3
FB
1159 if (!supervisor(dc))
1160 goto priv_insn;
1161 gen_op_rdpsr();
1162 gen_movl_T0_reg(rd);
1163 break;
3475187d
FB
1164#endif
1165 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
e8af50a3
FB
1166 if (!supervisor(dc))
1167 goto priv_insn;
3475187d
FB
1168#ifdef TARGET_SPARC64
1169 rs1 = GET_FIELD(insn, 13, 17);
1170 switch (rs1) {
1171 case 0: // tpc
1172 gen_op_rdtpc();
1173 break;
1174 case 1: // tnpc
1175 gen_op_rdtnpc();
1176 break;
1177 case 2: // tstate
1178 gen_op_rdtstate();
1179 break;
1180 case 3: // tt
1181 gen_op_rdtt();
1182 break;
1183 case 4: // tick
1184 gen_op_rdtick();
1185 break;
1186 case 5: // tba
1187 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1188 break;
1189 case 6: // pstate
1190 gen_op_rdpstate();
1191 break;
1192 case 7: // tl
1193 gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1194 break;
1195 case 8: // pil
1196 gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1197 break;
1198 case 9: // cwp
1199 gen_op_rdcwp();
1200 break;
1201 case 10: // cansave
1202 gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1203 break;
1204 case 11: // canrestore
1205 gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1206 break;
1207 case 12: // cleanwin
1208 gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1209 break;
1210 case 13: // otherwin
1211 gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1212 break;
1213 case 14: // wstate
1214 gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1215 break;
1216 case 31: // ver
1217 gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1218 break;
1219 case 15: // fq
1220 default:
1221 goto illegal_insn;
1222 }
1223#else
1224 gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
1225#endif
e8af50a3
FB
1226 gen_movl_T0_reg(rd);
1227 break;
3475187d
FB
1228 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1229#ifdef TARGET_SPARC64
1230 gen_op_flushw();
1231#else
e8af50a3
FB
1232 if (!supervisor(dc))
1233 goto priv_insn;
3475187d 1234 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
e8af50a3 1235 gen_movl_T0_reg(rd);
3475187d 1236#endif
e8af50a3
FB
1237 break;
1238#endif
e80cfcfc
FB
1239 } else if (xop == 0x34) { /* FPU Operations */
1240#if !defined(CONFIG_USER_ONLY)
55e4f664 1241 save_state(dc);
e80cfcfc
FB
1242 gen_op_trap_ifnofpu();
1243#endif
e8af50a3
FB
1244 rs1 = GET_FIELD(insn, 13, 17);
1245 rs2 = GET_FIELD(insn, 27, 31);
1246 xop = GET_FIELD(insn, 18, 26);
1247 switch (xop) {
1248 case 0x1: /* fmovs */
1249 gen_op_load_fpr_FT0(rs2);
1250 gen_op_store_FT0_fpr(rd);
1251 break;
1252 case 0x5: /* fnegs */
1253 gen_op_load_fpr_FT1(rs2);
1254 gen_op_fnegs();
1255 gen_op_store_FT0_fpr(rd);
1256 break;
1257 case 0x9: /* fabss */
1258 gen_op_load_fpr_FT1(rs2);
1259 gen_op_fabss();
1260 gen_op_store_FT0_fpr(rd);
1261 break;
1262 case 0x29: /* fsqrts */
1263 gen_op_load_fpr_FT1(rs2);
1264 gen_op_fsqrts();
1265 gen_op_store_FT0_fpr(rd);
1266 break;
1267 case 0x2a: /* fsqrtd */
3475187d 1268 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1269 gen_op_fsqrtd();
3475187d 1270 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1271 break;
e80cfcfc
FB
1272 case 0x2b: /* fsqrtq */
1273 goto nfpu_insn;
e8af50a3
FB
1274 case 0x41:
1275 gen_op_load_fpr_FT0(rs1);
1276 gen_op_load_fpr_FT1(rs2);
1277 gen_op_fadds();
1278 gen_op_store_FT0_fpr(rd);
1279 break;
1280 case 0x42:
3475187d
FB
1281 gen_op_load_fpr_DT0(DFPREG(rs1));
1282 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1283 gen_op_faddd();
3475187d 1284 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1285 break;
e80cfcfc
FB
1286 case 0x43: /* faddq */
1287 goto nfpu_insn;
e8af50a3
FB
1288 case 0x45:
1289 gen_op_load_fpr_FT0(rs1);
1290 gen_op_load_fpr_FT1(rs2);
1291 gen_op_fsubs();
1292 gen_op_store_FT0_fpr(rd);
1293 break;
1294 case 0x46:
3475187d
FB
1295 gen_op_load_fpr_DT0(DFPREG(rs1));
1296 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1297 gen_op_fsubd();
3475187d 1298 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1299 break;
e80cfcfc
FB
1300 case 0x47: /* fsubq */
1301 goto nfpu_insn;
e8af50a3
FB
1302 case 0x49:
1303 gen_op_load_fpr_FT0(rs1);
1304 gen_op_load_fpr_FT1(rs2);
1305 gen_op_fmuls();
1306 gen_op_store_FT0_fpr(rd);
1307 break;
1308 case 0x4a:
3475187d
FB
1309 gen_op_load_fpr_DT0(DFPREG(rs1));
1310 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3
FB
1311 gen_op_fmuld();
1312 gen_op_store_DT0_fpr(rd);
1313 break;
e80cfcfc
FB
1314 case 0x4b: /* fmulq */
1315 goto nfpu_insn;
e8af50a3
FB
1316 case 0x4d:
1317 gen_op_load_fpr_FT0(rs1);
1318 gen_op_load_fpr_FT1(rs2);
1319 gen_op_fdivs();
1320 gen_op_store_FT0_fpr(rd);
1321 break;
1322 case 0x4e:
3475187d
FB
1323 gen_op_load_fpr_DT0(DFPREG(rs1));
1324 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1325 gen_op_fdivd();
3475187d 1326 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1327 break;
e80cfcfc
FB
1328 case 0x4f: /* fdivq */
1329 goto nfpu_insn;
e8af50a3
FB
1330 case 0x69:
1331 gen_op_load_fpr_FT0(rs1);
1332 gen_op_load_fpr_FT1(rs2);
1333 gen_op_fsmuld();
3475187d 1334 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1335 break;
e80cfcfc
FB
1336 case 0x6e: /* fdmulq */
1337 goto nfpu_insn;
e8af50a3
FB
1338 case 0xc4:
1339 gen_op_load_fpr_FT1(rs2);
1340 gen_op_fitos();
1341 gen_op_store_FT0_fpr(rd);
1342 break;
1343 case 0xc6:
3475187d 1344 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3
FB
1345 gen_op_fdtos();
1346 gen_op_store_FT0_fpr(rd);
1347 break;
e80cfcfc
FB
1348 case 0xc7: /* fqtos */
1349 goto nfpu_insn;
e8af50a3
FB
1350 case 0xc8:
1351 gen_op_load_fpr_FT1(rs2);
1352 gen_op_fitod();
3475187d 1353 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3
FB
1354 break;
1355 case 0xc9:
1356 gen_op_load_fpr_FT1(rs2);
1357 gen_op_fstod();
3475187d 1358 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1359 break;
e80cfcfc
FB
1360 case 0xcb: /* fqtod */
1361 goto nfpu_insn;
1362 case 0xcc: /* fitoq */
1363 goto nfpu_insn;
1364 case 0xcd: /* fstoq */
1365 goto nfpu_insn;
1366 case 0xce: /* fdtoq */
1367 goto nfpu_insn;
e8af50a3
FB
1368 case 0xd1:
1369 gen_op_load_fpr_FT1(rs2);
1370 gen_op_fstoi();
1371 gen_op_store_FT0_fpr(rd);
1372 break;
1373 case 0xd2:
1374 gen_op_load_fpr_DT1(rs2);
1375 gen_op_fdtoi();
1376 gen_op_store_FT0_fpr(rd);
1377 break;
e80cfcfc
FB
1378 case 0xd3: /* fqtoi */
1379 goto nfpu_insn;
3475187d 1380#ifdef TARGET_SPARC64
af7bf89b 1381 case 0x2: /* V9 fmovd */
3475187d
FB
1382 gen_op_load_fpr_DT0(DFPREG(rs2));
1383 gen_op_store_DT0_fpr(DFPREG(rd));
1384 break;
af7bf89b 1385 case 0x6: /* V9 fnegd */
3475187d
FB
1386 gen_op_load_fpr_DT1(DFPREG(rs2));
1387 gen_op_fnegd();
1388 gen_op_store_DT0_fpr(DFPREG(rd));
1389 break;
af7bf89b 1390 case 0xa: /* V9 fabsd */
3475187d
FB
1391 gen_op_load_fpr_DT1(DFPREG(rs2));
1392 gen_op_fabsd();
1393 gen_op_store_DT0_fpr(DFPREG(rd));
1394 break;
af7bf89b 1395 case 0x81: /* V9 fstox */
3475187d
FB
1396 gen_op_load_fpr_FT1(rs2);
1397 gen_op_fstox();
1398 gen_op_store_DT0_fpr(DFPREG(rd));
1399 break;
af7bf89b 1400 case 0x82: /* V9 fdtox */
3475187d
FB
1401 gen_op_load_fpr_DT1(DFPREG(rs2));
1402 gen_op_fdtox();
1403 gen_op_store_DT0_fpr(DFPREG(rd));
1404 break;
af7bf89b 1405 case 0x84: /* V9 fxtos */
3475187d
FB
1406 gen_op_load_fpr_DT1(DFPREG(rs2));
1407 gen_op_fxtos();
1408 gen_op_store_FT0_fpr(rd);
1409 break;
af7bf89b 1410 case 0x88: /* V9 fxtod */
3475187d
FB
1411 gen_op_load_fpr_DT1(DFPREG(rs2));
1412 gen_op_fxtod();
1413 gen_op_store_DT0_fpr(DFPREG(rd));
1414 break;
af7bf89b
FB
1415 case 0x3: /* V9 fmovq */
1416 case 0x7: /* V9 fnegq */
1417 case 0xb: /* V9 fabsq */
1418 case 0x83: /* V9 fqtox */
1419 case 0x8c: /* V9 fxtoq */
3475187d
FB
1420 goto nfpu_insn;
1421#endif
1422 default:
e8af50a3
FB
1423 goto illegal_insn;
1424 }
e80cfcfc 1425 } else if (xop == 0x35) { /* FPU Operations */
3475187d
FB
1426#ifdef TARGET_SPARC64
1427 int cond;
1428#endif
e80cfcfc 1429#if !defined(CONFIG_USER_ONLY)
55e4f664 1430 save_state(dc);
e80cfcfc
FB
1431 gen_op_trap_ifnofpu();
1432#endif
cf495bcf 1433 rs1 = GET_FIELD(insn, 13, 17);
e80cfcfc
FB
1434 rs2 = GET_FIELD(insn, 27, 31);
1435 xop = GET_FIELD(insn, 18, 26);
3475187d
FB
1436#ifdef TARGET_SPARC64
1437 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
1438 cond = GET_FIELD_SP(insn, 14, 17);
1439 gen_op_load_fpr_FT0(rd);
1440 gen_op_load_fpr_FT1(rs2);
1441 rs1 = GET_FIELD(insn, 13, 17);
1442 gen_movl_reg_T0(rs1);
1443 flush_T2(dc);
1444 gen_cond_reg(cond);
1445 gen_op_fmovs_cc();
1446 gen_op_store_FT0_fpr(rd);
1447 break;
1448 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
1449 cond = GET_FIELD_SP(insn, 14, 17);
1450 gen_op_load_fpr_DT0(rd);
1451 gen_op_load_fpr_DT1(rs2);
1452 flush_T2(dc);
1453 rs1 = GET_FIELD(insn, 13, 17);
1454 gen_movl_reg_T0(rs1);
1455 gen_cond_reg(cond);
1456 gen_op_fmovs_cc();
1457 gen_op_store_DT0_fpr(rd);
1458 break;
1459 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1460 goto nfpu_insn;
1461 }
1462#endif
e80cfcfc 1463 switch (xop) {
3475187d
FB
1464#ifdef TARGET_SPARC64
1465 case 0x001: /* V9 fmovscc %fcc0 */
1466 cond = GET_FIELD_SP(insn, 14, 17);
1467 gen_op_load_fpr_FT0(rd);
1468 gen_op_load_fpr_FT1(rs2);
1469 flush_T2(dc);
1470 gen_fcond[0][cond]();
1471 gen_op_fmovs_cc();
1472 gen_op_store_FT0_fpr(rd);
1473 break;
1474 case 0x002: /* V9 fmovdcc %fcc0 */
1475 cond = GET_FIELD_SP(insn, 14, 17);
1476 gen_op_load_fpr_DT0(rd);
1477 gen_op_load_fpr_DT1(rs2);
1478 flush_T2(dc);
1479 gen_fcond[0][cond]();
1480 gen_op_fmovd_cc();
1481 gen_op_store_DT0_fpr(rd);
1482 break;
1483 case 0x003: /* V9 fmovqcc %fcc0 */
1484 goto nfpu_insn;
1485 case 0x041: /* V9 fmovscc %fcc1 */
1486 cond = GET_FIELD_SP(insn, 14, 17);
1487 gen_op_load_fpr_FT0(rd);
1488 gen_op_load_fpr_FT1(rs2);
1489 flush_T2(dc);
1490 gen_fcond[1][cond]();
1491 gen_op_fmovs_cc();
1492 gen_op_store_FT0_fpr(rd);
1493 break;
1494 case 0x042: /* V9 fmovdcc %fcc1 */
1495 cond = GET_FIELD_SP(insn, 14, 17);
1496 gen_op_load_fpr_DT0(rd);
1497 gen_op_load_fpr_DT1(rs2);
1498 flush_T2(dc);
1499 gen_fcond[1][cond]();
1500 gen_op_fmovd_cc();
1501 gen_op_store_DT0_fpr(rd);
1502 break;
1503 case 0x043: /* V9 fmovqcc %fcc1 */
1504 goto nfpu_insn;
1505 case 0x081: /* V9 fmovscc %fcc2 */
1506 cond = GET_FIELD_SP(insn, 14, 17);
1507 gen_op_load_fpr_FT0(rd);
1508 gen_op_load_fpr_FT1(rs2);
1509 flush_T2(dc);
1510 gen_fcond[2][cond]();
1511 gen_op_fmovs_cc();
1512 gen_op_store_FT0_fpr(rd);
1513 break;
1514 case 0x082: /* V9 fmovdcc %fcc2 */
1515 cond = GET_FIELD_SP(insn, 14, 17);
1516 gen_op_load_fpr_DT0(rd);
1517 gen_op_load_fpr_DT1(rs2);
1518 flush_T2(dc);
1519 gen_fcond[2][cond]();
1520 gen_op_fmovd_cc();
1521 gen_op_store_DT0_fpr(rd);
1522 break;
1523 case 0x083: /* V9 fmovqcc %fcc2 */
1524 goto nfpu_insn;
1525 case 0x0c1: /* V9 fmovscc %fcc3 */
1526 cond = GET_FIELD_SP(insn, 14, 17);
1527 gen_op_load_fpr_FT0(rd);
1528 gen_op_load_fpr_FT1(rs2);
1529 flush_T2(dc);
1530 gen_fcond[3][cond]();
1531 gen_op_fmovs_cc();
1532 gen_op_store_FT0_fpr(rd);
1533 break;
1534 case 0x0c2: /* V9 fmovdcc %fcc3 */
1535 cond = GET_FIELD_SP(insn, 14, 17);
1536 gen_op_load_fpr_DT0(rd);
1537 gen_op_load_fpr_DT1(rs2);
1538 flush_T2(dc);
1539 gen_fcond[3][cond]();
1540 gen_op_fmovd_cc();
1541 gen_op_store_DT0_fpr(rd);
1542 break;
1543 case 0x0c3: /* V9 fmovqcc %fcc3 */
1544 goto nfpu_insn;
1545 case 0x101: /* V9 fmovscc %icc */
1546 cond = GET_FIELD_SP(insn, 14, 17);
1547 gen_op_load_fpr_FT0(rd);
1548 gen_op_load_fpr_FT1(rs2);
1549 flush_T2(dc);
1550 gen_cond[0][cond]();
1551 gen_op_fmovs_cc();
1552 gen_op_store_FT0_fpr(rd);
1553 break;
1554 case 0x102: /* V9 fmovdcc %icc */
1555 cond = GET_FIELD_SP(insn, 14, 17);
1556 gen_op_load_fpr_DT0(rd);
1557 gen_op_load_fpr_DT1(rs2);
1558 flush_T2(dc);
1559 gen_cond[0][cond]();
1560 gen_op_fmovd_cc();
1561 gen_op_store_DT0_fpr(rd);
1562 break;
1563 case 0x103: /* V9 fmovqcc %icc */
1564 goto nfpu_insn;
1565 case 0x181: /* V9 fmovscc %xcc */
1566 cond = GET_FIELD_SP(insn, 14, 17);
1567 gen_op_load_fpr_FT0(rd);
1568 gen_op_load_fpr_FT1(rs2);
1569 flush_T2(dc);
1570 gen_cond[1][cond]();
1571 gen_op_fmovs_cc();
1572 gen_op_store_FT0_fpr(rd);
1573 break;
1574 case 0x182: /* V9 fmovdcc %xcc */
1575 cond = GET_FIELD_SP(insn, 14, 17);
1576 gen_op_load_fpr_DT0(rd);
1577 gen_op_load_fpr_DT1(rs2);
1578 flush_T2(dc);
1579 gen_cond[1][cond]();
1580 gen_op_fmovd_cc();
1581 gen_op_store_DT0_fpr(rd);
1582 break;
1583 case 0x183: /* V9 fmovqcc %xcc */
1584 goto nfpu_insn;
1585#endif
1586 case 0x51: /* V9 %fcc */
e80cfcfc
FB
1587 gen_op_load_fpr_FT0(rs1);
1588 gen_op_load_fpr_FT1(rs2);
3475187d
FB
1589#ifdef TARGET_SPARC64
1590 gen_fcmps[rd & 3]();
1591#else
e80cfcfc 1592 gen_op_fcmps();
3475187d 1593#endif
e80cfcfc 1594 break;
3475187d
FB
1595 case 0x52: /* V9 %fcc */
1596 gen_op_load_fpr_DT0(DFPREG(rs1));
1597 gen_op_load_fpr_DT1(DFPREG(rs2));
1598#ifdef TARGET_SPARC64
1599 gen_fcmpd[rd & 3]();
1600#else
e80cfcfc 1601 gen_op_fcmpd();
3475187d 1602#endif
e80cfcfc
FB
1603 break;
1604 case 0x53: /* fcmpq */
1605 goto nfpu_insn;
3475187d 1606 case 0x55: /* fcmpes, V9 %fcc */
e80cfcfc
FB
1607 gen_op_load_fpr_FT0(rs1);
1608 gen_op_load_fpr_FT1(rs2);
3475187d
FB
1609#ifdef TARGET_SPARC64
1610 gen_fcmps[rd & 3]();
1611#else
e80cfcfc 1612 gen_op_fcmps(); /* XXX should trap if qNaN or sNaN */
3475187d 1613#endif
e80cfcfc 1614 break;
3475187d
FB
1615 case 0x56: /* fcmped, V9 %fcc */
1616 gen_op_load_fpr_DT0(DFPREG(rs1));
1617 gen_op_load_fpr_DT1(DFPREG(rs2));
1618#ifdef TARGET_SPARC64
1619 gen_fcmpd[rd & 3]();
1620#else
e80cfcfc 1621 gen_op_fcmpd(); /* XXX should trap if qNaN or sNaN */
3475187d 1622#endif
e80cfcfc
FB
1623 break;
1624 case 0x57: /* fcmpeq */
1625 goto nfpu_insn;
1626 default:
1627 goto illegal_insn;
1628 }
1629#if defined(OPTIM)
1630 } else if (xop == 0x2) {
1631 // clr/mov shortcut
1632
1633 rs1 = GET_FIELD(insn, 13, 17);
1634 if (rs1 == 0) {
1635 // or %g0, x, y -> mov T1, x; mov y, T1
1636 if (IS_IMM) { /* immediate */
1637 rs2 = GET_FIELDs(insn, 19, 31);
3475187d 1638 gen_movl_simm_T1(rs2);
e80cfcfc
FB
1639 } else { /* register */
1640 rs2 = GET_FIELD(insn, 27, 31);
1641 gen_movl_reg_T1(rs2);
1642 }
1643 gen_movl_T1_reg(rd);
1644 } else {
1645 gen_movl_reg_T0(rs1);
1646 if (IS_IMM) { /* immediate */
1647 // or x, #0, y -> mov T1, x; mov y, T1
1648 rs2 = GET_FIELDs(insn, 19, 31);
1649 if (rs2 != 0) {
3475187d 1650 gen_movl_simm_T1(rs2);
e80cfcfc
FB
1651 gen_op_or_T1_T0();
1652 }
1653 } else { /* register */
1654 // or x, %g0, y -> mov T1, x; mov y, T1
1655 rs2 = GET_FIELD(insn, 27, 31);
1656 if (rs2 != 0) {
1657 gen_movl_reg_T1(rs2);
1658 gen_op_or_T1_T0();
1659 }
1660 }
1661 gen_movl_T0_reg(rd);
1662 }
83469015
FB
1663#endif
1664#ifdef TARGET_SPARC64
1665 } else if (xop == 0x25) { /* sll, V9 sllx ( == sll) */
1666 rs1 = GET_FIELD(insn, 13, 17);
1667 gen_movl_reg_T0(rs1);
1668 if (IS_IMM) { /* immediate */
1669 rs2 = GET_FIELDs(insn, 20, 31);
1670 gen_movl_simm_T1(rs2);
1671 } else { /* register */
1672 rs2 = GET_FIELD(insn, 27, 31);
1673 gen_movl_reg_T1(rs2);
1674 }
1675 gen_op_sll();
1676 gen_movl_T0_reg(rd);
1677 } else if (xop == 0x26) { /* srl, V9 srlx */
1678 rs1 = GET_FIELD(insn, 13, 17);
1679 gen_movl_reg_T0(rs1);
1680 if (IS_IMM) { /* immediate */
1681 rs2 = GET_FIELDs(insn, 20, 31);
1682 gen_movl_simm_T1(rs2);
1683 } else { /* register */
1684 rs2 = GET_FIELD(insn, 27, 31);
1685 gen_movl_reg_T1(rs2);
1686 }
1687 if (insn & (1 << 12))
1688 gen_op_srlx();
1689 else
1690 gen_op_srl();
1691 gen_movl_T0_reg(rd);
1692 } else if (xop == 0x27) { /* sra, V9 srax */
1693 rs1 = GET_FIELD(insn, 13, 17);
1694 gen_movl_reg_T0(rs1);
1695 if (IS_IMM) { /* immediate */
1696 rs2 = GET_FIELDs(insn, 20, 31);
1697 gen_movl_simm_T1(rs2);
1698 } else { /* register */
1699 rs2 = GET_FIELD(insn, 27, 31);
1700 gen_movl_reg_T1(rs2);
1701 }
1702 if (insn & (1 << 12))
1703 gen_op_srax();
1704 else
1705 gen_op_sra();
1706 gen_movl_T0_reg(rd);
e80cfcfc
FB
1707#endif
1708 } else if (xop < 0x38) {
1709 rs1 = GET_FIELD(insn, 13, 17);
1710 gen_movl_reg_T0(rs1);
1711 if (IS_IMM) { /* immediate */
cf495bcf 1712 rs2 = GET_FIELDs(insn, 19, 31);
3475187d 1713 gen_movl_simm_T1(rs2);
cf495bcf
FB
1714 } else { /* register */
1715 rs2 = GET_FIELD(insn, 27, 31);
1716 gen_movl_reg_T1(rs2);
1717 }
1718 if (xop < 0x20) {
1719 switch (xop & ~0x10) {
1720 case 0x0:
1721 if (xop & 0x10)
1722 gen_op_add_T1_T0_cc();
1723 else
1724 gen_op_add_T1_T0();
1725 break;
1726 case 0x1:
1727 gen_op_and_T1_T0();
1728 if (xop & 0x10)
1729 gen_op_logic_T0_cc();
1730 break;
1731 case 0x2:
e80cfcfc
FB
1732 gen_op_or_T1_T0();
1733 if (xop & 0x10)
1734 gen_op_logic_T0_cc();
1735 break;
cf495bcf
FB
1736 case 0x3:
1737 gen_op_xor_T1_T0();
1738 if (xop & 0x10)
1739 gen_op_logic_T0_cc();
1740 break;
1741 case 0x4:
1742 if (xop & 0x10)
1743 gen_op_sub_T1_T0_cc();
1744 else
1745 gen_op_sub_T1_T0();
1746 break;
1747 case 0x5:
1748 gen_op_andn_T1_T0();
1749 if (xop & 0x10)
1750 gen_op_logic_T0_cc();
1751 break;
1752 case 0x6:
1753 gen_op_orn_T1_T0();
1754 if (xop & 0x10)
1755 gen_op_logic_T0_cc();
1756 break;
1757 case 0x7:
1758 gen_op_xnor_T1_T0();
1759 if (xop & 0x10)
1760 gen_op_logic_T0_cc();
1761 break;
1762 case 0x8:
cf495bcf 1763 if (xop & 0x10)
af7bf89b
FB
1764 gen_op_addx_T1_T0_cc();
1765 else
1766 gen_op_addx_T1_T0();
cf495bcf
FB
1767 break;
1768 case 0xa:
1769 gen_op_umul_T1_T0();
1770 if (xop & 0x10)
1771 gen_op_logic_T0_cc();
1772 break;
1773 case 0xb:
1774 gen_op_smul_T1_T0();
1775 if (xop & 0x10)
1776 gen_op_logic_T0_cc();
1777 break;
1778 case 0xc:
cf495bcf 1779 if (xop & 0x10)
af7bf89b
FB
1780 gen_op_subx_T1_T0_cc();
1781 else
1782 gen_op_subx_T1_T0();
cf495bcf
FB
1783 break;
1784 case 0xe:
1785 gen_op_udiv_T1_T0();
1786 if (xop & 0x10)
1787 gen_op_div_cc();
1788 break;
1789 case 0xf:
1790 gen_op_sdiv_T1_T0();
1791 if (xop & 0x10)
1792 gen_op_div_cc();
1793 break;
1794 default:
1795 goto illegal_insn;
1796 }
e80cfcfc 1797 gen_movl_T0_reg(rd);
cf495bcf
FB
1798 } else {
1799 switch (xop) {
3475187d
FB
1800#ifdef TARGET_SPARC64
1801 case 0x9: /* V9 mulx */
1802 gen_op_mulx_T1_T0();
1803 gen_movl_T0_reg(rd);
1804 break;
1805 case 0xd: /* V9 udivx */
1806 gen_op_udivx_T1_T0();
1807 gen_movl_T0_reg(rd);
1808 break;
1809#endif
e80cfcfc
FB
1810 case 0x20: /* taddcc */
1811 case 0x21: /* tsubcc */
1812 case 0x22: /* taddcctv */
1813 case 0x23: /* tsubcctv */
1814 goto illegal_insn;
cf495bcf
FB
1815 case 0x24: /* mulscc */
1816 gen_op_mulscc_T1_T0();
1817 gen_movl_T0_reg(rd);
1818 break;
83469015
FB
1819#ifndef TARGET_SPARC64
1820 case 0x25: /* sll */
3475187d 1821 gen_op_sll();
cf495bcf
FB
1822 gen_movl_T0_reg(rd);
1823 break;
83469015 1824 case 0x26: /* srl */
3475187d 1825 gen_op_srl();
cf495bcf
FB
1826 gen_movl_T0_reg(rd);
1827 break;
83469015 1828 case 0x27: /* sra */
3475187d 1829 gen_op_sra();
cf495bcf
FB
1830 gen_movl_T0_reg(rd);
1831 break;
83469015 1832#endif
cf495bcf
FB
1833 case 0x30:
1834 {
cf495bcf 1835 switch(rd) {
3475187d
FB
1836 case 0: /* wry */
1837 gen_op_xor_T1_T0();
1838 gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
cf495bcf 1839 break;
3475187d 1840#ifdef TARGET_SPARC64
af7bf89b 1841 case 0x2: /* V9 wrccr */
3475187d
FB
1842 gen_op_wrccr();
1843 break;
af7bf89b 1844 case 0x3: /* V9 wrasi */
3475187d
FB
1845 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
1846 break;
af7bf89b 1847 case 0x6: /* V9 wrfprs */
3475187d
FB
1848 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
1849 break;
1850 case 0xf: /* V9 sir, nop if user */
1851#if !defined(CONFIG_USER_ONLY)
1852 if (supervisor(dc))
1853 gen_op_sir();
1854#endif
1855 break;
83469015
FB
1856 case 0x17: /* Tick compare */
1857#if !defined(CONFIG_USER_ONLY)
1858 if (!supervisor(dc))
1859 goto illegal_insn;
1860#endif
1861 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
1862 break;
1863 case 0x18: /* System tick */
1864#if !defined(CONFIG_USER_ONLY)
1865 if (!supervisor(dc))
1866 goto illegal_insn;
1867#endif
1868 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
1869 break;
1870 case 0x19: /* System tick compare */
1871#if !defined(CONFIG_USER_ONLY)
1872 if (!supervisor(dc))
1873 goto illegal_insn;
3475187d 1874#endif
83469015
FB
1875 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
1876 break;
1877
3475187d
FB
1878 case 0x10: /* Performance Control */
1879 case 0x11: /* Performance Instrumentation Counter */
1880 case 0x12: /* Dispatch Control */
1881 case 0x13: /* Graphics Status */
1882 case 0x14: /* Softint set */
1883 case 0x15: /* Softint clear */
1884 case 0x16: /* Softint write */
83469015 1885#endif
3475187d 1886 default:
cf495bcf
FB
1887 goto illegal_insn;
1888 }
1889 }
1890 break;
e8af50a3 1891#if !defined(CONFIG_USER_ONLY)
af7bf89b 1892 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3
FB
1893 {
1894 if (!supervisor(dc))
1895 goto priv_insn;
3475187d
FB
1896#ifdef TARGET_SPARC64
1897 switch (rd) {
1898 case 0:
1899 gen_op_saved();
1900 break;
1901 case 1:
1902 gen_op_restored();
1903 break;
1904 default:
1905 goto illegal_insn;
1906 }
1907#else
e8af50a3
FB
1908 gen_op_xor_T1_T0();
1909 gen_op_wrpsr();
9e61bde5
FB
1910 save_state(dc);
1911 gen_op_next_insn();
1912 gen_op_movl_T0_0();
1913 gen_op_exit_tb();
1914 dc->is_br = 1;
3475187d 1915#endif
e8af50a3
FB
1916 }
1917 break;
af7bf89b 1918 case 0x32: /* wrwim, V9 wrpr */
e8af50a3
FB
1919 {
1920 if (!supervisor(dc))
1921 goto priv_insn;
1922 gen_op_xor_T1_T0();
3475187d
FB
1923#ifdef TARGET_SPARC64
1924 switch (rd) {
1925 case 0: // tpc
1926 gen_op_wrtpc();
1927 break;
1928 case 1: // tnpc
1929 gen_op_wrtnpc();
1930 break;
1931 case 2: // tstate
1932 gen_op_wrtstate();
1933 break;
1934 case 3: // tt
1935 gen_op_wrtt();
1936 break;
1937 case 4: // tick
1938 gen_op_wrtick();
1939 break;
1940 case 5: // tba
83469015 1941 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
3475187d
FB
1942 break;
1943 case 6: // pstate
1944 gen_op_wrpstate();
1945 break;
1946 case 7: // tl
1947 gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
1948 break;
1949 case 8: // pil
1950 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
1951 break;
1952 case 9: // cwp
1953 gen_op_wrcwp();
1954 break;
1955 case 10: // cansave
1956 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
1957 break;
1958 case 11: // canrestore
1959 gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
1960 break;
1961 case 12: // cleanwin
1962 gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
1963 break;
1964 case 13: // otherwin
1965 gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
1966 break;
1967 case 14: // wstate
1968 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
1969 break;
1970 default:
1971 goto illegal_insn;
1972 }
1973#else
1974 gen_op_movl_env_T0(offsetof(CPUSPARCState, wim));
1975#endif
e8af50a3
FB
1976 }
1977 break;
3475187d
FB
1978#ifndef TARGET_SPARC64
1979 case 0x33: /* wrtbr, V9 unimp */
e8af50a3
FB
1980 {
1981 if (!supervisor(dc))
1982 goto priv_insn;
1983 gen_op_xor_T1_T0();
3475187d 1984 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
e8af50a3
FB
1985 }
1986 break;
1987#endif
3475187d
FB
1988#endif
1989#ifdef TARGET_SPARC64
af7bf89b 1990 case 0x2c: /* V9 movcc */
3475187d
FB
1991 {
1992 int cc = GET_FIELD_SP(insn, 11, 12);
1993 int cond = GET_FIELD_SP(insn, 14, 17);
1994 if (IS_IMM) { /* immediate */
1995 rs2 = GET_FIELD_SPs(insn, 0, 10);
1996 gen_movl_simm_T1(rs2);
1997 }
1998 else {
1999 rs2 = GET_FIELD_SP(insn, 0, 4);
2000 gen_movl_reg_T1(rs2);
2001 }
2002 gen_movl_reg_T0(rd);
2003 flush_T2(dc);
2004 if (insn & (1 << 18)) {
2005 if (cc == 0)
2006 gen_cond[0][cond]();
2007 else if (cc == 2)
2008 gen_cond[1][cond]();
2009 else
2010 goto illegal_insn;
2011 } else {
2012 gen_fcond[cc][cond]();
2013 }
2014 gen_op_mov_cc();
2015 gen_movl_T0_reg(rd);
2016 break;
2017 }
af7bf89b 2018 case 0x2d: /* V9 sdivx */
3475187d
FB
2019 gen_op_sdivx_T1_T0();
2020 gen_movl_T0_reg(rd);
2021 break;
af7bf89b 2022 case 0x2e: /* V9 popc */
3475187d
FB
2023 {
2024 if (IS_IMM) { /* immediate */
2025 rs2 = GET_FIELD_SPs(insn, 0, 12);
2026 gen_movl_simm_T1(rs2);
2027 // XXX optimize: popc(constant)
2028 }
2029 else {
2030 rs2 = GET_FIELD_SP(insn, 0, 4);
2031 gen_movl_reg_T1(rs2);
2032 }
2033 gen_op_popc();
2034 gen_movl_T0_reg(rd);
2035 }
af7bf89b 2036 case 0x2f: /* V9 movr */
3475187d
FB
2037 {
2038 int cond = GET_FIELD_SP(insn, 10, 12);
2039 rs1 = GET_FIELD(insn, 13, 17);
2040 flush_T2(dc);
2041 gen_movl_reg_T0(rs1);
2042 gen_cond_reg(cond);
2043 if (IS_IMM) { /* immediate */
2044 rs2 = GET_FIELD_SPs(insn, 0, 10);
2045 gen_movl_simm_T1(rs2);
2046 }
2047 else {
2048 rs2 = GET_FIELD_SP(insn, 0, 4);
2049 gen_movl_reg_T1(rs2);
2050 }
2051 gen_movl_reg_T0(rd);
2052 gen_op_mov_cc();
2053 gen_movl_T0_reg(rd);
2054 break;
2055 }
2056 case 0x36: /* UltraSparc shutdown, VIS */
2057 {
2058 // XXX
2059 }
2060#endif
2061 default:
e80cfcfc
FB
2062 goto illegal_insn;
2063 }
2064 }
3475187d
FB
2065#ifdef TARGET_SPARC64
2066 } else if (xop == 0x39) { /* V9 return */
3475187d
FB
2067 rs1 = GET_FIELD(insn, 13, 17);
2068 gen_movl_reg_T0(rs1);
2069 if (IS_IMM) { /* immediate */
2070 rs2 = GET_FIELDs(insn, 19, 31);
2071#if defined(OPTIM)
2072 if (rs2) {
2073#endif
2074 gen_movl_simm_T1(rs2);
2075 gen_op_add_T1_T0();
2076#if defined(OPTIM)
2077 }
2078#endif
2079 } else { /* register */
2080 rs2 = GET_FIELD(insn, 27, 31);
2081#if defined(OPTIM)
2082 if (rs2) {
2083#endif
2084 gen_movl_reg_T1(rs2);
2085 gen_op_add_T1_T0();
2086#if defined(OPTIM)
2087 }
2088#endif
2089 }
83469015 2090 gen_op_restore();
3475187d
FB
2091 gen_mov_pc_npc(dc);
2092 gen_op_movl_npc_T0();
2093 dc->npc = DYNAMIC_PC;
2094 goto jmp_insn;
2095#endif
e80cfcfc
FB
2096 } else {
2097 rs1 = GET_FIELD(insn, 13, 17);
2098 gen_movl_reg_T0(rs1);
2099 if (IS_IMM) { /* immediate */
2100 rs2 = GET_FIELDs(insn, 19, 31);
2101#if defined(OPTIM)
2102 if (rs2) {
e8af50a3 2103#endif
3475187d 2104 gen_movl_simm_T1(rs2);
e80cfcfc
FB
2105 gen_op_add_T1_T0();
2106#if defined(OPTIM)
2107 }
e8af50a3 2108#endif
e80cfcfc
FB
2109 } else { /* register */
2110 rs2 = GET_FIELD(insn, 27, 31);
2111#if defined(OPTIM)
2112 if (rs2) {
2113#endif
2114 gen_movl_reg_T1(rs2);
2115 gen_op_add_T1_T0();
2116#if defined(OPTIM)
2117 }
e8af50a3 2118#endif
cf495bcf 2119 }
e80cfcfc
FB
2120 switch (xop) {
2121 case 0x38: /* jmpl */
2122 {
e80cfcfc 2123 if (rd != 0) {
0bee699e
FB
2124 gen_op_movl_T1_im(dc->pc);
2125 gen_movl_T1_reg(rd);
e80cfcfc 2126 }
0bee699e
FB
2127 gen_mov_pc_npc(dc);
2128 gen_op_movl_npc_T0();
e80cfcfc
FB
2129 dc->npc = DYNAMIC_PC;
2130 }
2131 goto jmp_insn;
3475187d 2132#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
af7bf89b 2133 case 0x39: /* rett, V9 return */
e80cfcfc
FB
2134 {
2135 if (!supervisor(dc))
2136 goto priv_insn;
0bee699e 2137 gen_mov_pc_npc(dc);
e80cfcfc 2138 gen_op_movl_npc_T0();
0bee699e 2139 dc->npc = DYNAMIC_PC;
e80cfcfc
FB
2140 gen_op_rett();
2141 }
0bee699e 2142 goto jmp_insn;
e80cfcfc
FB
2143#endif
2144 case 0x3b: /* flush */
2145 gen_op_flush_T0();
2146 break;
2147 case 0x3c: /* save */
2148 save_state(dc);
2149 gen_op_save();
2150 gen_movl_T0_reg(rd);
2151 break;
2152 case 0x3d: /* restore */
2153 save_state(dc);
2154 gen_op_restore();
2155 gen_movl_T0_reg(rd);
2156 break;
3475187d 2157#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
af7bf89b 2158 case 0x3e: /* V9 done/retry */
3475187d
FB
2159 {
2160 switch (rd) {
2161 case 0:
2162 if (!supervisor(dc))
2163 goto priv_insn;
83469015
FB
2164 dc->npc = DYNAMIC_PC;
2165 dc->pc = DYNAMIC_PC;
3475187d 2166 gen_op_done();
83469015 2167 goto jmp_insn;
3475187d
FB
2168 case 1:
2169 if (!supervisor(dc))
2170 goto priv_insn;
83469015
FB
2171 dc->npc = DYNAMIC_PC;
2172 dc->pc = DYNAMIC_PC;
3475187d 2173 gen_op_retry();
83469015 2174 goto jmp_insn;
3475187d
FB
2175 default:
2176 goto illegal_insn;
2177 }
2178 }
2179 break;
2180#endif
2181 default:
e80cfcfc
FB
2182 goto illegal_insn;
2183 }
cf495bcf
FB
2184 }
2185 break;
2186 }
af7bf89b 2187 break;
cf495bcf
FB
2188 case 3: /* load/store instructions */
2189 {
2190 unsigned int xop = GET_FIELD(insn, 7, 12);
2191 rs1 = GET_FIELD(insn, 13, 17);
2192 gen_movl_reg_T0(rs1);
2193 if (IS_IMM) { /* immediate */
2194 rs2 = GET_FIELDs(insn, 19, 31);
e80cfcfc 2195#if defined(OPTIM)
e8af50a3 2196 if (rs2 != 0) {
e80cfcfc 2197#endif
3475187d 2198 gen_movl_simm_T1(rs2);
e8af50a3 2199 gen_op_add_T1_T0();
e80cfcfc 2200#if defined(OPTIM)
e8af50a3 2201 }
e80cfcfc 2202#endif
cf495bcf
FB
2203 } else { /* register */
2204 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc
FB
2205#if defined(OPTIM)
2206 if (rs2 != 0) {
2207#endif
2208 gen_movl_reg_T1(rs2);
2209 gen_op_add_T1_T0();
2210#if defined(OPTIM)
2211 }
2212#endif
cf495bcf 2213 }
3475187d
FB
2214 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || \
2215 (xop > 0x17 && xop < 0x1d ) || \
2216 (xop > 0x2c && xop < 0x33) || xop == 0x1f) {
cf495bcf
FB
2217 switch (xop) {
2218 case 0x0: /* load word */
e8af50a3 2219 gen_op_ldst(ld);
cf495bcf
FB
2220 break;
2221 case 0x1: /* load unsigned byte */
e8af50a3 2222 gen_op_ldst(ldub);
cf495bcf
FB
2223 break;
2224 case 0x2: /* load unsigned halfword */
e8af50a3 2225 gen_op_ldst(lduh);
cf495bcf
FB
2226 break;
2227 case 0x3: /* load double word */
e8af50a3 2228 gen_op_ldst(ldd);
cf495bcf
FB
2229 gen_movl_T0_reg(rd + 1);
2230 break;
2231 case 0x9: /* load signed byte */
e8af50a3 2232 gen_op_ldst(ldsb);
cf495bcf
FB
2233 break;
2234 case 0xa: /* load signed halfword */
e8af50a3 2235 gen_op_ldst(ldsh);
cf495bcf
FB
2236 break;
2237 case 0xd: /* ldstub -- XXX: should be atomically */
e8af50a3 2238 gen_op_ldst(ldstub);
cf495bcf
FB
2239 break;
2240 case 0x0f: /* swap register with memory. Also atomically */
e80cfcfc 2241 gen_movl_reg_T1(rd);
e8af50a3
FB
2242 gen_op_ldst(swap);
2243 break;
3475187d 2244#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
e8af50a3 2245 case 0x10: /* load word alternate */
3475187d 2246#ifndef TARGET_SPARC64
e8af50a3
FB
2247 if (!supervisor(dc))
2248 goto priv_insn;
3475187d 2249#endif
e8af50a3
FB
2250 gen_op_lda(insn, 1, 4, 0);
2251 break;
2252 case 0x11: /* load unsigned byte alternate */
3475187d 2253#ifndef TARGET_SPARC64
e8af50a3
FB
2254 if (!supervisor(dc))
2255 goto priv_insn;
3475187d 2256#endif
e8af50a3
FB
2257 gen_op_lduba(insn, 1, 1, 0);
2258 break;
2259 case 0x12: /* load unsigned halfword alternate */
3475187d 2260#ifndef TARGET_SPARC64
e8af50a3
FB
2261 if (!supervisor(dc))
2262 goto priv_insn;
3475187d 2263#endif
e8af50a3
FB
2264 gen_op_lduha(insn, 1, 2, 0);
2265 break;
2266 case 0x13: /* load double word alternate */
3475187d 2267#ifndef TARGET_SPARC64
e8af50a3
FB
2268 if (!supervisor(dc))
2269 goto priv_insn;
3475187d 2270#endif
e8af50a3
FB
2271 gen_op_ldda(insn, 1, 8, 0);
2272 gen_movl_T0_reg(rd + 1);
2273 break;
2274 case 0x19: /* load signed byte alternate */
3475187d 2275#ifndef TARGET_SPARC64
e8af50a3
FB
2276 if (!supervisor(dc))
2277 goto priv_insn;
3475187d 2278#endif
e8af50a3
FB
2279 gen_op_ldsba(insn, 1, 1, 1);
2280 break;
2281 case 0x1a: /* load signed halfword alternate */
3475187d 2282#ifndef TARGET_SPARC64
e8af50a3
FB
2283 if (!supervisor(dc))
2284 goto priv_insn;
3475187d 2285#endif
e8af50a3
FB
2286 gen_op_ldsha(insn, 1, 2 ,1);
2287 break;
2288 case 0x1d: /* ldstuba -- XXX: should be atomically */
3475187d 2289#ifndef TARGET_SPARC64
e8af50a3
FB
2290 if (!supervisor(dc))
2291 goto priv_insn;
3475187d 2292#endif
e8af50a3
FB
2293 gen_op_ldstuba(insn, 1, 1, 0);
2294 break;
2295 case 0x1f: /* swap reg with alt. memory. Also atomically */
3475187d 2296#ifndef TARGET_SPARC64
e8af50a3
FB
2297 if (!supervisor(dc))
2298 goto priv_insn;
3475187d 2299#endif
e80cfcfc 2300 gen_movl_reg_T1(rd);
e8af50a3 2301 gen_op_swapa(insn, 1, 4, 0);
cf495bcf 2302 break;
3475187d
FB
2303
2304#ifndef TARGET_SPARC64
0fa85d43
FB
2305 /* avoid warnings */
2306 (void) &gen_op_stfa;
2307 (void) &gen_op_stdfa;
2308 (void) &gen_op_ldfa;
2309 (void) &gen_op_lddfa;
3475187d
FB
2310#else
2311#if !defined(CONFIG_USER_ONLY)
2312 (void) &gen_op_cas;
2313 (void) &gen_op_casx;
e80cfcfc 2314#endif
3475187d
FB
2315#endif
2316#endif
2317#ifdef TARGET_SPARC64
af7bf89b 2318 case 0x08: /* V9 ldsw */
3475187d
FB
2319 gen_op_ldst(ldsw);
2320 break;
af7bf89b 2321 case 0x0b: /* V9 ldx */
3475187d
FB
2322 gen_op_ldst(ldx);
2323 break;
af7bf89b 2324 case 0x18: /* V9 ldswa */
3475187d
FB
2325 gen_op_ldswa(insn, 1, 4, 1);
2326 break;
af7bf89b 2327 case 0x1b: /* V9 ldxa */
3475187d
FB
2328 gen_op_ldxa(insn, 1, 8, 0);
2329 break;
2330 case 0x2d: /* V9 prefetch, no effect */
2331 goto skip_move;
af7bf89b 2332 case 0x30: /* V9 ldfa */
3475187d
FB
2333 gen_op_ldfa(insn, 1, 8, 0); // XXX
2334 break;
af7bf89b 2335 case 0x33: /* V9 lddfa */
3475187d 2336 gen_op_lddfa(insn, 1, 8, 0); // XXX
af7bf89b 2337
3475187d
FB
2338 break;
2339 case 0x3d: /* V9 prefetcha, no effect */
2340 goto skip_move;
af7bf89b 2341 case 0x32: /* V9 ldqfa */
3475187d
FB
2342 goto nfpu_insn;
2343#endif
2344 default:
e80cfcfc 2345 goto illegal_insn;
7a3f1944 2346 }
cf495bcf 2347 gen_movl_T1_reg(rd);
3475187d
FB
2348#ifdef TARGET_SPARC64
2349 skip_move: ;
2350#endif
e8af50a3 2351 } else if (xop >= 0x20 && xop < 0x24) {
3475187d 2352#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
55e4f664 2353 save_state(dc);
e80cfcfc
FB
2354 gen_op_trap_ifnofpu();
2355#endif
e8af50a3
FB
2356 switch (xop) {
2357 case 0x20: /* load fpreg */
2358 gen_op_ldst(ldf);
2359 gen_op_store_FT0_fpr(rd);
2360 break;
2361 case 0x21: /* load fsr */
9e61bde5 2362 gen_op_ldst(ldf);
e8af50a3
FB
2363 gen_op_ldfsr();
2364 break;
af7bf89b
FB
2365 case 0x22: /* load quad fpreg */
2366 goto nfpu_insn;
e8af50a3
FB
2367 case 0x23: /* load double fpreg */
2368 gen_op_ldst(lddf);
3475187d 2369 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 2370 break;
e80cfcfc
FB
2371 default:
2372 goto illegal_insn;
e8af50a3 2373 }
3475187d
FB
2374 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
2375 xop == 0xe || xop == 0x1e) {
cf495bcf
FB
2376 gen_movl_reg_T1(rd);
2377 switch (xop) {
2378 case 0x4:
e8af50a3 2379 gen_op_ldst(st);
cf495bcf
FB
2380 break;
2381 case 0x5:
e8af50a3 2382 gen_op_ldst(stb);
cf495bcf
FB
2383 break;
2384 case 0x6:
e8af50a3 2385 gen_op_ldst(sth);
cf495bcf
FB
2386 break;
2387 case 0x7:
72cbca10 2388 flush_T2(dc);
cf495bcf 2389 gen_movl_reg_T2(rd + 1);
e8af50a3
FB
2390 gen_op_ldst(std);
2391 break;
3475187d 2392#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
e8af50a3 2393 case 0x14:
3475187d 2394#ifndef TARGET_SPARC64
e8af50a3
FB
2395 if (!supervisor(dc))
2396 goto priv_insn;
3475187d 2397#endif
e8af50a3 2398 gen_op_sta(insn, 0, 4, 0);
d39c0b99 2399 break;
e8af50a3 2400 case 0x15:
3475187d 2401#ifndef TARGET_SPARC64
e8af50a3
FB
2402 if (!supervisor(dc))
2403 goto priv_insn;
3475187d 2404#endif
e8af50a3 2405 gen_op_stba(insn, 0, 1, 0);
d39c0b99 2406 break;
e8af50a3 2407 case 0x16:
3475187d 2408#ifndef TARGET_SPARC64
e8af50a3
FB
2409 if (!supervisor(dc))
2410 goto priv_insn;
3475187d 2411#endif
e8af50a3 2412 gen_op_stha(insn, 0, 2, 0);
d39c0b99 2413 break;
e8af50a3 2414 case 0x17:
3475187d 2415#ifndef TARGET_SPARC64
e8af50a3
FB
2416 if (!supervisor(dc))
2417 goto priv_insn;
3475187d 2418#endif
e8af50a3
FB
2419 flush_T2(dc);
2420 gen_movl_reg_T2(rd + 1);
2421 gen_op_stda(insn, 0, 8, 0);
d39c0b99 2422 break;
e80cfcfc 2423#endif
3475187d 2424#ifdef TARGET_SPARC64
af7bf89b 2425 case 0x0e: /* V9 stx */
3475187d
FB
2426 gen_op_ldst(stx);
2427 break;
af7bf89b 2428 case 0x1e: /* V9 stxa */
3475187d
FB
2429 gen_op_stxa(insn, 0, 8, 0); // XXX
2430 break;
2431#endif
2432 default:
e80cfcfc 2433 goto illegal_insn;
7a3f1944 2434 }
e8af50a3 2435 } else if (xop > 0x23 && xop < 0x28) {
e80cfcfc
FB
2436#if !defined(CONFIG_USER_ONLY)
2437 gen_op_trap_ifnofpu();
2438#endif
e8af50a3
FB
2439 switch (xop) {
2440 case 0x24:
2441 gen_op_load_fpr_FT0(rd);
2442 gen_op_ldst(stf);
2443 break;
af7bf89b 2444 case 0x25: /* stfsr, V9 stxfsr */
e8af50a3 2445 gen_op_stfsr();
9e61bde5 2446 gen_op_ldst(stf);
e8af50a3 2447 break;
af7bf89b
FB
2448 case 0x26: /* stdfq */
2449 goto nfpu_insn;
e8af50a3 2450 case 0x27:
3475187d 2451 gen_op_load_fpr_DT0(DFPREG(rd));
e8af50a3
FB
2452 gen_op_ldst(stdf);
2453 break;
e80cfcfc 2454 default:
3475187d
FB
2455 goto illegal_insn;
2456 }
2457 } else if (xop > 0x33 && xop < 0x3f) {
2458#ifdef TARGET_SPARC64
2459 switch (xop) {
af7bf89b 2460 case 0x34: /* V9 stfa */
3475187d
FB
2461 gen_op_stfa(insn, 0, 0, 0); // XXX
2462 break;
af7bf89b 2463 case 0x37: /* V9 stdfa */
3475187d
FB
2464 gen_op_stdfa(insn, 0, 0, 0); // XXX
2465 break;
af7bf89b 2466 case 0x3c: /* V9 casa */
3475187d
FB
2467 gen_op_casa(insn, 0, 4, 0); // XXX
2468 break;
af7bf89b 2469 case 0x3e: /* V9 casxa */
3475187d
FB
2470 gen_op_casxa(insn, 0, 8, 0); // XXX
2471 break;
af7bf89b 2472 case 0x36: /* V9 stqfa */
3475187d
FB
2473 goto nfpu_insn;
2474 default:
e80cfcfc 2475 goto illegal_insn;
e8af50a3 2476 }
3475187d 2477#else
e80cfcfc 2478 goto illegal_insn;
3475187d 2479#endif
e8af50a3 2480 }
e80cfcfc
FB
2481 else
2482 goto illegal_insn;
7a3f1944 2483 }
af7bf89b 2484 break;
cf495bcf
FB
2485 }
2486 /* default case for non jump instructions */
72cbca10
FB
2487 if (dc->npc == DYNAMIC_PC) {
2488 dc->pc = DYNAMIC_PC;
2489 gen_op_next_insn();
2490 } else if (dc->npc == JUMP_PC) {
2491 /* we can do a static jump */
83469015 2492 gen_branch2(dc, (long)dc->tb, dc->jump_pc[0], dc->jump_pc[1]);
72cbca10
FB
2493 dc->is_br = 1;
2494 } else {
cf495bcf
FB
2495 dc->pc = dc->npc;
2496 dc->npc = dc->npc + 4;
cf495bcf 2497 }
e80cfcfc 2498 jmp_insn:
cf495bcf
FB
2499 return;
2500 illegal_insn:
72cbca10 2501 save_state(dc);
cf495bcf
FB
2502 gen_op_exception(TT_ILL_INSN);
2503 dc->is_br = 1;
e8af50a3 2504 return;
e80cfcfc 2505#if !defined(CONFIG_USER_ONLY)
e8af50a3
FB
2506 priv_insn:
2507 save_state(dc);
2508 gen_op_exception(TT_PRIV_INSN);
2509 dc->is_br = 1;
e80cfcfc
FB
2510 return;
2511#endif
2512 nfpu_insn:
2513 save_state(dc);
2514 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
2515 dc->is_br = 1;
7a3f1944
FB
2516}
2517
cf495bcf 2518static inline int gen_intermediate_code_internal(TranslationBlock * tb,
e8af50a3 2519 int spc, CPUSPARCState *env)
7a3f1944 2520{
72cbca10 2521 target_ulong pc_start, last_pc;
cf495bcf
FB
2522 uint16_t *gen_opc_end;
2523 DisasContext dc1, *dc = &dc1;
e8af50a3 2524 int j, lj = -1;
cf495bcf
FB
2525
2526 memset(dc, 0, sizeof(DisasContext));
cf495bcf 2527 dc->tb = tb;
72cbca10 2528 pc_start = tb->pc;
cf495bcf 2529 dc->pc = pc_start;
e80cfcfc 2530 last_pc = dc->pc;
72cbca10 2531 dc->npc = (target_ulong) tb->cs_base;
e8af50a3
FB
2532#if defined(CONFIG_USER_ONLY)
2533 dc->mem_idx = 0;
2534#else
2535 dc->mem_idx = ((env->psrs) != 0);
2536#endif
cf495bcf
FB
2537 gen_opc_ptr = gen_opc_buf;
2538 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2539 gen_opparam_ptr = gen_opparam_buf;
83469015 2540 nb_gen_labels = 0;
cf495bcf
FB
2541
2542 do {
e8af50a3
FB
2543 if (env->nb_breakpoints > 0) {
2544 for(j = 0; j < env->nb_breakpoints; j++) {
2545 if (env->breakpoints[j] == dc->pc) {
e80cfcfc
FB
2546 if (dc->pc != pc_start)
2547 save_state(dc);
2548 gen_op_debug();
2549 gen_op_movl_T0_0();
2550 gen_op_exit_tb();
2551 dc->is_br = 1;
2552 goto exit_gen_loop;
e8af50a3
FB
2553 }
2554 }
2555 }
2556 if (spc) {
2557 if (loglevel > 0)
2558 fprintf(logfile, "Search PC...\n");
2559 j = gen_opc_ptr - gen_opc_buf;
2560 if (lj < j) {
2561 lj++;
2562 while (lj < j)
2563 gen_opc_instr_start[lj++] = 0;
2564 gen_opc_pc[lj] = dc->pc;
2565 gen_opc_npc[lj] = dc->npc;
2566 gen_opc_instr_start[lj] = 1;
2567 }
2568 }
cf495bcf
FB
2569 last_pc = dc->pc;
2570 disas_sparc_insn(dc);
3475187d 2571
cf495bcf
FB
2572 if (dc->is_br)
2573 break;
2574 /* if the next PC is different, we abort now */
2575 if (dc->pc != (last_pc + 4))
2576 break;
d39c0b99
FB
2577 /* if we reach a page boundary, we stop generation so that the
2578 PC of a TT_TFAULT exception is always in the right page */
2579 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
2580 break;
e80cfcfc
FB
2581 /* if single step mode, we generate only one instruction and
2582 generate an exception */
2583 if (env->singlestep_enabled) {
3475187d 2584 gen_jmp_im(dc->pc);
e80cfcfc
FB
2585 gen_op_movl_T0_0();
2586 gen_op_exit_tb();
2587 break;
2588 }
cf495bcf
FB
2589 } while ((gen_opc_ptr < gen_opc_end) &&
2590 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
e80cfcfc
FB
2591
2592 exit_gen_loop:
72cbca10
FB
2593 if (!dc->is_br) {
2594 if (dc->pc != DYNAMIC_PC &&
2595 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
2596 /* static PC and NPC: we can use direct chaining */
83469015 2597 gen_branch(dc, (long)tb, dc->pc, dc->npc);
72cbca10
FB
2598 } else {
2599 if (dc->pc != DYNAMIC_PC)
3475187d 2600 gen_jmp_im(dc->pc);
72cbca10
FB
2601 save_npc(dc);
2602 gen_op_movl_T0_0();
2603 gen_op_exit_tb();
2604 }
2605 }
cf495bcf 2606 *gen_opc_ptr = INDEX_op_end;
e8af50a3
FB
2607 if (spc) {
2608 j = gen_opc_ptr - gen_opc_buf;
2609 lj++;
2610 while (lj <= j)
2611 gen_opc_instr_start[lj++] = 0;
2612 tb->size = 0;
2613#if 0
2614 if (loglevel > 0) {
2615 page_dump(logfile);
2616 }
2617#endif
c3278b7b
FB
2618 gen_opc_jump_pc[0] = dc->jump_pc[0];
2619 gen_opc_jump_pc[1] = dc->jump_pc[1];
e8af50a3 2620 } else {
e80cfcfc 2621 tb->size = last_pc + 4 - pc_start;
e8af50a3 2622 }
7a3f1944 2623#ifdef DEBUG_DISAS
e19e89a5 2624 if (loglevel & CPU_LOG_TB_IN_ASM) {
cf495bcf 2625 fprintf(logfile, "--------------\n");
0fa85d43
FB
2626 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2627 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
cf495bcf 2628 fprintf(logfile, "\n");
e19e89a5
FB
2629 if (loglevel & CPU_LOG_TB_OP) {
2630 fprintf(logfile, "OP:\n");
2631 dump_ops(gen_opc_buf, gen_opparam_buf);
2632 fprintf(logfile, "\n");
2633 }
cf495bcf 2634 }
7a3f1944 2635#endif
cf495bcf 2636 return 0;
7a3f1944
FB
2637}
2638
cf495bcf 2639int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 2640{
e8af50a3 2641 return gen_intermediate_code_internal(tb, 0, env);
7a3f1944
FB
2642}
2643
cf495bcf 2644int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 2645{
e8af50a3 2646 return gen_intermediate_code_internal(tb, 1, env);
7a3f1944
FB
2647}
2648
e80cfcfc 2649extern int ram_size;
cf495bcf 2650
e80cfcfc
FB
2651void cpu_reset(CPUSPARCState *env)
2652{
cf495bcf 2653 memset(env, 0, sizeof(*env));
bb05683b 2654 tlb_flush(env, 1);
cf495bcf
FB
2655 env->cwp = 0;
2656 env->wim = 1;
2657 env->regwptr = env->regbase + (env->cwp * 16);
e8af50a3 2658#if defined(CONFIG_USER_ONLY)
cf495bcf 2659 env->user_mode_only = 1;
e8af50a3 2660#else
e8af50a3 2661 env->psrs = 1;
0bee699e 2662 env->psrps = 1;
e80cfcfc 2663 env->gregs[1] = ram_size;
3475187d 2664#ifdef TARGET_SPARC64
83469015 2665 env->pstate = PS_PRIV;
3475187d 2666 env->version = GET_VER(env);
83469015 2667 env->pc = 0x1fff0000000ULL;
3475187d
FB
2668#else
2669 env->mmuregs[0] = (0x04 << 24); /* Impl 0, ver 4, MMU disabled */
83469015 2670 env->pc = 0xffd00000;
3475187d 2671#endif
83469015 2672 env->npc = env->pc + 4;
e8af50a3 2673#endif
e80cfcfc
FB
2674}
2675
2676CPUSPARCState *cpu_sparc_init(void)
2677{
2678 CPUSPARCState *env;
2679
c68ea704
FB
2680 env = qemu_mallocz(sizeof(CPUSPARCState));
2681 if (!env)
2682 return NULL;
2683 cpu_exec_init(env);
e80cfcfc 2684 cpu_reset(env);
cf495bcf 2685 return (env);
7a3f1944
FB
2686}
2687
2688#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
2689
7fe48483
FB
2690void cpu_dump_state(CPUState *env, FILE *f,
2691 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2692 int flags)
7a3f1944 2693{
cf495bcf
FB
2694 int i, x;
2695
af7bf89b 2696 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
7fe48483 2697 cpu_fprintf(f, "General Registers:\n");
cf495bcf 2698 for (i = 0; i < 4; i++)
af7bf89b 2699 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 2700 cpu_fprintf(f, "\n");
cf495bcf 2701 for (; i < 8; i++)
af7bf89b 2702 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 2703 cpu_fprintf(f, "\nCurrent Register Window:\n");
cf495bcf
FB
2704 for (x = 0; x < 3; x++) {
2705 for (i = 0; i < 4; i++)
af7bf89b 2706 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
cf495bcf
FB
2707 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
2708 env->regwptr[i + x * 8]);
7fe48483 2709 cpu_fprintf(f, "\n");
cf495bcf 2710 for (; i < 8; i++)
af7bf89b 2711 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
cf495bcf
FB
2712 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
2713 env->regwptr[i + x * 8]);
7fe48483 2714 cpu_fprintf(f, "\n");
cf495bcf 2715 }
7fe48483 2716 cpu_fprintf(f, "\nFloating Point Registers:\n");
e8af50a3
FB
2717 for (i = 0; i < 32; i++) {
2718 if ((i & 3) == 0)
7fe48483
FB
2719 cpu_fprintf(f, "%%f%02d:", i);
2720 cpu_fprintf(f, " %016lf", env->fpr[i]);
e8af50a3 2721 if ((i & 3) == 3)
7fe48483 2722 cpu_fprintf(f, "\n");
e8af50a3 2723 }
7fe48483 2724 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
cf495bcf
FB
2725 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
2726 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
e8af50a3
FB
2727 env->psrs?'S':'-', env->psrps?'P':'-',
2728 env->psret?'E':'-', env->wim);
3475187d 2729 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
7a3f1944 2730}
edfcbd99 2731
e80cfcfc 2732#if defined(CONFIG_USER_ONLY)
d785e6be 2733target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
edfcbd99
FB
2734{
2735 return addr;
2736}
658138bc 2737
e80cfcfc 2738#else
af7bf89b
FB
2739extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
2740 int *access_index, target_ulong address, int rw,
0fa85d43
FB
2741 int is_user);
2742
d785e6be 2743target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
e80cfcfc 2744{
af7bf89b 2745 target_phys_addr_t phys_addr;
e80cfcfc
FB
2746 int prot, access_index;
2747
2748 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
2749 return -1;
2750 return phys_addr;
2751}
2752#endif
2753
658138bc
FB
2754void helper_flush(target_ulong addr)
2755{
2756 addr &= ~7;
2757 tb_invalidate_page_range(addr, addr + 8);
2758}