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audio capture fixes (malc)
[qemu.git] / target-sparc / translate.c
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7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
7a3f1944
FB		 23 TODO-list:
24
3475187d 25 Rest of V9 instructions, VIS instructions
bd497938 26 NPC/PC static optimisations (use JUMP_TB when possible)
7a3f1944 27 Optimize synthetic instructions
3475187d
FB		 28 Optional alignment check
29 128-bit float
30 Tagged add/sub
bd497938 31*/
7a3f1944
FB		 32
33#include <stdarg.h>
34#include <stdlib.h>
35#include <stdio.h>
36#include <string.h>
37#include <inttypes.h>
38
39#include "cpu.h"
40#include "exec-all.h"
41#include "disas.h"
42
43#define DEBUG_DISAS
44
72cbca10
FB		 45#define DYNAMIC_PC 1 /* dynamic pc value */
46#define JUMP_PC 2 /* dynamic pc value which takes only two values
47 according to jump_pc[T2] */
48
7a3f1944 49typedef struct DisasContext {
72cbca10
FB		 50 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
51 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
52 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 53 int is_br;
e8af50a3 54 int mem_idx;
a80dde08 55 int fpu_enabled;
cf495bcf 56 struct TranslationBlock *tb;
7a3f1944
FB		 57} DisasContext;
58
59static uint16_t *gen_opc_ptr;
60static uint32_t *gen_opparam_ptr;
61extern FILE *logfile;
62extern int loglevel;
63
64enum {
65#define DEF(s,n,copy_size) INDEX_op_ ## s,
66#include "opc.h"
67#undef DEF
cf495bcf 68 NB_OPS
7a3f1944
FB		 69};
70
71#include "gen-op.h"
72
3475187d 73// This function uses non-native bit order
7a3f1944
FB		 74#define GET_FIELD(X, FROM, TO) \
75 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
76
3475187d
FB		 77// This function uses the order in the manuals, i.e. bit 0 is 2^0
78#define GET_FIELD_SP(X, FROM, TO) \
79 GET_FIELD(X, 31 - (TO), 31 - (FROM))
80
81#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
82#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), 32 - ((b) - (a) + 1))
83
84#ifdef TARGET_SPARC64
85#define DFPREG(r) (((r & 1) << 6) | (r & 0x1e))
86#else
87#define DFPREG(r) (r)
88#endif
89
83469015
FB		 90#ifdef USE_DIRECT_JUMP
91#define TBPARAM(x)
92#else
93#define TBPARAM(x) (long)(x)
94#endif
95
3475187d
FB		 96static int sign_extend(int x, int len)
97{
98 len = 32 - len;
99 return (x << len) >> len;
100}
101
7a3f1944
FB		 102#define IS_IMM (insn & (1<<13))
103
cf495bcf 104static void disas_sparc_insn(DisasContext * dc);
7a3f1944 105
7a3f1944 106static GenOpFunc *gen_op_movl_TN_reg[2][32] = {
cf495bcf
FB		 107 {
108 gen_op_movl_g0_T0,
109 gen_op_movl_g1_T0,
110 gen_op_movl_g2_T0,
111 gen_op_movl_g3_T0,
112 gen_op_movl_g4_T0,
113 gen_op_movl_g5_T0,
114 gen_op_movl_g6_T0,
115 gen_op_movl_g7_T0,
116 gen_op_movl_o0_T0,
117 gen_op_movl_o1_T0,
118 gen_op_movl_o2_T0,
119 gen_op_movl_o3_T0,
120 gen_op_movl_o4_T0,
121 gen_op_movl_o5_T0,
122 gen_op_movl_o6_T0,
123 gen_op_movl_o7_T0,
124 gen_op_movl_l0_T0,
125 gen_op_movl_l1_T0,
126 gen_op_movl_l2_T0,
127 gen_op_movl_l3_T0,
128 gen_op_movl_l4_T0,
129 gen_op_movl_l5_T0,
130 gen_op_movl_l6_T0,
131 gen_op_movl_l7_T0,
132 gen_op_movl_i0_T0,
133 gen_op_movl_i1_T0,
134 gen_op_movl_i2_T0,
135 gen_op_movl_i3_T0,
136 gen_op_movl_i4_T0,
137 gen_op_movl_i5_T0,
138 gen_op_movl_i6_T0,
139 gen_op_movl_i7_T0,
140 },
141 {
142 gen_op_movl_g0_T1,
143 gen_op_movl_g1_T1,
144 gen_op_movl_g2_T1,
145 gen_op_movl_g3_T1,
146 gen_op_movl_g4_T1,
147 gen_op_movl_g5_T1,
148 gen_op_movl_g6_T1,
149 gen_op_movl_g7_T1,
150 gen_op_movl_o0_T1,
151 gen_op_movl_o1_T1,
152 gen_op_movl_o2_T1,
153 gen_op_movl_o3_T1,
154 gen_op_movl_o4_T1,
155 gen_op_movl_o5_T1,
156 gen_op_movl_o6_T1,
157 gen_op_movl_o7_T1,
158 gen_op_movl_l0_T1,
159 gen_op_movl_l1_T1,
160 gen_op_movl_l2_T1,
161 gen_op_movl_l3_T1,
162 gen_op_movl_l4_T1,
163 gen_op_movl_l5_T1,
164 gen_op_movl_l6_T1,
165 gen_op_movl_l7_T1,
166 gen_op_movl_i0_T1,
167 gen_op_movl_i1_T1,
168 gen_op_movl_i2_T1,
169 gen_op_movl_i3_T1,
170 gen_op_movl_i4_T1,
171 gen_op_movl_i5_T1,
172 gen_op_movl_i6_T1,
173 gen_op_movl_i7_T1,
174 }
7a3f1944
FB		 175};
176
177static GenOpFunc *gen_op_movl_reg_TN[3][32] = {
cf495bcf
FB		 178 {
179 gen_op_movl_T0_g0,
180 gen_op_movl_T0_g1,
181 gen_op_movl_T0_g2,
182 gen_op_movl_T0_g3,
183 gen_op_movl_T0_g4,
184 gen_op_movl_T0_g5,
185 gen_op_movl_T0_g6,
186 gen_op_movl_T0_g7,
187 gen_op_movl_T0_o0,
188 gen_op_movl_T0_o1,
189 gen_op_movl_T0_o2,
190 gen_op_movl_T0_o3,
191 gen_op_movl_T0_o4,
192 gen_op_movl_T0_o5,
193 gen_op_movl_T0_o6,
194 gen_op_movl_T0_o7,
195 gen_op_movl_T0_l0,
196 gen_op_movl_T0_l1,
197 gen_op_movl_T0_l2,
198 gen_op_movl_T0_l3,
199 gen_op_movl_T0_l4,
200 gen_op_movl_T0_l5,
201 gen_op_movl_T0_l6,
202 gen_op_movl_T0_l7,
203 gen_op_movl_T0_i0,
204 gen_op_movl_T0_i1,
205 gen_op_movl_T0_i2,
206 gen_op_movl_T0_i3,
207 gen_op_movl_T0_i4,
208 gen_op_movl_T0_i5,
209 gen_op_movl_T0_i6,
210 gen_op_movl_T0_i7,
211 },
212 {
213 gen_op_movl_T1_g0,
214 gen_op_movl_T1_g1,
215 gen_op_movl_T1_g2,
216 gen_op_movl_T1_g3,
217 gen_op_movl_T1_g4,
218 gen_op_movl_T1_g5,
219 gen_op_movl_T1_g6,
220 gen_op_movl_T1_g7,
221 gen_op_movl_T1_o0,
222 gen_op_movl_T1_o1,
223 gen_op_movl_T1_o2,
224 gen_op_movl_T1_o3,
225 gen_op_movl_T1_o4,
226 gen_op_movl_T1_o5,
227 gen_op_movl_T1_o6,
228 gen_op_movl_T1_o7,
229 gen_op_movl_T1_l0,
230 gen_op_movl_T1_l1,
231 gen_op_movl_T1_l2,
232 gen_op_movl_T1_l3,
233 gen_op_movl_T1_l4,
234 gen_op_movl_T1_l5,
235 gen_op_movl_T1_l6,
236 gen_op_movl_T1_l7,
237 gen_op_movl_T1_i0,
238 gen_op_movl_T1_i1,
239 gen_op_movl_T1_i2,
240 gen_op_movl_T1_i3,
241 gen_op_movl_T1_i4,
242 gen_op_movl_T1_i5,
243 gen_op_movl_T1_i6,
244 gen_op_movl_T1_i7,
245 },
246 {
247 gen_op_movl_T2_g0,
248 gen_op_movl_T2_g1,
249 gen_op_movl_T2_g2,
250 gen_op_movl_T2_g3,
251 gen_op_movl_T2_g4,
252 gen_op_movl_T2_g5,
253 gen_op_movl_T2_g6,
254 gen_op_movl_T2_g7,
255 gen_op_movl_T2_o0,
256 gen_op_movl_T2_o1,
257 gen_op_movl_T2_o2,
258 gen_op_movl_T2_o3,
259 gen_op_movl_T2_o4,
260 gen_op_movl_T2_o5,
261 gen_op_movl_T2_o6,
262 gen_op_movl_T2_o7,
263 gen_op_movl_T2_l0,
264 gen_op_movl_T2_l1,
265 gen_op_movl_T2_l2,
266 gen_op_movl_T2_l3,
267 gen_op_movl_T2_l4,
268 gen_op_movl_T2_l5,
269 gen_op_movl_T2_l6,
270 gen_op_movl_T2_l7,
271 gen_op_movl_T2_i0,
272 gen_op_movl_T2_i1,
273 gen_op_movl_T2_i2,
274 gen_op_movl_T2_i3,
275 gen_op_movl_T2_i4,
276 gen_op_movl_T2_i5,
277 gen_op_movl_T2_i6,
278 gen_op_movl_T2_i7,
279 }
7a3f1944
FB		 280};
281
282static GenOpFunc1 *gen_op_movl_TN_im[3] = {
cf495bcf
FB		 283 gen_op_movl_T0_im,
284 gen_op_movl_T1_im,
285 gen_op_movl_T2_im
7a3f1944
FB		 286};
287
3475187d
FB		 288// Sign extending version
289static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {
290 gen_op_movl_T0_sim,
291 gen_op_movl_T1_sim,
292 gen_op_movl_T2_sim
293};
294
295#ifdef TARGET_SPARC64
296#define GEN32(func, NAME) \
297static GenOpFunc *NAME ## _table [64] = { \
298NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
299NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
300NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
301NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
302NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
303NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
304NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
305NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
306NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
307NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
308NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
309NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
310}; \
311static inline void func(int n) \
312{ \
313 NAME ## _table[n](); \
314}
315#else
e8af50a3
FB		 316#define GEN32(func, NAME) \
317static GenOpFunc *NAME ## _table [32] = { \
318NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
319NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
320NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
321NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
322NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
323NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
324NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
325NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
326}; \
327static inline void func(int n) \
328{ \
329 NAME ## _table[n](); \
330}
3475187d 331#endif
e8af50a3
FB		 332
333/* floating point registers moves */
334GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
335GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
e8af50a3
FB		 336GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
337GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
e8af50a3
FB		 338
339GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
340GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
e8af50a3
FB		 341GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
342GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
e8af50a3 343
3475187d
FB		 344#ifdef TARGET_SPARC64
345// 'a' versions allowed to user depending on asi
346#if defined(CONFIG_USER_ONLY)
347#define supervisor(dc) 0
348#define gen_op_ldst(name) gen_op_##name##_raw()
349#define OP_LD_TABLE(width) \
350 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
351 { \
352 int asi, offset; \
353 \
354 if (IS_IMM) { \
355 offset = GET_FIELD(insn, 25, 31); \
356 if (is_ld) \
357 gen_op_ld_asi_reg(offset, size, sign); \
358 else \
359 gen_op_st_asi_reg(offset, size, sign); \
360 return; \
361 } \
362 asi = GET_FIELD(insn, 19, 26); \
363 switch (asi) { \
364 case 0x80: /* Primary address space */ \
365 gen_op_##width##_raw(); \
366 break; \
367 default: \
368 break; \
369 } \
370 }
371
372#else
373#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
374#define OP_LD_TABLE(width) \
375 static GenOpFunc *gen_op_##width[] = { \
376 &gen_op_##width##_user, \
377 &gen_op_##width##_kernel, \
378 }; \
379 \
380 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
381 { \
382 int asi, offset; \
383 \
384 if (IS_IMM) { \
385 offset = GET_FIELD(insn, 25, 31); \
386 if (is_ld) \
387 gen_op_ld_asi_reg(offset, size, sign); \
388 else \
389 gen_op_st_asi_reg(offset, size, sign); \
390 return; \
391 } \
392 asi = GET_FIELD(insn, 19, 26); \
393 if (is_ld) \
394 gen_op_ld_asi(asi, size, sign); \
395 else \
396 gen_op_st_asi(asi, size, sign); \
397 }
398
399#define supervisor(dc) (dc->mem_idx == 1)
400#endif
401#else
e8af50a3
FB		 402#if defined(CONFIG_USER_ONLY)
403#define gen_op_ldst(name) gen_op_##name##_raw()
0fa85d43 404#define OP_LD_TABLE(width)
e8af50a3
FB		 405#define supervisor(dc) 0
406#else
407#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
408#define OP_LD_TABLE(width) \
409static GenOpFunc *gen_op_##width[] = { \
410 &gen_op_##width##_user, \
411 &gen_op_##width##_kernel, \
412}; \
413 \
414static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
415{ \
416 int asi; \
417 \
418 asi = GET_FIELD(insn, 19, 26); \
419 switch (asi) { \
420 case 10: /* User data access */ \
421 gen_op_##width##_user(); \
422 break; \
423 case 11: /* Supervisor data access */ \
424 gen_op_##width##_kernel(); \
425 break; \
426 case 0x20 ... 0x2f: /* MMU passthrough */ \
427 if (is_ld) \
428 gen_op_ld_asi(asi, size, sign); \
429 else \
430 gen_op_st_asi(asi, size, sign); \
431 break; \
432 default: \
433 if (is_ld) \
434 gen_op_ld_asi(asi, size, sign); \
435 else \
436 gen_op_st_asi(asi, size, sign); \
437 break; \
438 } \
439}
440
441#define supervisor(dc) (dc->mem_idx == 1)
442#endif
3475187d 443#endif
e8af50a3
FB		 444
445OP_LD_TABLE(ld);
446OP_LD_TABLE(st);
447OP_LD_TABLE(ldub);
448OP_LD_TABLE(lduh);
449OP_LD_TABLE(ldsb);
450OP_LD_TABLE(ldsh);
451OP_LD_TABLE(stb);
452OP_LD_TABLE(sth);
453OP_LD_TABLE(std);
454OP_LD_TABLE(ldstub);
455OP_LD_TABLE(swap);
456OP_LD_TABLE(ldd);
457OP_LD_TABLE(stf);
458OP_LD_TABLE(stdf);
459OP_LD_TABLE(ldf);
460OP_LD_TABLE(lddf);
461
3475187d
FB		 462#ifdef TARGET_SPARC64
463OP_LD_TABLE(ldsw);
464OP_LD_TABLE(ldx);
465OP_LD_TABLE(stx);
466OP_LD_TABLE(cas);
467OP_LD_TABLE(casx);
468#endif
469
470static inline void gen_movl_imm_TN(int reg, uint32_t imm)
7a3f1944 471{
83469015 472 gen_op_movl_TN_im[reg](imm);
7a3f1944
FB		 473}
474
3475187d 475static inline void gen_movl_imm_T1(uint32_t val)
7a3f1944 476{
cf495bcf 477 gen_movl_imm_TN(1, val);
7a3f1944
FB		 478}
479
3475187d 480static inline void gen_movl_imm_T0(uint32_t val)
7a3f1944 481{
cf495bcf 482 gen_movl_imm_TN(0, val);
7a3f1944
FB		 483}
484
3475187d
FB		 485static inline void gen_movl_simm_TN(int reg, int32_t imm)
486{
487 gen_op_movl_TN_sim[reg](imm);
488}
489
490static inline void gen_movl_simm_T1(int32_t val)
491{
492 gen_movl_simm_TN(1, val);
493}
494
495static inline void gen_movl_simm_T0(int32_t val)
496{
497 gen_movl_simm_TN(0, val);
498}
499
cf495bcf 500static inline void gen_movl_reg_TN(int reg, int t)
7a3f1944 501{
cf495bcf
FB		 502 if (reg)
503 gen_op_movl_reg_TN[t][reg] ();
504 else
505 gen_movl_imm_TN(t, 0);
7a3f1944
FB		 506}
507
cf495bcf 508static inline void gen_movl_reg_T0(int reg)
7a3f1944 509{
cf495bcf 510 gen_movl_reg_TN(reg, 0);
7a3f1944
FB		 511}
512
cf495bcf 513static inline void gen_movl_reg_T1(int reg)
7a3f1944 514{
cf495bcf 515 gen_movl_reg_TN(reg, 1);
7a3f1944
FB		 516}
517
cf495bcf 518static inline void gen_movl_reg_T2(int reg)
7a3f1944 519{
cf495bcf 520 gen_movl_reg_TN(reg, 2);
7a3f1944
FB		 521}
522
cf495bcf 523static inline void gen_movl_TN_reg(int reg, int t)
7a3f1944 524{
cf495bcf
FB		 525 if (reg)
526 gen_op_movl_TN_reg[t][reg] ();
7a3f1944
FB		 527}
528
cf495bcf 529static inline void gen_movl_T0_reg(int reg)
7a3f1944 530{
cf495bcf 531 gen_movl_TN_reg(reg, 0);
7a3f1944
FB		 532}
533
cf495bcf 534static inline void gen_movl_T1_reg(int reg)
7a3f1944 535{
cf495bcf 536 gen_movl_TN_reg(reg, 1);
7a3f1944
FB		 537}
538
3475187d
FB		 539static inline void gen_jmp_im(target_ulong pc)
540{
541#ifdef TARGET_SPARC64
542 if (pc == (uint32_t)pc) {
543 gen_op_jmp_im(pc);
544 } else {
545 gen_op_jmp_im64(pc >> 32, pc);
546 }
547#else
548 gen_op_jmp_im(pc);
549#endif
550}
551
552static inline void gen_movl_npc_im(target_ulong npc)
553{
554#ifdef TARGET_SPARC64
555 if (npc == (uint32_t)npc) {
556 gen_op_movl_npc_im(npc);
557 } else {
558 gen_op_movq_npc_im64(npc >> 32, npc);
559 }
560#else
561 gen_op_movl_npc_im(npc);
562#endif
563}
564
6e256c93
FB		 565static inline void gen_goto_tb(DisasContext *s, int tb_num,
566 target_ulong pc, target_ulong npc)
567{
568 TranslationBlock *tb;
569
570 tb = s->tb;
571 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
572 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
573 /* jump to same page: we can use a direct jump */
574 if (tb_num == 0)
575 gen_op_goto_tb0(TBPARAM(tb));
576 else
577 gen_op_goto_tb1(TBPARAM(tb));
578 gen_jmp_im(pc);
579 gen_movl_npc_im(npc);
580 gen_op_movl_T0_im((long)tb + tb_num);
581 gen_op_exit_tb();
582 } else {
583 /* jump to another page: currently not optimized */
584 gen_jmp_im(pc);
585 gen_movl_npc_im(npc);
586 gen_op_movl_T0_0();
587 gen_op_exit_tb();
588 }
589}
590
83469015
FB		 591static inline void gen_branch2(DisasContext *dc, long tb, target_ulong pc1, target_ulong pc2)
592{
593 int l1;
594
595 l1 = gen_new_label();
596
597 gen_op_jz_T2_label(l1);
598
6e256c93 599 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 600
601 gen_set_label(l1);
6e256c93 602 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 603}
604
605static inline void gen_branch_a(DisasContext *dc, long tb, target_ulong pc1, target_ulong pc2)
606{
607 int l1;
608
609 l1 = gen_new_label();
610
611 gen_op_jz_T2_label(l1);
612
6e256c93 613 gen_goto_tb(dc, 0, pc2, pc1);
83469015
FB		 614
615 gen_set_label(l1);
6e256c93 616 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
83469015
FB		 617}
618
619static inline void gen_branch(DisasContext *dc, long tb, target_ulong pc, target_ulong npc)
620{
6e256c93 621 gen_goto_tb(dc, 0, pc, npc);
83469015
FB		 622}
623
624static inline void gen_generic_branch(DisasContext *dc, target_ulong npc1, target_ulong npc2)
625{
626 int l1, l2;
627
628 l1 = gen_new_label();
629 l2 = gen_new_label();
630 gen_op_jz_T2_label(l1);
631
632 gen_movl_npc_im(npc1);
633 gen_op_jmp_label(l2);
634
635 gen_set_label(l1);
636 gen_movl_npc_im(npc2);
637 gen_set_label(l2);
638}
639
640/* call this function before using T2 as it may have been set for a jump */
641static inline void flush_T2(DisasContext * dc)
642{
643 if (dc->npc == JUMP_PC) {
644 gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
645 dc->npc = DYNAMIC_PC;
646 }
647}
648
72cbca10
FB		 649static inline void save_npc(DisasContext * dc)
650{
651 if (dc->npc == JUMP_PC) {
83469015 652 gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
72cbca10
FB		 653 dc->npc = DYNAMIC_PC;
654 } else if (dc->npc != DYNAMIC_PC) {
3475187d 655 gen_movl_npc_im(dc->npc);
72cbca10
FB		 656 }
657}
658
659static inline void save_state(DisasContext * dc)
660{
3475187d 661 gen_jmp_im(dc->pc);
72cbca10
FB		 662 save_npc(dc);
663}
664
0bee699e
FB		 665static inline void gen_mov_pc_npc(DisasContext * dc)
666{
667 if (dc->npc == JUMP_PC) {
83469015 668 gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
0bee699e
FB		 669 gen_op_mov_pc_npc();
670 dc->pc = DYNAMIC_PC;
671 } else if (dc->npc == DYNAMIC_PC) {
672 gen_op_mov_pc_npc();
673 dc->pc = DYNAMIC_PC;
674 } else {
675 dc->pc = dc->npc;
676 }
677}
678
3475187d
FB		 679static GenOpFunc * const gen_cond[2][16] = {
680 {
681 gen_op_eval_ba,
682 gen_op_eval_be,
683 gen_op_eval_ble,
684 gen_op_eval_bl,
685 gen_op_eval_bleu,
686 gen_op_eval_bcs,
687 gen_op_eval_bneg,
688 gen_op_eval_bvs,
689 gen_op_eval_bn,
690 gen_op_eval_bne,
691 gen_op_eval_bg,
692 gen_op_eval_bge,
693 gen_op_eval_bgu,
694 gen_op_eval_bcc,
695 gen_op_eval_bpos,
696 gen_op_eval_bvc,
697 },
698 {
699#ifdef TARGET_SPARC64
700 gen_op_eval_ba,
701 gen_op_eval_xbe,
702 gen_op_eval_xble,
703 gen_op_eval_xbl,
704 gen_op_eval_xbleu,
705 gen_op_eval_xbcs,
706 gen_op_eval_xbneg,
707 gen_op_eval_xbvs,
708 gen_op_eval_bn,
709 gen_op_eval_xbne,
710 gen_op_eval_xbg,
711 gen_op_eval_xbge,
712 gen_op_eval_xbgu,
713 gen_op_eval_xbcc,
714 gen_op_eval_xbpos,
715 gen_op_eval_xbvc,
716#endif
717 },
718};
719
720static GenOpFunc * const gen_fcond[4][16] = {
721 {
722 gen_op_eval_ba,
723 gen_op_eval_fbne,
724 gen_op_eval_fblg,
725 gen_op_eval_fbul,
726 gen_op_eval_fbl,
727 gen_op_eval_fbug,
728 gen_op_eval_fbg,
729 gen_op_eval_fbu,
730 gen_op_eval_bn,
731 gen_op_eval_fbe,
732 gen_op_eval_fbue,
733 gen_op_eval_fbge,
734 gen_op_eval_fbuge,
735 gen_op_eval_fble,
736 gen_op_eval_fbule,
737 gen_op_eval_fbo,
738 },
739#ifdef TARGET_SPARC64
740 {
741 gen_op_eval_ba,
742 gen_op_eval_fbne_fcc1,
743 gen_op_eval_fblg_fcc1,
744 gen_op_eval_fbul_fcc1,
745 gen_op_eval_fbl_fcc1,
746 gen_op_eval_fbug_fcc1,
747 gen_op_eval_fbg_fcc1,
748 gen_op_eval_fbu_fcc1,
749 gen_op_eval_bn,
750 gen_op_eval_fbe_fcc1,
751 gen_op_eval_fbue_fcc1,
752 gen_op_eval_fbge_fcc1,
753 gen_op_eval_fbuge_fcc1,
754 gen_op_eval_fble_fcc1,
755 gen_op_eval_fbule_fcc1,
756 gen_op_eval_fbo_fcc1,
757 },
758 {
759 gen_op_eval_ba,
760 gen_op_eval_fbne_fcc2,
761 gen_op_eval_fblg_fcc2,
762 gen_op_eval_fbul_fcc2,
763 gen_op_eval_fbl_fcc2,
764 gen_op_eval_fbug_fcc2,
765 gen_op_eval_fbg_fcc2,
766 gen_op_eval_fbu_fcc2,
767 gen_op_eval_bn,
768 gen_op_eval_fbe_fcc2,
769 gen_op_eval_fbue_fcc2,
770 gen_op_eval_fbge_fcc2,
771 gen_op_eval_fbuge_fcc2,
772 gen_op_eval_fble_fcc2,
773 gen_op_eval_fbule_fcc2,
774 gen_op_eval_fbo_fcc2,
775 },
776 {
777 gen_op_eval_ba,
778 gen_op_eval_fbne_fcc3,
779 gen_op_eval_fblg_fcc3,
780 gen_op_eval_fbul_fcc3,
781 gen_op_eval_fbl_fcc3,
782 gen_op_eval_fbug_fcc3,
783 gen_op_eval_fbg_fcc3,
784 gen_op_eval_fbu_fcc3,
785 gen_op_eval_bn,
786 gen_op_eval_fbe_fcc3,
787 gen_op_eval_fbue_fcc3,
788 gen_op_eval_fbge_fcc3,
789 gen_op_eval_fbuge_fcc3,
790 gen_op_eval_fble_fcc3,
791 gen_op_eval_fbule_fcc3,
792 gen_op_eval_fbo_fcc3,
793 },
794#else
795 {}, {}, {},
796#endif
797};
7a3f1944 798
3475187d
FB		 799#ifdef TARGET_SPARC64
800static void gen_cond_reg(int cond)
e8af50a3
FB		 801{
802 switch (cond) {
e8af50a3 803 case 0x1:
3475187d 804 gen_op_eval_brz();
e8af50a3
FB		 805 break;
806 case 0x2:
3475187d 807 gen_op_eval_brlez();
e8af50a3
FB		 808 break;
809 case 0x3:
3475187d 810 gen_op_eval_brlz();
e8af50a3
FB		 811 break;
812 case 0x5:
3475187d 813 gen_op_eval_brnz();
e8af50a3
FB		 814 break;
815 case 0x6:
3475187d 816 gen_op_eval_brgz();
e8af50a3
FB		 817 break;
818 default:
3475187d
FB		 819 case 0x7:
820 gen_op_eval_brgez();
e8af50a3
FB		 821 break;
822 }
823}
3475187d 824#endif
cf495bcf 825
0bee699e 826/* XXX: potentially incorrect if dynamic npc */
3475187d 827static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 828{
cf495bcf 829 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 830 target_ulong target = dc->pc + offset;
3475187d 831
cf495bcf
FB		 832 if (cond == 0x0) {
833 /* unconditional not taken */
834 if (a) {
0bee699e 835 dc->pc = dc->npc + 4;
cf495bcf
FB		 836 dc->npc = dc->pc + 4;
837 } else {
838 dc->pc = dc->npc;
839 dc->npc = dc->pc + 4;
840 }
841 } else if (cond == 0x8) {
842 /* unconditional taken */
843 if (a) {
72cbca10 844 dc->pc = target;
cf495bcf
FB		 845 dc->npc = dc->pc + 4;
846 } else {
847 dc->pc = dc->npc;
72cbca10 848 dc->npc = target;
cf495bcf
FB		 849 }
850 } else {
72cbca10 851 flush_T2(dc);
3475187d 852 gen_cond[cc][cond]();
cf495bcf 853 if (a) {
83469015 854 gen_branch_a(dc, (long)dc->tb, target, dc->npc);
cf495bcf 855 dc->is_br = 1;
cf495bcf
FB		 856 } else {
857 dc->pc = dc->npc;
72cbca10
FB		 858 dc->jump_pc[0] = target;
859 dc->jump_pc[1] = dc->npc + 4;
860 dc->npc = JUMP_PC;
cf495bcf
FB		 861 }
862 }
7a3f1944
FB		 863}
864
0bee699e 865/* XXX: potentially incorrect if dynamic npc */
3475187d 866static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 867{
868 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 869 target_ulong target = dc->pc + offset;
870
e8af50a3
FB		 871 if (cond == 0x0) {
872 /* unconditional not taken */
873 if (a) {
874 dc->pc = dc->npc + 4;
875 dc->npc = dc->pc + 4;
876 } else {
877 dc->pc = dc->npc;
878 dc->npc = dc->pc + 4;
879 }
880 } else if (cond == 0x8) {
881 /* unconditional taken */
882 if (a) {
883 dc->pc = target;
884 dc->npc = dc->pc + 4;
885 } else {
886 dc->pc = dc->npc;
887 dc->npc = target;
888 }
889 } else {
890 flush_T2(dc);
3475187d 891 gen_fcond[cc][cond]();
e8af50a3 892 if (a) {
83469015 893 gen_branch_a(dc, (long)dc->tb, target, dc->npc);
e8af50a3
FB		 894 dc->is_br = 1;
895 } else {
896 dc->pc = dc->npc;
897 dc->jump_pc[0] = target;
898 dc->jump_pc[1] = dc->npc + 4;
899 dc->npc = JUMP_PC;
900 }
901 }
902}
903
3475187d
FB		 904#ifdef TARGET_SPARC64
905/* XXX: potentially incorrect if dynamic npc */
906static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
7a3f1944 907{
3475187d
FB		 908 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
909 target_ulong target = dc->pc + offset;
910
911 flush_T2(dc);
912 gen_cond_reg(cond);
913 if (a) {
83469015 914 gen_branch_a(dc, (long)dc->tb, target, dc->npc);
3475187d
FB		 915 dc->is_br = 1;
916 } else {
917 dc->pc = dc->npc;
918 dc->jump_pc[0] = target;
919 dc->jump_pc[1] = dc->npc + 4;
920 dc->npc = JUMP_PC;
921 }
7a3f1944
FB		 922}
923
3475187d
FB		 924static GenOpFunc * const gen_fcmps[4] = {
925 gen_op_fcmps,
926 gen_op_fcmps_fcc1,
927 gen_op_fcmps_fcc2,
928 gen_op_fcmps_fcc3,
929};
930
931static GenOpFunc * const gen_fcmpd[4] = {
932 gen_op_fcmpd,
933 gen_op_fcmpd_fcc1,
934 gen_op_fcmpd_fcc2,
935 gen_op_fcmpd_fcc3,
936};
937#endif
938
a80dde08
FB		 939static int gen_trap_ifnofpu(DisasContext * dc)
940{
941#if !defined(CONFIG_USER_ONLY)
942 if (!dc->fpu_enabled) {
943 save_state(dc);
944 gen_op_exception(TT_NFPU_INSN);
945 dc->is_br = 1;
946 return 1;
947 }
948#endif
949 return 0;
950}
951
0bee699e 952/* before an instruction, dc->pc must be static */
cf495bcf
FB		 953static void disas_sparc_insn(DisasContext * dc)
954{
955 unsigned int insn, opc, rs1, rs2, rd;
7a3f1944 956
0fa85d43 957 insn = ldl_code(dc->pc);
cf495bcf 958 opc = GET_FIELD(insn, 0, 1);
7a3f1944 959
cf495bcf
FB		 960 rd = GET_FIELD(insn, 2, 6);
961 switch (opc) {
962 case 0: /* branches/sethi */
963 {
964 unsigned int xop = GET_FIELD(insn, 7, 9);
af7bf89b 965 int32_t target;
cf495bcf 966 switch (xop) {
3475187d 967#ifdef TARGET_SPARC64
af7bf89b 968 case 0x1: /* V9 BPcc */
3475187d
FB		 969 {
970 int cc;
971
972 target = GET_FIELD_SP(insn, 0, 18);
3475187d 973 target = sign_extend(target, 18);
ee6c0b51 974 target <<= 2;
3475187d
FB		 975 cc = GET_FIELD_SP(insn, 20, 21);
976 if (cc == 0)
977 do_branch(dc, target, insn, 0);
978 else if (cc == 2)
979 do_branch(dc, target, insn, 1);
980 else
981 goto illegal_insn;
982 goto jmp_insn;
983 }
af7bf89b 984 case 0x3: /* V9 BPr */
3475187d
FB		 985 {
986 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 987 (GET_FIELD_SP(insn, 20, 21) << 14);
3475187d 988 target = sign_extend(target, 16);
ee6c0b51 989 target <<= 2;
3475187d 990 rs1 = GET_FIELD(insn, 13, 17);
83469015 991 gen_movl_reg_T0(rs1);
3475187d
FB		 992 do_branch_reg(dc, target, insn);
993 goto jmp_insn;
994 }
af7bf89b 995 case 0x5: /* V9 FBPcc */
3475187d
FB		 996 {
997 int cc = GET_FIELD_SP(insn, 20, 21);
a80dde08
FB		 998 if (gen_trap_ifnofpu(dc))
999 goto jmp_insn;
3475187d 1000 target = GET_FIELD_SP(insn, 0, 18);
3475187d 1001 target = sign_extend(target, 19);
ee6c0b51 1002 target <<= 2;
3475187d
FB		 1003 do_fbranch(dc, target, insn, cc);
1004 goto jmp_insn;
1005 }
1006#endif
cf495bcf 1007 case 0x2: /* BN+x */
7a3f1944 1008 {
3475187d 1009 target = GET_FIELD(insn, 10, 31);
cf495bcf 1010 target = sign_extend(target, 22);
ee6c0b51 1011 target <<= 2;
3475187d 1012 do_branch(dc, target, insn, 0);
cf495bcf 1013 goto jmp_insn;
7a3f1944 1014 }
e8af50a3
FB		 1015 case 0x6: /* FBN+x */
1016 {
a80dde08
FB		 1017 if (gen_trap_ifnofpu(dc))
1018 goto jmp_insn;
3475187d 1019 target = GET_FIELD(insn, 10, 31);
e8af50a3 1020 target = sign_extend(target, 22);
ee6c0b51 1021 target <<= 2;
3475187d 1022 do_fbranch(dc, target, insn, 0);
e8af50a3
FB		 1023 goto jmp_insn;
1024 }
cf495bcf 1025 case 0x4: /* SETHI */
e80cfcfc
FB		 1026#define OPTIM
1027#if defined(OPTIM)
1028 if (rd) { // nop
1029#endif
3475187d
FB		 1030 uint32_t value = GET_FIELD(insn, 10, 31);
1031 gen_movl_imm_T0(value << 10);
e80cfcfc
FB		 1032 gen_movl_T0_reg(rd);
1033#if defined(OPTIM)
1034 }
1035#endif
cf495bcf 1036 break;
3475187d
FB		 1037 case 0x0: /* UNIMPL */
1038 default:
1039 goto illegal_insn;
cf495bcf
FB		 1040 }
1041 break;
1042 }
af7bf89b 1043 break;
cf495bcf
FB		 1044 case 1:
1045 /*CALL*/ {
af7bf89b 1046 target_long target = GET_FIELDs(insn, 2, 31) << 2;
cf495bcf 1047
83469015
FB		 1048#ifdef TARGET_SPARC64
1049 if (dc->pc == (uint32_t)dc->pc) {
1050 gen_op_movl_T0_im(dc->pc);
1051 } else {
1052 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1053 }
1054#else
af7bf89b 1055 gen_op_movl_T0_im(dc->pc);
83469015 1056#endif
cf495bcf 1057 gen_movl_T0_reg(15);
af7bf89b 1058 target += dc->pc;
0bee699e 1059 gen_mov_pc_npc(dc);
72cbca10 1060 dc->npc = target;
cf495bcf
FB		 1061 }
1062 goto jmp_insn;
1063 case 2: /* FPU & Logical Operations */
1064 {
1065 unsigned int xop = GET_FIELD(insn, 7, 12);
1066 if (xop == 0x3a) { /* generate trap */
1067 int cond;
3475187d 1068
cf495bcf
FB		 1069 rs1 = GET_FIELD(insn, 13, 17);
1070 gen_movl_reg_T0(rs1);
1071 if (IS_IMM) {
e8af50a3 1072 rs2 = GET_FIELD(insn, 25, 31);
e80cfcfc 1073#if defined(OPTIM)
e8af50a3 1074 if (rs2 != 0) {
e80cfcfc 1075#endif
3475187d 1076 gen_movl_simm_T1(rs2);
e80cfcfc
FB		 1077 gen_op_add_T1_T0();
1078#if defined(OPTIM)
e8af50a3 1079 }
e80cfcfc 1080#endif
cf495bcf
FB		 1081 } else {
1082 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc
FB		 1083#if defined(OPTIM)
1084 if (rs2 != 0) {
1085#endif
1086 gen_movl_reg_T1(rs2);
1087 gen_op_add_T1_T0();
1088#if defined(OPTIM)
1089 }
1090#endif
cf495bcf 1091 }
cf495bcf
FB		 1092 cond = GET_FIELD(insn, 3, 6);
1093 if (cond == 0x8) {
a80dde08 1094 save_state(dc);
cf495bcf 1095 gen_op_trap_T0();
af7bf89b 1096 } else if (cond != 0) {
3475187d
FB		 1097#ifdef TARGET_SPARC64
1098 /* V9 icc/xcc */
1099 int cc = GET_FIELD_SP(insn, 11, 12);
a80dde08
FB		 1100 flush_T2(dc);
1101 save_state(dc);
3475187d
FB		 1102 if (cc == 0)
1103 gen_cond[0][cond]();
1104 else if (cc == 2)
1105 gen_cond[1][cond]();
1106 else
1107 goto illegal_insn;
1108#else
a80dde08
FB		 1109 flush_T2(dc);
1110 save_state(dc);
3475187d
FB		 1111 gen_cond[0][cond]();
1112#endif
cf495bcf
FB		 1113 gen_op_trapcc_T0();
1114 }
a80dde08
FB		 1115 gen_op_next_insn();
1116 gen_op_movl_T0_0();
1117 gen_op_exit_tb();
1118 dc->is_br = 1;
1119 goto jmp_insn;
cf495bcf
FB		 1120 } else if (xop == 0x28) {
1121 rs1 = GET_FIELD(insn, 13, 17);
1122 switch(rs1) {
1123 case 0: /* rdy */
3475187d 1124 gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
cf495bcf
FB		 1125 gen_movl_T0_reg(rd);
1126 break;
af7bf89b 1127 case 15: /* stbar / V9 membar */
e8af50a3 1128 break; /* no effect? */
3475187d 1129#ifdef TARGET_SPARC64
af7bf89b 1130 case 0x2: /* V9 rdccr */
3475187d
FB		 1131 gen_op_rdccr();
1132 gen_movl_T0_reg(rd);
1133 break;
af7bf89b 1134 case 0x3: /* V9 rdasi */
3475187d
FB		 1135 gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
1136 gen_movl_T0_reg(rd);
1137 break;
af7bf89b 1138 case 0x4: /* V9 rdtick */
3475187d
FB		 1139 gen_op_rdtick();
1140 gen_movl_T0_reg(rd);
1141 break;
af7bf89b 1142 case 0x5: /* V9 rdpc */
ded3ab80
PB		 1143 if (dc->pc == (uint32_t)dc->pc) {
1144 gen_op_movl_T0_im(dc->pc);
1145 } else {
1146 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1147 }
3475187d
FB		 1148 gen_movl_T0_reg(rd);
1149 break;
af7bf89b 1150 case 0x6: /* V9 rdfprs */
3475187d
FB		 1151 gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
1152 gen_movl_T0_reg(rd);
1153 break;
83469015
FB		 1154 case 0x17: /* Tick compare */
1155 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
1156 gen_movl_T0_reg(rd);
1157 break;
1158 case 0x18: /* System tick */
1159 gen_op_rdtick(); // XXX
1160 gen_movl_T0_reg(rd);
1161 break;
1162 case 0x19: /* System tick compare */
1163 gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
1164 gen_movl_T0_reg(rd);
1165 break;
1166 case 0x10: /* Performance Control */
1167 case 0x11: /* Performance Instrumentation Counter */
1168 case 0x12: /* Dispatch Control */
1169 case 0x13: /* Graphics Status */
1170 case 0x14: /* Softint set, WO */
1171 case 0x15: /* Softint clear, WO */
1172 case 0x16: /* Softint write */
3475187d
FB		 1173#endif
1174 default:
cf495bcf
FB		 1175 goto illegal_insn;
1176 }
e8af50a3 1177#if !defined(CONFIG_USER_ONLY)
3475187d
FB		 1178#ifndef TARGET_SPARC64
1179 } else if (xop == 0x29) { /* rdpsr / V9 unimp */
e8af50a3
FB		 1180 if (!supervisor(dc))
1181 goto priv_insn;
1182 gen_op_rdpsr();
1183 gen_movl_T0_reg(rd);
1184 break;
3475187d
FB		 1185#endif
1186 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
e8af50a3
FB		 1187 if (!supervisor(dc))
1188 goto priv_insn;
3475187d
FB		 1189#ifdef TARGET_SPARC64
1190 rs1 = GET_FIELD(insn, 13, 17);
1191 switch (rs1) {
1192 case 0: // tpc
1193 gen_op_rdtpc();
1194 break;
1195 case 1: // tnpc
1196 gen_op_rdtnpc();
1197 break;
1198 case 2: // tstate
1199 gen_op_rdtstate();
1200 break;
1201 case 3: // tt
1202 gen_op_rdtt();
1203 break;
1204 case 4: // tick
1205 gen_op_rdtick();
1206 break;
1207 case 5: // tba
1208 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1209 break;
1210 case 6: // pstate
1211 gen_op_rdpstate();
1212 break;
1213 case 7: // tl
1214 gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1215 break;
1216 case 8: // pil
1217 gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1218 break;
1219 case 9: // cwp
1220 gen_op_rdcwp();
1221 break;
1222 case 10: // cansave
1223 gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1224 break;
1225 case 11: // canrestore
1226 gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1227 break;
1228 case 12: // cleanwin
1229 gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1230 break;
1231 case 13: // otherwin
1232 gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1233 break;
1234 case 14: // wstate
1235 gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1236 break;
1237 case 31: // ver
1238 gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1239 break;
1240 case 15: // fq
1241 default:
1242 goto illegal_insn;
1243 }
1244#else
1245 gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
1246#endif
e8af50a3
FB		 1247 gen_movl_T0_reg(rd);
1248 break;
3475187d
FB		 1249 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1250#ifdef TARGET_SPARC64
1251 gen_op_flushw();
1252#else
e8af50a3
FB		 1253 if (!supervisor(dc))
1254 goto priv_insn;
3475187d 1255 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
e8af50a3 1256 gen_movl_T0_reg(rd);
3475187d 1257#endif
e8af50a3
FB		 1258 break;
1259#endif
e80cfcfc 1260 } else if (xop == 0x34) { /* FPU Operations */
a80dde08
FB		 1261 if (gen_trap_ifnofpu(dc))
1262 goto jmp_insn;
e8af50a3
FB		 1263 rs1 = GET_FIELD(insn, 13, 17);
1264 rs2 = GET_FIELD(insn, 27, 31);
1265 xop = GET_FIELD(insn, 18, 26);
1266 switch (xop) {
1267 case 0x1: /* fmovs */
1268 gen_op_load_fpr_FT0(rs2);
1269 gen_op_store_FT0_fpr(rd);
1270 break;
1271 case 0x5: /* fnegs */
1272 gen_op_load_fpr_FT1(rs2);
1273 gen_op_fnegs();
1274 gen_op_store_FT0_fpr(rd);
1275 break;
1276 case 0x9: /* fabss */
1277 gen_op_load_fpr_FT1(rs2);
1278 gen_op_fabss();
1279 gen_op_store_FT0_fpr(rd);
1280 break;
1281 case 0x29: /* fsqrts */
1282 gen_op_load_fpr_FT1(rs2);
1283 gen_op_fsqrts();
1284 gen_op_store_FT0_fpr(rd);
1285 break;
1286 case 0x2a: /* fsqrtd */
3475187d 1287 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1288 gen_op_fsqrtd();
3475187d 1289 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1290 break;
e80cfcfc
FB		 1291 case 0x2b: /* fsqrtq */
1292 goto nfpu_insn;
e8af50a3
FB		 1293 case 0x41:
1294 gen_op_load_fpr_FT0(rs1);
1295 gen_op_load_fpr_FT1(rs2);
1296 gen_op_fadds();
1297 gen_op_store_FT0_fpr(rd);
1298 break;
1299 case 0x42:
3475187d
FB		 1300 gen_op_load_fpr_DT0(DFPREG(rs1));
1301 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1302 gen_op_faddd();
3475187d 1303 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1304 break;
e80cfcfc
FB		 1305 case 0x43: /* faddq */
1306 goto nfpu_insn;
e8af50a3
FB		 1307 case 0x45:
1308 gen_op_load_fpr_FT0(rs1);
1309 gen_op_load_fpr_FT1(rs2);
1310 gen_op_fsubs();
1311 gen_op_store_FT0_fpr(rd);
1312 break;
1313 case 0x46:
3475187d
FB		 1314 gen_op_load_fpr_DT0(DFPREG(rs1));
1315 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1316 gen_op_fsubd();
3475187d 1317 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1318 break;
e80cfcfc
FB		 1319 case 0x47: /* fsubq */
1320 goto nfpu_insn;
e8af50a3
FB		 1321 case 0x49:
1322 gen_op_load_fpr_FT0(rs1);
1323 gen_op_load_fpr_FT1(rs2);
1324 gen_op_fmuls();
1325 gen_op_store_FT0_fpr(rd);
1326 break;
1327 case 0x4a:
3475187d
FB		 1328 gen_op_load_fpr_DT0(DFPREG(rs1));
1329 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3
FB		 1330 gen_op_fmuld();
1331 gen_op_store_DT0_fpr(rd);
1332 break;
e80cfcfc
FB		 1333 case 0x4b: /* fmulq */
1334 goto nfpu_insn;
e8af50a3
FB		 1335 case 0x4d:
1336 gen_op_load_fpr_FT0(rs1);
1337 gen_op_load_fpr_FT1(rs2);
1338 gen_op_fdivs();
1339 gen_op_store_FT0_fpr(rd);
1340 break;
1341 case 0x4e:
3475187d
FB		 1342 gen_op_load_fpr_DT0(DFPREG(rs1));
1343 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1344 gen_op_fdivd();
3475187d 1345 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1346 break;
e80cfcfc
FB		 1347 case 0x4f: /* fdivq */
1348 goto nfpu_insn;
e8af50a3
FB		 1349 case 0x69:
1350 gen_op_load_fpr_FT0(rs1);
1351 gen_op_load_fpr_FT1(rs2);
1352 gen_op_fsmuld();
3475187d 1353 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1354 break;
e80cfcfc
FB		 1355 case 0x6e: /* fdmulq */
1356 goto nfpu_insn;
e8af50a3
FB		 1357 case 0xc4:
1358 gen_op_load_fpr_FT1(rs2);
1359 gen_op_fitos();
1360 gen_op_store_FT0_fpr(rd);
1361 break;
1362 case 0xc6:
3475187d 1363 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3
FB		 1364 gen_op_fdtos();
1365 gen_op_store_FT0_fpr(rd);
1366 break;
e80cfcfc
FB		 1367 case 0xc7: /* fqtos */
1368 goto nfpu_insn;
e8af50a3
FB		 1369 case 0xc8:
1370 gen_op_load_fpr_FT1(rs2);
1371 gen_op_fitod();
3475187d 1372 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3
FB		 1373 break;
1374 case 0xc9:
1375 gen_op_load_fpr_FT1(rs2);
1376 gen_op_fstod();
3475187d 1377 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1378 break;
e80cfcfc
FB		 1379 case 0xcb: /* fqtod */
1380 goto nfpu_insn;
1381 case 0xcc: /* fitoq */
1382 goto nfpu_insn;
1383 case 0xcd: /* fstoq */
1384 goto nfpu_insn;
1385 case 0xce: /* fdtoq */
1386 goto nfpu_insn;
e8af50a3
FB		 1387 case 0xd1:
1388 gen_op_load_fpr_FT1(rs2);
1389 gen_op_fstoi();
1390 gen_op_store_FT0_fpr(rd);
1391 break;
1392 case 0xd2:
1393 gen_op_load_fpr_DT1(rs2);
1394 gen_op_fdtoi();
1395 gen_op_store_FT0_fpr(rd);
1396 break;
e80cfcfc
FB		 1397 case 0xd3: /* fqtoi */
1398 goto nfpu_insn;
3475187d 1399#ifdef TARGET_SPARC64
af7bf89b 1400 case 0x2: /* V9 fmovd */
3475187d
FB		 1401 gen_op_load_fpr_DT0(DFPREG(rs2));
1402 gen_op_store_DT0_fpr(DFPREG(rd));
1403 break;
af7bf89b 1404 case 0x6: /* V9 fnegd */
3475187d
FB		 1405 gen_op_load_fpr_DT1(DFPREG(rs2));
1406 gen_op_fnegd();
1407 gen_op_store_DT0_fpr(DFPREG(rd));
1408 break;
af7bf89b 1409 case 0xa: /* V9 fabsd */
3475187d
FB		 1410 gen_op_load_fpr_DT1(DFPREG(rs2));
1411 gen_op_fabsd();
1412 gen_op_store_DT0_fpr(DFPREG(rd));
1413 break;
af7bf89b 1414 case 0x81: /* V9 fstox */
3475187d
FB		 1415 gen_op_load_fpr_FT1(rs2);
1416 gen_op_fstox();
1417 gen_op_store_DT0_fpr(DFPREG(rd));
1418 break;
af7bf89b 1419 case 0x82: /* V9 fdtox */
3475187d
FB		 1420 gen_op_load_fpr_DT1(DFPREG(rs2));
1421 gen_op_fdtox();
1422 gen_op_store_DT0_fpr(DFPREG(rd));
1423 break;
af7bf89b 1424 case 0x84: /* V9 fxtos */
3475187d
FB		 1425 gen_op_load_fpr_DT1(DFPREG(rs2));
1426 gen_op_fxtos();
1427 gen_op_store_FT0_fpr(rd);
1428 break;
af7bf89b 1429 case 0x88: /* V9 fxtod */
3475187d
FB		 1430 gen_op_load_fpr_DT1(DFPREG(rs2));
1431 gen_op_fxtod();
1432 gen_op_store_DT0_fpr(DFPREG(rd));
1433 break;
af7bf89b
FB		 1434 case 0x3: /* V9 fmovq */
1435 case 0x7: /* V9 fnegq */
1436 case 0xb: /* V9 fabsq */
1437 case 0x83: /* V9 fqtox */
1438 case 0x8c: /* V9 fxtoq */
3475187d
FB		 1439 goto nfpu_insn;
1440#endif
1441 default:
e8af50a3
FB		 1442 goto illegal_insn;
1443 }
e80cfcfc 1444 } else if (xop == 0x35) { /* FPU Operations */
3475187d
FB		 1445#ifdef TARGET_SPARC64
1446 int cond;
1447#endif
a80dde08
FB		 1448 if (gen_trap_ifnofpu(dc))
1449 goto jmp_insn;
cf495bcf 1450 rs1 = GET_FIELD(insn, 13, 17);
e80cfcfc
FB		 1451 rs2 = GET_FIELD(insn, 27, 31);
1452 xop = GET_FIELD(insn, 18, 26);
3475187d
FB		 1453#ifdef TARGET_SPARC64
1454 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
1455 cond = GET_FIELD_SP(insn, 14, 17);
1456 gen_op_load_fpr_FT0(rd);
1457 gen_op_load_fpr_FT1(rs2);
1458 rs1 = GET_FIELD(insn, 13, 17);
1459 gen_movl_reg_T0(rs1);
1460 flush_T2(dc);
1461 gen_cond_reg(cond);
1462 gen_op_fmovs_cc();
1463 gen_op_store_FT0_fpr(rd);
1464 break;
1465 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
1466 cond = GET_FIELD_SP(insn, 14, 17);
1467 gen_op_load_fpr_DT0(rd);
1468 gen_op_load_fpr_DT1(rs2);
1469 flush_T2(dc);
1470 rs1 = GET_FIELD(insn, 13, 17);
1471 gen_movl_reg_T0(rs1);
1472 gen_cond_reg(cond);
1473 gen_op_fmovs_cc();
1474 gen_op_store_DT0_fpr(rd);
1475 break;
1476 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1477 goto nfpu_insn;
1478 }
1479#endif
e80cfcfc 1480 switch (xop) {
3475187d
FB		 1481#ifdef TARGET_SPARC64
1482 case 0x001: /* V9 fmovscc %fcc0 */
1483 cond = GET_FIELD_SP(insn, 14, 17);
1484 gen_op_load_fpr_FT0(rd);
1485 gen_op_load_fpr_FT1(rs2);
1486 flush_T2(dc);
1487 gen_fcond[0][cond]();
1488 gen_op_fmovs_cc();
1489 gen_op_store_FT0_fpr(rd);
1490 break;
1491 case 0x002: /* V9 fmovdcc %fcc0 */
1492 cond = GET_FIELD_SP(insn, 14, 17);
1493 gen_op_load_fpr_DT0(rd);
1494 gen_op_load_fpr_DT1(rs2);
1495 flush_T2(dc);
1496 gen_fcond[0][cond]();
1497 gen_op_fmovd_cc();
1498 gen_op_store_DT0_fpr(rd);
1499 break;
1500 case 0x003: /* V9 fmovqcc %fcc0 */
1501 goto nfpu_insn;
1502 case 0x041: /* V9 fmovscc %fcc1 */
1503 cond = GET_FIELD_SP(insn, 14, 17);
1504 gen_op_load_fpr_FT0(rd);
1505 gen_op_load_fpr_FT1(rs2);
1506 flush_T2(dc);
1507 gen_fcond[1][cond]();
1508 gen_op_fmovs_cc();
1509 gen_op_store_FT0_fpr(rd);
1510 break;
1511 case 0x042: /* V9 fmovdcc %fcc1 */
1512 cond = GET_FIELD_SP(insn, 14, 17);
1513 gen_op_load_fpr_DT0(rd);
1514 gen_op_load_fpr_DT1(rs2);
1515 flush_T2(dc);
1516 gen_fcond[1][cond]();
1517 gen_op_fmovd_cc();
1518 gen_op_store_DT0_fpr(rd);
1519 break;
1520 case 0x043: /* V9 fmovqcc %fcc1 */
1521 goto nfpu_insn;
1522 case 0x081: /* V9 fmovscc %fcc2 */
1523 cond = GET_FIELD_SP(insn, 14, 17);
1524 gen_op_load_fpr_FT0(rd);
1525 gen_op_load_fpr_FT1(rs2);
1526 flush_T2(dc);
1527 gen_fcond[2][cond]();
1528 gen_op_fmovs_cc();
1529 gen_op_store_FT0_fpr(rd);
1530 break;
1531 case 0x082: /* V9 fmovdcc %fcc2 */
1532 cond = GET_FIELD_SP(insn, 14, 17);
1533 gen_op_load_fpr_DT0(rd);
1534 gen_op_load_fpr_DT1(rs2);
1535 flush_T2(dc);
1536 gen_fcond[2][cond]();
1537 gen_op_fmovd_cc();
1538 gen_op_store_DT0_fpr(rd);
1539 break;
1540 case 0x083: /* V9 fmovqcc %fcc2 */
1541 goto nfpu_insn;
1542 case 0x0c1: /* V9 fmovscc %fcc3 */
1543 cond = GET_FIELD_SP(insn, 14, 17);
1544 gen_op_load_fpr_FT0(rd);
1545 gen_op_load_fpr_FT1(rs2);
1546 flush_T2(dc);
1547 gen_fcond[3][cond]();
1548 gen_op_fmovs_cc();
1549 gen_op_store_FT0_fpr(rd);
1550 break;
1551 case 0x0c2: /* V9 fmovdcc %fcc3 */
1552 cond = GET_FIELD_SP(insn, 14, 17);
1553 gen_op_load_fpr_DT0(rd);
1554 gen_op_load_fpr_DT1(rs2);
1555 flush_T2(dc);
1556 gen_fcond[3][cond]();
1557 gen_op_fmovd_cc();
1558 gen_op_store_DT0_fpr(rd);
1559 break;
1560 case 0x0c3: /* V9 fmovqcc %fcc3 */
1561 goto nfpu_insn;
1562 case 0x101: /* V9 fmovscc %icc */
1563 cond = GET_FIELD_SP(insn, 14, 17);
1564 gen_op_load_fpr_FT0(rd);
1565 gen_op_load_fpr_FT1(rs2);
1566 flush_T2(dc);
1567 gen_cond[0][cond]();
1568 gen_op_fmovs_cc();
1569 gen_op_store_FT0_fpr(rd);
1570 break;
1571 case 0x102: /* V9 fmovdcc %icc */
1572 cond = GET_FIELD_SP(insn, 14, 17);
1573 gen_op_load_fpr_DT0(rd);
1574 gen_op_load_fpr_DT1(rs2);
1575 flush_T2(dc);
1576 gen_cond[0][cond]();
1577 gen_op_fmovd_cc();
1578 gen_op_store_DT0_fpr(rd);
1579 break;
1580 case 0x103: /* V9 fmovqcc %icc */
1581 goto nfpu_insn;
1582 case 0x181: /* V9 fmovscc %xcc */
1583 cond = GET_FIELD_SP(insn, 14, 17);
1584 gen_op_load_fpr_FT0(rd);
1585 gen_op_load_fpr_FT1(rs2);
1586 flush_T2(dc);
1587 gen_cond[1][cond]();
1588 gen_op_fmovs_cc();
1589 gen_op_store_FT0_fpr(rd);
1590 break;
1591 case 0x182: /* V9 fmovdcc %xcc */
1592 cond = GET_FIELD_SP(insn, 14, 17);
1593 gen_op_load_fpr_DT0(rd);
1594 gen_op_load_fpr_DT1(rs2);
1595 flush_T2(dc);
1596 gen_cond[1][cond]();
1597 gen_op_fmovd_cc();
1598 gen_op_store_DT0_fpr(rd);
1599 break;
1600 case 0x183: /* V9 fmovqcc %xcc */
1601 goto nfpu_insn;
1602#endif
1603 case 0x51: /* V9 %fcc */
e80cfcfc
FB		 1604 gen_op_load_fpr_FT0(rs1);
1605 gen_op_load_fpr_FT1(rs2);
3475187d
FB		 1606#ifdef TARGET_SPARC64
1607 gen_fcmps[rd & 3]();
1608#else
e80cfcfc 1609 gen_op_fcmps();
3475187d 1610#endif
e80cfcfc 1611 break;
3475187d
FB		 1612 case 0x52: /* V9 %fcc */
1613 gen_op_load_fpr_DT0(DFPREG(rs1));
1614 gen_op_load_fpr_DT1(DFPREG(rs2));
1615#ifdef TARGET_SPARC64
1616 gen_fcmpd[rd & 3]();
1617#else
e80cfcfc 1618 gen_op_fcmpd();
3475187d 1619#endif
e80cfcfc
FB		 1620 break;
1621 case 0x53: /* fcmpq */
1622 goto nfpu_insn;
3475187d 1623 case 0x55: /* fcmpes, V9 %fcc */
e80cfcfc
FB		 1624 gen_op_load_fpr_FT0(rs1);
1625 gen_op_load_fpr_FT1(rs2);
3475187d
FB		 1626#ifdef TARGET_SPARC64
1627 gen_fcmps[rd & 3]();
1628#else
e80cfcfc 1629 gen_op_fcmps(); /* XXX should trap if qNaN or sNaN */
3475187d 1630#endif
e80cfcfc 1631 break;
3475187d
FB		 1632 case 0x56: /* fcmped, V9 %fcc */
1633 gen_op_load_fpr_DT0(DFPREG(rs1));
1634 gen_op_load_fpr_DT1(DFPREG(rs2));
1635#ifdef TARGET_SPARC64
1636 gen_fcmpd[rd & 3]();
1637#else
e80cfcfc 1638 gen_op_fcmpd(); /* XXX should trap if qNaN or sNaN */
3475187d 1639#endif
e80cfcfc
FB		 1640 break;
1641 case 0x57: /* fcmpeq */
1642 goto nfpu_insn;
1643 default:
1644 goto illegal_insn;
1645 }
1646#if defined(OPTIM)
1647 } else if (xop == 0x2) {
1648 // clr/mov shortcut
1649
1650 rs1 = GET_FIELD(insn, 13, 17);
1651 if (rs1 == 0) {
1652 // or %g0, x, y -> mov T1, x; mov y, T1
1653 if (IS_IMM) { /* immediate */
1654 rs2 = GET_FIELDs(insn, 19, 31);
3475187d 1655 gen_movl_simm_T1(rs2);
e80cfcfc
FB		 1656 } else { /* register */
1657 rs2 = GET_FIELD(insn, 27, 31);
1658 gen_movl_reg_T1(rs2);
1659 }
1660 gen_movl_T1_reg(rd);
1661 } else {
1662 gen_movl_reg_T0(rs1);
1663 if (IS_IMM) { /* immediate */
1664 // or x, #0, y -> mov T1, x; mov y, T1
1665 rs2 = GET_FIELDs(insn, 19, 31);
1666 if (rs2 != 0) {
3475187d 1667 gen_movl_simm_T1(rs2);
e80cfcfc
FB		 1668 gen_op_or_T1_T0();
1669 }
1670 } else { /* register */
1671 // or x, %g0, y -> mov T1, x; mov y, T1
1672 rs2 = GET_FIELD(insn, 27, 31);
1673 if (rs2 != 0) {
1674 gen_movl_reg_T1(rs2);
1675 gen_op_or_T1_T0();
1676 }
1677 }
1678 gen_movl_T0_reg(rd);
1679 }
83469015
FB		 1680#endif
1681#ifdef TARGET_SPARC64
1682 } else if (xop == 0x25) { /* sll, V9 sllx ( == sll) */
1683 rs1 = GET_FIELD(insn, 13, 17);
1684 gen_movl_reg_T0(rs1);
1685 if (IS_IMM) { /* immediate */
1686 rs2 = GET_FIELDs(insn, 20, 31);
1687 gen_movl_simm_T1(rs2);
1688 } else { /* register */
1689 rs2 = GET_FIELD(insn, 27, 31);
1690 gen_movl_reg_T1(rs2);
1691 }
1692 gen_op_sll();
1693 gen_movl_T0_reg(rd);
1694 } else if (xop == 0x26) { /* srl, V9 srlx */
1695 rs1 = GET_FIELD(insn, 13, 17);
1696 gen_movl_reg_T0(rs1);
1697 if (IS_IMM) { /* immediate */
1698 rs2 = GET_FIELDs(insn, 20, 31);
1699 gen_movl_simm_T1(rs2);
1700 } else { /* register */
1701 rs2 = GET_FIELD(insn, 27, 31);
1702 gen_movl_reg_T1(rs2);
1703 }
1704 if (insn & (1 << 12))
1705 gen_op_srlx();
1706 else
1707 gen_op_srl();
1708 gen_movl_T0_reg(rd);
1709 } else if (xop == 0x27) { /* sra, V9 srax */
1710 rs1 = GET_FIELD(insn, 13, 17);
1711 gen_movl_reg_T0(rs1);
1712 if (IS_IMM) { /* immediate */
1713 rs2 = GET_FIELDs(insn, 20, 31);
1714 gen_movl_simm_T1(rs2);
1715 } else { /* register */
1716 rs2 = GET_FIELD(insn, 27, 31);
1717 gen_movl_reg_T1(rs2);
1718 }
1719 if (insn & (1 << 12))
1720 gen_op_srax();
1721 else
1722 gen_op_sra();
1723 gen_movl_T0_reg(rd);
e80cfcfc
FB		 1724#endif
1725 } else if (xop < 0x38) {
1726 rs1 = GET_FIELD(insn, 13, 17);
1727 gen_movl_reg_T0(rs1);
1728 if (IS_IMM) { /* immediate */
cf495bcf 1729 rs2 = GET_FIELDs(insn, 19, 31);
3475187d 1730 gen_movl_simm_T1(rs2);
cf495bcf
FB		 1731 } else { /* register */
1732 rs2 = GET_FIELD(insn, 27, 31);
1733 gen_movl_reg_T1(rs2);
1734 }
1735 if (xop < 0x20) {
1736 switch (xop & ~0x10) {
1737 case 0x0:
1738 if (xop & 0x10)
1739 gen_op_add_T1_T0_cc();
1740 else
1741 gen_op_add_T1_T0();
1742 break;
1743 case 0x1:
1744 gen_op_and_T1_T0();
1745 if (xop & 0x10)
1746 gen_op_logic_T0_cc();
1747 break;
1748 case 0x2:
e80cfcfc
FB		 1749 gen_op_or_T1_T0();
1750 if (xop & 0x10)
1751 gen_op_logic_T0_cc();
1752 break;
cf495bcf
FB		 1753 case 0x3:
1754 gen_op_xor_T1_T0();
1755 if (xop & 0x10)
1756 gen_op_logic_T0_cc();
1757 break;
1758 case 0x4:
1759 if (xop & 0x10)
1760 gen_op_sub_T1_T0_cc();
1761 else
1762 gen_op_sub_T1_T0();
1763 break;
1764 case 0x5:
1765 gen_op_andn_T1_T0();
1766 if (xop & 0x10)
1767 gen_op_logic_T0_cc();
1768 break;
1769 case 0x6:
1770 gen_op_orn_T1_T0();
1771 if (xop & 0x10)
1772 gen_op_logic_T0_cc();
1773 break;
1774 case 0x7:
1775 gen_op_xnor_T1_T0();
1776 if (xop & 0x10)
1777 gen_op_logic_T0_cc();
1778 break;
1779 case 0x8:
cf495bcf 1780 if (xop & 0x10)
af7bf89b
FB		 1781 gen_op_addx_T1_T0_cc();
1782 else
1783 gen_op_addx_T1_T0();
cf495bcf 1784 break;
ded3ab80
PB		 1785#ifdef TARGET_SPARC64
1786 case 0x9: /* V9 mulx */
1787 gen_op_mulx_T1_T0();
1788 break;
1789#endif
cf495bcf
FB		 1790 case 0xa:
1791 gen_op_umul_T1_T0();
1792 if (xop & 0x10)
1793 gen_op_logic_T0_cc();
1794 break;
1795 case 0xb:
1796 gen_op_smul_T1_T0();
1797 if (xop & 0x10)
1798 gen_op_logic_T0_cc();
1799 break;
1800 case 0xc:
cf495bcf 1801 if (xop & 0x10)
af7bf89b
FB		 1802 gen_op_subx_T1_T0_cc();
1803 else
1804 gen_op_subx_T1_T0();
cf495bcf 1805 break;
ded3ab80
PB		 1806#ifdef TARGET_SPARC64
1807 case 0xd: /* V9 udivx */
1808 gen_op_udivx_T1_T0();
1809 break;
1810#endif
cf495bcf
FB		 1811 case 0xe:
1812 gen_op_udiv_T1_T0();
1813 if (xop & 0x10)
1814 gen_op_div_cc();
1815 break;
1816 case 0xf:
1817 gen_op_sdiv_T1_T0();
1818 if (xop & 0x10)
1819 gen_op_div_cc();
1820 break;
1821 default:
1822 goto illegal_insn;
1823 }
e80cfcfc 1824 gen_movl_T0_reg(rd);
cf495bcf
FB		 1825 } else {
1826 switch (xop) {
e80cfcfc
FB		 1827 case 0x20: /* taddcc */
1828 case 0x21: /* tsubcc */
1829 case 0x22: /* taddcctv */
1830 case 0x23: /* tsubcctv */
1831 goto illegal_insn;
cf495bcf
FB		 1832 case 0x24: /* mulscc */
1833 gen_op_mulscc_T1_T0();
1834 gen_movl_T0_reg(rd);
1835 break;
83469015
FB		 1836#ifndef TARGET_SPARC64
1837 case 0x25: /* sll */
3475187d 1838 gen_op_sll();
cf495bcf
FB		 1839 gen_movl_T0_reg(rd);
1840 break;
83469015 1841 case 0x26: /* srl */
3475187d 1842 gen_op_srl();
cf495bcf
FB		 1843 gen_movl_T0_reg(rd);
1844 break;
83469015 1845 case 0x27: /* sra */
3475187d 1846 gen_op_sra();
cf495bcf
FB		 1847 gen_movl_T0_reg(rd);
1848 break;
83469015 1849#endif
cf495bcf
FB		 1850 case 0x30:
1851 {
cf495bcf 1852 switch(rd) {
3475187d
FB		 1853 case 0: /* wry */
1854 gen_op_xor_T1_T0();
1855 gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
cf495bcf 1856 break;
3475187d 1857#ifdef TARGET_SPARC64
af7bf89b 1858 case 0x2: /* V9 wrccr */
3475187d
FB		 1859 gen_op_wrccr();
1860 break;
af7bf89b 1861 case 0x3: /* V9 wrasi */
3475187d
FB		 1862 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
1863 break;
af7bf89b 1864 case 0x6: /* V9 wrfprs */
3475187d
FB		 1865 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
1866 break;
1867 case 0xf: /* V9 sir, nop if user */
1868#if !defined(CONFIG_USER_ONLY)
1869 if (supervisor(dc))
1870 gen_op_sir();
1871#endif
1872 break;
83469015
FB		 1873 case 0x17: /* Tick compare */
1874#if !defined(CONFIG_USER_ONLY)
1875 if (!supervisor(dc))
1876 goto illegal_insn;
1877#endif
1878 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
1879 break;
1880 case 0x18: /* System tick */
1881#if !defined(CONFIG_USER_ONLY)
1882 if (!supervisor(dc))
1883 goto illegal_insn;
1884#endif
1885 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
1886 break;
1887 case 0x19: /* System tick compare */
1888#if !defined(CONFIG_USER_ONLY)
1889 if (!supervisor(dc))
1890 goto illegal_insn;
3475187d 1891#endif
83469015
FB		 1892 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
1893 break;
1894
3475187d
FB		 1895 case 0x10: /* Performance Control */
1896 case 0x11: /* Performance Instrumentation Counter */
1897 case 0x12: /* Dispatch Control */
1898 case 0x13: /* Graphics Status */
1899 case 0x14: /* Softint set */
1900 case 0x15: /* Softint clear */
1901 case 0x16: /* Softint write */
83469015 1902#endif
3475187d 1903 default:
cf495bcf
FB		 1904 goto illegal_insn;
1905 }
1906 }
1907 break;
e8af50a3 1908#if !defined(CONFIG_USER_ONLY)
af7bf89b 1909 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3
FB		 1910 {
1911 if (!supervisor(dc))
1912 goto priv_insn;
3475187d
FB		 1913#ifdef TARGET_SPARC64
1914 switch (rd) {
1915 case 0:
1916 gen_op_saved();
1917 break;
1918 case 1:
1919 gen_op_restored();
1920 break;
1921 default:
1922 goto illegal_insn;
1923 }
1924#else
e8af50a3
FB		 1925 gen_op_xor_T1_T0();
1926 gen_op_wrpsr();
9e61bde5
FB		 1927 save_state(dc);
1928 gen_op_next_insn();
1929 gen_op_movl_T0_0();
1930 gen_op_exit_tb();
1931 dc->is_br = 1;
3475187d 1932#endif
e8af50a3
FB		 1933 }
1934 break;
af7bf89b 1935 case 0x32: /* wrwim, V9 wrpr */
e8af50a3
FB		 1936 {
1937 if (!supervisor(dc))
1938 goto priv_insn;
1939 gen_op_xor_T1_T0();
3475187d
FB		 1940#ifdef TARGET_SPARC64
1941 switch (rd) {
1942 case 0: // tpc
1943 gen_op_wrtpc();
1944 break;
1945 case 1: // tnpc
1946 gen_op_wrtnpc();
1947 break;
1948 case 2: // tstate
1949 gen_op_wrtstate();
1950 break;
1951 case 3: // tt
1952 gen_op_wrtt();
1953 break;
1954 case 4: // tick
1955 gen_op_wrtick();
1956 break;
1957 case 5: // tba
83469015 1958 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
3475187d
FB		 1959 break;
1960 case 6: // pstate
1961 gen_op_wrpstate();
ded3ab80
PB		 1962 save_state(dc);
1963 gen_op_next_insn();
1964 gen_op_movl_T0_0();
1965 gen_op_exit_tb();
1966 dc->is_br = 1;
3475187d
FB		 1967 break;
1968 case 7: // tl
1969 gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
1970 break;
1971 case 8: // pil
1972 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
1973 break;
1974 case 9: // cwp
1975 gen_op_wrcwp();
1976 break;
1977 case 10: // cansave
1978 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
1979 break;
1980 case 11: // canrestore
1981 gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
1982 break;
1983 case 12: // cleanwin
1984 gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
1985 break;
1986 case 13: // otherwin
1987 gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
1988 break;
1989 case 14: // wstate
1990 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
1991 break;
1992 default:
1993 goto illegal_insn;
1994 }
1995#else
1996 gen_op_movl_env_T0(offsetof(CPUSPARCState, wim));
1997#endif
e8af50a3
FB		 1998 }
1999 break;
3475187d
FB		 2000#ifndef TARGET_SPARC64
2001 case 0x33: /* wrtbr, V9 unimp */
e8af50a3
FB		 2002 {
2003 if (!supervisor(dc))
2004 goto priv_insn;
2005 gen_op_xor_T1_T0();
3475187d 2006 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
e8af50a3
FB		 2007 }
2008 break;
2009#endif
3475187d
FB		 2010#endif
2011#ifdef TARGET_SPARC64
af7bf89b 2012 case 0x2c: /* V9 movcc */
3475187d
FB		 2013 {
2014 int cc = GET_FIELD_SP(insn, 11, 12);
2015 int cond = GET_FIELD_SP(insn, 14, 17);
2016 if (IS_IMM) { /* immediate */
2017 rs2 = GET_FIELD_SPs(insn, 0, 10);
2018 gen_movl_simm_T1(rs2);
2019 }
2020 else {
2021 rs2 = GET_FIELD_SP(insn, 0, 4);
2022 gen_movl_reg_T1(rs2);
2023 }
2024 gen_movl_reg_T0(rd);
2025 flush_T2(dc);
2026 if (insn & (1 << 18)) {
2027 if (cc == 0)
2028 gen_cond[0][cond]();
2029 else if (cc == 2)
2030 gen_cond[1][cond]();
2031 else
2032 goto illegal_insn;
2033 } else {
2034 gen_fcond[cc][cond]();
2035 }
2036 gen_op_mov_cc();
2037 gen_movl_T0_reg(rd);
2038 break;
2039 }
af7bf89b 2040 case 0x2d: /* V9 sdivx */
3475187d
FB		 2041 gen_op_sdivx_T1_T0();
2042 gen_movl_T0_reg(rd);
2043 break;
af7bf89b 2044 case 0x2e: /* V9 popc */
3475187d
FB		 2045 {
2046 if (IS_IMM) { /* immediate */
2047 rs2 = GET_FIELD_SPs(insn, 0, 12);
2048 gen_movl_simm_T1(rs2);
2049 // XXX optimize: popc(constant)
2050 }
2051 else {
2052 rs2 = GET_FIELD_SP(insn, 0, 4);
2053 gen_movl_reg_T1(rs2);
2054 }
2055 gen_op_popc();
2056 gen_movl_T0_reg(rd);
2057 }
af7bf89b 2058 case 0x2f: /* V9 movr */
3475187d
FB		 2059 {
2060 int cond = GET_FIELD_SP(insn, 10, 12);
2061 rs1 = GET_FIELD(insn, 13, 17);
2062 flush_T2(dc);
2063 gen_movl_reg_T0(rs1);
2064 gen_cond_reg(cond);
2065 if (IS_IMM) { /* immediate */
2066 rs2 = GET_FIELD_SPs(insn, 0, 10);
2067 gen_movl_simm_T1(rs2);
2068 }
2069 else {
2070 rs2 = GET_FIELD_SP(insn, 0, 4);
2071 gen_movl_reg_T1(rs2);
2072 }
2073 gen_movl_reg_T0(rd);
2074 gen_op_mov_cc();
2075 gen_movl_T0_reg(rd);
2076 break;
2077 }
2078 case 0x36: /* UltraSparc shutdown, VIS */
2079 {
2080 // XXX
2081 }
2082#endif
2083 default:
e80cfcfc
FB		 2084 goto illegal_insn;
2085 }
2086 }
3475187d
FB		 2087#ifdef TARGET_SPARC64
2088 } else if (xop == 0x39) { /* V9 return */
3475187d
FB		 2089 rs1 = GET_FIELD(insn, 13, 17);
2090 gen_movl_reg_T0(rs1);
2091 if (IS_IMM) { /* immediate */
2092 rs2 = GET_FIELDs(insn, 19, 31);
2093#if defined(OPTIM)
2094 if (rs2) {
2095#endif
2096 gen_movl_simm_T1(rs2);
2097 gen_op_add_T1_T0();
2098#if defined(OPTIM)
2099 }
2100#endif
2101 } else { /* register */
2102 rs2 = GET_FIELD(insn, 27, 31);
2103#if defined(OPTIM)
2104 if (rs2) {
2105#endif
2106 gen_movl_reg_T1(rs2);
2107 gen_op_add_T1_T0();
2108#if defined(OPTIM)
2109 }
2110#endif
2111 }
83469015 2112 gen_op_restore();
3475187d
FB		 2113 gen_mov_pc_npc(dc);
2114 gen_op_movl_npc_T0();
2115 dc->npc = DYNAMIC_PC;
2116 goto jmp_insn;
2117#endif
e80cfcfc
FB		 2118 } else {
2119 rs1 = GET_FIELD(insn, 13, 17);
2120 gen_movl_reg_T0(rs1);
2121 if (IS_IMM) { /* immediate */
2122 rs2 = GET_FIELDs(insn, 19, 31);
2123#if defined(OPTIM)
2124 if (rs2) {
e8af50a3 2125#endif
3475187d 2126 gen_movl_simm_T1(rs2);
e80cfcfc
FB		 2127 gen_op_add_T1_T0();
2128#if defined(OPTIM)
2129 }
e8af50a3 2130#endif
e80cfcfc
FB		 2131 } else { /* register */
2132 rs2 = GET_FIELD(insn, 27, 31);
2133#if defined(OPTIM)
2134 if (rs2) {
2135#endif
2136 gen_movl_reg_T1(rs2);
2137 gen_op_add_T1_T0();
2138#if defined(OPTIM)
2139 }
e8af50a3 2140#endif
cf495bcf 2141 }
e80cfcfc
FB		 2142 switch (xop) {
2143 case 0x38: /* jmpl */
2144 {
e80cfcfc 2145 if (rd != 0) {
ded3ab80
PB		 2146#ifdef TARGET_SPARC64
2147 if (dc->pc == (uint32_t)dc->pc) {
2148 gen_op_movl_T1_im(dc->pc);
2149 } else {
2150 gen_op_movq_T1_im64(dc->pc >> 32, dc->pc);
2151 }
2152#else
0bee699e 2153 gen_op_movl_T1_im(dc->pc);
ded3ab80 2154#endif
0bee699e 2155 gen_movl_T1_reg(rd);
e80cfcfc 2156 }
0bee699e
FB		 2157 gen_mov_pc_npc(dc);
2158 gen_op_movl_npc_T0();
e80cfcfc
FB		 2159 dc->npc = DYNAMIC_PC;
2160 }
2161 goto jmp_insn;
3475187d 2162#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
af7bf89b 2163 case 0x39: /* rett, V9 return */
e80cfcfc
FB		 2164 {
2165 if (!supervisor(dc))
2166 goto priv_insn;
0bee699e 2167 gen_mov_pc_npc(dc);
e80cfcfc 2168 gen_op_movl_npc_T0();
0bee699e 2169 dc->npc = DYNAMIC_PC;
e80cfcfc
FB		 2170 gen_op_rett();
2171 }
0bee699e 2172 goto jmp_insn;
e80cfcfc
FB		 2173#endif
2174 case 0x3b: /* flush */
2175 gen_op_flush_T0();
2176 break;
2177 case 0x3c: /* save */
2178 save_state(dc);
2179 gen_op_save();
2180 gen_movl_T0_reg(rd);
2181 break;
2182 case 0x3d: /* restore */
2183 save_state(dc);
2184 gen_op_restore();
2185 gen_movl_T0_reg(rd);
2186 break;
3475187d 2187#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
af7bf89b 2188 case 0x3e: /* V9 done/retry */
3475187d
FB		 2189 {
2190 switch (rd) {
2191 case 0:
2192 if (!supervisor(dc))
2193 goto priv_insn;
83469015
FB		 2194 dc->npc = DYNAMIC_PC;
2195 dc->pc = DYNAMIC_PC;
3475187d 2196 gen_op_done();
83469015 2197 goto jmp_insn;
3475187d
FB		 2198 case 1:
2199 if (!supervisor(dc))
2200 goto priv_insn;
83469015
FB		 2201 dc->npc = DYNAMIC_PC;
2202 dc->pc = DYNAMIC_PC;
3475187d 2203 gen_op_retry();
83469015 2204 goto jmp_insn;
3475187d
FB		 2205 default:
2206 goto illegal_insn;
2207 }
2208 }
2209 break;
2210#endif
2211 default:
e80cfcfc
FB		 2212 goto illegal_insn;
2213 }
cf495bcf
FB		 2214 }
2215 break;
2216 }
af7bf89b 2217 break;
cf495bcf
FB		 2218 case 3: /* load/store instructions */
2219 {
2220 unsigned int xop = GET_FIELD(insn, 7, 12);
2221 rs1 = GET_FIELD(insn, 13, 17);
2222 gen_movl_reg_T0(rs1);
2223 if (IS_IMM) { /* immediate */
2224 rs2 = GET_FIELDs(insn, 19, 31);
e80cfcfc 2225#if defined(OPTIM)
e8af50a3 2226 if (rs2 != 0) {
e80cfcfc 2227#endif
3475187d 2228 gen_movl_simm_T1(rs2);
e8af50a3 2229 gen_op_add_T1_T0();
e80cfcfc 2230#if defined(OPTIM)
e8af50a3 2231 }
e80cfcfc 2232#endif
cf495bcf
FB		 2233 } else { /* register */
2234 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc
FB		 2235#if defined(OPTIM)
2236 if (rs2 != 0) {
2237#endif
2238 gen_movl_reg_T1(rs2);
2239 gen_op_add_T1_T0();
2240#if defined(OPTIM)
2241 }
2242#endif
cf495bcf 2243 }
3475187d
FB		 2244 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || \
2245 (xop > 0x17 && xop < 0x1d ) || \
2246 (xop > 0x2c && xop < 0x33) || xop == 0x1f) {
cf495bcf
FB		 2247 switch (xop) {
2248 case 0x0: /* load word */
e8af50a3 2249 gen_op_ldst(ld);
cf495bcf
FB		 2250 break;
2251 case 0x1: /* load unsigned byte */
e8af50a3 2252 gen_op_ldst(ldub);
cf495bcf
FB		 2253 break;
2254 case 0x2: /* load unsigned halfword */
e8af50a3 2255 gen_op_ldst(lduh);
cf495bcf
FB		 2256 break;
2257 case 0x3: /* load double word */
e8af50a3 2258 gen_op_ldst(ldd);
cf495bcf
FB		 2259 gen_movl_T0_reg(rd + 1);
2260 break;
2261 case 0x9: /* load signed byte */
e8af50a3 2262 gen_op_ldst(ldsb);
cf495bcf
FB		 2263 break;
2264 case 0xa: /* load signed halfword */
e8af50a3 2265 gen_op_ldst(ldsh);
cf495bcf
FB		 2266 break;
2267 case 0xd: /* ldstub -- XXX: should be atomically */
e8af50a3 2268 gen_op_ldst(ldstub);
cf495bcf
FB		 2269 break;
2270 case 0x0f: /* swap register with memory. Also atomically */
e80cfcfc 2271 gen_movl_reg_T1(rd);
e8af50a3
FB		 2272 gen_op_ldst(swap);
2273 break;
3475187d 2274#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
e8af50a3 2275 case 0x10: /* load word alternate */
3475187d 2276#ifndef TARGET_SPARC64
e8af50a3
FB		 2277 if (!supervisor(dc))
2278 goto priv_insn;
3475187d 2279#endif
e8af50a3
FB		 2280 gen_op_lda(insn, 1, 4, 0);
2281 break;
2282 case 0x11: /* load unsigned byte alternate */
3475187d 2283#ifndef TARGET_SPARC64
e8af50a3
FB		 2284 if (!supervisor(dc))
2285 goto priv_insn;
3475187d 2286#endif
e8af50a3
FB		 2287 gen_op_lduba(insn, 1, 1, 0);
2288 break;
2289 case 0x12: /* load unsigned halfword alternate */
3475187d 2290#ifndef TARGET_SPARC64
e8af50a3
FB		 2291 if (!supervisor(dc))
2292 goto priv_insn;
3475187d 2293#endif
e8af50a3
FB		 2294 gen_op_lduha(insn, 1, 2, 0);
2295 break;
2296 case 0x13: /* load double word alternate */
3475187d 2297#ifndef TARGET_SPARC64
e8af50a3
FB		 2298 if (!supervisor(dc))
2299 goto priv_insn;
3475187d 2300#endif
e8af50a3
FB		 2301 gen_op_ldda(insn, 1, 8, 0);
2302 gen_movl_T0_reg(rd + 1);
2303 break;
2304 case 0x19: /* load signed byte alternate */
3475187d 2305#ifndef TARGET_SPARC64
e8af50a3
FB		 2306 if (!supervisor(dc))
2307 goto priv_insn;
3475187d 2308#endif
e8af50a3
FB		 2309 gen_op_ldsba(insn, 1, 1, 1);
2310 break;
2311 case 0x1a: /* load signed halfword alternate */
3475187d 2312#ifndef TARGET_SPARC64
e8af50a3
FB		 2313 if (!supervisor(dc))
2314 goto priv_insn;
3475187d 2315#endif
e8af50a3
FB		 2316 gen_op_ldsha(insn, 1, 2 ,1);
2317 break;
2318 case 0x1d: /* ldstuba -- XXX: should be atomically */
3475187d 2319#ifndef TARGET_SPARC64
e8af50a3
FB		 2320 if (!supervisor(dc))
2321 goto priv_insn;
3475187d 2322#endif
e8af50a3
FB		 2323 gen_op_ldstuba(insn, 1, 1, 0);
2324 break;
2325 case 0x1f: /* swap reg with alt. memory. Also atomically */
3475187d 2326#ifndef TARGET_SPARC64
e8af50a3
FB		 2327 if (!supervisor(dc))
2328 goto priv_insn;
3475187d 2329#endif
e80cfcfc 2330 gen_movl_reg_T1(rd);
e8af50a3 2331 gen_op_swapa(insn, 1, 4, 0);
cf495bcf 2332 break;
3475187d
FB		 2333
2334#ifndef TARGET_SPARC64
0fa85d43
FB		 2335 /* avoid warnings */
2336 (void) &gen_op_stfa;
2337 (void) &gen_op_stdfa;
2338 (void) &gen_op_ldfa;
2339 (void) &gen_op_lddfa;
3475187d
FB		 2340#else
2341#if !defined(CONFIG_USER_ONLY)
2342 (void) &gen_op_cas;
2343 (void) &gen_op_casx;
e80cfcfc 2344#endif
3475187d
FB		 2345#endif
2346#endif
2347#ifdef TARGET_SPARC64
af7bf89b 2348 case 0x08: /* V9 ldsw */
3475187d
FB		 2349 gen_op_ldst(ldsw);
2350 break;
af7bf89b 2351 case 0x0b: /* V9 ldx */
3475187d
FB		 2352 gen_op_ldst(ldx);
2353 break;
af7bf89b 2354 case 0x18: /* V9 ldswa */
3475187d
FB		 2355 gen_op_ldswa(insn, 1, 4, 1);
2356 break;
af7bf89b 2357 case 0x1b: /* V9 ldxa */
3475187d
FB		 2358 gen_op_ldxa(insn, 1, 8, 0);
2359 break;
2360 case 0x2d: /* V9 prefetch, no effect */
2361 goto skip_move;
af7bf89b 2362 case 0x30: /* V9 ldfa */
3475187d
FB		 2363 gen_op_ldfa(insn, 1, 8, 0); // XXX
2364 break;
af7bf89b 2365 case 0x33: /* V9 lddfa */
3475187d 2366 gen_op_lddfa(insn, 1, 8, 0); // XXX
af7bf89b 2367
3475187d
FB		 2368 break;
2369 case 0x3d: /* V9 prefetcha, no effect */
2370 goto skip_move;
af7bf89b 2371 case 0x32: /* V9 ldqfa */
3475187d
FB		 2372 goto nfpu_insn;
2373#endif
2374 default:
e80cfcfc 2375 goto illegal_insn;
7a3f1944 2376 }
cf495bcf 2377 gen_movl_T1_reg(rd);
3475187d
FB		 2378#ifdef TARGET_SPARC64
2379 skip_move: ;
2380#endif
e8af50a3 2381 } else if (xop >= 0x20 && xop < 0x24) {
a80dde08
FB		 2382 if (gen_trap_ifnofpu(dc))
2383 goto jmp_insn;
e8af50a3
FB		 2384 switch (xop) {
2385 case 0x20: /* load fpreg */
2386 gen_op_ldst(ldf);
2387 gen_op_store_FT0_fpr(rd);
2388 break;
2389 case 0x21: /* load fsr */
9e61bde5 2390 gen_op_ldst(ldf);
e8af50a3
FB		 2391 gen_op_ldfsr();
2392 break;
af7bf89b
FB		 2393 case 0x22: /* load quad fpreg */
2394 goto nfpu_insn;
e8af50a3
FB		 2395 case 0x23: /* load double fpreg */
2396 gen_op_ldst(lddf);
3475187d 2397 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 2398 break;
e80cfcfc
FB		 2399 default:
2400 goto illegal_insn;
e8af50a3 2401 }
3475187d
FB		 2402 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
2403 xop == 0xe || xop == 0x1e) {
cf495bcf
FB		 2404 gen_movl_reg_T1(rd);
2405 switch (xop) {
2406 case 0x4:
e8af50a3 2407 gen_op_ldst(st);
cf495bcf
FB		 2408 break;
2409 case 0x5:
e8af50a3 2410 gen_op_ldst(stb);
cf495bcf
FB		 2411 break;
2412 case 0x6:
e8af50a3 2413 gen_op_ldst(sth);
cf495bcf
FB		 2414 break;
2415 case 0x7:
72cbca10 2416 flush_T2(dc);
cf495bcf 2417 gen_movl_reg_T2(rd + 1);
e8af50a3
FB		 2418 gen_op_ldst(std);
2419 break;
3475187d 2420#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
e8af50a3 2421 case 0x14:
3475187d 2422#ifndef TARGET_SPARC64
e8af50a3
FB		 2423 if (!supervisor(dc))
2424 goto priv_insn;
3475187d 2425#endif
e8af50a3 2426 gen_op_sta(insn, 0, 4, 0);
d39c0b99 2427 break;
e8af50a3 2428 case 0x15:
3475187d 2429#ifndef TARGET_SPARC64
e8af50a3
FB		 2430 if (!supervisor(dc))
2431 goto priv_insn;
3475187d 2432#endif
e8af50a3 2433 gen_op_stba(insn, 0, 1, 0);
d39c0b99 2434 break;
e8af50a3 2435 case 0x16:
3475187d 2436#ifndef TARGET_SPARC64
e8af50a3
FB		 2437 if (!supervisor(dc))
2438 goto priv_insn;
3475187d 2439#endif
e8af50a3 2440 gen_op_stha(insn, 0, 2, 0);
d39c0b99 2441 break;
e8af50a3 2442 case 0x17:
3475187d 2443#ifndef TARGET_SPARC64
e8af50a3
FB		 2444 if (!supervisor(dc))
2445 goto priv_insn;
3475187d 2446#endif
e8af50a3
FB		 2447 flush_T2(dc);
2448 gen_movl_reg_T2(rd + 1);
2449 gen_op_stda(insn, 0, 8, 0);
d39c0b99 2450 break;
e80cfcfc 2451#endif
3475187d 2452#ifdef TARGET_SPARC64
af7bf89b 2453 case 0x0e: /* V9 stx */
3475187d
FB		 2454 gen_op_ldst(stx);
2455 break;
af7bf89b 2456 case 0x1e: /* V9 stxa */
3475187d
FB		 2457 gen_op_stxa(insn, 0, 8, 0); // XXX
2458 break;
2459#endif
2460 default:
e80cfcfc 2461 goto illegal_insn;
7a3f1944 2462 }
e8af50a3 2463 } else if (xop > 0x23 && xop < 0x28) {
a80dde08
FB		 2464 if (gen_trap_ifnofpu(dc))
2465 goto jmp_insn;
e8af50a3
FB		 2466 switch (xop) {
2467 case 0x24:
2468 gen_op_load_fpr_FT0(rd);
2469 gen_op_ldst(stf);
2470 break;
af7bf89b 2471 case 0x25: /* stfsr, V9 stxfsr */
e8af50a3 2472 gen_op_stfsr();
9e61bde5 2473 gen_op_ldst(stf);
e8af50a3 2474 break;
af7bf89b
FB		 2475 case 0x26: /* stdfq */
2476 goto nfpu_insn;
e8af50a3 2477 case 0x27:
3475187d 2478 gen_op_load_fpr_DT0(DFPREG(rd));
e8af50a3
FB		 2479 gen_op_ldst(stdf);
2480 break;
e80cfcfc 2481 default:
3475187d
FB		 2482 goto illegal_insn;
2483 }
2484 } else if (xop > 0x33 && xop < 0x3f) {
2485#ifdef TARGET_SPARC64
2486 switch (xop) {
af7bf89b 2487 case 0x34: /* V9 stfa */
3475187d
FB		 2488 gen_op_stfa(insn, 0, 0, 0); // XXX
2489 break;
af7bf89b 2490 case 0x37: /* V9 stdfa */
3475187d
FB		 2491 gen_op_stdfa(insn, 0, 0, 0); // XXX
2492 break;
af7bf89b 2493 case 0x3c: /* V9 casa */
3475187d
FB		 2494 gen_op_casa(insn, 0, 4, 0); // XXX
2495 break;
af7bf89b 2496 case 0x3e: /* V9 casxa */
3475187d
FB		 2497 gen_op_casxa(insn, 0, 8, 0); // XXX
2498 break;
af7bf89b 2499 case 0x36: /* V9 stqfa */
3475187d
FB		 2500 goto nfpu_insn;
2501 default:
e80cfcfc 2502 goto illegal_insn;
e8af50a3 2503 }
3475187d 2504#else
e80cfcfc 2505 goto illegal_insn;
3475187d 2506#endif
e8af50a3 2507 }
e80cfcfc
FB		 2508 else
2509 goto illegal_insn;
7a3f1944 2510 }
af7bf89b 2511 break;
cf495bcf
FB		 2512 }
2513 /* default case for non jump instructions */
72cbca10
FB		 2514 if (dc->npc == DYNAMIC_PC) {
2515 dc->pc = DYNAMIC_PC;
2516 gen_op_next_insn();
2517 } else if (dc->npc == JUMP_PC) {
2518 /* we can do a static jump */
83469015 2519 gen_branch2(dc, (long)dc->tb, dc->jump_pc[0], dc->jump_pc[1]);
72cbca10
FB		 2520 dc->is_br = 1;
2521 } else {
cf495bcf
FB		 2522 dc->pc = dc->npc;
2523 dc->npc = dc->npc + 4;
cf495bcf 2524 }
e80cfcfc 2525 jmp_insn:
cf495bcf
FB		 2526 return;
2527 illegal_insn:
72cbca10 2528 save_state(dc);
cf495bcf
FB		 2529 gen_op_exception(TT_ILL_INSN);
2530 dc->is_br = 1;
e8af50a3 2531 return;
e80cfcfc 2532#if !defined(CONFIG_USER_ONLY)
e8af50a3
FB		 2533 priv_insn:
2534 save_state(dc);
2535 gen_op_exception(TT_PRIV_INSN);
2536 dc->is_br = 1;
e80cfcfc
FB		 2537 return;
2538#endif
2539 nfpu_insn:
2540 save_state(dc);
2541 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
2542 dc->is_br = 1;
7a3f1944
FB		 2543}
2544
cf495bcf 2545static inline int gen_intermediate_code_internal(TranslationBlock * tb,
e8af50a3 2546 int spc, CPUSPARCState *env)
7a3f1944 2547{
72cbca10 2548 target_ulong pc_start, last_pc;
cf495bcf
FB		 2549 uint16_t *gen_opc_end;
2550 DisasContext dc1, *dc = &dc1;
e8af50a3 2551 int j, lj = -1;
cf495bcf
FB		 2552
2553 memset(dc, 0, sizeof(DisasContext));
cf495bcf 2554 dc->tb = tb;
72cbca10 2555 pc_start = tb->pc;
cf495bcf 2556 dc->pc = pc_start;
e80cfcfc 2557 last_pc = dc->pc;
72cbca10 2558 dc->npc = (target_ulong) tb->cs_base;
e8af50a3
FB		 2559#if defined(CONFIG_USER_ONLY)
2560 dc->mem_idx = 0;
a80dde08 2561 dc->fpu_enabled = 1;
e8af50a3
FB		 2562#else
2563 dc->mem_idx = ((env->psrs) != 0);
a80dde08
FB		 2564#ifdef TARGET_SPARC64
2565 dc->fpu_enabled = (((env->pstate & PS_PEF) != 0) && ((env->fprs & FPRS_FEF) != 0));
2566#else
2567 dc->fpu_enabled = ((env->psref) != 0);
2568#endif
e8af50a3 2569#endif
cf495bcf
FB		 2570 gen_opc_ptr = gen_opc_buf;
2571 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2572 gen_opparam_ptr = gen_opparam_buf;
83469015 2573 nb_gen_labels = 0;
cf495bcf
FB		 2574
2575 do {
e8af50a3
FB		 2576 if (env->nb_breakpoints > 0) {
2577 for(j = 0; j < env->nb_breakpoints; j++) {
2578 if (env->breakpoints[j] == dc->pc) {
e80cfcfc
FB		 2579 if (dc->pc != pc_start)
2580 save_state(dc);
2581 gen_op_debug();
2582 gen_op_movl_T0_0();
2583 gen_op_exit_tb();
2584 dc->is_br = 1;
2585 goto exit_gen_loop;
e8af50a3
FB		 2586 }
2587 }
2588 }
2589 if (spc) {
2590 if (loglevel > 0)
2591 fprintf(logfile, "Search PC...\n");
2592 j = gen_opc_ptr - gen_opc_buf;
2593 if (lj < j) {
2594 lj++;
2595 while (lj < j)
2596 gen_opc_instr_start[lj++] = 0;
2597 gen_opc_pc[lj] = dc->pc;
2598 gen_opc_npc[lj] = dc->npc;
2599 gen_opc_instr_start[lj] = 1;
2600 }
2601 }
cf495bcf
FB		 2602 last_pc = dc->pc;
2603 disas_sparc_insn(dc);
3475187d 2604
cf495bcf
FB		 2605 if (dc->is_br)
2606 break;
2607 /* if the next PC is different, we abort now */
2608 if (dc->pc != (last_pc + 4))
2609 break;
d39c0b99
FB		 2610 /* if we reach a page boundary, we stop generation so that the
2611 PC of a TT_TFAULT exception is always in the right page */
2612 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
2613 break;
e80cfcfc
FB		 2614 /* if single step mode, we generate only one instruction and
2615 generate an exception */
2616 if (env->singlestep_enabled) {
3475187d 2617 gen_jmp_im(dc->pc);
e80cfcfc
FB		 2618 gen_op_movl_T0_0();
2619 gen_op_exit_tb();
2620 break;
2621 }
cf495bcf
FB		 2622 } while ((gen_opc_ptr < gen_opc_end) &&
2623 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
e80cfcfc
FB		 2624
2625 exit_gen_loop:
72cbca10
FB		 2626 if (!dc->is_br) {
2627 if (dc->pc != DYNAMIC_PC &&
2628 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
2629 /* static PC and NPC: we can use direct chaining */
83469015 2630 gen_branch(dc, (long)tb, dc->pc, dc->npc);
72cbca10
FB		 2631 } else {
2632 if (dc->pc != DYNAMIC_PC)
3475187d 2633 gen_jmp_im(dc->pc);
72cbca10
FB		 2634 save_npc(dc);
2635 gen_op_movl_T0_0();
2636 gen_op_exit_tb();
2637 }
2638 }
cf495bcf 2639 *gen_opc_ptr = INDEX_op_end;
e8af50a3
FB		 2640 if (spc) {
2641 j = gen_opc_ptr - gen_opc_buf;
2642 lj++;
2643 while (lj <= j)
2644 gen_opc_instr_start[lj++] = 0;
2645 tb->size = 0;
2646#if 0
2647 if (loglevel > 0) {
2648 page_dump(logfile);
2649 }
2650#endif
c3278b7b
FB		 2651 gen_opc_jump_pc[0] = dc->jump_pc[0];
2652 gen_opc_jump_pc[1] = dc->jump_pc[1];
e8af50a3 2653 } else {
e80cfcfc 2654 tb->size = last_pc + 4 - pc_start;
e8af50a3 2655 }
7a3f1944 2656#ifdef DEBUG_DISAS
e19e89a5 2657 if (loglevel & CPU_LOG_TB_IN_ASM) {
cf495bcf 2658 fprintf(logfile, "--------------\n");
0fa85d43
FB		 2659 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2660 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
cf495bcf 2661 fprintf(logfile, "\n");
e19e89a5
FB		 2662 if (loglevel & CPU_LOG_TB_OP) {
2663 fprintf(logfile, "OP:\n");
2664 dump_ops(gen_opc_buf, gen_opparam_buf);
2665 fprintf(logfile, "\n");
2666 }
cf495bcf 2667 }
7a3f1944 2668#endif
cf495bcf 2669 return 0;
7a3f1944
FB		 2670}
2671
cf495bcf 2672int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 2673{
e8af50a3 2674 return gen_intermediate_code_internal(tb, 0, env);
7a3f1944
FB		 2675}
2676
cf495bcf 2677int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 2678{
e8af50a3 2679 return gen_intermediate_code_internal(tb, 1, env);
7a3f1944
FB		 2680}
2681
e80cfcfc 2682extern int ram_size;
cf495bcf 2683
e80cfcfc
FB		 2684void cpu_reset(CPUSPARCState *env)
2685{
cf495bcf 2686 memset(env, 0, sizeof(*env));
bb05683b 2687 tlb_flush(env, 1);
cf495bcf
FB		 2688 env->cwp = 0;
2689 env->wim = 1;
2690 env->regwptr = env->regbase + (env->cwp * 16);
e8af50a3 2691#if defined(CONFIG_USER_ONLY)
cf495bcf 2692 env->user_mode_only = 1;
e8af50a3 2693#else
e8af50a3 2694 env->psrs = 1;
0bee699e 2695 env->psrps = 1;
e80cfcfc 2696 env->gregs[1] = ram_size;
3475187d 2697#ifdef TARGET_SPARC64
83469015 2698 env->pstate = PS_PRIV;
3475187d 2699 env->version = GET_VER(env);
83469015 2700 env->pc = 0x1fff0000000ULL;
3475187d
FB		 2701#else
2702 env->mmuregs[0] = (0x04 << 24); /* Impl 0, ver 4, MMU disabled */
83469015 2703 env->pc = 0xffd00000;
3475187d 2704#endif
83469015 2705 env->npc = env->pc + 4;
e8af50a3 2706#endif
e80cfcfc
FB		 2707}
2708
2709CPUSPARCState *cpu_sparc_init(void)
2710{
2711 CPUSPARCState *env;
2712
c68ea704
FB		 2713 env = qemu_mallocz(sizeof(CPUSPARCState));
2714 if (!env)
2715 return NULL;
2716 cpu_exec_init(env);
e80cfcfc 2717 cpu_reset(env);
cf495bcf 2718 return (env);
7a3f1944
FB		 2719}
2720
2721#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
2722
7fe48483
FB		 2723void cpu_dump_state(CPUState *env, FILE *f,
2724 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2725 int flags)
7a3f1944 2726{
cf495bcf
FB		 2727 int i, x;
2728
af7bf89b 2729 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
7fe48483 2730 cpu_fprintf(f, "General Registers:\n");
cf495bcf 2731 for (i = 0; i < 4; i++)
af7bf89b 2732 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 2733 cpu_fprintf(f, "\n");
cf495bcf 2734 for (; i < 8; i++)
af7bf89b 2735 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 2736 cpu_fprintf(f, "\nCurrent Register Window:\n");
cf495bcf
FB		 2737 for (x = 0; x < 3; x++) {
2738 for (i = 0; i < 4; i++)
af7bf89b 2739 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
cf495bcf
FB		 2740 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
2741 env->regwptr[i + x * 8]);
7fe48483 2742 cpu_fprintf(f, "\n");
cf495bcf 2743 for (; i < 8; i++)
af7bf89b 2744 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
cf495bcf
FB		 2745 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
2746 env->regwptr[i + x * 8]);
7fe48483 2747 cpu_fprintf(f, "\n");
cf495bcf 2748 }
7fe48483 2749 cpu_fprintf(f, "\nFloating Point Registers:\n");
e8af50a3
FB		 2750 for (i = 0; i < 32; i++) {
2751 if ((i & 3) == 0)
7fe48483
FB		 2752 cpu_fprintf(f, "%%f%02d:", i);
2753 cpu_fprintf(f, " %016lf", env->fpr[i]);
e8af50a3 2754 if ((i & 3) == 3)
7fe48483 2755 cpu_fprintf(f, "\n");
e8af50a3 2756 }
ded3ab80
PB		 2757#ifdef TARGET_SPARC64
2758 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d\n",
2759 env->pstate, GET_CCR(env), env->asi, env->tl);
2760 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
2761 env->cansave, env->canrestore, env->otherwin, env->wstate,
2762 env->cleanwin, NWINDOWS - 1 - env->cwp);
2763#else
7fe48483 2764 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
cf495bcf
FB		 2765 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
2766 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
e8af50a3
FB		 2767 env->psrs?'S':'-', env->psrps?'P':'-',
2768 env->psret?'E':'-', env->wim);
ded3ab80 2769#endif
3475187d 2770 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
7a3f1944 2771}
edfcbd99 2772
e80cfcfc 2773#if defined(CONFIG_USER_ONLY)
d785e6be 2774target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
edfcbd99
FB		 2775{
2776 return addr;
2777}
658138bc 2778
e80cfcfc 2779#else
af7bf89b
FB		 2780extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
2781 int *access_index, target_ulong address, int rw,
0fa85d43
FB		 2782 int is_user);
2783
d785e6be 2784target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
e80cfcfc 2785{
af7bf89b 2786 target_phys_addr_t phys_addr;
e80cfcfc
FB		 2787 int prot, access_index;
2788
2789 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
6b1575b7
FB		 2790 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 0, 0) != 0)
2791 return -1;
e80cfcfc
FB		 2792 return phys_addr;
2793}
2794#endif
2795
658138bc
FB		 2796void helper_flush(target_ulong addr)
2797{
2798 addr &= ~7;
2799 tb_invalidate_page_range(addr, addr + 8);
2800}
Qemu copy for testing