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Commit | Line | Data |
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7a3f1944 FB |
1 | /* |
2 | SPARC translation | |
3 | ||
4 | Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at> | |
3475187d | 5 | Copyright (C) 2003-2005 Fabrice Bellard |
7a3f1944 FB |
6 | |
7 | This library is free software; you can redistribute it and/or | |
8 | modify it under the terms of the GNU Lesser General Public | |
9 | License as published by the Free Software Foundation; either | |
10 | version 2 of the License, or (at your option) any later version. | |
11 | ||
12 | This library is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | Lesser General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU Lesser General Public | |
18 | License along with this library; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
7a3f1944 FB |
22 | #include <stdarg.h> |
23 | #include <stdlib.h> | |
24 | #include <stdio.h> | |
25 | #include <string.h> | |
26 | #include <inttypes.h> | |
27 | ||
28 | #include "cpu.h" | |
29 | #include "exec-all.h" | |
30 | #include "disas.h" | |
1a2fb1c0 | 31 | #include "helper.h" |
57fec1fe | 32 | #include "tcg-op.h" |
7a3f1944 FB |
33 | |
34 | #define DEBUG_DISAS | |
35 | ||
72cbca10 FB |
36 | #define DYNAMIC_PC 1 /* dynamic pc value */ |
37 | #define JUMP_PC 2 /* dynamic pc value which takes only two values | |
38 | according to jump_pc[T2] */ | |
39 | ||
1a2fb1c0 | 40 | /* global register indexes */ |
d987963a | 41 | static TCGv cpu_env, cpu_regwptr; |
77f193da | 42 | static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst; |
48d5c82b | 43 | static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; |
255e1fcb BS |
44 | static TCGv cpu_y; |
45 | #ifndef CONFIG_USER_ONLY | |
46 | static TCGv cpu_tbr; | |
47 | #endif | |
6ae20372 | 48 | static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val; |
dc99a3f2 | 49 | #ifdef TARGET_SPARC64 |
255e1fcb BS |
50 | static TCGv cpu_xcc, cpu_asi, cpu_fprs, cpu_gsr; |
51 | static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr; | |
52 | static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver; | |
53 | #else | |
54 | static TCGv cpu_wim; | |
dc99a3f2 | 55 | #endif |
1a2fb1c0 | 56 | /* local register indexes (only used inside old micro ops) */ |
8911f501 | 57 | static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64; |
1a2fb1c0 | 58 | |
2e70f6ef PB |
59 | #include "gen-icount.h" |
60 | ||
7a3f1944 | 61 | typedef struct DisasContext { |
0f8a249a BS |
62 | target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */ |
63 | target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */ | |
72cbca10 | 64 | target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ |
cf495bcf | 65 | int is_br; |
e8af50a3 | 66 | int mem_idx; |
a80dde08 | 67 | int fpu_enabled; |
2cade6a3 | 68 | int address_mask_32bit; |
cf495bcf | 69 | struct TranslationBlock *tb; |
5578ceab | 70 | sparc_def_t *def; |
7a3f1944 FB |
71 | } DisasContext; |
72 | ||
3475187d | 73 | // This function uses non-native bit order |
7a3f1944 FB |
74 | #define GET_FIELD(X, FROM, TO) \ |
75 | ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) | |
76 | ||
3475187d FB |
77 | // This function uses the order in the manuals, i.e. bit 0 is 2^0 |
78 | #define GET_FIELD_SP(X, FROM, TO) \ | |
79 | GET_FIELD(X, 31 - (TO), 31 - (FROM)) | |
80 | ||
81 | #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) | |
46d38ba8 | 82 | #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1)) |
3475187d FB |
83 | |
84 | #ifdef TARGET_SPARC64 | |
19f329ad | 85 | #define FFPREG(r) (r) |
0387d928 | 86 | #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e)) |
1f587329 | 87 | #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c)) |
3475187d | 88 | #else |
19f329ad | 89 | #define FFPREG(r) (r) |
c185970a | 90 | #define DFPREG(r) (r & 0x1e) |
1f587329 | 91 | #define QFPREG(r) (r & 0x1c) |
3475187d FB |
92 | #endif |
93 | ||
94 | static int sign_extend(int x, int len) | |
95 | { | |
96 | len = 32 - len; | |
97 | return (x << len) >> len; | |
98 | } | |
99 | ||
7a3f1944 FB |
100 | #define IS_IMM (insn & (1<<13)) |
101 | ||
ff07ec83 BS |
102 | /* floating point registers moves */ |
103 | static void gen_op_load_fpr_FT0(unsigned int src) | |
104 | { | |
8911f501 BS |
105 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
106 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0)); | |
3475187d | 107 | } |
ff07ec83 BS |
108 | |
109 | static void gen_op_load_fpr_FT1(unsigned int src) | |
110 | { | |
8911f501 BS |
111 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
112 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1)); | |
e8af50a3 FB |
113 | } |
114 | ||
ff07ec83 BS |
115 | static void gen_op_store_FT0_fpr(unsigned int dst) |
116 | { | |
8911f501 BS |
117 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0)); |
118 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst])); | |
ff07ec83 BS |
119 | } |
120 | ||
121 | static void gen_op_load_fpr_DT0(unsigned int src) | |
122 | { | |
8911f501 | 123 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
77f193da BS |
124 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + |
125 | offsetof(CPU_DoubleU, l.upper)); | |
8911f501 | 126 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1])); |
77f193da BS |
127 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + |
128 | offsetof(CPU_DoubleU, l.lower)); | |
ff07ec83 BS |
129 | } |
130 | ||
131 | static void gen_op_load_fpr_DT1(unsigned int src) | |
132 | { | |
8911f501 | 133 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
77f193da BS |
134 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + |
135 | offsetof(CPU_DoubleU, l.upper)); | |
8911f501 | 136 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1])); |
77f193da BS |
137 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + |
138 | offsetof(CPU_DoubleU, l.lower)); | |
ff07ec83 BS |
139 | } |
140 | ||
141 | static void gen_op_store_DT0_fpr(unsigned int dst) | |
142 | { | |
77f193da BS |
143 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + |
144 | offsetof(CPU_DoubleU, l.upper)); | |
8911f501 | 145 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst])); |
77f193da BS |
146 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + |
147 | offsetof(CPU_DoubleU, l.lower)); | |
8911f501 | 148 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1])); |
ff07ec83 BS |
149 | } |
150 | ||
ff07ec83 BS |
151 | static void gen_op_load_fpr_QT0(unsigned int src) |
152 | { | |
8911f501 | 153 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
77f193da BS |
154 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
155 | offsetof(CPU_QuadU, l.upmost)); | |
8911f501 | 156 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1])); |
77f193da BS |
157 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
158 | offsetof(CPU_QuadU, l.upper)); | |
8911f501 | 159 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2])); |
77f193da BS |
160 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
161 | offsetof(CPU_QuadU, l.lower)); | |
8911f501 | 162 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3])); |
77f193da BS |
163 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
164 | offsetof(CPU_QuadU, l.lowest)); | |
ff07ec83 BS |
165 | } |
166 | ||
167 | static void gen_op_load_fpr_QT1(unsigned int src) | |
168 | { | |
8911f501 | 169 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
77f193da BS |
170 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + |
171 | offsetof(CPU_QuadU, l.upmost)); | |
8911f501 | 172 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1])); |
77f193da BS |
173 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + |
174 | offsetof(CPU_QuadU, l.upper)); | |
8911f501 | 175 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2])); |
77f193da BS |
176 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + |
177 | offsetof(CPU_QuadU, l.lower)); | |
8911f501 | 178 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3])); |
77f193da BS |
179 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + |
180 | offsetof(CPU_QuadU, l.lowest)); | |
ff07ec83 BS |
181 | } |
182 | ||
183 | static void gen_op_store_QT0_fpr(unsigned int dst) | |
184 | { | |
77f193da BS |
185 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
186 | offsetof(CPU_QuadU, l.upmost)); | |
8911f501 | 187 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst])); |
77f193da BS |
188 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
189 | offsetof(CPU_QuadU, l.upper)); | |
8911f501 | 190 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1])); |
77f193da BS |
191 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
192 | offsetof(CPU_QuadU, l.lower)); | |
8911f501 | 193 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2])); |
77f193da BS |
194 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
195 | offsetof(CPU_QuadU, l.lowest)); | |
8911f501 | 196 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3])); |
ff07ec83 | 197 | } |
1f587329 | 198 | |
81ad8ba2 BS |
199 | /* moves */ |
200 | #ifdef CONFIG_USER_ONLY | |
3475187d | 201 | #define supervisor(dc) 0 |
81ad8ba2 | 202 | #ifdef TARGET_SPARC64 |
e9ebed4d | 203 | #define hypervisor(dc) 0 |
81ad8ba2 | 204 | #endif |
3475187d | 205 | #else |
6f27aba6 | 206 | #define supervisor(dc) (dc->mem_idx >= 1) |
81ad8ba2 BS |
207 | #ifdef TARGET_SPARC64 |
208 | #define hypervisor(dc) (dc->mem_idx == 2) | |
6f27aba6 | 209 | #else |
3475187d | 210 | #endif |
81ad8ba2 BS |
211 | #endif |
212 | ||
2cade6a3 BS |
213 | #ifdef TARGET_SPARC64 |
214 | #ifndef TARGET_ABI32 | |
215 | #define AM_CHECK(dc) ((dc)->address_mask_32bit) | |
1a2fb1c0 | 216 | #else |
2cade6a3 BS |
217 | #define AM_CHECK(dc) (1) |
218 | #endif | |
1a2fb1c0 | 219 | #endif |
3391c818 | 220 | |
2cade6a3 BS |
221 | static inline void gen_address_mask(DisasContext *dc, TCGv addr) |
222 | { | |
223 | #ifdef TARGET_SPARC64 | |
224 | if (AM_CHECK(dc)) | |
225 | tcg_gen_andi_tl(addr, addr, 0xffffffffULL); | |
226 | #endif | |
227 | } | |
228 | ||
1a2fb1c0 | 229 | static inline void gen_movl_reg_TN(int reg, TCGv tn) |
81ad8ba2 | 230 | { |
1a2fb1c0 BS |
231 | if (reg == 0) |
232 | tcg_gen_movi_tl(tn, 0); | |
233 | else if (reg < 8) | |
f5069b26 | 234 | tcg_gen_mov_tl(tn, cpu_gregs[reg]); |
1a2fb1c0 | 235 | else { |
1a2fb1c0 | 236 | tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
81ad8ba2 BS |
237 | } |
238 | } | |
239 | ||
1a2fb1c0 | 240 | static inline void gen_movl_TN_reg(int reg, TCGv tn) |
81ad8ba2 | 241 | { |
1a2fb1c0 BS |
242 | if (reg == 0) |
243 | return; | |
244 | else if (reg < 8) | |
f5069b26 | 245 | tcg_gen_mov_tl(cpu_gregs[reg], tn); |
1a2fb1c0 | 246 | else { |
1a2fb1c0 | 247 | tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
81ad8ba2 BS |
248 | } |
249 | } | |
250 | ||
5fafdf24 | 251 | static inline void gen_goto_tb(DisasContext *s, int tb_num, |
6e256c93 FB |
252 | target_ulong pc, target_ulong npc) |
253 | { | |
254 | TranslationBlock *tb; | |
255 | ||
256 | tb = s->tb; | |
257 | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) && | |
258 | (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) { | |
259 | /* jump to same page: we can use a direct jump */ | |
57fec1fe | 260 | tcg_gen_goto_tb(tb_num); |
2f5680ee BS |
261 | tcg_gen_movi_tl(cpu_pc, pc); |
262 | tcg_gen_movi_tl(cpu_npc, npc); | |
57fec1fe | 263 | tcg_gen_exit_tb((long)tb + tb_num); |
6e256c93 FB |
264 | } else { |
265 | /* jump to another page: currently not optimized */ | |
2f5680ee BS |
266 | tcg_gen_movi_tl(cpu_pc, pc); |
267 | tcg_gen_movi_tl(cpu_npc, npc); | |
57fec1fe | 268 | tcg_gen_exit_tb(0); |
6e256c93 FB |
269 | } |
270 | } | |
271 | ||
19f329ad BS |
272 | // XXX suboptimal |
273 | static inline void gen_mov_reg_N(TCGv reg, TCGv src) | |
274 | { | |
8911f501 | 275 | tcg_gen_extu_i32_tl(reg, src); |
4b8b8b76 | 276 | tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT); |
19f329ad BS |
277 | tcg_gen_andi_tl(reg, reg, 0x1); |
278 | } | |
279 | ||
280 | static inline void gen_mov_reg_Z(TCGv reg, TCGv src) | |
281 | { | |
8911f501 | 282 | tcg_gen_extu_i32_tl(reg, src); |
4b8b8b76 | 283 | tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT); |
19f329ad BS |
284 | tcg_gen_andi_tl(reg, reg, 0x1); |
285 | } | |
286 | ||
287 | static inline void gen_mov_reg_V(TCGv reg, TCGv src) | |
288 | { | |
8911f501 | 289 | tcg_gen_extu_i32_tl(reg, src); |
4b8b8b76 | 290 | tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT); |
19f329ad BS |
291 | tcg_gen_andi_tl(reg, reg, 0x1); |
292 | } | |
293 | ||
294 | static inline void gen_mov_reg_C(TCGv reg, TCGv src) | |
295 | { | |
8911f501 | 296 | tcg_gen_extu_i32_tl(reg, src); |
4b8b8b76 | 297 | tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT); |
19f329ad BS |
298 | tcg_gen_andi_tl(reg, reg, 0x1); |
299 | } | |
300 | ||
ce5b3c3d | 301 | static inline void gen_cc_clear_icc(void) |
dc99a3f2 BS |
302 | { |
303 | tcg_gen_movi_i32(cpu_psr, 0); | |
ce5b3c3d BS |
304 | } |
305 | ||
dc99a3f2 | 306 | #ifdef TARGET_SPARC64 |
ce5b3c3d BS |
307 | static inline void gen_cc_clear_xcc(void) |
308 | { | |
dc99a3f2 | 309 | tcg_gen_movi_i32(cpu_xcc, 0); |
dc99a3f2 | 310 | } |
ce5b3c3d | 311 | #endif |
dc99a3f2 BS |
312 | |
313 | /* old op: | |
314 | if (!T0) | |
315 | env->psr |= PSR_ZERO; | |
316 | if ((int32_t) T0 < 0) | |
317 | env->psr |= PSR_NEG; | |
318 | */ | |
ce5b3c3d | 319 | static inline void gen_cc_NZ_icc(TCGv dst) |
dc99a3f2 | 320 | { |
8911f501 | 321 | TCGv r_temp; |
dc99a3f2 | 322 | int l1, l2; |
dc99a3f2 BS |
323 | |
324 | l1 = gen_new_label(); | |
325 | l2 = gen_new_label(); | |
8911f501 BS |
326 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
327 | tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL); | |
cb63669a | 328 | tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1); |
dc99a3f2 BS |
329 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO); |
330 | gen_set_label(l1); | |
bdf46ea2 | 331 | tcg_gen_ext_i32_tl(r_temp, dst); |
cb63669a | 332 | tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2); |
dc99a3f2 BS |
333 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG); |
334 | gen_set_label(l2); | |
2ea815ca | 335 | tcg_temp_free(r_temp); |
ce5b3c3d BS |
336 | } |
337 | ||
dc99a3f2 | 338 | #ifdef TARGET_SPARC64 |
ce5b3c3d BS |
339 | static inline void gen_cc_NZ_xcc(TCGv dst) |
340 | { | |
341 | int l1, l2; | |
342 | ||
343 | l1 = gen_new_label(); | |
344 | l2 = gen_new_label(); | |
cb63669a | 345 | tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1); |
ce5b3c3d BS |
346 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO); |
347 | gen_set_label(l1); | |
cb63669a | 348 | tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2); |
ce5b3c3d BS |
349 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG); |
350 | gen_set_label(l2); | |
dc99a3f2 | 351 | } |
ce5b3c3d | 352 | #endif |
dc99a3f2 BS |
353 | |
354 | /* old op: | |
355 | if (T0 < src1) | |
356 | env->psr |= PSR_CARRY; | |
357 | */ | |
ce5b3c3d | 358 | static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1) |
dc99a3f2 | 359 | { |
2ae72bce | 360 | TCGv r_temp1, r_temp2; |
dc99a3f2 BS |
361 | int l1; |
362 | ||
363 | l1 = gen_new_label(); | |
2ae72bce BS |
364 | r_temp1 = tcg_temp_new(TCG_TYPE_TL); |
365 | r_temp2 = tcg_temp_new(TCG_TYPE_TL); | |
366 | tcg_gen_andi_tl(r_temp1, dst, 0xffffffffULL); | |
367 | tcg_gen_andi_tl(r_temp2, src1, 0xffffffffULL); | |
368 | tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1); | |
dc99a3f2 BS |
369 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
370 | gen_set_label(l1); | |
2ae72bce BS |
371 | tcg_temp_free(r_temp1); |
372 | tcg_temp_free(r_temp2); | |
ce5b3c3d BS |
373 | } |
374 | ||
dc99a3f2 | 375 | #ifdef TARGET_SPARC64 |
ce5b3c3d BS |
376 | static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1) |
377 | { | |
378 | int l1; | |
dc99a3f2 | 379 | |
ce5b3c3d BS |
380 | l1 = gen_new_label(); |
381 | tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1); | |
382 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); | |
383 | gen_set_label(l1); | |
dc99a3f2 | 384 | } |
ce5b3c3d | 385 | #endif |
dc99a3f2 BS |
386 | |
387 | /* old op: | |
388 | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31)) | |
389 | env->psr |= PSR_OVF; | |
390 | */ | |
ce5b3c3d | 391 | static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 392 | { |
0425bee5 | 393 | TCGv r_temp; |
dc99a3f2 BS |
394 | |
395 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
dc99a3f2 BS |
396 | tcg_gen_xor_tl(r_temp, src1, src2); |
397 | tcg_gen_xori_tl(r_temp, r_temp, -1); | |
0425bee5 BS |
398 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
399 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
dd5e6304 | 400 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
653ccb80 BS |
401 | tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT); |
402 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); | |
2ea815ca | 403 | tcg_temp_free(r_temp); |
653ccb80 | 404 | tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32); |
ce5b3c3d BS |
405 | } |
406 | ||
dc99a3f2 | 407 | #ifdef TARGET_SPARC64 |
ce5b3c3d BS |
408 | static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2) |
409 | { | |
410 | TCGv r_temp; | |
ce5b3c3d BS |
411 | |
412 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
413 | tcg_gen_xor_tl(r_temp, src1, src2); | |
414 | tcg_gen_xori_tl(r_temp, r_temp, -1); | |
415 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); | |
416 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
417 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | |
653ccb80 BS |
418 | tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT); |
419 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); | |
2ea815ca | 420 | tcg_temp_free(r_temp); |
653ccb80 | 421 | tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32); |
dc99a3f2 | 422 | } |
ce5b3c3d | 423 | #endif |
dc99a3f2 BS |
424 | |
425 | static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) | |
426 | { | |
2ea815ca | 427 | TCGv r_temp, r_const; |
dc99a3f2 BS |
428 | int l1; |
429 | ||
430 | l1 = gen_new_label(); | |
431 | ||
432 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
dc99a3f2 BS |
433 | tcg_gen_xor_tl(r_temp, src1, src2); |
434 | tcg_gen_xori_tl(r_temp, r_temp, -1); | |
0425bee5 BS |
435 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
436 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
dd5e6304 | 437 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
cb63669a | 438 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1); |
2ea815ca BS |
439 | r_const = tcg_const_i32(TT_TOVF); |
440 | tcg_gen_helper_0_1(raise_exception, r_const); | |
441 | tcg_temp_free(r_const); | |
dc99a3f2 | 442 | gen_set_label(l1); |
2ea815ca | 443 | tcg_temp_free(r_temp); |
dc99a3f2 BS |
444 | } |
445 | ||
446 | static inline void gen_cc_V_tag(TCGv src1, TCGv src2) | |
447 | { | |
448 | int l1; | |
dc99a3f2 BS |
449 | |
450 | l1 = gen_new_label(); | |
0425bee5 BS |
451 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
452 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3); | |
cb63669a | 453 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1); |
dc99a3f2 BS |
454 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
455 | gen_set_label(l1); | |
456 | } | |
457 | ||
458 | static inline void gen_tag_tv(TCGv src1, TCGv src2) | |
459 | { | |
460 | int l1; | |
2ea815ca | 461 | TCGv r_const; |
dc99a3f2 BS |
462 | |
463 | l1 = gen_new_label(); | |
0425bee5 BS |
464 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
465 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3); | |
cb63669a | 466 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1); |
2ea815ca BS |
467 | r_const = tcg_const_i32(TT_TOVF); |
468 | tcg_gen_helper_0_1(raise_exception, r_const); | |
469 | tcg_temp_free(r_const); | |
dc99a3f2 BS |
470 | gen_set_label(l1); |
471 | } | |
472 | ||
4af984a7 | 473 | static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 474 | { |
4af984a7 | 475 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 | 476 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
5c6a0628 | 477 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d | 478 | gen_cc_clear_icc(); |
ba28189b BS |
479 | gen_cc_NZ_icc(cpu_cc_dst); |
480 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); | |
481 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d BS |
482 | #ifdef TARGET_SPARC64 |
483 | gen_cc_clear_xcc(); | |
ba28189b BS |
484 | gen_cc_NZ_xcc(cpu_cc_dst); |
485 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); | |
486 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 487 | #endif |
5c6a0628 | 488 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
dc99a3f2 BS |
489 | } |
490 | ||
4af984a7 | 491 | static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 492 | { |
4af984a7 | 493 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 | 494 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
dc99a3f2 | 495 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
5c6a0628 | 496 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
ce5b3c3d | 497 | gen_cc_clear_icc(); |
5c6a0628 | 498 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
ce5b3c3d BS |
499 | #ifdef TARGET_SPARC64 |
500 | gen_cc_clear_xcc(); | |
5c6a0628 | 501 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); |
ce5b3c3d | 502 | #endif |
5c6a0628 | 503 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); |
ba28189b BS |
504 | gen_cc_NZ_icc(cpu_cc_dst); |
505 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); | |
506 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 507 | #ifdef TARGET_SPARC64 |
ba28189b BS |
508 | gen_cc_NZ_xcc(cpu_cc_dst); |
509 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); | |
510 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 511 | #endif |
5c6a0628 | 512 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
dc99a3f2 BS |
513 | } |
514 | ||
4af984a7 | 515 | static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 516 | { |
4af984a7 | 517 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 | 518 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
5c6a0628 | 519 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d | 520 | gen_cc_clear_icc(); |
ba28189b BS |
521 | gen_cc_NZ_icc(cpu_cc_dst); |
522 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); | |
523 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
6f551262 | 524 | gen_cc_V_tag(cpu_cc_src, cpu_cc_src2); |
ce5b3c3d BS |
525 | #ifdef TARGET_SPARC64 |
526 | gen_cc_clear_xcc(); | |
ba28189b BS |
527 | gen_cc_NZ_xcc(cpu_cc_dst); |
528 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); | |
529 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 530 | #endif |
5c6a0628 | 531 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
dc99a3f2 BS |
532 | } |
533 | ||
4af984a7 | 534 | static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 535 | { |
4af984a7 | 536 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 BS |
537 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
538 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); | |
5c6a0628 BS |
539 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
540 | gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 541 | gen_cc_clear_icc(); |
ba28189b BS |
542 | gen_cc_NZ_icc(cpu_cc_dst); |
543 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); | |
ce5b3c3d BS |
544 | #ifdef TARGET_SPARC64 |
545 | gen_cc_clear_xcc(); | |
ba28189b BS |
546 | gen_cc_NZ_xcc(cpu_cc_dst); |
547 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); | |
548 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 549 | #endif |
5c6a0628 | 550 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
dc99a3f2 BS |
551 | } |
552 | ||
553 | /* old op: | |
554 | if (src1 < T1) | |
555 | env->psr |= PSR_CARRY; | |
556 | */ | |
ce5b3c3d | 557 | static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2) |
dc99a3f2 | 558 | { |
8911f501 | 559 | TCGv r_temp1, r_temp2; |
dc99a3f2 BS |
560 | int l1; |
561 | ||
562 | l1 = gen_new_label(); | |
8911f501 BS |
563 | r_temp1 = tcg_temp_new(TCG_TYPE_TL); |
564 | r_temp2 = tcg_temp_new(TCG_TYPE_TL); | |
565 | tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL); | |
566 | tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL); | |
567 | tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1); | |
dc99a3f2 BS |
568 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
569 | gen_set_label(l1); | |
2ea815ca BS |
570 | tcg_temp_free(r_temp1); |
571 | tcg_temp_free(r_temp2); | |
ce5b3c3d BS |
572 | } |
573 | ||
dc99a3f2 | 574 | #ifdef TARGET_SPARC64 |
ce5b3c3d BS |
575 | static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2) |
576 | { | |
577 | int l1; | |
dc99a3f2 | 578 | |
ce5b3c3d BS |
579 | l1 = gen_new_label(); |
580 | tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1); | |
581 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); | |
582 | gen_set_label(l1); | |
dc99a3f2 | 583 | } |
ce5b3c3d | 584 | #endif |
dc99a3f2 BS |
585 | |
586 | /* old op: | |
587 | if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31)) | |
588 | env->psr |= PSR_OVF; | |
589 | */ | |
ce5b3c3d | 590 | static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 591 | { |
0425bee5 | 592 | TCGv r_temp; |
dc99a3f2 BS |
593 | |
594 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
dc99a3f2 | 595 | tcg_gen_xor_tl(r_temp, src1, src2); |
0425bee5 BS |
596 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
597 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
dd5e6304 | 598 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
653ccb80 BS |
599 | tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT); |
600 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); | |
601 | tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32); | |
2ea815ca | 602 | tcg_temp_free(r_temp); |
ce5b3c3d BS |
603 | } |
604 | ||
dc99a3f2 | 605 | #ifdef TARGET_SPARC64 |
ce5b3c3d BS |
606 | static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2) |
607 | { | |
608 | TCGv r_temp; | |
ce5b3c3d BS |
609 | |
610 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
611 | tcg_gen_xor_tl(r_temp, src1, src2); | |
612 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); | |
613 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
614 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | |
653ccb80 BS |
615 | tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT); |
616 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); | |
617 | tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32); | |
2ea815ca | 618 | tcg_temp_free(r_temp); |
dc99a3f2 | 619 | } |
ce5b3c3d | 620 | #endif |
dc99a3f2 BS |
621 | |
622 | static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) | |
623 | { | |
2ea815ca | 624 | TCGv r_temp, r_const; |
dc99a3f2 BS |
625 | int l1; |
626 | ||
627 | l1 = gen_new_label(); | |
628 | ||
629 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
dc99a3f2 | 630 | tcg_gen_xor_tl(r_temp, src1, src2); |
0425bee5 BS |
631 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
632 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
dd5e6304 | 633 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
cb63669a | 634 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1); |
2ea815ca BS |
635 | r_const = tcg_const_i32(TT_TOVF); |
636 | tcg_gen_helper_0_1(raise_exception, r_const); | |
637 | tcg_temp_free(r_const); | |
dc99a3f2 | 638 | gen_set_label(l1); |
2ea815ca | 639 | tcg_temp_free(r_temp); |
dc99a3f2 BS |
640 | } |
641 | ||
4af984a7 | 642 | static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 643 | { |
4af984a7 | 644 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 | 645 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
5c6a0628 | 646 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d | 647 | gen_cc_clear_icc(); |
ba28189b | 648 | gen_cc_NZ_icc(cpu_cc_dst); |
6f551262 | 649 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
ba28189b | 650 | gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d BS |
651 | #ifdef TARGET_SPARC64 |
652 | gen_cc_clear_xcc(); | |
ba28189b | 653 | gen_cc_NZ_xcc(cpu_cc_dst); |
6f551262 | 654 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
ba28189b | 655 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d | 656 | #endif |
5c6a0628 | 657 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
dc99a3f2 BS |
658 | } |
659 | ||
4af984a7 | 660 | static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 661 | { |
4af984a7 | 662 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 | 663 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
dc99a3f2 | 664 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
5c6a0628 | 665 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
ce5b3c3d | 666 | gen_cc_clear_icc(); |
5c6a0628 | 667 | gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); |
ce5b3c3d BS |
668 | #ifdef TARGET_SPARC64 |
669 | gen_cc_clear_xcc(); | |
5c6a0628 | 670 | gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); |
ce5b3c3d | 671 | #endif |
5c6a0628 | 672 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); |
ba28189b BS |
673 | gen_cc_NZ_icc(cpu_cc_dst); |
674 | gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); | |
675 | gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 676 | #ifdef TARGET_SPARC64 |
ba28189b BS |
677 | gen_cc_NZ_xcc(cpu_cc_dst); |
678 | gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); | |
679 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 680 | #endif |
5c6a0628 | 681 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
dc99a3f2 BS |
682 | } |
683 | ||
4af984a7 | 684 | static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 685 | { |
4af984a7 | 686 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 | 687 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
5c6a0628 | 688 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d | 689 | gen_cc_clear_icc(); |
ba28189b | 690 | gen_cc_NZ_icc(cpu_cc_dst); |
6f551262 | 691 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
ba28189b | 692 | gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
6f551262 | 693 | gen_cc_V_tag(cpu_cc_src, cpu_cc_src2); |
ce5b3c3d BS |
694 | #ifdef TARGET_SPARC64 |
695 | gen_cc_clear_xcc(); | |
ba28189b | 696 | gen_cc_NZ_xcc(cpu_cc_dst); |
6f551262 | 697 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
ba28189b | 698 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d | 699 | #endif |
5c6a0628 | 700 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
dc99a3f2 BS |
701 | } |
702 | ||
4af984a7 | 703 | static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 704 | { |
4af984a7 | 705 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 BS |
706 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
707 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); | |
5c6a0628 BS |
708 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
709 | gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 710 | gen_cc_clear_icc(); |
ba28189b | 711 | gen_cc_NZ_icc(cpu_cc_dst); |
6f551262 | 712 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
ce5b3c3d BS |
713 | #ifdef TARGET_SPARC64 |
714 | gen_cc_clear_xcc(); | |
ba28189b | 715 | gen_cc_NZ_xcc(cpu_cc_dst); |
6f551262 | 716 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
ba28189b | 717 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d | 718 | #endif |
5c6a0628 | 719 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
dc99a3f2 BS |
720 | } |
721 | ||
4af984a7 | 722 | static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) |
d9bdab86 | 723 | { |
105a1f04 | 724 | TCGv r_temp; |
6f551262 | 725 | int l1; |
d9bdab86 BS |
726 | |
727 | l1 = gen_new_label(); | |
d9bdab86 BS |
728 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
729 | ||
730 | /* old op: | |
731 | if (!(env->y & 1)) | |
732 | T1 = 0; | |
733 | */ | |
6f551262 | 734 | tcg_gen_mov_tl(cpu_cc_src, src1); |
255e1fcb | 735 | tcg_gen_andi_tl(r_temp, cpu_y, 0x1); |
4af984a7 | 736 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
105a1f04 | 737 | tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1); |
d9bdab86 | 738 | tcg_gen_movi_tl(cpu_cc_src2, 0); |
6f551262 | 739 | gen_set_label(l1); |
d9bdab86 BS |
740 | |
741 | // b2 = T0 & 1; | |
742 | // env->y = (b2 << 31) | (env->y >> 1); | |
105a1f04 BS |
743 | tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1); |
744 | tcg_gen_shli_tl(r_temp, r_temp, 31); | |
255e1fcb BS |
745 | tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1); |
746 | tcg_gen_or_tl(cpu_y, cpu_tmp0, r_temp); | |
d9bdab86 BS |
747 | |
748 | // b1 = N ^ V; | |
749 | gen_mov_reg_N(cpu_tmp0, cpu_psr); | |
750 | gen_mov_reg_V(r_temp, cpu_psr); | |
751 | tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp); | |
2ea815ca | 752 | tcg_temp_free(r_temp); |
d9bdab86 BS |
753 | |
754 | // T0 = (b1 << 31) | (T0 >> 1); | |
755 | // src1 = T0; | |
756 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31); | |
6f551262 | 757 | tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1); |
d9bdab86 BS |
758 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); |
759 | ||
760 | /* do addition and update flags */ | |
5c6a0628 | 761 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
d9bdab86 | 762 | |
ce5b3c3d | 763 | gen_cc_clear_icc(); |
ba28189b BS |
764 | gen_cc_NZ_icc(cpu_cc_dst); |
765 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
766 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); | |
5c6a0628 | 767 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
d9bdab86 BS |
768 | } |
769 | ||
4af984a7 | 770 | static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) |
8879d139 BS |
771 | { |
772 | TCGv r_temp, r_temp2; | |
773 | ||
774 | r_temp = tcg_temp_new(TCG_TYPE_I64); | |
775 | r_temp2 = tcg_temp_new(TCG_TYPE_I64); | |
776 | ||
b991c385 BS |
777 | tcg_gen_extu_i32_i64(r_temp, src2); |
778 | tcg_gen_extu_i32_i64(r_temp2, src1); | |
8879d139 BS |
779 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
780 | ||
781 | tcg_gen_shri_i64(r_temp, r_temp2, 32); | |
105a1f04 | 782 | tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); |
2ea815ca | 783 | tcg_temp_free(r_temp); |
255e1fcb | 784 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff); |
8879d139 | 785 | #ifdef TARGET_SPARC64 |
4af984a7 | 786 | tcg_gen_mov_i64(dst, r_temp2); |
8879d139 | 787 | #else |
4af984a7 | 788 | tcg_gen_trunc_i64_tl(dst, r_temp2); |
8879d139 | 789 | #endif |
2ea815ca | 790 | tcg_temp_free(r_temp2); |
8879d139 BS |
791 | } |
792 | ||
4af984a7 | 793 | static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) |
8879d139 BS |
794 | { |
795 | TCGv r_temp, r_temp2; | |
796 | ||
797 | r_temp = tcg_temp_new(TCG_TYPE_I64); | |
798 | r_temp2 = tcg_temp_new(TCG_TYPE_I64); | |
799 | ||
b991c385 BS |
800 | tcg_gen_ext_i32_i64(r_temp, src2); |
801 | tcg_gen_ext_i32_i64(r_temp2, src1); | |
8879d139 BS |
802 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
803 | ||
804 | tcg_gen_shri_i64(r_temp, r_temp2, 32); | |
105a1f04 | 805 | tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); |
2ea815ca | 806 | tcg_temp_free(r_temp); |
255e1fcb | 807 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff); |
8879d139 | 808 | #ifdef TARGET_SPARC64 |
4af984a7 | 809 | tcg_gen_mov_i64(dst, r_temp2); |
8879d139 | 810 | #else |
4af984a7 | 811 | tcg_gen_trunc_i64_tl(dst, r_temp2); |
8879d139 | 812 | #endif |
2ea815ca | 813 | tcg_temp_free(r_temp2); |
8879d139 BS |
814 | } |
815 | ||
1a7b60e7 | 816 | #ifdef TARGET_SPARC64 |
8911f501 | 817 | static inline void gen_trap_ifdivzero_tl(TCGv divisor) |
1a7b60e7 | 818 | { |
2ea815ca | 819 | TCGv r_const; |
1a7b60e7 BS |
820 | int l1; |
821 | ||
822 | l1 = gen_new_label(); | |
cb63669a | 823 | tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1); |
2ea815ca BS |
824 | r_const = tcg_const_i32(TT_DIV_ZERO); |
825 | tcg_gen_helper_0_1(raise_exception, r_const); | |
826 | tcg_temp_free(r_const); | |
1a7b60e7 BS |
827 | gen_set_label(l1); |
828 | } | |
829 | ||
4af984a7 | 830 | static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2) |
1a7b60e7 BS |
831 | { |
832 | int l1, l2; | |
833 | ||
834 | l1 = gen_new_label(); | |
835 | l2 = gen_new_label(); | |
6f551262 BS |
836 | tcg_gen_mov_tl(cpu_cc_src, src1); |
837 | tcg_gen_mov_tl(cpu_cc_src2, src2); | |
5c6a0628 | 838 | gen_trap_ifdivzero_tl(cpu_cc_src2); |
cb63669a PB |
839 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1); |
840 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1); | |
4af984a7 | 841 | tcg_gen_movi_i64(dst, INT64_MIN); |
06b3e1b3 | 842 | tcg_gen_br(l2); |
1a7b60e7 | 843 | gen_set_label(l1); |
6f551262 | 844 | tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2); |
1a7b60e7 BS |
845 | gen_set_label(l2); |
846 | } | |
847 | #endif | |
848 | ||
4af984a7 | 849 | static inline void gen_op_div_cc(TCGv dst) |
dc99a3f2 BS |
850 | { |
851 | int l1; | |
dc99a3f2 | 852 | |
ba28189b | 853 | tcg_gen_mov_tl(cpu_cc_dst, dst); |
ce5b3c3d | 854 | gen_cc_clear_icc(); |
ba28189b | 855 | gen_cc_NZ_icc(cpu_cc_dst); |
dc99a3f2 | 856 | l1 = gen_new_label(); |
5c6a0628 | 857 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1); |
dc99a3f2 BS |
858 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
859 | gen_set_label(l1); | |
860 | } | |
861 | ||
4af984a7 | 862 | static inline void gen_op_logic_cc(TCGv dst) |
dc99a3f2 | 863 | { |
ba28189b BS |
864 | tcg_gen_mov_tl(cpu_cc_dst, dst); |
865 | ||
ce5b3c3d | 866 | gen_cc_clear_icc(); |
ba28189b | 867 | gen_cc_NZ_icc(cpu_cc_dst); |
ce5b3c3d BS |
868 | #ifdef TARGET_SPARC64 |
869 | gen_cc_clear_xcc(); | |
ba28189b | 870 | gen_cc_NZ_xcc(cpu_cc_dst); |
ce5b3c3d | 871 | #endif |
dc99a3f2 BS |
872 | } |
873 | ||
19f329ad BS |
874 | // 1 |
875 | static inline void gen_op_eval_ba(TCGv dst) | |
876 | { | |
877 | tcg_gen_movi_tl(dst, 1); | |
878 | } | |
879 | ||
880 | // Z | |
881 | static inline void gen_op_eval_be(TCGv dst, TCGv src) | |
882 | { | |
883 | gen_mov_reg_Z(dst, src); | |
884 | } | |
885 | ||
886 | // Z | (N ^ V) | |
887 | static inline void gen_op_eval_ble(TCGv dst, TCGv src) | |
888 | { | |
0425bee5 | 889 | gen_mov_reg_N(cpu_tmp0, src); |
19f329ad | 890 | gen_mov_reg_V(dst, src); |
0425bee5 BS |
891 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
892 | gen_mov_reg_Z(cpu_tmp0, src); | |
893 | tcg_gen_or_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
894 | } |
895 | ||
896 | // N ^ V | |
897 | static inline void gen_op_eval_bl(TCGv dst, TCGv src) | |
898 | { | |
0425bee5 | 899 | gen_mov_reg_V(cpu_tmp0, src); |
19f329ad | 900 | gen_mov_reg_N(dst, src); |
0425bee5 | 901 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
19f329ad BS |
902 | } |
903 | ||
904 | // C | Z | |
905 | static inline void gen_op_eval_bleu(TCGv dst, TCGv src) | |
906 | { | |
0425bee5 | 907 | gen_mov_reg_Z(cpu_tmp0, src); |
19f329ad | 908 | gen_mov_reg_C(dst, src); |
0425bee5 | 909 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
19f329ad BS |
910 | } |
911 | ||
912 | // C | |
913 | static inline void gen_op_eval_bcs(TCGv dst, TCGv src) | |
914 | { | |
915 | gen_mov_reg_C(dst, src); | |
916 | } | |
917 | ||
918 | // V | |
919 | static inline void gen_op_eval_bvs(TCGv dst, TCGv src) | |
920 | { | |
921 | gen_mov_reg_V(dst, src); | |
922 | } | |
923 | ||
924 | // 0 | |
925 | static inline void gen_op_eval_bn(TCGv dst) | |
926 | { | |
927 | tcg_gen_movi_tl(dst, 0); | |
928 | } | |
929 | ||
930 | // N | |
931 | static inline void gen_op_eval_bneg(TCGv dst, TCGv src) | |
932 | { | |
933 | gen_mov_reg_N(dst, src); | |
934 | } | |
935 | ||
936 | // !Z | |
937 | static inline void gen_op_eval_bne(TCGv dst, TCGv src) | |
938 | { | |
939 | gen_mov_reg_Z(dst, src); | |
940 | tcg_gen_xori_tl(dst, dst, 0x1); | |
941 | } | |
942 | ||
943 | // !(Z | (N ^ V)) | |
944 | static inline void gen_op_eval_bg(TCGv dst, TCGv src) | |
945 | { | |
0425bee5 | 946 | gen_mov_reg_N(cpu_tmp0, src); |
19f329ad | 947 | gen_mov_reg_V(dst, src); |
0425bee5 BS |
948 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
949 | gen_mov_reg_Z(cpu_tmp0, src); | |
950 | tcg_gen_or_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
951 | tcg_gen_xori_tl(dst, dst, 0x1); |
952 | } | |
953 | ||
954 | // !(N ^ V) | |
955 | static inline void gen_op_eval_bge(TCGv dst, TCGv src) | |
956 | { | |
0425bee5 | 957 | gen_mov_reg_V(cpu_tmp0, src); |
19f329ad | 958 | gen_mov_reg_N(dst, src); |
0425bee5 | 959 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
19f329ad BS |
960 | tcg_gen_xori_tl(dst, dst, 0x1); |
961 | } | |
962 | ||
963 | // !(C | Z) | |
964 | static inline void gen_op_eval_bgu(TCGv dst, TCGv src) | |
965 | { | |
0425bee5 | 966 | gen_mov_reg_Z(cpu_tmp0, src); |
19f329ad | 967 | gen_mov_reg_C(dst, src); |
0425bee5 | 968 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
19f329ad BS |
969 | tcg_gen_xori_tl(dst, dst, 0x1); |
970 | } | |
971 | ||
972 | // !C | |
973 | static inline void gen_op_eval_bcc(TCGv dst, TCGv src) | |
974 | { | |
975 | gen_mov_reg_C(dst, src); | |
976 | tcg_gen_xori_tl(dst, dst, 0x1); | |
977 | } | |
978 | ||
979 | // !N | |
980 | static inline void gen_op_eval_bpos(TCGv dst, TCGv src) | |
981 | { | |
982 | gen_mov_reg_N(dst, src); | |
983 | tcg_gen_xori_tl(dst, dst, 0x1); | |
984 | } | |
985 | ||
986 | // !V | |
987 | static inline void gen_op_eval_bvc(TCGv dst, TCGv src) | |
988 | { | |
989 | gen_mov_reg_V(dst, src); | |
990 | tcg_gen_xori_tl(dst, dst, 0x1); | |
991 | } | |
992 | ||
993 | /* | |
994 | FPSR bit field FCC1 | FCC0: | |
995 | 0 = | |
996 | 1 < | |
997 | 2 > | |
998 | 3 unordered | |
999 | */ | |
1000 | static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, | |
1001 | unsigned int fcc_offset) | |
1002 | { | |
ba6a9d8c | 1003 | tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset); |
19f329ad BS |
1004 | tcg_gen_andi_tl(reg, reg, 0x1); |
1005 | } | |
1006 | ||
1007 | static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, | |
1008 | unsigned int fcc_offset) | |
1009 | { | |
ba6a9d8c | 1010 | tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset); |
19f329ad BS |
1011 | tcg_gen_andi_tl(reg, reg, 0x1); |
1012 | } | |
1013 | ||
1014 | // !0: FCC0 | FCC1 | |
1015 | static inline void gen_op_eval_fbne(TCGv dst, TCGv src, | |
1016 | unsigned int fcc_offset) | |
1017 | { | |
19f329ad | 1018 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1019 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1020 | tcg_gen_or_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1021 | } |
1022 | ||
1023 | // 1 or 2: FCC0 ^ FCC1 | |
1024 | static inline void gen_op_eval_fblg(TCGv dst, TCGv src, | |
1025 | unsigned int fcc_offset) | |
1026 | { | |
19f329ad | 1027 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1028 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1029 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1030 | } |
1031 | ||
1032 | // 1 or 3: FCC0 | |
1033 | static inline void gen_op_eval_fbul(TCGv dst, TCGv src, | |
1034 | unsigned int fcc_offset) | |
1035 | { | |
1036 | gen_mov_reg_FCC0(dst, src, fcc_offset); | |
1037 | } | |
1038 | ||
1039 | // 1: FCC0 & !FCC1 | |
1040 | static inline void gen_op_eval_fbl(TCGv dst, TCGv src, | |
1041 | unsigned int fcc_offset) | |
1042 | { | |
19f329ad | 1043 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1044 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1045 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1); | |
1046 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1047 | } |
1048 | ||
1049 | // 2 or 3: FCC1 | |
1050 | static inline void gen_op_eval_fbug(TCGv dst, TCGv src, | |
1051 | unsigned int fcc_offset) | |
1052 | { | |
1053 | gen_mov_reg_FCC1(dst, src, fcc_offset); | |
1054 | } | |
1055 | ||
1056 | // 2: !FCC0 & FCC1 | |
1057 | static inline void gen_op_eval_fbg(TCGv dst, TCGv src, | |
1058 | unsigned int fcc_offset) | |
1059 | { | |
19f329ad BS |
1060 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1061 | tcg_gen_xori_tl(dst, dst, 0x1); | |
0425bee5 BS |
1062 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1063 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1064 | } |
1065 | ||
1066 | // 3: FCC0 & FCC1 | |
1067 | static inline void gen_op_eval_fbu(TCGv dst, TCGv src, | |
1068 | unsigned int fcc_offset) | |
1069 | { | |
19f329ad | 1070 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1071 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1072 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1073 | } |
1074 | ||
1075 | // 0: !(FCC0 | FCC1) | |
1076 | static inline void gen_op_eval_fbe(TCGv dst, TCGv src, | |
1077 | unsigned int fcc_offset) | |
1078 | { | |
19f329ad | 1079 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1080 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1081 | tcg_gen_or_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1082 | tcg_gen_xori_tl(dst, dst, 0x1); |
1083 | } | |
1084 | ||
1085 | // 0 or 3: !(FCC0 ^ FCC1) | |
1086 | static inline void gen_op_eval_fbue(TCGv dst, TCGv src, | |
1087 | unsigned int fcc_offset) | |
1088 | { | |
19f329ad | 1089 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1090 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1091 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1092 | tcg_gen_xori_tl(dst, dst, 0x1); |
1093 | } | |
1094 | ||
1095 | // 0 or 2: !FCC0 | |
1096 | static inline void gen_op_eval_fbge(TCGv dst, TCGv src, | |
1097 | unsigned int fcc_offset) | |
1098 | { | |
1099 | gen_mov_reg_FCC0(dst, src, fcc_offset); | |
1100 | tcg_gen_xori_tl(dst, dst, 0x1); | |
1101 | } | |
1102 | ||
1103 | // !1: !(FCC0 & !FCC1) | |
1104 | static inline void gen_op_eval_fbuge(TCGv dst, TCGv src, | |
1105 | unsigned int fcc_offset) | |
1106 | { | |
19f329ad | 1107 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1108 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1109 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1); | |
1110 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1111 | tcg_gen_xori_tl(dst, dst, 0x1); |
1112 | } | |
1113 | ||
1114 | // 0 or 1: !FCC1 | |
1115 | static inline void gen_op_eval_fble(TCGv dst, TCGv src, | |
1116 | unsigned int fcc_offset) | |
1117 | { | |
1118 | gen_mov_reg_FCC1(dst, src, fcc_offset); | |
1119 | tcg_gen_xori_tl(dst, dst, 0x1); | |
1120 | } | |
1121 | ||
1122 | // !2: !(!FCC0 & FCC1) | |
1123 | static inline void gen_op_eval_fbule(TCGv dst, TCGv src, | |
1124 | unsigned int fcc_offset) | |
1125 | { | |
19f329ad BS |
1126 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1127 | tcg_gen_xori_tl(dst, dst, 0x1); | |
0425bee5 BS |
1128 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1129 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1130 | tcg_gen_xori_tl(dst, dst, 0x1); |
1131 | } | |
1132 | ||
1133 | // !3: !(FCC0 & FCC1) | |
1134 | static inline void gen_op_eval_fbo(TCGv dst, TCGv src, | |
1135 | unsigned int fcc_offset) | |
1136 | { | |
19f329ad | 1137 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1138 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1139 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1140 | tcg_gen_xori_tl(dst, dst, 0x1); |
1141 | } | |
1142 | ||
46525e1f | 1143 | static inline void gen_branch2(DisasContext *dc, target_ulong pc1, |
19f329ad | 1144 | target_ulong pc2, TCGv r_cond) |
83469015 FB |
1145 | { |
1146 | int l1; | |
1147 | ||
1148 | l1 = gen_new_label(); | |
1149 | ||
cb63669a | 1150 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1); |
83469015 | 1151 | |
6e256c93 | 1152 | gen_goto_tb(dc, 0, pc1, pc1 + 4); |
83469015 FB |
1153 | |
1154 | gen_set_label(l1); | |
6e256c93 | 1155 | gen_goto_tb(dc, 1, pc2, pc2 + 4); |
83469015 FB |
1156 | } |
1157 | ||
46525e1f | 1158 | static inline void gen_branch_a(DisasContext *dc, target_ulong pc1, |
19f329ad | 1159 | target_ulong pc2, TCGv r_cond) |
83469015 FB |
1160 | { |
1161 | int l1; | |
1162 | ||
1163 | l1 = gen_new_label(); | |
1164 | ||
cb63669a | 1165 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1); |
83469015 | 1166 | |
6e256c93 | 1167 | gen_goto_tb(dc, 0, pc2, pc1); |
83469015 FB |
1168 | |
1169 | gen_set_label(l1); | |
6e256c93 | 1170 | gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8); |
83469015 FB |
1171 | } |
1172 | ||
19f329ad BS |
1173 | static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2, |
1174 | TCGv r_cond) | |
83469015 FB |
1175 | { |
1176 | int l1, l2; | |
1177 | ||
1178 | l1 = gen_new_label(); | |
1179 | l2 = gen_new_label(); | |
19f329ad | 1180 | |
cb63669a | 1181 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1); |
83469015 | 1182 | |
2f5680ee | 1183 | tcg_gen_movi_tl(cpu_npc, npc1); |
06b3e1b3 | 1184 | tcg_gen_br(l2); |
83469015 FB |
1185 | |
1186 | gen_set_label(l1); | |
2f5680ee | 1187 | tcg_gen_movi_tl(cpu_npc, npc2); |
83469015 FB |
1188 | gen_set_label(l2); |
1189 | } | |
1190 | ||
4af984a7 BS |
1191 | /* call this function before using the condition register as it may |
1192 | have been set for a jump */ | |
1193 | static inline void flush_cond(DisasContext *dc, TCGv cond) | |
83469015 FB |
1194 | { |
1195 | if (dc->npc == JUMP_PC) { | |
4af984a7 | 1196 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
83469015 FB |
1197 | dc->npc = DYNAMIC_PC; |
1198 | } | |
1199 | } | |
1200 | ||
4af984a7 | 1201 | static inline void save_npc(DisasContext *dc, TCGv cond) |
72cbca10 FB |
1202 | { |
1203 | if (dc->npc == JUMP_PC) { | |
4af984a7 | 1204 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
72cbca10 FB |
1205 | dc->npc = DYNAMIC_PC; |
1206 | } else if (dc->npc != DYNAMIC_PC) { | |
2f5680ee | 1207 | tcg_gen_movi_tl(cpu_npc, dc->npc); |
72cbca10 FB |
1208 | } |
1209 | } | |
1210 | ||
4af984a7 | 1211 | static inline void save_state(DisasContext *dc, TCGv cond) |
72cbca10 | 1212 | { |
2f5680ee | 1213 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
4af984a7 | 1214 | save_npc(dc, cond); |
72cbca10 FB |
1215 | } |
1216 | ||
4af984a7 | 1217 | static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond) |
0bee699e FB |
1218 | { |
1219 | if (dc->npc == JUMP_PC) { | |
4af984a7 | 1220 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
48d5c82b | 1221 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
0bee699e FB |
1222 | dc->pc = DYNAMIC_PC; |
1223 | } else if (dc->npc == DYNAMIC_PC) { | |
48d5c82b | 1224 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
0bee699e FB |
1225 | dc->pc = DYNAMIC_PC; |
1226 | } else { | |
1227 | dc->pc = dc->npc; | |
1228 | } | |
1229 | } | |
1230 | ||
38bc628b BS |
1231 | static inline void gen_op_next_insn(void) |
1232 | { | |
48d5c82b BS |
1233 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1234 | tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); | |
38bc628b BS |
1235 | } |
1236 | ||
19f329ad BS |
1237 | static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond) |
1238 | { | |
1239 | TCGv r_src; | |
3475187d | 1240 | |
3475187d | 1241 | #ifdef TARGET_SPARC64 |
19f329ad | 1242 | if (cc) |
dc99a3f2 | 1243 | r_src = cpu_xcc; |
19f329ad | 1244 | else |
dc99a3f2 | 1245 | r_src = cpu_psr; |
3475187d | 1246 | #else |
dc99a3f2 | 1247 | r_src = cpu_psr; |
3475187d | 1248 | #endif |
19f329ad BS |
1249 | switch (cond) { |
1250 | case 0x0: | |
1251 | gen_op_eval_bn(r_dst); | |
1252 | break; | |
1253 | case 0x1: | |
1254 | gen_op_eval_be(r_dst, r_src); | |
1255 | break; | |
1256 | case 0x2: | |
1257 | gen_op_eval_ble(r_dst, r_src); | |
1258 | break; | |
1259 | case 0x3: | |
1260 | gen_op_eval_bl(r_dst, r_src); | |
1261 | break; | |
1262 | case 0x4: | |
1263 | gen_op_eval_bleu(r_dst, r_src); | |
1264 | break; | |
1265 | case 0x5: | |
1266 | gen_op_eval_bcs(r_dst, r_src); | |
1267 | break; | |
1268 | case 0x6: | |
1269 | gen_op_eval_bneg(r_dst, r_src); | |
1270 | break; | |
1271 | case 0x7: | |
1272 | gen_op_eval_bvs(r_dst, r_src); | |
1273 | break; | |
1274 | case 0x8: | |
1275 | gen_op_eval_ba(r_dst); | |
1276 | break; | |
1277 | case 0x9: | |
1278 | gen_op_eval_bne(r_dst, r_src); | |
1279 | break; | |
1280 | case 0xa: | |
1281 | gen_op_eval_bg(r_dst, r_src); | |
1282 | break; | |
1283 | case 0xb: | |
1284 | gen_op_eval_bge(r_dst, r_src); | |
1285 | break; | |
1286 | case 0xc: | |
1287 | gen_op_eval_bgu(r_dst, r_src); | |
1288 | break; | |
1289 | case 0xd: | |
1290 | gen_op_eval_bcc(r_dst, r_src); | |
1291 | break; | |
1292 | case 0xe: | |
1293 | gen_op_eval_bpos(r_dst, r_src); | |
1294 | break; | |
1295 | case 0xf: | |
1296 | gen_op_eval_bvc(r_dst, r_src); | |
1297 | break; | |
1298 | } | |
1299 | } | |
7a3f1944 | 1300 | |
19f329ad | 1301 | static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) |
e8af50a3 | 1302 | { |
19f329ad BS |
1303 | unsigned int offset; |
1304 | ||
19f329ad BS |
1305 | switch (cc) { |
1306 | default: | |
1307 | case 0x0: | |
1308 | offset = 0; | |
1309 | break; | |
1310 | case 0x1: | |
1311 | offset = 32 - 10; | |
1312 | break; | |
1313 | case 0x2: | |
1314 | offset = 34 - 10; | |
1315 | break; | |
1316 | case 0x3: | |
1317 | offset = 36 - 10; | |
1318 | break; | |
1319 | } | |
1320 | ||
1321 | switch (cond) { | |
1322 | case 0x0: | |
1323 | gen_op_eval_bn(r_dst); | |
1324 | break; | |
1325 | case 0x1: | |
87e92502 | 1326 | gen_op_eval_fbne(r_dst, cpu_fsr, offset); |
19f329ad BS |
1327 | break; |
1328 | case 0x2: | |
87e92502 | 1329 | gen_op_eval_fblg(r_dst, cpu_fsr, offset); |
19f329ad BS |
1330 | break; |
1331 | case 0x3: | |
87e92502 | 1332 | gen_op_eval_fbul(r_dst, cpu_fsr, offset); |
19f329ad BS |
1333 | break; |
1334 | case 0x4: | |
87e92502 | 1335 | gen_op_eval_fbl(r_dst, cpu_fsr, offset); |
19f329ad BS |
1336 | break; |
1337 | case 0x5: | |
87e92502 | 1338 | gen_op_eval_fbug(r_dst, cpu_fsr, offset); |
19f329ad BS |
1339 | break; |
1340 | case 0x6: | |
87e92502 | 1341 | gen_op_eval_fbg(r_dst, cpu_fsr, offset); |
19f329ad BS |
1342 | break; |
1343 | case 0x7: | |
87e92502 | 1344 | gen_op_eval_fbu(r_dst, cpu_fsr, offset); |
19f329ad BS |
1345 | break; |
1346 | case 0x8: | |
1347 | gen_op_eval_ba(r_dst); | |
1348 | break; | |
1349 | case 0x9: | |
87e92502 | 1350 | gen_op_eval_fbe(r_dst, cpu_fsr, offset); |
19f329ad BS |
1351 | break; |
1352 | case 0xa: | |
87e92502 | 1353 | gen_op_eval_fbue(r_dst, cpu_fsr, offset); |
19f329ad BS |
1354 | break; |
1355 | case 0xb: | |
87e92502 | 1356 | gen_op_eval_fbge(r_dst, cpu_fsr, offset); |
19f329ad BS |
1357 | break; |
1358 | case 0xc: | |
87e92502 | 1359 | gen_op_eval_fbuge(r_dst, cpu_fsr, offset); |
19f329ad BS |
1360 | break; |
1361 | case 0xd: | |
87e92502 | 1362 | gen_op_eval_fble(r_dst, cpu_fsr, offset); |
19f329ad BS |
1363 | break; |
1364 | case 0xe: | |
87e92502 | 1365 | gen_op_eval_fbule(r_dst, cpu_fsr, offset); |
19f329ad BS |
1366 | break; |
1367 | case 0xf: | |
87e92502 | 1368 | gen_op_eval_fbo(r_dst, cpu_fsr, offset); |
19f329ad BS |
1369 | break; |
1370 | } | |
e8af50a3 | 1371 | } |
00f219bf | 1372 | |
19f329ad | 1373 | #ifdef TARGET_SPARC64 |
00f219bf BS |
1374 | // Inverted logic |
1375 | static const int gen_tcg_cond_reg[8] = { | |
1376 | -1, | |
1377 | TCG_COND_NE, | |
1378 | TCG_COND_GT, | |
1379 | TCG_COND_GE, | |
1380 | -1, | |
1381 | TCG_COND_EQ, | |
1382 | TCG_COND_LE, | |
1383 | TCG_COND_LT, | |
1384 | }; | |
19f329ad | 1385 | |
4af984a7 | 1386 | static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src) |
19f329ad | 1387 | { |
19f329ad BS |
1388 | int l1; |
1389 | ||
1390 | l1 = gen_new_label(); | |
0425bee5 | 1391 | tcg_gen_movi_tl(r_dst, 0); |
cb63669a | 1392 | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1); |
19f329ad BS |
1393 | tcg_gen_movi_tl(r_dst, 1); |
1394 | gen_set_label(l1); | |
1395 | } | |
3475187d | 1396 | #endif |
cf495bcf | 1397 | |
0bee699e | 1398 | /* XXX: potentially incorrect if dynamic npc */ |
4af984a7 BS |
1399 | static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc, |
1400 | TCGv r_cond) | |
7a3f1944 | 1401 | { |
cf495bcf | 1402 | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
af7bf89b | 1403 | target_ulong target = dc->pc + offset; |
5fafdf24 | 1404 | |
cf495bcf | 1405 | if (cond == 0x0) { |
0f8a249a BS |
1406 | /* unconditional not taken */ |
1407 | if (a) { | |
1408 | dc->pc = dc->npc + 4; | |
1409 | dc->npc = dc->pc + 4; | |
1410 | } else { | |
1411 | dc->pc = dc->npc; | |
1412 | dc->npc = dc->pc + 4; | |
1413 | } | |
cf495bcf | 1414 | } else if (cond == 0x8) { |
0f8a249a BS |
1415 | /* unconditional taken */ |
1416 | if (a) { | |
1417 | dc->pc = target; | |
1418 | dc->npc = dc->pc + 4; | |
1419 | } else { | |
1420 | dc->pc = dc->npc; | |
1421 | dc->npc = target; | |
1422 | } | |
cf495bcf | 1423 | } else { |
4af984a7 BS |
1424 | flush_cond(dc, r_cond); |
1425 | gen_cond(r_cond, cc, cond); | |
0f8a249a | 1426 | if (a) { |
4af984a7 | 1427 | gen_branch_a(dc, target, dc->npc, r_cond); |
cf495bcf | 1428 | dc->is_br = 1; |
0f8a249a | 1429 | } else { |
cf495bcf | 1430 | dc->pc = dc->npc; |
72cbca10 FB |
1431 | dc->jump_pc[0] = target; |
1432 | dc->jump_pc[1] = dc->npc + 4; | |
1433 | dc->npc = JUMP_PC; | |
0f8a249a | 1434 | } |
cf495bcf | 1435 | } |
7a3f1944 FB |
1436 | } |
1437 | ||
0bee699e | 1438 | /* XXX: potentially incorrect if dynamic npc */ |
4af984a7 BS |
1439 | static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc, |
1440 | TCGv r_cond) | |
e8af50a3 FB |
1441 | { |
1442 | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); | |
af7bf89b FB |
1443 | target_ulong target = dc->pc + offset; |
1444 | ||
e8af50a3 | 1445 | if (cond == 0x0) { |
0f8a249a BS |
1446 | /* unconditional not taken */ |
1447 | if (a) { | |
1448 | dc->pc = dc->npc + 4; | |
1449 | dc->npc = dc->pc + 4; | |
1450 | } else { | |
1451 | dc->pc = dc->npc; | |
1452 | dc->npc = dc->pc + 4; | |
1453 | } | |
e8af50a3 | 1454 | } else if (cond == 0x8) { |
0f8a249a BS |
1455 | /* unconditional taken */ |
1456 | if (a) { | |
1457 | dc->pc = target; | |
1458 | dc->npc = dc->pc + 4; | |
1459 | } else { | |
1460 | dc->pc = dc->npc; | |
1461 | dc->npc = target; | |
1462 | } | |
e8af50a3 | 1463 | } else { |
4af984a7 BS |
1464 | flush_cond(dc, r_cond); |
1465 | gen_fcond(r_cond, cc, cond); | |
0f8a249a | 1466 | if (a) { |
4af984a7 | 1467 | gen_branch_a(dc, target, dc->npc, r_cond); |
e8af50a3 | 1468 | dc->is_br = 1; |
0f8a249a | 1469 | } else { |
e8af50a3 FB |
1470 | dc->pc = dc->npc; |
1471 | dc->jump_pc[0] = target; | |
1472 | dc->jump_pc[1] = dc->npc + 4; | |
1473 | dc->npc = JUMP_PC; | |
0f8a249a | 1474 | } |
e8af50a3 FB |
1475 | } |
1476 | } | |
1477 | ||
3475187d FB |
1478 | #ifdef TARGET_SPARC64 |
1479 | /* XXX: potentially incorrect if dynamic npc */ | |
4af984a7 BS |
1480 | static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn, |
1481 | TCGv r_cond, TCGv r_reg) | |
7a3f1944 | 1482 | { |
3475187d FB |
1483 | unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); |
1484 | target_ulong target = dc->pc + offset; | |
1485 | ||
4af984a7 BS |
1486 | flush_cond(dc, r_cond); |
1487 | gen_cond_reg(r_cond, cond, r_reg); | |
3475187d | 1488 | if (a) { |
4af984a7 | 1489 | gen_branch_a(dc, target, dc->npc, r_cond); |
0f8a249a | 1490 | dc->is_br = 1; |
3475187d | 1491 | } else { |
0f8a249a BS |
1492 | dc->pc = dc->npc; |
1493 | dc->jump_pc[0] = target; | |
1494 | dc->jump_pc[1] = dc->npc + 4; | |
1495 | dc->npc = JUMP_PC; | |
3475187d | 1496 | } |
7a3f1944 FB |
1497 | } |
1498 | ||
3475187d | 1499 | static GenOpFunc * const gen_fcmps[4] = { |
7e8c2b6c BS |
1500 | helper_fcmps, |
1501 | helper_fcmps_fcc1, | |
1502 | helper_fcmps_fcc2, | |
1503 | helper_fcmps_fcc3, | |
3475187d FB |
1504 | }; |
1505 | ||
1506 | static GenOpFunc * const gen_fcmpd[4] = { | |
7e8c2b6c BS |
1507 | helper_fcmpd, |
1508 | helper_fcmpd_fcc1, | |
1509 | helper_fcmpd_fcc2, | |
1510 | helper_fcmpd_fcc3, | |
3475187d | 1511 | }; |
417454b0 | 1512 | |
1f587329 | 1513 | static GenOpFunc * const gen_fcmpq[4] = { |
7e8c2b6c BS |
1514 | helper_fcmpq, |
1515 | helper_fcmpq_fcc1, | |
1516 | helper_fcmpq_fcc2, | |
1517 | helper_fcmpq_fcc3, | |
1f587329 | 1518 | }; |
1f587329 | 1519 | |
417454b0 | 1520 | static GenOpFunc * const gen_fcmpes[4] = { |
7e8c2b6c BS |
1521 | helper_fcmpes, |
1522 | helper_fcmpes_fcc1, | |
1523 | helper_fcmpes_fcc2, | |
1524 | helper_fcmpes_fcc3, | |
417454b0 BS |
1525 | }; |
1526 | ||
1527 | static GenOpFunc * const gen_fcmped[4] = { | |
7e8c2b6c BS |
1528 | helper_fcmped, |
1529 | helper_fcmped_fcc1, | |
1530 | helper_fcmped_fcc2, | |
1531 | helper_fcmped_fcc3, | |
417454b0 BS |
1532 | }; |
1533 | ||
1f587329 | 1534 | static GenOpFunc * const gen_fcmpeq[4] = { |
7e8c2b6c BS |
1535 | helper_fcmpeq, |
1536 | helper_fcmpeq_fcc1, | |
1537 | helper_fcmpeq_fcc2, | |
1538 | helper_fcmpeq_fcc3, | |
1f587329 | 1539 | }; |
7e8c2b6c BS |
1540 | |
1541 | static inline void gen_op_fcmps(int fccno) | |
1542 | { | |
1543 | tcg_gen_helper_0_0(gen_fcmps[fccno]); | |
1544 | } | |
1545 | ||
1546 | static inline void gen_op_fcmpd(int fccno) | |
1547 | { | |
1548 | tcg_gen_helper_0_0(gen_fcmpd[fccno]); | |
1549 | } | |
1550 | ||
7e8c2b6c BS |
1551 | static inline void gen_op_fcmpq(int fccno) |
1552 | { | |
1553 | tcg_gen_helper_0_0(gen_fcmpq[fccno]); | |
1554 | } | |
7e8c2b6c BS |
1555 | |
1556 | static inline void gen_op_fcmpes(int fccno) | |
1557 | { | |
1558 | tcg_gen_helper_0_0(gen_fcmpes[fccno]); | |
1559 | } | |
1560 | ||
1561 | static inline void gen_op_fcmped(int fccno) | |
1562 | { | |
1563 | tcg_gen_helper_0_0(gen_fcmped[fccno]); | |
1564 | } | |
1565 | ||
7e8c2b6c BS |
1566 | static inline void gen_op_fcmpeq(int fccno) |
1567 | { | |
1568 | tcg_gen_helper_0_0(gen_fcmpeq[fccno]); | |
1569 | } | |
7e8c2b6c BS |
1570 | |
1571 | #else | |
1572 | ||
1573 | static inline void gen_op_fcmps(int fccno) | |
1574 | { | |
1575 | tcg_gen_helper_0_0(helper_fcmps); | |
1576 | } | |
1577 | ||
1578 | static inline void gen_op_fcmpd(int fccno) | |
1579 | { | |
1580 | tcg_gen_helper_0_0(helper_fcmpd); | |
1581 | } | |
1582 | ||
7e8c2b6c BS |
1583 | static inline void gen_op_fcmpq(int fccno) |
1584 | { | |
1585 | tcg_gen_helper_0_0(helper_fcmpq); | |
1586 | } | |
7e8c2b6c BS |
1587 | |
1588 | static inline void gen_op_fcmpes(int fccno) | |
1589 | { | |
1590 | tcg_gen_helper_0_0(helper_fcmpes); | |
1591 | } | |
1592 | ||
1593 | static inline void gen_op_fcmped(int fccno) | |
1594 | { | |
1595 | tcg_gen_helper_0_0(helper_fcmped); | |
1596 | } | |
1597 | ||
7e8c2b6c BS |
1598 | static inline void gen_op_fcmpeq(int fccno) |
1599 | { | |
1600 | tcg_gen_helper_0_0(helper_fcmpeq); | |
1601 | } | |
1602 | #endif | |
1603 | ||
134d77a1 BS |
1604 | static inline void gen_op_fpexception_im(int fsr_flags) |
1605 | { | |
2ea815ca BS |
1606 | TCGv r_const; |
1607 | ||
47ad35f1 | 1608 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK); |
87e92502 | 1609 | tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); |
2ea815ca BS |
1610 | r_const = tcg_const_i32(TT_FP_EXCP); |
1611 | tcg_gen_helper_0_1(raise_exception, r_const); | |
1612 | tcg_temp_free(r_const); | |
134d77a1 BS |
1613 | } |
1614 | ||
4af984a7 | 1615 | static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond) |
a80dde08 FB |
1616 | { |
1617 | #if !defined(CONFIG_USER_ONLY) | |
1618 | if (!dc->fpu_enabled) { | |
2ea815ca BS |
1619 | TCGv r_const; |
1620 | ||
4af984a7 | 1621 | save_state(dc, r_cond); |
2ea815ca BS |
1622 | r_const = tcg_const_i32(TT_NFPU_INSN); |
1623 | tcg_gen_helper_0_1(raise_exception, r_const); | |
1624 | tcg_temp_free(r_const); | |
a80dde08 FB |
1625 | dc->is_br = 1; |
1626 | return 1; | |
1627 | } | |
1628 | #endif | |
1629 | return 0; | |
1630 | } | |
1631 | ||
7e8c2b6c BS |
1632 | static inline void gen_op_clear_ieee_excp_and_FTT(void) |
1633 | { | |
47ad35f1 | 1634 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK); |
7e8c2b6c BS |
1635 | } |
1636 | ||
1637 | static inline void gen_clear_float_exceptions(void) | |
1638 | { | |
1639 | tcg_gen_helper_0_0(helper_clear_float_exceptions); | |
1640 | } | |
1641 | ||
1a2fb1c0 BS |
1642 | /* asi moves */ |
1643 | #ifdef TARGET_SPARC64 | |
0425bee5 | 1644 | static inline TCGv gen_get_asi(int insn, TCGv r_addr) |
1a2fb1c0 | 1645 | { |
95f9397c | 1646 | int asi; |
0425bee5 | 1647 | TCGv r_asi; |
1a2fb1c0 | 1648 | |
1a2fb1c0 | 1649 | if (IS_IMM) { |
0425bee5 | 1650 | r_asi = tcg_temp_new(TCG_TYPE_I32); |
255e1fcb | 1651 | tcg_gen_mov_i32(r_asi, cpu_asi); |
1a2fb1c0 BS |
1652 | } else { |
1653 | asi = GET_FIELD(insn, 19, 26); | |
0425bee5 | 1654 | r_asi = tcg_const_i32(asi); |
1a2fb1c0 | 1655 | } |
0425bee5 BS |
1656 | return r_asi; |
1657 | } | |
1658 | ||
77f193da BS |
1659 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
1660 | int sign) | |
0425bee5 | 1661 | { |
2ea815ca | 1662 | TCGv r_asi, r_size, r_sign; |
0425bee5 | 1663 | |
4af984a7 | 1664 | r_asi = gen_get_asi(insn, addr); |
2ea815ca BS |
1665 | r_size = tcg_const_i32(size); |
1666 | r_sign = tcg_const_i32(sign); | |
1667 | tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign); | |
1668 | tcg_temp_free(r_sign); | |
1669 | tcg_temp_free(r_size); | |
1670 | tcg_temp_free(r_asi); | |
1a2fb1c0 BS |
1671 | } |
1672 | ||
4af984a7 | 1673 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
1a2fb1c0 | 1674 | { |
2ea815ca | 1675 | TCGv r_asi, r_size; |
1a2fb1c0 | 1676 | |
4af984a7 | 1677 | r_asi = gen_get_asi(insn, addr); |
2ea815ca BS |
1678 | r_size = tcg_const_i32(size); |
1679 | tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size); | |
1680 | tcg_temp_free(r_size); | |
1681 | tcg_temp_free(r_asi); | |
1a2fb1c0 BS |
1682 | } |
1683 | ||
4af984a7 | 1684 | static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd) |
1a2fb1c0 | 1685 | { |
2ea815ca | 1686 | TCGv r_asi, r_size, r_rd; |
1a2fb1c0 | 1687 | |
4af984a7 | 1688 | r_asi = gen_get_asi(insn, addr); |
2ea815ca BS |
1689 | r_size = tcg_const_i32(size); |
1690 | r_rd = tcg_const_i32(rd); | |
1691 | tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd); | |
1692 | tcg_temp_free(r_rd); | |
1693 | tcg_temp_free(r_size); | |
1694 | tcg_temp_free(r_asi); | |
1a2fb1c0 BS |
1695 | } |
1696 | ||
4af984a7 | 1697 | static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd) |
1a2fb1c0 | 1698 | { |
2ea815ca | 1699 | TCGv r_asi, r_size, r_rd; |
1a2fb1c0 | 1700 | |
31741a27 | 1701 | r_asi = gen_get_asi(insn, addr); |
2ea815ca BS |
1702 | r_size = tcg_const_i32(size); |
1703 | r_rd = tcg_const_i32(rd); | |
1704 | tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd); | |
1705 | tcg_temp_free(r_rd); | |
1706 | tcg_temp_free(r_size); | |
1707 | tcg_temp_free(r_asi); | |
1a2fb1c0 BS |
1708 | } |
1709 | ||
4af984a7 | 1710 | static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
1a2fb1c0 | 1711 | { |
2ea815ca | 1712 | TCGv r_asi, r_size, r_sign; |
1a2fb1c0 | 1713 | |
4af984a7 | 1714 | r_asi = gen_get_asi(insn, addr); |
2ea815ca BS |
1715 | r_size = tcg_const_i32(4); |
1716 | r_sign = tcg_const_i32(0); | |
1717 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); | |
1718 | tcg_temp_free(r_sign); | |
1719 | tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size); | |
1720 | tcg_temp_free(r_size); | |
1721 | tcg_temp_free(r_asi); | |
8d96d209 | 1722 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1a2fb1c0 BS |
1723 | } |
1724 | ||
db166940 | 1725 | static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1a2fb1c0 | 1726 | { |
db166940 | 1727 | TCGv r_asi, r_rd; |
1a2fb1c0 | 1728 | |
4af984a7 | 1729 | r_asi = gen_get_asi(insn, addr); |
db166940 BS |
1730 | r_rd = tcg_const_i32(rd); |
1731 | tcg_gen_helper_0_3(helper_ldda_asi, addr, r_asi, r_rd); | |
1732 | tcg_temp_free(r_rd); | |
2ea815ca | 1733 | tcg_temp_free(r_asi); |
0425bee5 BS |
1734 | } |
1735 | ||
4af984a7 | 1736 | static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
0425bee5 | 1737 | { |
2ea815ca | 1738 | TCGv r_temp, r_asi, r_size; |
0425bee5 | 1739 | |
8d96d209 | 1740 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
0425bee5 | 1741 | gen_movl_reg_TN(rd + 1, r_temp); |
4af984a7 | 1742 | tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, |
0425bee5 | 1743 | r_temp); |
2ea815ca | 1744 | tcg_temp_free(r_temp); |
4af984a7 | 1745 | r_asi = gen_get_asi(insn, addr); |
2ea815ca BS |
1746 | r_size = tcg_const_i32(8); |
1747 | tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size); | |
1748 | tcg_temp_free(r_size); | |
1749 | tcg_temp_free(r_asi); | |
1a2fb1c0 BS |
1750 | } |
1751 | ||
77f193da BS |
1752 | static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
1753 | int rd) | |
1a2fb1c0 | 1754 | { |
1a2fb1c0 BS |
1755 | TCGv r_val1, r_asi; |
1756 | ||
ef28fd86 | 1757 | r_val1 = tcg_temp_new(TCG_TYPE_TL); |
1a2fb1c0 | 1758 | gen_movl_reg_TN(rd, r_val1); |
4af984a7 BS |
1759 | r_asi = gen_get_asi(insn, addr); |
1760 | tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi); | |
2ea815ca BS |
1761 | tcg_temp_free(r_asi); |
1762 | tcg_temp_free(r_val1); | |
1a2fb1c0 BS |
1763 | } |
1764 | ||
77f193da BS |
1765 | static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
1766 | int rd) | |
1a2fb1c0 | 1767 | { |
8911f501 | 1768 | TCGv r_asi; |
1a2fb1c0 | 1769 | |
8911f501 | 1770 | gen_movl_reg_TN(rd, cpu_tmp64); |
4af984a7 BS |
1771 | r_asi = gen_get_asi(insn, addr); |
1772 | tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi); | |
2ea815ca | 1773 | tcg_temp_free(r_asi); |
1a2fb1c0 BS |
1774 | } |
1775 | ||
1776 | #elif !defined(CONFIG_USER_ONLY) | |
1777 | ||
77f193da BS |
1778 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
1779 | int sign) | |
1a2fb1c0 | 1780 | { |
2ea815ca | 1781 | TCGv r_asi, r_size, r_sign; |
1a2fb1c0 | 1782 | |
2ea815ca BS |
1783 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1784 | r_size = tcg_const_i32(size); | |
1785 | r_sign = tcg_const_i32(sign); | |
1786 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); | |
1787 | tcg_temp_free(r_sign); | |
1788 | tcg_temp_free(r_size); | |
1789 | tcg_temp_free(r_asi); | |
4af984a7 | 1790 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1a2fb1c0 BS |
1791 | } |
1792 | ||
4af984a7 | 1793 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
1a2fb1c0 | 1794 | { |
2ea815ca | 1795 | TCGv r_asi, r_size; |
1a2fb1c0 | 1796 | |
4af984a7 | 1797 | tcg_gen_extu_tl_i64(cpu_tmp64, src); |
2ea815ca BS |
1798 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1799 | r_size = tcg_const_i32(size); | |
1800 | tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size); | |
1801 | tcg_temp_free(r_size); | |
1802 | tcg_temp_free(r_asi); | |
1a2fb1c0 BS |
1803 | } |
1804 | ||
4af984a7 | 1805 | static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
1a2fb1c0 | 1806 | { |
2ea815ca | 1807 | TCGv r_asi, r_size, r_sign; |
1a2fb1c0 | 1808 | |
2ea815ca BS |
1809 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1810 | r_size = tcg_const_i32(4); | |
1811 | r_sign = tcg_const_i32(0); | |
1812 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); | |
1813 | tcg_temp_free(r_sign); | |
1814 | tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size); | |
1815 | tcg_temp_free(r_size); | |
1816 | tcg_temp_free(r_asi); | |
8d96d209 | 1817 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1a2fb1c0 BS |
1818 | } |
1819 | ||
db166940 | 1820 | static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1a2fb1c0 | 1821 | { |
2ea815ca | 1822 | TCGv r_asi, r_size, r_sign; |
1a2fb1c0 | 1823 | |
2ea815ca BS |
1824 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1825 | r_size = tcg_const_i32(8); | |
1826 | r_sign = tcg_const_i32(0); | |
1827 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); | |
1828 | tcg_temp_free(r_sign); | |
1829 | tcg_temp_free(r_size); | |
1830 | tcg_temp_free(r_asi); | |
db166940 BS |
1831 | tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64); |
1832 | gen_movl_TN_reg(rd + 1, cpu_tmp0); | |
8911f501 | 1833 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32); |
4af984a7 | 1834 | tcg_gen_trunc_i64_tl(hi, cpu_tmp64); |
db166940 | 1835 | gen_movl_TN_reg(rd, hi); |
0425bee5 BS |
1836 | } |
1837 | ||
4af984a7 | 1838 | static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
0425bee5 | 1839 | { |
2ea815ca | 1840 | TCGv r_temp, r_asi, r_size; |
0425bee5 | 1841 | |
8d96d209 | 1842 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
0425bee5 | 1843 | gen_movl_reg_TN(rd + 1, r_temp); |
4af984a7 | 1844 | tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp); |
2ea815ca BS |
1845 | tcg_temp_free(r_temp); |
1846 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); | |
1847 | r_size = tcg_const_i32(8); | |
1848 | tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size); | |
1849 | tcg_temp_free(r_size); | |
1850 | tcg_temp_free(r_asi); | |
1a2fb1c0 BS |
1851 | } |
1852 | #endif | |
1853 | ||
1854 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) | |
4af984a7 | 1855 | static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn) |
1a2fb1c0 | 1856 | { |
2ea815ca | 1857 | TCGv r_val, r_asi, r_size; |
1a2fb1c0 | 1858 | |
4af984a7 | 1859 | gen_ld_asi(dst, addr, insn, 1, 0); |
1a2fb1c0 | 1860 | |
2ea815ca BS |
1861 | r_val = tcg_const_i64(0xffULL); |
1862 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); | |
1863 | r_size = tcg_const_i32(1); | |
1864 | tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size); | |
1865 | tcg_temp_free(r_size); | |
1866 | tcg_temp_free(r_asi); | |
1867 | tcg_temp_free(r_val); | |
1a2fb1c0 BS |
1868 | } |
1869 | #endif | |
1870 | ||
9322a4bf BS |
1871 | static inline TCGv get_src1(unsigned int insn, TCGv def) |
1872 | { | |
1873 | TCGv r_rs1 = def; | |
1874 | unsigned int rs1; | |
1875 | ||
1876 | rs1 = GET_FIELD(insn, 13, 17); | |
1877 | if (rs1 == 0) | |
5c6a0628 | 1878 | r_rs1 = tcg_const_tl(0); // XXX how to free? |
9322a4bf | 1879 | else if (rs1 < 8) |
5c6a0628 | 1880 | r_rs1 = cpu_gregs[rs1]; |
9322a4bf BS |
1881 | else |
1882 | tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong)); | |
1883 | return r_rs1; | |
1884 | } | |
1885 | ||
a49d9390 BS |
1886 | static inline TCGv get_src2(unsigned int insn, TCGv def) |
1887 | { | |
1888 | TCGv r_rs2 = def; | |
1889 | unsigned int rs2; | |
1890 | ||
1891 | if (IS_IMM) { /* immediate */ | |
1892 | rs2 = GET_FIELDs(insn, 19, 31); | |
2ea815ca | 1893 | r_rs2 = tcg_const_tl((int)rs2); // XXX how to free? |
a49d9390 BS |
1894 | } else { /* register */ |
1895 | rs2 = GET_FIELD(insn, 27, 31); | |
1896 | if (rs2 == 0) | |
2ea815ca | 1897 | r_rs2 = tcg_const_tl(0); // XXX how to free? |
a49d9390 BS |
1898 | else if (rs2 < 8) |
1899 | r_rs2 = cpu_gregs[rs2]; | |
1900 | else | |
1901 | tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong)); | |
1902 | } | |
1903 | return r_rs2; | |
1904 | } | |
1905 | ||
64a88d5d | 1906 | #define CHECK_IU_FEATURE(dc, FEATURE) \ |
5578ceab | 1907 | if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ |
64a88d5d BS |
1908 | goto illegal_insn; |
1909 | #define CHECK_FPU_FEATURE(dc, FEATURE) \ | |
5578ceab | 1910 | if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ |
64a88d5d BS |
1911 | goto nfpu_insn; |
1912 | ||
0bee699e | 1913 | /* before an instruction, dc->pc must be static */ |
cf495bcf FB |
1914 | static void disas_sparc_insn(DisasContext * dc) |
1915 | { | |
1916 | unsigned int insn, opc, rs1, rs2, rd; | |
7a3f1944 | 1917 | |
a8c768c0 BS |
1918 | if (unlikely(loglevel & CPU_LOG_TB_OP)) |
1919 | tcg_gen_debug_insn_start(dc->pc); | |
0fa85d43 | 1920 | insn = ldl_code(dc->pc); |
cf495bcf | 1921 | opc = GET_FIELD(insn, 0, 1); |
7a3f1944 | 1922 | |
cf495bcf | 1923 | rd = GET_FIELD(insn, 2, 6); |
6ae20372 | 1924 | |
5c6a0628 BS |
1925 | cpu_src1 = tcg_temp_new(TCG_TYPE_TL); // const |
1926 | cpu_src2 = tcg_temp_new(TCG_TYPE_TL); // const | |
6ae20372 | 1927 | |
cf495bcf | 1928 | switch (opc) { |
0f8a249a BS |
1929 | case 0: /* branches/sethi */ |
1930 | { | |
1931 | unsigned int xop = GET_FIELD(insn, 7, 9); | |
1932 | int32_t target; | |
1933 | switch (xop) { | |
3475187d | 1934 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
1935 | case 0x1: /* V9 BPcc */ |
1936 | { | |
1937 | int cc; | |
1938 | ||
1939 | target = GET_FIELD_SP(insn, 0, 18); | |
1940 | target = sign_extend(target, 18); | |
1941 | target <<= 2; | |
1942 | cc = GET_FIELD_SP(insn, 20, 21); | |
1943 | if (cc == 0) | |
6ae20372 | 1944 | do_branch(dc, target, insn, 0, cpu_cond); |
0f8a249a | 1945 | else if (cc == 2) |
6ae20372 | 1946 | do_branch(dc, target, insn, 1, cpu_cond); |
0f8a249a BS |
1947 | else |
1948 | goto illegal_insn; | |
1949 | goto jmp_insn; | |
1950 | } | |
1951 | case 0x3: /* V9 BPr */ | |
1952 | { | |
1953 | target = GET_FIELD_SP(insn, 0, 13) | | |
13846e70 | 1954 | (GET_FIELD_SP(insn, 20, 21) << 14); |
0f8a249a BS |
1955 | target = sign_extend(target, 16); |
1956 | target <<= 2; | |
9322a4bf | 1957 | cpu_src1 = get_src1(insn, cpu_src1); |
6ae20372 | 1958 | do_branch_reg(dc, target, insn, cpu_cond, cpu_src1); |
0f8a249a BS |
1959 | goto jmp_insn; |
1960 | } | |
1961 | case 0x5: /* V9 FBPcc */ | |
1962 | { | |
1963 | int cc = GET_FIELD_SP(insn, 20, 21); | |
6ae20372 | 1964 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
a80dde08 | 1965 | goto jmp_insn; |
0f8a249a BS |
1966 | target = GET_FIELD_SP(insn, 0, 18); |
1967 | target = sign_extend(target, 19); | |
1968 | target <<= 2; | |
6ae20372 | 1969 | do_fbranch(dc, target, insn, cc, cpu_cond); |
0f8a249a BS |
1970 | goto jmp_insn; |
1971 | } | |
a4d17f19 | 1972 | #else |
0f8a249a BS |
1973 | case 0x7: /* CBN+x */ |
1974 | { | |
1975 | goto ncp_insn; | |
1976 | } | |
1977 | #endif | |
1978 | case 0x2: /* BN+x */ | |
1979 | { | |
1980 | target = GET_FIELD(insn, 10, 31); | |
1981 | target = sign_extend(target, 22); | |
1982 | target <<= 2; | |
6ae20372 | 1983 | do_branch(dc, target, insn, 0, cpu_cond); |
0f8a249a BS |
1984 | goto jmp_insn; |
1985 | } | |
1986 | case 0x6: /* FBN+x */ | |
1987 | { | |
6ae20372 | 1988 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
a80dde08 | 1989 | goto jmp_insn; |
0f8a249a BS |
1990 | target = GET_FIELD(insn, 10, 31); |
1991 | target = sign_extend(target, 22); | |
1992 | target <<= 2; | |
6ae20372 | 1993 | do_fbranch(dc, target, insn, 0, cpu_cond); |
0f8a249a BS |
1994 | goto jmp_insn; |
1995 | } | |
1996 | case 0x4: /* SETHI */ | |
0f8a249a | 1997 | if (rd) { // nop |
0f8a249a | 1998 | uint32_t value = GET_FIELD(insn, 10, 31); |
2ea815ca BS |
1999 | TCGv r_const; |
2000 | ||
2001 | r_const = tcg_const_tl(value << 10); | |
2002 | gen_movl_TN_reg(rd, r_const); | |
2003 | tcg_temp_free(r_const); | |
0f8a249a | 2004 | } |
0f8a249a BS |
2005 | break; |
2006 | case 0x0: /* UNIMPL */ | |
2007 | default: | |
3475187d | 2008 | goto illegal_insn; |
0f8a249a BS |
2009 | } |
2010 | break; | |
2011 | } | |
2012 | break; | |
cf495bcf | 2013 | case 1: |
0f8a249a BS |
2014 | /*CALL*/ { |
2015 | target_long target = GET_FIELDs(insn, 2, 31) << 2; | |
2ea815ca | 2016 | TCGv r_const; |
cf495bcf | 2017 | |
2ea815ca BS |
2018 | r_const = tcg_const_tl(dc->pc); |
2019 | gen_movl_TN_reg(15, r_const); | |
2020 | tcg_temp_free(r_const); | |
0f8a249a | 2021 | target += dc->pc; |
6ae20372 | 2022 | gen_mov_pc_npc(dc, cpu_cond); |
0f8a249a BS |
2023 | dc->npc = target; |
2024 | } | |
2025 | goto jmp_insn; | |
2026 | case 2: /* FPU & Logical Operations */ | |
2027 | { | |
2028 | unsigned int xop = GET_FIELD(insn, 7, 12); | |
2029 | if (xop == 0x3a) { /* generate trap */ | |
cf495bcf | 2030 | int cond; |
3475187d | 2031 | |
9322a4bf | 2032 | cpu_src1 = get_src1(insn, cpu_src1); |
0f8a249a BS |
2033 | if (IS_IMM) { |
2034 | rs2 = GET_FIELD(insn, 25, 31); | |
6ae20372 | 2035 | tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2); |
cf495bcf FB |
2036 | } else { |
2037 | rs2 = GET_FIELD(insn, 27, 31); | |
0f8a249a | 2038 | if (rs2 != 0) { |
6ae20372 BS |
2039 | gen_movl_reg_TN(rs2, cpu_src2); |
2040 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); | |
6f551262 BS |
2041 | } else |
2042 | tcg_gen_mov_tl(cpu_dst, cpu_src1); | |
cf495bcf | 2043 | } |
cf495bcf FB |
2044 | cond = GET_FIELD(insn, 3, 6); |
2045 | if (cond == 0x8) { | |
6ae20372 BS |
2046 | save_state(dc, cpu_cond); |
2047 | tcg_gen_helper_0_1(helper_trap, cpu_dst); | |
af7bf89b | 2048 | } else if (cond != 0) { |
748b9d8e | 2049 | TCGv r_cond = tcg_temp_new(TCG_TYPE_TL); |
3475187d | 2050 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
2051 | /* V9 icc/xcc */ |
2052 | int cc = GET_FIELD_SP(insn, 11, 12); | |
748b9d8e | 2053 | |
6ae20372 | 2054 | save_state(dc, cpu_cond); |
0f8a249a | 2055 | if (cc == 0) |
748b9d8e | 2056 | gen_cond(r_cond, 0, cond); |
0f8a249a | 2057 | else if (cc == 2) |
748b9d8e | 2058 | gen_cond(r_cond, 1, cond); |
0f8a249a BS |
2059 | else |
2060 | goto illegal_insn; | |
3475187d | 2061 | #else |
6ae20372 | 2062 | save_state(dc, cpu_cond); |
748b9d8e | 2063 | gen_cond(r_cond, 0, cond); |
3475187d | 2064 | #endif |
6ae20372 | 2065 | tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond); |
2ea815ca | 2066 | tcg_temp_free(r_cond); |
cf495bcf | 2067 | } |
a80dde08 | 2068 | gen_op_next_insn(); |
57fec1fe | 2069 | tcg_gen_exit_tb(0); |
a80dde08 FB |
2070 | dc->is_br = 1; |
2071 | goto jmp_insn; | |
cf495bcf FB |
2072 | } else if (xop == 0x28) { |
2073 | rs1 = GET_FIELD(insn, 13, 17); | |
2074 | switch(rs1) { | |
2075 | case 0: /* rdy */ | |
65fe7b09 BS |
2076 | #ifndef TARGET_SPARC64 |
2077 | case 0x01 ... 0x0e: /* undefined in the SPARCv8 | |
2078 | manual, rdy on the microSPARC | |
2079 | II */ | |
2080 | case 0x0f: /* stbar in the SPARCv8 manual, | |
2081 | rdy on the microSPARC II */ | |
2082 | case 0x10 ... 0x1f: /* implementation-dependent in the | |
2083 | SPARCv8 manual, rdy on the | |
2084 | microSPARC II */ | |
2085 | #endif | |
255e1fcb | 2086 | gen_movl_TN_reg(rd, cpu_y); |
cf495bcf | 2087 | break; |
3475187d | 2088 | #ifdef TARGET_SPARC64 |
0f8a249a | 2089 | case 0x2: /* V9 rdccr */ |
6ae20372 BS |
2090 | tcg_gen_helper_1_0(helper_rdccr, cpu_dst); |
2091 | gen_movl_TN_reg(rd, cpu_dst); | |
3475187d | 2092 | break; |
0f8a249a | 2093 | case 0x3: /* V9 rdasi */ |
255e1fcb | 2094 | tcg_gen_ext_i32_tl(cpu_dst, cpu_asi); |
6ae20372 | 2095 | gen_movl_TN_reg(rd, cpu_dst); |
3475187d | 2096 | break; |
0f8a249a | 2097 | case 0x4: /* V9 rdtick */ |
ccd4a219 BS |
2098 | { |
2099 | TCGv r_tickptr; | |
2100 | ||
2101 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
2102 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
2103 | offsetof(CPUState, tick)); | |
6ae20372 | 2104 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst, |
ccd4a219 | 2105 | r_tickptr); |
2ea815ca | 2106 | tcg_temp_free(r_tickptr); |
6ae20372 | 2107 | gen_movl_TN_reg(rd, cpu_dst); |
ccd4a219 | 2108 | } |
3475187d | 2109 | break; |
0f8a249a | 2110 | case 0x5: /* V9 rdpc */ |
2ea815ca BS |
2111 | { |
2112 | TCGv r_const; | |
2113 | ||
2114 | r_const = tcg_const_tl(dc->pc); | |
2115 | gen_movl_TN_reg(rd, r_const); | |
2116 | tcg_temp_free(r_const); | |
2117 | } | |
0f8a249a BS |
2118 | break; |
2119 | case 0x6: /* V9 rdfprs */ | |
255e1fcb | 2120 | tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs); |
6ae20372 | 2121 | gen_movl_TN_reg(rd, cpu_dst); |
3475187d | 2122 | break; |
65fe7b09 BS |
2123 | case 0xf: /* V9 membar */ |
2124 | break; /* no effect */ | |
0f8a249a | 2125 | case 0x13: /* Graphics Status */ |
6ae20372 | 2126 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
725cb90b | 2127 | goto jmp_insn; |
255e1fcb | 2128 | gen_movl_TN_reg(rd, cpu_gsr); |
725cb90b | 2129 | break; |
0f8a249a | 2130 | case 0x17: /* Tick compare */ |
255e1fcb | 2131 | gen_movl_TN_reg(rd, cpu_tick_cmpr); |
83469015 | 2132 | break; |
0f8a249a | 2133 | case 0x18: /* System tick */ |
ccd4a219 BS |
2134 | { |
2135 | TCGv r_tickptr; | |
2136 | ||
2137 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
2138 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
2139 | offsetof(CPUState, stick)); | |
6ae20372 | 2140 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst, |
ccd4a219 | 2141 | r_tickptr); |
2ea815ca | 2142 | tcg_temp_free(r_tickptr); |
6ae20372 | 2143 | gen_movl_TN_reg(rd, cpu_dst); |
ccd4a219 | 2144 | } |
83469015 | 2145 | break; |
0f8a249a | 2146 | case 0x19: /* System tick compare */ |
255e1fcb | 2147 | gen_movl_TN_reg(rd, cpu_stick_cmpr); |
83469015 | 2148 | break; |
0f8a249a BS |
2149 | case 0x10: /* Performance Control */ |
2150 | case 0x11: /* Performance Instrumentation Counter */ | |
2151 | case 0x12: /* Dispatch Control */ | |
2152 | case 0x14: /* Softint set, WO */ | |
2153 | case 0x15: /* Softint clear, WO */ | |
2154 | case 0x16: /* Softint write */ | |
3475187d FB |
2155 | #endif |
2156 | default: | |
cf495bcf FB |
2157 | goto illegal_insn; |
2158 | } | |
e8af50a3 | 2159 | #if !defined(CONFIG_USER_ONLY) |
e9ebed4d | 2160 | } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ |
3475187d | 2161 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
2162 | if (!supervisor(dc)) |
2163 | goto priv_insn; | |
6ae20372 | 2164 | tcg_gen_helper_1_0(helper_rdpsr, cpu_dst); |
e9ebed4d | 2165 | #else |
fb79ceb9 | 2166 | CHECK_IU_FEATURE(dc, HYPV); |
e9ebed4d BS |
2167 | if (!hypervisor(dc)) |
2168 | goto priv_insn; | |
2169 | rs1 = GET_FIELD(insn, 13, 17); | |
2170 | switch (rs1) { | |
2171 | case 0: // hpstate | |
2172 | // gen_op_rdhpstate(); | |
2173 | break; | |
2174 | case 1: // htstate | |
2175 | // gen_op_rdhtstate(); | |
2176 | break; | |
2177 | case 3: // hintp | |
255e1fcb | 2178 | tcg_gen_mov_tl(cpu_dst, cpu_hintp); |
e9ebed4d BS |
2179 | break; |
2180 | case 5: // htba | |
255e1fcb | 2181 | tcg_gen_mov_tl(cpu_dst, cpu_htba); |
e9ebed4d BS |
2182 | break; |
2183 | case 6: // hver | |
255e1fcb | 2184 | tcg_gen_mov_tl(cpu_dst, cpu_hver); |
e9ebed4d BS |
2185 | break; |
2186 | case 31: // hstick_cmpr | |
255e1fcb | 2187 | tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr); |
e9ebed4d BS |
2188 | break; |
2189 | default: | |
2190 | goto illegal_insn; | |
2191 | } | |
2192 | #endif | |
6ae20372 | 2193 | gen_movl_TN_reg(rd, cpu_dst); |
e8af50a3 | 2194 | break; |
3475187d | 2195 | } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ |
0f8a249a BS |
2196 | if (!supervisor(dc)) |
2197 | goto priv_insn; | |
3475187d FB |
2198 | #ifdef TARGET_SPARC64 |
2199 | rs1 = GET_FIELD(insn, 13, 17); | |
0f8a249a BS |
2200 | switch (rs1) { |
2201 | case 0: // tpc | |
375ee38b BS |
2202 | { |
2203 | TCGv r_tsptr; | |
2204 | ||
2205 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
2206 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
2207 | offsetof(CPUState, tsptr)); | |
ece43b8d | 2208 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
375ee38b | 2209 | offsetof(trap_state, tpc)); |
2ea815ca | 2210 | tcg_temp_free(r_tsptr); |
375ee38b | 2211 | } |
0f8a249a BS |
2212 | break; |
2213 | case 1: // tnpc | |
375ee38b BS |
2214 | { |
2215 | TCGv r_tsptr; | |
2216 | ||
2217 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
2218 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
2219 | offsetof(CPUState, tsptr)); | |
ece43b8d | 2220 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
375ee38b | 2221 | offsetof(trap_state, tnpc)); |
2ea815ca | 2222 | tcg_temp_free(r_tsptr); |
375ee38b | 2223 | } |
0f8a249a BS |
2224 | break; |
2225 | case 2: // tstate | |
375ee38b BS |
2226 | { |
2227 | TCGv r_tsptr; | |
2228 | ||
2229 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
2230 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
2231 | offsetof(CPUState, tsptr)); | |
ece43b8d | 2232 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
375ee38b | 2233 | offsetof(trap_state, tstate)); |
2ea815ca | 2234 | tcg_temp_free(r_tsptr); |
375ee38b | 2235 | } |
0f8a249a BS |
2236 | break; |
2237 | case 3: // tt | |
375ee38b BS |
2238 | { |
2239 | TCGv r_tsptr; | |
2240 | ||
2241 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
2242 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
2243 | offsetof(CPUState, tsptr)); | |
ece43b8d | 2244 | tcg_gen_ld_i32(cpu_tmp0, r_tsptr, |
375ee38b | 2245 | offsetof(trap_state, tt)); |
2ea815ca | 2246 | tcg_temp_free(r_tsptr); |
375ee38b | 2247 | } |
0f8a249a BS |
2248 | break; |
2249 | case 4: // tick | |
ccd4a219 BS |
2250 | { |
2251 | TCGv r_tickptr; | |
2252 | ||
2253 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
2254 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
2255 | offsetof(CPUState, tick)); | |
ece43b8d | 2256 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_tmp0, |
ccd4a219 | 2257 | r_tickptr); |
ece43b8d | 2258 | gen_movl_TN_reg(rd, cpu_tmp0); |
2ea815ca | 2259 | tcg_temp_free(r_tickptr); |
ccd4a219 | 2260 | } |
0f8a249a BS |
2261 | break; |
2262 | case 5: // tba | |
255e1fcb | 2263 | tcg_gen_mov_tl(cpu_tmp0, cpu_tbr); |
0f8a249a BS |
2264 | break; |
2265 | case 6: // pstate | |
77f193da BS |
2266 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2267 | offsetof(CPUSPARCState, pstate)); | |
ece43b8d | 2268 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
0f8a249a BS |
2269 | break; |
2270 | case 7: // tl | |
77f193da BS |
2271 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2272 | offsetof(CPUSPARCState, tl)); | |
ece43b8d | 2273 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
0f8a249a BS |
2274 | break; |
2275 | case 8: // pil | |
77f193da BS |
2276 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2277 | offsetof(CPUSPARCState, psrpil)); | |
ece43b8d | 2278 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
0f8a249a BS |
2279 | break; |
2280 | case 9: // cwp | |
ece43b8d | 2281 | tcg_gen_helper_1_0(helper_rdcwp, cpu_tmp0); |
0f8a249a BS |
2282 | break; |
2283 | case 10: // cansave | |
77f193da BS |
2284 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2285 | offsetof(CPUSPARCState, cansave)); | |
ece43b8d | 2286 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
0f8a249a BS |
2287 | break; |
2288 | case 11: // canrestore | |
77f193da BS |
2289 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2290 | offsetof(CPUSPARCState, canrestore)); | |
ece43b8d | 2291 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
0f8a249a BS |
2292 | break; |
2293 | case 12: // cleanwin | |
77f193da BS |
2294 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2295 | offsetof(CPUSPARCState, cleanwin)); | |
ece43b8d | 2296 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
0f8a249a BS |
2297 | break; |
2298 | case 13: // otherwin | |
77f193da BS |
2299 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2300 | offsetof(CPUSPARCState, otherwin)); | |
ece43b8d | 2301 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
0f8a249a BS |
2302 | break; |
2303 | case 14: // wstate | |
77f193da BS |
2304 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2305 | offsetof(CPUSPARCState, wstate)); | |
ece43b8d | 2306 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
0f8a249a | 2307 | break; |
e9ebed4d | 2308 | case 16: // UA2005 gl |
fb79ceb9 | 2309 | CHECK_IU_FEATURE(dc, GL); |
77f193da BS |
2310 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2311 | offsetof(CPUSPARCState, gl)); | |
ece43b8d | 2312 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
e9ebed4d BS |
2313 | break; |
2314 | case 26: // UA2005 strand status | |
fb79ceb9 | 2315 | CHECK_IU_FEATURE(dc, HYPV); |
e9ebed4d BS |
2316 | if (!hypervisor(dc)) |
2317 | goto priv_insn; | |
255e1fcb | 2318 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_ssr); |
e9ebed4d | 2319 | break; |
0f8a249a | 2320 | case 31: // ver |
255e1fcb | 2321 | tcg_gen_mov_tl(cpu_tmp0, cpu_ver); |
0f8a249a BS |
2322 | break; |
2323 | case 15: // fq | |
2324 | default: | |
2325 | goto illegal_insn; | |
2326 | } | |
3475187d | 2327 | #else |
255e1fcb | 2328 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim); |
3475187d | 2329 | #endif |
ece43b8d | 2330 | gen_movl_TN_reg(rd, cpu_tmp0); |
e8af50a3 | 2331 | break; |
3475187d FB |
2332 | } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ |
2333 | #ifdef TARGET_SPARC64 | |
c5f2f668 | 2334 | save_state(dc, cpu_cond); |
72a9747b | 2335 | tcg_gen_helper_0_0(helper_flushw); |
3475187d | 2336 | #else |
0f8a249a BS |
2337 | if (!supervisor(dc)) |
2338 | goto priv_insn; | |
255e1fcb | 2339 | gen_movl_TN_reg(rd, cpu_tbr); |
3475187d | 2340 | #endif |
e8af50a3 FB |
2341 | break; |
2342 | #endif | |
0f8a249a | 2343 | } else if (xop == 0x34) { /* FPU Operations */ |
6ae20372 | 2344 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
a80dde08 | 2345 | goto jmp_insn; |
0f8a249a | 2346 | gen_op_clear_ieee_excp_and_FTT(); |
e8af50a3 | 2347 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a BS |
2348 | rs2 = GET_FIELD(insn, 27, 31); |
2349 | xop = GET_FIELD(insn, 18, 26); | |
2350 | switch (xop) { | |
2351 | case 0x1: /* fmovs */ | |
2352 | gen_op_load_fpr_FT0(rs2); | |
2353 | gen_op_store_FT0_fpr(rd); | |
2354 | break; | |
2355 | case 0x5: /* fnegs */ | |
2356 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 2357 | tcg_gen_helper_0_0(helper_fnegs); |
0f8a249a BS |
2358 | gen_op_store_FT0_fpr(rd); |
2359 | break; | |
2360 | case 0x9: /* fabss */ | |
2361 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2362 | tcg_gen_helper_0_0(helper_fabss); |
0f8a249a BS |
2363 | gen_op_store_FT0_fpr(rd); |
2364 | break; | |
2365 | case 0x29: /* fsqrts */ | |
64a88d5d | 2366 | CHECK_FPU_FEATURE(dc, FSQRT); |
0f8a249a | 2367 | gen_op_load_fpr_FT1(rs2); |
7e8c2b6c BS |
2368 | gen_clear_float_exceptions(); |
2369 | tcg_gen_helper_0_0(helper_fsqrts); | |
2370 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); | |
0f8a249a BS |
2371 | gen_op_store_FT0_fpr(rd); |
2372 | break; | |
2373 | case 0x2a: /* fsqrtd */ | |
64a88d5d | 2374 | CHECK_FPU_FEATURE(dc, FSQRT); |
0f8a249a | 2375 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
7e8c2b6c BS |
2376 | gen_clear_float_exceptions(); |
2377 | tcg_gen_helper_0_0(helper_fsqrtd); | |
2378 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); | |
0f8a249a BS |
2379 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2380 | break; | |
2381 | case 0x2b: /* fsqrtq */ | |
64a88d5d | 2382 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2383 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
7e8c2b6c BS |
2384 | gen_clear_float_exceptions(); |
2385 | tcg_gen_helper_0_0(helper_fsqrtq); | |
2386 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); | |
1f587329 BS |
2387 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2388 | break; | |
0f8a249a BS |
2389 | case 0x41: |
2390 | gen_op_load_fpr_FT0(rs1); | |
2391 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2392 | gen_clear_float_exceptions(); |
44e7757c | 2393 | tcg_gen_helper_0_0(helper_fadds); |
7e8c2b6c | 2394 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2395 | gen_op_store_FT0_fpr(rd); |
2396 | break; | |
2397 | case 0x42: | |
2398 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
2399 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2400 | gen_clear_float_exceptions(); |
44e7757c | 2401 | tcg_gen_helper_0_0(helper_faddd); |
7e8c2b6c | 2402 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2403 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2404 | break; | |
2405 | case 0x43: /* faddq */ | |
64a88d5d | 2406 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 BS |
2407 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2408 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2409 | gen_clear_float_exceptions(); |
44e7757c | 2410 | tcg_gen_helper_0_0(helper_faddq); |
7e8c2b6c | 2411 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2412 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2413 | break; | |
0f8a249a BS |
2414 | case 0x45: |
2415 | gen_op_load_fpr_FT0(rs1); | |
2416 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2417 | gen_clear_float_exceptions(); |
44e7757c | 2418 | tcg_gen_helper_0_0(helper_fsubs); |
7e8c2b6c | 2419 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2420 | gen_op_store_FT0_fpr(rd); |
2421 | break; | |
2422 | case 0x46: | |
2423 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
2424 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2425 | gen_clear_float_exceptions(); |
44e7757c | 2426 | tcg_gen_helper_0_0(helper_fsubd); |
7e8c2b6c | 2427 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2428 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2429 | break; | |
2430 | case 0x47: /* fsubq */ | |
64a88d5d | 2431 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 BS |
2432 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2433 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2434 | gen_clear_float_exceptions(); |
44e7757c | 2435 | tcg_gen_helper_0_0(helper_fsubq); |
7e8c2b6c | 2436 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2437 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2438 | break; | |
64a88d5d BS |
2439 | case 0x49: /* fmuls */ |
2440 | CHECK_FPU_FEATURE(dc, FMUL); | |
0f8a249a BS |
2441 | gen_op_load_fpr_FT0(rs1); |
2442 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2443 | gen_clear_float_exceptions(); |
44e7757c | 2444 | tcg_gen_helper_0_0(helper_fmuls); |
7e8c2b6c | 2445 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2446 | gen_op_store_FT0_fpr(rd); |
2447 | break; | |
64a88d5d BS |
2448 | case 0x4a: /* fmuld */ |
2449 | CHECK_FPU_FEATURE(dc, FMUL); | |
0f8a249a BS |
2450 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2451 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2452 | gen_clear_float_exceptions(); |
44e7757c | 2453 | tcg_gen_helper_0_0(helper_fmuld); |
7e8c2b6c | 2454 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2382dc6b | 2455 | gen_op_store_DT0_fpr(DFPREG(rd)); |
0f8a249a BS |
2456 | break; |
2457 | case 0x4b: /* fmulq */ | |
64a88d5d BS |
2458 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2459 | CHECK_FPU_FEATURE(dc, FMUL); | |
1f587329 BS |
2460 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2461 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2462 | gen_clear_float_exceptions(); |
44e7757c | 2463 | tcg_gen_helper_0_0(helper_fmulq); |
7e8c2b6c | 2464 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2465 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2466 | break; | |
0f8a249a BS |
2467 | case 0x4d: |
2468 | gen_op_load_fpr_FT0(rs1); | |
2469 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2470 | gen_clear_float_exceptions(); |
44e7757c | 2471 | tcg_gen_helper_0_0(helper_fdivs); |
7e8c2b6c | 2472 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2473 | gen_op_store_FT0_fpr(rd); |
2474 | break; | |
2475 | case 0x4e: | |
2476 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
2477 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2478 | gen_clear_float_exceptions(); |
44e7757c | 2479 | tcg_gen_helper_0_0(helper_fdivd); |
7e8c2b6c | 2480 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2481 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2482 | break; | |
2483 | case 0x4f: /* fdivq */ | |
64a88d5d | 2484 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 BS |
2485 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2486 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2487 | gen_clear_float_exceptions(); |
44e7757c | 2488 | tcg_gen_helper_0_0(helper_fdivq); |
7e8c2b6c | 2489 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2490 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2491 | break; | |
0f8a249a | 2492 | case 0x69: |
e30b4678 | 2493 | CHECK_FPU_FEATURE(dc, FSMULD); |
0f8a249a BS |
2494 | gen_op_load_fpr_FT0(rs1); |
2495 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2496 | gen_clear_float_exceptions(); |
44e7757c | 2497 | tcg_gen_helper_0_0(helper_fsmuld); |
7e8c2b6c | 2498 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2499 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2500 | break; | |
2501 | case 0x6e: /* fdmulq */ | |
64a88d5d | 2502 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 BS |
2503 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2504 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2505 | gen_clear_float_exceptions(); |
44e7757c | 2506 | tcg_gen_helper_0_0(helper_fdmulq); |
7e8c2b6c | 2507 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2508 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2509 | break; | |
0f8a249a BS |
2510 | case 0xc4: |
2511 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2512 | gen_clear_float_exceptions(); |
44e7757c | 2513 | tcg_gen_helper_0_0(helper_fitos); |
7e8c2b6c | 2514 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2515 | gen_op_store_FT0_fpr(rd); |
2516 | break; | |
2517 | case 0xc6: | |
2518 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2519 | gen_clear_float_exceptions(); |
44e7757c | 2520 | tcg_gen_helper_0_0(helper_fdtos); |
7e8c2b6c | 2521 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2522 | gen_op_store_FT0_fpr(rd); |
2523 | break; | |
2524 | case 0xc7: /* fqtos */ | |
64a88d5d | 2525 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2526 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
7e8c2b6c | 2527 | gen_clear_float_exceptions(); |
44e7757c | 2528 | tcg_gen_helper_0_0(helper_fqtos); |
7e8c2b6c | 2529 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2530 | gen_op_store_FT0_fpr(rd); |
2531 | break; | |
0f8a249a BS |
2532 | case 0xc8: |
2533 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 2534 | tcg_gen_helper_0_0(helper_fitod); |
0f8a249a BS |
2535 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2536 | break; | |
2537 | case 0xc9: | |
2538 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 2539 | tcg_gen_helper_0_0(helper_fstod); |
0f8a249a BS |
2540 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2541 | break; | |
2542 | case 0xcb: /* fqtod */ | |
64a88d5d | 2543 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2544 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
7e8c2b6c | 2545 | gen_clear_float_exceptions(); |
44e7757c | 2546 | tcg_gen_helper_0_0(helper_fqtod); |
7e8c2b6c | 2547 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2548 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2549 | break; | |
0f8a249a | 2550 | case 0xcc: /* fitoq */ |
64a88d5d | 2551 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2552 | gen_op_load_fpr_FT1(rs2); |
44e7757c | 2553 | tcg_gen_helper_0_0(helper_fitoq); |
1f587329 BS |
2554 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2555 | break; | |
0f8a249a | 2556 | case 0xcd: /* fstoq */ |
64a88d5d | 2557 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2558 | gen_op_load_fpr_FT1(rs2); |
44e7757c | 2559 | tcg_gen_helper_0_0(helper_fstoq); |
1f587329 BS |
2560 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2561 | break; | |
0f8a249a | 2562 | case 0xce: /* fdtoq */ |
64a88d5d | 2563 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2564 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
44e7757c | 2565 | tcg_gen_helper_0_0(helper_fdtoq); |
1f587329 BS |
2566 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2567 | break; | |
0f8a249a BS |
2568 | case 0xd1: |
2569 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2570 | gen_clear_float_exceptions(); |
44e7757c | 2571 | tcg_gen_helper_0_0(helper_fstoi); |
7e8c2b6c | 2572 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2573 | gen_op_store_FT0_fpr(rd); |
2574 | break; | |
2575 | case 0xd2: | |
2382dc6b | 2576 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
7e8c2b6c | 2577 | gen_clear_float_exceptions(); |
44e7757c | 2578 | tcg_gen_helper_0_0(helper_fdtoi); |
7e8c2b6c | 2579 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2580 | gen_op_store_FT0_fpr(rd); |
2581 | break; | |
2582 | case 0xd3: /* fqtoi */ | |
64a88d5d | 2583 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2584 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
7e8c2b6c | 2585 | gen_clear_float_exceptions(); |
44e7757c | 2586 | tcg_gen_helper_0_0(helper_fqtoi); |
7e8c2b6c | 2587 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2588 | gen_op_store_FT0_fpr(rd); |
2589 | break; | |
3475187d | 2590 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
2591 | case 0x2: /* V9 fmovd */ |
2592 | gen_op_load_fpr_DT0(DFPREG(rs2)); | |
2593 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
2594 | break; | |
1f587329 | 2595 | case 0x3: /* V9 fmovq */ |
64a88d5d | 2596 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 BS |
2597 | gen_op_load_fpr_QT0(QFPREG(rs2)); |
2598 | gen_op_store_QT0_fpr(QFPREG(rd)); | |
2599 | break; | |
0f8a249a BS |
2600 | case 0x6: /* V9 fnegd */ |
2601 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 2602 | tcg_gen_helper_0_0(helper_fnegd); |
0f8a249a BS |
2603 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2604 | break; | |
1f587329 | 2605 | case 0x7: /* V9 fnegq */ |
64a88d5d | 2606 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2607 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
44e7757c | 2608 | tcg_gen_helper_0_0(helper_fnegq); |
1f587329 BS |
2609 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2610 | break; | |
0f8a249a BS |
2611 | case 0xa: /* V9 fabsd */ |
2612 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2613 | tcg_gen_helper_0_0(helper_fabsd); |
0f8a249a BS |
2614 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2615 | break; | |
1f587329 | 2616 | case 0xb: /* V9 fabsq */ |
64a88d5d | 2617 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2618 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
7e8c2b6c | 2619 | tcg_gen_helper_0_0(helper_fabsq); |
1f587329 BS |
2620 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2621 | break; | |
0f8a249a BS |
2622 | case 0x81: /* V9 fstox */ |
2623 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2624 | gen_clear_float_exceptions(); |
44e7757c | 2625 | tcg_gen_helper_0_0(helper_fstox); |
7e8c2b6c | 2626 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2627 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2628 | break; | |
2629 | case 0x82: /* V9 fdtox */ | |
2630 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2631 | gen_clear_float_exceptions(); |
44e7757c | 2632 | tcg_gen_helper_0_0(helper_fdtox); |
7e8c2b6c | 2633 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2634 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2635 | break; | |
1f587329 | 2636 | case 0x83: /* V9 fqtox */ |
64a88d5d | 2637 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2638 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
7e8c2b6c | 2639 | gen_clear_float_exceptions(); |
44e7757c | 2640 | tcg_gen_helper_0_0(helper_fqtox); |
7e8c2b6c | 2641 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2642 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2643 | break; | |
0f8a249a BS |
2644 | case 0x84: /* V9 fxtos */ |
2645 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2646 | gen_clear_float_exceptions(); |
44e7757c | 2647 | tcg_gen_helper_0_0(helper_fxtos); |
7e8c2b6c | 2648 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2649 | gen_op_store_FT0_fpr(rd); |
2650 | break; | |
2651 | case 0x88: /* V9 fxtod */ | |
2652 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2653 | gen_clear_float_exceptions(); |
44e7757c | 2654 | tcg_gen_helper_0_0(helper_fxtod); |
7e8c2b6c | 2655 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2656 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2657 | break; | |
0f8a249a | 2658 | case 0x8c: /* V9 fxtoq */ |
64a88d5d | 2659 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2660 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
7e8c2b6c | 2661 | gen_clear_float_exceptions(); |
44e7757c | 2662 | tcg_gen_helper_0_0(helper_fxtoq); |
7e8c2b6c | 2663 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2664 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2665 | break; | |
0f8a249a BS |
2666 | #endif |
2667 | default: | |
2668 | goto illegal_insn; | |
2669 | } | |
2670 | } else if (xop == 0x35) { /* FPU Operations */ | |
3475187d | 2671 | #ifdef TARGET_SPARC64 |
0f8a249a | 2672 | int cond; |
3475187d | 2673 | #endif |
6ae20372 | 2674 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
a80dde08 | 2675 | goto jmp_insn; |
0f8a249a | 2676 | gen_op_clear_ieee_excp_and_FTT(); |
cf495bcf | 2677 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a BS |
2678 | rs2 = GET_FIELD(insn, 27, 31); |
2679 | xop = GET_FIELD(insn, 18, 26); | |
3475187d | 2680 | #ifdef TARGET_SPARC64 |
0f8a249a | 2681 | if ((xop & 0x11f) == 0x005) { // V9 fmovsr |
dcf24905 BS |
2682 | int l1; |
2683 | ||
2684 | l1 = gen_new_label(); | |
0f8a249a | 2685 | cond = GET_FIELD_SP(insn, 14, 17); |
9322a4bf | 2686 | cpu_src1 = get_src1(insn, cpu_src1); |
cb63669a PB |
2687 | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2688 | 0, l1); | |
19f329ad | 2689 | gen_op_load_fpr_FT0(rs2); |
0f8a249a | 2690 | gen_op_store_FT0_fpr(rd); |
dcf24905 | 2691 | gen_set_label(l1); |
0f8a249a BS |
2692 | break; |
2693 | } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr | |
dcf24905 BS |
2694 | int l1; |
2695 | ||
2696 | l1 = gen_new_label(); | |
0f8a249a | 2697 | cond = GET_FIELD_SP(insn, 14, 17); |
9322a4bf | 2698 | cpu_src1 = get_src1(insn, cpu_src1); |
cb63669a PB |
2699 | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2700 | 0, l1); | |
19f329ad | 2701 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
2382dc6b | 2702 | gen_op_store_DT0_fpr(DFPREG(rd)); |
dcf24905 | 2703 | gen_set_label(l1); |
0f8a249a BS |
2704 | break; |
2705 | } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr | |
dcf24905 BS |
2706 | int l1; |
2707 | ||
64a88d5d | 2708 | CHECK_FPU_FEATURE(dc, FLOAT128); |
dcf24905 | 2709 | l1 = gen_new_label(); |
1f587329 | 2710 | cond = GET_FIELD_SP(insn, 14, 17); |
9322a4bf | 2711 | cpu_src1 = get_src1(insn, cpu_src1); |
cb63669a PB |
2712 | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2713 | 0, l1); | |
19f329ad | 2714 | gen_op_load_fpr_QT0(QFPREG(rs2)); |
1f587329 | 2715 | gen_op_store_QT0_fpr(QFPREG(rd)); |
dcf24905 | 2716 | gen_set_label(l1); |
1f587329 | 2717 | break; |
0f8a249a BS |
2718 | } |
2719 | #endif | |
2720 | switch (xop) { | |
3475187d | 2721 | #ifdef TARGET_SPARC64 |
19f329ad BS |
2722 | #define FMOVCC(size_FDQ, fcc) \ |
2723 | { \ | |
0425bee5 | 2724 | TCGv r_cond; \ |
19f329ad BS |
2725 | int l1; \ |
2726 | \ | |
2727 | l1 = gen_new_label(); \ | |
19f329ad | 2728 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ |
19f329ad BS |
2729 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2730 | gen_fcond(r_cond, fcc, cond); \ | |
cb63669a PB |
2731 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2732 | 0, l1); \ | |
77f193da BS |
2733 | glue(glue(gen_op_load_fpr_, size_FDQ), T0) \ |
2734 | (glue(size_FDQ, FPREG(rs2))); \ | |
2735 | glue(glue(gen_op_store_, size_FDQ), T0_fpr) \ | |
2736 | (glue(size_FDQ, FPREG(rd))); \ | |
19f329ad | 2737 | gen_set_label(l1); \ |
2ea815ca | 2738 | tcg_temp_free(r_cond); \ |
19f329ad | 2739 | } |
0f8a249a | 2740 | case 0x001: /* V9 fmovscc %fcc0 */ |
19f329ad | 2741 | FMOVCC(F, 0); |
0f8a249a BS |
2742 | break; |
2743 | case 0x002: /* V9 fmovdcc %fcc0 */ | |
19f329ad | 2744 | FMOVCC(D, 0); |
0f8a249a BS |
2745 | break; |
2746 | case 0x003: /* V9 fmovqcc %fcc0 */ | |
64a88d5d | 2747 | CHECK_FPU_FEATURE(dc, FLOAT128); |
19f329ad | 2748 | FMOVCC(Q, 0); |
1f587329 | 2749 | break; |
0f8a249a | 2750 | case 0x041: /* V9 fmovscc %fcc1 */ |
19f329ad | 2751 | FMOVCC(F, 1); |
0f8a249a BS |
2752 | break; |
2753 | case 0x042: /* V9 fmovdcc %fcc1 */ | |
19f329ad | 2754 | FMOVCC(D, 1); |
0f8a249a BS |
2755 | break; |
2756 | case 0x043: /* V9 fmovqcc %fcc1 */ | |
64a88d5d | 2757 | CHECK_FPU_FEATURE(dc, FLOAT128); |
19f329ad | 2758 | FMOVCC(Q, 1); |
1f587329 | 2759 | break; |
0f8a249a | 2760 | case 0x081: /* V9 fmovscc %fcc2 */ |
19f329ad | 2761 | FMOVCC(F, 2); |
0f8a249a BS |
2762 | break; |
2763 | case 0x082: /* V9 fmovdcc %fcc2 */ | |
19f329ad | 2764 | FMOVCC(D, 2); |
0f8a249a BS |
2765 | break; |
2766 | case 0x083: /* V9 fmovqcc %fcc2 */ | |
64a88d5d | 2767 | CHECK_FPU_FEATURE(dc, FLOAT128); |
19f329ad | 2768 | FMOVCC(Q, 2); |
1f587329 | 2769 | break; |
0f8a249a | 2770 | case 0x0c1: /* V9 fmovscc %fcc3 */ |
19f329ad | 2771 | FMOVCC(F, 3); |
0f8a249a BS |
2772 | break; |
2773 | case 0x0c2: /* V9 fmovdcc %fcc3 */ | |
19f329ad | 2774 | FMOVCC(D, 3); |
0f8a249a BS |
2775 | break; |
2776 | case 0x0c3: /* V9 fmovqcc %fcc3 */ | |
64a88d5d | 2777 | CHECK_FPU_FEATURE(dc, FLOAT128); |
19f329ad | 2778 | FMOVCC(Q, 3); |
1f587329 | 2779 | break; |
19f329ad BS |
2780 | #undef FMOVCC |
2781 | #define FMOVCC(size_FDQ, icc) \ | |
2782 | { \ | |
0425bee5 | 2783 | TCGv r_cond; \ |
19f329ad BS |
2784 | int l1; \ |
2785 | \ | |
2786 | l1 = gen_new_label(); \ | |
19f329ad | 2787 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ |
19f329ad BS |
2788 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2789 | gen_cond(r_cond, icc, cond); \ | |
cb63669a PB |
2790 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2791 | 0, l1); \ | |
77f193da BS |
2792 | glue(glue(gen_op_load_fpr_, size_FDQ), T0) \ |
2793 | (glue(size_FDQ, FPREG(rs2))); \ | |
2794 | glue(glue(gen_op_store_, size_FDQ), T0_fpr) \ | |
2795 | (glue(size_FDQ, FPREG(rd))); \ | |
19f329ad | 2796 | gen_set_label(l1); \ |
2ea815ca | 2797 | tcg_temp_free(r_cond); \ |
19f329ad BS |
2798 | } |
2799 | ||
0f8a249a | 2800 | case 0x101: /* V9 fmovscc %icc */ |
19f329ad | 2801 | FMOVCC(F, 0); |
0f8a249a BS |
2802 | break; |
2803 | case 0x102: /* V9 fmovdcc %icc */ | |
19f329ad | 2804 | FMOVCC(D, 0); |
0f8a249a | 2805 | case 0x103: /* V9 fmovqcc %icc */ |
64a88d5d BS |
2806 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2807 | FMOVCC(Q, 0); | |
1f587329 | 2808 | break; |
0f8a249a | 2809 | case 0x181: /* V9 fmovscc %xcc */ |
19f329ad | 2810 | FMOVCC(F, 1); |
0f8a249a BS |
2811 | break; |
2812 | case 0x182: /* V9 fmovdcc %xcc */ | |
19f329ad | 2813 | FMOVCC(D, 1); |
0f8a249a BS |
2814 | break; |
2815 | case 0x183: /* V9 fmovqcc %xcc */ | |
64a88d5d | 2816 | CHECK_FPU_FEATURE(dc, FLOAT128); |
19f329ad | 2817 | FMOVCC(Q, 1); |
1f587329 | 2818 | break; |
19f329ad | 2819 | #undef FMOVCC |
1f587329 BS |
2820 | #endif |
2821 | case 0x51: /* fcmps, V9 %fcc */ | |
0f8a249a BS |
2822 | gen_op_load_fpr_FT0(rs1); |
2823 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2824 | gen_op_fcmps(rd & 3); |
0f8a249a | 2825 | break; |
1f587329 | 2826 | case 0x52: /* fcmpd, V9 %fcc */ |
0f8a249a BS |
2827 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2828 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2829 | gen_op_fcmpd(rd & 3); |
0f8a249a | 2830 | break; |
1f587329 | 2831 | case 0x53: /* fcmpq, V9 %fcc */ |
64a88d5d | 2832 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 BS |
2833 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2834 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2835 | gen_op_fcmpq(rd & 3); |
1f587329 | 2836 | break; |
0f8a249a BS |
2837 | case 0x55: /* fcmpes, V9 %fcc */ |
2838 | gen_op_load_fpr_FT0(rs1); | |
2839 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2840 | gen_op_fcmpes(rd & 3); |
0f8a249a BS |
2841 | break; |
2842 | case 0x56: /* fcmped, V9 %fcc */ | |
2843 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
2844 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2845 | gen_op_fcmped(rd & 3); |
0f8a249a | 2846 | break; |
1f587329 | 2847 | case 0x57: /* fcmpeq, V9 %fcc */ |
64a88d5d | 2848 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 BS |
2849 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2850 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2851 | gen_op_fcmpeq(rd & 3); |
1f587329 | 2852 | break; |
0f8a249a BS |
2853 | default: |
2854 | goto illegal_insn; | |
2855 | } | |
0f8a249a BS |
2856 | } else if (xop == 0x2) { |
2857 | // clr/mov shortcut | |
e80cfcfc FB |
2858 | |
2859 | rs1 = GET_FIELD(insn, 13, 17); | |
0f8a249a | 2860 | if (rs1 == 0) { |
1a2fb1c0 | 2861 | // or %g0, x, y -> mov T0, x; mov y, T0 |
0f8a249a | 2862 | if (IS_IMM) { /* immediate */ |
2ea815ca BS |
2863 | TCGv r_const; |
2864 | ||
0f8a249a | 2865 | rs2 = GET_FIELDs(insn, 19, 31); |
2ea815ca BS |
2866 | r_const = tcg_const_tl((int)rs2); |
2867 | gen_movl_TN_reg(rd, r_const); | |
2868 | tcg_temp_free(r_const); | |
0f8a249a BS |
2869 | } else { /* register */ |
2870 | rs2 = GET_FIELD(insn, 27, 31); | |
6ae20372 | 2871 | gen_movl_reg_TN(rs2, cpu_dst); |
9c6c6662 | 2872 | gen_movl_TN_reg(rd, cpu_dst); |
0f8a249a | 2873 | } |
0f8a249a | 2874 | } else { |
9322a4bf | 2875 | cpu_src1 = get_src1(insn, cpu_src1); |
0f8a249a | 2876 | if (IS_IMM) { /* immediate */ |
0f8a249a | 2877 | rs2 = GET_FIELDs(insn, 19, 31); |
6ae20372 | 2878 | tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2); |
9c6c6662 | 2879 | gen_movl_TN_reg(rd, cpu_dst); |
0f8a249a BS |
2880 | } else { /* register */ |
2881 | // or x, %g0, y -> mov T1, x; mov y, T1 | |
2882 | rs2 = GET_FIELD(insn, 27, 31); | |
2883 | if (rs2 != 0) { | |
6ae20372 BS |
2884 | gen_movl_reg_TN(rs2, cpu_src2); |
2885 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); | |
9c6c6662 | 2886 | gen_movl_TN_reg(rd, cpu_dst); |
6f551262 | 2887 | } else |
9c6c6662 | 2888 | gen_movl_TN_reg(rd, cpu_src1); |
0f8a249a | 2889 | } |
0f8a249a | 2890 | } |
83469015 | 2891 | #ifdef TARGET_SPARC64 |
0f8a249a | 2892 | } else if (xop == 0x25) { /* sll, V9 sllx */ |
9322a4bf | 2893 | cpu_src1 = get_src1(insn, cpu_src1); |
0f8a249a | 2894 | if (IS_IMM) { /* immediate */ |
83469015 | 2895 | rs2 = GET_FIELDs(insn, 20, 31); |
1a2fb1c0 | 2896 | if (insn & (1 << 12)) { |
6ae20372 | 2897 | tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f); |
1a2fb1c0 | 2898 | } else { |
01b1fa6d | 2899 | tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x1f); |
1a2fb1c0 | 2900 | } |
0f8a249a | 2901 | } else { /* register */ |
83469015 | 2902 | rs2 = GET_FIELD(insn, 27, 31); |
6ae20372 | 2903 | gen_movl_reg_TN(rs2, cpu_src2); |
1a2fb1c0 | 2904 | if (insn & (1 << 12)) { |
6ae20372 | 2905 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); |
1a2fb1c0 | 2906 | } else { |
6ae20372 | 2907 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); |
1a2fb1c0 | 2908 | } |
01b1fa6d | 2909 | tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0); |
83469015 | 2910 | } |
6ae20372 | 2911 | gen_movl_TN_reg(rd, cpu_dst); |
0f8a249a | 2912 | } else if (xop == 0x26) { /* srl, V9 srlx */ |
9322a4bf | 2913 | cpu_src1 = get_src1(insn, cpu_src1); |
0f8a249a | 2914 | if (IS_IMM) { /* immediate */ |
83469015 | 2915 | rs2 = GET_FIELDs(insn, 20, 31); |
1a2fb1c0 | 2916 | if (insn & (1 << 12)) { |
6ae20372 | 2917 | tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f); |
1a2fb1c0 | 2918 | } else { |
6ae20372 BS |
2919 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); |
2920 | tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f); | |
1a2fb1c0 | 2921 | } |
0f8a249a | 2922 | } else { /* register */ |
83469015 | 2923 | rs2 = GET_FIELD(insn, 27, 31); |
6ae20372 | 2924 | gen_movl_reg_TN(rs2, cpu_src2); |
1a2fb1c0 | 2925 | if (insn & (1 << 12)) { |
6ae20372 BS |
2926 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); |
2927 | tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0); | |
1a2fb1c0 | 2928 | } else { |
6ae20372 BS |
2929 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); |
2930 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); | |
2931 | tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0); | |
1a2fb1c0 | 2932 | } |
83469015 | 2933 | } |
6ae20372 | 2934 | gen_movl_TN_reg(rd, cpu_dst); |
0f8a249a | 2935 | } else if (xop == 0x27) { /* sra, V9 srax */ |
9322a4bf | 2936 | cpu_src1 = get_src1(insn, cpu_src1); |
0f8a249a | 2937 | if (IS_IMM) { /* immediate */ |
83469015 | 2938 | rs2 = GET_FIELDs(insn, 20, 31); |
1a2fb1c0 | 2939 | if (insn & (1 << 12)) { |
6ae20372 | 2940 | tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f); |
1a2fb1c0 | 2941 | } else { |
6ae20372 BS |
2942 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); |
2943 | tcg_gen_ext_i32_i64(cpu_dst, cpu_dst); | |
2944 | tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f); | |
1a2fb1c0 | 2945 | } |
0f8a249a | 2946 | } else { /* register */ |
83469015 | 2947 | rs2 = GET_FIELD(insn, 27, 31); |
6ae20372 | 2948 | gen_movl_reg_TN(rs2, cpu_src2); |
1a2fb1c0 | 2949 | if (insn & (1 << 12)) { |
6ae20372 BS |
2950 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); |
2951 | tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0); | |
1a2fb1c0 | 2952 | } else { |
6ae20372 BS |
2953 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); |
2954 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); | |
01b1fa6d | 2955 | tcg_gen_ext_i32_i64(cpu_dst, cpu_dst); |
6ae20372 | 2956 | tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0); |
1a2fb1c0 | 2957 | } |
83469015 | 2958 | } |
6ae20372 | 2959 | gen_movl_TN_reg(rd, cpu_dst); |
e80cfcfc | 2960 | #endif |
fcc72045 | 2961 | } else if (xop < 0x36) { |
9322a4bf | 2962 | cpu_src1 = get_src1(insn, cpu_src1); |
a49d9390 | 2963 | cpu_src2 = get_src2(insn, cpu_src2); |
cf495bcf FB |
2964 | if (xop < 0x20) { |
2965 | switch (xop & ~0x10) { | |
2966 | case 0x0: | |
2967 | if (xop & 0x10) | |
6ae20372 | 2968 | gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf | 2969 | else |
6ae20372 | 2970 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf FB |
2971 | break; |
2972 | case 0x1: | |
6ae20372 | 2973 | tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf | 2974 | if (xop & 0x10) |
6ae20372 | 2975 | gen_op_logic_cc(cpu_dst); |
cf495bcf FB |
2976 | break; |
2977 | case 0x2: | |
6ae20372 | 2978 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); |
0f8a249a | 2979 | if (xop & 0x10) |
6ae20372 | 2980 | gen_op_logic_cc(cpu_dst); |
0f8a249a | 2981 | break; |
cf495bcf | 2982 | case 0x3: |
6ae20372 | 2983 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf | 2984 | if (xop & 0x10) |
6ae20372 | 2985 | gen_op_logic_cc(cpu_dst); |
cf495bcf FB |
2986 | break; |
2987 | case 0x4: | |
2988 | if (xop & 0x10) | |
6ae20372 | 2989 | gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf | 2990 | else |
6ae20372 | 2991 | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf FB |
2992 | break; |
2993 | case 0x5: | |
6ae20372 BS |
2994 | tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1); |
2995 | tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
cf495bcf | 2996 | if (xop & 0x10) |
6ae20372 | 2997 | gen_op_logic_cc(cpu_dst); |
cf495bcf FB |
2998 | break; |
2999 | case 0x6: | |
6ae20372 BS |
3000 | tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1); |
3001 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
cf495bcf | 3002 | if (xop & 0x10) |
6ae20372 | 3003 | gen_op_logic_cc(cpu_dst); |
cf495bcf FB |
3004 | break; |
3005 | case 0x7: | |
6ae20372 BS |
3006 | tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1); |
3007 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
cf495bcf | 3008 | if (xop & 0x10) |
6ae20372 | 3009 | gen_op_logic_cc(cpu_dst); |
cf495bcf FB |
3010 | break; |
3011 | case 0x8: | |
cf495bcf | 3012 | if (xop & 0x10) |
6ae20372 | 3013 | gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2); |
38bc628b | 3014 | else { |
dc99a3f2 | 3015 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
6ae20372 BS |
3016 | tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0); |
3017 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
38bc628b | 3018 | } |
cf495bcf | 3019 | break; |
ded3ab80 | 3020 | #ifdef TARGET_SPARC64 |
0f8a249a | 3021 | case 0x9: /* V9 mulx */ |
6ae20372 | 3022 | tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2); |
ded3ab80 PB |
3023 | break; |
3024 | #endif | |
cf495bcf | 3025 | case 0xa: |
64a88d5d | 3026 | CHECK_IU_FEATURE(dc, MUL); |
6ae20372 | 3027 | gen_op_umul(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf | 3028 | if (xop & 0x10) |
6ae20372 | 3029 | gen_op_logic_cc(cpu_dst); |
cf495bcf FB |
3030 | break; |
3031 | case 0xb: | |
64a88d5d | 3032 | CHECK_IU_FEATURE(dc, MUL); |
6ae20372 | 3033 | gen_op_smul(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf | 3034 | if (xop & 0x10) |
6ae20372 | 3035 | gen_op_logic_cc(cpu_dst); |
cf495bcf FB |
3036 | break; |
3037 | case 0xc: | |
cf495bcf | 3038 | if (xop & 0x10) |
6ae20372 | 3039 | gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2); |
38bc628b | 3040 | else { |
dc99a3f2 | 3041 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
6ae20372 BS |
3042 | tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0); |
3043 | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
38bc628b | 3044 | } |
cf495bcf | 3045 | break; |
ded3ab80 | 3046 | #ifdef TARGET_SPARC64 |
0f8a249a | 3047 | case 0xd: /* V9 udivx */ |
07bf2857 BS |
3048 | tcg_gen_mov_tl(cpu_cc_src, cpu_src1); |
3049 | tcg_gen_mov_tl(cpu_cc_src2, cpu_src2); | |
3050 | gen_trap_ifdivzero_tl(cpu_cc_src2); | |
3051 | tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2); | |
ded3ab80 PB |
3052 | break; |
3053 | #endif | |
cf495bcf | 3054 | case 0xe: |
64a88d5d | 3055 | CHECK_IU_FEATURE(dc, DIV); |
77f193da BS |
3056 | tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1, |
3057 | cpu_src2); | |
cf495bcf | 3058 | if (xop & 0x10) |
6ae20372 | 3059 | gen_op_div_cc(cpu_dst); |
cf495bcf FB |
3060 | break; |
3061 | case 0xf: | |
64a88d5d | 3062 | CHECK_IU_FEATURE(dc, DIV); |
77f193da BS |
3063 | tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1, |
3064 | cpu_src2); | |
cf495bcf | 3065 | if (xop & 0x10) |
6ae20372 | 3066 | gen_op_div_cc(cpu_dst); |
cf495bcf FB |
3067 | break; |
3068 | default: | |
3069 | goto illegal_insn; | |
3070 | } | |
6ae20372 | 3071 | gen_movl_TN_reg(rd, cpu_dst); |
cf495bcf FB |
3072 | } else { |
3073 | switch (xop) { | |
0f8a249a | 3074 | case 0x20: /* taddcc */ |
6ae20372 BS |
3075 | gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2); |
3076 | gen_movl_TN_reg(rd, cpu_dst); | |
0f8a249a BS |
3077 | break; |
3078 | case 0x21: /* tsubcc */ | |
6ae20372 BS |
3079 | gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2); |
3080 | gen_movl_TN_reg(rd, cpu_dst); | |
0f8a249a BS |
3081 | break; |
3082 | case 0x22: /* taddcctv */ | |
6ae20372 BS |
3083 | save_state(dc, cpu_cond); |
3084 | gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2); | |
3085 | gen_movl_TN_reg(rd, cpu_dst); | |
0f8a249a BS |
3086 | break; |
3087 | case 0x23: /* tsubcctv */ | |
6ae20372 BS |
3088 | save_state(dc, cpu_cond); |
3089 | gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2); | |
3090 | gen_movl_TN_reg(rd, cpu_dst); | |
0f8a249a | 3091 | break; |
cf495bcf | 3092 | case 0x24: /* mulscc */ |
6ae20372 BS |
3093 | gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2); |
3094 | gen_movl_TN_reg(rd, cpu_dst); | |
cf495bcf | 3095 | break; |
83469015 | 3096 | #ifndef TARGET_SPARC64 |
0f8a249a | 3097 | case 0x25: /* sll */ |
e35298cd BS |
3098 | if (IS_IMM) { /* immediate */ |
3099 | rs2 = GET_FIELDs(insn, 20, 31); | |
3100 | tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f); | |
3101 | } else { /* register */ | |
3102 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); | |
3103 | tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
3104 | } | |
6ae20372 | 3105 | gen_movl_TN_reg(rd, cpu_dst); |
cf495bcf | 3106 | break; |
83469015 | 3107 | case 0x26: /* srl */ |
e35298cd BS |
3108 | if (IS_IMM) { /* immediate */ |
3109 | rs2 = GET_FIELDs(insn, 20, 31); | |
3110 | tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f); | |
3111 | } else { /* register */ | |
3112 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); | |
3113 | tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
3114 | } | |
6ae20372 | 3115 | gen_movl_TN_reg(rd, cpu_dst); |
cf495bcf | 3116 | break; |
83469015 | 3117 | case 0x27: /* sra */ |
e35298cd BS |
3118 | if (IS_IMM) { /* immediate */ |
3119 | rs2 = GET_FIELDs(insn, 20, 31); | |
3120 | tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f); | |
3121 | } else { /* register */ | |
3122 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); | |
3123 | tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
3124 | } | |
6ae20372 | 3125 | gen_movl_TN_reg(rd, cpu_dst); |
cf495bcf | 3126 | break; |
83469015 | 3127 | #endif |
cf495bcf FB |
3128 | case 0x30: |
3129 | { | |
cf495bcf | 3130 | switch(rd) { |
3475187d | 3131 | case 0: /* wry */ |
255e1fcb | 3132 | tcg_gen_xor_tl(cpu_y, cpu_src1, cpu_src2); |
cf495bcf | 3133 | break; |
65fe7b09 BS |
3134 | #ifndef TARGET_SPARC64 |
3135 | case 0x01 ... 0x0f: /* undefined in the | |
3136 | SPARCv8 manual, nop | |
3137 | on the microSPARC | |
3138 | II */ | |
3139 | case 0x10 ... 0x1f: /* implementation-dependent | |
3140 | in the SPARCv8 | |
3141 | manual, nop on the | |
3142 | microSPARC II */ | |
3143 | break; | |
3144 | #else | |
0f8a249a | 3145 | case 0x2: /* V9 wrccr */ |
6ae20372 BS |
3146 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3147 | tcg_gen_helper_0_1(helper_wrccr, cpu_dst); | |
0f8a249a BS |
3148 | break; |
3149 | case 0x3: /* V9 wrasi */ | |
6ae20372 | 3150 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
255e1fcb | 3151 | tcg_gen_trunc_tl_i32(cpu_asi, cpu_dst); |
0f8a249a BS |
3152 | break; |
3153 | case 0x6: /* V9 wrfprs */ | |
6ae20372 | 3154 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
255e1fcb | 3155 | tcg_gen_trunc_tl_i32(cpu_fprs, cpu_dst); |
6ae20372 | 3156 | save_state(dc, cpu_cond); |
3299908c | 3157 | gen_op_next_insn(); |
57fec1fe | 3158 | tcg_gen_exit_tb(0); |
3299908c | 3159 | dc->is_br = 1; |
0f8a249a BS |
3160 | break; |
3161 | case 0xf: /* V9 sir, nop if user */ | |
3475187d | 3162 | #if !defined(CONFIG_USER_ONLY) |
0f8a249a | 3163 | if (supervisor(dc)) |
1a2fb1c0 | 3164 | ; // XXX |
3475187d | 3165 | #endif |
0f8a249a BS |
3166 | break; |
3167 | case 0x13: /* Graphics Status */ | |
6ae20372 | 3168 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
725cb90b | 3169 | goto jmp_insn; |
255e1fcb | 3170 | tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2); |
0f8a249a BS |
3171 | break; |
3172 | case 0x17: /* Tick compare */ | |
83469015 | 3173 | #if !defined(CONFIG_USER_ONLY) |
0f8a249a BS |
3174 | if (!supervisor(dc)) |
3175 | goto illegal_insn; | |
83469015 | 3176 | #endif |
ccd4a219 BS |
3177 | { |
3178 | TCGv r_tickptr; | |
3179 | ||
255e1fcb | 3180 | tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1, |
6ae20372 | 3181 | cpu_src2); |
ccd4a219 BS |
3182 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3183 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
3184 | offsetof(CPUState, tick)); | |
3185 | tcg_gen_helper_0_2(helper_tick_set_limit, | |
255e1fcb | 3186 | r_tickptr, cpu_tick_cmpr); |
2ea815ca | 3187 | tcg_temp_free(r_tickptr); |
ccd4a219 | 3188 | } |
0f8a249a BS |
3189 | break; |
3190 | case 0x18: /* System tick */ | |
83469015 | 3191 | #if !defined(CONFIG_USER_ONLY) |
0f8a249a BS |
3192 | if (!supervisor(dc)) |
3193 | goto illegal_insn; | |
83469015 | 3194 | #endif |
ccd4a219 BS |
3195 | { |
3196 | TCGv r_tickptr; | |
3197 | ||
6ae20372 BS |
3198 | tcg_gen_xor_tl(cpu_dst, cpu_src1, |
3199 | cpu_src2); | |
ccd4a219 BS |
3200 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3201 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
3202 | offsetof(CPUState, stick)); | |
3203 | tcg_gen_helper_0_2(helper_tick_set_count, | |
6ae20372 | 3204 | r_tickptr, cpu_dst); |
2ea815ca | 3205 | tcg_temp_free(r_tickptr); |
ccd4a219 | 3206 | } |
0f8a249a BS |
3207 | break; |
3208 | case 0x19: /* System tick compare */ | |
83469015 | 3209 | #if !defined(CONFIG_USER_ONLY) |
0f8a249a BS |
3210 | if (!supervisor(dc)) |
3211 | goto illegal_insn; | |
3475187d | 3212 | #endif |
ccd4a219 BS |
3213 | { |
3214 | TCGv r_tickptr; | |
3215 | ||
255e1fcb | 3216 | tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1, |
6ae20372 | 3217 | cpu_src2); |
ccd4a219 BS |
3218 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3219 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
3220 | offsetof(CPUState, stick)); | |
3221 | tcg_gen_helper_0_2(helper_tick_set_limit, | |
255e1fcb | 3222 | r_tickptr, cpu_stick_cmpr); |
2ea815ca | 3223 | tcg_temp_free(r_tickptr); |
ccd4a219 | 3224 | } |
0f8a249a | 3225 | break; |
83469015 | 3226 | |
0f8a249a | 3227 | case 0x10: /* Performance Control */ |
77f193da BS |
3228 | case 0x11: /* Performance Instrumentation |
3229 | Counter */ | |
0f8a249a BS |
3230 | case 0x12: /* Dispatch Control */ |
3231 | case 0x14: /* Softint set */ | |
3232 | case 0x15: /* Softint clear */ | |
3233 | case 0x16: /* Softint write */ | |
83469015 | 3234 | #endif |
3475187d | 3235 | default: |
cf495bcf FB |
3236 | goto illegal_insn; |
3237 | } | |
3238 | } | |
3239 | break; | |
e8af50a3 | 3240 | #if !defined(CONFIG_USER_ONLY) |
af7bf89b | 3241 | case 0x31: /* wrpsr, V9 saved, restored */ |
e8af50a3 | 3242 | { |
0f8a249a BS |
3243 | if (!supervisor(dc)) |
3244 | goto priv_insn; | |
3475187d | 3245 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
3246 | switch (rd) { |
3247 | case 0: | |
72a9747b | 3248 | tcg_gen_helper_0_0(helper_saved); |
0f8a249a BS |
3249 | break; |
3250 | case 1: | |
72a9747b | 3251 | tcg_gen_helper_0_0(helper_restored); |
0f8a249a | 3252 | break; |
e9ebed4d BS |
3253 | case 2: /* UA2005 allclean */ |
3254 | case 3: /* UA2005 otherw */ | |
3255 | case 4: /* UA2005 normalw */ | |
3256 | case 5: /* UA2005 invalw */ | |
3257 | // XXX | |
0f8a249a | 3258 | default: |
3475187d FB |
3259 | goto illegal_insn; |
3260 | } | |
3261 | #else | |
6ae20372 BS |
3262 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3263 | tcg_gen_helper_0_1(helper_wrpsr, cpu_dst); | |
3264 | save_state(dc, cpu_cond); | |
9e61bde5 | 3265 | gen_op_next_insn(); |
57fec1fe | 3266 | tcg_gen_exit_tb(0); |
0f8a249a | 3267 | dc->is_br = 1; |
3475187d | 3268 | #endif |
e8af50a3 FB |
3269 | } |
3270 | break; | |
af7bf89b | 3271 | case 0x32: /* wrwim, V9 wrpr */ |
e8af50a3 | 3272 | { |
0f8a249a BS |
3273 | if (!supervisor(dc)) |
3274 | goto priv_insn; | |
ece43b8d | 3275 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3475187d | 3276 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
3277 | switch (rd) { |
3278 | case 0: // tpc | |
375ee38b BS |
3279 | { |
3280 | TCGv r_tsptr; | |
3281 | ||
3282 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
3283 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
3284 | offsetof(CPUState, tsptr)); | |
ece43b8d | 3285 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
375ee38b | 3286 | offsetof(trap_state, tpc)); |
2ea815ca | 3287 | tcg_temp_free(r_tsptr); |
375ee38b | 3288 | } |
0f8a249a BS |
3289 | break; |
3290 | case 1: // tnpc | |
375ee38b BS |
3291 | { |
3292 | TCGv r_tsptr; | |
3293 | ||
3294 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
3295 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
3296 | offsetof(CPUState, tsptr)); | |
ece43b8d | 3297 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
375ee38b | 3298 | offsetof(trap_state, tnpc)); |
2ea815ca | 3299 | tcg_temp_free(r_tsptr); |
375ee38b | 3300 | } |
0f8a249a BS |
3301 | break; |
3302 | case 2: // tstate | |
375ee38b BS |
3303 | { |
3304 | TCGv r_tsptr; | |
3305 | ||
3306 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
3307 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
3308 | offsetof(CPUState, tsptr)); | |
ece43b8d | 3309 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
77f193da BS |
3310 | offsetof(trap_state, |
3311 | tstate)); | |
2ea815ca | 3312 | tcg_temp_free(r_tsptr); |
375ee38b | 3313 | } |
0f8a249a BS |
3314 | break; |
3315 | case 3: // tt | |
375ee38b BS |
3316 | { |
3317 | TCGv r_tsptr; | |
3318 | ||
3319 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
3320 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
3321 | offsetof(CPUState, tsptr)); | |
ece43b8d | 3322 | tcg_gen_st_i32(cpu_tmp0, r_tsptr, |
375ee38b | 3323 | offsetof(trap_state, tt)); |
2ea815ca | 3324 | tcg_temp_free(r_tsptr); |
375ee38b | 3325 | } |
0f8a249a BS |
3326 | break; |
3327 | case 4: // tick | |
ccd4a219 BS |
3328 | { |
3329 | TCGv r_tickptr; | |
3330 | ||
3331 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
3332 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
3333 | offsetof(CPUState, tick)); | |
3334 | tcg_gen_helper_0_2(helper_tick_set_count, | |
ece43b8d | 3335 | r_tickptr, cpu_tmp0); |
2ea815ca | 3336 | tcg_temp_free(r_tickptr); |
ccd4a219 | 3337 | } |
0f8a249a BS |
3338 | break; |
3339 | case 5: // tba | |
255e1fcb | 3340 | tcg_gen_mov_tl(cpu_tbr, cpu_tmp0); |
0f8a249a BS |
3341 | break; |
3342 | case 6: // pstate | |
6ae20372 | 3343 | save_state(dc, cpu_cond); |
ece43b8d | 3344 | tcg_gen_helper_0_1(helper_wrpstate, cpu_tmp0); |
ded3ab80 | 3345 | gen_op_next_insn(); |
57fec1fe | 3346 | tcg_gen_exit_tb(0); |
ded3ab80 | 3347 | dc->is_br = 1; |
0f8a249a BS |
3348 | break; |
3349 | case 7: // tl | |
ece43b8d | 3350 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
77f193da BS |
3351 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3352 | offsetof(CPUSPARCState, tl)); | |
0f8a249a BS |
3353 | break; |
3354 | case 8: // pil | |
ece43b8d | 3355 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
77f193da BS |
3356 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3357 | offsetof(CPUSPARCState, | |
3358 | psrpil)); | |
0f8a249a BS |
3359 | break; |
3360 | case 9: // cwp | |
ece43b8d | 3361 | tcg_gen_helper_0_1(helper_wrcwp, cpu_tmp0); |
0f8a249a BS |
3362 | break; |
3363 | case 10: // cansave | |
ece43b8d | 3364 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
77f193da BS |
3365 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3366 | offsetof(CPUSPARCState, | |
3367 | cansave)); | |
0f8a249a BS |
3368 | break; |
3369 | case 11: // canrestore | |
ece43b8d | 3370 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
77f193da BS |
3371 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3372 | offsetof(CPUSPARCState, | |
3373 | canrestore)); | |
0f8a249a BS |
3374 | break; |
3375 | case 12: // cleanwin | |
ece43b8d | 3376 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
77f193da BS |
3377 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3378 | offsetof(CPUSPARCState, | |
3379 | cleanwin)); | |
0f8a249a BS |
3380 | break; |
3381 | case 13: // otherwin | |
ece43b8d | 3382 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
77f193da BS |
3383 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3384 | offsetof(CPUSPARCState, | |
3385 | otherwin)); | |
0f8a249a BS |
3386 | break; |
3387 | case 14: // wstate | |
ece43b8d | 3388 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
77f193da BS |
3389 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3390 | offsetof(CPUSPARCState, | |
3391 | wstate)); | |
0f8a249a | 3392 | break; |
e9ebed4d | 3393 | case 16: // UA2005 gl |
fb79ceb9 | 3394 | CHECK_IU_FEATURE(dc, GL); |
ece43b8d | 3395 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
77f193da BS |
3396 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3397 | offsetof(CPUSPARCState, gl)); | |
e9ebed4d BS |
3398 | break; |
3399 | case 26: // UA2005 strand status | |
fb79ceb9 | 3400 | CHECK_IU_FEATURE(dc, HYPV); |
e9ebed4d BS |
3401 | if (!hypervisor(dc)) |
3402 | goto priv_insn; | |
255e1fcb | 3403 | tcg_gen_trunc_tl_i32(cpu_ssr, cpu_tmp0); |
e9ebed4d | 3404 | break; |
0f8a249a BS |
3405 | default: |
3406 | goto illegal_insn; | |
3407 | } | |
3475187d | 3408 | #else |
ece43b8d | 3409 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
c93e7817 BS |
3410 | if (dc->def->nwindows != 32) |
3411 | tcg_gen_andi_tl(cpu_tmp32, cpu_tmp32, | |
3412 | (1 << dc->def->nwindows) - 1); | |
255e1fcb | 3413 | tcg_gen_mov_i32(cpu_wim, cpu_tmp32); |
3475187d | 3414 | #endif |
e8af50a3 FB |
3415 | } |
3416 | break; | |
e9ebed4d | 3417 | case 0x33: /* wrtbr, UA2005 wrhpr */ |
e8af50a3 | 3418 | { |
e9ebed4d | 3419 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
3420 | if (!supervisor(dc)) |
3421 | goto priv_insn; | |
255e1fcb | 3422 | tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2); |
e9ebed4d | 3423 | #else |
fb79ceb9 | 3424 | CHECK_IU_FEATURE(dc, HYPV); |
e9ebed4d BS |
3425 | if (!hypervisor(dc)) |
3426 | goto priv_insn; | |
ece43b8d | 3427 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
e9ebed4d BS |
3428 | switch (rd) { |
3429 | case 0: // hpstate | |
3430 | // XXX gen_op_wrhpstate(); | |
6ae20372 | 3431 | save_state(dc, cpu_cond); |
e9ebed4d | 3432 | gen_op_next_insn(); |
57fec1fe | 3433 | tcg_gen_exit_tb(0); |
e9ebed4d BS |
3434 | dc->is_br = 1; |
3435 | break; | |
3436 | case 1: // htstate | |
3437 | // XXX gen_op_wrhtstate(); | |
3438 | break; | |
3439 | case 3: // hintp | |
255e1fcb | 3440 | tcg_gen_mov_tl(cpu_hintp, cpu_tmp0); |
e9ebed4d BS |
3441 | break; |
3442 | case 5: // htba | |
255e1fcb | 3443 | tcg_gen_mov_tl(cpu_htba, cpu_tmp0); |
e9ebed4d BS |
3444 | break; |
3445 | case 31: // hstick_cmpr | |
ccd4a219 BS |
3446 | { |
3447 | TCGv r_tickptr; | |
3448 | ||
255e1fcb | 3449 | tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0); |
ccd4a219 BS |
3450 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3451 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
3452 | offsetof(CPUState, hstick)); | |
3453 | tcg_gen_helper_0_2(helper_tick_set_limit, | |
255e1fcb | 3454 | r_tickptr, cpu_hstick_cmpr); |
2ea815ca | 3455 | tcg_temp_free(r_tickptr); |
ccd4a219 | 3456 | } |
e9ebed4d BS |
3457 | break; |
3458 | case 6: // hver readonly | |
3459 | default: | |
3460 | goto illegal_insn; | |
3461 | } | |
3462 | #endif | |
e8af50a3 FB |
3463 | } |
3464 | break; | |
3465 | #endif | |
3475187d | 3466 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
3467 | case 0x2c: /* V9 movcc */ |
3468 | { | |
3469 | int cc = GET_FIELD_SP(insn, 11, 12); | |
3470 | int cond = GET_FIELD_SP(insn, 14, 17); | |
748b9d8e | 3471 | TCGv r_cond; |
00f219bf BS |
3472 | int l1; |
3473 | ||
748b9d8e | 3474 | r_cond = tcg_temp_new(TCG_TYPE_TL); |
0f8a249a BS |
3475 | if (insn & (1 << 18)) { |
3476 | if (cc == 0) | |
748b9d8e | 3477 | gen_cond(r_cond, 0, cond); |
0f8a249a | 3478 | else if (cc == 2) |
748b9d8e | 3479 | gen_cond(r_cond, 1, cond); |
0f8a249a BS |
3480 | else |
3481 | goto illegal_insn; | |
3482 | } else { | |
748b9d8e | 3483 | gen_fcond(r_cond, cc, cond); |
0f8a249a | 3484 | } |
00f219bf BS |
3485 | |
3486 | l1 = gen_new_label(); | |
3487 | ||
cb63669a | 3488 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1); |
00f219bf | 3489 | if (IS_IMM) { /* immediate */ |
2ea815ca BS |
3490 | TCGv r_const; |
3491 | ||
00f219bf | 3492 | rs2 = GET_FIELD_SPs(insn, 0, 10); |
2ea815ca BS |
3493 | r_const = tcg_const_tl((int)rs2); |
3494 | gen_movl_TN_reg(rd, r_const); | |
3495 | tcg_temp_free(r_const); | |
00f219bf BS |
3496 | } else { |
3497 | rs2 = GET_FIELD_SP(insn, 0, 4); | |
9c6c6662 BS |
3498 | gen_movl_reg_TN(rs2, cpu_tmp0); |
3499 | gen_movl_TN_reg(rd, cpu_tmp0); | |
00f219bf | 3500 | } |
00f219bf | 3501 | gen_set_label(l1); |
2ea815ca | 3502 | tcg_temp_free(r_cond); |
0f8a249a BS |
3503 | break; |
3504 | } | |
3505 | case 0x2d: /* V9 sdivx */ | |
6ae20372 BS |
3506 | gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2); |
3507 | gen_movl_TN_reg(rd, cpu_dst); | |
0f8a249a BS |
3508 | break; |
3509 | case 0x2e: /* V9 popc */ | |
3510 | { | |
a49d9390 | 3511 | cpu_src2 = get_src2(insn, cpu_src2); |
6ae20372 BS |
3512 | tcg_gen_helper_1_1(helper_popc, cpu_dst, |
3513 | cpu_src2); | |
3514 | gen_movl_TN_reg(rd, cpu_dst); | |
0f8a249a BS |
3515 | } |
3516 | case 0x2f: /* V9 movr */ | |
3517 | { | |
3518 | int cond = GET_FIELD_SP(insn, 10, 12); | |
00f219bf BS |
3519 | int l1; |
3520 | ||
9322a4bf | 3521 | cpu_src1 = get_src1(insn, cpu_src1); |
00f219bf BS |
3522 | |
3523 | l1 = gen_new_label(); | |
3524 | ||
cb63669a PB |
3525 | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], |
3526 | cpu_src1, 0, l1); | |
0f8a249a | 3527 | if (IS_IMM) { /* immediate */ |
2ea815ca BS |
3528 | TCGv r_const; |
3529 | ||
0f8a249a | 3530 | rs2 = GET_FIELD_SPs(insn, 0, 9); |
2ea815ca BS |
3531 | r_const = tcg_const_tl((int)rs2); |
3532 | gen_movl_TN_reg(rd, r_const); | |
3533 | tcg_temp_free(r_const); | |
00f219bf | 3534 | } else { |
0f8a249a | 3535 | rs2 = GET_FIELD_SP(insn, 0, 4); |
9c6c6662 BS |
3536 | gen_movl_reg_TN(rs2, cpu_tmp0); |
3537 | gen_movl_TN_reg(rd, cpu_tmp0); | |
0f8a249a | 3538 | } |
00f219bf | 3539 | gen_set_label(l1); |
0f8a249a BS |
3540 | break; |
3541 | } | |
3542 | #endif | |
3543 | default: | |
3544 | goto illegal_insn; | |
3545 | } | |
3546 | } | |
3299908c BS |
3547 | } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ |
3548 | #ifdef TARGET_SPARC64 | |
3549 | int opf = GET_FIELD_SP(insn, 5, 13); | |
3550 | rs1 = GET_FIELD(insn, 13, 17); | |
3551 | rs2 = GET_FIELD(insn, 27, 31); | |
6ae20372 | 3552 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
e9ebed4d | 3553 | goto jmp_insn; |
3299908c BS |
3554 | |
3555 | switch (opf) { | |
e9ebed4d BS |
3556 | case 0x000: /* VIS I edge8cc */ |
3557 | case 0x001: /* VIS II edge8n */ | |
3558 | case 0x002: /* VIS I edge8lcc */ | |
3559 | case 0x003: /* VIS II edge8ln */ | |
3560 | case 0x004: /* VIS I edge16cc */ | |
3561 | case 0x005: /* VIS II edge16n */ | |
3562 | case 0x006: /* VIS I edge16lcc */ | |
3563 | case 0x007: /* VIS II edge16ln */ | |
3564 | case 0x008: /* VIS I edge32cc */ | |
3565 | case 0x009: /* VIS II edge32n */ | |
3566 | case 0x00a: /* VIS I edge32lcc */ | |
3567 | case 0x00b: /* VIS II edge32ln */ | |
3568 | // XXX | |
3569 | goto illegal_insn; | |
3570 | case 0x010: /* VIS I array8 */ | |
64a88d5d | 3571 | CHECK_FPU_FEATURE(dc, VIS1); |
9322a4bf | 3572 | cpu_src1 = get_src1(insn, cpu_src1); |
6ae20372 BS |
3573 | gen_movl_reg_TN(rs2, cpu_src2); |
3574 | tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1, | |
3575 | cpu_src2); | |
3576 | gen_movl_TN_reg(rd, cpu_dst); | |
e9ebed4d BS |
3577 | break; |
3578 | case 0x012: /* VIS I array16 */ | |
64a88d5d | 3579 | CHECK_FPU_FEATURE(dc, VIS1); |
9322a4bf | 3580 | cpu_src1 = get_src1(insn, cpu_src1); |
6ae20372 BS |
3581 | gen_movl_reg_TN(rs2, cpu_src2); |
3582 | tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1, | |
3583 | cpu_src2); | |
3584 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 1); | |
3585 | gen_movl_TN_reg(rd, cpu_dst); | |
e9ebed4d BS |
3586 | break; |
3587 | case 0x014: /* VIS I array32 */ | |
64a88d5d | 3588 | CHECK_FPU_FEATURE(dc, VIS1); |
9322a4bf | 3589 | cpu_src1 = get_src1(insn, cpu_src1); |
6ae20372 BS |
3590 | gen_movl_reg_TN(rs2, cpu_src2); |
3591 | tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1, | |
3592 | cpu_src2); | |
3593 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 2); | |
3594 | gen_movl_TN_reg(rd, cpu_dst); | |
e9ebed4d | 3595 | break; |
3299908c | 3596 | case 0x018: /* VIS I alignaddr */ |
64a88d5d | 3597 | CHECK_FPU_FEATURE(dc, VIS1); |
9322a4bf | 3598 | cpu_src1 = get_src1(insn, cpu_src1); |
6ae20372 BS |
3599 | gen_movl_reg_TN(rs2, cpu_src2); |
3600 | tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1, | |
3601 | cpu_src2); | |
3602 | gen_movl_TN_reg(rd, cpu_dst); | |
3299908c | 3603 | break; |
e9ebed4d | 3604 | case 0x019: /* VIS II bmask */ |
3299908c | 3605 | case 0x01a: /* VIS I alignaddrl */ |
3299908c | 3606 | // XXX |
e9ebed4d BS |
3607 | goto illegal_insn; |
3608 | case 0x020: /* VIS I fcmple16 */ | |
64a88d5d | 3609 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3610 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3611 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3612 | tcg_gen_helper_0_0(helper_fcmple16); |
2382dc6b | 3613 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3614 | break; |
3615 | case 0x022: /* VIS I fcmpne16 */ | |
64a88d5d | 3616 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3617 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3618 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3619 | tcg_gen_helper_0_0(helper_fcmpne16); |
2382dc6b | 3620 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3299908c | 3621 | break; |
e9ebed4d | 3622 | case 0x024: /* VIS I fcmple32 */ |
64a88d5d | 3623 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3624 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3625 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3626 | tcg_gen_helper_0_0(helper_fcmple32); |
2382dc6b | 3627 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3628 | break; |
3629 | case 0x026: /* VIS I fcmpne32 */ | |
64a88d5d | 3630 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3631 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3632 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3633 | tcg_gen_helper_0_0(helper_fcmpne32); |
2382dc6b | 3634 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3635 | break; |
3636 | case 0x028: /* VIS I fcmpgt16 */ | |
64a88d5d | 3637 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3638 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3639 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3640 | tcg_gen_helper_0_0(helper_fcmpgt16); |
2382dc6b | 3641 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3642 | break; |
3643 | case 0x02a: /* VIS I fcmpeq16 */ | |
64a88d5d | 3644 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3645 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3646 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3647 | tcg_gen_helper_0_0(helper_fcmpeq16); |
2382dc6b | 3648 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3649 | break; |
3650 | case 0x02c: /* VIS I fcmpgt32 */ | |
64a88d5d | 3651 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3652 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3653 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3654 | tcg_gen_helper_0_0(helper_fcmpgt32); |
2382dc6b | 3655 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3656 | break; |
3657 | case 0x02e: /* VIS I fcmpeq32 */ | |
64a88d5d | 3658 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3659 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3660 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3661 | tcg_gen_helper_0_0(helper_fcmpeq32); |
2382dc6b | 3662 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3663 | break; |
3664 | case 0x031: /* VIS I fmul8x16 */ | |
64a88d5d | 3665 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3666 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3667 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3668 | tcg_gen_helper_0_0(helper_fmul8x16); |
2382dc6b | 3669 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3670 | break; |
3671 | case 0x033: /* VIS I fmul8x16au */ | |
64a88d5d | 3672 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3673 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3674 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3675 | tcg_gen_helper_0_0(helper_fmul8x16au); |
2382dc6b | 3676 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3677 | break; |
3678 | case 0x035: /* VIS I fmul8x16al */ | |
64a88d5d | 3679 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3680 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3681 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3682 | tcg_gen_helper_0_0(helper_fmul8x16al); |
2382dc6b | 3683 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3684 | break; |
3685 | case 0x036: /* VIS I fmul8sux16 */ | |
64a88d5d | 3686 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3687 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3688 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3689 | tcg_gen_helper_0_0(helper_fmul8sux16); |
2382dc6b | 3690 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3691 | break; |
3692 | case 0x037: /* VIS I fmul8ulx16 */ | |
64a88d5d | 3693 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3694 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3695 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3696 | tcg_gen_helper_0_0(helper_fmul8ulx16); |
2382dc6b | 3697 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3698 | break; |
3699 | case 0x038: /* VIS I fmuld8sux16 */ | |
64a88d5d | 3700 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3701 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3702 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3703 | tcg_gen_helper_0_0(helper_fmuld8sux16); |
2382dc6b | 3704 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3705 | break; |
3706 | case 0x039: /* VIS I fmuld8ulx16 */ | |
64a88d5d | 3707 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3708 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3709 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3710 | tcg_gen_helper_0_0(helper_fmuld8ulx16); |
2382dc6b | 3711 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3712 | break; |
3713 | case 0x03a: /* VIS I fpack32 */ | |
3714 | case 0x03b: /* VIS I fpack16 */ | |
3715 | case 0x03d: /* VIS I fpackfix */ | |
3716 | case 0x03e: /* VIS I pdist */ | |
3717 | // XXX | |
3718 | goto illegal_insn; | |
3299908c | 3719 | case 0x048: /* VIS I faligndata */ |
64a88d5d | 3720 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3721 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3722 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3723 | tcg_gen_helper_0_0(helper_faligndata); |
2382dc6b | 3724 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3299908c | 3725 | break; |
e9ebed4d | 3726 | case 0x04b: /* VIS I fpmerge */ |
64a88d5d | 3727 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3728 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3729 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3730 | tcg_gen_helper_0_0(helper_fpmerge); |
2382dc6b | 3731 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3732 | break; |
3733 | case 0x04c: /* VIS II bshuffle */ | |
3734 | // XXX | |
3735 | goto illegal_insn; | |
3736 | case 0x04d: /* VIS I fexpand */ | |
64a88d5d | 3737 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3738 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3739 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3740 | tcg_gen_helper_0_0(helper_fexpand); |
2382dc6b | 3741 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3742 | break; |
3743 | case 0x050: /* VIS I fpadd16 */ | |
64a88d5d | 3744 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3745 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3746 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3747 | tcg_gen_helper_0_0(helper_fpadd16); |
2382dc6b | 3748 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3749 | break; |
3750 | case 0x051: /* VIS I fpadd16s */ | |
64a88d5d | 3751 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3752 | gen_op_load_fpr_FT0(rs1); |
3753 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3754 | tcg_gen_helper_0_0(helper_fpadd16s); |
e9ebed4d BS |
3755 | gen_op_store_FT0_fpr(rd); |
3756 | break; | |
3757 | case 0x052: /* VIS I fpadd32 */ | |
64a88d5d | 3758 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3759 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3760 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3761 | tcg_gen_helper_0_0(helper_fpadd32); |
2382dc6b | 3762 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3763 | break; |
3764 | case 0x053: /* VIS I fpadd32s */ | |
64a88d5d | 3765 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3766 | gen_op_load_fpr_FT0(rs1); |
3767 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3768 | tcg_gen_helper_0_0(helper_fpadd32s); |
e9ebed4d BS |
3769 | gen_op_store_FT0_fpr(rd); |
3770 | break; | |
3771 | case 0x054: /* VIS I fpsub16 */ | |
64a88d5d | 3772 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3773 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3774 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3775 | tcg_gen_helper_0_0(helper_fpsub16); |
2382dc6b | 3776 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3777 | break; |
3778 | case 0x055: /* VIS I fpsub16s */ | |
64a88d5d | 3779 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3780 | gen_op_load_fpr_FT0(rs1); |
3781 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3782 | tcg_gen_helper_0_0(helper_fpsub16s); |
e9ebed4d BS |
3783 | gen_op_store_FT0_fpr(rd); |
3784 | break; | |
3785 | case 0x056: /* VIS I fpsub32 */ | |
64a88d5d | 3786 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3787 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3788 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
510aba20 | 3789 | tcg_gen_helper_0_0(helper_fpsub32); |
2382dc6b | 3790 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3791 | break; |
3792 | case 0x057: /* VIS I fpsub32s */ | |
64a88d5d | 3793 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3794 | gen_op_load_fpr_FT0(rs1); |
3795 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3796 | tcg_gen_helper_0_0(helper_fpsub32s); |
e9ebed4d BS |
3797 | gen_op_store_FT0_fpr(rd); |
3798 | break; | |
3299908c | 3799 | case 0x060: /* VIS I fzero */ |
64a88d5d | 3800 | CHECK_FPU_FEATURE(dc, VIS1); |
44e7757c | 3801 | tcg_gen_helper_0_0(helper_movl_DT0_0); |
2382dc6b | 3802 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3299908c BS |
3803 | break; |
3804 | case 0x061: /* VIS I fzeros */ | |
64a88d5d | 3805 | CHECK_FPU_FEATURE(dc, VIS1); |
44e7757c | 3806 | tcg_gen_helper_0_0(helper_movl_FT0_0); |
3299908c BS |
3807 | gen_op_store_FT0_fpr(rd); |
3808 | break; | |
e9ebed4d | 3809 | case 0x062: /* VIS I fnor */ |
64a88d5d | 3810 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3811 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3812 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3813 | tcg_gen_helper_0_0(helper_fnor); |
2382dc6b | 3814 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3815 | break; |
3816 | case 0x063: /* VIS I fnors */ | |
64a88d5d | 3817 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3818 | gen_op_load_fpr_FT0(rs1); |
3819 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3820 | tcg_gen_helper_0_0(helper_fnors); |
e9ebed4d BS |
3821 | gen_op_store_FT0_fpr(rd); |
3822 | break; | |
3823 | case 0x064: /* VIS I fandnot2 */ | |
64a88d5d | 3824 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3825 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
3826 | gen_op_load_fpr_DT0(DFPREG(rs2)); | |
44e7757c | 3827 | tcg_gen_helper_0_0(helper_fandnot); |
2382dc6b | 3828 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3829 | break; |
3830 | case 0x065: /* VIS I fandnot2s */ | |
64a88d5d | 3831 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3832 | gen_op_load_fpr_FT1(rs1); |
3833 | gen_op_load_fpr_FT0(rs2); | |
44e7757c | 3834 | tcg_gen_helper_0_0(helper_fandnots); |
e9ebed4d BS |
3835 | gen_op_store_FT0_fpr(rd); |
3836 | break; | |
3837 | case 0x066: /* VIS I fnot2 */ | |
64a88d5d | 3838 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b | 3839 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
44e7757c | 3840 | tcg_gen_helper_0_0(helper_fnot); |
2382dc6b | 3841 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3842 | break; |
3843 | case 0x067: /* VIS I fnot2s */ | |
64a88d5d | 3844 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d | 3845 | gen_op_load_fpr_FT1(rs2); |
44e7757c | 3846 | tcg_gen_helper_0_0(helper_fnot); |
e9ebed4d BS |
3847 | gen_op_store_FT0_fpr(rd); |
3848 | break; | |
3849 | case 0x068: /* VIS I fandnot1 */ | |
64a88d5d | 3850 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3851 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3852 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3853 | tcg_gen_helper_0_0(helper_fandnot); |
2382dc6b | 3854 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3855 | break; |
3856 | case 0x069: /* VIS I fandnot1s */ | |
64a88d5d | 3857 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3858 | gen_op_load_fpr_FT0(rs1); |
3859 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3860 | tcg_gen_helper_0_0(helper_fandnots); |
e9ebed4d BS |
3861 | gen_op_store_FT0_fpr(rd); |
3862 | break; | |
3863 | case 0x06a: /* VIS I fnot1 */ | |
64a88d5d | 3864 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b | 3865 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
44e7757c | 3866 | tcg_gen_helper_0_0(helper_fnot); |
2382dc6b | 3867 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3868 | break; |
3869 | case 0x06b: /* VIS I fnot1s */ | |
64a88d5d | 3870 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d | 3871 | gen_op_load_fpr_FT1(rs1); |
44e7757c | 3872 | tcg_gen_helper_0_0(helper_fnot); |
e9ebed4d BS |
3873 | gen_op_store_FT0_fpr(rd); |
3874 | break; | |
3875 | case 0x06c: /* VIS I fxor */ | |
64a88d5d | 3876 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3877 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3878 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3879 | tcg_gen_helper_0_0(helper_fxor); |
2382dc6b | 3880 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3881 | break; |
3882 | case 0x06d: /* VIS I fxors */ | |
64a88d5d | 3883 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3884 | gen_op_load_fpr_FT0(rs1); |
3885 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3886 | tcg_gen_helper_0_0(helper_fxors); |
e9ebed4d BS |
3887 | gen_op_store_FT0_fpr(rd); |
3888 | break; | |
3889 | case 0x06e: /* VIS I fnand */ | |
64a88d5d | 3890 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3891 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3892 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3893 | tcg_gen_helper_0_0(helper_fnand); |
2382dc6b | 3894 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3895 | break; |
3896 | case 0x06f: /* VIS I fnands */ | |
64a88d5d | 3897 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3898 | gen_op_load_fpr_FT0(rs1); |
3899 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3900 | tcg_gen_helper_0_0(helper_fnands); |
e9ebed4d BS |
3901 | gen_op_store_FT0_fpr(rd); |
3902 | break; | |
3903 | case 0x070: /* VIS I fand */ | |
64a88d5d | 3904 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3905 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3906 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3907 | tcg_gen_helper_0_0(helper_fand); |
2382dc6b | 3908 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3909 | break; |
3910 | case 0x071: /* VIS I fands */ | |
64a88d5d | 3911 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3912 | gen_op_load_fpr_FT0(rs1); |
3913 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3914 | tcg_gen_helper_0_0(helper_fands); |
e9ebed4d BS |
3915 | gen_op_store_FT0_fpr(rd); |
3916 | break; | |
3917 | case 0x072: /* VIS I fxnor */ | |
64a88d5d | 3918 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3919 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3920 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3921 | tcg_gen_helper_0_0(helper_fxnor); |
2382dc6b | 3922 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3923 | break; |
3924 | case 0x073: /* VIS I fxnors */ | |
64a88d5d | 3925 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3926 | gen_op_load_fpr_FT0(rs1); |
3927 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3928 | tcg_gen_helper_0_0(helper_fxnors); |
e9ebed4d BS |
3929 | gen_op_store_FT0_fpr(rd); |
3930 | break; | |
3299908c | 3931 | case 0x074: /* VIS I fsrc1 */ |
64a88d5d | 3932 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3933 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3934 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
3299908c BS |
3935 | break; |
3936 | case 0x075: /* VIS I fsrc1s */ | |
64a88d5d | 3937 | CHECK_FPU_FEATURE(dc, VIS1); |
3299908c BS |
3938 | gen_op_load_fpr_FT0(rs1); |
3939 | gen_op_store_FT0_fpr(rd); | |
3940 | break; | |
e9ebed4d | 3941 | case 0x076: /* VIS I fornot2 */ |
64a88d5d | 3942 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3943 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
3944 | gen_op_load_fpr_DT0(DFPREG(rs2)); | |
44e7757c | 3945 | tcg_gen_helper_0_0(helper_fornot); |
2382dc6b | 3946 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3947 | break; |
3948 | case 0x077: /* VIS I fornot2s */ | |
64a88d5d | 3949 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3950 | gen_op_load_fpr_FT1(rs1); |
3951 | gen_op_load_fpr_FT0(rs2); | |
44e7757c | 3952 | tcg_gen_helper_0_0(helper_fornots); |
e9ebed4d BS |
3953 | gen_op_store_FT0_fpr(rd); |
3954 | break; | |
3299908c | 3955 | case 0x078: /* VIS I fsrc2 */ |
64a88d5d | 3956 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3957 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
3958 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
3299908c BS |
3959 | break; |
3960 | case 0x079: /* VIS I fsrc2s */ | |
64a88d5d | 3961 | CHECK_FPU_FEATURE(dc, VIS1); |
3299908c BS |
3962 | gen_op_load_fpr_FT0(rs2); |
3963 | gen_op_store_FT0_fpr(rd); | |
3964 | break; | |
e9ebed4d | 3965 | case 0x07a: /* VIS I fornot1 */ |
64a88d5d | 3966 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3967 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3968 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3969 | tcg_gen_helper_0_0(helper_fornot); |
2382dc6b | 3970 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3971 | break; |
3972 | case 0x07b: /* VIS I fornot1s */ | |
64a88d5d | 3973 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3974 | gen_op_load_fpr_FT0(rs1); |
3975 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3976 | tcg_gen_helper_0_0(helper_fornots); |
e9ebed4d BS |
3977 | gen_op_store_FT0_fpr(rd); |
3978 | break; | |
3979 | case 0x07c: /* VIS I for */ | |
64a88d5d | 3980 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3981 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3982 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3983 | tcg_gen_helper_0_0(helper_for); |
2382dc6b | 3984 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3985 | break; |
3986 | case 0x07d: /* VIS I fors */ | |
64a88d5d | 3987 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3988 | gen_op_load_fpr_FT0(rs1); |
3989 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3990 | tcg_gen_helper_0_0(helper_fors); |
e9ebed4d BS |
3991 | gen_op_store_FT0_fpr(rd); |
3992 | break; | |
3299908c | 3993 | case 0x07e: /* VIS I fone */ |
64a88d5d | 3994 | CHECK_FPU_FEATURE(dc, VIS1); |
44e7757c | 3995 | tcg_gen_helper_0_0(helper_movl_DT0_1); |
2382dc6b | 3996 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3299908c BS |
3997 | break; |
3998 | case 0x07f: /* VIS I fones */ | |
64a88d5d | 3999 | CHECK_FPU_FEATURE(dc, VIS1); |
44e7757c | 4000 | tcg_gen_helper_0_0(helper_movl_FT0_1); |
3299908c BS |
4001 | gen_op_store_FT0_fpr(rd); |
4002 | break; | |
e9ebed4d BS |
4003 | case 0x080: /* VIS I shutdown */ |
4004 | case 0x081: /* VIS II siam */ | |
4005 | // XXX | |
4006 | goto illegal_insn; | |
3299908c BS |
4007 | default: |
4008 | goto illegal_insn; | |
4009 | } | |
4010 | #else | |
0f8a249a | 4011 | goto ncp_insn; |
3299908c BS |
4012 | #endif |
4013 | } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ | |
fcc72045 | 4014 | #ifdef TARGET_SPARC64 |
0f8a249a | 4015 | goto illegal_insn; |
fcc72045 | 4016 | #else |
0f8a249a | 4017 | goto ncp_insn; |
fcc72045 | 4018 | #endif |
3475187d | 4019 | #ifdef TARGET_SPARC64 |
0f8a249a | 4020 | } else if (xop == 0x39) { /* V9 return */ |
2ea815ca BS |
4021 | TCGv r_const; |
4022 | ||
6ae20372 | 4023 | save_state(dc, cpu_cond); |
9322a4bf | 4024 | cpu_src1 = get_src1(insn, cpu_src1); |
0f8a249a BS |
4025 | if (IS_IMM) { /* immediate */ |
4026 | rs2 = GET_FIELDs(insn, 19, 31); | |
6ae20372 | 4027 | tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2); |
0f8a249a | 4028 | } else { /* register */ |
3475187d | 4029 | rs2 = GET_FIELD(insn, 27, 31); |
0f8a249a | 4030 | if (rs2) { |
6ae20372 BS |
4031 | gen_movl_reg_TN(rs2, cpu_src2); |
4032 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); | |
6f551262 BS |
4033 | } else |
4034 | tcg_gen_mov_tl(cpu_dst, cpu_src1); | |
3475187d | 4035 | } |
72a9747b | 4036 | tcg_gen_helper_0_0(helper_restore); |
6ae20372 | 4037 | gen_mov_pc_npc(dc, cpu_cond); |
2ea815ca BS |
4038 | r_const = tcg_const_i32(3); |
4039 | tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const); | |
4040 | tcg_temp_free(r_const); | |
6ae20372 | 4041 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
0f8a249a BS |
4042 | dc->npc = DYNAMIC_PC; |
4043 | goto jmp_insn; | |
3475187d | 4044 | #endif |
0f8a249a | 4045 | } else { |
9322a4bf | 4046 | cpu_src1 = get_src1(insn, cpu_src1); |
0f8a249a BS |
4047 | if (IS_IMM) { /* immediate */ |
4048 | rs2 = GET_FIELDs(insn, 19, 31); | |
6ae20372 | 4049 | tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2); |
0f8a249a | 4050 | } else { /* register */ |
e80cfcfc | 4051 | rs2 = GET_FIELD(insn, 27, 31); |
0f8a249a | 4052 | if (rs2) { |
6ae20372 BS |
4053 | gen_movl_reg_TN(rs2, cpu_src2); |
4054 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); | |
6f551262 BS |
4055 | } else |
4056 | tcg_gen_mov_tl(cpu_dst, cpu_src1); | |
cf495bcf | 4057 | } |
0f8a249a BS |
4058 | switch (xop) { |
4059 | case 0x38: /* jmpl */ | |
4060 | { | |
2ea815ca BS |
4061 | TCGv r_const; |
4062 | ||
4063 | r_const = tcg_const_tl(dc->pc); | |
4064 | gen_movl_TN_reg(rd, r_const); | |
4065 | tcg_temp_free(r_const); | |
6ae20372 | 4066 | gen_mov_pc_npc(dc, cpu_cond); |
2ea815ca | 4067 | r_const = tcg_const_i32(3); |
77f193da | 4068 | tcg_gen_helper_0_2(helper_check_align, cpu_dst, |
2ea815ca BS |
4069 | r_const); |
4070 | tcg_temp_free(r_const); | |
6ae20372 | 4071 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
0f8a249a BS |
4072 | dc->npc = DYNAMIC_PC; |
4073 | } | |
4074 | goto jmp_insn; | |
3475187d | 4075 | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) |
0f8a249a BS |
4076 | case 0x39: /* rett, V9 return */ |
4077 | { | |
2ea815ca BS |
4078 | TCGv r_const; |
4079 | ||
0f8a249a BS |
4080 | if (!supervisor(dc)) |
4081 | goto priv_insn; | |
6ae20372 | 4082 | gen_mov_pc_npc(dc, cpu_cond); |
2ea815ca | 4083 | r_const = tcg_const_i32(3); |
77f193da | 4084 | tcg_gen_helper_0_2(helper_check_align, cpu_dst, |
2ea815ca BS |
4085 | r_const); |
4086 | tcg_temp_free(r_const); | |
6ae20372 | 4087 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
0f8a249a | 4088 | dc->npc = DYNAMIC_PC; |
1a2fb1c0 | 4089 | tcg_gen_helper_0_0(helper_rett); |
0f8a249a BS |
4090 | } |
4091 | goto jmp_insn; | |
4092 | #endif | |
4093 | case 0x3b: /* flush */ | |
5578ceab | 4094 | if (!((dc)->def->features & CPU_FEATURE_FLUSH)) |
64a88d5d | 4095 | goto unimp_flush; |
6ae20372 | 4096 | tcg_gen_helper_0_1(helper_flush, cpu_dst); |
0f8a249a BS |
4097 | break; |
4098 | case 0x3c: /* save */ | |
6ae20372 | 4099 | save_state(dc, cpu_cond); |
72a9747b | 4100 | tcg_gen_helper_0_0(helper_save); |
6ae20372 | 4101 | gen_movl_TN_reg(rd, cpu_dst); |
0f8a249a BS |
4102 | break; |
4103 | case 0x3d: /* restore */ | |
6ae20372 | 4104 | save_state(dc, cpu_cond); |
72a9747b | 4105 | tcg_gen_helper_0_0(helper_restore); |
6ae20372 | 4106 | gen_movl_TN_reg(rd, cpu_dst); |
0f8a249a | 4107 | break; |
3475187d | 4108 | #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64) |
0f8a249a BS |
4109 | case 0x3e: /* V9 done/retry */ |
4110 | { | |
4111 | switch (rd) { | |
4112 | case 0: | |
4113 | if (!supervisor(dc)) | |
4114 | goto priv_insn; | |
4115 | dc->npc = DYNAMIC_PC; | |
4116 | dc->pc = DYNAMIC_PC; | |
1a2fb1c0 | 4117 | tcg_gen_helper_0_0(helper_done); |
0f8a249a BS |
4118 | goto jmp_insn; |
4119 | case 1: | |
4120 | if (!supervisor(dc)) | |
4121 | goto priv_insn; | |
4122 | dc->npc = DYNAMIC_PC; | |
4123 | dc->pc = DYNAMIC_PC; | |
1a2fb1c0 | 4124 | tcg_gen_helper_0_0(helper_retry); |
0f8a249a BS |
4125 | goto jmp_insn; |
4126 | default: | |
4127 | goto illegal_insn; | |
4128 | } | |
4129 | } | |
4130 | break; | |
4131 | #endif | |
4132 | default: | |
4133 | goto illegal_insn; | |
4134 | } | |
cf495bcf | 4135 | } |
0f8a249a BS |
4136 | break; |
4137 | } | |
4138 | break; | |
4139 | case 3: /* load/store instructions */ | |
4140 | { | |
4141 | unsigned int xop = GET_FIELD(insn, 7, 12); | |
9322a4bf | 4142 | |
9322a4bf | 4143 | cpu_src1 = get_src1(insn, cpu_src1); |
71817e48 | 4144 | if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa |
81ad8ba2 | 4145 | rs2 = GET_FIELD(insn, 27, 31); |
6ae20372 | 4146 | gen_movl_reg_TN(rs2, cpu_src2); |
71817e48 BS |
4147 | tcg_gen_mov_tl(cpu_addr, cpu_src1); |
4148 | } else if (IS_IMM) { /* immediate */ | |
0f8a249a | 4149 | rs2 = GET_FIELDs(insn, 19, 31); |
6ae20372 | 4150 | tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2); |
0f8a249a BS |
4151 | } else { /* register */ |
4152 | rs2 = GET_FIELD(insn, 27, 31); | |
0f8a249a | 4153 | if (rs2 != 0) { |
6ae20372 BS |
4154 | gen_movl_reg_TN(rs2, cpu_src2); |
4155 | tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2); | |
6f551262 BS |
4156 | } else |
4157 | tcg_gen_mov_tl(cpu_addr, cpu_src1); | |
0f8a249a | 4158 | } |
2f2ecb83 BS |
4159 | if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || |
4160 | (xop > 0x17 && xop <= 0x1d ) || | |
4161 | (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { | |
0f8a249a | 4162 | switch (xop) { |
1a2fb1c0 | 4163 | case 0x0: /* load unsigned word */ |
2cade6a3 | 4164 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4165 | tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a BS |
4166 | break; |
4167 | case 0x1: /* load unsigned byte */ | |
2cade6a3 | 4168 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4169 | tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a BS |
4170 | break; |
4171 | case 0x2: /* load unsigned halfword */ | |
2cade6a3 | 4172 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4173 | tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a BS |
4174 | break; |
4175 | case 0x3: /* load double word */ | |
0f8a249a | 4176 | if (rd & 1) |
d4218d99 | 4177 | goto illegal_insn; |
1a2fb1c0 | 4178 | else { |
2ea815ca BS |
4179 | TCGv r_const; |
4180 | ||
c2bc0e38 | 4181 | save_state(dc, cpu_cond); |
2ea815ca | 4182 | r_const = tcg_const_i32(7); |
d987963a | 4183 | tcg_gen_helper_0_2(helper_check_align, cpu_addr, |
2ea815ca BS |
4184 | r_const); // XXX remove |
4185 | tcg_temp_free(r_const); | |
2cade6a3 | 4186 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4187 | tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); |
32b6c812 BS |
4188 | tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64); |
4189 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL); | |
4190 | gen_movl_TN_reg(rd + 1, cpu_tmp0); | |
8911f501 | 4191 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32); |
6ae20372 BS |
4192 | tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64); |
4193 | tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL); | |
1a2fb1c0 | 4194 | } |
0f8a249a BS |
4195 | break; |
4196 | case 0x9: /* load signed byte */ | |
2cade6a3 | 4197 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4198 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a BS |
4199 | break; |
4200 | case 0xa: /* load signed halfword */ | |
2cade6a3 | 4201 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4202 | tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a BS |
4203 | break; |
4204 | case 0xd: /* ldstub -- XXX: should be atomically */ | |
2ea815ca BS |
4205 | { |
4206 | TCGv r_const; | |
4207 | ||
2cade6a3 | 4208 | gen_address_mask(dc, cpu_addr); |
2ea815ca BS |
4209 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
4210 | r_const = tcg_const_tl(0xff); | |
4211 | tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx); | |
4212 | tcg_temp_free(r_const); | |
4213 | } | |
0f8a249a | 4214 | break; |
77f193da BS |
4215 | case 0x0f: /* swap register with memory. Also |
4216 | atomically */ | |
64a88d5d | 4217 | CHECK_IU_FEATURE(dc, SWAP); |
6ae20372 | 4218 | gen_movl_reg_TN(rd, cpu_val); |
2cade6a3 | 4219 | gen_address_mask(dc, cpu_addr); |
6ae20372 BS |
4220 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); |
4221 | tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); | |
4222 | tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32); | |
0f8a249a | 4223 | break; |
3475187d | 4224 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) |
0f8a249a | 4225 | case 0x10: /* load word alternate */ |
3475187d | 4226 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4227 | if (IS_IMM) |
4228 | goto illegal_insn; | |
4229 | if (!supervisor(dc)) | |
4230 | goto priv_insn; | |
6ea4a6c8 | 4231 | #endif |
c2bc0e38 | 4232 | save_state(dc, cpu_cond); |
6ae20372 | 4233 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0); |
0f8a249a BS |
4234 | break; |
4235 | case 0x11: /* load unsigned byte alternate */ | |
3475187d | 4236 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4237 | if (IS_IMM) |
4238 | goto illegal_insn; | |
4239 | if (!supervisor(dc)) | |
4240 | goto priv_insn; | |
4241 | #endif | |
c2bc0e38 | 4242 | save_state(dc, cpu_cond); |
6ae20372 | 4243 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0); |
0f8a249a BS |
4244 | break; |
4245 | case 0x12: /* load unsigned halfword alternate */ | |
3475187d | 4246 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4247 | if (IS_IMM) |
4248 | goto illegal_insn; | |
4249 | if (!supervisor(dc)) | |
4250 | goto priv_insn; | |
3475187d | 4251 | #endif |
c2bc0e38 | 4252 | save_state(dc, cpu_cond); |
6ae20372 | 4253 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0); |
0f8a249a BS |
4254 | break; |
4255 | case 0x13: /* load double word alternate */ | |
3475187d | 4256 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4257 | if (IS_IMM) |
4258 | goto illegal_insn; | |
4259 | if (!supervisor(dc)) | |
4260 | goto priv_insn; | |
3475187d | 4261 | #endif |
0f8a249a | 4262 | if (rd & 1) |
d4218d99 | 4263 | goto illegal_insn; |
c2bc0e38 | 4264 | save_state(dc, cpu_cond); |
db166940 BS |
4265 | gen_ldda_asi(cpu_val, cpu_addr, insn, rd); |
4266 | goto skip_move; | |
0f8a249a | 4267 | case 0x19: /* load signed byte alternate */ |
3475187d | 4268 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4269 | if (IS_IMM) |
4270 | goto illegal_insn; | |
4271 | if (!supervisor(dc)) | |
4272 | goto priv_insn; | |
4273 | #endif | |
c2bc0e38 | 4274 | save_state(dc, cpu_cond); |
6ae20372 | 4275 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1); |
0f8a249a BS |
4276 | break; |
4277 | case 0x1a: /* load signed halfword alternate */ | |
3475187d | 4278 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4279 | if (IS_IMM) |
4280 | goto illegal_insn; | |
4281 | if (!supervisor(dc)) | |
4282 | goto priv_insn; | |
3475187d | 4283 | #endif |
c2bc0e38 | 4284 | save_state(dc, cpu_cond); |
6ae20372 | 4285 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1); |
0f8a249a BS |
4286 | break; |
4287 | case 0x1d: /* ldstuba -- XXX: should be atomically */ | |
3475187d | 4288 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4289 | if (IS_IMM) |
4290 | goto illegal_insn; | |
4291 | if (!supervisor(dc)) | |
4292 | goto priv_insn; | |
4293 | #endif | |
c2bc0e38 | 4294 | save_state(dc, cpu_cond); |
6ae20372 | 4295 | gen_ldstub_asi(cpu_val, cpu_addr, insn); |
0f8a249a | 4296 | break; |
77f193da BS |
4297 | case 0x1f: /* swap reg with alt. memory. Also |
4298 | atomically */ | |
64a88d5d | 4299 | CHECK_IU_FEATURE(dc, SWAP); |
3475187d | 4300 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4301 | if (IS_IMM) |
4302 | goto illegal_insn; | |
4303 | if (!supervisor(dc)) | |
4304 | goto priv_insn; | |
6ea4a6c8 | 4305 | #endif |
c2bc0e38 | 4306 | save_state(dc, cpu_cond); |
6ae20372 BS |
4307 | gen_movl_reg_TN(rd, cpu_val); |
4308 | gen_swap_asi(cpu_val, cpu_addr, insn); | |
0f8a249a | 4309 | break; |
3475187d FB |
4310 | |
4311 | #ifndef TARGET_SPARC64 | |
0f8a249a BS |
4312 | case 0x30: /* ldc */ |
4313 | case 0x31: /* ldcsr */ | |
4314 | case 0x33: /* lddc */ | |
4315 | goto ncp_insn; | |
3475187d FB |
4316 | #endif |
4317 | #endif | |
4318 | #ifdef TARGET_SPARC64 | |
0f8a249a | 4319 | case 0x08: /* V9 ldsw */ |
2cade6a3 | 4320 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4321 | tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a BS |
4322 | break; |
4323 | case 0x0b: /* V9 ldx */ | |
2cade6a3 | 4324 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4325 | tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a BS |
4326 | break; |
4327 | case 0x18: /* V9 ldswa */ | |
c2bc0e38 | 4328 | save_state(dc, cpu_cond); |
6ae20372 | 4329 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1); |
0f8a249a BS |
4330 | break; |
4331 | case 0x1b: /* V9 ldxa */ | |
c2bc0e38 | 4332 | save_state(dc, cpu_cond); |
6ae20372 | 4333 | gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0); |
0f8a249a BS |
4334 | break; |
4335 | case 0x2d: /* V9 prefetch, no effect */ | |
4336 | goto skip_move; | |
4337 | case 0x30: /* V9 ldfa */ | |
c2bc0e38 | 4338 | save_state(dc, cpu_cond); |
6ae20372 | 4339 | gen_ldf_asi(cpu_addr, insn, 4, rd); |
81ad8ba2 | 4340 | goto skip_move; |
0f8a249a | 4341 | case 0x33: /* V9 lddfa */ |
c2bc0e38 | 4342 | save_state(dc, cpu_cond); |
6ae20372 | 4343 | gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd)); |
81ad8ba2 | 4344 | goto skip_move; |
0f8a249a BS |
4345 | case 0x3d: /* V9 prefetcha, no effect */ |
4346 | goto skip_move; | |
4347 | case 0x32: /* V9 ldqfa */ | |
64a88d5d | 4348 | CHECK_FPU_FEATURE(dc, FLOAT128); |
c2bc0e38 | 4349 | save_state(dc, cpu_cond); |
6ae20372 | 4350 | gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd)); |
1f587329 | 4351 | goto skip_move; |
0f8a249a BS |
4352 | #endif |
4353 | default: | |
4354 | goto illegal_insn; | |
4355 | } | |
6ae20372 | 4356 | gen_movl_TN_reg(rd, cpu_val); |
db166940 | 4357 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) |
0f8a249a | 4358 | skip_move: ; |
3475187d | 4359 | #endif |
0f8a249a | 4360 | } else if (xop >= 0x20 && xop < 0x24) { |
6ae20372 | 4361 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
a80dde08 | 4362 | goto jmp_insn; |
c2bc0e38 | 4363 | save_state(dc, cpu_cond); |
0f8a249a BS |
4364 | switch (xop) { |
4365 | case 0x20: /* load fpreg */ | |
2cade6a3 | 4366 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4367 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); |
ce8536e2 BS |
4368 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
4369 | offsetof(CPUState, fpr[rd])); | |
0f8a249a | 4370 | break; |
3a3b925d BS |
4371 | case 0x21: /* ldfsr, V9 ldxfsr */ |
4372 | #ifdef TARGET_SPARC64 | |
2cade6a3 | 4373 | gen_address_mask(dc, cpu_addr); |
3a3b925d BS |
4374 | if (rd == 1) { |
4375 | tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); | |
4376 | tcg_gen_helper_0_1(helper_ldxfsr, cpu_tmp64); | |
4377 | } else | |
4378 | #else | |
4379 | { | |
4380 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); | |
4381 | tcg_gen_helper_0_1(helper_ldfsr, cpu_tmp32); | |
4382 | } | |
4383 | #endif | |
0f8a249a BS |
4384 | break; |
4385 | case 0x22: /* load quad fpreg */ | |
2ea815ca BS |
4386 | { |
4387 | TCGv r_const; | |
4388 | ||
4389 | CHECK_FPU_FEATURE(dc, FLOAT128); | |
4390 | r_const = tcg_const_i32(dc->mem_idx); | |
4391 | tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const); | |
4392 | tcg_temp_free(r_const); | |
4393 | gen_op_store_QT0_fpr(QFPREG(rd)); | |
4394 | } | |
1f587329 | 4395 | break; |
0f8a249a | 4396 | case 0x23: /* load double fpreg */ |
2ea815ca BS |
4397 | { |
4398 | TCGv r_const; | |
4399 | ||
4400 | r_const = tcg_const_i32(dc->mem_idx); | |
4401 | tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const); | |
4402 | tcg_temp_free(r_const); | |
4403 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
4404 | } | |
0f8a249a BS |
4405 | break; |
4406 | default: | |
4407 | goto illegal_insn; | |
4408 | } | |
4409 | } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \ | |
4410 | xop == 0xe || xop == 0x1e) { | |
6ae20372 | 4411 | gen_movl_reg_TN(rd, cpu_val); |
0f8a249a | 4412 | switch (xop) { |
1a2fb1c0 | 4413 | case 0x4: /* store word */ |
2cade6a3 | 4414 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4415 | tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a | 4416 | break; |
1a2fb1c0 | 4417 | case 0x5: /* store byte */ |
2cade6a3 | 4418 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4419 | tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a | 4420 | break; |
1a2fb1c0 | 4421 | case 0x6: /* store halfword */ |
2cade6a3 | 4422 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4423 | tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a | 4424 | break; |
1a2fb1c0 | 4425 | case 0x7: /* store double word */ |
0f8a249a | 4426 | if (rd & 1) |
d4218d99 | 4427 | goto illegal_insn; |
1a2fb1c0 | 4428 | else { |
2ea815ca | 4429 | TCGv r_low, r_const; |
1a2fb1c0 | 4430 | |
c2bc0e38 | 4431 | save_state(dc, cpu_cond); |
2cade6a3 | 4432 | gen_address_mask(dc, cpu_addr); |
2ea815ca | 4433 | r_const = tcg_const_i32(7); |
c2bc0e38 | 4434 | tcg_gen_helper_0_2(helper_check_align, cpu_addr, |
2ea815ca BS |
4435 | r_const); // XXX remove |
4436 | tcg_temp_free(r_const); | |
8d96d209 | 4437 | r_low = tcg_temp_new(TCG_TYPE_TL); |
1a2fb1c0 | 4438 | gen_movl_reg_TN(rd + 1, r_low); |
6ae20372 | 4439 | tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val, |
1a2fb1c0 | 4440 | r_low); |
2ea815ca | 4441 | tcg_temp_free(r_low); |
6ae20372 | 4442 | tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); |
7fa76c0b | 4443 | } |
0f8a249a | 4444 | break; |
3475187d | 4445 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) |
1a2fb1c0 | 4446 | case 0x14: /* store word alternate */ |
3475187d | 4447 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4448 | if (IS_IMM) |
4449 | goto illegal_insn; | |
4450 | if (!supervisor(dc)) | |
4451 | goto priv_insn; | |
6ea4a6c8 | 4452 | #endif |
c2bc0e38 | 4453 | save_state(dc, cpu_cond); |
6ae20372 | 4454 | gen_st_asi(cpu_val, cpu_addr, insn, 4); |
d39c0b99 | 4455 | break; |
1a2fb1c0 | 4456 | case 0x15: /* store byte alternate */ |
3475187d | 4457 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4458 | if (IS_IMM) |
4459 | goto illegal_insn; | |
4460 | if (!supervisor(dc)) | |
4461 | goto priv_insn; | |
3475187d | 4462 | #endif |
c2bc0e38 | 4463 | save_state(dc, cpu_cond); |
6ae20372 | 4464 | gen_st_asi(cpu_val, cpu_addr, insn, 1); |
d39c0b99 | 4465 | break; |
1a2fb1c0 | 4466 | case 0x16: /* store halfword alternate */ |
3475187d | 4467 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4468 | if (IS_IMM) |
4469 | goto illegal_insn; | |
4470 | if (!supervisor(dc)) | |
4471 | goto priv_insn; | |
6ea4a6c8 | 4472 | #endif |
c2bc0e38 | 4473 | save_state(dc, cpu_cond); |
6ae20372 | 4474 | gen_st_asi(cpu_val, cpu_addr, insn, 2); |
d39c0b99 | 4475 | break; |
1a2fb1c0 | 4476 | case 0x17: /* store double word alternate */ |
3475187d | 4477 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4478 | if (IS_IMM) |
4479 | goto illegal_insn; | |
4480 | if (!supervisor(dc)) | |
4481 | goto priv_insn; | |
3475187d | 4482 | #endif |
0f8a249a | 4483 | if (rd & 1) |
d4218d99 | 4484 | goto illegal_insn; |
1a2fb1c0 | 4485 | else { |
c2bc0e38 | 4486 | save_state(dc, cpu_cond); |
6ae20372 | 4487 | gen_stda_asi(cpu_val, cpu_addr, insn, rd); |
1a2fb1c0 | 4488 | } |
d39c0b99 | 4489 | break; |
e80cfcfc | 4490 | #endif |
3475187d | 4491 | #ifdef TARGET_SPARC64 |
0f8a249a | 4492 | case 0x0e: /* V9 stx */ |
2cade6a3 | 4493 | gen_address_mask(dc, cpu_addr); |
6ae20372 | 4494 | tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx); |
0f8a249a BS |
4495 | break; |
4496 | case 0x1e: /* V9 stxa */ | |
c2bc0e38 | 4497 | save_state(dc, cpu_cond); |
6ae20372 | 4498 | gen_st_asi(cpu_val, cpu_addr, insn, 8); |
0f8a249a | 4499 | break; |
3475187d | 4500 | #endif |
0f8a249a BS |
4501 | default: |
4502 | goto illegal_insn; | |
4503 | } | |
4504 | } else if (xop > 0x23 && xop < 0x28) { | |
6ae20372 | 4505 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
a80dde08 | 4506 | goto jmp_insn; |
c2bc0e38 | 4507 | save_state(dc, cpu_cond); |
0f8a249a | 4508 | switch (xop) { |
ce8536e2 | 4509 | case 0x24: /* store fpreg */ |
2cade6a3 | 4510 | gen_address_mask(dc, cpu_addr); |
ce8536e2 BS |
4511 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
4512 | offsetof(CPUState, fpr[rd])); | |
6ae20372 | 4513 | tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx); |
0f8a249a BS |
4514 | break; |
4515 | case 0x25: /* stfsr, V9 stxfsr */ | |
3a3b925d | 4516 | #ifdef TARGET_SPARC64 |
2cade6a3 | 4517 | gen_address_mask(dc, cpu_addr); |
3a3b925d BS |
4518 | tcg_gen_ld_i64(cpu_tmp64, cpu_env, offsetof(CPUState, fsr)); |
4519 | if (rd == 1) | |
4520 | tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); | |
4521 | else { | |
4522 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp64); | |
4523 | tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx); | |
4524 | } | |
4525 | #else | |
4526 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUState, fsr)); | |
6ae20372 | 4527 | tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx); |
3a3b925d | 4528 | #endif |
0f8a249a | 4529 | break; |
1f587329 BS |
4530 | case 0x26: |
4531 | #ifdef TARGET_SPARC64 | |
1f587329 | 4532 | /* V9 stqf, store quad fpreg */ |
2ea815ca BS |
4533 | { |
4534 | TCGv r_const; | |
4535 | ||
4536 | CHECK_FPU_FEATURE(dc, FLOAT128); | |
4537 | gen_op_load_fpr_QT0(QFPREG(rd)); | |
4538 | r_const = tcg_const_i32(dc->mem_idx); | |
4539 | tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const); | |
4540 | tcg_temp_free(r_const); | |
4541 | } | |
1f587329 | 4542 | break; |
1f587329 BS |
4543 | #else /* !TARGET_SPARC64 */ |
4544 | /* stdfq, store floating point queue */ | |
4545 | #if defined(CONFIG_USER_ONLY) | |
4546 | goto illegal_insn; | |
4547 | #else | |
0f8a249a BS |
4548 | if (!supervisor(dc)) |
4549 | goto priv_insn; | |
6ae20372 | 4550 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
0f8a249a BS |
4551 | goto jmp_insn; |
4552 | goto nfq_insn; | |
1f587329 | 4553 | #endif |
0f8a249a | 4554 | #endif |
7fa76c0b | 4555 | case 0x27: /* store double fpreg */ |
2ea815ca BS |
4556 | { |
4557 | TCGv r_const; | |
4558 | ||
4559 | gen_op_load_fpr_DT0(DFPREG(rd)); | |
4560 | r_const = tcg_const_i32(dc->mem_idx); | |
4561 | tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const); | |
4562 | tcg_temp_free(r_const); | |
4563 | } | |
0f8a249a BS |
4564 | break; |
4565 | default: | |
4566 | goto illegal_insn; | |
4567 | } | |
4568 | } else if (xop > 0x33 && xop < 0x3f) { | |
c2bc0e38 | 4569 | save_state(dc, cpu_cond); |
0f8a249a | 4570 | switch (xop) { |
a4d17f19 | 4571 | #ifdef TARGET_SPARC64 |
0f8a249a | 4572 | case 0x34: /* V9 stfa */ |
3391c818 | 4573 | gen_op_load_fpr_FT0(rd); |
6ae20372 | 4574 | gen_stf_asi(cpu_addr, insn, 4, rd); |
0f8a249a | 4575 | break; |
1f587329 | 4576 | case 0x36: /* V9 stqfa */ |
2ea815ca BS |
4577 | { |
4578 | TCGv r_const; | |
4579 | ||
4580 | CHECK_FPU_FEATURE(dc, FLOAT128); | |
4581 | r_const = tcg_const_i32(7); | |
4582 | tcg_gen_helper_0_2(helper_check_align, cpu_addr, | |
4583 | r_const); | |
4584 | tcg_temp_free(r_const); | |
4585 | gen_op_load_fpr_QT0(QFPREG(rd)); | |
4586 | gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd)); | |
4587 | } | |
1f587329 | 4588 | break; |
0f8a249a | 4589 | case 0x37: /* V9 stdfa */ |
3391c818 | 4590 | gen_op_load_fpr_DT0(DFPREG(rd)); |
6ae20372 | 4591 | gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd)); |
0f8a249a BS |
4592 | break; |
4593 | case 0x3c: /* V9 casa */ | |
71817e48 | 4594 | gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd); |
6ae20372 | 4595 | gen_movl_TN_reg(rd, cpu_val); |
0f8a249a BS |
4596 | break; |
4597 | case 0x3e: /* V9 casxa */ | |
71817e48 | 4598 | gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd); |
6ae20372 | 4599 | gen_movl_TN_reg(rd, cpu_val); |
0f8a249a | 4600 | break; |
a4d17f19 | 4601 | #else |
0f8a249a BS |
4602 | case 0x34: /* stc */ |
4603 | case 0x35: /* stcsr */ | |
4604 | case 0x36: /* stdcq */ | |
4605 | case 0x37: /* stdc */ | |
4606 | goto ncp_insn; | |
4607 | #endif | |
4608 | default: | |
4609 | goto illegal_insn; | |
4610 | } | |
e8af50a3 | 4611 | } |
0f8a249a BS |
4612 | else |
4613 | goto illegal_insn; | |
4614 | } | |
4615 | break; | |
cf495bcf FB |
4616 | } |
4617 | /* default case for non jump instructions */ | |
72cbca10 | 4618 | if (dc->npc == DYNAMIC_PC) { |
0f8a249a BS |
4619 | dc->pc = DYNAMIC_PC; |
4620 | gen_op_next_insn(); | |
72cbca10 FB |
4621 | } else if (dc->npc == JUMP_PC) { |
4622 | /* we can do a static jump */ | |
6ae20372 | 4623 | gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); |
72cbca10 FB |
4624 | dc->is_br = 1; |
4625 | } else { | |
0f8a249a BS |
4626 | dc->pc = dc->npc; |
4627 | dc->npc = dc->npc + 4; | |
cf495bcf | 4628 | } |
e80cfcfc | 4629 | jmp_insn: |
cf495bcf FB |
4630 | return; |
4631 | illegal_insn: | |
2ea815ca BS |
4632 | { |
4633 | TCGv r_const; | |
4634 | ||
4635 | save_state(dc, cpu_cond); | |
4636 | r_const = tcg_const_i32(TT_ILL_INSN); | |
4637 | tcg_gen_helper_0_1(raise_exception, r_const); | |
4638 | tcg_temp_free(r_const); | |
4639 | dc->is_br = 1; | |
4640 | } | |
e8af50a3 | 4641 | return; |
64a88d5d | 4642 | unimp_flush: |
2ea815ca BS |
4643 | { |
4644 | TCGv r_const; | |
4645 | ||
4646 | save_state(dc, cpu_cond); | |
4647 | r_const = tcg_const_i32(TT_UNIMP_FLUSH); | |
4648 | tcg_gen_helper_0_1(raise_exception, r_const); | |
4649 | tcg_temp_free(r_const); | |
4650 | dc->is_br = 1; | |
4651 | } | |
64a88d5d | 4652 | return; |
e80cfcfc | 4653 | #if !defined(CONFIG_USER_ONLY) |
e8af50a3 | 4654 | priv_insn: |
2ea815ca BS |
4655 | { |
4656 | TCGv r_const; | |
4657 | ||
4658 | save_state(dc, cpu_cond); | |
4659 | r_const = tcg_const_i32(TT_PRIV_INSN); | |
4660 | tcg_gen_helper_0_1(raise_exception, r_const); | |
4661 | tcg_temp_free(r_const); | |
4662 | dc->is_br = 1; | |
4663 | } | |
e80cfcfc | 4664 | return; |
64a88d5d | 4665 | #endif |
e80cfcfc | 4666 | nfpu_insn: |
6ae20372 | 4667 | save_state(dc, cpu_cond); |
e80cfcfc FB |
4668 | gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); |
4669 | dc->is_br = 1; | |
fcc72045 | 4670 | return; |
64a88d5d | 4671 | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) |
9143e598 | 4672 | nfq_insn: |
6ae20372 | 4673 | save_state(dc, cpu_cond); |
9143e598 BS |
4674 | gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); |
4675 | dc->is_br = 1; | |
4676 | return; | |
4677 | #endif | |
fcc72045 BS |
4678 | #ifndef TARGET_SPARC64 |
4679 | ncp_insn: | |
2ea815ca BS |
4680 | { |
4681 | TCGv r_const; | |
4682 | ||
4683 | save_state(dc, cpu_cond); | |
4684 | r_const = tcg_const_i32(TT_NCP_INSN); | |
4685 | tcg_gen_helper_0_1(raise_exception, r_const); | |
4686 | tcg_temp_free(r_const); | |
4687 | dc->is_br = 1; | |
4688 | } | |
fcc72045 BS |
4689 | return; |
4690 | #endif | |
7a3f1944 FB |
4691 | } |
4692 | ||
2cfc5f17 TS |
4693 | static inline void gen_intermediate_code_internal(TranslationBlock * tb, |
4694 | int spc, CPUSPARCState *env) | |
7a3f1944 | 4695 | { |
72cbca10 | 4696 | target_ulong pc_start, last_pc; |
cf495bcf FB |
4697 | uint16_t *gen_opc_end; |
4698 | DisasContext dc1, *dc = &dc1; | |
e8af50a3 | 4699 | int j, lj = -1; |
2e70f6ef PB |
4700 | int num_insns; |
4701 | int max_insns; | |
cf495bcf FB |
4702 | |
4703 | memset(dc, 0, sizeof(DisasContext)); | |
cf495bcf | 4704 | dc->tb = tb; |
72cbca10 | 4705 | pc_start = tb->pc; |
cf495bcf | 4706 | dc->pc = pc_start; |
e80cfcfc | 4707 | last_pc = dc->pc; |
72cbca10 | 4708 | dc->npc = (target_ulong) tb->cs_base; |
6f27aba6 | 4709 | dc->mem_idx = cpu_mmu_index(env); |
5578ceab BS |
4710 | dc->def = env->def; |
4711 | if ((dc->def->features & CPU_FEATURE_FLOAT)) | |
64a88d5d | 4712 | dc->fpu_enabled = cpu_fpu_enabled(env); |
5578ceab | 4713 | else |
64a88d5d | 4714 | dc->fpu_enabled = 0; |
2cade6a3 BS |
4715 | #ifdef TARGET_SPARC64 |
4716 | dc->address_mask_32bit = env->pstate & PS_AM; | |
4717 | #endif | |
cf495bcf | 4718 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
cf495bcf | 4719 | |
1a2fb1c0 | 4720 | cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL); |
8911f501 BS |
4721 | cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32); |
4722 | cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64); | |
d987963a BS |
4723 | |
4724 | cpu_dst = tcg_temp_local_new(TCG_TYPE_TL); | |
4725 | ||
4726 | // loads and stores | |
3f0436fe | 4727 | cpu_val = tcg_temp_local_new(TCG_TYPE_TL); |
d987963a | 4728 | cpu_addr = tcg_temp_local_new(TCG_TYPE_TL); |
1a2fb1c0 | 4729 | |
2e70f6ef PB |
4730 | num_insns = 0; |
4731 | max_insns = tb->cflags & CF_COUNT_MASK; | |
4732 | if (max_insns == 0) | |
4733 | max_insns = CF_COUNT_MASK; | |
4734 | gen_icount_start(); | |
cf495bcf | 4735 | do { |
e8af50a3 FB |
4736 | if (env->nb_breakpoints > 0) { |
4737 | for(j = 0; j < env->nb_breakpoints; j++) { | |
4738 | if (env->breakpoints[j] == dc->pc) { | |
0f8a249a | 4739 | if (dc->pc != pc_start) |
6ae20372 | 4740 | save_state(dc, cpu_cond); |
1a2fb1c0 | 4741 | tcg_gen_helper_0_0(helper_debug); |
57fec1fe | 4742 | tcg_gen_exit_tb(0); |
0f8a249a | 4743 | dc->is_br = 1; |
e80cfcfc | 4744 | goto exit_gen_loop; |
e8af50a3 FB |
4745 | } |
4746 | } | |
4747 | } | |
4748 | if (spc) { | |
4749 | if (loglevel > 0) | |
4750 | fprintf(logfile, "Search PC...\n"); | |
4751 | j = gen_opc_ptr - gen_opc_buf; | |
4752 | if (lj < j) { | |
4753 | lj++; | |
4754 | while (lj < j) | |
4755 | gen_opc_instr_start[lj++] = 0; | |
4756 | gen_opc_pc[lj] = dc->pc; | |
4757 | gen_opc_npc[lj] = dc->npc; | |
4758 | gen_opc_instr_start[lj] = 1; | |
2e70f6ef | 4759 | gen_opc_icount[lj] = num_insns; |
e8af50a3 FB |
4760 | } |
4761 | } | |
2e70f6ef PB |
4762 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
4763 | gen_io_start(); | |
0f8a249a BS |
4764 | last_pc = dc->pc; |
4765 | disas_sparc_insn(dc); | |
2e70f6ef | 4766 | num_insns++; |
0f8a249a BS |
4767 | |
4768 | if (dc->is_br) | |
4769 | break; | |
4770 | /* if the next PC is different, we abort now */ | |
4771 | if (dc->pc != (last_pc + 4)) | |
4772 | break; | |
d39c0b99 FB |
4773 | /* if we reach a page boundary, we stop generation so that the |
4774 | PC of a TT_TFAULT exception is always in the right page */ | |
4775 | if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) | |
4776 | break; | |
e80cfcfc FB |
4777 | /* if single step mode, we generate only one instruction and |
4778 | generate an exception */ | |
4779 | if (env->singlestep_enabled) { | |
2f5680ee | 4780 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
57fec1fe | 4781 | tcg_gen_exit_tb(0); |
e80cfcfc FB |
4782 | break; |
4783 | } | |
cf495bcf | 4784 | } while ((gen_opc_ptr < gen_opc_end) && |
2e70f6ef PB |
4785 | (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) && |
4786 | num_insns < max_insns); | |
e80cfcfc FB |
4787 | |
4788 | exit_gen_loop: | |
d987963a | 4789 | tcg_temp_free(cpu_addr); |
3f0436fe | 4790 | tcg_temp_free(cpu_val); |
d987963a | 4791 | tcg_temp_free(cpu_dst); |
2ea815ca BS |
4792 | tcg_temp_free(cpu_tmp64); |
4793 | tcg_temp_free(cpu_tmp32); | |
4794 | tcg_temp_free(cpu_tmp0); | |
2e70f6ef PB |
4795 | if (tb->cflags & CF_LAST_IO) |
4796 | gen_io_end(); | |
72cbca10 | 4797 | if (!dc->is_br) { |
5fafdf24 | 4798 | if (dc->pc != DYNAMIC_PC && |
72cbca10 FB |
4799 | (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { |
4800 | /* static PC and NPC: we can use direct chaining */ | |
2f5680ee | 4801 | gen_goto_tb(dc, 0, dc->pc, dc->npc); |
72cbca10 FB |
4802 | } else { |
4803 | if (dc->pc != DYNAMIC_PC) | |
2f5680ee | 4804 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
6ae20372 | 4805 | save_npc(dc, cpu_cond); |
57fec1fe | 4806 | tcg_gen_exit_tb(0); |
72cbca10 FB |
4807 | } |
4808 | } | |
2e70f6ef | 4809 | gen_icount_end(tb, num_insns); |
cf495bcf | 4810 | *gen_opc_ptr = INDEX_op_end; |
e8af50a3 FB |
4811 | if (spc) { |
4812 | j = gen_opc_ptr - gen_opc_buf; | |
4813 | lj++; | |
4814 | while (lj <= j) | |
4815 | gen_opc_instr_start[lj++] = 0; | |
e8af50a3 FB |
4816 | #if 0 |
4817 | if (loglevel > 0) { | |
4818 | page_dump(logfile); | |
4819 | } | |
4820 | #endif | |
c3278b7b FB |
4821 | gen_opc_jump_pc[0] = dc->jump_pc[0]; |
4822 | gen_opc_jump_pc[1] = dc->jump_pc[1]; | |
e8af50a3 | 4823 | } else { |
e80cfcfc | 4824 | tb->size = last_pc + 4 - pc_start; |
2e70f6ef | 4825 | tb->icount = num_insns; |
e8af50a3 | 4826 | } |
7a3f1944 | 4827 | #ifdef DEBUG_DISAS |
e19e89a5 | 4828 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
0f8a249a BS |
4829 | fprintf(logfile, "--------------\n"); |
4830 | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start)); | |
4831 | target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0); | |
4832 | fprintf(logfile, "\n"); | |
cf495bcf | 4833 | } |
7a3f1944 | 4834 | #endif |
7a3f1944 FB |
4835 | } |
4836 | ||
2cfc5f17 | 4837 | void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb) |
7a3f1944 | 4838 | { |
2cfc5f17 | 4839 | gen_intermediate_code_internal(tb, 0, env); |
7a3f1944 FB |
4840 | } |
4841 | ||
2cfc5f17 | 4842 | void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb) |
7a3f1944 | 4843 | { |
2cfc5f17 | 4844 | gen_intermediate_code_internal(tb, 1, env); |
7a3f1944 FB |
4845 | } |
4846 | ||
c48fcb47 | 4847 | void gen_intermediate_code_init(CPUSPARCState *env) |
e80cfcfc | 4848 | { |
f5069b26 | 4849 | unsigned int i; |
c48fcb47 | 4850 | static int inited; |
f5069b26 BS |
4851 | static const char * const gregnames[8] = { |
4852 | NULL, // g0 not used | |
4853 | "g1", | |
4854 | "g2", | |
4855 | "g3", | |
4856 | "g4", | |
4857 | "g5", | |
4858 | "g6", | |
4859 | "g7", | |
4860 | }; | |
aaed909a | 4861 | |
1a2fb1c0 BS |
4862 | /* init various static tables */ |
4863 | if (!inited) { | |
4864 | inited = 1; | |
4865 | ||
1a2fb1c0 | 4866 | cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env"); |
db4a4ea4 BS |
4867 | cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0, |
4868 | offsetof(CPUState, regwptr), | |
4869 | "regwptr"); | |
1a2fb1c0 | 4870 | #ifdef TARGET_SPARC64 |
dc99a3f2 BS |
4871 | cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32, |
4872 | TCG_AREG0, offsetof(CPUState, xcc), | |
4873 | "xcc"); | |
255e1fcb BS |
4874 | cpu_asi = tcg_global_mem_new(TCG_TYPE_I32, |
4875 | TCG_AREG0, offsetof(CPUState, asi), | |
4876 | "asi"); | |
4877 | cpu_fprs = tcg_global_mem_new(TCG_TYPE_I32, | |
4878 | TCG_AREG0, offsetof(CPUState, fprs), | |
4879 | "fprs"); | |
4880 | cpu_gsr = tcg_global_mem_new(TCG_TYPE_TL, | |
4881 | TCG_AREG0, offsetof(CPUState, gsr), | |
4882 | "gsr"); | |
4883 | cpu_tick_cmpr = tcg_global_mem_new(TCG_TYPE_TL, | |
4884 | TCG_AREG0, | |
4885 | offsetof(CPUState, tick_cmpr), | |
4886 | "tick_cmpr"); | |
4887 | cpu_stick_cmpr = tcg_global_mem_new(TCG_TYPE_TL, | |
4888 | TCG_AREG0, | |
4889 | offsetof(CPUState, stick_cmpr), | |
4890 | "stick_cmpr"); | |
4891 | cpu_hstick_cmpr = tcg_global_mem_new(TCG_TYPE_TL, | |
4892 | TCG_AREG0, | |
4893 | offsetof(CPUState, hstick_cmpr), | |
4894 | "hstick_cmpr"); | |
4895 | cpu_hintp = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, | |
4896 | offsetof(CPUState, hintp), | |
4897 | "hintp"); | |
4898 | cpu_htba = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, | |
4899 | offsetof(CPUState, htba), | |
4900 | "htba"); | |
4901 | cpu_hver = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, | |
4902 | offsetof(CPUState, hver), | |
4903 | "hver"); | |
4904 | cpu_ssr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, | |
4905 | offsetof(CPUState, ssr), "ssr"); | |
4906 | cpu_ver = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, | |
4907 | offsetof(CPUState, version), "ver"); | |
4908 | #else | |
4909 | cpu_wim = tcg_global_mem_new(TCG_TYPE_I32, | |
4910 | TCG_AREG0, offsetof(CPUState, wim), | |
4911 | "wim"); | |
1a2fb1c0 | 4912 | #endif |
7c60cc4b | 4913 | cpu_cond = tcg_global_mem_new(TCG_TYPE_TL, |
77f193da BS |
4914 | TCG_AREG0, offsetof(CPUState, cond), |
4915 | "cond"); | |
dc99a3f2 BS |
4916 | cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL, |
4917 | TCG_AREG0, offsetof(CPUState, cc_src), | |
4918 | "cc_src"); | |
d9bdab86 BS |
4919 | cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
4920 | offsetof(CPUState, cc_src2), | |
4921 | "cc_src2"); | |
dc99a3f2 BS |
4922 | cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL, |
4923 | TCG_AREG0, offsetof(CPUState, cc_dst), | |
4924 | "cc_dst"); | |
4925 | cpu_psr = tcg_global_mem_new(TCG_TYPE_I32, | |
4926 | TCG_AREG0, offsetof(CPUState, psr), | |
4927 | "psr"); | |
87e92502 BS |
4928 | cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL, |
4929 | TCG_AREG0, offsetof(CPUState, fsr), | |
4930 | "fsr"); | |
48d5c82b BS |
4931 | cpu_pc = tcg_global_mem_new(TCG_TYPE_TL, |
4932 | TCG_AREG0, offsetof(CPUState, pc), | |
4933 | "pc"); | |
4934 | cpu_npc = tcg_global_mem_new(TCG_TYPE_TL, | |
4935 | TCG_AREG0, offsetof(CPUState, npc), | |
4936 | "npc"); | |
255e1fcb BS |
4937 | cpu_y = tcg_global_mem_new(TCG_TYPE_TL, |
4938 | TCG_AREG0, offsetof(CPUState, y), "y"); | |
4939 | #ifndef CONFIG_USER_ONLY | |
4940 | cpu_tbr = tcg_global_mem_new(TCG_TYPE_TL, | |
4941 | TCG_AREG0, offsetof(CPUState, tbr), | |
4942 | "tbr"); | |
4943 | #endif | |
f5069b26 BS |
4944 | for (i = 1; i < 8; i++) |
4945 | cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, | |
4946 | offsetof(CPUState, gregs[i]), | |
4947 | gregnames[i]); | |
c9e03d8f BS |
4948 | /* register helpers */ |
4949 | ||
4950 | #undef DEF_HELPER | |
4951 | #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); | |
4952 | #include "helper.h" | |
1a2fb1c0 | 4953 | } |
658138bc | 4954 | } |
d2856f1a AJ |
4955 | |
4956 | void gen_pc_load(CPUState *env, TranslationBlock *tb, | |
4957 | unsigned long searched_pc, int pc_pos, void *puc) | |
4958 | { | |
4959 | target_ulong npc; | |
4960 | env->pc = gen_opc_pc[pc_pos]; | |
4961 | npc = gen_opc_npc[pc_pos]; | |
4962 | if (npc == 1) { | |
4963 | /* dynamic NPC: already stored */ | |
4964 | } else if (npc == 2) { | |
4965 | target_ulong t2 = (target_ulong)(unsigned long)puc; | |
4966 | /* jump PC: use T2 and the jump targets of the translation */ | |
4967 | if (t2) | |
4968 | env->npc = gen_opc_jump_pc[0]; | |
4969 | else | |
4970 | env->npc = gen_opc_jump_pc[1]; | |
4971 | } else { | |
4972 | env->npc = npc; | |
4973 | } | |
4974 | } |