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[qemu.git] / target-sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
7a3f1944
FB		 23 TODO-list:
24
3475187d 25 Rest of V9 instructions, VIS instructions
bd497938 26 NPC/PC static optimisations (use JUMP_TB when possible)
7a3f1944 27 Optimize synthetic instructions
bd497938 28*/
7a3f1944
FB		 29
30#include <stdarg.h>
31#include <stdlib.h>
32#include <stdio.h>
33#include <string.h>
34#include <inttypes.h>
35
36#include "cpu.h"
37#include "exec-all.h"
38#include "disas.h"
1a2fb1c0 39#include "helper.h"
57fec1fe 40#include "tcg-op.h"
7a3f1944
FB		 41
42#define DEBUG_DISAS
43
72cbca10
FB		 44#define DYNAMIC_PC 1 /* dynamic pc value */
45#define JUMP_PC 2 /* dynamic pc value which takes only two values
46 according to jump_pc[T2] */
47
1a2fb1c0 48/* global register indexes */
d9bdab86 49static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
48d5c82b 50static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
6ae20372 51static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
dc99a3f2
BS		 52#ifdef TARGET_SPARC64
53static TCGv cpu_xcc;
54#endif
1a2fb1c0 55/* local register indexes (only used inside old micro ops) */
8911f501 56static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
1a2fb1c0 57
7a3f1944 58typedef struct DisasContext {
0f8a249a
BS		 59 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
60 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 61 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 62 int is_br;
e8af50a3 63 int mem_idx;
a80dde08 64 int fpu_enabled;
cf495bcf 65 struct TranslationBlock *tb;
7a3f1944
FB		 66} DisasContext;
67
7a3f1944
FB		 68extern FILE *logfile;
69extern int loglevel;
70
3475187d 71// This function uses non-native bit order
7a3f1944
FB		 72#define GET_FIELD(X, FROM, TO) \
73 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
74
3475187d
FB		 75// This function uses the order in the manuals, i.e. bit 0 is 2^0
76#define GET_FIELD_SP(X, FROM, TO) \
77 GET_FIELD(X, 31 - (TO), 31 - (FROM))
78
79#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 80#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 81
82#ifdef TARGET_SPARC64
19f329ad 83#define FFPREG(r) (r)
0387d928 84#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 85#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 86#else
19f329ad 87#define FFPREG(r) (r)
c185970a 88#define DFPREG(r) (r & 0x1e)
1f587329 89#define QFPREG(r) (r & 0x1c)
3475187d
FB		 90#endif
91
92static int sign_extend(int x, int len)
93{
94 len = 32 - len;
95 return (x << len) >> len;
96}
97
7a3f1944
FB		 98#define IS_IMM (insn & (1<<13))
99
ff07ec83
BS		 100/* floating point registers moves */
101static void gen_op_load_fpr_FT0(unsigned int src)
102{
8911f501
BS		 103 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
104 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
3475187d 105}
ff07ec83
BS		 106
107static void gen_op_load_fpr_FT1(unsigned int src)
108{
8911f501
BS		 109 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
110 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
e8af50a3
FB		 111}
112
ff07ec83
BS		 113static void gen_op_store_FT0_fpr(unsigned int dst)
114{
8911f501
BS		 115 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
116 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
ff07ec83
BS		 117}
118
119static void gen_op_load_fpr_DT0(unsigned int src)
120{
8911f501
BS		 121 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
122 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
123 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
124 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
ff07ec83
BS		 125}
126
127static void gen_op_load_fpr_DT1(unsigned int src)
128{
8911f501
BS		 129 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
130 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.upper));
131 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
132 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.lower));
ff07ec83
BS		 133}
134
135static void gen_op_store_DT0_fpr(unsigned int dst)
136{
8911f501
BS		 137 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
138 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
139 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
140 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
ff07ec83
BS		 141}
142
143#ifdef CONFIG_USER_ONLY
144static void gen_op_load_fpr_QT0(unsigned int src)
145{
8911f501
BS		 146 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
147 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
148 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
149 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
150 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
151 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
152 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
153 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
ff07ec83
BS		 154}
155
156static void gen_op_load_fpr_QT1(unsigned int src)
157{
8911f501
BS		 158 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
159 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost));
160 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
161 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper));
162 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
163 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower));
164 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
165 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest));
ff07ec83
BS		 166}
167
168static void gen_op_store_QT0_fpr(unsigned int dst)
169{
8911f501
BS		 170 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
171 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
172 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
173 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
174 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
175 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
176 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
177 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
ff07ec83 178}
1f587329
BS		 179#endif
180
81ad8ba2
BS		 181/* moves */
182#ifdef CONFIG_USER_ONLY
3475187d 183#define supervisor(dc) 0
81ad8ba2 184#ifdef TARGET_SPARC64
e9ebed4d 185#define hypervisor(dc) 0
81ad8ba2 186#endif
3475187d 187#define gen_op_ldst(name) gen_op_##name##_raw()
3475187d 188#else
6f27aba6 189#define supervisor(dc) (dc->mem_idx >= 1)
81ad8ba2
BS		 190#ifdef TARGET_SPARC64
191#define hypervisor(dc) (dc->mem_idx == 2)
6f27aba6
BS		 192#define OP_LD_TABLE(width) \
193 static GenOpFunc * const gen_op_##width[] = { \
194 &gen_op_##width##_user, \
195 &gen_op_##width##_kernel, \
196 &gen_op_##width##_hypv, \
197 };
198#else
0f8a249a 199#define OP_LD_TABLE(width) \
a68156d0 200 static GenOpFunc * const gen_op_##width[] = { \
0f8a249a
BS		 201 &gen_op_##width##_user, \
202 &gen_op_##width##_kernel, \
81ad8ba2 203 };
3475187d 204#endif
6f27aba6
BS		 205#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
206#endif
e8af50a3 207
81ad8ba2 208#ifndef CONFIG_USER_ONLY
b25deda7
BS		 209#ifdef __i386__
210OP_LD_TABLE(std);
211#endif /* __i386__ */
e8af50a3 212OP_LD_TABLE(stdf);
e8af50a3 213OP_LD_TABLE(lddf);
81ad8ba2
BS		 214#endif
215
1a2fb1c0 216#ifdef TARGET_ABI32
8911f501 217#define ABI32_MASK(addr) tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
1a2fb1c0
BS		 218#else
219#define ABI32_MASK(addr)
220#endif
3391c818 221
1a2fb1c0 222static inline void gen_movl_reg_TN(int reg, TCGv tn)
81ad8ba2 223{
1a2fb1c0
BS		 224 if (reg == 0)
225 tcg_gen_movi_tl(tn, 0);
226 else if (reg < 8)
f5069b26 227 tcg_gen_mov_tl(tn, cpu_gregs[reg]);
1a2fb1c0 228 else {
1a2fb1c0 229 tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
81ad8ba2
BS		 230 }
231}
232
1a2fb1c0 233static inline void gen_movl_TN_reg(int reg, TCGv tn)
81ad8ba2 234{
1a2fb1c0
BS		 235 if (reg == 0)
236 return;
237 else if (reg < 8)
f5069b26 238 tcg_gen_mov_tl(cpu_gregs[reg], tn);
1a2fb1c0 239 else {
1a2fb1c0 240 tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
81ad8ba2
BS		 241 }
242}
243
5fafdf24 244static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 245 target_ulong pc, target_ulong npc)
246{
247 TranslationBlock *tb;
248
249 tb = s->tb;
250 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
251 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
252 /* jump to same page: we can use a direct jump */
57fec1fe 253 tcg_gen_goto_tb(tb_num);
2f5680ee
BS		 254 tcg_gen_movi_tl(cpu_pc, pc);
255 tcg_gen_movi_tl(cpu_npc, npc);
57fec1fe 256 tcg_gen_exit_tb((long)tb + tb_num);
6e256c93
FB		 257 } else {
258 /* jump to another page: currently not optimized */
2f5680ee
BS		 259 tcg_gen_movi_tl(cpu_pc, pc);
260 tcg_gen_movi_tl(cpu_npc, npc);
57fec1fe 261 tcg_gen_exit_tb(0);
6e256c93
FB		 262 }
263}
264
19f329ad
BS		 265// XXX suboptimal
266static inline void gen_mov_reg_N(TCGv reg, TCGv src)
267{
8911f501 268 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 269 tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
19f329ad
BS		 270 tcg_gen_andi_tl(reg, reg, 0x1);
271}
272
273static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
274{
8911f501 275 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 276 tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
19f329ad
BS		 277 tcg_gen_andi_tl(reg, reg, 0x1);
278}
279
280static inline void gen_mov_reg_V(TCGv reg, TCGv src)
281{
8911f501 282 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 283 tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
19f329ad
BS		 284 tcg_gen_andi_tl(reg, reg, 0x1);
285}
286
287static inline void gen_mov_reg_C(TCGv reg, TCGv src)
288{
8911f501 289 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 290 tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
19f329ad
BS		 291 tcg_gen_andi_tl(reg, reg, 0x1);
292}
293
ce5b3c3d 294static inline void gen_cc_clear_icc(void)
dc99a3f2
BS		 295{
296 tcg_gen_movi_i32(cpu_psr, 0);
ce5b3c3d
BS		 297}
298
dc99a3f2 299#ifdef TARGET_SPARC64
ce5b3c3d
BS		 300static inline void gen_cc_clear_xcc(void)
301{
dc99a3f2 302 tcg_gen_movi_i32(cpu_xcc, 0);
dc99a3f2 303}
ce5b3c3d 304#endif
dc99a3f2
BS		 305
306/* old op:
307 if (!T0)
308 env->psr |= PSR_ZERO;
309 if ((int32_t) T0 < 0)
310 env->psr |= PSR_NEG;
311*/
ce5b3c3d 312static inline void gen_cc_NZ_icc(TCGv dst)
dc99a3f2 313{
8911f501 314 TCGv r_temp;
dc99a3f2 315 int l1, l2;
dc99a3f2
BS		 316
317 l1 = gen_new_label();
318 l2 = gen_new_label();
8911f501
BS		 319 r_temp = tcg_temp_new(TCG_TYPE_TL);
320 tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
321 tcg_gen_brcond_tl(TCG_COND_NE, r_temp, tcg_const_tl(0), l1);
dc99a3f2
BS		 322 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
323 gen_set_label(l1);
bdf46ea2 324 tcg_gen_ext_i32_tl(r_temp, dst);
8911f501 325 tcg_gen_brcond_tl(TCG_COND_GE, r_temp, tcg_const_tl(0), l2);
dc99a3f2
BS		 326 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
327 gen_set_label(l2);
ce5b3c3d
BS		 328}
329
dc99a3f2 330#ifdef TARGET_SPARC64
ce5b3c3d
BS		 331static inline void gen_cc_NZ_xcc(TCGv dst)
332{
333 int l1, l2;
334
335 l1 = gen_new_label();
336 l2 = gen_new_label();
337 tcg_gen_brcond_tl(TCG_COND_NE, dst, tcg_const_tl(0), l1);
338 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
339 gen_set_label(l1);
340 tcg_gen_brcond_tl(TCG_COND_GE, dst, tcg_const_tl(0), l2);
341 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
342 gen_set_label(l2);
dc99a3f2 343}
ce5b3c3d 344#endif
dc99a3f2
BS		 345
346/* old op:
347 if (T0 < src1)
348 env->psr |= PSR_CARRY;
349*/
ce5b3c3d 350static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
dc99a3f2 351{
8911f501 352 TCGv r_temp;
dc99a3f2
BS		 353 int l1;
354
355 l1 = gen_new_label();
8911f501
BS		 356 r_temp = tcg_temp_new(TCG_TYPE_TL);
357 tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
358 tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
dc99a3f2
BS		 359 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
360 gen_set_label(l1);
ce5b3c3d
BS		 361}
362
dc99a3f2 363#ifdef TARGET_SPARC64
ce5b3c3d
BS		 364static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
365{
366 int l1;
dc99a3f2 367
ce5b3c3d
BS		 368 l1 = gen_new_label();
369 tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
370 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
371 gen_set_label(l1);
dc99a3f2 372}
ce5b3c3d 373#endif
dc99a3f2
BS		 374
375/* old op:
376 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
377 env->psr |= PSR_OVF;
378*/
ce5b3c3d 379static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 380{
0425bee5 381 TCGv r_temp;
dc99a3f2
BS		 382
383 r_temp = tcg_temp_new(TCG_TYPE_TL);
dc99a3f2
BS		 384 tcg_gen_xor_tl(r_temp, src1, src2);
385 tcg_gen_xori_tl(r_temp, r_temp, -1);
0425bee5
BS		 386 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
387 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
388 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
653ccb80
BS		 389 tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
390 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
391 tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
ce5b3c3d
BS		 392}
393
dc99a3f2 394#ifdef TARGET_SPARC64
ce5b3c3d
BS		 395static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
396{
397 TCGv r_temp;
ce5b3c3d
BS		 398
399 r_temp = tcg_temp_new(TCG_TYPE_TL);
400 tcg_gen_xor_tl(r_temp, src1, src2);
401 tcg_gen_xori_tl(r_temp, r_temp, -1);
402 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
403 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
404 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
653ccb80
BS		 405 tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
406 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
407 tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
dc99a3f2 408}
ce5b3c3d 409#endif
dc99a3f2
BS		 410
411static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
412{
0425bee5 413 TCGv r_temp;
dc99a3f2
BS		 414 int l1;
415
416 l1 = gen_new_label();
417
418 r_temp = tcg_temp_new(TCG_TYPE_TL);
dc99a3f2
BS		 419 tcg_gen_xor_tl(r_temp, src1, src2);
420 tcg_gen_xori_tl(r_temp, r_temp, -1);
0425bee5
BS		 421 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
422 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
423 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
8911f501 424 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
2f5680ee 425 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
dc99a3f2 426 gen_set_label(l1);
dc99a3f2
BS		 427}
428
429static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
430{
431 int l1;
dc99a3f2
BS		 432
433 l1 = gen_new_label();
0425bee5
BS		 434 tcg_gen_or_tl(cpu_tmp0, src1, src2);
435 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
436 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
dc99a3f2
BS		 437 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
438 gen_set_label(l1);
439}
440
441static inline void gen_tag_tv(TCGv src1, TCGv src2)
442{
443 int l1;
dc99a3f2
BS		 444
445 l1 = gen_new_label();
0425bee5
BS		 446 tcg_gen_or_tl(cpu_tmp0, src1, src2);
447 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
448 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
2f5680ee 449 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
dc99a3f2
BS		 450 gen_set_label(l1);
451}
452
4af984a7 453static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 454{
4af984a7 455 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 456 tcg_gen_mov_tl(cpu_cc_src2, src2);
4af984a7 457 tcg_gen_add_tl(dst, src1, src2);
ce5b3c3d 458 gen_cc_clear_icc();
4af984a7
BS		 459 gen_cc_NZ_icc(dst);
460 gen_cc_C_add_icc(dst, cpu_cc_src);
6f551262 461 gen_cc_V_add_icc(dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d
BS		 462#ifdef TARGET_SPARC64
463 gen_cc_clear_xcc();
4af984a7
BS		 464 gen_cc_NZ_xcc(dst);
465 gen_cc_C_add_xcc(dst, cpu_cc_src);
6f551262 466 gen_cc_V_add_xcc(dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 467#endif
dc99a3f2
BS		 468}
469
4af984a7 470static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 471{
4af984a7 472 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 473 tcg_gen_mov_tl(cpu_cc_src2, src2);
dc99a3f2 474 gen_mov_reg_C(cpu_tmp0, cpu_psr);
4af984a7 475 tcg_gen_add_tl(dst, src1, cpu_tmp0);
ce5b3c3d 476 gen_cc_clear_icc();
4af984a7 477 gen_cc_C_add_icc(dst, cpu_cc_src);
ce5b3c3d
BS		 478#ifdef TARGET_SPARC64
479 gen_cc_clear_xcc();
4af984a7 480 gen_cc_C_add_xcc(dst, cpu_cc_src);
ce5b3c3d 481#endif
6f551262 482 tcg_gen_add_tl(dst, dst, cpu_cc_src2);
4af984a7
BS		 483 gen_cc_NZ_icc(dst);
484 gen_cc_C_add_icc(dst, cpu_cc_src);
6f551262 485 gen_cc_V_add_icc(dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 486#ifdef TARGET_SPARC64
4af984a7
BS		 487 gen_cc_NZ_xcc(dst);
488 gen_cc_C_add_xcc(dst, cpu_cc_src);
6f551262 489 gen_cc_V_add_xcc(dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 490#endif
dc99a3f2
BS		 491}
492
4af984a7 493static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 494{
4af984a7 495 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 496 tcg_gen_mov_tl(cpu_cc_src2, src2);
4af984a7 497 tcg_gen_add_tl(dst, src1, src2);
ce5b3c3d 498 gen_cc_clear_icc();
4af984a7
BS		 499 gen_cc_NZ_icc(dst);
500 gen_cc_C_add_icc(dst, cpu_cc_src);
6f551262
BS		 501 gen_cc_V_add_icc(dst, cpu_cc_src, cpu_cc_src2);
502 gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
ce5b3c3d
BS		 503#ifdef TARGET_SPARC64
504 gen_cc_clear_xcc();
4af984a7
BS		 505 gen_cc_NZ_xcc(dst);
506 gen_cc_C_add_xcc(dst, cpu_cc_src);
6f551262 507 gen_cc_V_add_xcc(dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 508#endif
dc99a3f2
BS		 509}
510
4af984a7 511static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 512{
4af984a7 513 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262
BS		 514 tcg_gen_mov_tl(cpu_cc_src2, src2);
515 gen_tag_tv(cpu_cc_src, cpu_cc_src2);
4af984a7 516 tcg_gen_add_tl(dst, src1, src2);
6f551262 517 gen_add_tv(dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 518 gen_cc_clear_icc();
4af984a7
BS		 519 gen_cc_NZ_icc(dst);
520 gen_cc_C_add_icc(dst, cpu_cc_src);
ce5b3c3d
BS		 521#ifdef TARGET_SPARC64
522 gen_cc_clear_xcc();
4af984a7
BS		 523 gen_cc_NZ_xcc(dst);
524 gen_cc_C_add_xcc(dst, cpu_cc_src);
6f551262 525 gen_cc_V_add_xcc(dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 526#endif
dc99a3f2
BS		 527}
528
529/* old op:
530 if (src1 < T1)
531 env->psr |= PSR_CARRY;
532*/
ce5b3c3d 533static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
dc99a3f2 534{
8911f501 535 TCGv r_temp1, r_temp2;
dc99a3f2
BS		 536 int l1;
537
538 l1 = gen_new_label();
8911f501
BS		 539 r_temp1 = tcg_temp_new(TCG_TYPE_TL);
540 r_temp2 = tcg_temp_new(TCG_TYPE_TL);
541 tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
542 tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
543 tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
dc99a3f2
BS		 544 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
545 gen_set_label(l1);
ce5b3c3d
BS		 546}
547
dc99a3f2 548#ifdef TARGET_SPARC64
ce5b3c3d
BS		 549static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
550{
551 int l1;
dc99a3f2 552
ce5b3c3d
BS		 553 l1 = gen_new_label();
554 tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
555 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
556 gen_set_label(l1);
dc99a3f2 557}
ce5b3c3d 558#endif
dc99a3f2
BS		 559
560/* old op:
561 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
562 env->psr |= PSR_OVF;
563*/
ce5b3c3d 564static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 565{
0425bee5 566 TCGv r_temp;
dc99a3f2
BS		 567
568 r_temp = tcg_temp_new(TCG_TYPE_TL);
dc99a3f2 569 tcg_gen_xor_tl(r_temp, src1, src2);
0425bee5
BS		 570 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
571 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
572 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
653ccb80
BS		 573 tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
574 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
575 tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
ce5b3c3d
BS		 576}
577
dc99a3f2 578#ifdef TARGET_SPARC64
ce5b3c3d
BS		 579static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
580{
581 TCGv r_temp;
ce5b3c3d
BS		 582
583 r_temp = tcg_temp_new(TCG_TYPE_TL);
584 tcg_gen_xor_tl(r_temp, src1, src2);
585 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
586 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
587 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
653ccb80
BS		 588 tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
589 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
590 tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
dc99a3f2 591}
ce5b3c3d 592#endif
dc99a3f2
BS		 593
594static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
595{
0425bee5 596 TCGv r_temp;
dc99a3f2
BS		 597 int l1;
598
599 l1 = gen_new_label();
600
601 r_temp = tcg_temp_new(TCG_TYPE_TL);
dc99a3f2 602 tcg_gen_xor_tl(r_temp, src1, src2);
0425bee5
BS		 603 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
604 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
605 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
8911f501 606 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
2f5680ee 607 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
dc99a3f2 608 gen_set_label(l1);
dc99a3f2
BS		 609}
610
4af984a7 611static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 612{
4af984a7 613 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 614 tcg_gen_mov_tl(cpu_cc_src2, src2);
4af984a7 615 tcg_gen_sub_tl(dst, src1, src2);
ce5b3c3d 616 gen_cc_clear_icc();
4af984a7 617 gen_cc_NZ_icc(dst);
6f551262
BS		 618 gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
619 gen_cc_V_sub_icc(dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d
BS		 620#ifdef TARGET_SPARC64
621 gen_cc_clear_xcc();
4af984a7 622 gen_cc_NZ_xcc(dst);
6f551262
BS		 623 gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
624 gen_cc_V_sub_xcc(dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 625#endif
dc99a3f2
BS		 626}
627
4af984a7 628static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 629{
4af984a7 630 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 631 tcg_gen_mov_tl(cpu_cc_src2, src2);
dc99a3f2 632 gen_mov_reg_C(cpu_tmp0, cpu_psr);
4af984a7 633 tcg_gen_sub_tl(dst, src1, cpu_tmp0);
ce5b3c3d 634 gen_cc_clear_icc();
4af984a7 635 gen_cc_C_sub_icc(dst, cpu_cc_src);
ce5b3c3d
BS		 636#ifdef TARGET_SPARC64
637 gen_cc_clear_xcc();
4af984a7 638 gen_cc_C_sub_xcc(dst, cpu_cc_src);
ce5b3c3d 639#endif
6f551262 640 tcg_gen_sub_tl(dst, dst, cpu_cc_src2);
4af984a7
BS		 641 gen_cc_NZ_icc(dst);
642 gen_cc_C_sub_icc(dst, cpu_cc_src);
6f551262 643 gen_cc_V_sub_icc(dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 644#ifdef TARGET_SPARC64
4af984a7
BS		 645 gen_cc_NZ_xcc(dst);
646 gen_cc_C_sub_xcc(dst, cpu_cc_src);
6f551262 647 gen_cc_V_sub_xcc(dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 648#endif
dc99a3f2
BS		 649}
650
4af984a7 651static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 652{
4af984a7 653 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 654 tcg_gen_mov_tl(cpu_cc_src2, src2);
4af984a7 655 tcg_gen_sub_tl(dst, src1, src2);
ce5b3c3d 656 gen_cc_clear_icc();
4af984a7 657 gen_cc_NZ_icc(dst);
6f551262
BS		 658 gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
659 gen_cc_V_sub_icc(dst, cpu_cc_src, cpu_cc_src2);
660 gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
ce5b3c3d
BS		 661#ifdef TARGET_SPARC64
662 gen_cc_clear_xcc();
4af984a7 663 gen_cc_NZ_xcc(dst);
6f551262
BS		 664 gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
665 gen_cc_V_sub_xcc(dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 666#endif
dc99a3f2
BS		 667}
668
4af984a7 669static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 670{
4af984a7 671 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262
BS		 672 tcg_gen_mov_tl(cpu_cc_src2, src2);
673 gen_tag_tv(cpu_cc_src, cpu_cc_src2);
4af984a7 674 tcg_gen_sub_tl(dst, src1, src2);
6f551262 675 gen_sub_tv(dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 676 gen_cc_clear_icc();
4af984a7 677 gen_cc_NZ_icc(dst);
6f551262 678 gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
ce5b3c3d
BS		 679#ifdef TARGET_SPARC64
680 gen_cc_clear_xcc();
4af984a7 681 gen_cc_NZ_xcc(dst);
6f551262
BS		 682 gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
683 gen_cc_V_sub_xcc(dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 684#endif
dc99a3f2
BS		 685}
686
4af984a7 687static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
d9bdab86 688{
7127fe84 689 TCGv r_temp, r_temp2;
6f551262 690 int l1;
d9bdab86
BS		 691
692 l1 = gen_new_label();
d9bdab86 693 r_temp = tcg_temp_new(TCG_TYPE_TL);
7127fe84 694 r_temp2 = tcg_temp_new(TCG_TYPE_I32);
d9bdab86
BS		 695
696 /* old op:
697 if (!(env->y & 1))
698 T1 = 0;
699 */
6f551262 700 tcg_gen_mov_tl(cpu_cc_src, src1);
7127fe84
BS		 701 tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
702 tcg_gen_trunc_tl_i32(r_temp2, r_temp);
703 tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
4af984a7 704 tcg_gen_mov_tl(cpu_cc_src2, src2);
6f551262 705 tcg_gen_brcond_i32(TCG_COND_NE, r_temp2, tcg_const_i32(0), l1);
d9bdab86 706 tcg_gen_movi_tl(cpu_cc_src2, 0);
6f551262 707 gen_set_label(l1);
d9bdab86
BS		 708
709 // b2 = T0 & 1;
710 // env->y = (b2 << 31) | (env->y >> 1);
6f551262 711 tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src);
7127fe84
BS		 712 tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
713 tcg_gen_shli_i32(r_temp2, r_temp2, 31);
8911f501
BS		 714 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
715 tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
7127fe84 716 tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
8911f501 717 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
d9bdab86
BS		 718
719 // b1 = N ^ V;
720 gen_mov_reg_N(cpu_tmp0, cpu_psr);
721 gen_mov_reg_V(r_temp, cpu_psr);
722 tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
723
724 // T0 = (b1 << 31) | (T0 >> 1);
725 // src1 = T0;
726 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
6f551262 727 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
d9bdab86
BS		 728 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
729
730 /* do addition and update flags */
4af984a7 731 tcg_gen_add_tl(dst, cpu_cc_src, cpu_cc_src2);
d9bdab86 732
ce5b3c3d 733 gen_cc_clear_icc();
4af984a7
BS		 734 gen_cc_NZ_icc(dst);
735 gen_cc_V_add_icc(dst, cpu_cc_src, cpu_cc_src2);
736 gen_cc_C_add_icc(dst, cpu_cc_src);
d9bdab86
BS		 737}
738
4af984a7 739static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
8879d139
BS		 740{
741 TCGv r_temp, r_temp2;
742
743 r_temp = tcg_temp_new(TCG_TYPE_I64);
744 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
745
4af984a7
BS		 746 tcg_gen_extu_tl_i64(r_temp, src2);
747 tcg_gen_extu_tl_i64(r_temp2, src1);
8879d139
BS		 748 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
749
750 tcg_gen_shri_i64(r_temp, r_temp2, 32);
751 tcg_gen_trunc_i64_i32(r_temp, r_temp);
752 tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
753#ifdef TARGET_SPARC64
4af984a7 754 tcg_gen_mov_i64(dst, r_temp2);
8879d139 755#else
4af984a7 756 tcg_gen_trunc_i64_tl(dst, r_temp2);
8879d139 757#endif
8879d139
BS		 758}
759
4af984a7 760static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
8879d139
BS		 761{
762 TCGv r_temp, r_temp2;
763
764 r_temp = tcg_temp_new(TCG_TYPE_I64);
765 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
766
4af984a7
BS		 767 tcg_gen_ext_tl_i64(r_temp, src2);
768 tcg_gen_ext_tl_i64(r_temp2, src1);
8879d139
BS		 769 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
770
771 tcg_gen_shri_i64(r_temp, r_temp2, 32);
772 tcg_gen_trunc_i64_i32(r_temp, r_temp);
773 tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
774#ifdef TARGET_SPARC64
4af984a7 775 tcg_gen_mov_i64(dst, r_temp2);
8879d139 776#else
4af984a7 777 tcg_gen_trunc_i64_tl(dst, r_temp2);
8879d139 778#endif
8879d139
BS		 779}
780
1a7b60e7 781#ifdef TARGET_SPARC64
8911f501 782static inline void gen_trap_ifdivzero_tl(TCGv divisor)
1a7b60e7
BS		 783{
784 int l1;
785
786 l1 = gen_new_label();
8911f501 787 tcg_gen_brcond_tl(TCG_COND_NE, divisor, tcg_const_tl(0), l1);
2f5680ee 788 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_DIV_ZERO));
1a7b60e7
BS		 789 gen_set_label(l1);
790}
791
4af984a7 792static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
1a7b60e7
BS		 793{
794 int l1, l2;
795
796 l1 = gen_new_label();
797 l2 = gen_new_label();
6f551262
BS		 798 tcg_gen_mov_tl(cpu_cc_src, src1);
799 tcg_gen_mov_tl(cpu_cc_src2, src2);
4af984a7 800 gen_trap_ifdivzero_tl(src2);
6f551262
BS		 801 tcg_gen_brcond_tl(TCG_COND_NE, cpu_cc_src, tcg_const_tl(INT64_MIN), l1);
802 tcg_gen_brcond_tl(TCG_COND_NE, cpu_cc_src2, tcg_const_tl(-1), l1);
4af984a7 803 tcg_gen_movi_i64(dst, INT64_MIN);
06b3e1b3 804 tcg_gen_br(l2);
1a7b60e7 805 gen_set_label(l1);
6f551262 806 tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
1a7b60e7
BS		 807 gen_set_label(l2);
808}
809#endif
810
4af984a7 811static inline void gen_op_div_cc(TCGv dst)
dc99a3f2
BS		 812{
813 int l1;
dc99a3f2 814
ce5b3c3d 815 gen_cc_clear_icc();
4af984a7 816 gen_cc_NZ_icc(dst);
dc99a3f2 817 l1 = gen_new_label();
3b89f26c
BS		 818 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2));
819 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
dc99a3f2
BS		 820 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
821 gen_set_label(l1);
822}
823
4af984a7 824static inline void gen_op_logic_cc(TCGv dst)
dc99a3f2 825{
ce5b3c3d 826 gen_cc_clear_icc();
4af984a7 827 gen_cc_NZ_icc(dst);
ce5b3c3d
BS		 828#ifdef TARGET_SPARC64
829 gen_cc_clear_xcc();
4af984a7 830 gen_cc_NZ_xcc(dst);
ce5b3c3d 831#endif
dc99a3f2
BS		 832}
833
19f329ad
BS		 834// 1
835static inline void gen_op_eval_ba(TCGv dst)
836{
837 tcg_gen_movi_tl(dst, 1);
838}
839
840// Z
841static inline void gen_op_eval_be(TCGv dst, TCGv src)
842{
843 gen_mov_reg_Z(dst, src);
844}
845
846// Z | (N ^ V)
847static inline void gen_op_eval_ble(TCGv dst, TCGv src)
848{
0425bee5 849 gen_mov_reg_N(cpu_tmp0, src);
19f329ad 850 gen_mov_reg_V(dst, src);
0425bee5
BS		 851 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
852 gen_mov_reg_Z(cpu_tmp0, src);
853 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 854}
855
856// N ^ V
857static inline void gen_op_eval_bl(TCGv dst, TCGv src)
858{
0425bee5 859 gen_mov_reg_V(cpu_tmp0, src);
19f329ad 860 gen_mov_reg_N(dst, src);
0425bee5 861 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 862}
863
864// C | Z
865static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
866{
0425bee5 867 gen_mov_reg_Z(cpu_tmp0, src);
19f329ad 868 gen_mov_reg_C(dst, src);
0425bee5 869 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 870}
871
872// C
873static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
874{
875 gen_mov_reg_C(dst, src);
876}
877
878// V
879static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
880{
881 gen_mov_reg_V(dst, src);
882}
883
884// 0
885static inline void gen_op_eval_bn(TCGv dst)
886{
887 tcg_gen_movi_tl(dst, 0);
888}
889
890// N
891static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
892{
893 gen_mov_reg_N(dst, src);
894}
895
896// !Z
897static inline void gen_op_eval_bne(TCGv dst, TCGv src)
898{
899 gen_mov_reg_Z(dst, src);
900 tcg_gen_xori_tl(dst, dst, 0x1);
901}
902
903// !(Z | (N ^ V))
904static inline void gen_op_eval_bg(TCGv dst, TCGv src)
905{
0425bee5 906 gen_mov_reg_N(cpu_tmp0, src);
19f329ad 907 gen_mov_reg_V(dst, src);
0425bee5
BS		 908 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
909 gen_mov_reg_Z(cpu_tmp0, src);
910 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 911 tcg_gen_xori_tl(dst, dst, 0x1);
912}
913
914// !(N ^ V)
915static inline void gen_op_eval_bge(TCGv dst, TCGv src)
916{
0425bee5 917 gen_mov_reg_V(cpu_tmp0, src);
19f329ad 918 gen_mov_reg_N(dst, src);
0425bee5 919 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 920 tcg_gen_xori_tl(dst, dst, 0x1);
921}
922
923// !(C | Z)
924static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
925{
0425bee5 926 gen_mov_reg_Z(cpu_tmp0, src);
19f329ad 927 gen_mov_reg_C(dst, src);
0425bee5 928 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 929 tcg_gen_xori_tl(dst, dst, 0x1);
930}
931
932// !C
933static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
934{
935 gen_mov_reg_C(dst, src);
936 tcg_gen_xori_tl(dst, dst, 0x1);
937}
938
939// !N
940static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
941{
942 gen_mov_reg_N(dst, src);
943 tcg_gen_xori_tl(dst, dst, 0x1);
944}
945
946// !V
947static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
948{
949 gen_mov_reg_V(dst, src);
950 tcg_gen_xori_tl(dst, dst, 0x1);
951}
952
953/*
954 FPSR bit field FCC1 | FCC0:
955 0 =
956 1 <
957 2 >
958 3 unordered
959*/
960static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
961 unsigned int fcc_offset)
962{
8911f501 963 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 964 tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset);
19f329ad
BS		 965 tcg_gen_andi_tl(reg, reg, 0x1);
966}
967
968static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
969 unsigned int fcc_offset)
970{
8911f501 971 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 972 tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset);
19f329ad
BS		 973 tcg_gen_andi_tl(reg, reg, 0x1);
974}
975
976// !0: FCC0 | FCC1
977static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
978 unsigned int fcc_offset)
979{
19f329ad 980 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 981 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
982 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 983}
984
985// 1 or 2: FCC0 ^ FCC1
986static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
987 unsigned int fcc_offset)
988{
19f329ad 989 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 990 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
991 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 992}
993
994// 1 or 3: FCC0
995static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
996 unsigned int fcc_offset)
997{
998 gen_mov_reg_FCC0(dst, src, fcc_offset);
999}
1000
1001// 1: FCC0 & !FCC1
1002static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1003 unsigned int fcc_offset)
1004{
19f329ad 1005 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1006 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1007 tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1008 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1009}
1010
1011// 2 or 3: FCC1
1012static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1013 unsigned int fcc_offset)
1014{
1015 gen_mov_reg_FCC1(dst, src, fcc_offset);
1016}
1017
1018// 2: !FCC0 & FCC1
1019static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1020 unsigned int fcc_offset)
1021{
19f329ad
BS		 1022 gen_mov_reg_FCC0(dst, src, fcc_offset);
1023 tcg_gen_xori_tl(dst, dst, 0x1);
0425bee5
BS		 1024 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1025 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1026}
1027
1028// 3: FCC0 & FCC1
1029static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1030 unsigned int fcc_offset)
1031{
19f329ad 1032 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1033 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1034 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1035}
1036
1037// 0: !(FCC0 | FCC1)
1038static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1039 unsigned int fcc_offset)
1040{
19f329ad 1041 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1042 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1043 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1044 tcg_gen_xori_tl(dst, dst, 0x1);
1045}
1046
1047// 0 or 3: !(FCC0 ^ FCC1)
1048static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1049 unsigned int fcc_offset)
1050{
19f329ad 1051 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1052 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1053 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1054 tcg_gen_xori_tl(dst, dst, 0x1);
1055}
1056
1057// 0 or 2: !FCC0
1058static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1059 unsigned int fcc_offset)
1060{
1061 gen_mov_reg_FCC0(dst, src, fcc_offset);
1062 tcg_gen_xori_tl(dst, dst, 0x1);
1063}
1064
1065// !1: !(FCC0 & !FCC1)
1066static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1067 unsigned int fcc_offset)
1068{
19f329ad 1069 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1070 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1071 tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1072 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1073 tcg_gen_xori_tl(dst, dst, 0x1);
1074}
1075
1076// 0 or 1: !FCC1
1077static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1078 unsigned int fcc_offset)
1079{
1080 gen_mov_reg_FCC1(dst, src, fcc_offset);
1081 tcg_gen_xori_tl(dst, dst, 0x1);
1082}
1083
1084// !2: !(!FCC0 & FCC1)
1085static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1086 unsigned int fcc_offset)
1087{
19f329ad
BS		 1088 gen_mov_reg_FCC0(dst, src, fcc_offset);
1089 tcg_gen_xori_tl(dst, dst, 0x1);
0425bee5
BS		 1090 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1091 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1092 tcg_gen_xori_tl(dst, dst, 0x1);
1093}
1094
1095// !3: !(FCC0 & FCC1)
1096static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1097 unsigned int fcc_offset)
1098{
19f329ad 1099 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1100 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1101 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1102 tcg_gen_xori_tl(dst, dst, 0x1);
1103}
1104
46525e1f 1105static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
19f329ad 1106 target_ulong pc2, TCGv r_cond)
83469015
FB		 1107{
1108 int l1;
1109
1110 l1 = gen_new_label();
1111
0425bee5 1112 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
83469015 1113
6e256c93 1114 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 1115
1116 gen_set_label(l1);
6e256c93 1117 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 1118}
1119
46525e1f 1120static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
19f329ad 1121 target_ulong pc2, TCGv r_cond)
83469015
FB		 1122{
1123 int l1;
1124
1125 l1 = gen_new_label();
1126
0425bee5 1127 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
83469015 1128
6e256c93 1129 gen_goto_tb(dc, 0, pc2, pc1);
83469015
FB		 1130
1131 gen_set_label(l1);
6e256c93 1132 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
83469015
FB		 1133}
1134
19f329ad
BS		 1135static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1136 TCGv r_cond)
83469015
FB		 1137{
1138 int l1, l2;
1139
1140 l1 = gen_new_label();
1141 l2 = gen_new_label();
19f329ad 1142
0425bee5 1143 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
83469015 1144
2f5680ee 1145 tcg_gen_movi_tl(cpu_npc, npc1);
06b3e1b3 1146 tcg_gen_br(l2);
83469015
FB		 1147
1148 gen_set_label(l1);
2f5680ee 1149 tcg_gen_movi_tl(cpu_npc, npc2);
83469015
FB		 1150 gen_set_label(l2);
1151}
1152
4af984a7
BS		 1153/* call this function before using the condition register as it may
1154 have been set for a jump */
1155static inline void flush_cond(DisasContext *dc, TCGv cond)
83469015
FB		 1156{
1157 if (dc->npc == JUMP_PC) {
4af984a7 1158 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
83469015
FB		 1159 dc->npc = DYNAMIC_PC;
1160 }
1161}
1162
4af984a7 1163static inline void save_npc(DisasContext *dc, TCGv cond)
72cbca10
FB		 1164{
1165 if (dc->npc == JUMP_PC) {
4af984a7 1166 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
72cbca10
FB		 1167 dc->npc = DYNAMIC_PC;
1168 } else if (dc->npc != DYNAMIC_PC) {
2f5680ee 1169 tcg_gen_movi_tl(cpu_npc, dc->npc);
72cbca10
FB		 1170 }
1171}
1172
4af984a7 1173static inline void save_state(DisasContext *dc, TCGv cond)
72cbca10 1174{
2f5680ee 1175 tcg_gen_movi_tl(cpu_pc, dc->pc);
4af984a7 1176 save_npc(dc, cond);
72cbca10
FB		 1177}
1178
4af984a7 1179static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
0bee699e
FB		 1180{
1181 if (dc->npc == JUMP_PC) {
4af984a7 1182 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
48d5c82b 1183 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1184 dc->pc = DYNAMIC_PC;
1185 } else if (dc->npc == DYNAMIC_PC) {
48d5c82b 1186 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1187 dc->pc = DYNAMIC_PC;
1188 } else {
1189 dc->pc = dc->npc;
1190 }
1191}
1192
38bc628b
BS		 1193static inline void gen_op_next_insn(void)
1194{
48d5c82b
BS		 1195 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1196 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
38bc628b
BS		 1197}
1198
19f329ad
BS		 1199static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1200{
1201 TCGv r_src;
3475187d 1202
3475187d 1203#ifdef TARGET_SPARC64
19f329ad 1204 if (cc)
dc99a3f2 1205 r_src = cpu_xcc;
19f329ad 1206 else
dc99a3f2 1207 r_src = cpu_psr;
3475187d 1208#else
dc99a3f2 1209 r_src = cpu_psr;
3475187d 1210#endif
19f329ad
BS		 1211 switch (cond) {
1212 case 0x0:
1213 gen_op_eval_bn(r_dst);
1214 break;
1215 case 0x1:
1216 gen_op_eval_be(r_dst, r_src);
1217 break;
1218 case 0x2:
1219 gen_op_eval_ble(r_dst, r_src);
1220 break;
1221 case 0x3:
1222 gen_op_eval_bl(r_dst, r_src);
1223 break;
1224 case 0x4:
1225 gen_op_eval_bleu(r_dst, r_src);
1226 break;
1227 case 0x5:
1228 gen_op_eval_bcs(r_dst, r_src);
1229 break;
1230 case 0x6:
1231 gen_op_eval_bneg(r_dst, r_src);
1232 break;
1233 case 0x7:
1234 gen_op_eval_bvs(r_dst, r_src);
1235 break;
1236 case 0x8:
1237 gen_op_eval_ba(r_dst);
1238 break;
1239 case 0x9:
1240 gen_op_eval_bne(r_dst, r_src);
1241 break;
1242 case 0xa:
1243 gen_op_eval_bg(r_dst, r_src);
1244 break;
1245 case 0xb:
1246 gen_op_eval_bge(r_dst, r_src);
1247 break;
1248 case 0xc:
1249 gen_op_eval_bgu(r_dst, r_src);
1250 break;
1251 case 0xd:
1252 gen_op_eval_bcc(r_dst, r_src);
1253 break;
1254 case 0xe:
1255 gen_op_eval_bpos(r_dst, r_src);
1256 break;
1257 case 0xf:
1258 gen_op_eval_bvc(r_dst, r_src);
1259 break;
1260 }
1261}
7a3f1944 1262
19f329ad 1263static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
e8af50a3 1264{
19f329ad
BS		 1265 unsigned int offset;
1266
19f329ad
BS		 1267 switch (cc) {
1268 default:
1269 case 0x0:
1270 offset = 0;
1271 break;
1272 case 0x1:
1273 offset = 32 - 10;
1274 break;
1275 case 0x2:
1276 offset = 34 - 10;
1277 break;
1278 case 0x3:
1279 offset = 36 - 10;
1280 break;
1281 }
1282
1283 switch (cond) {
1284 case 0x0:
1285 gen_op_eval_bn(r_dst);
1286 break;
1287 case 0x1:
87e92502 1288 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
19f329ad
BS		 1289 break;
1290 case 0x2:
87e92502 1291 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1292 break;
1293 case 0x3:
87e92502 1294 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
19f329ad
BS		 1295 break;
1296 case 0x4:
87e92502 1297 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
19f329ad
BS		 1298 break;
1299 case 0x5:
87e92502 1300 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
19f329ad
BS		 1301 break;
1302 case 0x6:
87e92502 1303 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1304 break;
1305 case 0x7:
87e92502 1306 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
19f329ad
BS		 1307 break;
1308 case 0x8:
1309 gen_op_eval_ba(r_dst);
1310 break;
1311 case 0x9:
87e92502 1312 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
19f329ad
BS		 1313 break;
1314 case 0xa:
87e92502 1315 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
19f329ad
BS		 1316 break;
1317 case 0xb:
87e92502 1318 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1319 break;
1320 case 0xc:
87e92502 1321 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1322 break;
1323 case 0xd:
87e92502 1324 gen_op_eval_fble(r_dst, cpu_fsr, offset);
19f329ad
BS		 1325 break;
1326 case 0xe:
87e92502 1327 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
19f329ad
BS		 1328 break;
1329 case 0xf:
87e92502 1330 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
19f329ad
BS		 1331 break;
1332 }
e8af50a3 1333}
00f219bf 1334
19f329ad 1335#ifdef TARGET_SPARC64
00f219bf
BS		 1336// Inverted logic
1337static const int gen_tcg_cond_reg[8] = {
1338 -1,
1339 TCG_COND_NE,
1340 TCG_COND_GT,
1341 TCG_COND_GE,
1342 -1,
1343 TCG_COND_EQ,
1344 TCG_COND_LE,
1345 TCG_COND_LT,
1346};
19f329ad 1347
4af984a7 1348static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
19f329ad 1349{
19f329ad
BS		 1350 int l1;
1351
1352 l1 = gen_new_label();
0425bee5 1353 tcg_gen_movi_tl(r_dst, 0);
4af984a7 1354 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], r_src, tcg_const_tl(0), l1);
19f329ad
BS		 1355 tcg_gen_movi_tl(r_dst, 1);
1356 gen_set_label(l1);
1357}
3475187d 1358#endif
cf495bcf 1359
0bee699e 1360/* XXX: potentially incorrect if dynamic npc */
4af984a7
BS		 1361static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1362 TCGv r_cond)
7a3f1944 1363{
cf495bcf 1364 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 1365 target_ulong target = dc->pc + offset;
5fafdf24 1366
cf495bcf 1367 if (cond == 0x0) {
0f8a249a
BS		 1368 /* unconditional not taken */
1369 if (a) {
1370 dc->pc = dc->npc + 4;
1371 dc->npc = dc->pc + 4;
1372 } else {
1373 dc->pc = dc->npc;
1374 dc->npc = dc->pc + 4;
1375 }
cf495bcf 1376 } else if (cond == 0x8) {
0f8a249a
BS		 1377 /* unconditional taken */
1378 if (a) {
1379 dc->pc = target;
1380 dc->npc = dc->pc + 4;
1381 } else {
1382 dc->pc = dc->npc;
1383 dc->npc = target;
1384 }
cf495bcf 1385 } else {
4af984a7
BS		 1386 flush_cond(dc, r_cond);
1387 gen_cond(r_cond, cc, cond);
0f8a249a 1388 if (a) {
4af984a7 1389 gen_branch_a(dc, target, dc->npc, r_cond);
cf495bcf 1390 dc->is_br = 1;
0f8a249a 1391 } else {
cf495bcf 1392 dc->pc = dc->npc;
72cbca10
FB		 1393 dc->jump_pc[0] = target;
1394 dc->jump_pc[1] = dc->npc + 4;
1395 dc->npc = JUMP_PC;
0f8a249a 1396 }
cf495bcf 1397 }
7a3f1944
FB		 1398}
1399
0bee699e 1400/* XXX: potentially incorrect if dynamic npc */
4af984a7
BS		 1401static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1402 TCGv r_cond)
e8af50a3
FB		 1403{
1404 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 1405 target_ulong target = dc->pc + offset;
1406
e8af50a3 1407 if (cond == 0x0) {
0f8a249a
BS		 1408 /* unconditional not taken */
1409 if (a) {
1410 dc->pc = dc->npc + 4;
1411 dc->npc = dc->pc + 4;
1412 } else {
1413 dc->pc = dc->npc;
1414 dc->npc = dc->pc + 4;
1415 }
e8af50a3 1416 } else if (cond == 0x8) {
0f8a249a
BS		 1417 /* unconditional taken */
1418 if (a) {
1419 dc->pc = target;
1420 dc->npc = dc->pc + 4;
1421 } else {
1422 dc->pc = dc->npc;
1423 dc->npc = target;
1424 }
e8af50a3 1425 } else {
4af984a7
BS		 1426 flush_cond(dc, r_cond);
1427 gen_fcond(r_cond, cc, cond);
0f8a249a 1428 if (a) {
4af984a7 1429 gen_branch_a(dc, target, dc->npc, r_cond);
e8af50a3 1430 dc->is_br = 1;
0f8a249a 1431 } else {
e8af50a3
FB		 1432 dc->pc = dc->npc;
1433 dc->jump_pc[0] = target;
1434 dc->jump_pc[1] = dc->npc + 4;
1435 dc->npc = JUMP_PC;
0f8a249a 1436 }
e8af50a3
FB		 1437 }
1438}
1439
3475187d
FB		 1440#ifdef TARGET_SPARC64
1441/* XXX: potentially incorrect if dynamic npc */
4af984a7
BS		 1442static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1443 TCGv r_cond, TCGv r_reg)
7a3f1944 1444{
3475187d
FB		 1445 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1446 target_ulong target = dc->pc + offset;
1447
4af984a7
BS		 1448 flush_cond(dc, r_cond);
1449 gen_cond_reg(r_cond, cond, r_reg);
3475187d 1450 if (a) {
4af984a7 1451 gen_branch_a(dc, target, dc->npc, r_cond);
0f8a249a 1452 dc->is_br = 1;
3475187d 1453 } else {
0f8a249a
BS		 1454 dc->pc = dc->npc;
1455 dc->jump_pc[0] = target;
1456 dc->jump_pc[1] = dc->npc + 4;
1457 dc->npc = JUMP_PC;
3475187d 1458 }
7a3f1944
FB		 1459}
1460
3475187d 1461static GenOpFunc * const gen_fcmps[4] = {
7e8c2b6c
BS		 1462 helper_fcmps,
1463 helper_fcmps_fcc1,
1464 helper_fcmps_fcc2,
1465 helper_fcmps_fcc3,
3475187d
FB		 1466};
1467
1468static GenOpFunc * const gen_fcmpd[4] = {
7e8c2b6c
BS		 1469 helper_fcmpd,
1470 helper_fcmpd_fcc1,
1471 helper_fcmpd_fcc2,
1472 helper_fcmpd_fcc3,
3475187d 1473};
417454b0 1474
1f587329
BS		 1475#if defined(CONFIG_USER_ONLY)
1476static GenOpFunc * const gen_fcmpq[4] = {
7e8c2b6c
BS		 1477 helper_fcmpq,
1478 helper_fcmpq_fcc1,
1479 helper_fcmpq_fcc2,
1480 helper_fcmpq_fcc3,
1f587329
BS		 1481};
1482#endif
1483
417454b0 1484static GenOpFunc * const gen_fcmpes[4] = {
7e8c2b6c
BS		 1485 helper_fcmpes,
1486 helper_fcmpes_fcc1,
1487 helper_fcmpes_fcc2,
1488 helper_fcmpes_fcc3,
417454b0
BS		 1489};
1490
1491static GenOpFunc * const gen_fcmped[4] = {
7e8c2b6c
BS		 1492 helper_fcmped,
1493 helper_fcmped_fcc1,
1494 helper_fcmped_fcc2,
1495 helper_fcmped_fcc3,
417454b0
BS		 1496};
1497
1f587329
BS		 1498#if defined(CONFIG_USER_ONLY)
1499static GenOpFunc * const gen_fcmpeq[4] = {
7e8c2b6c
BS		 1500 helper_fcmpeq,
1501 helper_fcmpeq_fcc1,
1502 helper_fcmpeq_fcc2,
1503 helper_fcmpeq_fcc3,
1f587329
BS		 1504};
1505#endif
7e8c2b6c
BS		 1506
1507static inline void gen_op_fcmps(int fccno)
1508{
1509 tcg_gen_helper_0_0(gen_fcmps[fccno]);
1510}
1511
1512static inline void gen_op_fcmpd(int fccno)
1513{
1514 tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1515}
1516
1517#if defined(CONFIG_USER_ONLY)
1518static inline void gen_op_fcmpq(int fccno)
1519{
1520 tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1521}
1522#endif
1523
1524static inline void gen_op_fcmpes(int fccno)
1525{
1526 tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1527}
1528
1529static inline void gen_op_fcmped(int fccno)
1530{
1531 tcg_gen_helper_0_0(gen_fcmped[fccno]);
1532}
1533
1534#if defined(CONFIG_USER_ONLY)
1535static inline void gen_op_fcmpeq(int fccno)
1536{
1537 tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1538}
1539#endif
1540
1541#else
1542
1543static inline void gen_op_fcmps(int fccno)
1544{
1545 tcg_gen_helper_0_0(helper_fcmps);
1546}
1547
1548static inline void gen_op_fcmpd(int fccno)
1549{
1550 tcg_gen_helper_0_0(helper_fcmpd);
1551}
1552
1553#if defined(CONFIG_USER_ONLY)
1554static inline void gen_op_fcmpq(int fccno)
1555{
1556 tcg_gen_helper_0_0(helper_fcmpq);
1557}
1558#endif
1559
1560static inline void gen_op_fcmpes(int fccno)
1561{
1562 tcg_gen_helper_0_0(helper_fcmpes);
1563}
1564
1565static inline void gen_op_fcmped(int fccno)
1566{
1567 tcg_gen_helper_0_0(helper_fcmped);
1568}
1569
1570#if defined(CONFIG_USER_ONLY)
1571static inline void gen_op_fcmpeq(int fccno)
1572{
1573 tcg_gen_helper_0_0(helper_fcmpeq);
1574}
1575#endif
1576
3475187d
FB		 1577#endif
1578
134d77a1
BS		 1579static inline void gen_op_fpexception_im(int fsr_flags)
1580{
87e92502
BS		 1581 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1582 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
2f5680ee 1583 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_FP_EXCP));
134d77a1
BS		 1584}
1585
4af984a7 1586static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
a80dde08
FB		 1587{
1588#if !defined(CONFIG_USER_ONLY)
1589 if (!dc->fpu_enabled) {
4af984a7 1590 save_state(dc, r_cond);
2f5680ee 1591 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NFPU_INSN));
a80dde08
FB		 1592 dc->is_br = 1;
1593 return 1;
1594 }
1595#endif
1596 return 0;
1597}
1598
7e8c2b6c
BS		 1599static inline void gen_op_clear_ieee_excp_and_FTT(void)
1600{
87e92502 1601 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
7e8c2b6c
BS		 1602}
1603
1604static inline void gen_clear_float_exceptions(void)
1605{
1606 tcg_gen_helper_0_0(helper_clear_float_exceptions);
1607}
1608
1a2fb1c0
BS		 1609/* asi moves */
1610#ifdef TARGET_SPARC64
0425bee5 1611static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1a2fb1c0
BS		 1612{
1613 int asi, offset;
0425bee5 1614 TCGv r_asi;
1a2fb1c0 1615
1a2fb1c0 1616 if (IS_IMM) {
0425bee5 1617 r_asi = tcg_temp_new(TCG_TYPE_I32);
1a2fb1c0 1618 offset = GET_FIELD(insn, 25, 31);
0425bee5
BS		 1619 tcg_gen_addi_tl(r_addr, r_addr, offset);
1620 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1a2fb1c0
BS		 1621 } else {
1622 asi = GET_FIELD(insn, 19, 26);
0425bee5 1623 r_asi = tcg_const_i32(asi);
1a2fb1c0 1624 }
0425bee5
BS		 1625 return r_asi;
1626}
1627
4af984a7 1628static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
0425bee5
BS		 1629{
1630 TCGv r_asi;
1631
4af984a7
BS		 1632 r_asi = gen_get_asi(insn, addr);
1633 tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi,
0425bee5 1634 tcg_const_i32(size), tcg_const_i32(sign));
1a2fb1c0
BS		 1635}
1636
4af984a7 1637static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1a2fb1c0 1638{
0425bee5 1639 TCGv r_asi;
1a2fb1c0 1640
4af984a7
BS		 1641 r_asi = gen_get_asi(insn, addr);
1642 tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, tcg_const_i32(size));
1a2fb1c0
BS		 1643}
1644
4af984a7 1645static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1a2fb1c0 1646{
0425bee5 1647 TCGv r_asi;
1a2fb1c0 1648
4af984a7
BS		 1649 r_asi = gen_get_asi(insn, addr);
1650 tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, tcg_const_i32(size),
0425bee5 1651 tcg_const_i32(rd));
1a2fb1c0
BS		 1652}
1653
4af984a7 1654static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1a2fb1c0 1655{
0425bee5 1656 TCGv r_asi;
1a2fb1c0 1657
31741a27
BS		 1658 r_asi = gen_get_asi(insn, addr);
1659 tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, tcg_const_i32(size),
0425bee5 1660 tcg_const_i32(rd));
1a2fb1c0
BS		 1661}
1662
4af984a7 1663static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1a2fb1c0 1664{
0425bee5 1665 TCGv r_temp, r_asi;
1a2fb1c0 1666
1a2fb1c0 1667 r_temp = tcg_temp_new(TCG_TYPE_I32);
4af984a7
BS		 1668 r_asi = gen_get_asi(insn, addr);
1669 tcg_gen_helper_1_4(helper_ld_asi, r_temp, addr, r_asi,
0425bee5 1670 tcg_const_i32(4), tcg_const_i32(0));
4af984a7 1671 tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi,
0425bee5 1672 tcg_const_i32(4));
4af984a7 1673 tcg_gen_extu_i32_tl(dst, r_temp);
1a2fb1c0
BS		 1674}
1675
4af984a7 1676static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1a2fb1c0 1677{
8911f501 1678 TCGv r_asi;
1a2fb1c0 1679
4af984a7
BS		 1680 r_asi = gen_get_asi(insn, addr);
1681 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi,
0425bee5 1682 tcg_const_i32(8), tcg_const_i32(0));
4af984a7 1683 tcg_gen_andi_i64(lo, cpu_tmp64, 0xffffffffULL);
8911f501 1684 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4af984a7 1685 tcg_gen_andi_i64(hi, cpu_tmp64, 0xffffffffULL);
0425bee5
BS		 1686}
1687
4af984a7 1688static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
0425bee5 1689{
8911f501 1690 TCGv r_temp, r_asi;
0425bee5 1691
0425bee5
BS		 1692 r_temp = tcg_temp_new(TCG_TYPE_I32);
1693 gen_movl_reg_TN(rd + 1, r_temp);
4af984a7 1694 tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
0425bee5 1695 r_temp);
4af984a7
BS		 1696 r_asi = gen_get_asi(insn, addr);
1697 tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi,
0425bee5 1698 tcg_const_i32(8));
1a2fb1c0
BS		 1699}
1700
4af984a7 1701static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
1a2fb1c0 1702{
1a2fb1c0
BS		 1703 TCGv r_val1, r_asi;
1704
1705 r_val1 = tcg_temp_new(TCG_TYPE_I32);
1a2fb1c0 1706 gen_movl_reg_TN(rd, r_val1);
4af984a7
BS		 1707 r_asi = gen_get_asi(insn, addr);
1708 tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1a2fb1c0
BS		 1709}
1710
4af984a7 1711static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
1a2fb1c0 1712{
8911f501 1713 TCGv r_asi;
1a2fb1c0 1714
8911f501 1715 gen_movl_reg_TN(rd, cpu_tmp64);
4af984a7
BS		 1716 r_asi = gen_get_asi(insn, addr);
1717 tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1a2fb1c0
BS		 1718}
1719
1720#elif !defined(CONFIG_USER_ONLY)
1721
4af984a7 1722static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
1a2fb1c0
BS		 1723{
1724 int asi;
1a2fb1c0 1725
1a2fb1c0 1726 asi = GET_FIELD(insn, 19, 26);
4af984a7 1727 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi),
0425bee5 1728 tcg_const_i32(size), tcg_const_i32(sign));
4af984a7 1729 tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1a2fb1c0
BS		 1730}
1731
4af984a7 1732static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1a2fb1c0
BS		 1733{
1734 int asi;
1a2fb1c0 1735
4af984a7 1736 tcg_gen_extu_tl_i64(cpu_tmp64, src);
1a2fb1c0 1737 asi = GET_FIELD(insn, 19, 26);
4af984a7 1738 tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi),
0425bee5 1739 tcg_const_i32(size));
1a2fb1c0
BS		 1740}
1741
4af984a7 1742static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1a2fb1c0
BS		 1743{
1744 int asi;
0425bee5 1745 TCGv r_temp;
1a2fb1c0 1746
1a2fb1c0 1747 r_temp = tcg_temp_new(TCG_TYPE_I32);
1a2fb1c0 1748 asi = GET_FIELD(insn, 19, 26);
4af984a7 1749 tcg_gen_helper_1_4(helper_ld_asi, r_temp, addr, tcg_const_i32(asi),
0425bee5 1750 tcg_const_i32(4), tcg_const_i32(0));
4af984a7 1751 tcg_gen_helper_0_4(helper_st_asi, addr, dst, tcg_const_i32(asi),
0425bee5 1752 tcg_const_i32(4));
4af984a7 1753 tcg_gen_extu_i32_tl(dst, r_temp);
1a2fb1c0
BS		 1754}
1755
4af984a7 1756static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1a2fb1c0
BS		 1757{
1758 int asi;
1a2fb1c0 1759
1a2fb1c0 1760 asi = GET_FIELD(insn, 19, 26);
4af984a7 1761 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi),
0425bee5 1762 tcg_const_i32(8), tcg_const_i32(0));
4af984a7 1763 tcg_gen_trunc_i64_tl(lo, cpu_tmp64);
8911f501 1764 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4af984a7 1765 tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
0425bee5
BS		 1766}
1767
4af984a7 1768static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
0425bee5
BS		 1769{
1770 int asi;
8911f501 1771 TCGv r_temp;
0425bee5 1772
0425bee5
BS		 1773 r_temp = tcg_temp_new(TCG_TYPE_I32);
1774 gen_movl_reg_TN(rd + 1, r_temp);
4af984a7 1775 tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
0425bee5 1776 asi = GET_FIELD(insn, 19, 26);
4af984a7 1777 tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi),
0425bee5 1778 tcg_const_i32(8));
1a2fb1c0
BS		 1779}
1780#endif
1781
1782#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4af984a7 1783static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1a2fb1c0
BS		 1784{
1785 int asi;
1a2fb1c0 1786
4af984a7 1787 gen_ld_asi(dst, addr, insn, 1, 0);
1a2fb1c0 1788
1a2fb1c0 1789 asi = GET_FIELD(insn, 19, 26);
4af984a7 1790 tcg_gen_helper_0_4(helper_st_asi, addr, tcg_const_i64(0xffULL),
0425bee5 1791 tcg_const_i32(asi), tcg_const_i32(1));
1a2fb1c0
BS		 1792}
1793#endif
1794
9322a4bf
BS		 1795static inline TCGv get_src1(unsigned int insn, TCGv def)
1796{
1797 TCGv r_rs1 = def;
1798 unsigned int rs1;
1799
1800 rs1 = GET_FIELD(insn, 13, 17);
1801 if (rs1 == 0)
1802 //r_rs1 = tcg_const_tl(0);
1803 tcg_gen_movi_tl(def, 0);
1804 else if (rs1 < 8)
1805 //r_rs1 = cpu_gregs[rs1];
1806 tcg_gen_mov_tl(def, cpu_gregs[rs1]);
1807 else
1808 tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1809 return r_rs1;
1810}
1811
a49d9390
BS		 1812static inline TCGv get_src2(unsigned int insn, TCGv def)
1813{
1814 TCGv r_rs2 = def;
1815 unsigned int rs2;
1816
1817 if (IS_IMM) { /* immediate */
1818 rs2 = GET_FIELDs(insn, 19, 31);
1819 r_rs2 = tcg_const_tl((int)rs2);
1820 } else { /* register */
1821 rs2 = GET_FIELD(insn, 27, 31);
1822 if (rs2 == 0)
1823 r_rs2 = tcg_const_tl(0);
1824 else if (rs2 < 8)
1825 r_rs2 = cpu_gregs[rs2];
1826 else
1827 tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1828 }
1829 return r_rs2;
1830}
1831
0bee699e 1832/* before an instruction, dc->pc must be static */
cf495bcf
FB		 1833static void disas_sparc_insn(DisasContext * dc)
1834{
1835 unsigned int insn, opc, rs1, rs2, rd;
7a3f1944 1836
0fa85d43 1837 insn = ldl_code(dc->pc);
cf495bcf 1838 opc = GET_FIELD(insn, 0, 1);
7a3f1944 1839
cf495bcf 1840 rd = GET_FIELD(insn, 2, 6);
6ae20372
BS		 1841
1842 cpu_dst = cpu_T[0];
1843 cpu_src1 = cpu_T[0]; // const
1844 cpu_src2 = cpu_T[1]; // const
1845
1846 // loads and stores
1847 cpu_addr = cpu_T[0];
1848 cpu_val = cpu_T[1];
1849
cf495bcf 1850 switch (opc) {
0f8a249a
BS		 1851 case 0: /* branches/sethi */
1852 {
1853 unsigned int xop = GET_FIELD(insn, 7, 9);
1854 int32_t target;
1855 switch (xop) {
3475187d 1856#ifdef TARGET_SPARC64
0f8a249a
BS		 1857 case 0x1: /* V9 BPcc */
1858 {
1859 int cc;
1860
1861 target = GET_FIELD_SP(insn, 0, 18);
1862 target = sign_extend(target, 18);
1863 target <<= 2;
1864 cc = GET_FIELD_SP(insn, 20, 21);
1865 if (cc == 0)
6ae20372 1866 do_branch(dc, target, insn, 0, cpu_cond);
0f8a249a 1867 else if (cc == 2)
6ae20372 1868 do_branch(dc, target, insn, 1, cpu_cond);
0f8a249a
BS		 1869 else
1870 goto illegal_insn;
1871 goto jmp_insn;
1872 }
1873 case 0x3: /* V9 BPr */
1874 {
1875 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 1876 (GET_FIELD_SP(insn, 20, 21) << 14);
0f8a249a
BS		 1877 target = sign_extend(target, 16);
1878 target <<= 2;
9322a4bf 1879 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372 1880 do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
0f8a249a
BS		 1881 goto jmp_insn;
1882 }
1883 case 0x5: /* V9 FBPcc */
1884 {
1885 int cc = GET_FIELD_SP(insn, 20, 21);
6ae20372 1886 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 1887 goto jmp_insn;
0f8a249a
BS		 1888 target = GET_FIELD_SP(insn, 0, 18);
1889 target = sign_extend(target, 19);
1890 target <<= 2;
6ae20372 1891 do_fbranch(dc, target, insn, cc, cpu_cond);
0f8a249a
BS		 1892 goto jmp_insn;
1893 }
a4d17f19 1894#else
0f8a249a
BS		 1895 case 0x7: /* CBN+x */
1896 {
1897 goto ncp_insn;
1898 }
1899#endif
1900 case 0x2: /* BN+x */
1901 {
1902 target = GET_FIELD(insn, 10, 31);
1903 target = sign_extend(target, 22);
1904 target <<= 2;
6ae20372 1905 do_branch(dc, target, insn, 0, cpu_cond);
0f8a249a
BS		 1906 goto jmp_insn;
1907 }
1908 case 0x6: /* FBN+x */
1909 {
6ae20372 1910 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 1911 goto jmp_insn;
0f8a249a
BS		 1912 target = GET_FIELD(insn, 10, 31);
1913 target = sign_extend(target, 22);
1914 target <<= 2;
6ae20372 1915 do_fbranch(dc, target, insn, 0, cpu_cond);
0f8a249a
BS		 1916 goto jmp_insn;
1917 }
1918 case 0x4: /* SETHI */
0f8a249a 1919 if (rd) { // nop
0f8a249a 1920 uint32_t value = GET_FIELD(insn, 10, 31);
6ae20372
BS		 1921 tcg_gen_movi_tl(cpu_dst, value << 10);
1922 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a 1923 }
0f8a249a
BS		 1924 break;
1925 case 0x0: /* UNIMPL */
1926 default:
3475187d 1927 goto illegal_insn;
0f8a249a
BS		 1928 }
1929 break;
1930 }
1931 break;
cf495bcf 1932 case 1:
0f8a249a
BS		 1933 /*CALL*/ {
1934 target_long target = GET_FIELDs(insn, 2, 31) << 2;
cf495bcf 1935
48d5c82b 1936 gen_movl_TN_reg(15, tcg_const_tl(dc->pc));
0f8a249a 1937 target += dc->pc;
6ae20372 1938 gen_mov_pc_npc(dc, cpu_cond);
0f8a249a
BS		 1939 dc->npc = target;
1940 }
1941 goto jmp_insn;
1942 case 2: /* FPU & Logical Operations */
1943 {
1944 unsigned int xop = GET_FIELD(insn, 7, 12);
1945 if (xop == 0x3a) { /* generate trap */
cf495bcf 1946 int cond;
3475187d 1947
9322a4bf 1948 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a
BS		 1949 if (IS_IMM) {
1950 rs2 = GET_FIELD(insn, 25, 31);
6ae20372 1951 tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
cf495bcf
FB		 1952 } else {
1953 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 1954 if (rs2 != 0) {
6ae20372
BS		 1955 gen_movl_reg_TN(rs2, cpu_src2);
1956 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
6f551262
BS		 1957 } else
1958 tcg_gen_mov_tl(cpu_dst, cpu_src1);
cf495bcf 1959 }
cf495bcf
FB		 1960 cond = GET_FIELD(insn, 3, 6);
1961 if (cond == 0x8) {
6ae20372
BS		 1962 save_state(dc, cpu_cond);
1963 tcg_gen_helper_0_1(helper_trap, cpu_dst);
af7bf89b 1964 } else if (cond != 0) {
748b9d8e 1965 TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
3475187d 1966#ifdef TARGET_SPARC64
0f8a249a
BS		 1967 /* V9 icc/xcc */
1968 int cc = GET_FIELD_SP(insn, 11, 12);
748b9d8e 1969
6ae20372 1970 save_state(dc, cpu_cond);
0f8a249a 1971 if (cc == 0)
748b9d8e 1972 gen_cond(r_cond, 0, cond);
0f8a249a 1973 else if (cc == 2)
748b9d8e 1974 gen_cond(r_cond, 1, cond);
0f8a249a
BS		 1975 else
1976 goto illegal_insn;
3475187d 1977#else
6ae20372 1978 save_state(dc, cpu_cond);
748b9d8e 1979 gen_cond(r_cond, 0, cond);
3475187d 1980#endif
6ae20372 1981 tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
cf495bcf 1982 }
a80dde08 1983 gen_op_next_insn();
57fec1fe 1984 tcg_gen_exit_tb(0);
a80dde08
FB		 1985 dc->is_br = 1;
1986 goto jmp_insn;
cf495bcf
FB		 1987 } else if (xop == 0x28) {
1988 rs1 = GET_FIELD(insn, 13, 17);
1989 switch(rs1) {
1990 case 0: /* rdy */
65fe7b09
BS		 1991#ifndef TARGET_SPARC64
1992 case 0x01 ... 0x0e: /* undefined in the SPARCv8
1993 manual, rdy on the microSPARC
1994 II */
1995 case 0x0f: /* stbar in the SPARCv8 manual,
1996 rdy on the microSPARC II */
1997 case 0x10 ... 0x1f: /* implementation-dependent in the
1998 SPARCv8 manual, rdy on the
1999 microSPARC II */
2000#endif
6ae20372
BS		 2001 tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, y));
2002 gen_movl_TN_reg(rd, cpu_dst);
cf495bcf 2003 break;
3475187d 2004#ifdef TARGET_SPARC64
0f8a249a 2005 case 0x2: /* V9 rdccr */
6ae20372
BS		 2006 tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2007 gen_movl_TN_reg(rd, cpu_dst);
3475187d 2008 break;
0f8a249a 2009 case 0x3: /* V9 rdasi */
2f5680ee 2010 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
6ae20372
BS		 2011 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2012 gen_movl_TN_reg(rd, cpu_dst);
3475187d 2013 break;
0f8a249a 2014 case 0x4: /* V9 rdtick */
ccd4a219
BS		 2015 {
2016 TCGv r_tickptr;
2017
2018 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2019 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2020 offsetof(CPUState, tick));
6ae20372 2021 tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
ccd4a219 2022 r_tickptr);
6ae20372 2023 gen_movl_TN_reg(rd, cpu_dst);
ccd4a219 2024 }
3475187d 2025 break;
0f8a249a 2026 case 0x5: /* V9 rdpc */
6ae20372
BS		 2027 tcg_gen_movi_tl(cpu_dst, dc->pc);
2028 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 2029 break;
2030 case 0x6: /* V9 rdfprs */
2f5680ee 2031 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
6ae20372
BS		 2032 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2033 gen_movl_TN_reg(rd, cpu_dst);
3475187d 2034 break;
65fe7b09
BS		 2035 case 0xf: /* V9 membar */
2036 break; /* no effect */
0f8a249a 2037 case 0x13: /* Graphics Status */
6ae20372 2038 if (gen_trap_ifnofpu(dc, cpu_cond))
725cb90b 2039 goto jmp_insn;
6ae20372
BS		 2040 tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, gsr));
2041 gen_movl_TN_reg(rd, cpu_dst);
725cb90b 2042 break;
0f8a249a 2043 case 0x17: /* Tick compare */
6ae20372
BS		 2044 tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tick_cmpr));
2045 gen_movl_TN_reg(rd, cpu_dst);
83469015 2046 break;
0f8a249a 2047 case 0x18: /* System tick */
ccd4a219
BS		 2048 {
2049 TCGv r_tickptr;
2050
2051 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2052 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2053 offsetof(CPUState, stick));
6ae20372 2054 tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
ccd4a219 2055 r_tickptr);
6ae20372 2056 gen_movl_TN_reg(rd, cpu_dst);
ccd4a219 2057 }
83469015 2058 break;
0f8a249a 2059 case 0x19: /* System tick compare */
6ae20372
BS		 2060 tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, stick_cmpr));
2061 gen_movl_TN_reg(rd, cpu_dst);
83469015 2062 break;
0f8a249a
BS		 2063 case 0x10: /* Performance Control */
2064 case 0x11: /* Performance Instrumentation Counter */
2065 case 0x12: /* Dispatch Control */
2066 case 0x14: /* Softint set, WO */
2067 case 0x15: /* Softint clear, WO */
2068 case 0x16: /* Softint write */
3475187d
FB		 2069#endif
2070 default:
cf495bcf
FB		 2071 goto illegal_insn;
2072 }
e8af50a3 2073#if !defined(CONFIG_USER_ONLY)
e9ebed4d 2074 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 2075#ifndef TARGET_SPARC64
0f8a249a
BS		 2076 if (!supervisor(dc))
2077 goto priv_insn;
6ae20372 2078 tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
e9ebed4d
BS		 2079#else
2080 if (!hypervisor(dc))
2081 goto priv_insn;
2082 rs1 = GET_FIELD(insn, 13, 17);
2083 switch (rs1) {
2084 case 0: // hpstate
2085 // gen_op_rdhpstate();
2086 break;
2087 case 1: // htstate
2088 // gen_op_rdhtstate();
2089 break;
2090 case 3: // hintp
2f5680ee 2091 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
6ae20372 2092 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
e9ebed4d
BS		 2093 break;
2094 case 5: // htba
2f5680ee 2095 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
6ae20372 2096 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
e9ebed4d
BS		 2097 break;
2098 case 6: // hver
2f5680ee 2099 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hver));
6ae20372 2100 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
e9ebed4d
BS		 2101 break;
2102 case 31: // hstick_cmpr
6ae20372 2103 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 2104 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hstick_cmpr));
e9ebed4d
BS		 2105 break;
2106 default:
2107 goto illegal_insn;
2108 }
2109#endif
6ae20372 2110 gen_movl_TN_reg(rd, cpu_dst);
e8af50a3 2111 break;
3475187d 2112 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
0f8a249a
BS		 2113 if (!supervisor(dc))
2114 goto priv_insn;
3475187d
FB		 2115#ifdef TARGET_SPARC64
2116 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2117 switch (rs1) {
2118 case 0: // tpc
375ee38b
BS		 2119 {
2120 TCGv r_tsptr;
2121
2122 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2123 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2124 offsetof(CPUState, tsptr));
6ae20372 2125 tcg_gen_ld_tl(cpu_dst, r_tsptr,
375ee38b
BS		 2126 offsetof(trap_state, tpc));
2127 }
0f8a249a
BS		 2128 break;
2129 case 1: // tnpc
375ee38b
BS		 2130 {
2131 TCGv r_tsptr;
2132
2133 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2134 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2135 offsetof(CPUState, tsptr));
6ae20372 2136 tcg_gen_ld_tl(cpu_dst, r_tsptr,
375ee38b
BS		 2137 offsetof(trap_state, tnpc));
2138 }
0f8a249a
BS		 2139 break;
2140 case 2: // tstate
375ee38b
BS		 2141 {
2142 TCGv r_tsptr;
2143
2144 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2145 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2146 offsetof(CPUState, tsptr));
6ae20372 2147 tcg_gen_ld_tl(cpu_dst, r_tsptr,
375ee38b
BS		 2148 offsetof(trap_state, tstate));
2149 }
0f8a249a
BS		 2150 break;
2151 case 3: // tt
375ee38b
BS		 2152 {
2153 TCGv r_tsptr;
2154
2155 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2156 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2157 offsetof(CPUState, tsptr));
6ae20372 2158 tcg_gen_ld_i32(cpu_dst, r_tsptr,
375ee38b
BS		 2159 offsetof(trap_state, tt));
2160 }
0f8a249a
BS		 2161 break;
2162 case 4: // tick
ccd4a219
BS		 2163 {
2164 TCGv r_tickptr;
2165
2166 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2167 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2168 offsetof(CPUState, tick));
6ae20372 2169 tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
ccd4a219 2170 r_tickptr);
6ae20372 2171 gen_movl_TN_reg(rd, cpu_dst);
ccd4a219 2172 }
0f8a249a
BS		 2173 break;
2174 case 5: // tba
6ae20372 2175 tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
0f8a249a
BS		 2176 break;
2177 case 6: // pstate
2f5680ee 2178 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, pstate));
6ae20372 2179 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
0f8a249a
BS		 2180 break;
2181 case 7: // tl
2f5680ee 2182 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
6ae20372 2183 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
0f8a249a
BS		 2184 break;
2185 case 8: // pil
2f5680ee 2186 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
6ae20372 2187 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
0f8a249a
BS		 2188 break;
2189 case 9: // cwp
6ae20372 2190 tcg_gen_helper_1_0(helper_rdcwp, cpu_dst);
0f8a249a
BS		 2191 break;
2192 case 10: // cansave
2f5680ee 2193 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
6ae20372 2194 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
0f8a249a
BS		 2195 break;
2196 case 11: // canrestore
2f5680ee 2197 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
6ae20372 2198 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
0f8a249a
BS		 2199 break;
2200 case 12: // cleanwin
2f5680ee 2201 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
6ae20372 2202 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
0f8a249a
BS		 2203 break;
2204 case 13: // otherwin
2f5680ee 2205 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
6ae20372 2206 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
0f8a249a
BS		 2207 break;
2208 case 14: // wstate
2f5680ee 2209 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
6ae20372 2210 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
0f8a249a 2211 break;
e9ebed4d 2212 case 16: // UA2005 gl
2f5680ee 2213 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
6ae20372 2214 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
e9ebed4d
BS		 2215 break;
2216 case 26: // UA2005 strand status
2217 if (!hypervisor(dc))
2218 goto priv_insn;
2f5680ee 2219 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
6ae20372 2220 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
e9ebed4d 2221 break;
0f8a249a 2222 case 31: // ver
6ae20372 2223 tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, version));
0f8a249a
BS		 2224 break;
2225 case 15: // fq
2226 default:
2227 goto illegal_insn;
2228 }
3475187d 2229#else
2f5680ee 2230 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
6ae20372 2231 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
3475187d 2232#endif
6ae20372 2233 gen_movl_TN_reg(rd, cpu_dst);
e8af50a3 2234 break;
3475187d
FB		 2235 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2236#ifdef TARGET_SPARC64
72a9747b 2237 tcg_gen_helper_0_0(helper_flushw);
3475187d 2238#else
0f8a249a
BS		 2239 if (!supervisor(dc))
2240 goto priv_insn;
6ae20372
BS		 2241 tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
2242 gen_movl_TN_reg(rd, cpu_dst);
3475187d 2243#endif
e8af50a3
FB		 2244 break;
2245#endif
0f8a249a 2246 } else if (xop == 0x34) { /* FPU Operations */
6ae20372 2247 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 2248 goto jmp_insn;
0f8a249a 2249 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 2250 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2251 rs2 = GET_FIELD(insn, 27, 31);
2252 xop = GET_FIELD(insn, 18, 26);
2253 switch (xop) {
2254 case 0x1: /* fmovs */
2255 gen_op_load_fpr_FT0(rs2);
2256 gen_op_store_FT0_fpr(rd);
2257 break;
2258 case 0x5: /* fnegs */
2259 gen_op_load_fpr_FT1(rs2);
44e7757c 2260 tcg_gen_helper_0_0(helper_fnegs);
0f8a249a
BS		 2261 gen_op_store_FT0_fpr(rd);
2262 break;
2263 case 0x9: /* fabss */
2264 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2265 tcg_gen_helper_0_0(helper_fabss);
0f8a249a
BS		 2266 gen_op_store_FT0_fpr(rd);
2267 break;
2268 case 0x29: /* fsqrts */
2269 gen_op_load_fpr_FT1(rs2);
7e8c2b6c
BS		 2270 gen_clear_float_exceptions();
2271 tcg_gen_helper_0_0(helper_fsqrts);
2272 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2273 gen_op_store_FT0_fpr(rd);
2274 break;
2275 case 0x2a: /* fsqrtd */
2276 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c
BS		 2277 gen_clear_float_exceptions();
2278 tcg_gen_helper_0_0(helper_fsqrtd);
2279 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2280 gen_op_store_DT0_fpr(DFPREG(rd));
2281 break;
2282 case 0x2b: /* fsqrtq */
1f587329
BS		 2283#if defined(CONFIG_USER_ONLY)
2284 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c
BS		 2285 gen_clear_float_exceptions();
2286 tcg_gen_helper_0_0(helper_fsqrtq);
2287 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2288 gen_op_store_QT0_fpr(QFPREG(rd));
2289 break;
2290#else
0f8a249a 2291 goto nfpu_insn;
1f587329 2292#endif
0f8a249a
BS		 2293 case 0x41:
2294 gen_op_load_fpr_FT0(rs1);
2295 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2296 gen_clear_float_exceptions();
44e7757c 2297 tcg_gen_helper_0_0(helper_fadds);
7e8c2b6c 2298 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2299 gen_op_store_FT0_fpr(rd);
2300 break;
2301 case 0x42:
2302 gen_op_load_fpr_DT0(DFPREG(rs1));
2303 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2304 gen_clear_float_exceptions();
44e7757c 2305 tcg_gen_helper_0_0(helper_faddd);
7e8c2b6c 2306 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2307 gen_op_store_DT0_fpr(DFPREG(rd));
2308 break;
2309 case 0x43: /* faddq */
1f587329
BS		 2310#if defined(CONFIG_USER_ONLY)
2311 gen_op_load_fpr_QT0(QFPREG(rs1));
2312 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2313 gen_clear_float_exceptions();
44e7757c 2314 tcg_gen_helper_0_0(helper_faddq);
7e8c2b6c 2315 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2316 gen_op_store_QT0_fpr(QFPREG(rd));
2317 break;
2318#else
0f8a249a 2319 goto nfpu_insn;
1f587329 2320#endif
0f8a249a
BS		 2321 case 0x45:
2322 gen_op_load_fpr_FT0(rs1);
2323 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2324 gen_clear_float_exceptions();
44e7757c 2325 tcg_gen_helper_0_0(helper_fsubs);
7e8c2b6c 2326 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2327 gen_op_store_FT0_fpr(rd);
2328 break;
2329 case 0x46:
2330 gen_op_load_fpr_DT0(DFPREG(rs1));
2331 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2332 gen_clear_float_exceptions();
44e7757c 2333 tcg_gen_helper_0_0(helper_fsubd);
7e8c2b6c 2334 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2335 gen_op_store_DT0_fpr(DFPREG(rd));
2336 break;
2337 case 0x47: /* fsubq */
1f587329
BS		 2338#if defined(CONFIG_USER_ONLY)
2339 gen_op_load_fpr_QT0(QFPREG(rs1));
2340 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2341 gen_clear_float_exceptions();
44e7757c 2342 tcg_gen_helper_0_0(helper_fsubq);
7e8c2b6c 2343 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2344 gen_op_store_QT0_fpr(QFPREG(rd));
2345 break;
2346#else
0f8a249a 2347 goto nfpu_insn;
1f587329 2348#endif
0f8a249a
BS		 2349 case 0x49:
2350 gen_op_load_fpr_FT0(rs1);
2351 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2352 gen_clear_float_exceptions();
44e7757c 2353 tcg_gen_helper_0_0(helper_fmuls);
7e8c2b6c 2354 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2355 gen_op_store_FT0_fpr(rd);
2356 break;
2357 case 0x4a:
2358 gen_op_load_fpr_DT0(DFPREG(rs1));
2359 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2360 gen_clear_float_exceptions();
44e7757c 2361 tcg_gen_helper_0_0(helper_fmuld);
7e8c2b6c 2362 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2382dc6b 2363 gen_op_store_DT0_fpr(DFPREG(rd));
0f8a249a
BS		 2364 break;
2365 case 0x4b: /* fmulq */
1f587329
BS		 2366#if defined(CONFIG_USER_ONLY)
2367 gen_op_load_fpr_QT0(QFPREG(rs1));
2368 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2369 gen_clear_float_exceptions();
44e7757c 2370 tcg_gen_helper_0_0(helper_fmulq);
7e8c2b6c 2371 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2372 gen_op_store_QT0_fpr(QFPREG(rd));
2373 break;
2374#else
0f8a249a 2375 goto nfpu_insn;
1f587329 2376#endif
0f8a249a
BS		 2377 case 0x4d:
2378 gen_op_load_fpr_FT0(rs1);
2379 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2380 gen_clear_float_exceptions();
44e7757c 2381 tcg_gen_helper_0_0(helper_fdivs);
7e8c2b6c 2382 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2383 gen_op_store_FT0_fpr(rd);
2384 break;
2385 case 0x4e:
2386 gen_op_load_fpr_DT0(DFPREG(rs1));
2387 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2388 gen_clear_float_exceptions();
44e7757c 2389 tcg_gen_helper_0_0(helper_fdivd);
7e8c2b6c 2390 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2391 gen_op_store_DT0_fpr(DFPREG(rd));
2392 break;
2393 case 0x4f: /* fdivq */
1f587329
BS		 2394#if defined(CONFIG_USER_ONLY)
2395 gen_op_load_fpr_QT0(QFPREG(rs1));
2396 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2397 gen_clear_float_exceptions();
44e7757c 2398 tcg_gen_helper_0_0(helper_fdivq);
7e8c2b6c 2399 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2400 gen_op_store_QT0_fpr(QFPREG(rd));
2401 break;
2402#else
0f8a249a 2403 goto nfpu_insn;
1f587329 2404#endif
0f8a249a
BS		 2405 case 0x69:
2406 gen_op_load_fpr_FT0(rs1);
2407 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2408 gen_clear_float_exceptions();
44e7757c 2409 tcg_gen_helper_0_0(helper_fsmuld);
7e8c2b6c 2410 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2411 gen_op_store_DT0_fpr(DFPREG(rd));
2412 break;
2413 case 0x6e: /* fdmulq */
1f587329
BS		 2414#if defined(CONFIG_USER_ONLY)
2415 gen_op_load_fpr_DT0(DFPREG(rs1));
2416 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2417 gen_clear_float_exceptions();
44e7757c 2418 tcg_gen_helper_0_0(helper_fdmulq);
7e8c2b6c 2419 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2420 gen_op_store_QT0_fpr(QFPREG(rd));
2421 break;
2422#else
0f8a249a 2423 goto nfpu_insn;
1f587329 2424#endif
0f8a249a
BS		 2425 case 0xc4:
2426 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2427 gen_clear_float_exceptions();
44e7757c 2428 tcg_gen_helper_0_0(helper_fitos);
7e8c2b6c 2429 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2430 gen_op_store_FT0_fpr(rd);
2431 break;
2432 case 0xc6:
2433 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2434 gen_clear_float_exceptions();
44e7757c 2435 tcg_gen_helper_0_0(helper_fdtos);
7e8c2b6c 2436 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2437 gen_op_store_FT0_fpr(rd);
2438 break;
2439 case 0xc7: /* fqtos */
1f587329
BS		 2440#if defined(CONFIG_USER_ONLY)
2441 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2442 gen_clear_float_exceptions();
44e7757c 2443 tcg_gen_helper_0_0(helper_fqtos);
7e8c2b6c 2444 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2445 gen_op_store_FT0_fpr(rd);
2446 break;
2447#else
0f8a249a 2448 goto nfpu_insn;
1f587329 2449#endif
0f8a249a
BS		 2450 case 0xc8:
2451 gen_op_load_fpr_FT1(rs2);
44e7757c 2452 tcg_gen_helper_0_0(helper_fitod);
0f8a249a
BS		 2453 gen_op_store_DT0_fpr(DFPREG(rd));
2454 break;
2455 case 0xc9:
2456 gen_op_load_fpr_FT1(rs2);
44e7757c 2457 tcg_gen_helper_0_0(helper_fstod);
0f8a249a
BS		 2458 gen_op_store_DT0_fpr(DFPREG(rd));
2459 break;
2460 case 0xcb: /* fqtod */
1f587329
BS		 2461#if defined(CONFIG_USER_ONLY)
2462 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2463 gen_clear_float_exceptions();
44e7757c 2464 tcg_gen_helper_0_0(helper_fqtod);
7e8c2b6c 2465 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2466 gen_op_store_DT0_fpr(DFPREG(rd));
2467 break;
2468#else
0f8a249a 2469 goto nfpu_insn;
1f587329 2470#endif
0f8a249a 2471 case 0xcc: /* fitoq */
1f587329
BS		 2472#if defined(CONFIG_USER_ONLY)
2473 gen_op_load_fpr_FT1(rs2);
44e7757c 2474 tcg_gen_helper_0_0(helper_fitoq);
1f587329
BS		 2475 gen_op_store_QT0_fpr(QFPREG(rd));
2476 break;
2477#else
0f8a249a 2478 goto nfpu_insn;
1f587329 2479#endif
0f8a249a 2480 case 0xcd: /* fstoq */
1f587329
BS		 2481#if defined(CONFIG_USER_ONLY)
2482 gen_op_load_fpr_FT1(rs2);
44e7757c 2483 tcg_gen_helper_0_0(helper_fstoq);
1f587329
BS		 2484 gen_op_store_QT0_fpr(QFPREG(rd));
2485 break;
2486#else
0f8a249a 2487 goto nfpu_insn;
1f587329 2488#endif
0f8a249a 2489 case 0xce: /* fdtoq */
1f587329
BS		 2490#if defined(CONFIG_USER_ONLY)
2491 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 2492 tcg_gen_helper_0_0(helper_fdtoq);
1f587329
BS		 2493 gen_op_store_QT0_fpr(QFPREG(rd));
2494 break;
2495#else
0f8a249a 2496 goto nfpu_insn;
1f587329 2497#endif
0f8a249a
BS		 2498 case 0xd1:
2499 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2500 gen_clear_float_exceptions();
44e7757c 2501 tcg_gen_helper_0_0(helper_fstoi);
7e8c2b6c 2502 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2503 gen_op_store_FT0_fpr(rd);
2504 break;
2505 case 0xd2:
2382dc6b 2506 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2507 gen_clear_float_exceptions();
44e7757c 2508 tcg_gen_helper_0_0(helper_fdtoi);
7e8c2b6c 2509 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2510 gen_op_store_FT0_fpr(rd);
2511 break;
2512 case 0xd3: /* fqtoi */
1f587329
BS		 2513#if defined(CONFIG_USER_ONLY)
2514 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2515 gen_clear_float_exceptions();
44e7757c 2516 tcg_gen_helper_0_0(helper_fqtoi);
7e8c2b6c 2517 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2518 gen_op_store_FT0_fpr(rd);
2519 break;
2520#else
0f8a249a 2521 goto nfpu_insn;
1f587329 2522#endif
3475187d 2523#ifdef TARGET_SPARC64
0f8a249a
BS		 2524 case 0x2: /* V9 fmovd */
2525 gen_op_load_fpr_DT0(DFPREG(rs2));
2526 gen_op_store_DT0_fpr(DFPREG(rd));
2527 break;
1f587329
BS		 2528 case 0x3: /* V9 fmovq */
2529#if defined(CONFIG_USER_ONLY)
2530 gen_op_load_fpr_QT0(QFPREG(rs2));
2531 gen_op_store_QT0_fpr(QFPREG(rd));
2532 break;
2533#else
2534 goto nfpu_insn;
2535#endif
0f8a249a
BS		 2536 case 0x6: /* V9 fnegd */
2537 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 2538 tcg_gen_helper_0_0(helper_fnegd);
0f8a249a
BS		 2539 gen_op_store_DT0_fpr(DFPREG(rd));
2540 break;
1f587329
BS		 2541 case 0x7: /* V9 fnegq */
2542#if defined(CONFIG_USER_ONLY)
2543 gen_op_load_fpr_QT1(QFPREG(rs2));
44e7757c 2544 tcg_gen_helper_0_0(helper_fnegq);
1f587329
BS		 2545 gen_op_store_QT0_fpr(QFPREG(rd));
2546 break;
2547#else
2548 goto nfpu_insn;
2549#endif
0f8a249a
BS		 2550 case 0xa: /* V9 fabsd */
2551 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2552 tcg_gen_helper_0_0(helper_fabsd);
0f8a249a
BS		 2553 gen_op_store_DT0_fpr(DFPREG(rd));
2554 break;
1f587329
BS		 2555 case 0xb: /* V9 fabsq */
2556#if defined(CONFIG_USER_ONLY)
2557 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2558 tcg_gen_helper_0_0(helper_fabsq);
1f587329
BS		 2559 gen_op_store_QT0_fpr(QFPREG(rd));
2560 break;
2561#else
2562 goto nfpu_insn;
2563#endif
0f8a249a
BS		 2564 case 0x81: /* V9 fstox */
2565 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2566 gen_clear_float_exceptions();
44e7757c 2567 tcg_gen_helper_0_0(helper_fstox);
7e8c2b6c 2568 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2569 gen_op_store_DT0_fpr(DFPREG(rd));
2570 break;
2571 case 0x82: /* V9 fdtox */
2572 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2573 gen_clear_float_exceptions();
44e7757c 2574 tcg_gen_helper_0_0(helper_fdtox);
7e8c2b6c 2575 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2576 gen_op_store_DT0_fpr(DFPREG(rd));
2577 break;
1f587329
BS		 2578 case 0x83: /* V9 fqtox */
2579#if defined(CONFIG_USER_ONLY)
2580 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2581 gen_clear_float_exceptions();
44e7757c 2582 tcg_gen_helper_0_0(helper_fqtox);
7e8c2b6c 2583 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2584 gen_op_store_DT0_fpr(DFPREG(rd));
2585 break;
2586#else
2587 goto nfpu_insn;
2588#endif
0f8a249a
BS		 2589 case 0x84: /* V9 fxtos */
2590 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2591 gen_clear_float_exceptions();
44e7757c 2592 tcg_gen_helper_0_0(helper_fxtos);
7e8c2b6c 2593 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2594 gen_op_store_FT0_fpr(rd);
2595 break;
2596 case 0x88: /* V9 fxtod */
2597 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2598 gen_clear_float_exceptions();
44e7757c 2599 tcg_gen_helper_0_0(helper_fxtod);
7e8c2b6c 2600 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2601 gen_op_store_DT0_fpr(DFPREG(rd));
2602 break;
0f8a249a 2603 case 0x8c: /* V9 fxtoq */
1f587329
BS		 2604#if defined(CONFIG_USER_ONLY)
2605 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2606 gen_clear_float_exceptions();
44e7757c 2607 tcg_gen_helper_0_0(helper_fxtoq);
7e8c2b6c 2608 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2609 gen_op_store_QT0_fpr(QFPREG(rd));
2610 break;
2611#else
0f8a249a 2612 goto nfpu_insn;
1f587329 2613#endif
0f8a249a
BS		 2614#endif
2615 default:
2616 goto illegal_insn;
2617 }
2618 } else if (xop == 0x35) { /* FPU Operations */
3475187d 2619#ifdef TARGET_SPARC64
0f8a249a 2620 int cond;
3475187d 2621#endif
6ae20372 2622 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 2623 goto jmp_insn;
0f8a249a 2624 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 2625 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2626 rs2 = GET_FIELD(insn, 27, 31);
2627 xop = GET_FIELD(insn, 18, 26);
3475187d 2628#ifdef TARGET_SPARC64
0f8a249a 2629 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
dcf24905
BS		 2630 int l1;
2631
2632 l1 = gen_new_label();
0f8a249a 2633 cond = GET_FIELD_SP(insn, 14, 17);
9322a4bf 2634 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372 2635 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
0425bee5 2636 tcg_const_tl(0), l1);
19f329ad 2637 gen_op_load_fpr_FT0(rs2);
0f8a249a 2638 gen_op_store_FT0_fpr(rd);
dcf24905 2639 gen_set_label(l1);
0f8a249a
BS		 2640 break;
2641 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
dcf24905
BS		 2642 int l1;
2643
2644 l1 = gen_new_label();
0f8a249a 2645 cond = GET_FIELD_SP(insn, 14, 17);
9322a4bf 2646 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372 2647 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
0425bee5 2648 tcg_const_tl(0), l1);
19f329ad 2649 gen_op_load_fpr_DT0(DFPREG(rs2));
2382dc6b 2650 gen_op_store_DT0_fpr(DFPREG(rd));
dcf24905 2651 gen_set_label(l1);
0f8a249a
BS		 2652 break;
2653 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1f587329 2654#if defined(CONFIG_USER_ONLY)
dcf24905
BS		 2655 int l1;
2656
2657 l1 = gen_new_label();
1f587329 2658 cond = GET_FIELD_SP(insn, 14, 17);
9322a4bf 2659 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372 2660 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
0425bee5 2661 tcg_const_tl(0), l1);
19f329ad 2662 gen_op_load_fpr_QT0(QFPREG(rs2));
1f587329 2663 gen_op_store_QT0_fpr(QFPREG(rd));
dcf24905 2664 gen_set_label(l1);
1f587329
BS		 2665 break;
2666#else
0f8a249a 2667 goto nfpu_insn;
1f587329 2668#endif
0f8a249a
BS		 2669 }
2670#endif
2671 switch (xop) {
3475187d 2672#ifdef TARGET_SPARC64
19f329ad
BS		 2673#define FMOVCC(size_FDQ, fcc) \
2674 { \
0425bee5 2675 TCGv r_cond; \
19f329ad
BS		 2676 int l1; \
2677 \
2678 l1 = gen_new_label(); \
19f329ad 2679 r_cond = tcg_temp_new(TCG_TYPE_TL); \
19f329ad
BS		 2680 cond = GET_FIELD_SP(insn, 14, 17); \
2681 gen_fcond(r_cond, fcc, cond); \
0425bee5
BS		 2682 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \
2683 tcg_const_tl(0), l1); \
19f329ad
BS		 2684 glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2685 glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2686 gen_set_label(l1); \
2687 }
0f8a249a 2688 case 0x001: /* V9 fmovscc %fcc0 */
19f329ad 2689 FMOVCC(F, 0);
0f8a249a
BS		 2690 break;
2691 case 0x002: /* V9 fmovdcc %fcc0 */
19f329ad 2692 FMOVCC(D, 0);
0f8a249a
BS		 2693 break;
2694 case 0x003: /* V9 fmovqcc %fcc0 */
1f587329 2695#if defined(CONFIG_USER_ONLY)
19f329ad 2696 FMOVCC(Q, 0);
1f587329
BS		 2697 break;
2698#else
0f8a249a 2699 goto nfpu_insn;
1f587329 2700#endif
0f8a249a 2701 case 0x041: /* V9 fmovscc %fcc1 */
19f329ad 2702 FMOVCC(F, 1);
0f8a249a
BS		 2703 break;
2704 case 0x042: /* V9 fmovdcc %fcc1 */
19f329ad 2705 FMOVCC(D, 1);
0f8a249a
BS		 2706 break;
2707 case 0x043: /* V9 fmovqcc %fcc1 */
1f587329 2708#if defined(CONFIG_USER_ONLY)
19f329ad 2709 FMOVCC(Q, 1);
1f587329
BS		 2710 break;
2711#else
0f8a249a 2712 goto nfpu_insn;
1f587329 2713#endif
0f8a249a 2714 case 0x081: /* V9 fmovscc %fcc2 */
19f329ad 2715 FMOVCC(F, 2);
0f8a249a
BS		 2716 break;
2717 case 0x082: /* V9 fmovdcc %fcc2 */
19f329ad 2718 FMOVCC(D, 2);
0f8a249a
BS		 2719 break;
2720 case 0x083: /* V9 fmovqcc %fcc2 */
1f587329 2721#if defined(CONFIG_USER_ONLY)
19f329ad 2722 FMOVCC(Q, 2);
1f587329
BS		 2723 break;
2724#else
0f8a249a 2725 goto nfpu_insn;
1f587329 2726#endif
0f8a249a 2727 case 0x0c1: /* V9 fmovscc %fcc3 */
19f329ad 2728 FMOVCC(F, 3);
0f8a249a
BS		 2729 break;
2730 case 0x0c2: /* V9 fmovdcc %fcc3 */
19f329ad 2731 FMOVCC(D, 3);
0f8a249a
BS		 2732 break;
2733 case 0x0c3: /* V9 fmovqcc %fcc3 */
1f587329 2734#if defined(CONFIG_USER_ONLY)
19f329ad 2735 FMOVCC(Q, 3);
1f587329
BS		 2736 break;
2737#else
0f8a249a 2738 goto nfpu_insn;
1f587329 2739#endif
19f329ad
BS		 2740#undef FMOVCC
2741#define FMOVCC(size_FDQ, icc) \
2742 { \
0425bee5 2743 TCGv r_cond; \
19f329ad
BS		 2744 int l1; \
2745 \
2746 l1 = gen_new_label(); \
19f329ad 2747 r_cond = tcg_temp_new(TCG_TYPE_TL); \
19f329ad
BS		 2748 cond = GET_FIELD_SP(insn, 14, 17); \
2749 gen_cond(r_cond, icc, cond); \
0425bee5
BS		 2750 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \
2751 tcg_const_tl(0), l1); \
19f329ad
BS		 2752 glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2753 glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2754 gen_set_label(l1); \
2755 }
2756
0f8a249a 2757 case 0x101: /* V9 fmovscc %icc */
19f329ad 2758 FMOVCC(F, 0);
0f8a249a
BS		 2759 break;
2760 case 0x102: /* V9 fmovdcc %icc */
19f329ad 2761 FMOVCC(D, 0);
0f8a249a 2762 case 0x103: /* V9 fmovqcc %icc */
1f587329 2763#if defined(CONFIG_USER_ONLY)
19f329ad 2764 FMOVCC(D, 0);
1f587329
BS		 2765 break;
2766#else
0f8a249a 2767 goto nfpu_insn;
1f587329 2768#endif
0f8a249a 2769 case 0x181: /* V9 fmovscc %xcc */
19f329ad 2770 FMOVCC(F, 1);
0f8a249a
BS		 2771 break;
2772 case 0x182: /* V9 fmovdcc %xcc */
19f329ad 2773 FMOVCC(D, 1);
0f8a249a
BS		 2774 break;
2775 case 0x183: /* V9 fmovqcc %xcc */
1f587329 2776#if defined(CONFIG_USER_ONLY)
19f329ad 2777 FMOVCC(Q, 1);
1f587329
BS		 2778 break;
2779#else
0f8a249a
BS		 2780 goto nfpu_insn;
2781#endif
19f329ad 2782#undef FMOVCC
1f587329
BS		 2783#endif
2784 case 0x51: /* fcmps, V9 %fcc */
0f8a249a
BS		 2785 gen_op_load_fpr_FT0(rs1);
2786 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2787 gen_op_fcmps(rd & 3);
0f8a249a 2788 break;
1f587329 2789 case 0x52: /* fcmpd, V9 %fcc */
0f8a249a
BS		 2790 gen_op_load_fpr_DT0(DFPREG(rs1));
2791 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2792 gen_op_fcmpd(rd & 3);
0f8a249a 2793 break;
1f587329
BS		 2794 case 0x53: /* fcmpq, V9 %fcc */
2795#if defined(CONFIG_USER_ONLY)
2796 gen_op_load_fpr_QT0(QFPREG(rs1));
2797 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2798 gen_op_fcmpq(rd & 3);
1f587329
BS		 2799 break;
2800#else /* !defined(CONFIG_USER_ONLY) */
0f8a249a 2801 goto nfpu_insn;
1f587329 2802#endif
0f8a249a
BS		 2803 case 0x55: /* fcmpes, V9 %fcc */
2804 gen_op_load_fpr_FT0(rs1);
2805 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2806 gen_op_fcmpes(rd & 3);
0f8a249a
BS		 2807 break;
2808 case 0x56: /* fcmped, V9 %fcc */
2809 gen_op_load_fpr_DT0(DFPREG(rs1));
2810 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2811 gen_op_fcmped(rd & 3);
0f8a249a 2812 break;
1f587329
BS		 2813 case 0x57: /* fcmpeq, V9 %fcc */
2814#if defined(CONFIG_USER_ONLY)
2815 gen_op_load_fpr_QT0(QFPREG(rs1));
2816 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2817 gen_op_fcmpeq(rd & 3);
1f587329
BS		 2818 break;
2819#else/* !defined(CONFIG_USER_ONLY) */
0f8a249a 2820 goto nfpu_insn;
1f587329 2821#endif
0f8a249a
BS		 2822 default:
2823 goto illegal_insn;
2824 }
0f8a249a
BS		 2825 } else if (xop == 0x2) {
2826 // clr/mov shortcut
e80cfcfc
FB		 2827
2828 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 2829 if (rs1 == 0) {
1a2fb1c0 2830 // or %g0, x, y -> mov T0, x; mov y, T0
0f8a249a
BS		 2831 if (IS_IMM) { /* immediate */
2832 rs2 = GET_FIELDs(insn, 19, 31);
6ae20372 2833 tcg_gen_movi_tl(cpu_dst, (int)rs2);
0f8a249a
BS		 2834 } else { /* register */
2835 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 2836 gen_movl_reg_TN(rs2, cpu_dst);
0f8a249a 2837 }
0f8a249a 2838 } else {
9322a4bf 2839 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a 2840 if (IS_IMM) { /* immediate */
0f8a249a 2841 rs2 = GET_FIELDs(insn, 19, 31);
6ae20372 2842 tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
0f8a249a
BS		 2843 } else { /* register */
2844 // or x, %g0, y -> mov T1, x; mov y, T1
2845 rs2 = GET_FIELD(insn, 27, 31);
2846 if (rs2 != 0) {
6ae20372
BS		 2847 gen_movl_reg_TN(rs2, cpu_src2);
2848 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
6f551262
BS		 2849 } else
2850 tcg_gen_mov_tl(cpu_dst, cpu_src1);
0f8a249a 2851 }
0f8a249a 2852 }
6ae20372 2853 gen_movl_TN_reg(rd, cpu_dst);
83469015 2854#ifdef TARGET_SPARC64
0f8a249a 2855 } else if (xop == 0x25) { /* sll, V9 sllx */
9322a4bf 2856 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a 2857 if (IS_IMM) { /* immediate */
83469015 2858 rs2 = GET_FIELDs(insn, 20, 31);
1a2fb1c0 2859 if (insn & (1 << 12)) {
6ae20372 2860 tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
1a2fb1c0 2861 } else {
6ae20372
BS		 2862 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2863 tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
1a2fb1c0 2864 }
0f8a249a 2865 } else { /* register */
83469015 2866 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 2867 gen_movl_reg_TN(rs2, cpu_src2);
1a2fb1c0 2868 if (insn & (1 << 12)) {
6ae20372
BS		 2869 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2870 tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 2871 } else {
6ae20372
BS		 2872 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2873 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2874 tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 2875 }
83469015 2876 }
6ae20372 2877 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a 2878 } else if (xop == 0x26) { /* srl, V9 srlx */
9322a4bf 2879 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a 2880 if (IS_IMM) { /* immediate */
83469015 2881 rs2 = GET_FIELDs(insn, 20, 31);
1a2fb1c0 2882 if (insn & (1 << 12)) {
6ae20372 2883 tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
1a2fb1c0 2884 } else {
6ae20372
BS		 2885 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2886 tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
1a2fb1c0 2887 }
0f8a249a 2888 } else { /* register */
83469015 2889 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 2890 gen_movl_reg_TN(rs2, cpu_src2);
1a2fb1c0 2891 if (insn & (1 << 12)) {
6ae20372
BS		 2892 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2893 tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 2894 } else {
6ae20372
BS		 2895 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2896 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2897 tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 2898 }
83469015 2899 }
6ae20372 2900 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a 2901 } else if (xop == 0x27) { /* sra, V9 srax */
9322a4bf 2902 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a 2903 if (IS_IMM) { /* immediate */
83469015 2904 rs2 = GET_FIELDs(insn, 20, 31);
1a2fb1c0 2905 if (insn & (1 << 12)) {
6ae20372 2906 tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
1a2fb1c0 2907 } else {
6ae20372
BS		 2908 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2909 tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2910 tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
1a2fb1c0 2911 }
0f8a249a 2912 } else { /* register */
83469015 2913 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 2914 gen_movl_reg_TN(rs2, cpu_src2);
1a2fb1c0 2915 if (insn & (1 << 12)) {
6ae20372
BS		 2916 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2917 tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 2918 } else {
6ae20372
BS		 2919 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2920 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2921 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 2922 }
83469015 2923 }
6ae20372 2924 gen_movl_TN_reg(rd, cpu_dst);
e80cfcfc 2925#endif
fcc72045 2926 } else if (xop < 0x36) {
9322a4bf 2927 cpu_src1 = get_src1(insn, cpu_src1);
a49d9390 2928 cpu_src2 = get_src2(insn, cpu_src2);
cf495bcf
FB		 2929 if (xop < 0x20) {
2930 switch (xop & ~0x10) {
2931 case 0x0:
2932 if (xop & 0x10)
6ae20372 2933 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
cf495bcf 2934 else
6ae20372 2935 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
cf495bcf
FB		 2936 break;
2937 case 0x1:
6ae20372 2938 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
cf495bcf 2939 if (xop & 0x10)
6ae20372 2940 gen_op_logic_cc(cpu_dst);
cf495bcf
FB		 2941 break;
2942 case 0x2:
6ae20372 2943 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
0f8a249a 2944 if (xop & 0x10)
6ae20372 2945 gen_op_logic_cc(cpu_dst);
0f8a249a 2946 break;
cf495bcf 2947 case 0x3:
6ae20372 2948 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
cf495bcf 2949 if (xop & 0x10)
6ae20372 2950 gen_op_logic_cc(cpu_dst);
cf495bcf
FB		 2951 break;
2952 case 0x4:
2953 if (xop & 0x10)
6ae20372 2954 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
cf495bcf 2955 else
6ae20372 2956 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
cf495bcf
FB		 2957 break;
2958 case 0x5:
6ae20372
BS		 2959 tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2960 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
cf495bcf 2961 if (xop & 0x10)
6ae20372 2962 gen_op_logic_cc(cpu_dst);
cf495bcf
FB		 2963 break;
2964 case 0x6:
6ae20372
BS		 2965 tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2966 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
cf495bcf 2967 if (xop & 0x10)
6ae20372 2968 gen_op_logic_cc(cpu_dst);
cf495bcf
FB		 2969 break;
2970 case 0x7:
6ae20372
BS		 2971 tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2972 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
cf495bcf 2973 if (xop & 0x10)
6ae20372 2974 gen_op_logic_cc(cpu_dst);
cf495bcf
FB		 2975 break;
2976 case 0x8:
cf495bcf 2977 if (xop & 0x10)
6ae20372 2978 gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
38bc628b 2979 else {
dc99a3f2 2980 gen_mov_reg_C(cpu_tmp0, cpu_psr);
6ae20372
BS		 2981 tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
2982 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
38bc628b 2983 }
cf495bcf 2984 break;
ded3ab80 2985#ifdef TARGET_SPARC64
0f8a249a 2986 case 0x9: /* V9 mulx */
6ae20372 2987 tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
ded3ab80
PB		 2988 break;
2989#endif
cf495bcf 2990 case 0xa:
6ae20372 2991 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
cf495bcf 2992 if (xop & 0x10)
6ae20372 2993 gen_op_logic_cc(cpu_dst);
cf495bcf
FB		 2994 break;
2995 case 0xb:
6ae20372 2996 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
cf495bcf 2997 if (xop & 0x10)
6ae20372 2998 gen_op_logic_cc(cpu_dst);
cf495bcf
FB		 2999 break;
3000 case 0xc:
cf495bcf 3001 if (xop & 0x10)
6ae20372 3002 gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
38bc628b 3003 else {
dc99a3f2 3004 gen_mov_reg_C(cpu_tmp0, cpu_psr);
6ae20372
BS		 3005 tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3006 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
38bc628b 3007 }
cf495bcf 3008 break;
ded3ab80 3009#ifdef TARGET_SPARC64
0f8a249a 3010 case 0xd: /* V9 udivx */
6ae20372
BS		 3011 gen_trap_ifdivzero_tl(cpu_src2);
3012 tcg_gen_divu_i64(cpu_dst, cpu_src1, cpu_src2);
ded3ab80
PB		 3013 break;
3014#endif
cf495bcf 3015 case 0xe:
6ae20372 3016 tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1, cpu_src2);
cf495bcf 3017 if (xop & 0x10)
6ae20372 3018 gen_op_div_cc(cpu_dst);
cf495bcf
FB		 3019 break;
3020 case 0xf:
6ae20372 3021 tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1, cpu_src2);
cf495bcf 3022 if (xop & 0x10)
6ae20372 3023 gen_op_div_cc(cpu_dst);
cf495bcf
FB		 3024 break;
3025 default:
3026 goto illegal_insn;
3027 }
6ae20372 3028 gen_movl_TN_reg(rd, cpu_dst);
cf495bcf
FB		 3029 } else {
3030 switch (xop) {
0f8a249a 3031 case 0x20: /* taddcc */
6ae20372
BS		 3032 gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3033 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 3034 break;
3035 case 0x21: /* tsubcc */
6ae20372
BS		 3036 gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3037 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 3038 break;
3039 case 0x22: /* taddcctv */
6ae20372
BS		 3040 save_state(dc, cpu_cond);
3041 gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3042 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 3043 break;
3044 case 0x23: /* tsubcctv */
6ae20372
BS		 3045 save_state(dc, cpu_cond);
3046 gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3047 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a 3048 break;
cf495bcf 3049 case 0x24: /* mulscc */
6ae20372
BS		 3050 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3051 gen_movl_TN_reg(rd, cpu_dst);
cf495bcf 3052 break;
83469015 3053#ifndef TARGET_SPARC64
0f8a249a 3054 case 0x25: /* sll */
6ae20372
BS		 3055 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3056 tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3057 gen_movl_TN_reg(rd, cpu_dst);
cf495bcf 3058 break;
83469015 3059 case 0x26: /* srl */
6ae20372
BS		 3060 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3061 tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3062 gen_movl_TN_reg(rd, cpu_dst);
cf495bcf 3063 break;
83469015 3064 case 0x27: /* sra */
6ae20372
BS		 3065 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3066 tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3067 gen_movl_TN_reg(rd, cpu_dst);
cf495bcf 3068 break;
83469015 3069#endif
cf495bcf
FB		 3070 case 0x30:
3071 {
cf495bcf 3072 switch(rd) {
3475187d 3073 case 0: /* wry */
6ae20372
BS		 3074 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3075 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, y));
cf495bcf 3076 break;
65fe7b09
BS		 3077#ifndef TARGET_SPARC64
3078 case 0x01 ... 0x0f: /* undefined in the
3079 SPARCv8 manual, nop
3080 on the microSPARC
3081 II */
3082 case 0x10 ... 0x1f: /* implementation-dependent
3083 in the SPARCv8
3084 manual, nop on the
3085 microSPARC II */
3086 break;
3087#else
0f8a249a 3088 case 0x2: /* V9 wrccr */
6ae20372
BS		 3089 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3090 tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
0f8a249a
BS		 3091 break;
3092 case 0x3: /* V9 wrasi */
6ae20372
BS		 3093 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3094 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3095 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
0f8a249a
BS		 3096 break;
3097 case 0x6: /* V9 wrfprs */
6ae20372
BS		 3098 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3099 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3100 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
6ae20372 3101 save_state(dc, cpu_cond);
3299908c 3102 gen_op_next_insn();
57fec1fe 3103 tcg_gen_exit_tb(0);
3299908c 3104 dc->is_br = 1;
0f8a249a
BS		 3105 break;
3106 case 0xf: /* V9 sir, nop if user */
3475187d 3107#if !defined(CONFIG_USER_ONLY)
0f8a249a 3108 if (supervisor(dc))
1a2fb1c0 3109 ; // XXX
3475187d 3110#endif
0f8a249a
BS		 3111 break;
3112 case 0x13: /* Graphics Status */
6ae20372 3113 if (gen_trap_ifnofpu(dc, cpu_cond))
725cb90b 3114 goto jmp_insn;
6ae20372
BS		 3115 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3116 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, gsr));
0f8a249a
BS		 3117 break;
3118 case 0x17: /* Tick compare */
83469015 3119#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3120 if (!supervisor(dc))
3121 goto illegal_insn;
83469015 3122#endif
ccd4a219
BS		 3123 {
3124 TCGv r_tickptr;
3125
6ae20372
BS		 3126 tcg_gen_xor_tl(cpu_dst, cpu_src1,
3127 cpu_src2);
3128 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
ccd4a219
BS		 3129 tick_cmpr));
3130 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3131 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3132 offsetof(CPUState, tick));
3133 tcg_gen_helper_0_2(helper_tick_set_limit,
6ae20372 3134 r_tickptr, cpu_dst);
ccd4a219 3135 }
0f8a249a
BS		 3136 break;
3137 case 0x18: /* System tick */
83469015 3138#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3139 if (!supervisor(dc))
3140 goto illegal_insn;
83469015 3141#endif
ccd4a219
BS		 3142 {
3143 TCGv r_tickptr;
3144
6ae20372
BS		 3145 tcg_gen_xor_tl(cpu_dst, cpu_src1,
3146 cpu_src2);
ccd4a219
BS		 3147 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3148 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3149 offsetof(CPUState, stick));
3150 tcg_gen_helper_0_2(helper_tick_set_count,
6ae20372 3151 r_tickptr, cpu_dst);
ccd4a219 3152 }
0f8a249a
BS		 3153 break;
3154 case 0x19: /* System tick compare */
83469015 3155#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3156 if (!supervisor(dc))
3157 goto illegal_insn;
3475187d 3158#endif
ccd4a219
BS		 3159 {
3160 TCGv r_tickptr;
3161
6ae20372
BS		 3162 tcg_gen_xor_tl(cpu_dst, cpu_src1,
3163 cpu_src2);
3164 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
ccd4a219
BS		 3165 stick_cmpr));
3166 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3167 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3168 offsetof(CPUState, stick));
3169 tcg_gen_helper_0_2(helper_tick_set_limit,
6ae20372 3170 r_tickptr, cpu_dst);
ccd4a219 3171 }
0f8a249a 3172 break;
83469015 3173
0f8a249a
BS		 3174 case 0x10: /* Performance Control */
3175 case 0x11: /* Performance Instrumentation Counter */
3176 case 0x12: /* Dispatch Control */
3177 case 0x14: /* Softint set */
3178 case 0x15: /* Softint clear */
3179 case 0x16: /* Softint write */
83469015 3180#endif
3475187d 3181 default:
cf495bcf
FB		 3182 goto illegal_insn;
3183 }
3184 }
3185 break;
e8af50a3 3186#if !defined(CONFIG_USER_ONLY)
af7bf89b 3187 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3 3188 {
0f8a249a
BS		 3189 if (!supervisor(dc))
3190 goto priv_insn;
3475187d 3191#ifdef TARGET_SPARC64
0f8a249a
BS		 3192 switch (rd) {
3193 case 0:
72a9747b 3194 tcg_gen_helper_0_0(helper_saved);
0f8a249a
BS		 3195 break;
3196 case 1:
72a9747b 3197 tcg_gen_helper_0_0(helper_restored);
0f8a249a 3198 break;
e9ebed4d
BS		 3199 case 2: /* UA2005 allclean */
3200 case 3: /* UA2005 otherw */
3201 case 4: /* UA2005 normalw */
3202 case 5: /* UA2005 invalw */
3203 // XXX
0f8a249a 3204 default:
3475187d
FB		 3205 goto illegal_insn;
3206 }
3207#else
6ae20372
BS		 3208 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3209 tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3210 save_state(dc, cpu_cond);
9e61bde5 3211 gen_op_next_insn();
57fec1fe 3212 tcg_gen_exit_tb(0);
0f8a249a 3213 dc->is_br = 1;
3475187d 3214#endif
e8af50a3
FB		 3215 }
3216 break;
af7bf89b 3217 case 0x32: /* wrwim, V9 wrpr */
e8af50a3 3218 {
0f8a249a
BS		 3219 if (!supervisor(dc))
3220 goto priv_insn;
6ae20372 3221 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3475187d 3222#ifdef TARGET_SPARC64
0f8a249a
BS		 3223 switch (rd) {
3224 case 0: // tpc
375ee38b
BS		 3225 {
3226 TCGv r_tsptr;
3227
3228 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3229 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3230 offsetof(CPUState, tsptr));
6ae20372 3231 tcg_gen_st_tl(cpu_dst, r_tsptr,
375ee38b
BS		 3232 offsetof(trap_state, tpc));
3233 }
0f8a249a
BS		 3234 break;
3235 case 1: // tnpc
375ee38b
BS		 3236 {
3237 TCGv r_tsptr;
3238
3239 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3240 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3241 offsetof(CPUState, tsptr));
6ae20372 3242 tcg_gen_st_tl(cpu_dst, r_tsptr,
375ee38b
BS		 3243 offsetof(trap_state, tnpc));
3244 }
0f8a249a
BS		 3245 break;
3246 case 2: // tstate
375ee38b
BS		 3247 {
3248 TCGv r_tsptr;
3249
3250 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3251 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3252 offsetof(CPUState, tsptr));
6ae20372 3253 tcg_gen_st_tl(cpu_dst, r_tsptr,
375ee38b
BS		 3254 offsetof(trap_state, tstate));
3255 }
0f8a249a
BS		 3256 break;
3257 case 3: // tt
375ee38b
BS		 3258 {
3259 TCGv r_tsptr;
3260
3261 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3262 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3263 offsetof(CPUState, tsptr));
6ae20372 3264 tcg_gen_st_i32(cpu_dst, r_tsptr,
375ee38b
BS		 3265 offsetof(trap_state, tt));
3266 }
0f8a249a
BS		 3267 break;
3268 case 4: // tick
ccd4a219
BS		 3269 {
3270 TCGv r_tickptr;
3271
3272 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3273 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3274 offsetof(CPUState, tick));
3275 tcg_gen_helper_0_2(helper_tick_set_count,
6ae20372 3276 r_tickptr, cpu_dst);
ccd4a219 3277 }
0f8a249a
BS		 3278 break;
3279 case 5: // tba
6ae20372 3280 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
0f8a249a
BS		 3281 break;
3282 case 6: // pstate
6ae20372
BS		 3283 save_state(dc, cpu_cond);
3284 tcg_gen_helper_0_1(helper_wrpstate, cpu_dst);
ded3ab80 3285 gen_op_next_insn();
57fec1fe 3286 tcg_gen_exit_tb(0);
ded3ab80 3287 dc->is_br = 1;
0f8a249a
BS		 3288 break;
3289 case 7: // tl
6ae20372 3290 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3291 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
0f8a249a
BS		 3292 break;
3293 case 8: // pil
6ae20372 3294 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3295 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
0f8a249a
BS		 3296 break;
3297 case 9: // cwp
6ae20372 3298 tcg_gen_helper_0_1(helper_wrcwp, cpu_dst);
0f8a249a
BS		 3299 break;
3300 case 10: // cansave
6ae20372 3301 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3302 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
0f8a249a
BS		 3303 break;
3304 case 11: // canrestore
6ae20372 3305 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3306 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
0f8a249a
BS		 3307 break;
3308 case 12: // cleanwin
6ae20372 3309 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3310 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
0f8a249a
BS		 3311 break;
3312 case 13: // otherwin
6ae20372 3313 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3314 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
0f8a249a
BS		 3315 break;
3316 case 14: // wstate
6ae20372 3317 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3318 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
0f8a249a 3319 break;
e9ebed4d 3320 case 16: // UA2005 gl
6ae20372 3321 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3322 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 3323 break;
3324 case 26: // UA2005 strand status
3325 if (!hypervisor(dc))
3326 goto priv_insn;
6ae20372 3327 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3328 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
e9ebed4d 3329 break;
0f8a249a
BS		 3330 default:
3331 goto illegal_insn;
3332 }
3475187d 3333#else
6ae20372
BS		 3334 tcg_gen_andi_tl(cpu_dst, cpu_dst, ((1 << NWINDOWS) - 1));
3335 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3336 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
3475187d 3337#endif
e8af50a3
FB		 3338 }
3339 break;
e9ebed4d 3340 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 3341 {
e9ebed4d 3342#ifndef TARGET_SPARC64
0f8a249a
BS		 3343 if (!supervisor(dc))
3344 goto priv_insn;
6ae20372
BS		 3345 tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
3346 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
e9ebed4d
BS		 3347#else
3348 if (!hypervisor(dc))
3349 goto priv_insn;
6ae20372 3350 tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
e9ebed4d
BS		 3351 switch (rd) {
3352 case 0: // hpstate
3353 // XXX gen_op_wrhpstate();
6ae20372 3354 save_state(dc, cpu_cond);
e9ebed4d 3355 gen_op_next_insn();
57fec1fe 3356 tcg_gen_exit_tb(0);
e9ebed4d
BS		 3357 dc->is_br = 1;
3358 break;
3359 case 1: // htstate
3360 // XXX gen_op_wrhtstate();
3361 break;
3362 case 3: // hintp
6ae20372 3363 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3364 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
e9ebed4d
BS		 3365 break;
3366 case 5: // htba
6ae20372 3367 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2f5680ee 3368 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
e9ebed4d
BS		 3369 break;
3370 case 31: // hstick_cmpr
ccd4a219
BS		 3371 {
3372 TCGv r_tickptr;
3373
6ae20372 3374 tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
ccd4a219
BS		 3375 hstick_cmpr));
3376 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3377 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3378 offsetof(CPUState, hstick));
3379 tcg_gen_helper_0_2(helper_tick_set_limit,
6ae20372 3380 r_tickptr, cpu_dst);
ccd4a219 3381 }
e9ebed4d
BS		 3382 break;
3383 case 6: // hver readonly
3384 default:
3385 goto illegal_insn;
3386 }
3387#endif
e8af50a3
FB		 3388 }
3389 break;
3390#endif
3475187d 3391#ifdef TARGET_SPARC64
0f8a249a
BS		 3392 case 0x2c: /* V9 movcc */
3393 {
3394 int cc = GET_FIELD_SP(insn, 11, 12);
3395 int cond = GET_FIELD_SP(insn, 14, 17);
748b9d8e 3396 TCGv r_cond;
00f219bf
BS		 3397 int l1;
3398
748b9d8e 3399 r_cond = tcg_temp_new(TCG_TYPE_TL);
0f8a249a
BS		 3400 if (insn & (1 << 18)) {
3401 if (cc == 0)
748b9d8e 3402 gen_cond(r_cond, 0, cond);
0f8a249a 3403 else if (cc == 2)
748b9d8e 3404 gen_cond(r_cond, 1, cond);
0f8a249a
BS		 3405 else
3406 goto illegal_insn;
3407 } else {
748b9d8e 3408 gen_fcond(r_cond, cc, cond);
0f8a249a 3409 }
00f219bf
BS		 3410
3411 l1 = gen_new_label();
3412
748b9d8e
BS		 3413 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond,
3414 tcg_const_tl(0), l1);
00f219bf
BS		 3415 if (IS_IMM) { /* immediate */
3416 rs2 = GET_FIELD_SPs(insn, 0, 10);
6ae20372 3417 tcg_gen_movi_tl(cpu_dst, (int)rs2);
00f219bf
BS		 3418 } else {
3419 rs2 = GET_FIELD_SP(insn, 0, 4);
6ae20372 3420 gen_movl_reg_TN(rs2, cpu_dst);
00f219bf 3421 }
6ae20372 3422 gen_movl_TN_reg(rd, cpu_dst);
00f219bf 3423 gen_set_label(l1);
0f8a249a
BS		 3424 break;
3425 }
3426 case 0x2d: /* V9 sdivx */
6ae20372
BS		 3427 gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3428 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 3429 break;
3430 case 0x2e: /* V9 popc */
3431 {
a49d9390 3432 cpu_src2 = get_src2(insn, cpu_src2);
6ae20372
BS		 3433 tcg_gen_helper_1_1(helper_popc, cpu_dst,
3434 cpu_src2);
3435 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 3436 }
3437 case 0x2f: /* V9 movr */
3438 {
3439 int cond = GET_FIELD_SP(insn, 10, 12);
00f219bf
BS		 3440 int l1;
3441
9322a4bf 3442 cpu_src1 = get_src1(insn, cpu_src1);
00f219bf
BS		 3443
3444 l1 = gen_new_label();
3445
6ae20372 3446 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
0425bee5 3447 tcg_const_tl(0), l1);
0f8a249a
BS		 3448 if (IS_IMM) { /* immediate */
3449 rs2 = GET_FIELD_SPs(insn, 0, 9);
6ae20372 3450 tcg_gen_movi_tl(cpu_dst, (int)rs2);
00f219bf 3451 } else {
0f8a249a 3452 rs2 = GET_FIELD_SP(insn, 0, 4);
6ae20372 3453 gen_movl_reg_TN(rs2, cpu_dst);
0f8a249a 3454 }
6ae20372 3455 gen_movl_TN_reg(rd, cpu_dst);
00f219bf 3456 gen_set_label(l1);
0f8a249a
BS		 3457 break;
3458 }
3459#endif
3460 default:
3461 goto illegal_insn;
3462 }
3463 }
3299908c
BS		 3464 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3465#ifdef TARGET_SPARC64
3466 int opf = GET_FIELD_SP(insn, 5, 13);
3467 rs1 = GET_FIELD(insn, 13, 17);
3468 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 3469 if (gen_trap_ifnofpu(dc, cpu_cond))
e9ebed4d 3470 goto jmp_insn;
3299908c
BS		 3471
3472 switch (opf) {
e9ebed4d
BS		 3473 case 0x000: /* VIS I edge8cc */
3474 case 0x001: /* VIS II edge8n */
3475 case 0x002: /* VIS I edge8lcc */
3476 case 0x003: /* VIS II edge8ln */
3477 case 0x004: /* VIS I edge16cc */
3478 case 0x005: /* VIS II edge16n */
3479 case 0x006: /* VIS I edge16lcc */
3480 case 0x007: /* VIS II edge16ln */
3481 case 0x008: /* VIS I edge32cc */
3482 case 0x009: /* VIS II edge32n */
3483 case 0x00a: /* VIS I edge32lcc */
3484 case 0x00b: /* VIS II edge32ln */
3485 // XXX
3486 goto illegal_insn;
3487 case 0x010: /* VIS I array8 */
9322a4bf 3488 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372
BS		 3489 gen_movl_reg_TN(rs2, cpu_src2);
3490 tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3491 cpu_src2);
3492 gen_movl_TN_reg(rd, cpu_dst);
e9ebed4d
BS		 3493 break;
3494 case 0x012: /* VIS I array16 */
9322a4bf 3495 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372
BS		 3496 gen_movl_reg_TN(rs2, cpu_src2);
3497 tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3498 cpu_src2);
3499 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3500 gen_movl_TN_reg(rd, cpu_dst);
e9ebed4d
BS		 3501 break;
3502 case 0x014: /* VIS I array32 */
9322a4bf 3503 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372
BS		 3504 gen_movl_reg_TN(rs2, cpu_src2);
3505 tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3506 cpu_src2);
3507 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3508 gen_movl_TN_reg(rd, cpu_dst);
e9ebed4d 3509 break;
3299908c 3510 case 0x018: /* VIS I alignaddr */
9322a4bf 3511 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372
BS		 3512 gen_movl_reg_TN(rs2, cpu_src2);
3513 tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3514 cpu_src2);
3515 gen_movl_TN_reg(rd, cpu_dst);
3299908c 3516 break;
e9ebed4d 3517 case 0x019: /* VIS II bmask */
3299908c 3518 case 0x01a: /* VIS I alignaddrl */
3299908c 3519 // XXX
e9ebed4d
BS		 3520 goto illegal_insn;
3521 case 0x020: /* VIS I fcmple16 */
2382dc6b
BS		 3522 gen_op_load_fpr_DT0(DFPREG(rs1));
3523 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3524 tcg_gen_helper_0_0(helper_fcmple16);
2382dc6b 3525 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3526 break;
3527 case 0x022: /* VIS I fcmpne16 */
2382dc6b
BS		 3528 gen_op_load_fpr_DT0(DFPREG(rs1));
3529 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3530 tcg_gen_helper_0_0(helper_fcmpne16);
2382dc6b 3531 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c 3532 break;
e9ebed4d 3533 case 0x024: /* VIS I fcmple32 */
2382dc6b
BS		 3534 gen_op_load_fpr_DT0(DFPREG(rs1));
3535 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3536 tcg_gen_helper_0_0(helper_fcmple32);
2382dc6b 3537 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3538 break;
3539 case 0x026: /* VIS I fcmpne32 */
2382dc6b
BS		 3540 gen_op_load_fpr_DT0(DFPREG(rs1));
3541 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3542 tcg_gen_helper_0_0(helper_fcmpne32);
2382dc6b 3543 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3544 break;
3545 case 0x028: /* VIS I fcmpgt16 */
2382dc6b
BS		 3546 gen_op_load_fpr_DT0(DFPREG(rs1));
3547 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3548 tcg_gen_helper_0_0(helper_fcmpgt16);
2382dc6b 3549 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3550 break;
3551 case 0x02a: /* VIS I fcmpeq16 */
2382dc6b
BS		 3552 gen_op_load_fpr_DT0(DFPREG(rs1));
3553 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3554 tcg_gen_helper_0_0(helper_fcmpeq16);
2382dc6b 3555 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3556 break;
3557 case 0x02c: /* VIS I fcmpgt32 */
2382dc6b
BS		 3558 gen_op_load_fpr_DT0(DFPREG(rs1));
3559 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3560 tcg_gen_helper_0_0(helper_fcmpgt32);
2382dc6b 3561 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3562 break;
3563 case 0x02e: /* VIS I fcmpeq32 */
2382dc6b
BS		 3564 gen_op_load_fpr_DT0(DFPREG(rs1));
3565 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3566 tcg_gen_helper_0_0(helper_fcmpeq32);
2382dc6b 3567 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3568 break;
3569 case 0x031: /* VIS I fmul8x16 */
2382dc6b
BS		 3570 gen_op_load_fpr_DT0(DFPREG(rs1));
3571 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3572 tcg_gen_helper_0_0(helper_fmul8x16);
2382dc6b 3573 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3574 break;
3575 case 0x033: /* VIS I fmul8x16au */
2382dc6b
BS		 3576 gen_op_load_fpr_DT0(DFPREG(rs1));
3577 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3578 tcg_gen_helper_0_0(helper_fmul8x16au);
2382dc6b 3579 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3580 break;
3581 case 0x035: /* VIS I fmul8x16al */
2382dc6b
BS		 3582 gen_op_load_fpr_DT0(DFPREG(rs1));
3583 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3584 tcg_gen_helper_0_0(helper_fmul8x16al);
2382dc6b 3585 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3586 break;
3587 case 0x036: /* VIS I fmul8sux16 */
2382dc6b
BS		 3588 gen_op_load_fpr_DT0(DFPREG(rs1));
3589 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3590 tcg_gen_helper_0_0(helper_fmul8sux16);
2382dc6b 3591 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3592 break;
3593 case 0x037: /* VIS I fmul8ulx16 */
2382dc6b
BS		 3594 gen_op_load_fpr_DT0(DFPREG(rs1));
3595 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3596 tcg_gen_helper_0_0(helper_fmul8ulx16);
2382dc6b 3597 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3598 break;
3599 case 0x038: /* VIS I fmuld8sux16 */
2382dc6b
BS		 3600 gen_op_load_fpr_DT0(DFPREG(rs1));
3601 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3602 tcg_gen_helper_0_0(helper_fmuld8sux16);
2382dc6b 3603 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3604 break;
3605 case 0x039: /* VIS I fmuld8ulx16 */
2382dc6b
BS		 3606 gen_op_load_fpr_DT0(DFPREG(rs1));
3607 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3608 tcg_gen_helper_0_0(helper_fmuld8ulx16);
2382dc6b 3609 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3610 break;
3611 case 0x03a: /* VIS I fpack32 */
3612 case 0x03b: /* VIS I fpack16 */
3613 case 0x03d: /* VIS I fpackfix */
3614 case 0x03e: /* VIS I pdist */
3615 // XXX
3616 goto illegal_insn;
3299908c 3617 case 0x048: /* VIS I faligndata */
2382dc6b
BS		 3618 gen_op_load_fpr_DT0(DFPREG(rs1));
3619 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3620 tcg_gen_helper_0_0(helper_faligndata);
2382dc6b 3621 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c 3622 break;
e9ebed4d 3623 case 0x04b: /* VIS I fpmerge */
2382dc6b
BS		 3624 gen_op_load_fpr_DT0(DFPREG(rs1));
3625 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3626 tcg_gen_helper_0_0(helper_fpmerge);
2382dc6b 3627 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3628 break;
3629 case 0x04c: /* VIS II bshuffle */
3630 // XXX
3631 goto illegal_insn;
3632 case 0x04d: /* VIS I fexpand */
2382dc6b
BS		 3633 gen_op_load_fpr_DT0(DFPREG(rs1));
3634 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3635 tcg_gen_helper_0_0(helper_fexpand);
2382dc6b 3636 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3637 break;
3638 case 0x050: /* VIS I fpadd16 */
2382dc6b
BS		 3639 gen_op_load_fpr_DT0(DFPREG(rs1));
3640 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3641 tcg_gen_helper_0_0(helper_fpadd16);
2382dc6b 3642 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3643 break;
3644 case 0x051: /* VIS I fpadd16s */
3645 gen_op_load_fpr_FT0(rs1);
3646 gen_op_load_fpr_FT1(rs2);
44e7757c 3647 tcg_gen_helper_0_0(helper_fpadd16s);
e9ebed4d
BS		 3648 gen_op_store_FT0_fpr(rd);
3649 break;
3650 case 0x052: /* VIS I fpadd32 */
2382dc6b
BS		 3651 gen_op_load_fpr_DT0(DFPREG(rs1));
3652 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3653 tcg_gen_helper_0_0(helper_fpadd32);
2382dc6b 3654 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3655 break;
3656 case 0x053: /* VIS I fpadd32s */
3657 gen_op_load_fpr_FT0(rs1);
3658 gen_op_load_fpr_FT1(rs2);
44e7757c 3659 tcg_gen_helper_0_0(helper_fpadd32s);
e9ebed4d
BS		 3660 gen_op_store_FT0_fpr(rd);
3661 break;
3662 case 0x054: /* VIS I fpsub16 */
2382dc6b
BS		 3663 gen_op_load_fpr_DT0(DFPREG(rs1));
3664 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3665 tcg_gen_helper_0_0(helper_fpsub16);
2382dc6b 3666 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3667 break;
3668 case 0x055: /* VIS I fpsub16s */
3669 gen_op_load_fpr_FT0(rs1);
3670 gen_op_load_fpr_FT1(rs2);
44e7757c 3671 tcg_gen_helper_0_0(helper_fpsub16s);
e9ebed4d
BS		 3672 gen_op_store_FT0_fpr(rd);
3673 break;
3674 case 0x056: /* VIS I fpsub32 */
2382dc6b
BS		 3675 gen_op_load_fpr_DT0(DFPREG(rs1));
3676 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3677 tcg_gen_helper_0_0(helper_fpadd32);
2382dc6b 3678 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3679 break;
3680 case 0x057: /* VIS I fpsub32s */
3681 gen_op_load_fpr_FT0(rs1);
3682 gen_op_load_fpr_FT1(rs2);
44e7757c 3683 tcg_gen_helper_0_0(helper_fpsub32s);
e9ebed4d
BS		 3684 gen_op_store_FT0_fpr(rd);
3685 break;
3299908c 3686 case 0x060: /* VIS I fzero */
44e7757c 3687 tcg_gen_helper_0_0(helper_movl_DT0_0);
2382dc6b 3688 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3689 break;
3690 case 0x061: /* VIS I fzeros */
44e7757c 3691 tcg_gen_helper_0_0(helper_movl_FT0_0);
3299908c
BS		 3692 gen_op_store_FT0_fpr(rd);
3693 break;
e9ebed4d 3694 case 0x062: /* VIS I fnor */
2382dc6b
BS		 3695 gen_op_load_fpr_DT0(DFPREG(rs1));
3696 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3697 tcg_gen_helper_0_0(helper_fnor);
2382dc6b 3698 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3699 break;
3700 case 0x063: /* VIS I fnors */
3701 gen_op_load_fpr_FT0(rs1);
3702 gen_op_load_fpr_FT1(rs2);
44e7757c 3703 tcg_gen_helper_0_0(helper_fnors);
e9ebed4d
BS		 3704 gen_op_store_FT0_fpr(rd);
3705 break;
3706 case 0x064: /* VIS I fandnot2 */
2382dc6b
BS		 3707 gen_op_load_fpr_DT1(DFPREG(rs1));
3708 gen_op_load_fpr_DT0(DFPREG(rs2));
44e7757c 3709 tcg_gen_helper_0_0(helper_fandnot);
2382dc6b 3710 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3711 break;
3712 case 0x065: /* VIS I fandnot2s */
3713 gen_op_load_fpr_FT1(rs1);
3714 gen_op_load_fpr_FT0(rs2);
44e7757c 3715 tcg_gen_helper_0_0(helper_fandnots);
e9ebed4d
BS		 3716 gen_op_store_FT0_fpr(rd);
3717 break;
3718 case 0x066: /* VIS I fnot2 */
2382dc6b 3719 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3720 tcg_gen_helper_0_0(helper_fnot);
2382dc6b 3721 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3722 break;
3723 case 0x067: /* VIS I fnot2s */
3724 gen_op_load_fpr_FT1(rs2);
44e7757c 3725 tcg_gen_helper_0_0(helper_fnot);
e9ebed4d
BS		 3726 gen_op_store_FT0_fpr(rd);
3727 break;
3728 case 0x068: /* VIS I fandnot1 */
2382dc6b
BS		 3729 gen_op_load_fpr_DT0(DFPREG(rs1));
3730 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3731 tcg_gen_helper_0_0(helper_fandnot);
2382dc6b 3732 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3733 break;
3734 case 0x069: /* VIS I fandnot1s */
3735 gen_op_load_fpr_FT0(rs1);
3736 gen_op_load_fpr_FT1(rs2);
44e7757c 3737 tcg_gen_helper_0_0(helper_fandnots);
e9ebed4d
BS		 3738 gen_op_store_FT0_fpr(rd);
3739 break;
3740 case 0x06a: /* VIS I fnot1 */
2382dc6b 3741 gen_op_load_fpr_DT1(DFPREG(rs1));
44e7757c 3742 tcg_gen_helper_0_0(helper_fnot);
2382dc6b 3743 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3744 break;
3745 case 0x06b: /* VIS I fnot1s */
3746 gen_op_load_fpr_FT1(rs1);
44e7757c 3747 tcg_gen_helper_0_0(helper_fnot);
e9ebed4d
BS		 3748 gen_op_store_FT0_fpr(rd);
3749 break;
3750 case 0x06c: /* VIS I fxor */
2382dc6b
BS		 3751 gen_op_load_fpr_DT0(DFPREG(rs1));
3752 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3753 tcg_gen_helper_0_0(helper_fxor);
2382dc6b 3754 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3755 break;
3756 case 0x06d: /* VIS I fxors */
3757 gen_op_load_fpr_FT0(rs1);
3758 gen_op_load_fpr_FT1(rs2);
44e7757c 3759 tcg_gen_helper_0_0(helper_fxors);
e9ebed4d
BS		 3760 gen_op_store_FT0_fpr(rd);
3761 break;
3762 case 0x06e: /* VIS I fnand */
2382dc6b
BS		 3763 gen_op_load_fpr_DT0(DFPREG(rs1));
3764 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3765 tcg_gen_helper_0_0(helper_fnand);
2382dc6b 3766 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3767 break;
3768 case 0x06f: /* VIS I fnands */
3769 gen_op_load_fpr_FT0(rs1);
3770 gen_op_load_fpr_FT1(rs2);
44e7757c 3771 tcg_gen_helper_0_0(helper_fnands);
e9ebed4d
BS		 3772 gen_op_store_FT0_fpr(rd);
3773 break;
3774 case 0x070: /* VIS I fand */
2382dc6b
BS		 3775 gen_op_load_fpr_DT0(DFPREG(rs1));
3776 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3777 tcg_gen_helper_0_0(helper_fand);
2382dc6b 3778 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3779 break;
3780 case 0x071: /* VIS I fands */
3781 gen_op_load_fpr_FT0(rs1);
3782 gen_op_load_fpr_FT1(rs2);
44e7757c 3783 tcg_gen_helper_0_0(helper_fands);
e9ebed4d
BS		 3784 gen_op_store_FT0_fpr(rd);
3785 break;
3786 case 0x072: /* VIS I fxnor */
2382dc6b
BS		 3787 gen_op_load_fpr_DT0(DFPREG(rs1));
3788 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3789 tcg_gen_helper_0_0(helper_fxnor);
2382dc6b 3790 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3791 break;
3792 case 0x073: /* VIS I fxnors */
3793 gen_op_load_fpr_FT0(rs1);
3794 gen_op_load_fpr_FT1(rs2);
44e7757c 3795 tcg_gen_helper_0_0(helper_fxnors);
e9ebed4d
BS		 3796 gen_op_store_FT0_fpr(rd);
3797 break;
3299908c 3798 case 0x074: /* VIS I fsrc1 */
2382dc6b
BS		 3799 gen_op_load_fpr_DT0(DFPREG(rs1));
3800 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3801 break;
3802 case 0x075: /* VIS I fsrc1s */
3299908c
BS		 3803 gen_op_load_fpr_FT0(rs1);
3804 gen_op_store_FT0_fpr(rd);
3805 break;
e9ebed4d 3806 case 0x076: /* VIS I fornot2 */
2382dc6b
BS		 3807 gen_op_load_fpr_DT1(DFPREG(rs1));
3808 gen_op_load_fpr_DT0(DFPREG(rs2));
44e7757c 3809 tcg_gen_helper_0_0(helper_fornot);
2382dc6b 3810 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3811 break;
3812 case 0x077: /* VIS I fornot2s */
3813 gen_op_load_fpr_FT1(rs1);
3814 gen_op_load_fpr_FT0(rs2);
44e7757c 3815 tcg_gen_helper_0_0(helper_fornots);
e9ebed4d
BS		 3816 gen_op_store_FT0_fpr(rd);
3817 break;
3299908c 3818 case 0x078: /* VIS I fsrc2 */
2382dc6b
BS		 3819 gen_op_load_fpr_DT0(DFPREG(rs2));
3820 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3821 break;
3822 case 0x079: /* VIS I fsrc2s */
3299908c
BS		 3823 gen_op_load_fpr_FT0(rs2);
3824 gen_op_store_FT0_fpr(rd);
3825 break;
e9ebed4d 3826 case 0x07a: /* VIS I fornot1 */
2382dc6b
BS		 3827 gen_op_load_fpr_DT0(DFPREG(rs1));
3828 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3829 tcg_gen_helper_0_0(helper_fornot);
2382dc6b 3830 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3831 break;
3832 case 0x07b: /* VIS I fornot1s */
3833 gen_op_load_fpr_FT0(rs1);
3834 gen_op_load_fpr_FT1(rs2);
44e7757c 3835 tcg_gen_helper_0_0(helper_fornots);
e9ebed4d
BS		 3836 gen_op_store_FT0_fpr(rd);
3837 break;
3838 case 0x07c: /* VIS I for */
2382dc6b
BS		 3839 gen_op_load_fpr_DT0(DFPREG(rs1));
3840 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3841 tcg_gen_helper_0_0(helper_for);
2382dc6b 3842 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3843 break;
3844 case 0x07d: /* VIS I fors */
3845 gen_op_load_fpr_FT0(rs1);
3846 gen_op_load_fpr_FT1(rs2);
44e7757c 3847 tcg_gen_helper_0_0(helper_fors);
e9ebed4d
BS		 3848 gen_op_store_FT0_fpr(rd);
3849 break;
3299908c 3850 case 0x07e: /* VIS I fone */
44e7757c 3851 tcg_gen_helper_0_0(helper_movl_DT0_1);
2382dc6b 3852 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3853 break;
3854 case 0x07f: /* VIS I fones */
44e7757c 3855 tcg_gen_helper_0_0(helper_movl_FT0_1);
3299908c
BS		 3856 gen_op_store_FT0_fpr(rd);
3857 break;
e9ebed4d
BS		 3858 case 0x080: /* VIS I shutdown */
3859 case 0x081: /* VIS II siam */
3860 // XXX
3861 goto illegal_insn;
3299908c
BS		 3862 default:
3863 goto illegal_insn;
3864 }
3865#else
0f8a249a 3866 goto ncp_insn;
3299908c
BS		 3867#endif
3868 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045 3869#ifdef TARGET_SPARC64
0f8a249a 3870 goto illegal_insn;
fcc72045 3871#else
0f8a249a 3872 goto ncp_insn;
fcc72045 3873#endif
3475187d 3874#ifdef TARGET_SPARC64
0f8a249a 3875 } else if (xop == 0x39) { /* V9 return */
6ae20372 3876 save_state(dc, cpu_cond);
9322a4bf 3877 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a
BS		 3878 if (IS_IMM) { /* immediate */
3879 rs2 = GET_FIELDs(insn, 19, 31);
6ae20372 3880 tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
0f8a249a 3881 } else { /* register */
3475187d 3882 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 3883 if (rs2) {
6ae20372
BS		 3884 gen_movl_reg_TN(rs2, cpu_src2);
3885 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
6f551262
BS		 3886 } else
3887 tcg_gen_mov_tl(cpu_dst, cpu_src1);
3475187d 3888 }
72a9747b 3889 tcg_gen_helper_0_0(helper_restore);
6ae20372
BS		 3890 gen_mov_pc_npc(dc, cpu_cond);
3891 tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
3892 tcg_gen_mov_tl(cpu_npc, cpu_dst);
0f8a249a
BS		 3893 dc->npc = DYNAMIC_PC;
3894 goto jmp_insn;
3475187d 3895#endif
0f8a249a 3896 } else {
9322a4bf 3897 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a
BS		 3898 if (IS_IMM) { /* immediate */
3899 rs2 = GET_FIELDs(insn, 19, 31);
6ae20372 3900 tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
0f8a249a 3901 } else { /* register */
e80cfcfc 3902 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 3903 if (rs2) {
6ae20372
BS		 3904 gen_movl_reg_TN(rs2, cpu_src2);
3905 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
6f551262
BS		 3906 } else
3907 tcg_gen_mov_tl(cpu_dst, cpu_src1);
cf495bcf 3908 }
0f8a249a
BS		 3909 switch (xop) {
3910 case 0x38: /* jmpl */
3911 {
3912 if (rd != 0) {
32b6c812
BS		 3913 tcg_gen_movi_tl(cpu_tmp0, dc->pc);
3914 gen_movl_TN_reg(rd, cpu_tmp0);
0f8a249a 3915 }
6ae20372
BS		 3916 gen_mov_pc_npc(dc, cpu_cond);
3917 tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
3918 tcg_gen_mov_tl(cpu_npc, cpu_dst);
0f8a249a
BS		 3919 dc->npc = DYNAMIC_PC;
3920 }
3921 goto jmp_insn;
3475187d 3922#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
0f8a249a
BS		 3923 case 0x39: /* rett, V9 return */
3924 {
3925 if (!supervisor(dc))
3926 goto priv_insn;
6ae20372
BS		 3927 gen_mov_pc_npc(dc, cpu_cond);
3928 tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
3929 tcg_gen_mov_tl(cpu_npc, cpu_dst);
0f8a249a 3930 dc->npc = DYNAMIC_PC;
1a2fb1c0 3931 tcg_gen_helper_0_0(helper_rett);
0f8a249a
BS		 3932 }
3933 goto jmp_insn;
3934#endif
3935 case 0x3b: /* flush */
6ae20372 3936 tcg_gen_helper_0_1(helper_flush, cpu_dst);
0f8a249a
BS		 3937 break;
3938 case 0x3c: /* save */
6ae20372 3939 save_state(dc, cpu_cond);
72a9747b 3940 tcg_gen_helper_0_0(helper_save);
6ae20372 3941 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 3942 break;
3943 case 0x3d: /* restore */
6ae20372 3944 save_state(dc, cpu_cond);
72a9747b 3945 tcg_gen_helper_0_0(helper_restore);
6ae20372 3946 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a 3947 break;
3475187d 3948#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
0f8a249a
BS		 3949 case 0x3e: /* V9 done/retry */
3950 {
3951 switch (rd) {
3952 case 0:
3953 if (!supervisor(dc))
3954 goto priv_insn;
3955 dc->npc = DYNAMIC_PC;
3956 dc->pc = DYNAMIC_PC;
1a2fb1c0 3957 tcg_gen_helper_0_0(helper_done);
0f8a249a
BS		 3958 goto jmp_insn;
3959 case 1:
3960 if (!supervisor(dc))
3961 goto priv_insn;
3962 dc->npc = DYNAMIC_PC;
3963 dc->pc = DYNAMIC_PC;
1a2fb1c0 3964 tcg_gen_helper_0_0(helper_retry);
0f8a249a
BS		 3965 goto jmp_insn;
3966 default:
3967 goto illegal_insn;
3968 }
3969 }
3970 break;
3971#endif
3972 default:
3973 goto illegal_insn;
3974 }
cf495bcf 3975 }
0f8a249a
BS		 3976 break;
3977 }
3978 break;
3979 case 3: /* load/store instructions */
3980 {
3981 unsigned int xop = GET_FIELD(insn, 7, 12);
9322a4bf 3982
6ae20372 3983 save_state(dc, cpu_cond);
9322a4bf 3984 cpu_src1 = get_src1(insn, cpu_src1);
81ad8ba2
BS		 3985 if (xop == 0x3c || xop == 0x3e)
3986 {
3987 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 3988 gen_movl_reg_TN(rs2, cpu_src2);
81ad8ba2
BS		 3989 }
3990 else if (IS_IMM) { /* immediate */
0f8a249a 3991 rs2 = GET_FIELDs(insn, 19, 31);
6ae20372 3992 tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
0f8a249a
BS		 3993 } else { /* register */
3994 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 3995 if (rs2 != 0) {
6ae20372
BS		 3996 gen_movl_reg_TN(rs2, cpu_src2);
3997 tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
6f551262
BS		 3998 } else
3999 tcg_gen_mov_tl(cpu_addr, cpu_src1);
0f8a249a 4000 }
2f2ecb83
BS		 4001 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4002 (xop > 0x17 && xop <= 0x1d ) ||
4003 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
0f8a249a 4004 switch (xop) {
1a2fb1c0 4005 case 0x0: /* load unsigned word */
6ae20372
BS		 4006 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4007 ABI32_MASK(cpu_addr);
4008 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4009 break;
4010 case 0x1: /* load unsigned byte */
6ae20372
BS		 4011 ABI32_MASK(cpu_addr);
4012 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4013 break;
4014 case 0x2: /* load unsigned halfword */
6ae20372
BS		 4015 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4016 ABI32_MASK(cpu_addr);
4017 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4018 break;
4019 case 0x3: /* load double word */
0f8a249a 4020 if (rd & 1)
d4218d99 4021 goto illegal_insn;
1a2fb1c0 4022 else {
6ae20372
BS		 4023 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4024 ABI32_MASK(cpu_addr);
4025 tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
32b6c812
BS		 4026 tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4027 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4028 gen_movl_TN_reg(rd + 1, cpu_tmp0);
8911f501 4029 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
6ae20372
BS		 4030 tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4031 tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
1a2fb1c0 4032 }
0f8a249a
BS		 4033 break;
4034 case 0x9: /* load signed byte */
6ae20372
BS		 4035 ABI32_MASK(cpu_addr);
4036 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4037 break;
4038 case 0xa: /* load signed halfword */
6ae20372
BS		 4039 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4040 ABI32_MASK(cpu_addr);
4041 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4042 break;
4043 case 0xd: /* ldstub -- XXX: should be atomically */
6ae20372
BS		 4044 ABI32_MASK(cpu_addr);
4045 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4046 tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_addr, dc->mem_idx);
0f8a249a
BS		 4047 break;
4048 case 0x0f: /* swap register with memory. Also atomically */
6ae20372
BS		 4049 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4050 gen_movl_reg_TN(rd, cpu_val);
4051 ABI32_MASK(cpu_addr);
4052 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4053 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4054 tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
0f8a249a 4055 break;
3475187d 4056#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 4057 case 0x10: /* load word alternate */
3475187d 4058#ifndef TARGET_SPARC64
0f8a249a
BS		 4059 if (IS_IMM)
4060 goto illegal_insn;
4061 if (!supervisor(dc))
4062 goto priv_insn;
6ea4a6c8 4063#endif
6ae20372
BS		 4064 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4065 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
0f8a249a
BS		 4066 break;
4067 case 0x11: /* load unsigned byte alternate */
3475187d 4068#ifndef TARGET_SPARC64
0f8a249a
BS		 4069 if (IS_IMM)
4070 goto illegal_insn;
4071 if (!supervisor(dc))
4072 goto priv_insn;
4073#endif
6ae20372 4074 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
0f8a249a
BS		 4075 break;
4076 case 0x12: /* load unsigned halfword alternate */
3475187d 4077#ifndef TARGET_SPARC64
0f8a249a
BS		 4078 if (IS_IMM)
4079 goto illegal_insn;
4080 if (!supervisor(dc))
4081 goto priv_insn;
3475187d 4082#endif
6ae20372
BS		 4083 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4084 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
0f8a249a
BS		 4085 break;
4086 case 0x13: /* load double word alternate */
3475187d 4087#ifndef TARGET_SPARC64
0f8a249a
BS		 4088 if (IS_IMM)
4089 goto illegal_insn;
4090 if (!supervisor(dc))
4091 goto priv_insn;
3475187d 4092#endif
0f8a249a 4093 if (rd & 1)
d4218d99 4094 goto illegal_insn;
6ae20372
BS		 4095 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4096 gen_ldda_asi(cpu_tmp0, cpu_val, cpu_addr, insn);
32b6c812 4097 gen_movl_TN_reg(rd + 1, cpu_tmp0);
0f8a249a
BS		 4098 break;
4099 case 0x19: /* load signed byte alternate */
3475187d 4100#ifndef TARGET_SPARC64
0f8a249a
BS		 4101 if (IS_IMM)
4102 goto illegal_insn;
4103 if (!supervisor(dc))
4104 goto priv_insn;
4105#endif
6ae20372 4106 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
0f8a249a
BS		 4107 break;
4108 case 0x1a: /* load signed halfword alternate */
3475187d 4109#ifndef TARGET_SPARC64
0f8a249a
BS		 4110 if (IS_IMM)
4111 goto illegal_insn;
4112 if (!supervisor(dc))
4113 goto priv_insn;
3475187d 4114#endif
6ae20372
BS		 4115 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4116 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
0f8a249a
BS		 4117 break;
4118 case 0x1d: /* ldstuba -- XXX: should be atomically */
3475187d 4119#ifndef TARGET_SPARC64
0f8a249a
BS		 4120 if (IS_IMM)
4121 goto illegal_insn;
4122 if (!supervisor(dc))
4123 goto priv_insn;
4124#endif
6ae20372 4125 gen_ldstub_asi(cpu_val, cpu_addr, insn);
0f8a249a
BS		 4126 break;
4127 case 0x1f: /* swap reg with alt. memory. Also atomically */
3475187d 4128#ifndef TARGET_SPARC64
0f8a249a
BS		 4129 if (IS_IMM)
4130 goto illegal_insn;
4131 if (!supervisor(dc))
4132 goto priv_insn;
6ea4a6c8 4133#endif
6ae20372
BS		 4134 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4135 gen_movl_reg_TN(rd, cpu_val);
4136 gen_swap_asi(cpu_val, cpu_addr, insn);
0f8a249a 4137 break;
3475187d
FB		 4138
4139#ifndef TARGET_SPARC64
0f8a249a
BS		 4140 case 0x30: /* ldc */
4141 case 0x31: /* ldcsr */
4142 case 0x33: /* lddc */
4143 goto ncp_insn;
3475187d
FB		 4144#endif
4145#endif
4146#ifdef TARGET_SPARC64
0f8a249a 4147 case 0x08: /* V9 ldsw */
6ae20372
BS		 4148 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4149 ABI32_MASK(cpu_addr);
4150 tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4151 break;
4152 case 0x0b: /* V9 ldx */
6ae20372
BS		 4153 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4154 ABI32_MASK(cpu_addr);
4155 tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4156 break;
4157 case 0x18: /* V9 ldswa */
6ae20372
BS		 4158 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4159 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
0f8a249a
BS		 4160 break;
4161 case 0x1b: /* V9 ldxa */
6ae20372
BS		 4162 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4163 gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
0f8a249a
BS		 4164 break;
4165 case 0x2d: /* V9 prefetch, no effect */
4166 goto skip_move;
4167 case 0x30: /* V9 ldfa */
6ae20372
BS		 4168 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4169 gen_ldf_asi(cpu_addr, insn, 4, rd);
81ad8ba2 4170 goto skip_move;
0f8a249a 4171 case 0x33: /* V9 lddfa */
6ae20372
BS		 4172 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4173 gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
81ad8ba2 4174 goto skip_move;
0f8a249a
BS		 4175 case 0x3d: /* V9 prefetcha, no effect */
4176 goto skip_move;
4177 case 0x32: /* V9 ldqfa */
1f587329 4178#if defined(CONFIG_USER_ONLY)
6ae20372
BS		 4179 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4180 gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
1f587329
BS		 4181 goto skip_move;
4182#else
0f8a249a 4183 goto nfpu_insn;
1f587329 4184#endif
0f8a249a
BS		 4185#endif
4186 default:
4187 goto illegal_insn;
4188 }
6ae20372 4189 gen_movl_TN_reg(rd, cpu_val);
3475187d 4190#ifdef TARGET_SPARC64
0f8a249a 4191 skip_move: ;
3475187d 4192#endif
0f8a249a 4193 } else if (xop >= 0x20 && xop < 0x24) {
6ae20372 4194 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 4195 goto jmp_insn;
0f8a249a
BS		 4196 switch (xop) {
4197 case 0x20: /* load fpreg */
6ae20372
BS		 4198 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4199 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
ce8536e2
BS		 4200 tcg_gen_st_i32(cpu_tmp32, cpu_env,
4201 offsetof(CPUState, fpr[rd]));
0f8a249a
BS		 4202 break;
4203 case 0x21: /* load fsr */
6ae20372
BS		 4204 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4205 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
ce8536e2
BS		 4206 tcg_gen_st_i32(cpu_tmp32, cpu_env,
4207 offsetof(CPUState, ft0));
7e8c2b6c 4208 tcg_gen_helper_0_0(helper_ldfsr);
0f8a249a
BS		 4209 break;
4210 case 0x22: /* load quad fpreg */
1f587329 4211#if defined(CONFIG_USER_ONLY)
6ae20372 4212 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
1f587329
BS		 4213 gen_op_ldst(ldqf);
4214 gen_op_store_QT0_fpr(QFPREG(rd));
4215 break;
4216#else
0f8a249a 4217 goto nfpu_insn;
1f587329 4218#endif
0f8a249a 4219 case 0x23: /* load double fpreg */
6ae20372 4220 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
0f8a249a
BS		 4221 gen_op_ldst(lddf);
4222 gen_op_store_DT0_fpr(DFPREG(rd));
4223 break;
4224 default:
4225 goto illegal_insn;
4226 }
4227 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4228 xop == 0xe || xop == 0x1e) {
6ae20372 4229 gen_movl_reg_TN(rd, cpu_val);
0f8a249a 4230 switch (xop) {
1a2fb1c0 4231 case 0x4: /* store word */
6ae20372
BS		 4232 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4233 ABI32_MASK(cpu_addr);
4234 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4235 break;
1a2fb1c0 4236 case 0x5: /* store byte */
6ae20372
BS		 4237 ABI32_MASK(cpu_addr);
4238 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4239 break;
1a2fb1c0 4240 case 0x6: /* store halfword */
6ae20372
BS		 4241 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4242 ABI32_MASK(cpu_addr);
4243 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4244 break;
1a2fb1c0 4245 case 0x7: /* store double word */
0f8a249a 4246 if (rd & 1)
d4218d99 4247 goto illegal_insn;
b25deda7 4248#ifndef __i386__
1a2fb1c0 4249 else {
8911f501 4250 TCGv r_low;
1a2fb1c0 4251
6ae20372 4252 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
1a2fb1c0
BS		 4253 r_low = tcg_temp_new(TCG_TYPE_I32);
4254 gen_movl_reg_TN(rd + 1, r_low);
6ae20372 4255 tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
1a2fb1c0 4256 r_low);
6ae20372 4257 tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
1a2fb1c0 4258 }
b25deda7 4259#else /* __i386__ */
6ae20372
BS		 4260 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4261 flush_cond(dc, cpu_cond);
4262 gen_movl_reg_TN(rd + 1, cpu_cond);
b25deda7
BS		 4263 gen_op_ldst(std);
4264#endif /* __i386__ */
0f8a249a 4265 break;
3475187d 4266#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1a2fb1c0 4267 case 0x14: /* store word alternate */
3475187d 4268#ifndef TARGET_SPARC64
0f8a249a
BS		 4269 if (IS_IMM)
4270 goto illegal_insn;
4271 if (!supervisor(dc))
4272 goto priv_insn;
6ea4a6c8 4273#endif
6ae20372
BS		 4274 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4275 gen_st_asi(cpu_val, cpu_addr, insn, 4);
d39c0b99 4276 break;
1a2fb1c0 4277 case 0x15: /* store byte alternate */
3475187d 4278#ifndef TARGET_SPARC64
0f8a249a
BS		 4279 if (IS_IMM)
4280 goto illegal_insn;
4281 if (!supervisor(dc))
4282 goto priv_insn;
3475187d 4283#endif
6ae20372 4284 gen_st_asi(cpu_val, cpu_addr, insn, 1);
d39c0b99 4285 break;
1a2fb1c0 4286 case 0x16: /* store halfword alternate */
3475187d 4287#ifndef TARGET_SPARC64
0f8a249a
BS		 4288 if (IS_IMM)
4289 goto illegal_insn;
4290 if (!supervisor(dc))
4291 goto priv_insn;
6ea4a6c8 4292#endif
6ae20372
BS		 4293 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4294 gen_st_asi(cpu_val, cpu_addr, insn, 2);
d39c0b99 4295 break;
1a2fb1c0 4296 case 0x17: /* store double word alternate */
3475187d 4297#ifndef TARGET_SPARC64
0f8a249a
BS		 4298 if (IS_IMM)
4299 goto illegal_insn;
4300 if (!supervisor(dc))
4301 goto priv_insn;
3475187d 4302#endif
0f8a249a 4303 if (rd & 1)
d4218d99 4304 goto illegal_insn;
1a2fb1c0 4305 else {
6ae20372
BS		 4306 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4307 gen_stda_asi(cpu_val, cpu_addr, insn, rd);
1a2fb1c0 4308 }
d39c0b99 4309 break;
e80cfcfc 4310#endif
3475187d 4311#ifdef TARGET_SPARC64
0f8a249a 4312 case 0x0e: /* V9 stx */
6ae20372
BS		 4313 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4314 ABI32_MASK(cpu_addr);
4315 tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4316 break;
4317 case 0x1e: /* V9 stxa */
6ae20372
BS		 4318 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4319 gen_st_asi(cpu_val, cpu_addr, insn, 8);
0f8a249a 4320 break;
3475187d 4321#endif
0f8a249a
BS		 4322 default:
4323 goto illegal_insn;
4324 }
4325 } else if (xop > 0x23 && xop < 0x28) {
6ae20372 4326 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 4327 goto jmp_insn;
0f8a249a 4328 switch (xop) {
ce8536e2 4329 case 0x24: /* store fpreg */
6ae20372 4330 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
ce8536e2
BS		 4331 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4332 offsetof(CPUState, fpr[rd]));
6ae20372 4333 tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4334 break;
4335 case 0x25: /* stfsr, V9 stxfsr */
6ea4a6c8 4336#ifdef CONFIG_USER_ONLY
6ae20372 4337 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
6ea4a6c8 4338#endif
bb5529bb 4339 tcg_gen_helper_0_0(helper_stfsr);
ce8536e2
BS		 4340 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4341 offsetof(CPUState, ft0));
6ae20372 4342 tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
0f8a249a 4343 break;
1f587329
BS		 4344 case 0x26:
4345#ifdef TARGET_SPARC64
4346#if defined(CONFIG_USER_ONLY)
4347 /* V9 stqf, store quad fpreg */
6ae20372 4348 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
1f587329
BS		 4349 gen_op_load_fpr_QT0(QFPREG(rd));
4350 gen_op_ldst(stqf);
4351 break;
4352#else
4353 goto nfpu_insn;
4354#endif
4355#else /* !TARGET_SPARC64 */
4356 /* stdfq, store floating point queue */
4357#if defined(CONFIG_USER_ONLY)
4358 goto illegal_insn;
4359#else
0f8a249a
BS		 4360 if (!supervisor(dc))
4361 goto priv_insn;
6ae20372 4362 if (gen_trap_ifnofpu(dc, cpu_cond))
0f8a249a
BS		 4363 goto jmp_insn;
4364 goto nfq_insn;
1f587329 4365#endif
0f8a249a
BS		 4366#endif
4367 case 0x27:
6ae20372 4368 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
3475187d 4369 gen_op_load_fpr_DT0(DFPREG(rd));
0f8a249a
BS		 4370 gen_op_ldst(stdf);
4371 break;
4372 default:
4373 goto illegal_insn;
4374 }
4375 } else if (xop > 0x33 && xop < 0x3f) {
4376 switch (xop) {
a4d17f19 4377#ifdef TARGET_SPARC64
0f8a249a 4378 case 0x34: /* V9 stfa */
6ae20372 4379 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
3391c818 4380 gen_op_load_fpr_FT0(rd);
6ae20372 4381 gen_stf_asi(cpu_addr, insn, 4, rd);
0f8a249a 4382 break;
1f587329
BS		 4383 case 0x36: /* V9 stqfa */
4384#if defined(CONFIG_USER_ONLY)
6ae20372 4385 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
1f587329 4386 gen_op_load_fpr_QT0(QFPREG(rd));
6ae20372 4387 gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
1f587329
BS		 4388 break;
4389#else
4390 goto nfpu_insn;
4391#endif
0f8a249a 4392 case 0x37: /* V9 stdfa */
6ae20372 4393 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
3391c818 4394 gen_op_load_fpr_DT0(DFPREG(rd));
6ae20372 4395 gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
0f8a249a
BS		 4396 break;
4397 case 0x3c: /* V9 casa */
6ae20372
BS		 4398 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4399 gen_cas_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4400 gen_movl_TN_reg(rd, cpu_val);
0f8a249a
BS		 4401 break;
4402 case 0x3e: /* V9 casxa */
6ae20372
BS		 4403 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4404 gen_casx_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4405 gen_movl_TN_reg(rd, cpu_val);
0f8a249a 4406 break;
a4d17f19 4407#else
0f8a249a
BS		 4408 case 0x34: /* stc */
4409 case 0x35: /* stcsr */
4410 case 0x36: /* stdcq */
4411 case 0x37: /* stdc */
4412 goto ncp_insn;
4413#endif
4414 default:
4415 goto illegal_insn;
4416 }
e8af50a3 4417 }
0f8a249a
BS		 4418 else
4419 goto illegal_insn;
4420 }
4421 break;
cf495bcf
FB		 4422 }
4423 /* default case for non jump instructions */
72cbca10 4424 if (dc->npc == DYNAMIC_PC) {
0f8a249a
BS		 4425 dc->pc = DYNAMIC_PC;
4426 gen_op_next_insn();
72cbca10
FB		 4427 } else if (dc->npc == JUMP_PC) {
4428 /* we can do a static jump */
6ae20372 4429 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
72cbca10
FB		 4430 dc->is_br = 1;
4431 } else {
0f8a249a
BS		 4432 dc->pc = dc->npc;
4433 dc->npc = dc->npc + 4;
cf495bcf 4434 }
e80cfcfc 4435 jmp_insn:
cf495bcf
FB		 4436 return;
4437 illegal_insn:
6ae20372 4438 save_state(dc, cpu_cond);
2f5680ee 4439 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_ILL_INSN));
cf495bcf 4440 dc->is_br = 1;
e8af50a3 4441 return;
e80cfcfc 4442#if !defined(CONFIG_USER_ONLY)
e8af50a3 4443 priv_insn:
6ae20372 4444 save_state(dc, cpu_cond);
2f5680ee 4445 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_PRIV_INSN));
e8af50a3 4446 dc->is_br = 1;
e80cfcfc 4447 return;
e80cfcfc 4448 nfpu_insn:
6ae20372 4449 save_state(dc, cpu_cond);
e80cfcfc
FB		 4450 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4451 dc->is_br = 1;
fcc72045 4452 return;
1f587329 4453#ifndef TARGET_SPARC64
9143e598 4454 nfq_insn:
6ae20372 4455 save_state(dc, cpu_cond);
9143e598
BS		 4456 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4457 dc->is_br = 1;
4458 return;
4459#endif
1f587329 4460#endif
fcc72045
BS		 4461#ifndef TARGET_SPARC64
4462 ncp_insn:
6ae20372 4463 save_state(dc, cpu_cond);
2f5680ee 4464 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NCP_INSN));
fcc72045
BS		 4465 dc->is_br = 1;
4466 return;
4467#endif
7a3f1944
FB		 4468}
4469
1a2fb1c0
BS		 4470static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
4471{
4472}
4473
cf495bcf 4474static inline int gen_intermediate_code_internal(TranslationBlock * tb,
0f8a249a 4475 int spc, CPUSPARCState *env)
7a3f1944 4476{
72cbca10 4477 target_ulong pc_start, last_pc;
cf495bcf
FB		 4478 uint16_t *gen_opc_end;
4479 DisasContext dc1, *dc = &dc1;
e8af50a3 4480 int j, lj = -1;
cf495bcf
FB		 4481
4482 memset(dc, 0, sizeof(DisasContext));
cf495bcf 4483 dc->tb = tb;
72cbca10 4484 pc_start = tb->pc;
cf495bcf 4485 dc->pc = pc_start;
e80cfcfc 4486 last_pc = dc->pc;
72cbca10 4487 dc->npc = (target_ulong) tb->cs_base;
6f27aba6
BS		 4488 dc->mem_idx = cpu_mmu_index(env);
4489 dc->fpu_enabled = cpu_fpu_enabled(env);
cf495bcf 4490 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
cf495bcf 4491
1a2fb1c0 4492 cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
8911f501
BS		 4493 cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4494 cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
1a2fb1c0 4495
6ae20372
BS		 4496 cpu_cond = cpu_T[2];
4497
cf495bcf 4498 do {
e8af50a3
FB		 4499 if (env->nb_breakpoints > 0) {
4500 for(j = 0; j < env->nb_breakpoints; j++) {
4501 if (env->breakpoints[j] == dc->pc) {
0f8a249a 4502 if (dc->pc != pc_start)
6ae20372 4503 save_state(dc, cpu_cond);
1a2fb1c0 4504 tcg_gen_helper_0_0(helper_debug);
57fec1fe 4505 tcg_gen_exit_tb(0);
0f8a249a 4506 dc->is_br = 1;
e80cfcfc 4507 goto exit_gen_loop;
e8af50a3
FB		 4508 }
4509 }
4510 }
4511 if (spc) {
4512 if (loglevel > 0)
4513 fprintf(logfile, "Search PC...\n");
4514 j = gen_opc_ptr - gen_opc_buf;
4515 if (lj < j) {
4516 lj++;
4517 while (lj < j)
4518 gen_opc_instr_start[lj++] = 0;
4519 gen_opc_pc[lj] = dc->pc;
4520 gen_opc_npc[lj] = dc->npc;
4521 gen_opc_instr_start[lj] = 1;
4522 }
4523 }
0f8a249a
BS		 4524 last_pc = dc->pc;
4525 disas_sparc_insn(dc);
4526
4527 if (dc->is_br)
4528 break;
4529 /* if the next PC is different, we abort now */
4530 if (dc->pc != (last_pc + 4))
4531 break;
d39c0b99
FB		 4532 /* if we reach a page boundary, we stop generation so that the
4533 PC of a TT_TFAULT exception is always in the right page */
4534 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4535 break;
e80cfcfc
FB		 4536 /* if single step mode, we generate only one instruction and
4537 generate an exception */
4538 if (env->singlestep_enabled) {
2f5680ee 4539 tcg_gen_movi_tl(cpu_pc, dc->pc);
57fec1fe 4540 tcg_gen_exit_tb(0);
e80cfcfc
FB		 4541 break;
4542 }
cf495bcf 4543 } while ((gen_opc_ptr < gen_opc_end) &&
0f8a249a 4544 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
e80cfcfc
FB		 4545
4546 exit_gen_loop:
72cbca10 4547 if (!dc->is_br) {
5fafdf24 4548 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 4549 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4550 /* static PC and NPC: we can use direct chaining */
2f5680ee 4551 gen_goto_tb(dc, 0, dc->pc, dc->npc);
72cbca10
FB		 4552 } else {
4553 if (dc->pc != DYNAMIC_PC)
2f5680ee 4554 tcg_gen_movi_tl(cpu_pc, dc->pc);
6ae20372 4555 save_npc(dc, cpu_cond);
57fec1fe 4556 tcg_gen_exit_tb(0);
72cbca10
FB		 4557 }
4558 }
cf495bcf 4559 *gen_opc_ptr = INDEX_op_end;
e8af50a3
FB		 4560 if (spc) {
4561 j = gen_opc_ptr - gen_opc_buf;
4562 lj++;
4563 while (lj <= j)
4564 gen_opc_instr_start[lj++] = 0;
e8af50a3
FB		 4565#if 0
4566 if (loglevel > 0) {
4567 page_dump(logfile);
4568 }
4569#endif
c3278b7b
FB		 4570 gen_opc_jump_pc[0] = dc->jump_pc[0];
4571 gen_opc_jump_pc[1] = dc->jump_pc[1];
e8af50a3 4572 } else {
e80cfcfc 4573 tb->size = last_pc + 4 - pc_start;
e8af50a3 4574 }
7a3f1944 4575#ifdef DEBUG_DISAS
e19e89a5 4576 if (loglevel & CPU_LOG_TB_IN_ASM) {
0f8a249a
BS		 4577 fprintf(logfile, "--------------\n");
4578 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4579 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4580 fprintf(logfile, "\n");
cf495bcf 4581 }
7a3f1944 4582#endif
cf495bcf 4583 return 0;
7a3f1944
FB		 4584}
4585
cf495bcf 4586int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 4587{
e8af50a3 4588 return gen_intermediate_code_internal(tb, 0, env);
7a3f1944
FB		 4589}
4590
cf495bcf 4591int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 4592{
e8af50a3 4593 return gen_intermediate_code_internal(tb, 1, env);
7a3f1944
FB		 4594}
4595
c48fcb47 4596void gen_intermediate_code_init(CPUSPARCState *env)
e80cfcfc 4597{
f5069b26 4598 unsigned int i;
c48fcb47 4599 static int inited;
f5069b26
BS		 4600 static const char * const gregnames[8] = {
4601 NULL, // g0 not used
4602 "g1",
4603 "g2",
4604 "g3",
4605 "g4",
4606 "g5",
4607 "g6",
4608 "g7",
4609 };
aaed909a 4610
1a2fb1c0
BS		 4611 /* init various static tables */
4612 if (!inited) {
4613 inited = 1;
4614
4615 tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
4616 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
db4a4ea4
BS		 4617 cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4618 offsetof(CPUState, regwptr),
4619 "regwptr");
1a2fb1c0
BS		 4620 //#if TARGET_LONG_BITS > HOST_LONG_BITS
4621#ifdef TARGET_SPARC64
4622 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
4623 TCG_AREG0, offsetof(CPUState, t0), "T0");
4624 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
4625 TCG_AREG0, offsetof(CPUState, t1), "T1");
4626 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
4627 TCG_AREG0, offsetof(CPUState, t2), "T2");
dc99a3f2
BS		 4628 cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4629 TCG_AREG0, offsetof(CPUState, xcc),
4630 "xcc");
1a2fb1c0
BS		 4631#else
4632 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
4633 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
4634 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
4635#endif
dc99a3f2
BS		 4636 cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4637 TCG_AREG0, offsetof(CPUState, cc_src),
4638 "cc_src");
d9bdab86
BS		 4639 cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4640 offsetof(CPUState, cc_src2),
4641 "cc_src2");
dc99a3f2
BS		 4642 cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4643 TCG_AREG0, offsetof(CPUState, cc_dst),
4644 "cc_dst");
4645 cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4646 TCG_AREG0, offsetof(CPUState, psr),
4647 "psr");
87e92502
BS		 4648 cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4649 TCG_AREG0, offsetof(CPUState, fsr),
4650 "fsr");
48d5c82b
BS		 4651 cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,
4652 TCG_AREG0, offsetof(CPUState, pc),
4653 "pc");
4654 cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
4655 TCG_AREG0, offsetof(CPUState, npc),
4656 "npc");
f5069b26
BS		 4657 for (i = 1; i < 8; i++)
4658 cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4659 offsetof(CPUState, gregs[i]),
4660 gregnames[i]);
1a2fb1c0 4661 }
658138bc 4662}
d2856f1a
AJ		 4663
4664void gen_pc_load(CPUState *env, TranslationBlock *tb,
4665 unsigned long searched_pc, int pc_pos, void *puc)
4666{
4667 target_ulong npc;
4668 env->pc = gen_opc_pc[pc_pos];
4669 npc = gen_opc_npc[pc_pos];
4670 if (npc == 1) {
4671 /* dynamic NPC: already stored */
4672 } else if (npc == 2) {
4673 target_ulong t2 = (target_ulong)(unsigned long)puc;
4674 /* jump PC: use T2 and the jump targets of the translation */
4675 if (t2)
4676 env->npc = gen_opc_jump_pc[0];
4677 else
4678 env->npc = gen_opc_jump_pc[1];
4679 } else {
4680 env->npc = npc;
4681 }
4682}
Qemu copy for testing