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Commit | Line | Data |
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7a3f1944 FB |
1 | /* |
2 | SPARC translation | |
3 | ||
4 | Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at> | |
3475187d | 5 | Copyright (C) 2003-2005 Fabrice Bellard |
7a3f1944 FB |
6 | |
7 | This library is free software; you can redistribute it and/or | |
8 | modify it under the terms of the GNU Lesser General Public | |
9 | License as published by the Free Software Foundation; either | |
10 | version 2 of the License, or (at your option) any later version. | |
11 | ||
12 | This library is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | Lesser General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU Lesser General Public | |
18 | License along with this library; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | /* | |
7a3f1944 FB |
23 | TODO-list: |
24 | ||
3475187d | 25 | Rest of V9 instructions, VIS instructions |
bd497938 | 26 | NPC/PC static optimisations (use JUMP_TB when possible) |
7a3f1944 | 27 | Optimize synthetic instructions |
bd497938 | 28 | */ |
7a3f1944 FB |
29 | |
30 | #include <stdarg.h> | |
31 | #include <stdlib.h> | |
32 | #include <stdio.h> | |
33 | #include <string.h> | |
34 | #include <inttypes.h> | |
35 | ||
36 | #include "cpu.h" | |
37 | #include "exec-all.h" | |
38 | #include "disas.h" | |
1a2fb1c0 | 39 | #include "helper.h" |
57fec1fe | 40 | #include "tcg-op.h" |
7a3f1944 FB |
41 | |
42 | #define DEBUG_DISAS | |
43 | ||
72cbca10 FB |
44 | #define DYNAMIC_PC 1 /* dynamic pc value */ |
45 | #define JUMP_PC 2 /* dynamic pc value which takes only two values | |
46 | according to jump_pc[T2] */ | |
47 | ||
1a2fb1c0 | 48 | /* global register indexes */ |
d9bdab86 | 49 | static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_src2, cpu_cc_dst; |
48d5c82b | 50 | static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; |
dc99a3f2 BS |
51 | #ifdef TARGET_SPARC64 |
52 | static TCGv cpu_xcc; | |
53 | #endif | |
1a2fb1c0 BS |
54 | /* local register indexes (only used inside old micro ops) */ |
55 | static TCGv cpu_tmp0; | |
56 | ||
7a3f1944 | 57 | typedef struct DisasContext { |
0f8a249a BS |
58 | target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */ |
59 | target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */ | |
72cbca10 | 60 | target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ |
cf495bcf | 61 | int is_br; |
e8af50a3 | 62 | int mem_idx; |
a80dde08 | 63 | int fpu_enabled; |
cf495bcf | 64 | struct TranslationBlock *tb; |
7a3f1944 FB |
65 | } DisasContext; |
66 | ||
aaed909a FB |
67 | typedef struct sparc_def_t sparc_def_t; |
68 | ||
62724a37 BS |
69 | struct sparc_def_t { |
70 | const unsigned char *name; | |
71 | target_ulong iu_version; | |
72 | uint32_t fpu_version; | |
73 | uint32_t mmu_version; | |
6d5f237a | 74 | uint32_t mmu_bm; |
3deaeab7 BS |
75 | uint32_t mmu_ctpr_mask; |
76 | uint32_t mmu_cxr_mask; | |
77 | uint32_t mmu_sfsr_mask; | |
78 | uint32_t mmu_trcr_mask; | |
62724a37 BS |
79 | }; |
80 | ||
aaed909a FB |
81 | static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name); |
82 | ||
7a3f1944 FB |
83 | extern FILE *logfile; |
84 | extern int loglevel; | |
85 | ||
3475187d | 86 | // This function uses non-native bit order |
7a3f1944 FB |
87 | #define GET_FIELD(X, FROM, TO) \ |
88 | ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) | |
89 | ||
3475187d FB |
90 | // This function uses the order in the manuals, i.e. bit 0 is 2^0 |
91 | #define GET_FIELD_SP(X, FROM, TO) \ | |
92 | GET_FIELD(X, 31 - (TO), 31 - (FROM)) | |
93 | ||
94 | #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) | |
46d38ba8 | 95 | #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1)) |
3475187d FB |
96 | |
97 | #ifdef TARGET_SPARC64 | |
19f329ad | 98 | #define FFPREG(r) (r) |
0387d928 | 99 | #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e)) |
1f587329 | 100 | #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c)) |
3475187d | 101 | #else |
19f329ad | 102 | #define FFPREG(r) (r) |
c185970a | 103 | #define DFPREG(r) (r & 0x1e) |
1f587329 | 104 | #define QFPREG(r) (r & 0x1c) |
3475187d FB |
105 | #endif |
106 | ||
107 | static int sign_extend(int x, int len) | |
108 | { | |
109 | len = 32 - len; | |
110 | return (x << len) >> len; | |
111 | } | |
112 | ||
7a3f1944 FB |
113 | #define IS_IMM (insn & (1<<13)) |
114 | ||
cf495bcf | 115 | static void disas_sparc_insn(DisasContext * dc); |
7a3f1944 | 116 | |
ff07ec83 BS |
117 | /* floating point registers moves */ |
118 | static void gen_op_load_fpr_FT0(unsigned int src) | |
119 | { | |
120 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src])); | |
121 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, ft0)); | |
3475187d | 122 | } |
ff07ec83 BS |
123 | |
124 | static void gen_op_load_fpr_FT1(unsigned int src) | |
125 | { | |
126 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src])); | |
127 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, ft1)); | |
e8af50a3 FB |
128 | } |
129 | ||
ff07ec83 BS |
130 | static void gen_op_store_FT0_fpr(unsigned int dst) |
131 | { | |
132 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, ft0)); | |
133 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst])); | |
134 | } | |
135 | ||
136 | static void gen_op_load_fpr_DT0(unsigned int src) | |
137 | { | |
138 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src])); | |
139 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper)); | |
140 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1])); | |
141 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower)); | |
142 | } | |
143 | ||
144 | static void gen_op_load_fpr_DT1(unsigned int src) | |
145 | { | |
146 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src])); | |
147 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.upper)); | |
148 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1])); | |
149 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.lower)); | |
150 | } | |
151 | ||
152 | static void gen_op_store_DT0_fpr(unsigned int dst) | |
153 | { | |
154 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper)); | |
155 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst])); | |
156 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower)); | |
157 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1])); | |
158 | } | |
159 | ||
160 | #ifdef CONFIG_USER_ONLY | |
161 | static void gen_op_load_fpr_QT0(unsigned int src) | |
162 | { | |
163 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src])); | |
164 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost)); | |
165 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1])); | |
166 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper)); | |
167 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 2])); | |
168 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower)); | |
169 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 3])); | |
170 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest)); | |
171 | } | |
172 | ||
173 | static void gen_op_load_fpr_QT1(unsigned int src) | |
174 | { | |
175 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src])); | |
176 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost)); | |
177 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1])); | |
178 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper)); | |
179 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 2])); | |
180 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower)); | |
181 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 3])); | |
182 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest)); | |
183 | } | |
184 | ||
185 | static void gen_op_store_QT0_fpr(unsigned int dst) | |
186 | { | |
187 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost)); | |
188 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst])); | |
189 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper)); | |
190 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1])); | |
191 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower)); | |
192 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2])); | |
193 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest)); | |
194 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3])); | |
195 | } | |
1f587329 BS |
196 | #endif |
197 | ||
81ad8ba2 BS |
198 | /* moves */ |
199 | #ifdef CONFIG_USER_ONLY | |
3475187d | 200 | #define supervisor(dc) 0 |
81ad8ba2 | 201 | #ifdef TARGET_SPARC64 |
e9ebed4d | 202 | #define hypervisor(dc) 0 |
81ad8ba2 | 203 | #endif |
3475187d | 204 | #define gen_op_ldst(name) gen_op_##name##_raw() |
3475187d | 205 | #else |
6f27aba6 | 206 | #define supervisor(dc) (dc->mem_idx >= 1) |
81ad8ba2 BS |
207 | #ifdef TARGET_SPARC64 |
208 | #define hypervisor(dc) (dc->mem_idx == 2) | |
6f27aba6 BS |
209 | #define OP_LD_TABLE(width) \ |
210 | static GenOpFunc * const gen_op_##width[] = { \ | |
211 | &gen_op_##width##_user, \ | |
212 | &gen_op_##width##_kernel, \ | |
213 | &gen_op_##width##_hypv, \ | |
214 | }; | |
215 | #else | |
0f8a249a | 216 | #define OP_LD_TABLE(width) \ |
a68156d0 | 217 | static GenOpFunc * const gen_op_##width[] = { \ |
0f8a249a BS |
218 | &gen_op_##width##_user, \ |
219 | &gen_op_##width##_kernel, \ | |
81ad8ba2 | 220 | }; |
3475187d | 221 | #endif |
6f27aba6 BS |
222 | #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])() |
223 | #endif | |
e8af50a3 | 224 | |
81ad8ba2 | 225 | #ifndef CONFIG_USER_ONLY |
b25deda7 BS |
226 | #ifdef __i386__ |
227 | OP_LD_TABLE(std); | |
228 | #endif /* __i386__ */ | |
e8af50a3 FB |
229 | OP_LD_TABLE(stf); |
230 | OP_LD_TABLE(stdf); | |
231 | OP_LD_TABLE(ldf); | |
232 | OP_LD_TABLE(lddf); | |
81ad8ba2 BS |
233 | #endif |
234 | ||
1a2fb1c0 BS |
235 | #ifdef TARGET_ABI32 |
236 | #define ABI32_MASK(addr) tcg_gen_andi_i64(addr, addr, 0xffffffffULL); | |
237 | #else | |
238 | #define ABI32_MASK(addr) | |
239 | #endif | |
3391c818 | 240 | |
1a2fb1c0 | 241 | static inline void gen_movl_simm_T1(int32_t val) |
81ad8ba2 | 242 | { |
1a2fb1c0 | 243 | tcg_gen_movi_tl(cpu_T[1], val); |
81ad8ba2 BS |
244 | } |
245 | ||
1a2fb1c0 | 246 | static inline void gen_movl_reg_TN(int reg, TCGv tn) |
81ad8ba2 | 247 | { |
1a2fb1c0 BS |
248 | if (reg == 0) |
249 | tcg_gen_movi_tl(tn, 0); | |
250 | else if (reg < 8) | |
f5069b26 | 251 | tcg_gen_mov_tl(tn, cpu_gregs[reg]); |
1a2fb1c0 | 252 | else { |
1a2fb1c0 | 253 | tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
81ad8ba2 BS |
254 | } |
255 | } | |
256 | ||
1a2fb1c0 | 257 | static inline void gen_movl_reg_T0(int reg) |
81ad8ba2 | 258 | { |
1a2fb1c0 | 259 | gen_movl_reg_TN(reg, cpu_T[0]); |
81ad8ba2 BS |
260 | } |
261 | ||
1a2fb1c0 | 262 | static inline void gen_movl_reg_T1(int reg) |
81ad8ba2 | 263 | { |
1a2fb1c0 | 264 | gen_movl_reg_TN(reg, cpu_T[1]); |
81ad8ba2 BS |
265 | } |
266 | ||
b25deda7 BS |
267 | #ifdef __i386__ |
268 | static inline void gen_movl_reg_T2(int reg) | |
269 | { | |
270 | gen_movl_reg_TN(reg, cpu_T[2]); | |
271 | } | |
272 | ||
273 | #endif /* __i386__ */ | |
1a2fb1c0 | 274 | static inline void gen_movl_TN_reg(int reg, TCGv tn) |
81ad8ba2 | 275 | { |
1a2fb1c0 BS |
276 | if (reg == 0) |
277 | return; | |
278 | else if (reg < 8) | |
f5069b26 | 279 | tcg_gen_mov_tl(cpu_gregs[reg], tn); |
1a2fb1c0 | 280 | else { |
1a2fb1c0 | 281 | tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
81ad8ba2 BS |
282 | } |
283 | } | |
284 | ||
1a2fb1c0 | 285 | static inline void gen_movl_T0_reg(int reg) |
3475187d | 286 | { |
1a2fb1c0 | 287 | gen_movl_TN_reg(reg, cpu_T[0]); |
3475187d FB |
288 | } |
289 | ||
1a2fb1c0 | 290 | static inline void gen_movl_T1_reg(int reg) |
3475187d | 291 | { |
1a2fb1c0 | 292 | gen_movl_TN_reg(reg, cpu_T[1]); |
3475187d FB |
293 | } |
294 | ||
1a2fb1c0 | 295 | static inline void gen_op_movl_T0_env(size_t offset) |
7a3f1944 | 296 | { |
1a2fb1c0 | 297 | tcg_gen_ld_i32(cpu_T[0], cpu_env, offset); |
7a3f1944 FB |
298 | } |
299 | ||
1a2fb1c0 | 300 | static inline void gen_op_movl_env_T0(size_t offset) |
7a3f1944 | 301 | { |
1a2fb1c0 | 302 | tcg_gen_st_i32(cpu_T[0], cpu_env, offset); |
7a3f1944 FB |
303 | } |
304 | ||
1a2fb1c0 | 305 | static inline void gen_op_movtl_T0_env(size_t offset) |
7a3f1944 | 306 | { |
1a2fb1c0 | 307 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offset); |
7a3f1944 FB |
308 | } |
309 | ||
1a2fb1c0 | 310 | static inline void gen_op_movtl_env_T0(size_t offset) |
7a3f1944 | 311 | { |
1a2fb1c0 | 312 | tcg_gen_st_tl(cpu_T[0], cpu_env, offset); |
7a3f1944 FB |
313 | } |
314 | ||
1a2fb1c0 | 315 | static inline void gen_op_add_T1_T0(void) |
7a3f1944 | 316 | { |
1a2fb1c0 | 317 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
7a3f1944 FB |
318 | } |
319 | ||
1a2fb1c0 | 320 | static inline void gen_op_or_T1_T0(void) |
7a3f1944 | 321 | { |
1a2fb1c0 | 322 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
7a3f1944 FB |
323 | } |
324 | ||
1a2fb1c0 | 325 | static inline void gen_op_xor_T1_T0(void) |
7a3f1944 | 326 | { |
1a2fb1c0 | 327 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
7a3f1944 FB |
328 | } |
329 | ||
3475187d FB |
330 | static inline void gen_jmp_im(target_ulong pc) |
331 | { | |
48d5c82b | 332 | tcg_gen_movi_tl(cpu_pc, pc); |
3475187d FB |
333 | } |
334 | ||
335 | static inline void gen_movl_npc_im(target_ulong npc) | |
336 | { | |
48d5c82b | 337 | tcg_gen_movi_tl(cpu_npc, npc); |
3475187d FB |
338 | } |
339 | ||
5fafdf24 | 340 | static inline void gen_goto_tb(DisasContext *s, int tb_num, |
6e256c93 FB |
341 | target_ulong pc, target_ulong npc) |
342 | { | |
343 | TranslationBlock *tb; | |
344 | ||
345 | tb = s->tb; | |
346 | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) && | |
347 | (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) { | |
348 | /* jump to same page: we can use a direct jump */ | |
57fec1fe | 349 | tcg_gen_goto_tb(tb_num); |
6e256c93 FB |
350 | gen_jmp_im(pc); |
351 | gen_movl_npc_im(npc); | |
57fec1fe | 352 | tcg_gen_exit_tb((long)tb + tb_num); |
6e256c93 FB |
353 | } else { |
354 | /* jump to another page: currently not optimized */ | |
355 | gen_jmp_im(pc); | |
356 | gen_movl_npc_im(npc); | |
57fec1fe | 357 | tcg_gen_exit_tb(0); |
6e256c93 FB |
358 | } |
359 | } | |
360 | ||
19f329ad BS |
361 | // XXX suboptimal |
362 | static inline void gen_mov_reg_N(TCGv reg, TCGv src) | |
363 | { | |
364 | tcg_gen_shri_i32(reg, src, 23); | |
365 | tcg_gen_andi_tl(reg, reg, 0x1); | |
366 | } | |
367 | ||
368 | static inline void gen_mov_reg_Z(TCGv reg, TCGv src) | |
369 | { | |
370 | tcg_gen_shri_i32(reg, src, 22); | |
371 | tcg_gen_andi_tl(reg, reg, 0x1); | |
372 | } | |
373 | ||
374 | static inline void gen_mov_reg_V(TCGv reg, TCGv src) | |
375 | { | |
376 | tcg_gen_shri_i32(reg, src, 21); | |
377 | tcg_gen_andi_tl(reg, reg, 0x1); | |
378 | } | |
379 | ||
380 | static inline void gen_mov_reg_C(TCGv reg, TCGv src) | |
381 | { | |
382 | tcg_gen_shri_i32(reg, src, 20); | |
383 | tcg_gen_andi_tl(reg, reg, 0x1); | |
384 | } | |
385 | ||
dc99a3f2 BS |
386 | static inline void gen_op_exception(int exception) |
387 | { | |
0425bee5 BS |
388 | tcg_gen_movi_i32(cpu_tmp0, exception); |
389 | tcg_gen_helper_0_1(raise_exception, cpu_tmp0); | |
dc99a3f2 BS |
390 | } |
391 | ||
392 | static inline void gen_cc_clear(void) | |
393 | { | |
394 | tcg_gen_movi_i32(cpu_psr, 0); | |
395 | #ifdef TARGET_SPARC64 | |
396 | tcg_gen_movi_i32(cpu_xcc, 0); | |
397 | #endif | |
398 | } | |
399 | ||
400 | /* old op: | |
401 | if (!T0) | |
402 | env->psr |= PSR_ZERO; | |
403 | if ((int32_t) T0 < 0) | |
404 | env->psr |= PSR_NEG; | |
405 | */ | |
406 | static inline void gen_cc_NZ(TCGv dst) | |
407 | { | |
408 | int l1, l2; | |
dc99a3f2 BS |
409 | |
410 | l1 = gen_new_label(); | |
411 | l2 = gen_new_label(); | |
0425bee5 | 412 | tcg_gen_brcond_i32(TCG_COND_NE, dst, tcg_const_i32(0), l1); |
dc99a3f2 BS |
413 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO); |
414 | gen_set_label(l1); | |
0425bee5 | 415 | tcg_gen_brcond_i32(TCG_COND_GE, dst, tcg_const_i32(0), l2); |
dc99a3f2 BS |
416 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG); |
417 | gen_set_label(l2); | |
418 | #ifdef TARGET_SPARC64 | |
419 | { | |
420 | int l3, l4; | |
421 | ||
422 | l3 = gen_new_label(); | |
423 | l4 = gen_new_label(); | |
0425bee5 | 424 | tcg_gen_brcond_tl(TCG_COND_NE, dst, tcg_const_tl(0), l3); |
dc99a3f2 BS |
425 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO); |
426 | gen_set_label(l3); | |
0425bee5 | 427 | tcg_gen_brcond_tl(TCG_COND_GE, dst, tcg_const_tl(0), l4); |
dc99a3f2 BS |
428 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG); |
429 | gen_set_label(l4); | |
430 | } | |
431 | #endif | |
432 | } | |
433 | ||
434 | /* old op: | |
435 | if (T0 < src1) | |
436 | env->psr |= PSR_CARRY; | |
437 | */ | |
438 | static inline void gen_cc_C_add(TCGv dst, TCGv src1) | |
439 | { | |
440 | int l1; | |
441 | ||
442 | l1 = gen_new_label(); | |
443 | tcg_gen_brcond_i32(TCG_COND_GEU, dst, src1, l1); | |
444 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); | |
445 | gen_set_label(l1); | |
446 | #ifdef TARGET_SPARC64 | |
447 | { | |
448 | int l2; | |
449 | ||
450 | l2 = gen_new_label(); | |
451 | tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l2); | |
452 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); | |
453 | gen_set_label(l2); | |
454 | } | |
455 | #endif | |
456 | } | |
457 | ||
458 | /* old op: | |
459 | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31)) | |
460 | env->psr |= PSR_OVF; | |
461 | */ | |
462 | static inline void gen_cc_V_add(TCGv dst, TCGv src1, TCGv src2) | |
463 | { | |
0425bee5 | 464 | TCGv r_temp; |
dc99a3f2 BS |
465 | int l1; |
466 | ||
467 | l1 = gen_new_label(); | |
468 | ||
469 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
dc99a3f2 BS |
470 | tcg_gen_xor_tl(r_temp, src1, src2); |
471 | tcg_gen_xori_tl(r_temp, r_temp, -1); | |
0425bee5 BS |
472 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
473 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
474 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); | |
475 | tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_i32(0), l1); | |
dc99a3f2 BS |
476 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
477 | gen_set_label(l1); | |
478 | #ifdef TARGET_SPARC64 | |
479 | { | |
480 | int l2; | |
481 | ||
482 | l2 = gen_new_label(); | |
dc99a3f2 BS |
483 | tcg_gen_xor_tl(r_temp, src1, src2); |
484 | tcg_gen_xori_tl(r_temp, r_temp, -1); | |
0425bee5 BS |
485 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
486 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
487 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | |
488 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2); | |
dc99a3f2 BS |
489 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF); |
490 | gen_set_label(l2); | |
491 | } | |
492 | #endif | |
0425bee5 | 493 | tcg_gen_discard_tl(r_temp); |
dc99a3f2 BS |
494 | } |
495 | ||
496 | static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) | |
497 | { | |
0425bee5 | 498 | TCGv r_temp; |
dc99a3f2 BS |
499 | int l1; |
500 | ||
501 | l1 = gen_new_label(); | |
502 | ||
503 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
dc99a3f2 BS |
504 | tcg_gen_xor_tl(r_temp, src1, src2); |
505 | tcg_gen_xori_tl(r_temp, r_temp, -1); | |
0425bee5 BS |
506 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
507 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
508 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); | |
509 | tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_i32(0), l1); | |
dc99a3f2 BS |
510 | gen_op_exception(TT_TOVF); |
511 | gen_set_label(l1); | |
512 | #ifdef TARGET_SPARC64 | |
513 | { | |
514 | int l2; | |
515 | ||
516 | l2 = gen_new_label(); | |
dc99a3f2 BS |
517 | tcg_gen_xor_tl(r_temp, src1, src2); |
518 | tcg_gen_xori_tl(r_temp, r_temp, -1); | |
0425bee5 BS |
519 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
520 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
521 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | |
522 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2); | |
dc99a3f2 BS |
523 | gen_op_exception(TT_TOVF); |
524 | gen_set_label(l2); | |
525 | } | |
526 | #endif | |
0425bee5 | 527 | tcg_gen_discard_tl(r_temp); |
dc99a3f2 BS |
528 | } |
529 | ||
530 | static inline void gen_cc_V_tag(TCGv src1, TCGv src2) | |
531 | { | |
532 | int l1; | |
dc99a3f2 BS |
533 | |
534 | l1 = gen_new_label(); | |
0425bee5 BS |
535 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
536 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3); | |
537 | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1); | |
dc99a3f2 BS |
538 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
539 | gen_set_label(l1); | |
540 | } | |
541 | ||
542 | static inline void gen_tag_tv(TCGv src1, TCGv src2) | |
543 | { | |
544 | int l1; | |
dc99a3f2 BS |
545 | |
546 | l1 = gen_new_label(); | |
0425bee5 BS |
547 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
548 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3); | |
549 | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1); | |
dc99a3f2 BS |
550 | gen_op_exception(TT_TOVF); |
551 | gen_set_label(l1); | |
552 | } | |
553 | ||
554 | static inline void gen_op_add_T1_T0_cc(void) | |
555 | { | |
556 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
557 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
558 | gen_cc_clear(); | |
559 | gen_cc_NZ(cpu_T[0]); | |
560 | gen_cc_C_add(cpu_T[0], cpu_cc_src); | |
561 | gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
562 | } | |
563 | ||
564 | static inline void gen_op_addx_T1_T0_cc(void) | |
565 | { | |
566 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
567 | gen_mov_reg_C(cpu_tmp0, cpu_psr); | |
568 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
569 | gen_cc_clear(); | |
570 | gen_cc_C_add(cpu_T[0], cpu_cc_src); | |
571 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
572 | gen_cc_C_add(cpu_T[0], cpu_cc_src); | |
573 | gen_cc_NZ(cpu_T[0]); | |
574 | gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
575 | } | |
576 | ||
577 | static inline void gen_op_tadd_T1_T0_cc(void) | |
578 | { | |
579 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
580 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
581 | gen_cc_clear(); | |
582 | gen_cc_NZ(cpu_T[0]); | |
583 | gen_cc_C_add(cpu_T[0], cpu_cc_src); | |
584 | gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
585 | gen_cc_V_tag(cpu_cc_src, cpu_T[1]); | |
586 | } | |
587 | ||
588 | static inline void gen_op_tadd_T1_T0_ccTV(void) | |
589 | { | |
590 | gen_tag_tv(cpu_T[0], cpu_T[1]); | |
591 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
592 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
593 | gen_add_tv(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
594 | gen_cc_clear(); | |
595 | gen_cc_NZ(cpu_T[0]); | |
596 | gen_cc_C_add(cpu_T[0], cpu_cc_src); | |
597 | } | |
598 | ||
599 | /* old op: | |
600 | if (src1 < T1) | |
601 | env->psr |= PSR_CARRY; | |
602 | */ | |
603 | static inline void gen_cc_C_sub(TCGv src1, TCGv src2) | |
604 | { | |
605 | int l1; | |
606 | ||
607 | l1 = gen_new_label(); | |
608 | tcg_gen_brcond_i32(TCG_COND_GEU, src1, src2, l1); | |
609 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); | |
610 | gen_set_label(l1); | |
611 | #ifdef TARGET_SPARC64 | |
612 | { | |
613 | int l2; | |
614 | ||
615 | l2 = gen_new_label(); | |
616 | tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l2); | |
617 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); | |
618 | gen_set_label(l2); | |
619 | } | |
620 | #endif | |
621 | } | |
622 | ||
623 | /* old op: | |
624 | if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31)) | |
625 | env->psr |= PSR_OVF; | |
626 | */ | |
627 | static inline void gen_cc_V_sub(TCGv dst, TCGv src1, TCGv src2) | |
628 | { | |
0425bee5 | 629 | TCGv r_temp; |
dc99a3f2 BS |
630 | int l1; |
631 | ||
632 | l1 = gen_new_label(); | |
633 | ||
634 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
dc99a3f2 | 635 | tcg_gen_xor_tl(r_temp, src1, src2); |
0425bee5 BS |
636 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
637 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
638 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); | |
639 | tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_i32(0), l1); | |
dc99a3f2 BS |
640 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
641 | gen_set_label(l1); | |
642 | #ifdef TARGET_SPARC64 | |
643 | { | |
644 | int l2; | |
645 | ||
646 | l2 = gen_new_label(); | |
dc99a3f2 | 647 | tcg_gen_xor_tl(r_temp, src1, src2); |
0425bee5 BS |
648 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
649 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
650 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | |
651 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2); | |
dc99a3f2 BS |
652 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF); |
653 | gen_set_label(l2); | |
654 | } | |
655 | #endif | |
0425bee5 | 656 | tcg_gen_discard_tl(r_temp); |
dc99a3f2 BS |
657 | } |
658 | ||
659 | static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) | |
660 | { | |
0425bee5 | 661 | TCGv r_temp; |
dc99a3f2 BS |
662 | int l1; |
663 | ||
664 | l1 = gen_new_label(); | |
665 | ||
666 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
dc99a3f2 | 667 | tcg_gen_xor_tl(r_temp, src1, src2); |
0425bee5 BS |
668 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
669 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
670 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); | |
671 | tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_i32(0), l1); | |
dc99a3f2 BS |
672 | gen_op_exception(TT_TOVF); |
673 | gen_set_label(l1); | |
674 | #ifdef TARGET_SPARC64 | |
675 | { | |
676 | int l2; | |
677 | ||
678 | l2 = gen_new_label(); | |
dc99a3f2 | 679 | tcg_gen_xor_tl(r_temp, src1, src2); |
0425bee5 BS |
680 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
681 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
682 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | |
683 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2); | |
dc99a3f2 BS |
684 | gen_op_exception(TT_TOVF); |
685 | gen_set_label(l2); | |
686 | } | |
687 | #endif | |
0425bee5 | 688 | tcg_gen_discard_tl(r_temp); |
dc99a3f2 BS |
689 | } |
690 | ||
691 | static inline void gen_op_sub_T1_T0_cc(void) | |
692 | { | |
693 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
694 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
695 | gen_cc_clear(); | |
696 | gen_cc_NZ(cpu_T[0]); | |
697 | gen_cc_C_sub(cpu_cc_src, cpu_T[1]); | |
698 | gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
699 | } | |
700 | ||
701 | static inline void gen_op_subx_T1_T0_cc(void) | |
702 | { | |
703 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
704 | gen_mov_reg_C(cpu_tmp0, cpu_psr); | |
705 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
706 | gen_cc_clear(); | |
707 | gen_cc_C_sub(cpu_T[0], cpu_cc_src); | |
708 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
709 | gen_cc_C_sub(cpu_T[0], cpu_cc_src); | |
710 | gen_cc_NZ(cpu_T[0]); | |
711 | gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
712 | } | |
713 | ||
714 | static inline void gen_op_tsub_T1_T0_cc(void) | |
715 | { | |
716 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
717 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
718 | gen_cc_clear(); | |
719 | gen_cc_NZ(cpu_T[0]); | |
720 | gen_cc_C_sub(cpu_cc_src, cpu_T[1]); | |
721 | gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
722 | gen_cc_V_tag(cpu_cc_src, cpu_T[1]); | |
723 | } | |
724 | ||
725 | static inline void gen_op_tsub_T1_T0_ccTV(void) | |
726 | { | |
727 | gen_tag_tv(cpu_T[0], cpu_T[1]); | |
728 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
729 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
730 | gen_sub_tv(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
731 | gen_cc_clear(); | |
732 | gen_cc_NZ(cpu_T[0]); | |
733 | gen_cc_C_sub(cpu_cc_src, cpu_T[1]); | |
734 | } | |
735 | ||
d9bdab86 BS |
736 | static inline void gen_op_mulscc_T1_T0(void) |
737 | { | |
738 | TCGv r_temp; | |
739 | int l1, l2; | |
740 | ||
741 | l1 = gen_new_label(); | |
742 | l2 = gen_new_label(); | |
743 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
744 | ||
745 | /* old op: | |
746 | if (!(env->y & 1)) | |
747 | T1 = 0; | |
748 | */ | |
749 | tcg_gen_ld_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); | |
750 | tcg_gen_andi_i32(r_temp, r_temp, 0x1); | |
751 | tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); | |
752 | tcg_gen_mov_tl(cpu_cc_src2, cpu_T[1]); | |
06b3e1b3 | 753 | tcg_gen_br(l2); |
d9bdab86 BS |
754 | gen_set_label(l1); |
755 | tcg_gen_movi_tl(cpu_cc_src2, 0); | |
756 | gen_set_label(l2); | |
757 | ||
758 | // b2 = T0 & 1; | |
759 | // env->y = (b2 << 31) | (env->y >> 1); | |
760 | tcg_gen_shli_i32(r_temp, cpu_T[0], 31); | |
761 | tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y)); | |
762 | tcg_gen_shri_i32(cpu_tmp0, cpu_tmp0, 1); | |
763 | tcg_gen_or_i32(cpu_tmp0, cpu_tmp0, r_temp); | |
764 | tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y)); | |
765 | ||
766 | // b1 = N ^ V; | |
767 | gen_mov_reg_N(cpu_tmp0, cpu_psr); | |
768 | gen_mov_reg_V(r_temp, cpu_psr); | |
769 | tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp); | |
770 | ||
771 | // T0 = (b1 << 31) | (T0 >> 1); | |
772 | // src1 = T0; | |
773 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31); | |
774 | tcg_gen_shri_tl(cpu_cc_src, cpu_T[0], 1); | |
775 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); | |
776 | ||
777 | /* do addition and update flags */ | |
778 | tcg_gen_add_tl(cpu_T[0], cpu_cc_src, cpu_cc_src2); | |
779 | tcg_gen_discard_tl(r_temp); | |
780 | ||
781 | gen_cc_clear(); | |
782 | gen_cc_NZ(cpu_T[0]); | |
783 | gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_cc_src2); | |
784 | gen_cc_C_add(cpu_T[0], cpu_cc_src); | |
785 | } | |
786 | ||
8879d139 BS |
787 | static inline void gen_op_umul_T1_T0(void) |
788 | { | |
789 | TCGv r_temp, r_temp2; | |
790 | ||
791 | r_temp = tcg_temp_new(TCG_TYPE_I64); | |
792 | r_temp2 = tcg_temp_new(TCG_TYPE_I64); | |
793 | ||
794 | tcg_gen_extu_i32_i64(r_temp, cpu_T[1]); | |
795 | tcg_gen_extu_i32_i64(r_temp2, cpu_T[0]); | |
796 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); | |
797 | ||
798 | tcg_gen_shri_i64(r_temp, r_temp2, 32); | |
799 | tcg_gen_trunc_i64_i32(r_temp, r_temp); | |
800 | tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); | |
801 | #ifdef TARGET_SPARC64 | |
802 | tcg_gen_mov_i64(cpu_T[0], r_temp2); | |
803 | #else | |
804 | tcg_gen_trunc_i64_i32(cpu_T[0], r_temp2); | |
805 | #endif | |
806 | ||
807 | tcg_gen_discard_i64(r_temp); | |
808 | tcg_gen_discard_i64(r_temp2); | |
809 | } | |
810 | ||
811 | static inline void gen_op_smul_T1_T0(void) | |
812 | { | |
813 | TCGv r_temp, r_temp2; | |
814 | ||
815 | r_temp = tcg_temp_new(TCG_TYPE_I64); | |
816 | r_temp2 = tcg_temp_new(TCG_TYPE_I64); | |
817 | ||
2483386a BS |
818 | tcg_gen_ext_i32_i64(r_temp, cpu_T[1]); |
819 | tcg_gen_ext_i32_i64(r_temp2, cpu_T[0]); | |
8879d139 BS |
820 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
821 | ||
822 | tcg_gen_shri_i64(r_temp, r_temp2, 32); | |
823 | tcg_gen_trunc_i64_i32(r_temp, r_temp); | |
824 | tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); | |
825 | #ifdef TARGET_SPARC64 | |
826 | tcg_gen_mov_i64(cpu_T[0], r_temp2); | |
827 | #else | |
828 | tcg_gen_trunc_i64_i32(cpu_T[0], r_temp2); | |
829 | #endif | |
830 | ||
831 | tcg_gen_discard_i64(r_temp); | |
832 | tcg_gen_discard_i64(r_temp2); | |
833 | } | |
834 | ||
3b89f26c BS |
835 | static inline void gen_op_udiv_T1_T0(void) |
836 | { | |
837 | tcg_gen_helper_1_2(helper_udiv, cpu_T[0], cpu_T[0], cpu_T[1]); | |
838 | } | |
839 | ||
840 | static inline void gen_op_sdiv_T1_T0(void) | |
841 | { | |
842 | tcg_gen_helper_1_2(helper_sdiv, cpu_T[0], cpu_T[0], cpu_T[1]); | |
843 | } | |
844 | ||
1a7b60e7 BS |
845 | #ifdef TARGET_SPARC64 |
846 | static inline void gen_trap_ifdivzero_i64(TCGv divisor) | |
847 | { | |
848 | int l1; | |
849 | ||
850 | l1 = gen_new_label(); | |
851 | tcg_gen_brcond_i64(TCG_COND_NE, divisor, tcg_const_tl(0), l1); | |
852 | gen_op_exception(TT_DIV_ZERO); | |
853 | gen_set_label(l1); | |
854 | } | |
855 | ||
856 | static inline void gen_op_sdivx_T1_T0(void) | |
857 | { | |
858 | int l1, l2; | |
859 | ||
860 | l1 = gen_new_label(); | |
861 | l2 = gen_new_label(); | |
862 | gen_trap_ifdivzero_i64(cpu_T[1]); | |
863 | tcg_gen_brcond_i64(TCG_COND_NE, cpu_T[0], tcg_const_i64(INT64_MIN), l1); | |
864 | tcg_gen_brcond_i64(TCG_COND_NE, cpu_T[1], tcg_const_i64(-1), l1); | |
865 | tcg_gen_movi_i64(cpu_T[0], INT64_MIN); | |
06b3e1b3 | 866 | tcg_gen_br(l2); |
1a7b60e7 BS |
867 | gen_set_label(l1); |
868 | tcg_gen_div_i64(cpu_T[0], cpu_T[0], cpu_T[1]); | |
869 | gen_set_label(l2); | |
870 | } | |
871 | #endif | |
872 | ||
dc99a3f2 BS |
873 | static inline void gen_op_div_cc(void) |
874 | { | |
875 | int l1; | |
dc99a3f2 BS |
876 | |
877 | gen_cc_clear(); | |
878 | gen_cc_NZ(cpu_T[0]); | |
879 | l1 = gen_new_label(); | |
3b89f26c BS |
880 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2)); |
881 | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1); | |
dc99a3f2 BS |
882 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
883 | gen_set_label(l1); | |
884 | } | |
885 | ||
886 | static inline void gen_op_logic_T0_cc(void) | |
887 | { | |
888 | gen_cc_clear(); | |
889 | gen_cc_NZ(cpu_T[0]); | |
890 | } | |
891 | ||
19f329ad BS |
892 | // 1 |
893 | static inline void gen_op_eval_ba(TCGv dst) | |
894 | { | |
895 | tcg_gen_movi_tl(dst, 1); | |
896 | } | |
897 | ||
898 | // Z | |
899 | static inline void gen_op_eval_be(TCGv dst, TCGv src) | |
900 | { | |
901 | gen_mov_reg_Z(dst, src); | |
902 | } | |
903 | ||
904 | // Z | (N ^ V) | |
905 | static inline void gen_op_eval_ble(TCGv dst, TCGv src) | |
906 | { | |
0425bee5 | 907 | gen_mov_reg_N(cpu_tmp0, src); |
19f329ad | 908 | gen_mov_reg_V(dst, src); |
0425bee5 BS |
909 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
910 | gen_mov_reg_Z(cpu_tmp0, src); | |
911 | tcg_gen_or_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
912 | } |
913 | ||
914 | // N ^ V | |
915 | static inline void gen_op_eval_bl(TCGv dst, TCGv src) | |
916 | { | |
0425bee5 | 917 | gen_mov_reg_V(cpu_tmp0, src); |
19f329ad | 918 | gen_mov_reg_N(dst, src); |
0425bee5 | 919 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
19f329ad BS |
920 | } |
921 | ||
922 | // C | Z | |
923 | static inline void gen_op_eval_bleu(TCGv dst, TCGv src) | |
924 | { | |
0425bee5 | 925 | gen_mov_reg_Z(cpu_tmp0, src); |
19f329ad | 926 | gen_mov_reg_C(dst, src); |
0425bee5 | 927 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
19f329ad BS |
928 | } |
929 | ||
930 | // C | |
931 | static inline void gen_op_eval_bcs(TCGv dst, TCGv src) | |
932 | { | |
933 | gen_mov_reg_C(dst, src); | |
934 | } | |
935 | ||
936 | // V | |
937 | static inline void gen_op_eval_bvs(TCGv dst, TCGv src) | |
938 | { | |
939 | gen_mov_reg_V(dst, src); | |
940 | } | |
941 | ||
942 | // 0 | |
943 | static inline void gen_op_eval_bn(TCGv dst) | |
944 | { | |
945 | tcg_gen_movi_tl(dst, 0); | |
946 | } | |
947 | ||
948 | // N | |
949 | static inline void gen_op_eval_bneg(TCGv dst, TCGv src) | |
950 | { | |
951 | gen_mov_reg_N(dst, src); | |
952 | } | |
953 | ||
954 | // !Z | |
955 | static inline void gen_op_eval_bne(TCGv dst, TCGv src) | |
956 | { | |
957 | gen_mov_reg_Z(dst, src); | |
958 | tcg_gen_xori_tl(dst, dst, 0x1); | |
959 | } | |
960 | ||
961 | // !(Z | (N ^ V)) | |
962 | static inline void gen_op_eval_bg(TCGv dst, TCGv src) | |
963 | { | |
0425bee5 | 964 | gen_mov_reg_N(cpu_tmp0, src); |
19f329ad | 965 | gen_mov_reg_V(dst, src); |
0425bee5 BS |
966 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
967 | gen_mov_reg_Z(cpu_tmp0, src); | |
968 | tcg_gen_or_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
969 | tcg_gen_xori_tl(dst, dst, 0x1); |
970 | } | |
971 | ||
972 | // !(N ^ V) | |
973 | static inline void gen_op_eval_bge(TCGv dst, TCGv src) | |
974 | { | |
0425bee5 | 975 | gen_mov_reg_V(cpu_tmp0, src); |
19f329ad | 976 | gen_mov_reg_N(dst, src); |
0425bee5 | 977 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
19f329ad BS |
978 | tcg_gen_xori_tl(dst, dst, 0x1); |
979 | } | |
980 | ||
981 | // !(C | Z) | |
982 | static inline void gen_op_eval_bgu(TCGv dst, TCGv src) | |
983 | { | |
0425bee5 | 984 | gen_mov_reg_Z(cpu_tmp0, src); |
19f329ad | 985 | gen_mov_reg_C(dst, src); |
0425bee5 | 986 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
19f329ad BS |
987 | tcg_gen_xori_tl(dst, dst, 0x1); |
988 | } | |
989 | ||
990 | // !C | |
991 | static inline void gen_op_eval_bcc(TCGv dst, TCGv src) | |
992 | { | |
993 | gen_mov_reg_C(dst, src); | |
994 | tcg_gen_xori_tl(dst, dst, 0x1); | |
995 | } | |
996 | ||
997 | // !N | |
998 | static inline void gen_op_eval_bpos(TCGv dst, TCGv src) | |
999 | { | |
1000 | gen_mov_reg_N(dst, src); | |
1001 | tcg_gen_xori_tl(dst, dst, 0x1); | |
1002 | } | |
1003 | ||
1004 | // !V | |
1005 | static inline void gen_op_eval_bvc(TCGv dst, TCGv src) | |
1006 | { | |
1007 | gen_mov_reg_V(dst, src); | |
1008 | tcg_gen_xori_tl(dst, dst, 0x1); | |
1009 | } | |
1010 | ||
1011 | /* | |
1012 | FPSR bit field FCC1 | FCC0: | |
1013 | 0 = | |
1014 | 1 < | |
1015 | 2 > | |
1016 | 3 unordered | |
1017 | */ | |
1018 | static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, | |
1019 | unsigned int fcc_offset) | |
1020 | { | |
1021 | tcg_gen_shri_i32(reg, src, 10 + fcc_offset); | |
1022 | tcg_gen_andi_tl(reg, reg, 0x1); | |
1023 | } | |
1024 | ||
1025 | static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, | |
1026 | unsigned int fcc_offset) | |
1027 | { | |
1028 | tcg_gen_shri_i32(reg, src, 11 + fcc_offset); | |
1029 | tcg_gen_andi_tl(reg, reg, 0x1); | |
1030 | } | |
1031 | ||
1032 | // !0: FCC0 | FCC1 | |
1033 | static inline void gen_op_eval_fbne(TCGv dst, TCGv src, | |
1034 | unsigned int fcc_offset) | |
1035 | { | |
19f329ad | 1036 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1037 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1038 | tcg_gen_or_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1039 | } |
1040 | ||
1041 | // 1 or 2: FCC0 ^ FCC1 | |
1042 | static inline void gen_op_eval_fblg(TCGv dst, TCGv src, | |
1043 | unsigned int fcc_offset) | |
1044 | { | |
19f329ad | 1045 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1046 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1047 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1048 | } |
1049 | ||
1050 | // 1 or 3: FCC0 | |
1051 | static inline void gen_op_eval_fbul(TCGv dst, TCGv src, | |
1052 | unsigned int fcc_offset) | |
1053 | { | |
1054 | gen_mov_reg_FCC0(dst, src, fcc_offset); | |
1055 | } | |
1056 | ||
1057 | // 1: FCC0 & !FCC1 | |
1058 | static inline void gen_op_eval_fbl(TCGv dst, TCGv src, | |
1059 | unsigned int fcc_offset) | |
1060 | { | |
19f329ad | 1061 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1062 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1063 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1); | |
1064 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1065 | } |
1066 | ||
1067 | // 2 or 3: FCC1 | |
1068 | static inline void gen_op_eval_fbug(TCGv dst, TCGv src, | |
1069 | unsigned int fcc_offset) | |
1070 | { | |
1071 | gen_mov_reg_FCC1(dst, src, fcc_offset); | |
1072 | } | |
1073 | ||
1074 | // 2: !FCC0 & FCC1 | |
1075 | static inline void gen_op_eval_fbg(TCGv dst, TCGv src, | |
1076 | unsigned int fcc_offset) | |
1077 | { | |
19f329ad BS |
1078 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1079 | tcg_gen_xori_tl(dst, dst, 0x1); | |
0425bee5 BS |
1080 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1081 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1082 | } |
1083 | ||
1084 | // 3: FCC0 & FCC1 | |
1085 | static inline void gen_op_eval_fbu(TCGv dst, TCGv src, | |
1086 | unsigned int fcc_offset) | |
1087 | { | |
19f329ad | 1088 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1089 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1090 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1091 | } |
1092 | ||
1093 | // 0: !(FCC0 | FCC1) | |
1094 | static inline void gen_op_eval_fbe(TCGv dst, TCGv src, | |
1095 | unsigned int fcc_offset) | |
1096 | { | |
19f329ad | 1097 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1098 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1099 | tcg_gen_or_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1100 | tcg_gen_xori_tl(dst, dst, 0x1); |
1101 | } | |
1102 | ||
1103 | // 0 or 3: !(FCC0 ^ FCC1) | |
1104 | static inline void gen_op_eval_fbue(TCGv dst, TCGv src, | |
1105 | unsigned int fcc_offset) | |
1106 | { | |
19f329ad | 1107 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1108 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1109 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1110 | tcg_gen_xori_tl(dst, dst, 0x1); |
1111 | } | |
1112 | ||
1113 | // 0 or 2: !FCC0 | |
1114 | static inline void gen_op_eval_fbge(TCGv dst, TCGv src, | |
1115 | unsigned int fcc_offset) | |
1116 | { | |
1117 | gen_mov_reg_FCC0(dst, src, fcc_offset); | |
1118 | tcg_gen_xori_tl(dst, dst, 0x1); | |
1119 | } | |
1120 | ||
1121 | // !1: !(FCC0 & !FCC1) | |
1122 | static inline void gen_op_eval_fbuge(TCGv dst, TCGv src, | |
1123 | unsigned int fcc_offset) | |
1124 | { | |
19f329ad | 1125 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1126 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1127 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1); | |
1128 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1129 | tcg_gen_xori_tl(dst, dst, 0x1); |
1130 | } | |
1131 | ||
1132 | // 0 or 1: !FCC1 | |
1133 | static inline void gen_op_eval_fble(TCGv dst, TCGv src, | |
1134 | unsigned int fcc_offset) | |
1135 | { | |
1136 | gen_mov_reg_FCC1(dst, src, fcc_offset); | |
1137 | tcg_gen_xori_tl(dst, dst, 0x1); | |
1138 | } | |
1139 | ||
1140 | // !2: !(!FCC0 & FCC1) | |
1141 | static inline void gen_op_eval_fbule(TCGv dst, TCGv src, | |
1142 | unsigned int fcc_offset) | |
1143 | { | |
19f329ad BS |
1144 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1145 | tcg_gen_xori_tl(dst, dst, 0x1); | |
0425bee5 BS |
1146 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1147 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1148 | tcg_gen_xori_tl(dst, dst, 0x1); |
1149 | } | |
1150 | ||
1151 | // !3: !(FCC0 & FCC1) | |
1152 | static inline void gen_op_eval_fbo(TCGv dst, TCGv src, | |
1153 | unsigned int fcc_offset) | |
1154 | { | |
19f329ad | 1155 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1156 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1157 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1158 | tcg_gen_xori_tl(dst, dst, 0x1); |
1159 | } | |
1160 | ||
46525e1f | 1161 | static inline void gen_branch2(DisasContext *dc, target_ulong pc1, |
19f329ad | 1162 | target_ulong pc2, TCGv r_cond) |
83469015 FB |
1163 | { |
1164 | int l1; | |
1165 | ||
1166 | l1 = gen_new_label(); | |
1167 | ||
0425bee5 | 1168 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1); |
83469015 | 1169 | |
6e256c93 | 1170 | gen_goto_tb(dc, 0, pc1, pc1 + 4); |
83469015 FB |
1171 | |
1172 | gen_set_label(l1); | |
6e256c93 | 1173 | gen_goto_tb(dc, 1, pc2, pc2 + 4); |
83469015 FB |
1174 | } |
1175 | ||
46525e1f | 1176 | static inline void gen_branch_a(DisasContext *dc, target_ulong pc1, |
19f329ad | 1177 | target_ulong pc2, TCGv r_cond) |
83469015 FB |
1178 | { |
1179 | int l1; | |
1180 | ||
1181 | l1 = gen_new_label(); | |
1182 | ||
0425bee5 | 1183 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1); |
83469015 | 1184 | |
6e256c93 | 1185 | gen_goto_tb(dc, 0, pc2, pc1); |
83469015 FB |
1186 | |
1187 | gen_set_label(l1); | |
6e256c93 | 1188 | gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8); |
83469015 FB |
1189 | } |
1190 | ||
46525e1f BS |
1191 | static inline void gen_branch(DisasContext *dc, target_ulong pc, |
1192 | target_ulong npc) | |
83469015 | 1193 | { |
6e256c93 | 1194 | gen_goto_tb(dc, 0, pc, npc); |
83469015 FB |
1195 | } |
1196 | ||
19f329ad BS |
1197 | static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2, |
1198 | TCGv r_cond) | |
83469015 FB |
1199 | { |
1200 | int l1, l2; | |
1201 | ||
1202 | l1 = gen_new_label(); | |
1203 | l2 = gen_new_label(); | |
19f329ad | 1204 | |
0425bee5 | 1205 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1); |
83469015 FB |
1206 | |
1207 | gen_movl_npc_im(npc1); | |
06b3e1b3 | 1208 | tcg_gen_br(l2); |
83469015 FB |
1209 | |
1210 | gen_set_label(l1); | |
1211 | gen_movl_npc_im(npc2); | |
1212 | gen_set_label(l2); | |
1213 | } | |
1214 | ||
1215 | /* call this function before using T2 as it may have been set for a jump */ | |
1216 | static inline void flush_T2(DisasContext * dc) | |
1217 | { | |
1218 | if (dc->npc == JUMP_PC) { | |
19f329ad | 1219 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]); |
83469015 FB |
1220 | dc->npc = DYNAMIC_PC; |
1221 | } | |
1222 | } | |
1223 | ||
72cbca10 FB |
1224 | static inline void save_npc(DisasContext * dc) |
1225 | { | |
1226 | if (dc->npc == JUMP_PC) { | |
19f329ad | 1227 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]); |
72cbca10 FB |
1228 | dc->npc = DYNAMIC_PC; |
1229 | } else if (dc->npc != DYNAMIC_PC) { | |
3475187d | 1230 | gen_movl_npc_im(dc->npc); |
72cbca10 FB |
1231 | } |
1232 | } | |
1233 | ||
1234 | static inline void save_state(DisasContext * dc) | |
1235 | { | |
3475187d | 1236 | gen_jmp_im(dc->pc); |
72cbca10 FB |
1237 | save_npc(dc); |
1238 | } | |
1239 | ||
0bee699e FB |
1240 | static inline void gen_mov_pc_npc(DisasContext * dc) |
1241 | { | |
1242 | if (dc->npc == JUMP_PC) { | |
19f329ad | 1243 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]); |
48d5c82b | 1244 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
0bee699e FB |
1245 | dc->pc = DYNAMIC_PC; |
1246 | } else if (dc->npc == DYNAMIC_PC) { | |
48d5c82b | 1247 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
0bee699e FB |
1248 | dc->pc = DYNAMIC_PC; |
1249 | } else { | |
1250 | dc->pc = dc->npc; | |
1251 | } | |
1252 | } | |
1253 | ||
38bc628b BS |
1254 | static inline void gen_op_next_insn(void) |
1255 | { | |
48d5c82b BS |
1256 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1257 | tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); | |
38bc628b BS |
1258 | } |
1259 | ||
19f329ad BS |
1260 | static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond) |
1261 | { | |
1262 | TCGv r_src; | |
3475187d | 1263 | |
3475187d | 1264 | #ifdef TARGET_SPARC64 |
19f329ad | 1265 | if (cc) |
dc99a3f2 | 1266 | r_src = cpu_xcc; |
19f329ad | 1267 | else |
dc99a3f2 | 1268 | r_src = cpu_psr; |
3475187d | 1269 | #else |
dc99a3f2 | 1270 | r_src = cpu_psr; |
3475187d | 1271 | #endif |
19f329ad BS |
1272 | switch (cond) { |
1273 | case 0x0: | |
1274 | gen_op_eval_bn(r_dst); | |
1275 | break; | |
1276 | case 0x1: | |
1277 | gen_op_eval_be(r_dst, r_src); | |
1278 | break; | |
1279 | case 0x2: | |
1280 | gen_op_eval_ble(r_dst, r_src); | |
1281 | break; | |
1282 | case 0x3: | |
1283 | gen_op_eval_bl(r_dst, r_src); | |
1284 | break; | |
1285 | case 0x4: | |
1286 | gen_op_eval_bleu(r_dst, r_src); | |
1287 | break; | |
1288 | case 0x5: | |
1289 | gen_op_eval_bcs(r_dst, r_src); | |
1290 | break; | |
1291 | case 0x6: | |
1292 | gen_op_eval_bneg(r_dst, r_src); | |
1293 | break; | |
1294 | case 0x7: | |
1295 | gen_op_eval_bvs(r_dst, r_src); | |
1296 | break; | |
1297 | case 0x8: | |
1298 | gen_op_eval_ba(r_dst); | |
1299 | break; | |
1300 | case 0x9: | |
1301 | gen_op_eval_bne(r_dst, r_src); | |
1302 | break; | |
1303 | case 0xa: | |
1304 | gen_op_eval_bg(r_dst, r_src); | |
1305 | break; | |
1306 | case 0xb: | |
1307 | gen_op_eval_bge(r_dst, r_src); | |
1308 | break; | |
1309 | case 0xc: | |
1310 | gen_op_eval_bgu(r_dst, r_src); | |
1311 | break; | |
1312 | case 0xd: | |
1313 | gen_op_eval_bcc(r_dst, r_src); | |
1314 | break; | |
1315 | case 0xe: | |
1316 | gen_op_eval_bpos(r_dst, r_src); | |
1317 | break; | |
1318 | case 0xf: | |
1319 | gen_op_eval_bvc(r_dst, r_src); | |
1320 | break; | |
1321 | } | |
1322 | } | |
7a3f1944 | 1323 | |
19f329ad | 1324 | static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) |
e8af50a3 | 1325 | { |
19f329ad BS |
1326 | unsigned int offset; |
1327 | ||
19f329ad BS |
1328 | switch (cc) { |
1329 | default: | |
1330 | case 0x0: | |
1331 | offset = 0; | |
1332 | break; | |
1333 | case 0x1: | |
1334 | offset = 32 - 10; | |
1335 | break; | |
1336 | case 0x2: | |
1337 | offset = 34 - 10; | |
1338 | break; | |
1339 | case 0x3: | |
1340 | offset = 36 - 10; | |
1341 | break; | |
1342 | } | |
1343 | ||
1344 | switch (cond) { | |
1345 | case 0x0: | |
1346 | gen_op_eval_bn(r_dst); | |
1347 | break; | |
1348 | case 0x1: | |
87e92502 | 1349 | gen_op_eval_fbne(r_dst, cpu_fsr, offset); |
19f329ad BS |
1350 | break; |
1351 | case 0x2: | |
87e92502 | 1352 | gen_op_eval_fblg(r_dst, cpu_fsr, offset); |
19f329ad BS |
1353 | break; |
1354 | case 0x3: | |
87e92502 | 1355 | gen_op_eval_fbul(r_dst, cpu_fsr, offset); |
19f329ad BS |
1356 | break; |
1357 | case 0x4: | |
87e92502 | 1358 | gen_op_eval_fbl(r_dst, cpu_fsr, offset); |
19f329ad BS |
1359 | break; |
1360 | case 0x5: | |
87e92502 | 1361 | gen_op_eval_fbug(r_dst, cpu_fsr, offset); |
19f329ad BS |
1362 | break; |
1363 | case 0x6: | |
87e92502 | 1364 | gen_op_eval_fbg(r_dst, cpu_fsr, offset); |
19f329ad BS |
1365 | break; |
1366 | case 0x7: | |
87e92502 | 1367 | gen_op_eval_fbu(r_dst, cpu_fsr, offset); |
19f329ad BS |
1368 | break; |
1369 | case 0x8: | |
1370 | gen_op_eval_ba(r_dst); | |
1371 | break; | |
1372 | case 0x9: | |
87e92502 | 1373 | gen_op_eval_fbe(r_dst, cpu_fsr, offset); |
19f329ad BS |
1374 | break; |
1375 | case 0xa: | |
87e92502 | 1376 | gen_op_eval_fbue(r_dst, cpu_fsr, offset); |
19f329ad BS |
1377 | break; |
1378 | case 0xb: | |
87e92502 | 1379 | gen_op_eval_fbge(r_dst, cpu_fsr, offset); |
19f329ad BS |
1380 | break; |
1381 | case 0xc: | |
87e92502 | 1382 | gen_op_eval_fbuge(r_dst, cpu_fsr, offset); |
19f329ad BS |
1383 | break; |
1384 | case 0xd: | |
87e92502 | 1385 | gen_op_eval_fble(r_dst, cpu_fsr, offset); |
19f329ad BS |
1386 | break; |
1387 | case 0xe: | |
87e92502 | 1388 | gen_op_eval_fbule(r_dst, cpu_fsr, offset); |
19f329ad BS |
1389 | break; |
1390 | case 0xf: | |
87e92502 | 1391 | gen_op_eval_fbo(r_dst, cpu_fsr, offset); |
19f329ad BS |
1392 | break; |
1393 | } | |
e8af50a3 | 1394 | } |
00f219bf | 1395 | |
19f329ad | 1396 | #ifdef TARGET_SPARC64 |
00f219bf BS |
1397 | // Inverted logic |
1398 | static const int gen_tcg_cond_reg[8] = { | |
1399 | -1, | |
1400 | TCG_COND_NE, | |
1401 | TCG_COND_GT, | |
1402 | TCG_COND_GE, | |
1403 | -1, | |
1404 | TCG_COND_EQ, | |
1405 | TCG_COND_LE, | |
1406 | TCG_COND_LT, | |
1407 | }; | |
19f329ad BS |
1408 | |
1409 | static inline void gen_cond_reg(TCGv r_dst, int cond) | |
1410 | { | |
19f329ad BS |
1411 | int l1; |
1412 | ||
1413 | l1 = gen_new_label(); | |
0425bee5 BS |
1414 | tcg_gen_movi_tl(r_dst, 0); |
1415 | tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], tcg_const_tl(0), l1); | |
19f329ad BS |
1416 | tcg_gen_movi_tl(r_dst, 1); |
1417 | gen_set_label(l1); | |
1418 | } | |
3475187d | 1419 | #endif |
cf495bcf | 1420 | |
0bee699e | 1421 | /* XXX: potentially incorrect if dynamic npc */ |
3475187d | 1422 | static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) |
7a3f1944 | 1423 | { |
cf495bcf | 1424 | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
af7bf89b | 1425 | target_ulong target = dc->pc + offset; |
5fafdf24 | 1426 | |
cf495bcf | 1427 | if (cond == 0x0) { |
0f8a249a BS |
1428 | /* unconditional not taken */ |
1429 | if (a) { | |
1430 | dc->pc = dc->npc + 4; | |
1431 | dc->npc = dc->pc + 4; | |
1432 | } else { | |
1433 | dc->pc = dc->npc; | |
1434 | dc->npc = dc->pc + 4; | |
1435 | } | |
cf495bcf | 1436 | } else if (cond == 0x8) { |
0f8a249a BS |
1437 | /* unconditional taken */ |
1438 | if (a) { | |
1439 | dc->pc = target; | |
1440 | dc->npc = dc->pc + 4; | |
1441 | } else { | |
1442 | dc->pc = dc->npc; | |
1443 | dc->npc = target; | |
1444 | } | |
cf495bcf | 1445 | } else { |
72cbca10 | 1446 | flush_T2(dc); |
19f329ad | 1447 | gen_cond(cpu_T[2], cc, cond); |
0f8a249a | 1448 | if (a) { |
19f329ad | 1449 | gen_branch_a(dc, target, dc->npc, cpu_T[2]); |
cf495bcf | 1450 | dc->is_br = 1; |
0f8a249a | 1451 | } else { |
cf495bcf | 1452 | dc->pc = dc->npc; |
72cbca10 FB |
1453 | dc->jump_pc[0] = target; |
1454 | dc->jump_pc[1] = dc->npc + 4; | |
1455 | dc->npc = JUMP_PC; | |
0f8a249a | 1456 | } |
cf495bcf | 1457 | } |
7a3f1944 FB |
1458 | } |
1459 | ||
0bee699e | 1460 | /* XXX: potentially incorrect if dynamic npc */ |
3475187d | 1461 | static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) |
e8af50a3 FB |
1462 | { |
1463 | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); | |
af7bf89b FB |
1464 | target_ulong target = dc->pc + offset; |
1465 | ||
e8af50a3 | 1466 | if (cond == 0x0) { |
0f8a249a BS |
1467 | /* unconditional not taken */ |
1468 | if (a) { | |
1469 | dc->pc = dc->npc + 4; | |
1470 | dc->npc = dc->pc + 4; | |
1471 | } else { | |
1472 | dc->pc = dc->npc; | |
1473 | dc->npc = dc->pc + 4; | |
1474 | } | |
e8af50a3 | 1475 | } else if (cond == 0x8) { |
0f8a249a BS |
1476 | /* unconditional taken */ |
1477 | if (a) { | |
1478 | dc->pc = target; | |
1479 | dc->npc = dc->pc + 4; | |
1480 | } else { | |
1481 | dc->pc = dc->npc; | |
1482 | dc->npc = target; | |
1483 | } | |
e8af50a3 FB |
1484 | } else { |
1485 | flush_T2(dc); | |
19f329ad | 1486 | gen_fcond(cpu_T[2], cc, cond); |
0f8a249a | 1487 | if (a) { |
19f329ad | 1488 | gen_branch_a(dc, target, dc->npc, cpu_T[2]); |
e8af50a3 | 1489 | dc->is_br = 1; |
0f8a249a | 1490 | } else { |
e8af50a3 FB |
1491 | dc->pc = dc->npc; |
1492 | dc->jump_pc[0] = target; | |
1493 | dc->jump_pc[1] = dc->npc + 4; | |
1494 | dc->npc = JUMP_PC; | |
0f8a249a | 1495 | } |
e8af50a3 FB |
1496 | } |
1497 | } | |
1498 | ||
3475187d FB |
1499 | #ifdef TARGET_SPARC64 |
1500 | /* XXX: potentially incorrect if dynamic npc */ | |
1501 | static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn) | |
7a3f1944 | 1502 | { |
3475187d FB |
1503 | unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); |
1504 | target_ulong target = dc->pc + offset; | |
1505 | ||
1506 | flush_T2(dc); | |
19f329ad | 1507 | gen_cond_reg(cpu_T[2], cond); |
3475187d | 1508 | if (a) { |
19f329ad | 1509 | gen_branch_a(dc, target, dc->npc, cpu_T[2]); |
0f8a249a | 1510 | dc->is_br = 1; |
3475187d | 1511 | } else { |
0f8a249a BS |
1512 | dc->pc = dc->npc; |
1513 | dc->jump_pc[0] = target; | |
1514 | dc->jump_pc[1] = dc->npc + 4; | |
1515 | dc->npc = JUMP_PC; | |
3475187d | 1516 | } |
7a3f1944 FB |
1517 | } |
1518 | ||
3475187d | 1519 | static GenOpFunc * const gen_fcmps[4] = { |
7e8c2b6c BS |
1520 | helper_fcmps, |
1521 | helper_fcmps_fcc1, | |
1522 | helper_fcmps_fcc2, | |
1523 | helper_fcmps_fcc3, | |
3475187d FB |
1524 | }; |
1525 | ||
1526 | static GenOpFunc * const gen_fcmpd[4] = { | |
7e8c2b6c BS |
1527 | helper_fcmpd, |
1528 | helper_fcmpd_fcc1, | |
1529 | helper_fcmpd_fcc2, | |
1530 | helper_fcmpd_fcc3, | |
3475187d | 1531 | }; |
417454b0 | 1532 | |
1f587329 BS |
1533 | #if defined(CONFIG_USER_ONLY) |
1534 | static GenOpFunc * const gen_fcmpq[4] = { | |
7e8c2b6c BS |
1535 | helper_fcmpq, |
1536 | helper_fcmpq_fcc1, | |
1537 | helper_fcmpq_fcc2, | |
1538 | helper_fcmpq_fcc3, | |
1f587329 BS |
1539 | }; |
1540 | #endif | |
1541 | ||
417454b0 | 1542 | static GenOpFunc * const gen_fcmpes[4] = { |
7e8c2b6c BS |
1543 | helper_fcmpes, |
1544 | helper_fcmpes_fcc1, | |
1545 | helper_fcmpes_fcc2, | |
1546 | helper_fcmpes_fcc3, | |
417454b0 BS |
1547 | }; |
1548 | ||
1549 | static GenOpFunc * const gen_fcmped[4] = { | |
7e8c2b6c BS |
1550 | helper_fcmped, |
1551 | helper_fcmped_fcc1, | |
1552 | helper_fcmped_fcc2, | |
1553 | helper_fcmped_fcc3, | |
417454b0 BS |
1554 | }; |
1555 | ||
1f587329 BS |
1556 | #if defined(CONFIG_USER_ONLY) |
1557 | static GenOpFunc * const gen_fcmpeq[4] = { | |
7e8c2b6c BS |
1558 | helper_fcmpeq, |
1559 | helper_fcmpeq_fcc1, | |
1560 | helper_fcmpeq_fcc2, | |
1561 | helper_fcmpeq_fcc3, | |
1f587329 BS |
1562 | }; |
1563 | #endif | |
7e8c2b6c BS |
1564 | |
1565 | static inline void gen_op_fcmps(int fccno) | |
1566 | { | |
1567 | tcg_gen_helper_0_0(gen_fcmps[fccno]); | |
1568 | } | |
1569 | ||
1570 | static inline void gen_op_fcmpd(int fccno) | |
1571 | { | |
1572 | tcg_gen_helper_0_0(gen_fcmpd[fccno]); | |
1573 | } | |
1574 | ||
1575 | #if defined(CONFIG_USER_ONLY) | |
1576 | static inline void gen_op_fcmpq(int fccno) | |
1577 | { | |
1578 | tcg_gen_helper_0_0(gen_fcmpq[fccno]); | |
1579 | } | |
1580 | #endif | |
1581 | ||
1582 | static inline void gen_op_fcmpes(int fccno) | |
1583 | { | |
1584 | tcg_gen_helper_0_0(gen_fcmpes[fccno]); | |
1585 | } | |
1586 | ||
1587 | static inline void gen_op_fcmped(int fccno) | |
1588 | { | |
1589 | tcg_gen_helper_0_0(gen_fcmped[fccno]); | |
1590 | } | |
1591 | ||
1592 | #if defined(CONFIG_USER_ONLY) | |
1593 | static inline void gen_op_fcmpeq(int fccno) | |
1594 | { | |
1595 | tcg_gen_helper_0_0(gen_fcmpeq[fccno]); | |
1596 | } | |
1597 | #endif | |
1598 | ||
1599 | #else | |
1600 | ||
1601 | static inline void gen_op_fcmps(int fccno) | |
1602 | { | |
1603 | tcg_gen_helper_0_0(helper_fcmps); | |
1604 | } | |
1605 | ||
1606 | static inline void gen_op_fcmpd(int fccno) | |
1607 | { | |
1608 | tcg_gen_helper_0_0(helper_fcmpd); | |
1609 | } | |
1610 | ||
1611 | #if defined(CONFIG_USER_ONLY) | |
1612 | static inline void gen_op_fcmpq(int fccno) | |
1613 | { | |
1614 | tcg_gen_helper_0_0(helper_fcmpq); | |
1615 | } | |
1616 | #endif | |
1617 | ||
1618 | static inline void gen_op_fcmpes(int fccno) | |
1619 | { | |
1620 | tcg_gen_helper_0_0(helper_fcmpes); | |
1621 | } | |
1622 | ||
1623 | static inline void gen_op_fcmped(int fccno) | |
1624 | { | |
1625 | tcg_gen_helper_0_0(helper_fcmped); | |
1626 | } | |
1627 | ||
1628 | #if defined(CONFIG_USER_ONLY) | |
1629 | static inline void gen_op_fcmpeq(int fccno) | |
1630 | { | |
1631 | tcg_gen_helper_0_0(helper_fcmpeq); | |
1632 | } | |
1633 | #endif | |
1634 | ||
3475187d FB |
1635 | #endif |
1636 | ||
134d77a1 BS |
1637 | static inline void gen_op_fpexception_im(int fsr_flags) |
1638 | { | |
87e92502 BS |
1639 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK); |
1640 | tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); | |
134d77a1 BS |
1641 | gen_op_exception(TT_FP_EXCP); |
1642 | } | |
1643 | ||
a80dde08 FB |
1644 | static int gen_trap_ifnofpu(DisasContext * dc) |
1645 | { | |
1646 | #if !defined(CONFIG_USER_ONLY) | |
1647 | if (!dc->fpu_enabled) { | |
1648 | save_state(dc); | |
1649 | gen_op_exception(TT_NFPU_INSN); | |
1650 | dc->is_br = 1; | |
1651 | return 1; | |
1652 | } | |
1653 | #endif | |
1654 | return 0; | |
1655 | } | |
1656 | ||
7e8c2b6c BS |
1657 | static inline void gen_op_clear_ieee_excp_and_FTT(void) |
1658 | { | |
87e92502 | 1659 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK)); |
7e8c2b6c BS |
1660 | } |
1661 | ||
1662 | static inline void gen_clear_float_exceptions(void) | |
1663 | { | |
1664 | tcg_gen_helper_0_0(helper_clear_float_exceptions); | |
1665 | } | |
1666 | ||
2b29924f BS |
1667 | static inline void gen_check_align(TCGv r_addr, int align) |
1668 | { | |
1669 | tcg_gen_helper_0_2(helper_check_align, r_addr, tcg_const_i32(align)); | |
1670 | } | |
1671 | ||
1672 | static inline void gen_op_check_align_T0_1(void) | |
1673 | { | |
1674 | gen_check_align(cpu_T[0], 1); | |
1675 | } | |
1676 | ||
1677 | static inline void gen_op_check_align_T0_3(void) | |
1678 | { | |
1679 | gen_check_align(cpu_T[0], 3); | |
1680 | } | |
1681 | ||
1682 | static inline void gen_op_check_align_T0_7(void) | |
1683 | { | |
1684 | gen_check_align(cpu_T[0], 7); | |
1685 | } | |
1686 | ||
1a2fb1c0 BS |
1687 | /* asi moves */ |
1688 | #ifdef TARGET_SPARC64 | |
0425bee5 | 1689 | static inline TCGv gen_get_asi(int insn, TCGv r_addr) |
1a2fb1c0 BS |
1690 | { |
1691 | int asi, offset; | |
0425bee5 | 1692 | TCGv r_asi; |
1a2fb1c0 | 1693 | |
1a2fb1c0 | 1694 | if (IS_IMM) { |
0425bee5 | 1695 | r_asi = tcg_temp_new(TCG_TYPE_I32); |
1a2fb1c0 | 1696 | offset = GET_FIELD(insn, 25, 31); |
0425bee5 BS |
1697 | tcg_gen_addi_tl(r_addr, r_addr, offset); |
1698 | tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi)); | |
1a2fb1c0 BS |
1699 | } else { |
1700 | asi = GET_FIELD(insn, 19, 26); | |
0425bee5 | 1701 | r_asi = tcg_const_i32(asi); |
1a2fb1c0 | 1702 | } |
0425bee5 BS |
1703 | return r_asi; |
1704 | } | |
1705 | ||
1706 | static inline void gen_ld_asi(int insn, int size, int sign) | |
1707 | { | |
1708 | TCGv r_asi; | |
1709 | ||
1710 | r_asi = gen_get_asi(insn, cpu_T[0]); | |
1711 | tcg_gen_helper_1_4(helper_ld_asi, cpu_T[1], cpu_T[0], r_asi, | |
1712 | tcg_const_i32(size), tcg_const_i32(sign)); | |
1713 | tcg_gen_discard_i32(r_asi); | |
1a2fb1c0 BS |
1714 | } |
1715 | ||
1716 | static inline void gen_st_asi(int insn, int size) | |
1717 | { | |
0425bee5 | 1718 | TCGv r_asi; |
1a2fb1c0 | 1719 | |
0425bee5 BS |
1720 | r_asi = gen_get_asi(insn, cpu_T[0]); |
1721 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_asi, | |
1722 | tcg_const_i32(size)); | |
1723 | tcg_gen_discard_i32(r_asi); | |
1a2fb1c0 BS |
1724 | } |
1725 | ||
1726 | static inline void gen_ldf_asi(int insn, int size, int rd) | |
1727 | { | |
0425bee5 | 1728 | TCGv r_asi; |
1a2fb1c0 | 1729 | |
0425bee5 BS |
1730 | r_asi = gen_get_asi(insn, cpu_T[0]); |
1731 | tcg_gen_helper_0_4(helper_ldf_asi, cpu_T[0], r_asi, tcg_const_i32(size), | |
1732 | tcg_const_i32(rd)); | |
1733 | tcg_gen_discard_i32(r_asi); | |
1a2fb1c0 BS |
1734 | } |
1735 | ||
1736 | static inline void gen_stf_asi(int insn, int size, int rd) | |
1737 | { | |
0425bee5 | 1738 | TCGv r_asi; |
1a2fb1c0 | 1739 | |
0425bee5 BS |
1740 | r_asi = gen_get_asi(insn, cpu_T[0]); |
1741 | tcg_gen_helper_0_4(helper_stf_asi, cpu_T[0], r_asi, tcg_const_i32(size), | |
1742 | tcg_const_i32(rd)); | |
1743 | tcg_gen_discard_i32(r_asi); | |
1a2fb1c0 BS |
1744 | } |
1745 | ||
1746 | static inline void gen_swap_asi(int insn) | |
1747 | { | |
0425bee5 | 1748 | TCGv r_temp, r_asi; |
1a2fb1c0 | 1749 | |
1a2fb1c0 | 1750 | r_temp = tcg_temp_new(TCG_TYPE_I32); |
0425bee5 BS |
1751 | r_asi = gen_get_asi(insn, cpu_T[0]); |
1752 | tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], r_asi, | |
1753 | tcg_const_i32(4), tcg_const_i32(0)); | |
1754 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_temp, r_asi, | |
1755 | tcg_const_i32(4)); | |
1a2fb1c0 | 1756 | tcg_gen_mov_i32(cpu_T[1], r_temp); |
0425bee5 BS |
1757 | tcg_gen_discard_i32(r_asi); |
1758 | tcg_gen_discard_i32(r_temp); | |
1a2fb1c0 BS |
1759 | } |
1760 | ||
1761 | static inline void gen_ldda_asi(int insn) | |
1762 | { | |
0425bee5 | 1763 | TCGv r_dword, r_asi; |
1a2fb1c0 | 1764 | |
1a2fb1c0 | 1765 | r_dword = tcg_temp_new(TCG_TYPE_I64); |
0425bee5 BS |
1766 | r_asi = gen_get_asi(insn, cpu_T[0]); |
1767 | tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], r_asi, | |
1768 | tcg_const_i32(8), tcg_const_i32(0)); | |
1a2fb1c0 BS |
1769 | tcg_gen_trunc_i64_i32(cpu_T[0], r_dword); |
1770 | tcg_gen_shri_i64(r_dword, r_dword, 32); | |
1771 | tcg_gen_trunc_i64_i32(cpu_T[1], r_dword); | |
0425bee5 BS |
1772 | tcg_gen_discard_i32(r_asi); |
1773 | tcg_gen_discard_i64(r_dword); | |
1774 | } | |
1775 | ||
1776 | static inline void gen_stda_asi(int insn, int rd) | |
1777 | { | |
1778 | TCGv r_dword, r_temp, r_asi; | |
1779 | ||
1780 | r_dword = tcg_temp_new(TCG_TYPE_I64); | |
1781 | r_temp = tcg_temp_new(TCG_TYPE_I32); | |
1782 | gen_movl_reg_TN(rd + 1, r_temp); | |
1783 | tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1], | |
1784 | r_temp); | |
1785 | r_asi = gen_get_asi(insn, cpu_T[0]); | |
1786 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_asi, | |
1787 | tcg_const_i32(8)); | |
1788 | tcg_gen_discard_i32(r_asi); | |
1789 | tcg_gen_discard_i32(r_temp); | |
1790 | tcg_gen_discard_i64(r_dword); | |
1a2fb1c0 BS |
1791 | } |
1792 | ||
1793 | static inline void gen_cas_asi(int insn, int rd) | |
1794 | { | |
1a2fb1c0 BS |
1795 | TCGv r_val1, r_asi; |
1796 | ||
1797 | r_val1 = tcg_temp_new(TCG_TYPE_I32); | |
1a2fb1c0 | 1798 | gen_movl_reg_TN(rd, r_val1); |
0425bee5 | 1799 | r_asi = gen_get_asi(insn, cpu_T[0]); |
1a2fb1c0 BS |
1800 | tcg_gen_helper_1_4(helper_cas_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1], |
1801 | r_asi); | |
0425bee5 BS |
1802 | tcg_gen_discard_i32(r_asi); |
1803 | tcg_gen_discard_i32(r_val1); | |
1a2fb1c0 BS |
1804 | } |
1805 | ||
1806 | static inline void gen_casx_asi(int insn, int rd) | |
1807 | { | |
1a2fb1c0 BS |
1808 | TCGv r_val1, r_asi; |
1809 | ||
1810 | r_val1 = tcg_temp_new(TCG_TYPE_I64); | |
1a2fb1c0 | 1811 | gen_movl_reg_TN(rd, r_val1); |
0425bee5 | 1812 | r_asi = gen_get_asi(insn, cpu_T[0]); |
1a2fb1c0 BS |
1813 | tcg_gen_helper_1_4(helper_casx_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1], |
1814 | r_asi); | |
0425bee5 BS |
1815 | tcg_gen_discard_i32(r_asi); |
1816 | tcg_gen_discard_i32(r_val1); | |
1a2fb1c0 BS |
1817 | } |
1818 | ||
1819 | #elif !defined(CONFIG_USER_ONLY) | |
1820 | ||
1821 | static inline void gen_ld_asi(int insn, int size, int sign) | |
1822 | { | |
1823 | int asi; | |
0425bee5 | 1824 | TCGv r_dword; |
1a2fb1c0 | 1825 | |
1a2fb1c0 | 1826 | r_dword = tcg_temp_new(TCG_TYPE_I64); |
1a2fb1c0 | 1827 | asi = GET_FIELD(insn, 19, 26); |
0425bee5 BS |
1828 | tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], tcg_const_i32(asi), |
1829 | tcg_const_i32(size), tcg_const_i32(sign)); | |
1a2fb1c0 | 1830 | tcg_gen_trunc_i64_i32(cpu_T[1], r_dword); |
0425bee5 | 1831 | tcg_gen_discard_i64(r_dword); |
1a2fb1c0 BS |
1832 | } |
1833 | ||
1834 | static inline void gen_st_asi(int insn, int size) | |
1835 | { | |
1836 | int asi; | |
0425bee5 | 1837 | TCGv r_dword; |
1a2fb1c0 BS |
1838 | |
1839 | r_dword = tcg_temp_new(TCG_TYPE_I64); | |
1840 | tcg_gen_extu_i32_i64(r_dword, cpu_T[1]); | |
1a2fb1c0 | 1841 | asi = GET_FIELD(insn, 19, 26); |
0425bee5 BS |
1842 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, tcg_const_i32(asi), |
1843 | tcg_const_i32(size)); | |
1844 | tcg_gen_discard_i64(r_dword); | |
1a2fb1c0 BS |
1845 | } |
1846 | ||
1847 | static inline void gen_swap_asi(int insn) | |
1848 | { | |
1849 | int asi; | |
0425bee5 | 1850 | TCGv r_temp; |
1a2fb1c0 | 1851 | |
1a2fb1c0 | 1852 | r_temp = tcg_temp_new(TCG_TYPE_I32); |
1a2fb1c0 | 1853 | asi = GET_FIELD(insn, 19, 26); |
0425bee5 BS |
1854 | tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], tcg_const_i32(asi), |
1855 | tcg_const_i32(4), tcg_const_i32(0)); | |
1856 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], tcg_const_i32(asi), | |
1857 | tcg_const_i32(4)); | |
1a2fb1c0 | 1858 | tcg_gen_mov_i32(cpu_T[1], r_temp); |
0425bee5 | 1859 | tcg_gen_discard_i32(r_temp); |
1a2fb1c0 BS |
1860 | } |
1861 | ||
1862 | static inline void gen_ldda_asi(int insn) | |
1863 | { | |
1864 | int asi; | |
0425bee5 | 1865 | TCGv r_dword; |
1a2fb1c0 | 1866 | |
1a2fb1c0 | 1867 | r_dword = tcg_temp_new(TCG_TYPE_I64); |
1a2fb1c0 | 1868 | asi = GET_FIELD(insn, 19, 26); |
0425bee5 BS |
1869 | tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], tcg_const_i32(asi), |
1870 | tcg_const_i32(8), tcg_const_i32(0)); | |
1a2fb1c0 BS |
1871 | tcg_gen_trunc_i64_i32(cpu_T[0], r_dword); |
1872 | tcg_gen_shri_i64(r_dword, r_dword, 32); | |
1873 | tcg_gen_trunc_i64_i32(cpu_T[1], r_dword); | |
0425bee5 BS |
1874 | tcg_gen_discard_i64(r_dword); |
1875 | } | |
1876 | ||
1877 | static inline void gen_stda_asi(int insn, int rd) | |
1878 | { | |
1879 | int asi; | |
1880 | TCGv r_dword, r_temp; | |
1881 | ||
1882 | r_dword = tcg_temp_new(TCG_TYPE_I64); | |
1883 | r_temp = tcg_temp_new(TCG_TYPE_I32); | |
1884 | gen_movl_reg_TN(rd + 1, r_temp); | |
1885 | tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1], r_temp); | |
1886 | asi = GET_FIELD(insn, 19, 26); | |
1887 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, tcg_const_i32(asi), | |
1888 | tcg_const_i32(8)); | |
1889 | tcg_gen_discard_i64(r_dword); | |
1a2fb1c0 BS |
1890 | } |
1891 | #endif | |
1892 | ||
1893 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) | |
1894 | static inline void gen_ldstub_asi(int insn) | |
1895 | { | |
1896 | int asi; | |
1a2fb1c0 BS |
1897 | |
1898 | gen_ld_asi(insn, 1, 0); | |
1899 | ||
1a2fb1c0 | 1900 | asi = GET_FIELD(insn, 19, 26); |
0425bee5 BS |
1901 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], tcg_const_i64(0xff), |
1902 | tcg_const_i32(asi), tcg_const_i32(1)); | |
1a2fb1c0 BS |
1903 | } |
1904 | #endif | |
1905 | ||
0bee699e | 1906 | /* before an instruction, dc->pc must be static */ |
cf495bcf FB |
1907 | static void disas_sparc_insn(DisasContext * dc) |
1908 | { | |
1909 | unsigned int insn, opc, rs1, rs2, rd; | |
7a3f1944 | 1910 | |
0fa85d43 | 1911 | insn = ldl_code(dc->pc); |
cf495bcf | 1912 | opc = GET_FIELD(insn, 0, 1); |
7a3f1944 | 1913 | |
cf495bcf FB |
1914 | rd = GET_FIELD(insn, 2, 6); |
1915 | switch (opc) { | |
0f8a249a BS |
1916 | case 0: /* branches/sethi */ |
1917 | { | |
1918 | unsigned int xop = GET_FIELD(insn, 7, 9); | |
1919 | int32_t target; | |
1920 | switch (xop) { | |
3475187d | 1921 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
1922 | case 0x1: /* V9 BPcc */ |
1923 | { | |
1924 | int cc; | |
1925 | ||
1926 | target = GET_FIELD_SP(insn, 0, 18); | |
1927 | target = sign_extend(target, 18); | |
1928 | target <<= 2; | |
1929 | cc = GET_FIELD_SP(insn, 20, 21); | |
1930 | if (cc == 0) | |
1931 | do_branch(dc, target, insn, 0); | |
1932 | else if (cc == 2) | |
1933 | do_branch(dc, target, insn, 1); | |
1934 | else | |
1935 | goto illegal_insn; | |
1936 | goto jmp_insn; | |
1937 | } | |
1938 | case 0x3: /* V9 BPr */ | |
1939 | { | |
1940 | target = GET_FIELD_SP(insn, 0, 13) | | |
13846e70 | 1941 | (GET_FIELD_SP(insn, 20, 21) << 14); |
0f8a249a BS |
1942 | target = sign_extend(target, 16); |
1943 | target <<= 2; | |
1944 | rs1 = GET_FIELD(insn, 13, 17); | |
1945 | gen_movl_reg_T0(rs1); | |
1946 | do_branch_reg(dc, target, insn); | |
1947 | goto jmp_insn; | |
1948 | } | |
1949 | case 0x5: /* V9 FBPcc */ | |
1950 | { | |
1951 | int cc = GET_FIELD_SP(insn, 20, 21); | |
a80dde08 FB |
1952 | if (gen_trap_ifnofpu(dc)) |
1953 | goto jmp_insn; | |
0f8a249a BS |
1954 | target = GET_FIELD_SP(insn, 0, 18); |
1955 | target = sign_extend(target, 19); | |
1956 | target <<= 2; | |
1957 | do_fbranch(dc, target, insn, cc); | |
1958 | goto jmp_insn; | |
1959 | } | |
a4d17f19 | 1960 | #else |
0f8a249a BS |
1961 | case 0x7: /* CBN+x */ |
1962 | { | |
1963 | goto ncp_insn; | |
1964 | } | |
1965 | #endif | |
1966 | case 0x2: /* BN+x */ | |
1967 | { | |
1968 | target = GET_FIELD(insn, 10, 31); | |
1969 | target = sign_extend(target, 22); | |
1970 | target <<= 2; | |
1971 | do_branch(dc, target, insn, 0); | |
1972 | goto jmp_insn; | |
1973 | } | |
1974 | case 0x6: /* FBN+x */ | |
1975 | { | |
a80dde08 FB |
1976 | if (gen_trap_ifnofpu(dc)) |
1977 | goto jmp_insn; | |
0f8a249a BS |
1978 | target = GET_FIELD(insn, 10, 31); |
1979 | target = sign_extend(target, 22); | |
1980 | target <<= 2; | |
1981 | do_fbranch(dc, target, insn, 0); | |
1982 | goto jmp_insn; | |
1983 | } | |
1984 | case 0x4: /* SETHI */ | |
e80cfcfc FB |
1985 | #define OPTIM |
1986 | #if defined(OPTIM) | |
0f8a249a | 1987 | if (rd) { // nop |
e80cfcfc | 1988 | #endif |
0f8a249a | 1989 | uint32_t value = GET_FIELD(insn, 10, 31); |
1a2fb1c0 | 1990 | tcg_gen_movi_tl(cpu_T[0], value << 10); |
0f8a249a | 1991 | gen_movl_T0_reg(rd); |
e80cfcfc | 1992 | #if defined(OPTIM) |
0f8a249a | 1993 | } |
e80cfcfc | 1994 | #endif |
0f8a249a BS |
1995 | break; |
1996 | case 0x0: /* UNIMPL */ | |
1997 | default: | |
3475187d | 1998 | goto illegal_insn; |
0f8a249a BS |
1999 | } |
2000 | break; | |
2001 | } | |
2002 | break; | |
cf495bcf | 2003 | case 1: |
0f8a249a BS |
2004 | /*CALL*/ { |
2005 | target_long target = GET_FIELDs(insn, 2, 31) << 2; | |
cf495bcf | 2006 | |
48d5c82b | 2007 | gen_movl_TN_reg(15, tcg_const_tl(dc->pc)); |
0f8a249a | 2008 | target += dc->pc; |
0bee699e | 2009 | gen_mov_pc_npc(dc); |
0f8a249a BS |
2010 | dc->npc = target; |
2011 | } | |
2012 | goto jmp_insn; | |
2013 | case 2: /* FPU & Logical Operations */ | |
2014 | { | |
2015 | unsigned int xop = GET_FIELD(insn, 7, 12); | |
2016 | if (xop == 0x3a) { /* generate trap */ | |
cf495bcf | 2017 | int cond; |
3475187d | 2018 | |
cf495bcf FB |
2019 | rs1 = GET_FIELD(insn, 13, 17); |
2020 | gen_movl_reg_T0(rs1); | |
0f8a249a BS |
2021 | if (IS_IMM) { |
2022 | rs2 = GET_FIELD(insn, 25, 31); | |
1a2fb1c0 | 2023 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], rs2); |
cf495bcf FB |
2024 | } else { |
2025 | rs2 = GET_FIELD(insn, 27, 31); | |
e80cfcfc | 2026 | #if defined(OPTIM) |
0f8a249a | 2027 | if (rs2 != 0) { |
e80cfcfc | 2028 | #endif |
0f8a249a BS |
2029 | gen_movl_reg_T1(rs2); |
2030 | gen_op_add_T1_T0(); | |
e80cfcfc | 2031 | #if defined(OPTIM) |
0f8a249a | 2032 | } |
e80cfcfc | 2033 | #endif |
cf495bcf | 2034 | } |
cf495bcf FB |
2035 | cond = GET_FIELD(insn, 3, 6); |
2036 | if (cond == 0x8) { | |
a80dde08 | 2037 | save_state(dc); |
1a2fb1c0 | 2038 | tcg_gen_helper_0_1(helper_trap, cpu_T[0]); |
af7bf89b | 2039 | } else if (cond != 0) { |
748b9d8e | 2040 | TCGv r_cond = tcg_temp_new(TCG_TYPE_TL); |
3475187d | 2041 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
2042 | /* V9 icc/xcc */ |
2043 | int cc = GET_FIELD_SP(insn, 11, 12); | |
748b9d8e | 2044 | |
a80dde08 | 2045 | save_state(dc); |
0f8a249a | 2046 | if (cc == 0) |
748b9d8e | 2047 | gen_cond(r_cond, 0, cond); |
0f8a249a | 2048 | else if (cc == 2) |
748b9d8e | 2049 | gen_cond(r_cond, 1, cond); |
0f8a249a BS |
2050 | else |
2051 | goto illegal_insn; | |
3475187d | 2052 | #else |
a80dde08 | 2053 | save_state(dc); |
748b9d8e | 2054 | gen_cond(r_cond, 0, cond); |
3475187d | 2055 | #endif |
748b9d8e | 2056 | tcg_gen_helper_0_2(helper_trapcc, cpu_T[0], r_cond); |
0425bee5 | 2057 | tcg_gen_discard_tl(r_cond); |
cf495bcf | 2058 | } |
a80dde08 | 2059 | gen_op_next_insn(); |
57fec1fe | 2060 | tcg_gen_exit_tb(0); |
a80dde08 FB |
2061 | dc->is_br = 1; |
2062 | goto jmp_insn; | |
cf495bcf FB |
2063 | } else if (xop == 0x28) { |
2064 | rs1 = GET_FIELD(insn, 13, 17); | |
2065 | switch(rs1) { | |
2066 | case 0: /* rdy */ | |
65fe7b09 BS |
2067 | #ifndef TARGET_SPARC64 |
2068 | case 0x01 ... 0x0e: /* undefined in the SPARCv8 | |
2069 | manual, rdy on the microSPARC | |
2070 | II */ | |
2071 | case 0x0f: /* stbar in the SPARCv8 manual, | |
2072 | rdy on the microSPARC II */ | |
2073 | case 0x10 ... 0x1f: /* implementation-dependent in the | |
2074 | SPARCv8 manual, rdy on the | |
2075 | microSPARC II */ | |
2076 | #endif | |
2077 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, y)); | |
cf495bcf FB |
2078 | gen_movl_T0_reg(rd); |
2079 | break; | |
3475187d | 2080 | #ifdef TARGET_SPARC64 |
0f8a249a | 2081 | case 0x2: /* V9 rdccr */ |
d35527d9 | 2082 | tcg_gen_helper_1_0(helper_rdccr, cpu_T[0]); |
3475187d FB |
2083 | gen_movl_T0_reg(rd); |
2084 | break; | |
0f8a249a BS |
2085 | case 0x3: /* V9 rdasi */ |
2086 | gen_op_movl_T0_env(offsetof(CPUSPARCState, asi)); | |
3475187d FB |
2087 | gen_movl_T0_reg(rd); |
2088 | break; | |
0f8a249a | 2089 | case 0x4: /* V9 rdtick */ |
ccd4a219 BS |
2090 | { |
2091 | TCGv r_tickptr; | |
2092 | ||
2093 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
2094 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
2095 | offsetof(CPUState, tick)); | |
2096 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0], | |
2097 | r_tickptr); | |
2098 | gen_movl_T0_reg(rd); | |
0425bee5 | 2099 | tcg_gen_discard_ptr(r_tickptr); |
ccd4a219 | 2100 | } |
3475187d | 2101 | break; |
0f8a249a | 2102 | case 0x5: /* V9 rdpc */ |
1a2fb1c0 | 2103 | tcg_gen_movi_tl(cpu_T[0], dc->pc); |
0f8a249a BS |
2104 | gen_movl_T0_reg(rd); |
2105 | break; | |
2106 | case 0x6: /* V9 rdfprs */ | |
2107 | gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs)); | |
3475187d FB |
2108 | gen_movl_T0_reg(rd); |
2109 | break; | |
65fe7b09 BS |
2110 | case 0xf: /* V9 membar */ |
2111 | break; /* no effect */ | |
0f8a249a | 2112 | case 0x13: /* Graphics Status */ |
725cb90b FB |
2113 | if (gen_trap_ifnofpu(dc)) |
2114 | goto jmp_insn; | |
0f8a249a | 2115 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr)); |
725cb90b FB |
2116 | gen_movl_T0_reg(rd); |
2117 | break; | |
0f8a249a BS |
2118 | case 0x17: /* Tick compare */ |
2119 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr)); | |
83469015 FB |
2120 | gen_movl_T0_reg(rd); |
2121 | break; | |
0f8a249a | 2122 | case 0x18: /* System tick */ |
ccd4a219 BS |
2123 | { |
2124 | TCGv r_tickptr; | |
2125 | ||
2126 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
2127 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
2128 | offsetof(CPUState, stick)); | |
2129 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0], | |
2130 | r_tickptr); | |
2131 | gen_movl_T0_reg(rd); | |
0425bee5 | 2132 | tcg_gen_discard_ptr(r_tickptr); |
ccd4a219 | 2133 | } |
83469015 | 2134 | break; |
0f8a249a BS |
2135 | case 0x19: /* System tick compare */ |
2136 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr)); | |
83469015 FB |
2137 | gen_movl_T0_reg(rd); |
2138 | break; | |
0f8a249a BS |
2139 | case 0x10: /* Performance Control */ |
2140 | case 0x11: /* Performance Instrumentation Counter */ | |
2141 | case 0x12: /* Dispatch Control */ | |
2142 | case 0x14: /* Softint set, WO */ | |
2143 | case 0x15: /* Softint clear, WO */ | |
2144 | case 0x16: /* Softint write */ | |
3475187d FB |
2145 | #endif |
2146 | default: | |
cf495bcf FB |
2147 | goto illegal_insn; |
2148 | } | |
e8af50a3 | 2149 | #if !defined(CONFIG_USER_ONLY) |
e9ebed4d | 2150 | } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ |
3475187d | 2151 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
2152 | if (!supervisor(dc)) |
2153 | goto priv_insn; | |
1a2fb1c0 | 2154 | tcg_gen_helper_1_0(helper_rdpsr, cpu_T[0]); |
e9ebed4d BS |
2155 | #else |
2156 | if (!hypervisor(dc)) | |
2157 | goto priv_insn; | |
2158 | rs1 = GET_FIELD(insn, 13, 17); | |
2159 | switch (rs1) { | |
2160 | case 0: // hpstate | |
2161 | // gen_op_rdhpstate(); | |
2162 | break; | |
2163 | case 1: // htstate | |
2164 | // gen_op_rdhtstate(); | |
2165 | break; | |
2166 | case 3: // hintp | |
2167 | gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp)); | |
2168 | break; | |
2169 | case 5: // htba | |
2170 | gen_op_movl_T0_env(offsetof(CPUSPARCState, htba)); | |
2171 | break; | |
2172 | case 6: // hver | |
2173 | gen_op_movl_T0_env(offsetof(CPUSPARCState, hver)); | |
2174 | break; | |
2175 | case 31: // hstick_cmpr | |
2176 | gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr)); | |
2177 | break; | |
2178 | default: | |
2179 | goto illegal_insn; | |
2180 | } | |
2181 | #endif | |
e8af50a3 FB |
2182 | gen_movl_T0_reg(rd); |
2183 | break; | |
3475187d | 2184 | } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ |
0f8a249a BS |
2185 | if (!supervisor(dc)) |
2186 | goto priv_insn; | |
3475187d FB |
2187 | #ifdef TARGET_SPARC64 |
2188 | rs1 = GET_FIELD(insn, 13, 17); | |
0f8a249a BS |
2189 | switch (rs1) { |
2190 | case 0: // tpc | |
375ee38b BS |
2191 | { |
2192 | TCGv r_tsptr; | |
2193 | ||
2194 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
2195 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
2196 | offsetof(CPUState, tsptr)); | |
2197 | tcg_gen_ld_tl(cpu_T[0], r_tsptr, | |
2198 | offsetof(trap_state, tpc)); | |
0425bee5 | 2199 | tcg_gen_discard_ptr(r_tsptr); |
375ee38b | 2200 | } |
0f8a249a BS |
2201 | break; |
2202 | case 1: // tnpc | |
375ee38b BS |
2203 | { |
2204 | TCGv r_tsptr; | |
2205 | ||
2206 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
2207 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
2208 | offsetof(CPUState, tsptr)); | |
2209 | tcg_gen_ld_tl(cpu_T[0], r_tsptr, | |
2210 | offsetof(trap_state, tnpc)); | |
0425bee5 | 2211 | tcg_gen_discard_ptr(r_tsptr); |
375ee38b | 2212 | } |
0f8a249a BS |
2213 | break; |
2214 | case 2: // tstate | |
375ee38b BS |
2215 | { |
2216 | TCGv r_tsptr; | |
2217 | ||
2218 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
2219 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
2220 | offsetof(CPUState, tsptr)); | |
2221 | tcg_gen_ld_tl(cpu_T[0], r_tsptr, | |
2222 | offsetof(trap_state, tstate)); | |
0425bee5 | 2223 | tcg_gen_discard_ptr(r_tsptr); |
375ee38b | 2224 | } |
0f8a249a BS |
2225 | break; |
2226 | case 3: // tt | |
375ee38b BS |
2227 | { |
2228 | TCGv r_tsptr; | |
2229 | ||
2230 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
2231 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
2232 | offsetof(CPUState, tsptr)); | |
2233 | tcg_gen_ld_i32(cpu_T[0], r_tsptr, | |
2234 | offsetof(trap_state, tt)); | |
0425bee5 | 2235 | tcg_gen_discard_ptr(r_tsptr); |
375ee38b | 2236 | } |
0f8a249a BS |
2237 | break; |
2238 | case 4: // tick | |
ccd4a219 BS |
2239 | { |
2240 | TCGv r_tickptr; | |
2241 | ||
2242 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
2243 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
2244 | offsetof(CPUState, tick)); | |
2245 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0], | |
2246 | r_tickptr); | |
2247 | gen_movl_T0_reg(rd); | |
0425bee5 | 2248 | tcg_gen_discard_ptr(r_tickptr); |
ccd4a219 | 2249 | } |
0f8a249a BS |
2250 | break; |
2251 | case 5: // tba | |
2252 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); | |
2253 | break; | |
2254 | case 6: // pstate | |
1a2fb1c0 | 2255 | gen_op_movl_T0_env(offsetof(CPUSPARCState, pstate)); |
0f8a249a BS |
2256 | break; |
2257 | case 7: // tl | |
2258 | gen_op_movl_T0_env(offsetof(CPUSPARCState, tl)); | |
2259 | break; | |
2260 | case 8: // pil | |
2261 | gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil)); | |
2262 | break; | |
2263 | case 9: // cwp | |
d35527d9 | 2264 | tcg_gen_helper_1_0(helper_rdcwp, cpu_T[0]); |
0f8a249a BS |
2265 | break; |
2266 | case 10: // cansave | |
2267 | gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave)); | |
2268 | break; | |
2269 | case 11: // canrestore | |
2270 | gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore)); | |
2271 | break; | |
2272 | case 12: // cleanwin | |
2273 | gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin)); | |
2274 | break; | |
2275 | case 13: // otherwin | |
2276 | gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin)); | |
2277 | break; | |
2278 | case 14: // wstate | |
2279 | gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate)); | |
2280 | break; | |
e9ebed4d BS |
2281 | case 16: // UA2005 gl |
2282 | gen_op_movl_T0_env(offsetof(CPUSPARCState, gl)); | |
2283 | break; | |
2284 | case 26: // UA2005 strand status | |
2285 | if (!hypervisor(dc)) | |
2286 | goto priv_insn; | |
2287 | gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr)); | |
2288 | break; | |
0f8a249a BS |
2289 | case 31: // ver |
2290 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, version)); | |
2291 | break; | |
2292 | case 15: // fq | |
2293 | default: | |
2294 | goto illegal_insn; | |
2295 | } | |
3475187d | 2296 | #else |
0f8a249a | 2297 | gen_op_movl_T0_env(offsetof(CPUSPARCState, wim)); |
3475187d | 2298 | #endif |
e8af50a3 FB |
2299 | gen_movl_T0_reg(rd); |
2300 | break; | |
3475187d FB |
2301 | } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ |
2302 | #ifdef TARGET_SPARC64 | |
72a9747b | 2303 | tcg_gen_helper_0_0(helper_flushw); |
3475187d | 2304 | #else |
0f8a249a BS |
2305 | if (!supervisor(dc)) |
2306 | goto priv_insn; | |
2307 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); | |
e8af50a3 | 2308 | gen_movl_T0_reg(rd); |
3475187d | 2309 | #endif |
e8af50a3 FB |
2310 | break; |
2311 | #endif | |
0f8a249a | 2312 | } else if (xop == 0x34) { /* FPU Operations */ |
a80dde08 FB |
2313 | if (gen_trap_ifnofpu(dc)) |
2314 | goto jmp_insn; | |
0f8a249a | 2315 | gen_op_clear_ieee_excp_and_FTT(); |
e8af50a3 | 2316 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a BS |
2317 | rs2 = GET_FIELD(insn, 27, 31); |
2318 | xop = GET_FIELD(insn, 18, 26); | |
2319 | switch (xop) { | |
2320 | case 0x1: /* fmovs */ | |
2321 | gen_op_load_fpr_FT0(rs2); | |
2322 | gen_op_store_FT0_fpr(rd); | |
2323 | break; | |
2324 | case 0x5: /* fnegs */ | |
2325 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 2326 | tcg_gen_helper_0_0(helper_fnegs); |
0f8a249a BS |
2327 | gen_op_store_FT0_fpr(rd); |
2328 | break; | |
2329 | case 0x9: /* fabss */ | |
2330 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2331 | tcg_gen_helper_0_0(helper_fabss); |
0f8a249a BS |
2332 | gen_op_store_FT0_fpr(rd); |
2333 | break; | |
2334 | case 0x29: /* fsqrts */ | |
2335 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c BS |
2336 | gen_clear_float_exceptions(); |
2337 | tcg_gen_helper_0_0(helper_fsqrts); | |
2338 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); | |
0f8a249a BS |
2339 | gen_op_store_FT0_fpr(rd); |
2340 | break; | |
2341 | case 0x2a: /* fsqrtd */ | |
2342 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c BS |
2343 | gen_clear_float_exceptions(); |
2344 | tcg_gen_helper_0_0(helper_fsqrtd); | |
2345 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); | |
0f8a249a BS |
2346 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2347 | break; | |
2348 | case 0x2b: /* fsqrtq */ | |
1f587329 BS |
2349 | #if defined(CONFIG_USER_ONLY) |
2350 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c BS |
2351 | gen_clear_float_exceptions(); |
2352 | tcg_gen_helper_0_0(helper_fsqrtq); | |
2353 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); | |
1f587329 BS |
2354 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2355 | break; | |
2356 | #else | |
0f8a249a | 2357 | goto nfpu_insn; |
1f587329 | 2358 | #endif |
0f8a249a BS |
2359 | case 0x41: |
2360 | gen_op_load_fpr_FT0(rs1); | |
2361 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2362 | gen_clear_float_exceptions(); |
44e7757c | 2363 | tcg_gen_helper_0_0(helper_fadds); |
7e8c2b6c | 2364 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2365 | gen_op_store_FT0_fpr(rd); |
2366 | break; | |
2367 | case 0x42: | |
2368 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
2369 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2370 | gen_clear_float_exceptions(); |
44e7757c | 2371 | tcg_gen_helper_0_0(helper_faddd); |
7e8c2b6c | 2372 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2373 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2374 | break; | |
2375 | case 0x43: /* faddq */ | |
1f587329 BS |
2376 | #if defined(CONFIG_USER_ONLY) |
2377 | gen_op_load_fpr_QT0(QFPREG(rs1)); | |
2378 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2379 | gen_clear_float_exceptions(); |
44e7757c | 2380 | tcg_gen_helper_0_0(helper_faddq); |
7e8c2b6c | 2381 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2382 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2383 | break; | |
2384 | #else | |
0f8a249a | 2385 | goto nfpu_insn; |
1f587329 | 2386 | #endif |
0f8a249a BS |
2387 | case 0x45: |
2388 | gen_op_load_fpr_FT0(rs1); | |
2389 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2390 | gen_clear_float_exceptions(); |
44e7757c | 2391 | tcg_gen_helper_0_0(helper_fsubs); |
7e8c2b6c | 2392 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2393 | gen_op_store_FT0_fpr(rd); |
2394 | break; | |
2395 | case 0x46: | |
2396 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
2397 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2398 | gen_clear_float_exceptions(); |
44e7757c | 2399 | tcg_gen_helper_0_0(helper_fsubd); |
7e8c2b6c | 2400 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2401 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2402 | break; | |
2403 | case 0x47: /* fsubq */ | |
1f587329 BS |
2404 | #if defined(CONFIG_USER_ONLY) |
2405 | gen_op_load_fpr_QT0(QFPREG(rs1)); | |
2406 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2407 | gen_clear_float_exceptions(); |
44e7757c | 2408 | tcg_gen_helper_0_0(helper_fsubq); |
7e8c2b6c | 2409 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2410 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2411 | break; | |
2412 | #else | |
0f8a249a | 2413 | goto nfpu_insn; |
1f587329 | 2414 | #endif |
0f8a249a BS |
2415 | case 0x49: |
2416 | gen_op_load_fpr_FT0(rs1); | |
2417 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2418 | gen_clear_float_exceptions(); |
44e7757c | 2419 | tcg_gen_helper_0_0(helper_fmuls); |
7e8c2b6c | 2420 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2421 | gen_op_store_FT0_fpr(rd); |
2422 | break; | |
2423 | case 0x4a: | |
2424 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
2425 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2426 | gen_clear_float_exceptions(); |
44e7757c | 2427 | tcg_gen_helper_0_0(helper_fmuld); |
7e8c2b6c | 2428 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2382dc6b | 2429 | gen_op_store_DT0_fpr(DFPREG(rd)); |
0f8a249a BS |
2430 | break; |
2431 | case 0x4b: /* fmulq */ | |
1f587329 BS |
2432 | #if defined(CONFIG_USER_ONLY) |
2433 | gen_op_load_fpr_QT0(QFPREG(rs1)); | |
2434 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2435 | gen_clear_float_exceptions(); |
44e7757c | 2436 | tcg_gen_helper_0_0(helper_fmulq); |
7e8c2b6c | 2437 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2438 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2439 | break; | |
2440 | #else | |
0f8a249a | 2441 | goto nfpu_insn; |
1f587329 | 2442 | #endif |
0f8a249a BS |
2443 | case 0x4d: |
2444 | gen_op_load_fpr_FT0(rs1); | |
2445 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2446 | gen_clear_float_exceptions(); |
44e7757c | 2447 | tcg_gen_helper_0_0(helper_fdivs); |
7e8c2b6c | 2448 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2449 | gen_op_store_FT0_fpr(rd); |
2450 | break; | |
2451 | case 0x4e: | |
2452 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
2453 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2454 | gen_clear_float_exceptions(); |
44e7757c | 2455 | tcg_gen_helper_0_0(helper_fdivd); |
7e8c2b6c | 2456 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2457 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2458 | break; | |
2459 | case 0x4f: /* fdivq */ | |
1f587329 BS |
2460 | #if defined(CONFIG_USER_ONLY) |
2461 | gen_op_load_fpr_QT0(QFPREG(rs1)); | |
2462 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2463 | gen_clear_float_exceptions(); |
44e7757c | 2464 | tcg_gen_helper_0_0(helper_fdivq); |
7e8c2b6c | 2465 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2466 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2467 | break; | |
2468 | #else | |
0f8a249a | 2469 | goto nfpu_insn; |
1f587329 | 2470 | #endif |
0f8a249a BS |
2471 | case 0x69: |
2472 | gen_op_load_fpr_FT0(rs1); | |
2473 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2474 | gen_clear_float_exceptions(); |
44e7757c | 2475 | tcg_gen_helper_0_0(helper_fsmuld); |
7e8c2b6c | 2476 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2477 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2478 | break; | |
2479 | case 0x6e: /* fdmulq */ | |
1f587329 BS |
2480 | #if defined(CONFIG_USER_ONLY) |
2481 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
2482 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2483 | gen_clear_float_exceptions(); |
44e7757c | 2484 | tcg_gen_helper_0_0(helper_fdmulq); |
7e8c2b6c | 2485 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2486 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2487 | break; | |
2488 | #else | |
0f8a249a | 2489 | goto nfpu_insn; |
1f587329 | 2490 | #endif |
0f8a249a BS |
2491 | case 0xc4: |
2492 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2493 | gen_clear_float_exceptions(); |
44e7757c | 2494 | tcg_gen_helper_0_0(helper_fitos); |
7e8c2b6c | 2495 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2496 | gen_op_store_FT0_fpr(rd); |
2497 | break; | |
2498 | case 0xc6: | |
2499 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2500 | gen_clear_float_exceptions(); |
44e7757c | 2501 | tcg_gen_helper_0_0(helper_fdtos); |
7e8c2b6c | 2502 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2503 | gen_op_store_FT0_fpr(rd); |
2504 | break; | |
2505 | case 0xc7: /* fqtos */ | |
1f587329 BS |
2506 | #if defined(CONFIG_USER_ONLY) |
2507 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2508 | gen_clear_float_exceptions(); |
44e7757c | 2509 | tcg_gen_helper_0_0(helper_fqtos); |
7e8c2b6c | 2510 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2511 | gen_op_store_FT0_fpr(rd); |
2512 | break; | |
2513 | #else | |
0f8a249a | 2514 | goto nfpu_insn; |
1f587329 | 2515 | #endif |
0f8a249a BS |
2516 | case 0xc8: |
2517 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 2518 | tcg_gen_helper_0_0(helper_fitod); |
0f8a249a BS |
2519 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2520 | break; | |
2521 | case 0xc9: | |
2522 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 2523 | tcg_gen_helper_0_0(helper_fstod); |
0f8a249a BS |
2524 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2525 | break; | |
2526 | case 0xcb: /* fqtod */ | |
1f587329 BS |
2527 | #if defined(CONFIG_USER_ONLY) |
2528 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2529 | gen_clear_float_exceptions(); |
44e7757c | 2530 | tcg_gen_helper_0_0(helper_fqtod); |
7e8c2b6c | 2531 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2532 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2533 | break; | |
2534 | #else | |
0f8a249a | 2535 | goto nfpu_insn; |
1f587329 | 2536 | #endif |
0f8a249a | 2537 | case 0xcc: /* fitoq */ |
1f587329 BS |
2538 | #if defined(CONFIG_USER_ONLY) |
2539 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 2540 | tcg_gen_helper_0_0(helper_fitoq); |
1f587329 BS |
2541 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2542 | break; | |
2543 | #else | |
0f8a249a | 2544 | goto nfpu_insn; |
1f587329 | 2545 | #endif |
0f8a249a | 2546 | case 0xcd: /* fstoq */ |
1f587329 BS |
2547 | #if defined(CONFIG_USER_ONLY) |
2548 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 2549 | tcg_gen_helper_0_0(helper_fstoq); |
1f587329 BS |
2550 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2551 | break; | |
2552 | #else | |
0f8a249a | 2553 | goto nfpu_insn; |
1f587329 | 2554 | #endif |
0f8a249a | 2555 | case 0xce: /* fdtoq */ |
1f587329 BS |
2556 | #if defined(CONFIG_USER_ONLY) |
2557 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 2558 | tcg_gen_helper_0_0(helper_fdtoq); |
1f587329 BS |
2559 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2560 | break; | |
2561 | #else | |
0f8a249a | 2562 | goto nfpu_insn; |
1f587329 | 2563 | #endif |
0f8a249a BS |
2564 | case 0xd1: |
2565 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2566 | gen_clear_float_exceptions(); |
44e7757c | 2567 | tcg_gen_helper_0_0(helper_fstoi); |
7e8c2b6c | 2568 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2569 | gen_op_store_FT0_fpr(rd); |
2570 | break; | |
2571 | case 0xd2: | |
2382dc6b | 2572 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
7e8c2b6c | 2573 | gen_clear_float_exceptions(); |
44e7757c | 2574 | tcg_gen_helper_0_0(helper_fdtoi); |
7e8c2b6c | 2575 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2576 | gen_op_store_FT0_fpr(rd); |
2577 | break; | |
2578 | case 0xd3: /* fqtoi */ | |
1f587329 BS |
2579 | #if defined(CONFIG_USER_ONLY) |
2580 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2581 | gen_clear_float_exceptions(); |
44e7757c | 2582 | tcg_gen_helper_0_0(helper_fqtoi); |
7e8c2b6c | 2583 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2584 | gen_op_store_FT0_fpr(rd); |
2585 | break; | |
2586 | #else | |
0f8a249a | 2587 | goto nfpu_insn; |
1f587329 | 2588 | #endif |
3475187d | 2589 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
2590 | case 0x2: /* V9 fmovd */ |
2591 | gen_op_load_fpr_DT0(DFPREG(rs2)); | |
2592 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
2593 | break; | |
1f587329 BS |
2594 | case 0x3: /* V9 fmovq */ |
2595 | #if defined(CONFIG_USER_ONLY) | |
2596 | gen_op_load_fpr_QT0(QFPREG(rs2)); | |
2597 | gen_op_store_QT0_fpr(QFPREG(rd)); | |
2598 | break; | |
2599 | #else | |
2600 | goto nfpu_insn; | |
2601 | #endif | |
0f8a249a BS |
2602 | case 0x6: /* V9 fnegd */ |
2603 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 2604 | tcg_gen_helper_0_0(helper_fnegd); |
0f8a249a BS |
2605 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2606 | break; | |
1f587329 BS |
2607 | case 0x7: /* V9 fnegq */ |
2608 | #if defined(CONFIG_USER_ONLY) | |
2609 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
44e7757c | 2610 | tcg_gen_helper_0_0(helper_fnegq); |
1f587329 BS |
2611 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2612 | break; | |
2613 | #else | |
2614 | goto nfpu_insn; | |
2615 | #endif | |
0f8a249a BS |
2616 | case 0xa: /* V9 fabsd */ |
2617 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2618 | tcg_gen_helper_0_0(helper_fabsd); |
0f8a249a BS |
2619 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2620 | break; | |
1f587329 BS |
2621 | case 0xb: /* V9 fabsq */ |
2622 | #if defined(CONFIG_USER_ONLY) | |
2623 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2624 | tcg_gen_helper_0_0(helper_fabsq); |
1f587329 BS |
2625 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2626 | break; | |
2627 | #else | |
2628 | goto nfpu_insn; | |
2629 | #endif | |
0f8a249a BS |
2630 | case 0x81: /* V9 fstox */ |
2631 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2632 | gen_clear_float_exceptions(); |
44e7757c | 2633 | tcg_gen_helper_0_0(helper_fstox); |
7e8c2b6c | 2634 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2635 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2636 | break; | |
2637 | case 0x82: /* V9 fdtox */ | |
2638 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2639 | gen_clear_float_exceptions(); |
44e7757c | 2640 | tcg_gen_helper_0_0(helper_fdtox); |
7e8c2b6c | 2641 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2642 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2643 | break; | |
1f587329 BS |
2644 | case 0x83: /* V9 fqtox */ |
2645 | #if defined(CONFIG_USER_ONLY) | |
2646 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2647 | gen_clear_float_exceptions(); |
44e7757c | 2648 | tcg_gen_helper_0_0(helper_fqtox); |
7e8c2b6c | 2649 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2650 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2651 | break; | |
2652 | #else | |
2653 | goto nfpu_insn; | |
2654 | #endif | |
0f8a249a BS |
2655 | case 0x84: /* V9 fxtos */ |
2656 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2657 | gen_clear_float_exceptions(); |
44e7757c | 2658 | tcg_gen_helper_0_0(helper_fxtos); |
7e8c2b6c | 2659 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2660 | gen_op_store_FT0_fpr(rd); |
2661 | break; | |
2662 | case 0x88: /* V9 fxtod */ | |
2663 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2664 | gen_clear_float_exceptions(); |
44e7757c | 2665 | tcg_gen_helper_0_0(helper_fxtod); |
7e8c2b6c | 2666 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2667 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2668 | break; | |
0f8a249a | 2669 | case 0x8c: /* V9 fxtoq */ |
1f587329 BS |
2670 | #if defined(CONFIG_USER_ONLY) |
2671 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2672 | gen_clear_float_exceptions(); |
44e7757c | 2673 | tcg_gen_helper_0_0(helper_fxtoq); |
7e8c2b6c | 2674 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2675 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2676 | break; | |
2677 | #else | |
0f8a249a | 2678 | goto nfpu_insn; |
1f587329 | 2679 | #endif |
0f8a249a BS |
2680 | #endif |
2681 | default: | |
2682 | goto illegal_insn; | |
2683 | } | |
2684 | } else if (xop == 0x35) { /* FPU Operations */ | |
3475187d | 2685 | #ifdef TARGET_SPARC64 |
0f8a249a | 2686 | int cond; |
3475187d | 2687 | #endif |
a80dde08 FB |
2688 | if (gen_trap_ifnofpu(dc)) |
2689 | goto jmp_insn; | |
0f8a249a | 2690 | gen_op_clear_ieee_excp_and_FTT(); |
cf495bcf | 2691 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a BS |
2692 | rs2 = GET_FIELD(insn, 27, 31); |
2693 | xop = GET_FIELD(insn, 18, 26); | |
3475187d | 2694 | #ifdef TARGET_SPARC64 |
0f8a249a | 2695 | if ((xop & 0x11f) == 0x005) { // V9 fmovsr |
dcf24905 BS |
2696 | int l1; |
2697 | ||
2698 | l1 = gen_new_label(); | |
0f8a249a | 2699 | cond = GET_FIELD_SP(insn, 14, 17); |
0f8a249a BS |
2700 | rs1 = GET_FIELD(insn, 13, 17); |
2701 | gen_movl_reg_T0(rs1); | |
0425bee5 BS |
2702 | tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], |
2703 | tcg_const_tl(0), l1); | |
19f329ad | 2704 | gen_op_load_fpr_FT0(rs2); |
0f8a249a | 2705 | gen_op_store_FT0_fpr(rd); |
dcf24905 | 2706 | gen_set_label(l1); |
0f8a249a BS |
2707 | break; |
2708 | } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr | |
dcf24905 BS |
2709 | int l1; |
2710 | ||
2711 | l1 = gen_new_label(); | |
0f8a249a | 2712 | cond = GET_FIELD_SP(insn, 14, 17); |
0f8a249a BS |
2713 | rs1 = GET_FIELD(insn, 13, 17); |
2714 | gen_movl_reg_T0(rs1); | |
0425bee5 BS |
2715 | tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], |
2716 | tcg_const_tl(0), l1); | |
19f329ad | 2717 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
2382dc6b | 2718 | gen_op_store_DT0_fpr(DFPREG(rd)); |
dcf24905 | 2719 | gen_set_label(l1); |
0f8a249a BS |
2720 | break; |
2721 | } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr | |
1f587329 | 2722 | #if defined(CONFIG_USER_ONLY) |
dcf24905 BS |
2723 | int l1; |
2724 | ||
2725 | l1 = gen_new_label(); | |
1f587329 | 2726 | cond = GET_FIELD_SP(insn, 14, 17); |
1f587329 BS |
2727 | rs1 = GET_FIELD(insn, 13, 17); |
2728 | gen_movl_reg_T0(rs1); | |
0425bee5 BS |
2729 | tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], |
2730 | tcg_const_tl(0), l1); | |
19f329ad | 2731 | gen_op_load_fpr_QT0(QFPREG(rs2)); |
1f587329 | 2732 | gen_op_store_QT0_fpr(QFPREG(rd)); |
dcf24905 | 2733 | gen_set_label(l1); |
1f587329 BS |
2734 | break; |
2735 | #else | |
0f8a249a | 2736 | goto nfpu_insn; |
1f587329 | 2737 | #endif |
0f8a249a BS |
2738 | } |
2739 | #endif | |
2740 | switch (xop) { | |
3475187d | 2741 | #ifdef TARGET_SPARC64 |
19f329ad BS |
2742 | #define FMOVCC(size_FDQ, fcc) \ |
2743 | { \ | |
0425bee5 | 2744 | TCGv r_cond; \ |
19f329ad BS |
2745 | int l1; \ |
2746 | \ | |
2747 | l1 = gen_new_label(); \ | |
19f329ad | 2748 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ |
19f329ad BS |
2749 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2750 | gen_fcond(r_cond, fcc, cond); \ | |
0425bee5 BS |
2751 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \ |
2752 | tcg_const_tl(0), l1); \ | |
19f329ad BS |
2753 | glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \ |
2754 | glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \ | |
2755 | gen_set_label(l1); \ | |
0425bee5 | 2756 | tcg_gen_discard_tl(r_cond); \ |
19f329ad | 2757 | } |
0f8a249a | 2758 | case 0x001: /* V9 fmovscc %fcc0 */ |
19f329ad | 2759 | FMOVCC(F, 0); |
0f8a249a BS |
2760 | break; |
2761 | case 0x002: /* V9 fmovdcc %fcc0 */ | |
19f329ad | 2762 | FMOVCC(D, 0); |
0f8a249a BS |
2763 | break; |
2764 | case 0x003: /* V9 fmovqcc %fcc0 */ | |
1f587329 | 2765 | #if defined(CONFIG_USER_ONLY) |
19f329ad | 2766 | FMOVCC(Q, 0); |
1f587329 BS |
2767 | break; |
2768 | #else | |
0f8a249a | 2769 | goto nfpu_insn; |
1f587329 | 2770 | #endif |
0f8a249a | 2771 | case 0x041: /* V9 fmovscc %fcc1 */ |
19f329ad | 2772 | FMOVCC(F, 1); |
0f8a249a BS |
2773 | break; |
2774 | case 0x042: /* V9 fmovdcc %fcc1 */ | |
19f329ad | 2775 | FMOVCC(D, 1); |
0f8a249a BS |
2776 | break; |
2777 | case 0x043: /* V9 fmovqcc %fcc1 */ | |
1f587329 | 2778 | #if defined(CONFIG_USER_ONLY) |
19f329ad | 2779 | FMOVCC(Q, 1); |
1f587329 BS |
2780 | break; |
2781 | #else | |
0f8a249a | 2782 | goto nfpu_insn; |
1f587329 | 2783 | #endif |
0f8a249a | 2784 | case 0x081: /* V9 fmovscc %fcc2 */ |
19f329ad | 2785 | FMOVCC(F, 2); |
0f8a249a BS |
2786 | break; |
2787 | case 0x082: /* V9 fmovdcc %fcc2 */ | |
19f329ad | 2788 | FMOVCC(D, 2); |
0f8a249a BS |
2789 | break; |
2790 | case 0x083: /* V9 fmovqcc %fcc2 */ | |
1f587329 | 2791 | #if defined(CONFIG_USER_ONLY) |
19f329ad | 2792 | FMOVCC(Q, 2); |
1f587329 BS |
2793 | break; |
2794 | #else | |
0f8a249a | 2795 | goto nfpu_insn; |
1f587329 | 2796 | #endif |
0f8a249a | 2797 | case 0x0c1: /* V9 fmovscc %fcc3 */ |
19f329ad | 2798 | FMOVCC(F, 3); |
0f8a249a BS |
2799 | break; |
2800 | case 0x0c2: /* V9 fmovdcc %fcc3 */ | |
19f329ad | 2801 | FMOVCC(D, 3); |
0f8a249a BS |
2802 | break; |
2803 | case 0x0c3: /* V9 fmovqcc %fcc3 */ | |
1f587329 | 2804 | #if defined(CONFIG_USER_ONLY) |
19f329ad | 2805 | FMOVCC(Q, 3); |
1f587329 BS |
2806 | break; |
2807 | #else | |
0f8a249a | 2808 | goto nfpu_insn; |
1f587329 | 2809 | #endif |
19f329ad BS |
2810 | #undef FMOVCC |
2811 | #define FMOVCC(size_FDQ, icc) \ | |
2812 | { \ | |
0425bee5 | 2813 | TCGv r_cond; \ |
19f329ad BS |
2814 | int l1; \ |
2815 | \ | |
2816 | l1 = gen_new_label(); \ | |
19f329ad | 2817 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ |
19f329ad BS |
2818 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2819 | gen_cond(r_cond, icc, cond); \ | |
0425bee5 BS |
2820 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \ |
2821 | tcg_const_tl(0), l1); \ | |
19f329ad BS |
2822 | glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \ |
2823 | glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \ | |
2824 | gen_set_label(l1); \ | |
0425bee5 | 2825 | tcg_gen_discard_tl(r_cond); \ |
19f329ad BS |
2826 | } |
2827 | ||
0f8a249a | 2828 | case 0x101: /* V9 fmovscc %icc */ |
19f329ad | 2829 | FMOVCC(F, 0); |
0f8a249a BS |
2830 | break; |
2831 | case 0x102: /* V9 fmovdcc %icc */ | |
19f329ad | 2832 | FMOVCC(D, 0); |
0f8a249a | 2833 | case 0x103: /* V9 fmovqcc %icc */ |
1f587329 | 2834 | #if defined(CONFIG_USER_ONLY) |
19f329ad | 2835 | FMOVCC(D, 0); |
1f587329 BS |
2836 | break; |
2837 | #else | |
0f8a249a | 2838 | goto nfpu_insn; |
1f587329 | 2839 | #endif |
0f8a249a | 2840 | case 0x181: /* V9 fmovscc %xcc */ |
19f329ad | 2841 | FMOVCC(F, 1); |
0f8a249a BS |
2842 | break; |
2843 | case 0x182: /* V9 fmovdcc %xcc */ | |
19f329ad | 2844 | FMOVCC(D, 1); |
0f8a249a BS |
2845 | break; |
2846 | case 0x183: /* V9 fmovqcc %xcc */ | |
1f587329 | 2847 | #if defined(CONFIG_USER_ONLY) |
19f329ad | 2848 | FMOVCC(Q, 1); |
1f587329 BS |
2849 | break; |
2850 | #else | |
0f8a249a BS |
2851 | goto nfpu_insn; |
2852 | #endif | |
19f329ad | 2853 | #undef FMOVCC |
1f587329 BS |
2854 | #endif |
2855 | case 0x51: /* fcmps, V9 %fcc */ | |
0f8a249a BS |
2856 | gen_op_load_fpr_FT0(rs1); |
2857 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2858 | gen_op_fcmps(rd & 3); |
0f8a249a | 2859 | break; |
1f587329 | 2860 | case 0x52: /* fcmpd, V9 %fcc */ |
0f8a249a BS |
2861 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2862 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2863 | gen_op_fcmpd(rd & 3); |
0f8a249a | 2864 | break; |
1f587329 BS |
2865 | case 0x53: /* fcmpq, V9 %fcc */ |
2866 | #if defined(CONFIG_USER_ONLY) | |
2867 | gen_op_load_fpr_QT0(QFPREG(rs1)); | |
2868 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2869 | gen_op_fcmpq(rd & 3); |
1f587329 BS |
2870 | break; |
2871 | #else /* !defined(CONFIG_USER_ONLY) */ | |
0f8a249a | 2872 | goto nfpu_insn; |
1f587329 | 2873 | #endif |
0f8a249a BS |
2874 | case 0x55: /* fcmpes, V9 %fcc */ |
2875 | gen_op_load_fpr_FT0(rs1); | |
2876 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2877 | gen_op_fcmpes(rd & 3); |
0f8a249a BS |
2878 | break; |
2879 | case 0x56: /* fcmped, V9 %fcc */ | |
2880 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
2881 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2882 | gen_op_fcmped(rd & 3); |
0f8a249a | 2883 | break; |
1f587329 BS |
2884 | case 0x57: /* fcmpeq, V9 %fcc */ |
2885 | #if defined(CONFIG_USER_ONLY) | |
2886 | gen_op_load_fpr_QT0(QFPREG(rs1)); | |
2887 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2888 | gen_op_fcmpeq(rd & 3); |
1f587329 BS |
2889 | break; |
2890 | #else/* !defined(CONFIG_USER_ONLY) */ | |
0f8a249a | 2891 | goto nfpu_insn; |
1f587329 | 2892 | #endif |
0f8a249a BS |
2893 | default: |
2894 | goto illegal_insn; | |
2895 | } | |
e80cfcfc | 2896 | #if defined(OPTIM) |
0f8a249a BS |
2897 | } else if (xop == 0x2) { |
2898 | // clr/mov shortcut | |
e80cfcfc FB |
2899 | |
2900 | rs1 = GET_FIELD(insn, 13, 17); | |
0f8a249a | 2901 | if (rs1 == 0) { |
1a2fb1c0 | 2902 | // or %g0, x, y -> mov T0, x; mov y, T0 |
0f8a249a BS |
2903 | if (IS_IMM) { /* immediate */ |
2904 | rs2 = GET_FIELDs(insn, 19, 31); | |
1a2fb1c0 | 2905 | tcg_gen_movi_tl(cpu_T[0], (int)rs2); |
0f8a249a BS |
2906 | } else { /* register */ |
2907 | rs2 = GET_FIELD(insn, 27, 31); | |
1a2fb1c0 | 2908 | gen_movl_reg_T0(rs2); |
0f8a249a | 2909 | } |
0f8a249a BS |
2910 | } else { |
2911 | gen_movl_reg_T0(rs1); | |
2912 | if (IS_IMM) { /* immediate */ | |
0f8a249a | 2913 | rs2 = GET_FIELDs(insn, 19, 31); |
1a2fb1c0 | 2914 | tcg_gen_ori_tl(cpu_T[0], cpu_T[0], (int)rs2); |
0f8a249a BS |
2915 | } else { /* register */ |
2916 | // or x, %g0, y -> mov T1, x; mov y, T1 | |
2917 | rs2 = GET_FIELD(insn, 27, 31); | |
2918 | if (rs2 != 0) { | |
2919 | gen_movl_reg_T1(rs2); | |
2920 | gen_op_or_T1_T0(); | |
2921 | } | |
2922 | } | |
0f8a249a | 2923 | } |
1a2fb1c0 | 2924 | gen_movl_T0_reg(rd); |
83469015 FB |
2925 | #endif |
2926 | #ifdef TARGET_SPARC64 | |
0f8a249a | 2927 | } else if (xop == 0x25) { /* sll, V9 sllx */ |
83469015 | 2928 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a BS |
2929 | gen_movl_reg_T0(rs1); |
2930 | if (IS_IMM) { /* immediate */ | |
83469015 | 2931 | rs2 = GET_FIELDs(insn, 20, 31); |
1a2fb1c0 BS |
2932 | if (insn & (1 << 12)) { |
2933 | tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f); | |
2934 | } else { | |
2935 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); | |
2936 | tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f); | |
2937 | } | |
0f8a249a | 2938 | } else { /* register */ |
83469015 FB |
2939 | rs2 = GET_FIELD(insn, 27, 31); |
2940 | gen_movl_reg_T1(rs2); | |
1a2fb1c0 BS |
2941 | if (insn & (1 << 12)) { |
2942 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f); | |
2943 | tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]); | |
2944 | } else { | |
2945 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f); | |
2946 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); | |
2947 | tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]); | |
2948 | } | |
83469015 | 2949 | } |
0f8a249a BS |
2950 | gen_movl_T0_reg(rd); |
2951 | } else if (xop == 0x26) { /* srl, V9 srlx */ | |
83469015 | 2952 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a BS |
2953 | gen_movl_reg_T0(rs1); |
2954 | if (IS_IMM) { /* immediate */ | |
83469015 | 2955 | rs2 = GET_FIELDs(insn, 20, 31); |
1a2fb1c0 BS |
2956 | if (insn & (1 << 12)) { |
2957 | tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f); | |
2958 | } else { | |
2959 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); | |
2960 | tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f); | |
2961 | } | |
0f8a249a | 2962 | } else { /* register */ |
83469015 FB |
2963 | rs2 = GET_FIELD(insn, 27, 31); |
2964 | gen_movl_reg_T1(rs2); | |
1a2fb1c0 BS |
2965 | if (insn & (1 << 12)) { |
2966 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f); | |
2967 | tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]); | |
2968 | } else { | |
2969 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f); | |
2970 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); | |
2971 | tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]); | |
2972 | } | |
83469015 | 2973 | } |
0f8a249a BS |
2974 | gen_movl_T0_reg(rd); |
2975 | } else if (xop == 0x27) { /* sra, V9 srax */ | |
83469015 | 2976 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a BS |
2977 | gen_movl_reg_T0(rs1); |
2978 | if (IS_IMM) { /* immediate */ | |
83469015 | 2979 | rs2 = GET_FIELDs(insn, 20, 31); |
1a2fb1c0 BS |
2980 | if (insn & (1 << 12)) { |
2981 | tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f); | |
2982 | } else { | |
2983 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); | |
2984 | tcg_gen_ext_i32_i64(cpu_T[0], cpu_T[0]); | |
2985 | tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f); | |
2986 | } | |
0f8a249a | 2987 | } else { /* register */ |
83469015 FB |
2988 | rs2 = GET_FIELD(insn, 27, 31); |
2989 | gen_movl_reg_T1(rs2); | |
1a2fb1c0 BS |
2990 | if (insn & (1 << 12)) { |
2991 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f); | |
2992 | tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]); | |
2993 | } else { | |
2994 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f); | |
2995 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); | |
2996 | tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]); | |
2997 | } | |
83469015 | 2998 | } |
0f8a249a | 2999 | gen_movl_T0_reg(rd); |
e80cfcfc | 3000 | #endif |
fcc72045 | 3001 | } else if (xop < 0x36) { |
e80cfcfc | 3002 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a BS |
3003 | gen_movl_reg_T0(rs1); |
3004 | if (IS_IMM) { /* immediate */ | |
cf495bcf | 3005 | rs2 = GET_FIELDs(insn, 19, 31); |
3475187d | 3006 | gen_movl_simm_T1(rs2); |
0f8a249a | 3007 | } else { /* register */ |
cf495bcf FB |
3008 | rs2 = GET_FIELD(insn, 27, 31); |
3009 | gen_movl_reg_T1(rs2); | |
3010 | } | |
3011 | if (xop < 0x20) { | |
3012 | switch (xop & ~0x10) { | |
3013 | case 0x0: | |
3014 | if (xop & 0x10) | |
3015 | gen_op_add_T1_T0_cc(); | |
3016 | else | |
3017 | gen_op_add_T1_T0(); | |
3018 | break; | |
3019 | case 0x1: | |
1a2fb1c0 | 3020 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cf495bcf FB |
3021 | if (xop & 0x10) |
3022 | gen_op_logic_T0_cc(); | |
3023 | break; | |
3024 | case 0x2: | |
1a2fb1c0 | 3025 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
0f8a249a BS |
3026 | if (xop & 0x10) |
3027 | gen_op_logic_T0_cc(); | |
3028 | break; | |
cf495bcf | 3029 | case 0x3: |
1a2fb1c0 | 3030 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cf495bcf FB |
3031 | if (xop & 0x10) |
3032 | gen_op_logic_T0_cc(); | |
3033 | break; | |
3034 | case 0x4: | |
3035 | if (xop & 0x10) | |
3036 | gen_op_sub_T1_T0_cc(); | |
3037 | else | |
1a2fb1c0 | 3038 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cf495bcf FB |
3039 | break; |
3040 | case 0x5: | |
56ec06bb BS |
3041 | tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1); |
3042 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
cf495bcf FB |
3043 | if (xop & 0x10) |
3044 | gen_op_logic_T0_cc(); | |
3045 | break; | |
3046 | case 0x6: | |
56ec06bb BS |
3047 | tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1); |
3048 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
cf495bcf FB |
3049 | if (xop & 0x10) |
3050 | gen_op_logic_T0_cc(); | |
3051 | break; | |
3052 | case 0x7: | |
56ec06bb BS |
3053 | tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1); |
3054 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
cf495bcf FB |
3055 | if (xop & 0x10) |
3056 | gen_op_logic_T0_cc(); | |
3057 | break; | |
3058 | case 0x8: | |
cf495bcf | 3059 | if (xop & 0x10) |
af7bf89b | 3060 | gen_op_addx_T1_T0_cc(); |
38bc628b | 3061 | else { |
dc99a3f2 | 3062 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
38bc628b BS |
3063 | tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0); |
3064 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
3065 | } | |
cf495bcf | 3066 | break; |
ded3ab80 | 3067 | #ifdef TARGET_SPARC64 |
0f8a249a | 3068 | case 0x9: /* V9 mulx */ |
1a2fb1c0 | 3069 | tcg_gen_mul_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
ded3ab80 PB |
3070 | break; |
3071 | #endif | |
cf495bcf FB |
3072 | case 0xa: |
3073 | gen_op_umul_T1_T0(); | |
3074 | if (xop & 0x10) | |
3075 | gen_op_logic_T0_cc(); | |
3076 | break; | |
3077 | case 0xb: | |
3078 | gen_op_smul_T1_T0(); | |
3079 | if (xop & 0x10) | |
3080 | gen_op_logic_T0_cc(); | |
3081 | break; | |
3082 | case 0xc: | |
cf495bcf | 3083 | if (xop & 0x10) |
af7bf89b | 3084 | gen_op_subx_T1_T0_cc(); |
38bc628b | 3085 | else { |
dc99a3f2 | 3086 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
38bc628b BS |
3087 | tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0); |
3088 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
3089 | } | |
cf495bcf | 3090 | break; |
ded3ab80 | 3091 | #ifdef TARGET_SPARC64 |
0f8a249a | 3092 | case 0xd: /* V9 udivx */ |
1a7b60e7 BS |
3093 | gen_trap_ifdivzero_i64(cpu_T[1]); |
3094 | tcg_gen_divu_i64(cpu_T[0], cpu_T[0], cpu_T[1]); | |
ded3ab80 PB |
3095 | break; |
3096 | #endif | |
cf495bcf FB |
3097 | case 0xe: |
3098 | gen_op_udiv_T1_T0(); | |
3099 | if (xop & 0x10) | |
3100 | gen_op_div_cc(); | |
3101 | break; | |
3102 | case 0xf: | |
3103 | gen_op_sdiv_T1_T0(); | |
3104 | if (xop & 0x10) | |
3105 | gen_op_div_cc(); | |
3106 | break; | |
3107 | default: | |
3108 | goto illegal_insn; | |
3109 | } | |
0f8a249a | 3110 | gen_movl_T0_reg(rd); |
cf495bcf FB |
3111 | } else { |
3112 | switch (xop) { | |
0f8a249a BS |
3113 | case 0x20: /* taddcc */ |
3114 | gen_op_tadd_T1_T0_cc(); | |
3115 | gen_movl_T0_reg(rd); | |
3116 | break; | |
3117 | case 0x21: /* tsubcc */ | |
3118 | gen_op_tsub_T1_T0_cc(); | |
3119 | gen_movl_T0_reg(rd); | |
3120 | break; | |
3121 | case 0x22: /* taddcctv */ | |
90251fb9 | 3122 | save_state(dc); |
0f8a249a BS |
3123 | gen_op_tadd_T1_T0_ccTV(); |
3124 | gen_movl_T0_reg(rd); | |
3125 | break; | |
3126 | case 0x23: /* tsubcctv */ | |
90251fb9 | 3127 | save_state(dc); |
0f8a249a BS |
3128 | gen_op_tsub_T1_T0_ccTV(); |
3129 | gen_movl_T0_reg(rd); | |
3130 | break; | |
cf495bcf FB |
3131 | case 0x24: /* mulscc */ |
3132 | gen_op_mulscc_T1_T0(); | |
3133 | gen_movl_T0_reg(rd); | |
3134 | break; | |
83469015 | 3135 | #ifndef TARGET_SPARC64 |
0f8a249a | 3136 | case 0x25: /* sll */ |
1a2fb1c0 BS |
3137 | tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f); |
3138 | tcg_gen_shl_i32(cpu_T[0], cpu_T[0], cpu_T[1]); | |
cf495bcf FB |
3139 | gen_movl_T0_reg(rd); |
3140 | break; | |
83469015 | 3141 | case 0x26: /* srl */ |
1a2fb1c0 BS |
3142 | tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f); |
3143 | tcg_gen_shr_i32(cpu_T[0], cpu_T[0], cpu_T[1]); | |
cf495bcf FB |
3144 | gen_movl_T0_reg(rd); |
3145 | break; | |
83469015 | 3146 | case 0x27: /* sra */ |
1a2fb1c0 BS |
3147 | tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f); |
3148 | tcg_gen_sar_i32(cpu_T[0], cpu_T[0], cpu_T[1]); | |
cf495bcf FB |
3149 | gen_movl_T0_reg(rd); |
3150 | break; | |
83469015 | 3151 | #endif |
cf495bcf FB |
3152 | case 0x30: |
3153 | { | |
cf495bcf | 3154 | switch(rd) { |
3475187d | 3155 | case 0: /* wry */ |
0f8a249a BS |
3156 | gen_op_xor_T1_T0(); |
3157 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, y)); | |
cf495bcf | 3158 | break; |
65fe7b09 BS |
3159 | #ifndef TARGET_SPARC64 |
3160 | case 0x01 ... 0x0f: /* undefined in the | |
3161 | SPARCv8 manual, nop | |
3162 | on the microSPARC | |
3163 | II */ | |
3164 | case 0x10 ... 0x1f: /* implementation-dependent | |
3165 | in the SPARCv8 | |
3166 | manual, nop on the | |
3167 | microSPARC II */ | |
3168 | break; | |
3169 | #else | |
0f8a249a | 3170 | case 0x2: /* V9 wrccr */ |
ee0b03fd | 3171 | gen_op_xor_T1_T0(); |
d35527d9 | 3172 | tcg_gen_helper_0_1(helper_wrccr, cpu_T[0]); |
0f8a249a BS |
3173 | break; |
3174 | case 0x3: /* V9 wrasi */ | |
ee0b03fd | 3175 | gen_op_xor_T1_T0(); |
0f8a249a BS |
3176 | gen_op_movl_env_T0(offsetof(CPUSPARCState, asi)); |
3177 | break; | |
3178 | case 0x6: /* V9 wrfprs */ | |
3179 | gen_op_xor_T1_T0(); | |
3180 | gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs)); | |
3299908c BS |
3181 | save_state(dc); |
3182 | gen_op_next_insn(); | |
57fec1fe | 3183 | tcg_gen_exit_tb(0); |
3299908c | 3184 | dc->is_br = 1; |
0f8a249a BS |
3185 | break; |
3186 | case 0xf: /* V9 sir, nop if user */ | |
3475187d | 3187 | #if !defined(CONFIG_USER_ONLY) |
0f8a249a | 3188 | if (supervisor(dc)) |
1a2fb1c0 | 3189 | ; // XXX |
3475187d | 3190 | #endif |
0f8a249a BS |
3191 | break; |
3192 | case 0x13: /* Graphics Status */ | |
725cb90b FB |
3193 | if (gen_trap_ifnofpu(dc)) |
3194 | goto jmp_insn; | |
ee0b03fd | 3195 | gen_op_xor_T1_T0(); |
0f8a249a BS |
3196 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr)); |
3197 | break; | |
3198 | case 0x17: /* Tick compare */ | |
83469015 | 3199 | #if !defined(CONFIG_USER_ONLY) |
0f8a249a BS |
3200 | if (!supervisor(dc)) |
3201 | goto illegal_insn; | |
83469015 | 3202 | #endif |
ccd4a219 BS |
3203 | { |
3204 | TCGv r_tickptr; | |
3205 | ||
3206 | gen_op_xor_T1_T0(); | |
3207 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, | |
3208 | tick_cmpr)); | |
3209 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
3210 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
3211 | offsetof(CPUState, tick)); | |
3212 | tcg_gen_helper_0_2(helper_tick_set_limit, | |
3213 | r_tickptr, cpu_T[0]); | |
0425bee5 | 3214 | tcg_gen_discard_ptr(r_tickptr); |
ccd4a219 | 3215 | } |
0f8a249a BS |
3216 | break; |
3217 | case 0x18: /* System tick */ | |
83469015 | 3218 | #if !defined(CONFIG_USER_ONLY) |
0f8a249a BS |
3219 | if (!supervisor(dc)) |
3220 | goto illegal_insn; | |
83469015 | 3221 | #endif |
ccd4a219 BS |
3222 | { |
3223 | TCGv r_tickptr; | |
3224 | ||
3225 | gen_op_xor_T1_T0(); | |
3226 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
3227 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
3228 | offsetof(CPUState, stick)); | |
3229 | tcg_gen_helper_0_2(helper_tick_set_count, | |
3230 | r_tickptr, cpu_T[0]); | |
0425bee5 | 3231 | tcg_gen_discard_ptr(r_tickptr); |
ccd4a219 | 3232 | } |
0f8a249a BS |
3233 | break; |
3234 | case 0x19: /* System tick compare */ | |
83469015 | 3235 | #if !defined(CONFIG_USER_ONLY) |
0f8a249a BS |
3236 | if (!supervisor(dc)) |
3237 | goto illegal_insn; | |
3475187d | 3238 | #endif |
ccd4a219 BS |
3239 | { |
3240 | TCGv r_tickptr; | |
3241 | ||
3242 | gen_op_xor_T1_T0(); | |
3243 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, | |
3244 | stick_cmpr)); | |
3245 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
3246 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
3247 | offsetof(CPUState, stick)); | |
3248 | tcg_gen_helper_0_2(helper_tick_set_limit, | |
3249 | r_tickptr, cpu_T[0]); | |
0425bee5 | 3250 | tcg_gen_discard_ptr(r_tickptr); |
ccd4a219 | 3251 | } |
0f8a249a | 3252 | break; |
83469015 | 3253 | |
0f8a249a BS |
3254 | case 0x10: /* Performance Control */ |
3255 | case 0x11: /* Performance Instrumentation Counter */ | |
3256 | case 0x12: /* Dispatch Control */ | |
3257 | case 0x14: /* Softint set */ | |
3258 | case 0x15: /* Softint clear */ | |
3259 | case 0x16: /* Softint write */ | |
83469015 | 3260 | #endif |
3475187d | 3261 | default: |
cf495bcf FB |
3262 | goto illegal_insn; |
3263 | } | |
3264 | } | |
3265 | break; | |
e8af50a3 | 3266 | #if !defined(CONFIG_USER_ONLY) |
af7bf89b | 3267 | case 0x31: /* wrpsr, V9 saved, restored */ |
e8af50a3 | 3268 | { |
0f8a249a BS |
3269 | if (!supervisor(dc)) |
3270 | goto priv_insn; | |
3475187d | 3271 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
3272 | switch (rd) { |
3273 | case 0: | |
72a9747b | 3274 | tcg_gen_helper_0_0(helper_saved); |
0f8a249a BS |
3275 | break; |
3276 | case 1: | |
72a9747b | 3277 | tcg_gen_helper_0_0(helper_restored); |
0f8a249a | 3278 | break; |
e9ebed4d BS |
3279 | case 2: /* UA2005 allclean */ |
3280 | case 3: /* UA2005 otherw */ | |
3281 | case 4: /* UA2005 normalw */ | |
3282 | case 5: /* UA2005 invalw */ | |
3283 | // XXX | |
0f8a249a | 3284 | default: |
3475187d FB |
3285 | goto illegal_insn; |
3286 | } | |
3287 | #else | |
e8af50a3 | 3288 | gen_op_xor_T1_T0(); |
1a2fb1c0 | 3289 | tcg_gen_helper_0_1(helper_wrpsr, cpu_T[0]); |
9e61bde5 FB |
3290 | save_state(dc); |
3291 | gen_op_next_insn(); | |
57fec1fe | 3292 | tcg_gen_exit_tb(0); |
0f8a249a | 3293 | dc->is_br = 1; |
3475187d | 3294 | #endif |
e8af50a3 FB |
3295 | } |
3296 | break; | |
af7bf89b | 3297 | case 0x32: /* wrwim, V9 wrpr */ |
e8af50a3 | 3298 | { |
0f8a249a BS |
3299 | if (!supervisor(dc)) |
3300 | goto priv_insn; | |
e8af50a3 | 3301 | gen_op_xor_T1_T0(); |
3475187d | 3302 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
3303 | switch (rd) { |
3304 | case 0: // tpc | |
375ee38b BS |
3305 | { |
3306 | TCGv r_tsptr; | |
3307 | ||
3308 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
3309 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
3310 | offsetof(CPUState, tsptr)); | |
3311 | tcg_gen_st_tl(cpu_T[0], r_tsptr, | |
3312 | offsetof(trap_state, tpc)); | |
0425bee5 | 3313 | tcg_gen_discard_ptr(r_tsptr); |
375ee38b | 3314 | } |
0f8a249a BS |
3315 | break; |
3316 | case 1: // tnpc | |
375ee38b BS |
3317 | { |
3318 | TCGv r_tsptr; | |
3319 | ||
3320 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
3321 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
3322 | offsetof(CPUState, tsptr)); | |
3323 | tcg_gen_st_tl(cpu_T[0], r_tsptr, | |
3324 | offsetof(trap_state, tnpc)); | |
0425bee5 | 3325 | tcg_gen_discard_ptr(r_tsptr); |
375ee38b | 3326 | } |
0f8a249a BS |
3327 | break; |
3328 | case 2: // tstate | |
375ee38b BS |
3329 | { |
3330 | TCGv r_tsptr; | |
3331 | ||
3332 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
3333 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
3334 | offsetof(CPUState, tsptr)); | |
3335 | tcg_gen_st_tl(cpu_T[0], r_tsptr, | |
3336 | offsetof(trap_state, tstate)); | |
0425bee5 | 3337 | tcg_gen_discard_ptr(r_tsptr); |
375ee38b | 3338 | } |
0f8a249a BS |
3339 | break; |
3340 | case 3: // tt | |
375ee38b BS |
3341 | { |
3342 | TCGv r_tsptr; | |
3343 | ||
3344 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
3345 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
3346 | offsetof(CPUState, tsptr)); | |
3347 | tcg_gen_st_i32(cpu_T[0], r_tsptr, | |
3348 | offsetof(trap_state, tt)); | |
0425bee5 | 3349 | tcg_gen_discard_ptr(r_tsptr); |
375ee38b | 3350 | } |
0f8a249a BS |
3351 | break; |
3352 | case 4: // tick | |
ccd4a219 BS |
3353 | { |
3354 | TCGv r_tickptr; | |
3355 | ||
3356 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
3357 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
3358 | offsetof(CPUState, tick)); | |
3359 | tcg_gen_helper_0_2(helper_tick_set_count, | |
3360 | r_tickptr, cpu_T[0]); | |
0425bee5 | 3361 | tcg_gen_discard_ptr(r_tickptr); |
ccd4a219 | 3362 | } |
0f8a249a BS |
3363 | break; |
3364 | case 5: // tba | |
3365 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); | |
3366 | break; | |
3367 | case 6: // pstate | |
ded3ab80 | 3368 | save_state(dc); |
1a2fb1c0 | 3369 | tcg_gen_helper_0_1(helper_wrpstate, cpu_T[0]); |
ded3ab80 | 3370 | gen_op_next_insn(); |
57fec1fe | 3371 | tcg_gen_exit_tb(0); |
ded3ab80 | 3372 | dc->is_br = 1; |
0f8a249a BS |
3373 | break; |
3374 | case 7: // tl | |
3375 | gen_op_movl_env_T0(offsetof(CPUSPARCState, tl)); | |
3376 | break; | |
3377 | case 8: // pil | |
3378 | gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil)); | |
3379 | break; | |
3380 | case 9: // cwp | |
d35527d9 | 3381 | tcg_gen_helper_0_1(helper_wrcwp, cpu_T[0]); |
0f8a249a BS |
3382 | break; |
3383 | case 10: // cansave | |
3384 | gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave)); | |
3385 | break; | |
3386 | case 11: // canrestore | |
3387 | gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore)); | |
3388 | break; | |
3389 | case 12: // cleanwin | |
3390 | gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin)); | |
3391 | break; | |
3392 | case 13: // otherwin | |
3393 | gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin)); | |
3394 | break; | |
3395 | case 14: // wstate | |
3396 | gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate)); | |
3397 | break; | |
e9ebed4d BS |
3398 | case 16: // UA2005 gl |
3399 | gen_op_movl_env_T0(offsetof(CPUSPARCState, gl)); | |
3400 | break; | |
3401 | case 26: // UA2005 strand status | |
3402 | if (!hypervisor(dc)) | |
3403 | goto priv_insn; | |
3404 | gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr)); | |
3405 | break; | |
0f8a249a BS |
3406 | default: |
3407 | goto illegal_insn; | |
3408 | } | |
3475187d | 3409 | #else |
1a2fb1c0 BS |
3410 | tcg_gen_andi_i32(cpu_T[0], cpu_T[0], ((1 << NWINDOWS) - 1)); |
3411 | gen_op_movl_env_T0(offsetof(CPUSPARCState, wim)); | |
3475187d | 3412 | #endif |
e8af50a3 FB |
3413 | } |
3414 | break; | |
e9ebed4d | 3415 | case 0x33: /* wrtbr, UA2005 wrhpr */ |
e8af50a3 | 3416 | { |
e9ebed4d | 3417 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
3418 | if (!supervisor(dc)) |
3419 | goto priv_insn; | |
e8af50a3 | 3420 | gen_op_xor_T1_T0(); |
e9ebed4d BS |
3421 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); |
3422 | #else | |
3423 | if (!hypervisor(dc)) | |
3424 | goto priv_insn; | |
3425 | gen_op_xor_T1_T0(); | |
3426 | switch (rd) { | |
3427 | case 0: // hpstate | |
3428 | // XXX gen_op_wrhpstate(); | |
3429 | save_state(dc); | |
3430 | gen_op_next_insn(); | |
57fec1fe | 3431 | tcg_gen_exit_tb(0); |
e9ebed4d BS |
3432 | dc->is_br = 1; |
3433 | break; | |
3434 | case 1: // htstate | |
3435 | // XXX gen_op_wrhtstate(); | |
3436 | break; | |
3437 | case 3: // hintp | |
3438 | gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp)); | |
3439 | break; | |
3440 | case 5: // htba | |
3441 | gen_op_movl_env_T0(offsetof(CPUSPARCState, htba)); | |
3442 | break; | |
3443 | case 31: // hstick_cmpr | |
ccd4a219 BS |
3444 | { |
3445 | TCGv r_tickptr; | |
3446 | ||
3447 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, | |
3448 | hstick_cmpr)); | |
3449 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
3450 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
3451 | offsetof(CPUState, hstick)); | |
3452 | tcg_gen_helper_0_2(helper_tick_set_limit, | |
3453 | r_tickptr, cpu_T[0]); | |
0425bee5 | 3454 | tcg_gen_discard_ptr(r_tickptr); |
ccd4a219 | 3455 | } |
e9ebed4d BS |
3456 | break; |
3457 | case 6: // hver readonly | |
3458 | default: | |
3459 | goto illegal_insn; | |
3460 | } | |
3461 | #endif | |
e8af50a3 FB |
3462 | } |
3463 | break; | |
3464 | #endif | |
3475187d | 3465 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
3466 | case 0x2c: /* V9 movcc */ |
3467 | { | |
3468 | int cc = GET_FIELD_SP(insn, 11, 12); | |
3469 | int cond = GET_FIELD_SP(insn, 14, 17); | |
748b9d8e | 3470 | TCGv r_cond; |
00f219bf BS |
3471 | int l1; |
3472 | ||
748b9d8e | 3473 | r_cond = tcg_temp_new(TCG_TYPE_TL); |
0f8a249a BS |
3474 | if (insn & (1 << 18)) { |
3475 | if (cc == 0) | |
748b9d8e | 3476 | gen_cond(r_cond, 0, cond); |
0f8a249a | 3477 | else if (cc == 2) |
748b9d8e | 3478 | gen_cond(r_cond, 1, cond); |
0f8a249a BS |
3479 | else |
3480 | goto illegal_insn; | |
3481 | } else { | |
748b9d8e | 3482 | gen_fcond(r_cond, cc, cond); |
0f8a249a | 3483 | } |
00f219bf BS |
3484 | |
3485 | l1 = gen_new_label(); | |
3486 | ||
748b9d8e BS |
3487 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, |
3488 | tcg_const_tl(0), l1); | |
00f219bf BS |
3489 | if (IS_IMM) { /* immediate */ |
3490 | rs2 = GET_FIELD_SPs(insn, 0, 10); | |
3491 | gen_movl_simm_T1(rs2); | |
3492 | } else { | |
3493 | rs2 = GET_FIELD_SP(insn, 0, 4); | |
3494 | gen_movl_reg_T1(rs2); | |
3495 | } | |
3496 | gen_movl_T1_reg(rd); | |
3497 | gen_set_label(l1); | |
0425bee5 | 3498 | tcg_gen_discard_tl(r_cond); |
0f8a249a BS |
3499 | break; |
3500 | } | |
3501 | case 0x2d: /* V9 sdivx */ | |
3475187d | 3502 | gen_op_sdivx_T1_T0(); |
0f8a249a BS |
3503 | gen_movl_T0_reg(rd); |
3504 | break; | |
3505 | case 0x2e: /* V9 popc */ | |
3506 | { | |
3507 | if (IS_IMM) { /* immediate */ | |
3508 | rs2 = GET_FIELD_SPs(insn, 0, 12); | |
3509 | gen_movl_simm_T1(rs2); | |
3510 | // XXX optimize: popc(constant) | |
3511 | } | |
3512 | else { | |
3513 | rs2 = GET_FIELD_SP(insn, 0, 4); | |
3514 | gen_movl_reg_T1(rs2); | |
3515 | } | |
1a2fb1c0 BS |
3516 | tcg_gen_helper_1_1(helper_popc, cpu_T[0], |
3517 | cpu_T[1]); | |
0f8a249a BS |
3518 | gen_movl_T0_reg(rd); |
3519 | } | |
3520 | case 0x2f: /* V9 movr */ | |
3521 | { | |
3522 | int cond = GET_FIELD_SP(insn, 10, 12); | |
00f219bf BS |
3523 | int l1; |
3524 | ||
0f8a249a | 3525 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a | 3526 | gen_movl_reg_T0(rs1); |
00f219bf BS |
3527 | |
3528 | l1 = gen_new_label(); | |
3529 | ||
0425bee5 BS |
3530 | tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], |
3531 | tcg_const_tl(0), l1); | |
0f8a249a BS |
3532 | if (IS_IMM) { /* immediate */ |
3533 | rs2 = GET_FIELD_SPs(insn, 0, 9); | |
3534 | gen_movl_simm_T1(rs2); | |
00f219bf | 3535 | } else { |
0f8a249a BS |
3536 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3537 | gen_movl_reg_T1(rs2); | |
3538 | } | |
00f219bf BS |
3539 | gen_movl_T1_reg(rd); |
3540 | gen_set_label(l1); | |
0f8a249a BS |
3541 | break; |
3542 | } | |
3543 | #endif | |
3544 | default: | |
3545 | goto illegal_insn; | |
3546 | } | |
3547 | } | |
3299908c BS |
3548 | } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ |
3549 | #ifdef TARGET_SPARC64 | |
3550 | int opf = GET_FIELD_SP(insn, 5, 13); | |
3551 | rs1 = GET_FIELD(insn, 13, 17); | |
3552 | rs2 = GET_FIELD(insn, 27, 31); | |
e9ebed4d BS |
3553 | if (gen_trap_ifnofpu(dc)) |
3554 | goto jmp_insn; | |
3299908c BS |
3555 | |
3556 | switch (opf) { | |
e9ebed4d BS |
3557 | case 0x000: /* VIS I edge8cc */ |
3558 | case 0x001: /* VIS II edge8n */ | |
3559 | case 0x002: /* VIS I edge8lcc */ | |
3560 | case 0x003: /* VIS II edge8ln */ | |
3561 | case 0x004: /* VIS I edge16cc */ | |
3562 | case 0x005: /* VIS II edge16n */ | |
3563 | case 0x006: /* VIS I edge16lcc */ | |
3564 | case 0x007: /* VIS II edge16ln */ | |
3565 | case 0x008: /* VIS I edge32cc */ | |
3566 | case 0x009: /* VIS II edge32n */ | |
3567 | case 0x00a: /* VIS I edge32lcc */ | |
3568 | case 0x00b: /* VIS II edge32ln */ | |
3569 | // XXX | |
3570 | goto illegal_insn; | |
3571 | case 0x010: /* VIS I array8 */ | |
3572 | gen_movl_reg_T0(rs1); | |
3573 | gen_movl_reg_T1(rs2); | |
1f5063fb BS |
3574 | tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0], |
3575 | cpu_T[1]); | |
e9ebed4d BS |
3576 | gen_movl_T0_reg(rd); |
3577 | break; | |
3578 | case 0x012: /* VIS I array16 */ | |
3579 | gen_movl_reg_T0(rs1); | |
3580 | gen_movl_reg_T1(rs2); | |
1f5063fb BS |
3581 | tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0], |
3582 | cpu_T[1]); | |
3583 | tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 1); | |
e9ebed4d BS |
3584 | gen_movl_T0_reg(rd); |
3585 | break; | |
3586 | case 0x014: /* VIS I array32 */ | |
3587 | gen_movl_reg_T0(rs1); | |
3588 | gen_movl_reg_T1(rs2); | |
1f5063fb BS |
3589 | tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0], |
3590 | cpu_T[1]); | |
3591 | tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 2); | |
e9ebed4d BS |
3592 | gen_movl_T0_reg(rd); |
3593 | break; | |
3299908c | 3594 | case 0x018: /* VIS I alignaddr */ |
3299908c BS |
3595 | gen_movl_reg_T0(rs1); |
3596 | gen_movl_reg_T1(rs2); | |
1f5063fb BS |
3597 | tcg_gen_helper_1_2(helper_alignaddr, cpu_T[0], cpu_T[0], |
3598 | cpu_T[1]); | |
3299908c BS |
3599 | gen_movl_T0_reg(rd); |
3600 | break; | |
e9ebed4d | 3601 | case 0x019: /* VIS II bmask */ |
3299908c | 3602 | case 0x01a: /* VIS I alignaddrl */ |
3299908c | 3603 | // XXX |
e9ebed4d BS |
3604 | goto illegal_insn; |
3605 | case 0x020: /* VIS I fcmple16 */ | |
2382dc6b BS |
3606 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3607 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3608 | tcg_gen_helper_0_0(helper_fcmple16); |
2382dc6b | 3609 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3610 | break; |
3611 | case 0x022: /* VIS I fcmpne16 */ | |
2382dc6b BS |
3612 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3613 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3614 | tcg_gen_helper_0_0(helper_fcmpne16); |
2382dc6b | 3615 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3299908c | 3616 | break; |
e9ebed4d | 3617 | case 0x024: /* VIS I fcmple32 */ |
2382dc6b BS |
3618 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3619 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3620 | tcg_gen_helper_0_0(helper_fcmple32); |
2382dc6b | 3621 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3622 | break; |
3623 | case 0x026: /* VIS I fcmpne32 */ | |
2382dc6b BS |
3624 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3625 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3626 | tcg_gen_helper_0_0(helper_fcmpne32); |
2382dc6b | 3627 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3628 | break; |
3629 | case 0x028: /* VIS I fcmpgt16 */ | |
2382dc6b BS |
3630 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3631 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3632 | tcg_gen_helper_0_0(helper_fcmpgt16); |
2382dc6b | 3633 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3634 | break; |
3635 | case 0x02a: /* VIS I fcmpeq16 */ | |
2382dc6b BS |
3636 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3637 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3638 | tcg_gen_helper_0_0(helper_fcmpeq16); |
2382dc6b | 3639 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3640 | break; |
3641 | case 0x02c: /* VIS I fcmpgt32 */ | |
2382dc6b BS |
3642 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3643 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3644 | tcg_gen_helper_0_0(helper_fcmpgt32); |
2382dc6b | 3645 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3646 | break; |
3647 | case 0x02e: /* VIS I fcmpeq32 */ | |
2382dc6b BS |
3648 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3649 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3650 | tcg_gen_helper_0_0(helper_fcmpeq32); |
2382dc6b | 3651 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3652 | break; |
3653 | case 0x031: /* VIS I fmul8x16 */ | |
2382dc6b BS |
3654 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3655 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3656 | tcg_gen_helper_0_0(helper_fmul8x16); |
2382dc6b | 3657 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3658 | break; |
3659 | case 0x033: /* VIS I fmul8x16au */ | |
2382dc6b BS |
3660 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3661 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3662 | tcg_gen_helper_0_0(helper_fmul8x16au); |
2382dc6b | 3663 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3664 | break; |
3665 | case 0x035: /* VIS I fmul8x16al */ | |
2382dc6b BS |
3666 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3667 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3668 | tcg_gen_helper_0_0(helper_fmul8x16al); |
2382dc6b | 3669 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3670 | break; |
3671 | case 0x036: /* VIS I fmul8sux16 */ | |
2382dc6b BS |
3672 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3673 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3674 | tcg_gen_helper_0_0(helper_fmul8sux16); |
2382dc6b | 3675 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3676 | break; |
3677 | case 0x037: /* VIS I fmul8ulx16 */ | |
2382dc6b BS |
3678 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3679 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3680 | tcg_gen_helper_0_0(helper_fmul8ulx16); |
2382dc6b | 3681 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3682 | break; |
3683 | case 0x038: /* VIS I fmuld8sux16 */ | |
2382dc6b BS |
3684 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3685 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3686 | tcg_gen_helper_0_0(helper_fmuld8sux16); |
2382dc6b | 3687 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3688 | break; |
3689 | case 0x039: /* VIS I fmuld8ulx16 */ | |
2382dc6b BS |
3690 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3691 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3692 | tcg_gen_helper_0_0(helper_fmuld8ulx16); |
2382dc6b | 3693 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3694 | break; |
3695 | case 0x03a: /* VIS I fpack32 */ | |
3696 | case 0x03b: /* VIS I fpack16 */ | |
3697 | case 0x03d: /* VIS I fpackfix */ | |
3698 | case 0x03e: /* VIS I pdist */ | |
3699 | // XXX | |
3700 | goto illegal_insn; | |
3299908c | 3701 | case 0x048: /* VIS I faligndata */ |
2382dc6b BS |
3702 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3703 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3704 | tcg_gen_helper_0_0(helper_faligndata); |
2382dc6b | 3705 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3299908c | 3706 | break; |
e9ebed4d | 3707 | case 0x04b: /* VIS I fpmerge */ |
2382dc6b BS |
3708 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3709 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3710 | tcg_gen_helper_0_0(helper_fpmerge); |
2382dc6b | 3711 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3712 | break; |
3713 | case 0x04c: /* VIS II bshuffle */ | |
3714 | // XXX | |
3715 | goto illegal_insn; | |
3716 | case 0x04d: /* VIS I fexpand */ | |
2382dc6b BS |
3717 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3718 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3719 | tcg_gen_helper_0_0(helper_fexpand); |
2382dc6b | 3720 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3721 | break; |
3722 | case 0x050: /* VIS I fpadd16 */ | |
2382dc6b BS |
3723 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3724 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3725 | tcg_gen_helper_0_0(helper_fpadd16); |
2382dc6b | 3726 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3727 | break; |
3728 | case 0x051: /* VIS I fpadd16s */ | |
3729 | gen_op_load_fpr_FT0(rs1); | |
3730 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3731 | tcg_gen_helper_0_0(helper_fpadd16s); |
e9ebed4d BS |
3732 | gen_op_store_FT0_fpr(rd); |
3733 | break; | |
3734 | case 0x052: /* VIS I fpadd32 */ | |
2382dc6b BS |
3735 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3736 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3737 | tcg_gen_helper_0_0(helper_fpadd32); |
2382dc6b | 3738 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3739 | break; |
3740 | case 0x053: /* VIS I fpadd32s */ | |
3741 | gen_op_load_fpr_FT0(rs1); | |
3742 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3743 | tcg_gen_helper_0_0(helper_fpadd32s); |
e9ebed4d BS |
3744 | gen_op_store_FT0_fpr(rd); |
3745 | break; | |
3746 | case 0x054: /* VIS I fpsub16 */ | |
2382dc6b BS |
3747 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3748 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3749 | tcg_gen_helper_0_0(helper_fpsub16); |
2382dc6b | 3750 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3751 | break; |
3752 | case 0x055: /* VIS I fpsub16s */ | |
3753 | gen_op_load_fpr_FT0(rs1); | |
3754 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3755 | tcg_gen_helper_0_0(helper_fpsub16s); |
e9ebed4d BS |
3756 | gen_op_store_FT0_fpr(rd); |
3757 | break; | |
3758 | case 0x056: /* VIS I fpsub32 */ | |
2382dc6b BS |
3759 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3760 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3761 | tcg_gen_helper_0_0(helper_fpadd32); |
2382dc6b | 3762 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3763 | break; |
3764 | case 0x057: /* VIS I fpsub32s */ | |
3765 | gen_op_load_fpr_FT0(rs1); | |
3766 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3767 | tcg_gen_helper_0_0(helper_fpsub32s); |
e9ebed4d BS |
3768 | gen_op_store_FT0_fpr(rd); |
3769 | break; | |
3299908c | 3770 | case 0x060: /* VIS I fzero */ |
44e7757c | 3771 | tcg_gen_helper_0_0(helper_movl_DT0_0); |
2382dc6b | 3772 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3299908c BS |
3773 | break; |
3774 | case 0x061: /* VIS I fzeros */ | |
44e7757c | 3775 | tcg_gen_helper_0_0(helper_movl_FT0_0); |
3299908c BS |
3776 | gen_op_store_FT0_fpr(rd); |
3777 | break; | |
e9ebed4d | 3778 | case 0x062: /* VIS I fnor */ |
2382dc6b BS |
3779 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3780 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3781 | tcg_gen_helper_0_0(helper_fnor); |
2382dc6b | 3782 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3783 | break; |
3784 | case 0x063: /* VIS I fnors */ | |
3785 | gen_op_load_fpr_FT0(rs1); | |
3786 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3787 | tcg_gen_helper_0_0(helper_fnors); |
e9ebed4d BS |
3788 | gen_op_store_FT0_fpr(rd); |
3789 | break; | |
3790 | case 0x064: /* VIS I fandnot2 */ | |
2382dc6b BS |
3791 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
3792 | gen_op_load_fpr_DT0(DFPREG(rs2)); | |
44e7757c | 3793 | tcg_gen_helper_0_0(helper_fandnot); |
2382dc6b | 3794 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3795 | break; |
3796 | case 0x065: /* VIS I fandnot2s */ | |
3797 | gen_op_load_fpr_FT1(rs1); | |
3798 | gen_op_load_fpr_FT0(rs2); | |
44e7757c | 3799 | tcg_gen_helper_0_0(helper_fandnots); |
e9ebed4d BS |
3800 | gen_op_store_FT0_fpr(rd); |
3801 | break; | |
3802 | case 0x066: /* VIS I fnot2 */ | |
2382dc6b | 3803 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
44e7757c | 3804 | tcg_gen_helper_0_0(helper_fnot); |
2382dc6b | 3805 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3806 | break; |
3807 | case 0x067: /* VIS I fnot2s */ | |
3808 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3809 | tcg_gen_helper_0_0(helper_fnot); |
e9ebed4d BS |
3810 | gen_op_store_FT0_fpr(rd); |
3811 | break; | |
3812 | case 0x068: /* VIS I fandnot1 */ | |
2382dc6b BS |
3813 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3814 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3815 | tcg_gen_helper_0_0(helper_fandnot); |
2382dc6b | 3816 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3817 | break; |
3818 | case 0x069: /* VIS I fandnot1s */ | |
3819 | gen_op_load_fpr_FT0(rs1); | |
3820 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3821 | tcg_gen_helper_0_0(helper_fandnots); |
e9ebed4d BS |
3822 | gen_op_store_FT0_fpr(rd); |
3823 | break; | |
3824 | case 0x06a: /* VIS I fnot1 */ | |
2382dc6b | 3825 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
44e7757c | 3826 | tcg_gen_helper_0_0(helper_fnot); |
2382dc6b | 3827 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3828 | break; |
3829 | case 0x06b: /* VIS I fnot1s */ | |
3830 | gen_op_load_fpr_FT1(rs1); | |
44e7757c | 3831 | tcg_gen_helper_0_0(helper_fnot); |
e9ebed4d BS |
3832 | gen_op_store_FT0_fpr(rd); |
3833 | break; | |
3834 | case 0x06c: /* VIS I fxor */ | |
2382dc6b BS |
3835 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3836 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3837 | tcg_gen_helper_0_0(helper_fxor); |
2382dc6b | 3838 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3839 | break; |
3840 | case 0x06d: /* VIS I fxors */ | |
3841 | gen_op_load_fpr_FT0(rs1); | |
3842 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3843 | tcg_gen_helper_0_0(helper_fxors); |
e9ebed4d BS |
3844 | gen_op_store_FT0_fpr(rd); |
3845 | break; | |
3846 | case 0x06e: /* VIS I fnand */ | |
2382dc6b BS |
3847 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3848 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3849 | tcg_gen_helper_0_0(helper_fnand); |
2382dc6b | 3850 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3851 | break; |
3852 | case 0x06f: /* VIS I fnands */ | |
3853 | gen_op_load_fpr_FT0(rs1); | |
3854 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3855 | tcg_gen_helper_0_0(helper_fnands); |
e9ebed4d BS |
3856 | gen_op_store_FT0_fpr(rd); |
3857 | break; | |
3858 | case 0x070: /* VIS I fand */ | |
2382dc6b BS |
3859 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3860 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3861 | tcg_gen_helper_0_0(helper_fand); |
2382dc6b | 3862 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3863 | break; |
3864 | case 0x071: /* VIS I fands */ | |
3865 | gen_op_load_fpr_FT0(rs1); | |
3866 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3867 | tcg_gen_helper_0_0(helper_fands); |
e9ebed4d BS |
3868 | gen_op_store_FT0_fpr(rd); |
3869 | break; | |
3870 | case 0x072: /* VIS I fxnor */ | |
2382dc6b BS |
3871 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3872 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3873 | tcg_gen_helper_0_0(helper_fxnor); |
2382dc6b | 3874 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3875 | break; |
3876 | case 0x073: /* VIS I fxnors */ | |
3877 | gen_op_load_fpr_FT0(rs1); | |
3878 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3879 | tcg_gen_helper_0_0(helper_fxnors); |
e9ebed4d BS |
3880 | gen_op_store_FT0_fpr(rd); |
3881 | break; | |
3299908c | 3882 | case 0x074: /* VIS I fsrc1 */ |
2382dc6b BS |
3883 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3884 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
3299908c BS |
3885 | break; |
3886 | case 0x075: /* VIS I fsrc1s */ | |
3299908c BS |
3887 | gen_op_load_fpr_FT0(rs1); |
3888 | gen_op_store_FT0_fpr(rd); | |
3889 | break; | |
e9ebed4d | 3890 | case 0x076: /* VIS I fornot2 */ |
2382dc6b BS |
3891 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
3892 | gen_op_load_fpr_DT0(DFPREG(rs2)); | |
44e7757c | 3893 | tcg_gen_helper_0_0(helper_fornot); |
2382dc6b | 3894 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3895 | break; |
3896 | case 0x077: /* VIS I fornot2s */ | |
3897 | gen_op_load_fpr_FT1(rs1); | |
3898 | gen_op_load_fpr_FT0(rs2); | |
44e7757c | 3899 | tcg_gen_helper_0_0(helper_fornots); |
e9ebed4d BS |
3900 | gen_op_store_FT0_fpr(rd); |
3901 | break; | |
3299908c | 3902 | case 0x078: /* VIS I fsrc2 */ |
2382dc6b BS |
3903 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
3904 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
3299908c BS |
3905 | break; |
3906 | case 0x079: /* VIS I fsrc2s */ | |
3299908c BS |
3907 | gen_op_load_fpr_FT0(rs2); |
3908 | gen_op_store_FT0_fpr(rd); | |
3909 | break; | |
e9ebed4d | 3910 | case 0x07a: /* VIS I fornot1 */ |
2382dc6b BS |
3911 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3912 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3913 | tcg_gen_helper_0_0(helper_fornot); |
2382dc6b | 3914 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3915 | break; |
3916 | case 0x07b: /* VIS I fornot1s */ | |
3917 | gen_op_load_fpr_FT0(rs1); | |
3918 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3919 | tcg_gen_helper_0_0(helper_fornots); |
e9ebed4d BS |
3920 | gen_op_store_FT0_fpr(rd); |
3921 | break; | |
3922 | case 0x07c: /* VIS I for */ | |
2382dc6b BS |
3923 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3924 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3925 | tcg_gen_helper_0_0(helper_for); |
2382dc6b | 3926 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3927 | break; |
3928 | case 0x07d: /* VIS I fors */ | |
3929 | gen_op_load_fpr_FT0(rs1); | |
3930 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3931 | tcg_gen_helper_0_0(helper_fors); |
e9ebed4d BS |
3932 | gen_op_store_FT0_fpr(rd); |
3933 | break; | |
3299908c | 3934 | case 0x07e: /* VIS I fone */ |
44e7757c | 3935 | tcg_gen_helper_0_0(helper_movl_DT0_1); |
2382dc6b | 3936 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3299908c BS |
3937 | break; |
3938 | case 0x07f: /* VIS I fones */ | |
44e7757c | 3939 | tcg_gen_helper_0_0(helper_movl_FT0_1); |
3299908c BS |
3940 | gen_op_store_FT0_fpr(rd); |
3941 | break; | |
e9ebed4d BS |
3942 | case 0x080: /* VIS I shutdown */ |
3943 | case 0x081: /* VIS II siam */ | |
3944 | // XXX | |
3945 | goto illegal_insn; | |
3299908c BS |
3946 | default: |
3947 | goto illegal_insn; | |
3948 | } | |
3949 | #else | |
0f8a249a | 3950 | goto ncp_insn; |
3299908c BS |
3951 | #endif |
3952 | } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ | |
fcc72045 | 3953 | #ifdef TARGET_SPARC64 |
0f8a249a | 3954 | goto illegal_insn; |
fcc72045 | 3955 | #else |
0f8a249a | 3956 | goto ncp_insn; |
fcc72045 | 3957 | #endif |
3475187d | 3958 | #ifdef TARGET_SPARC64 |
0f8a249a | 3959 | } else if (xop == 0x39) { /* V9 return */ |
3475187d | 3960 | rs1 = GET_FIELD(insn, 13, 17); |
1ad21e69 | 3961 | save_state(dc); |
0f8a249a BS |
3962 | gen_movl_reg_T0(rs1); |
3963 | if (IS_IMM) { /* immediate */ | |
3964 | rs2 = GET_FIELDs(insn, 19, 31); | |
1a2fb1c0 | 3965 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2); |
0f8a249a | 3966 | } else { /* register */ |
3475187d FB |
3967 | rs2 = GET_FIELD(insn, 27, 31); |
3968 | #if defined(OPTIM) | |
0f8a249a | 3969 | if (rs2) { |
3475187d | 3970 | #endif |
0f8a249a BS |
3971 | gen_movl_reg_T1(rs2); |
3972 | gen_op_add_T1_T0(); | |
3475187d | 3973 | #if defined(OPTIM) |
0f8a249a | 3974 | } |
3475187d FB |
3975 | #endif |
3976 | } | |
72a9747b | 3977 | tcg_gen_helper_0_0(helper_restore); |
0f8a249a | 3978 | gen_mov_pc_npc(dc); |
6ea4a6c8 | 3979 | gen_op_check_align_T0_3(); |
48d5c82b | 3980 | tcg_gen_mov_tl(cpu_npc, cpu_T[0]); |
0f8a249a BS |
3981 | dc->npc = DYNAMIC_PC; |
3982 | goto jmp_insn; | |
3475187d | 3983 | #endif |
0f8a249a | 3984 | } else { |
e80cfcfc | 3985 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a BS |
3986 | gen_movl_reg_T0(rs1); |
3987 | if (IS_IMM) { /* immediate */ | |
3988 | rs2 = GET_FIELDs(insn, 19, 31); | |
1a2fb1c0 | 3989 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2); |
0f8a249a | 3990 | } else { /* register */ |
e80cfcfc FB |
3991 | rs2 = GET_FIELD(insn, 27, 31); |
3992 | #if defined(OPTIM) | |
0f8a249a | 3993 | if (rs2) { |
e80cfcfc | 3994 | #endif |
0f8a249a BS |
3995 | gen_movl_reg_T1(rs2); |
3996 | gen_op_add_T1_T0(); | |
e80cfcfc | 3997 | #if defined(OPTIM) |
0f8a249a | 3998 | } |
e8af50a3 | 3999 | #endif |
cf495bcf | 4000 | } |
0f8a249a BS |
4001 | switch (xop) { |
4002 | case 0x38: /* jmpl */ | |
4003 | { | |
4004 | if (rd != 0) { | |
1a2fb1c0 | 4005 | tcg_gen_movi_tl(cpu_T[1], dc->pc); |
0f8a249a BS |
4006 | gen_movl_T1_reg(rd); |
4007 | } | |
0bee699e | 4008 | gen_mov_pc_npc(dc); |
6ea4a6c8 | 4009 | gen_op_check_align_T0_3(); |
48d5c82b | 4010 | tcg_gen_mov_tl(cpu_npc, cpu_T[0]); |
0f8a249a BS |
4011 | dc->npc = DYNAMIC_PC; |
4012 | } | |
4013 | goto jmp_insn; | |
3475187d | 4014 | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) |
0f8a249a BS |
4015 | case 0x39: /* rett, V9 return */ |
4016 | { | |
4017 | if (!supervisor(dc)) | |
4018 | goto priv_insn; | |
0bee699e | 4019 | gen_mov_pc_npc(dc); |
6ea4a6c8 | 4020 | gen_op_check_align_T0_3(); |
48d5c82b | 4021 | tcg_gen_mov_tl(cpu_npc, cpu_T[0]); |
0f8a249a | 4022 | dc->npc = DYNAMIC_PC; |
1a2fb1c0 | 4023 | tcg_gen_helper_0_0(helper_rett); |
0f8a249a BS |
4024 | } |
4025 | goto jmp_insn; | |
4026 | #endif | |
4027 | case 0x3b: /* flush */ | |
1a2fb1c0 | 4028 | tcg_gen_helper_0_1(helper_flush, cpu_T[0]); |
0f8a249a BS |
4029 | break; |
4030 | case 0x3c: /* save */ | |
4031 | save_state(dc); | |
72a9747b | 4032 | tcg_gen_helper_0_0(helper_save); |
0f8a249a BS |
4033 | gen_movl_T0_reg(rd); |
4034 | break; | |
4035 | case 0x3d: /* restore */ | |
4036 | save_state(dc); | |
72a9747b | 4037 | tcg_gen_helper_0_0(helper_restore); |
0f8a249a BS |
4038 | gen_movl_T0_reg(rd); |
4039 | break; | |
3475187d | 4040 | #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64) |
0f8a249a BS |
4041 | case 0x3e: /* V9 done/retry */ |
4042 | { | |
4043 | switch (rd) { | |
4044 | case 0: | |
4045 | if (!supervisor(dc)) | |
4046 | goto priv_insn; | |
4047 | dc->npc = DYNAMIC_PC; | |
4048 | dc->pc = DYNAMIC_PC; | |
1a2fb1c0 | 4049 | tcg_gen_helper_0_0(helper_done); |
0f8a249a BS |
4050 | goto jmp_insn; |
4051 | case 1: | |
4052 | if (!supervisor(dc)) | |
4053 | goto priv_insn; | |
4054 | dc->npc = DYNAMIC_PC; | |
4055 | dc->pc = DYNAMIC_PC; | |
1a2fb1c0 | 4056 | tcg_gen_helper_0_0(helper_retry); |
0f8a249a BS |
4057 | goto jmp_insn; |
4058 | default: | |
4059 | goto illegal_insn; | |
4060 | } | |
4061 | } | |
4062 | break; | |
4063 | #endif | |
4064 | default: | |
4065 | goto illegal_insn; | |
4066 | } | |
cf495bcf | 4067 | } |
0f8a249a BS |
4068 | break; |
4069 | } | |
4070 | break; | |
4071 | case 3: /* load/store instructions */ | |
4072 | { | |
4073 | unsigned int xop = GET_FIELD(insn, 7, 12); | |
4074 | rs1 = GET_FIELD(insn, 13, 17); | |
2371aaa2 | 4075 | save_state(dc); |
0f8a249a | 4076 | gen_movl_reg_T0(rs1); |
81ad8ba2 BS |
4077 | if (xop == 0x3c || xop == 0x3e) |
4078 | { | |
4079 | rs2 = GET_FIELD(insn, 27, 31); | |
4080 | gen_movl_reg_T1(rs2); | |
4081 | } | |
4082 | else if (IS_IMM) { /* immediate */ | |
0f8a249a | 4083 | rs2 = GET_FIELDs(insn, 19, 31); |
1a2fb1c0 | 4084 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2); |
0f8a249a BS |
4085 | } else { /* register */ |
4086 | rs2 = GET_FIELD(insn, 27, 31); | |
e80cfcfc | 4087 | #if defined(OPTIM) |
0f8a249a | 4088 | if (rs2 != 0) { |
e80cfcfc | 4089 | #endif |
0f8a249a BS |
4090 | gen_movl_reg_T1(rs2); |
4091 | gen_op_add_T1_T0(); | |
e80cfcfc | 4092 | #if defined(OPTIM) |
0f8a249a | 4093 | } |
e80cfcfc | 4094 | #endif |
0f8a249a | 4095 | } |
2f2ecb83 BS |
4096 | if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || |
4097 | (xop > 0x17 && xop <= 0x1d ) || | |
4098 | (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { | |
0f8a249a | 4099 | switch (xop) { |
1a2fb1c0 | 4100 | case 0x0: /* load unsigned word */ |
6ea4a6c8 | 4101 | gen_op_check_align_T0_3(); |
1a2fb1c0 BS |
4102 | ABI32_MASK(cpu_T[0]); |
4103 | tcg_gen_qemu_ld32u(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a BS |
4104 | break; |
4105 | case 0x1: /* load unsigned byte */ | |
1a2fb1c0 BS |
4106 | ABI32_MASK(cpu_T[0]); |
4107 | tcg_gen_qemu_ld8u(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a BS |
4108 | break; |
4109 | case 0x2: /* load unsigned halfword */ | |
6ea4a6c8 | 4110 | gen_op_check_align_T0_1(); |
1a2fb1c0 BS |
4111 | ABI32_MASK(cpu_T[0]); |
4112 | tcg_gen_qemu_ld16u(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a BS |
4113 | break; |
4114 | case 0x3: /* load double word */ | |
0f8a249a | 4115 | if (rd & 1) |
d4218d99 | 4116 | goto illegal_insn; |
1a2fb1c0 BS |
4117 | else { |
4118 | TCGv r_dword; | |
4119 | ||
4120 | r_dword = tcg_temp_new(TCG_TYPE_I64); | |
4121 | gen_op_check_align_T0_7(); | |
4122 | ABI32_MASK(cpu_T[0]); | |
4123 | tcg_gen_qemu_ld64(r_dword, cpu_T[0], dc->mem_idx); | |
4124 | tcg_gen_trunc_i64_i32(cpu_T[0], r_dword); | |
4125 | gen_movl_T0_reg(rd + 1); | |
4126 | tcg_gen_shri_i64(r_dword, r_dword, 32); | |
4127 | tcg_gen_trunc_i64_i32(cpu_T[1], r_dword); | |
0425bee5 | 4128 | tcg_gen_discard_i64(r_dword); |
1a2fb1c0 | 4129 | } |
0f8a249a BS |
4130 | break; |
4131 | case 0x9: /* load signed byte */ | |
1a2fb1c0 BS |
4132 | ABI32_MASK(cpu_T[0]); |
4133 | tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a BS |
4134 | break; |
4135 | case 0xa: /* load signed halfword */ | |
6ea4a6c8 | 4136 | gen_op_check_align_T0_1(); |
1a2fb1c0 BS |
4137 | ABI32_MASK(cpu_T[0]); |
4138 | tcg_gen_qemu_ld16s(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a BS |
4139 | break; |
4140 | case 0xd: /* ldstub -- XXX: should be atomically */ | |
1a2fb1c0 BS |
4141 | tcg_gen_movi_i32(cpu_tmp0, 0xff); |
4142 | ABI32_MASK(cpu_T[0]); | |
4143 | tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx); | |
4144 | tcg_gen_qemu_st8(cpu_tmp0, cpu_T[0], dc->mem_idx); | |
0f8a249a BS |
4145 | break; |
4146 | case 0x0f: /* swap register with memory. Also atomically */ | |
6ea4a6c8 | 4147 | gen_op_check_align_T0_3(); |
0f8a249a | 4148 | gen_movl_reg_T1(rd); |
1a2fb1c0 BS |
4149 | ABI32_MASK(cpu_T[0]); |
4150 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_T[0], dc->mem_idx); | |
4151 | tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx); | |
4152 | tcg_gen_mov_i32(cpu_T[1], cpu_tmp0); | |
0f8a249a | 4153 | break; |
3475187d | 4154 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) |
0f8a249a | 4155 | case 0x10: /* load word alternate */ |
3475187d | 4156 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4157 | if (IS_IMM) |
4158 | goto illegal_insn; | |
4159 | if (!supervisor(dc)) | |
4160 | goto priv_insn; | |
6ea4a6c8 | 4161 | #endif |
8f577d3d | 4162 | gen_op_check_align_T0_3(); |
81ad8ba2 | 4163 | gen_ld_asi(insn, 4, 0); |
0f8a249a BS |
4164 | break; |
4165 | case 0x11: /* load unsigned byte alternate */ | |
3475187d | 4166 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4167 | if (IS_IMM) |
4168 | goto illegal_insn; | |
4169 | if (!supervisor(dc)) | |
4170 | goto priv_insn; | |
4171 | #endif | |
81ad8ba2 | 4172 | gen_ld_asi(insn, 1, 0); |
0f8a249a BS |
4173 | break; |
4174 | case 0x12: /* load unsigned halfword alternate */ | |
3475187d | 4175 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4176 | if (IS_IMM) |
4177 | goto illegal_insn; | |
4178 | if (!supervisor(dc)) | |
4179 | goto priv_insn; | |
3475187d | 4180 | #endif |
8f577d3d | 4181 | gen_op_check_align_T0_1(); |
81ad8ba2 | 4182 | gen_ld_asi(insn, 2, 0); |
0f8a249a BS |
4183 | break; |
4184 | case 0x13: /* load double word alternate */ | |
3475187d | 4185 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4186 | if (IS_IMM) |
4187 | goto illegal_insn; | |
4188 | if (!supervisor(dc)) | |
4189 | goto priv_insn; | |
3475187d | 4190 | #endif |
0f8a249a | 4191 | if (rd & 1) |
d4218d99 | 4192 | goto illegal_insn; |
6ea4a6c8 | 4193 | gen_op_check_align_T0_7(); |
81ad8ba2 | 4194 | gen_ldda_asi(insn); |
0f8a249a BS |
4195 | gen_movl_T0_reg(rd + 1); |
4196 | break; | |
4197 | case 0x19: /* load signed byte alternate */ | |
3475187d | 4198 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4199 | if (IS_IMM) |
4200 | goto illegal_insn; | |
4201 | if (!supervisor(dc)) | |
4202 | goto priv_insn; | |
4203 | #endif | |
81ad8ba2 | 4204 | gen_ld_asi(insn, 1, 1); |
0f8a249a BS |
4205 | break; |
4206 | case 0x1a: /* load signed halfword alternate */ | |
3475187d | 4207 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4208 | if (IS_IMM) |
4209 | goto illegal_insn; | |
4210 | if (!supervisor(dc)) | |
4211 | goto priv_insn; | |
3475187d | 4212 | #endif |
8f577d3d | 4213 | gen_op_check_align_T0_1(); |
81ad8ba2 | 4214 | gen_ld_asi(insn, 2, 1); |
0f8a249a BS |
4215 | break; |
4216 | case 0x1d: /* ldstuba -- XXX: should be atomically */ | |
3475187d | 4217 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4218 | if (IS_IMM) |
4219 | goto illegal_insn; | |
4220 | if (!supervisor(dc)) | |
4221 | goto priv_insn; | |
4222 | #endif | |
81ad8ba2 | 4223 | gen_ldstub_asi(insn); |
0f8a249a BS |
4224 | break; |
4225 | case 0x1f: /* swap reg with alt. memory. Also atomically */ | |
3475187d | 4226 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4227 | if (IS_IMM) |
4228 | goto illegal_insn; | |
4229 | if (!supervisor(dc)) | |
4230 | goto priv_insn; | |
6ea4a6c8 | 4231 | #endif |
8f577d3d | 4232 | gen_op_check_align_T0_3(); |
81ad8ba2 BS |
4233 | gen_movl_reg_T1(rd); |
4234 | gen_swap_asi(insn); | |
0f8a249a | 4235 | break; |
3475187d FB |
4236 | |
4237 | #ifndef TARGET_SPARC64 | |
0f8a249a BS |
4238 | case 0x30: /* ldc */ |
4239 | case 0x31: /* ldcsr */ | |
4240 | case 0x33: /* lddc */ | |
4241 | goto ncp_insn; | |
3475187d FB |
4242 | #endif |
4243 | #endif | |
4244 | #ifdef TARGET_SPARC64 | |
0f8a249a | 4245 | case 0x08: /* V9 ldsw */ |
6ea4a6c8 | 4246 | gen_op_check_align_T0_3(); |
1a2fb1c0 BS |
4247 | ABI32_MASK(cpu_T[0]); |
4248 | tcg_gen_qemu_ld32s(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a BS |
4249 | break; |
4250 | case 0x0b: /* V9 ldx */ | |
6ea4a6c8 | 4251 | gen_op_check_align_T0_7(); |
1a2fb1c0 BS |
4252 | ABI32_MASK(cpu_T[0]); |
4253 | tcg_gen_qemu_ld64(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a BS |
4254 | break; |
4255 | case 0x18: /* V9 ldswa */ | |
6ea4a6c8 | 4256 | gen_op_check_align_T0_3(); |
81ad8ba2 | 4257 | gen_ld_asi(insn, 4, 1); |
0f8a249a BS |
4258 | break; |
4259 | case 0x1b: /* V9 ldxa */ | |
6ea4a6c8 | 4260 | gen_op_check_align_T0_7(); |
81ad8ba2 | 4261 | gen_ld_asi(insn, 8, 0); |
0f8a249a BS |
4262 | break; |
4263 | case 0x2d: /* V9 prefetch, no effect */ | |
4264 | goto skip_move; | |
4265 | case 0x30: /* V9 ldfa */ | |
6ea4a6c8 | 4266 | gen_op_check_align_T0_3(); |
2382dc6b | 4267 | gen_ldf_asi(insn, 4, rd); |
81ad8ba2 | 4268 | goto skip_move; |
0f8a249a | 4269 | case 0x33: /* V9 lddfa */ |
3391c818 | 4270 | gen_op_check_align_T0_3(); |
2382dc6b | 4271 | gen_ldf_asi(insn, 8, DFPREG(rd)); |
81ad8ba2 | 4272 | goto skip_move; |
0f8a249a BS |
4273 | case 0x3d: /* V9 prefetcha, no effect */ |
4274 | goto skip_move; | |
4275 | case 0x32: /* V9 ldqfa */ | |
1f587329 BS |
4276 | #if defined(CONFIG_USER_ONLY) |
4277 | gen_op_check_align_T0_3(); | |
2382dc6b | 4278 | gen_ldf_asi(insn, 16, QFPREG(rd)); |
1f587329 BS |
4279 | goto skip_move; |
4280 | #else | |
0f8a249a | 4281 | goto nfpu_insn; |
1f587329 | 4282 | #endif |
0f8a249a BS |
4283 | #endif |
4284 | default: | |
4285 | goto illegal_insn; | |
4286 | } | |
4287 | gen_movl_T1_reg(rd); | |
3475187d | 4288 | #ifdef TARGET_SPARC64 |
0f8a249a | 4289 | skip_move: ; |
3475187d | 4290 | #endif |
0f8a249a | 4291 | } else if (xop >= 0x20 && xop < 0x24) { |
a80dde08 FB |
4292 | if (gen_trap_ifnofpu(dc)) |
4293 | goto jmp_insn; | |
0f8a249a BS |
4294 | switch (xop) { |
4295 | case 0x20: /* load fpreg */ | |
6ea4a6c8 | 4296 | gen_op_check_align_T0_3(); |
0f8a249a BS |
4297 | gen_op_ldst(ldf); |
4298 | gen_op_store_FT0_fpr(rd); | |
4299 | break; | |
4300 | case 0x21: /* load fsr */ | |
6ea4a6c8 | 4301 | gen_op_check_align_T0_3(); |
0f8a249a | 4302 | gen_op_ldst(ldf); |
7e8c2b6c | 4303 | tcg_gen_helper_0_0(helper_ldfsr); |
0f8a249a BS |
4304 | break; |
4305 | case 0x22: /* load quad fpreg */ | |
1f587329 BS |
4306 | #if defined(CONFIG_USER_ONLY) |
4307 | gen_op_check_align_T0_7(); | |
4308 | gen_op_ldst(ldqf); | |
4309 | gen_op_store_QT0_fpr(QFPREG(rd)); | |
4310 | break; | |
4311 | #else | |
0f8a249a | 4312 | goto nfpu_insn; |
1f587329 | 4313 | #endif |
0f8a249a | 4314 | case 0x23: /* load double fpreg */ |
6ea4a6c8 | 4315 | gen_op_check_align_T0_7(); |
0f8a249a BS |
4316 | gen_op_ldst(lddf); |
4317 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
4318 | break; | |
4319 | default: | |
4320 | goto illegal_insn; | |
4321 | } | |
4322 | } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \ | |
4323 | xop == 0xe || xop == 0x1e) { | |
4324 | gen_movl_reg_T1(rd); | |
4325 | switch (xop) { | |
1a2fb1c0 | 4326 | case 0x4: /* store word */ |
6ea4a6c8 | 4327 | gen_op_check_align_T0_3(); |
1a2fb1c0 BS |
4328 | ABI32_MASK(cpu_T[0]); |
4329 | tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a | 4330 | break; |
1a2fb1c0 BS |
4331 | case 0x5: /* store byte */ |
4332 | ABI32_MASK(cpu_T[0]); | |
4333 | tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a | 4334 | break; |
1a2fb1c0 | 4335 | case 0x6: /* store halfword */ |
6ea4a6c8 | 4336 | gen_op_check_align_T0_1(); |
1a2fb1c0 BS |
4337 | ABI32_MASK(cpu_T[0]); |
4338 | tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a | 4339 | break; |
1a2fb1c0 | 4340 | case 0x7: /* store double word */ |
0f8a249a | 4341 | if (rd & 1) |
d4218d99 | 4342 | goto illegal_insn; |
b25deda7 | 4343 | #ifndef __i386__ |
1a2fb1c0 BS |
4344 | else { |
4345 | TCGv r_dword, r_low; | |
4346 | ||
4347 | gen_op_check_align_T0_7(); | |
4348 | r_dword = tcg_temp_new(TCG_TYPE_I64); | |
4349 | r_low = tcg_temp_new(TCG_TYPE_I32); | |
4350 | gen_movl_reg_TN(rd + 1, r_low); | |
4351 | tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1], | |
4352 | r_low); | |
4353 | tcg_gen_qemu_st64(r_dword, cpu_T[0], dc->mem_idx); | |
0425bee5 | 4354 | tcg_gen_discard_i64(r_dword); |
1a2fb1c0 | 4355 | } |
b25deda7 BS |
4356 | #else /* __i386__ */ |
4357 | gen_op_check_align_T0_7(); | |
4358 | flush_T2(dc); | |
4359 | gen_movl_reg_T2(rd + 1); | |
4360 | gen_op_ldst(std); | |
4361 | #endif /* __i386__ */ | |
0f8a249a | 4362 | break; |
3475187d | 4363 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) |
1a2fb1c0 | 4364 | case 0x14: /* store word alternate */ |
3475187d | 4365 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4366 | if (IS_IMM) |
4367 | goto illegal_insn; | |
4368 | if (!supervisor(dc)) | |
4369 | goto priv_insn; | |
6ea4a6c8 | 4370 | #endif |
6ea4a6c8 | 4371 | gen_op_check_align_T0_3(); |
81ad8ba2 | 4372 | gen_st_asi(insn, 4); |
d39c0b99 | 4373 | break; |
1a2fb1c0 | 4374 | case 0x15: /* store byte alternate */ |
3475187d | 4375 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4376 | if (IS_IMM) |
4377 | goto illegal_insn; | |
4378 | if (!supervisor(dc)) | |
4379 | goto priv_insn; | |
3475187d | 4380 | #endif |
81ad8ba2 | 4381 | gen_st_asi(insn, 1); |
d39c0b99 | 4382 | break; |
1a2fb1c0 | 4383 | case 0x16: /* store halfword alternate */ |
3475187d | 4384 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4385 | if (IS_IMM) |
4386 | goto illegal_insn; | |
4387 | if (!supervisor(dc)) | |
4388 | goto priv_insn; | |
6ea4a6c8 | 4389 | #endif |
6ea4a6c8 | 4390 | gen_op_check_align_T0_1(); |
81ad8ba2 | 4391 | gen_st_asi(insn, 2); |
d39c0b99 | 4392 | break; |
1a2fb1c0 | 4393 | case 0x17: /* store double word alternate */ |
3475187d | 4394 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4395 | if (IS_IMM) |
4396 | goto illegal_insn; | |
4397 | if (!supervisor(dc)) | |
4398 | goto priv_insn; | |
3475187d | 4399 | #endif |
0f8a249a | 4400 | if (rd & 1) |
d4218d99 | 4401 | goto illegal_insn; |
1a2fb1c0 | 4402 | else { |
1a2fb1c0 | 4403 | gen_op_check_align_T0_7(); |
0425bee5 | 4404 | gen_stda_asi(insn, rd); |
1a2fb1c0 | 4405 | } |
d39c0b99 | 4406 | break; |
e80cfcfc | 4407 | #endif |
3475187d | 4408 | #ifdef TARGET_SPARC64 |
0f8a249a | 4409 | case 0x0e: /* V9 stx */ |
6ea4a6c8 | 4410 | gen_op_check_align_T0_7(); |
1a2fb1c0 BS |
4411 | ABI32_MASK(cpu_T[0]); |
4412 | tcg_gen_qemu_st64(cpu_T[1], cpu_T[0], dc->mem_idx); | |
0f8a249a BS |
4413 | break; |
4414 | case 0x1e: /* V9 stxa */ | |
6ea4a6c8 | 4415 | gen_op_check_align_T0_7(); |
81ad8ba2 | 4416 | gen_st_asi(insn, 8); |
0f8a249a | 4417 | break; |
3475187d | 4418 | #endif |
0f8a249a BS |
4419 | default: |
4420 | goto illegal_insn; | |
4421 | } | |
4422 | } else if (xop > 0x23 && xop < 0x28) { | |
a80dde08 FB |
4423 | if (gen_trap_ifnofpu(dc)) |
4424 | goto jmp_insn; | |
0f8a249a BS |
4425 | switch (xop) { |
4426 | case 0x24: | |
6ea4a6c8 | 4427 | gen_op_check_align_T0_3(); |
e8af50a3 | 4428 | gen_op_load_fpr_FT0(rd); |
0f8a249a BS |
4429 | gen_op_ldst(stf); |
4430 | break; | |
4431 | case 0x25: /* stfsr, V9 stxfsr */ | |
6ea4a6c8 BS |
4432 | #ifdef CONFIG_USER_ONLY |
4433 | gen_op_check_align_T0_3(); | |
4434 | #endif | |
bb5529bb | 4435 | tcg_gen_helper_0_0(helper_stfsr); |
0f8a249a BS |
4436 | gen_op_ldst(stf); |
4437 | break; | |
1f587329 BS |
4438 | case 0x26: |
4439 | #ifdef TARGET_SPARC64 | |
4440 | #if defined(CONFIG_USER_ONLY) | |
4441 | /* V9 stqf, store quad fpreg */ | |
4442 | gen_op_check_align_T0_7(); | |
4443 | gen_op_load_fpr_QT0(QFPREG(rd)); | |
4444 | gen_op_ldst(stqf); | |
4445 | break; | |
4446 | #else | |
4447 | goto nfpu_insn; | |
4448 | #endif | |
4449 | #else /* !TARGET_SPARC64 */ | |
4450 | /* stdfq, store floating point queue */ | |
4451 | #if defined(CONFIG_USER_ONLY) | |
4452 | goto illegal_insn; | |
4453 | #else | |
0f8a249a BS |
4454 | if (!supervisor(dc)) |
4455 | goto priv_insn; | |
4456 | if (gen_trap_ifnofpu(dc)) | |
4457 | goto jmp_insn; | |
4458 | goto nfq_insn; | |
1f587329 | 4459 | #endif |
0f8a249a BS |
4460 | #endif |
4461 | case 0x27: | |
6ea4a6c8 | 4462 | gen_op_check_align_T0_7(); |
3475187d | 4463 | gen_op_load_fpr_DT0(DFPREG(rd)); |
0f8a249a BS |
4464 | gen_op_ldst(stdf); |
4465 | break; | |
4466 | default: | |
4467 | goto illegal_insn; | |
4468 | } | |
4469 | } else if (xop > 0x33 && xop < 0x3f) { | |
4470 | switch (xop) { | |
a4d17f19 | 4471 | #ifdef TARGET_SPARC64 |
0f8a249a | 4472 | case 0x34: /* V9 stfa */ |
6ea4a6c8 | 4473 | gen_op_check_align_T0_3(); |
3391c818 | 4474 | gen_op_load_fpr_FT0(rd); |
2382dc6b | 4475 | gen_stf_asi(insn, 4, rd); |
0f8a249a | 4476 | break; |
1f587329 BS |
4477 | case 0x36: /* V9 stqfa */ |
4478 | #if defined(CONFIG_USER_ONLY) | |
4479 | gen_op_check_align_T0_7(); | |
4480 | gen_op_load_fpr_QT0(QFPREG(rd)); | |
2382dc6b | 4481 | gen_stf_asi(insn, 16, QFPREG(rd)); |
1f587329 BS |
4482 | break; |
4483 | #else | |
4484 | goto nfpu_insn; | |
4485 | #endif | |
0f8a249a | 4486 | case 0x37: /* V9 stdfa */ |
3391c818 BS |
4487 | gen_op_check_align_T0_3(); |
4488 | gen_op_load_fpr_DT0(DFPREG(rd)); | |
2382dc6b | 4489 | gen_stf_asi(insn, 8, DFPREG(rd)); |
0f8a249a BS |
4490 | break; |
4491 | case 0x3c: /* V9 casa */ | |
6ea4a6c8 | 4492 | gen_op_check_align_T0_3(); |
1a2fb1c0 | 4493 | gen_cas_asi(insn, rd); |
81ad8ba2 | 4494 | gen_movl_T1_reg(rd); |
0f8a249a BS |
4495 | break; |
4496 | case 0x3e: /* V9 casxa */ | |
6ea4a6c8 | 4497 | gen_op_check_align_T0_7(); |
1a2fb1c0 | 4498 | gen_casx_asi(insn, rd); |
81ad8ba2 | 4499 | gen_movl_T1_reg(rd); |
0f8a249a | 4500 | break; |
a4d17f19 | 4501 | #else |
0f8a249a BS |
4502 | case 0x34: /* stc */ |
4503 | case 0x35: /* stcsr */ | |
4504 | case 0x36: /* stdcq */ | |
4505 | case 0x37: /* stdc */ | |
4506 | goto ncp_insn; | |
4507 | #endif | |
4508 | default: | |
4509 | goto illegal_insn; | |
4510 | } | |
e8af50a3 | 4511 | } |
0f8a249a BS |
4512 | else |
4513 | goto illegal_insn; | |
4514 | } | |
4515 | break; | |
cf495bcf FB |
4516 | } |
4517 | /* default case for non jump instructions */ | |
72cbca10 | 4518 | if (dc->npc == DYNAMIC_PC) { |
0f8a249a BS |
4519 | dc->pc = DYNAMIC_PC; |
4520 | gen_op_next_insn(); | |
72cbca10 FB |
4521 | } else if (dc->npc == JUMP_PC) { |
4522 | /* we can do a static jump */ | |
19f329ad | 4523 | gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]); |
72cbca10 FB |
4524 | dc->is_br = 1; |
4525 | } else { | |
0f8a249a BS |
4526 | dc->pc = dc->npc; |
4527 | dc->npc = dc->npc + 4; | |
cf495bcf | 4528 | } |
e80cfcfc | 4529 | jmp_insn: |
cf495bcf FB |
4530 | return; |
4531 | illegal_insn: | |
72cbca10 | 4532 | save_state(dc); |
cf495bcf FB |
4533 | gen_op_exception(TT_ILL_INSN); |
4534 | dc->is_br = 1; | |
e8af50a3 | 4535 | return; |
e80cfcfc | 4536 | #if !defined(CONFIG_USER_ONLY) |
e8af50a3 FB |
4537 | priv_insn: |
4538 | save_state(dc); | |
4539 | gen_op_exception(TT_PRIV_INSN); | |
4540 | dc->is_br = 1; | |
e80cfcfc | 4541 | return; |
e80cfcfc FB |
4542 | nfpu_insn: |
4543 | save_state(dc); | |
4544 | gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); | |
4545 | dc->is_br = 1; | |
fcc72045 | 4546 | return; |
1f587329 | 4547 | #ifndef TARGET_SPARC64 |
9143e598 BS |
4548 | nfq_insn: |
4549 | save_state(dc); | |
4550 | gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); | |
4551 | dc->is_br = 1; | |
4552 | return; | |
4553 | #endif | |
1f587329 | 4554 | #endif |
fcc72045 BS |
4555 | #ifndef TARGET_SPARC64 |
4556 | ncp_insn: | |
4557 | save_state(dc); | |
4558 | gen_op_exception(TT_NCP_INSN); | |
4559 | dc->is_br = 1; | |
4560 | return; | |
4561 | #endif | |
7a3f1944 FB |
4562 | } |
4563 | ||
1a2fb1c0 BS |
4564 | static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args) |
4565 | { | |
4566 | } | |
4567 | ||
cf495bcf | 4568 | static inline int gen_intermediate_code_internal(TranslationBlock * tb, |
0f8a249a | 4569 | int spc, CPUSPARCState *env) |
7a3f1944 | 4570 | { |
72cbca10 | 4571 | target_ulong pc_start, last_pc; |
cf495bcf FB |
4572 | uint16_t *gen_opc_end; |
4573 | DisasContext dc1, *dc = &dc1; | |
e8af50a3 | 4574 | int j, lj = -1; |
cf495bcf FB |
4575 | |
4576 | memset(dc, 0, sizeof(DisasContext)); | |
cf495bcf | 4577 | dc->tb = tb; |
72cbca10 | 4578 | pc_start = tb->pc; |
cf495bcf | 4579 | dc->pc = pc_start; |
e80cfcfc | 4580 | last_pc = dc->pc; |
72cbca10 | 4581 | dc->npc = (target_ulong) tb->cs_base; |
6f27aba6 BS |
4582 | dc->mem_idx = cpu_mmu_index(env); |
4583 | dc->fpu_enabled = cpu_fpu_enabled(env); | |
cf495bcf | 4584 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
cf495bcf | 4585 | |
1a2fb1c0 | 4586 | cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL); |
1a2fb1c0 | 4587 | |
cf495bcf | 4588 | do { |
e8af50a3 FB |
4589 | if (env->nb_breakpoints > 0) { |
4590 | for(j = 0; j < env->nb_breakpoints; j++) { | |
4591 | if (env->breakpoints[j] == dc->pc) { | |
0f8a249a BS |
4592 | if (dc->pc != pc_start) |
4593 | save_state(dc); | |
1a2fb1c0 | 4594 | tcg_gen_helper_0_0(helper_debug); |
57fec1fe | 4595 | tcg_gen_exit_tb(0); |
0f8a249a | 4596 | dc->is_br = 1; |
e80cfcfc | 4597 | goto exit_gen_loop; |
e8af50a3 FB |
4598 | } |
4599 | } | |
4600 | } | |
4601 | if (spc) { | |
4602 | if (loglevel > 0) | |
4603 | fprintf(logfile, "Search PC...\n"); | |
4604 | j = gen_opc_ptr - gen_opc_buf; | |
4605 | if (lj < j) { | |
4606 | lj++; | |
4607 | while (lj < j) | |
4608 | gen_opc_instr_start[lj++] = 0; | |
4609 | gen_opc_pc[lj] = dc->pc; | |
4610 | gen_opc_npc[lj] = dc->npc; | |
4611 | gen_opc_instr_start[lj] = 1; | |
4612 | } | |
4613 | } | |
0f8a249a BS |
4614 | last_pc = dc->pc; |
4615 | disas_sparc_insn(dc); | |
4616 | ||
4617 | if (dc->is_br) | |
4618 | break; | |
4619 | /* if the next PC is different, we abort now */ | |
4620 | if (dc->pc != (last_pc + 4)) | |
4621 | break; | |
d39c0b99 FB |
4622 | /* if we reach a page boundary, we stop generation so that the |
4623 | PC of a TT_TFAULT exception is always in the right page */ | |
4624 | if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) | |
4625 | break; | |
e80cfcfc FB |
4626 | /* if single step mode, we generate only one instruction and |
4627 | generate an exception */ | |
4628 | if (env->singlestep_enabled) { | |
3475187d | 4629 | gen_jmp_im(dc->pc); |
57fec1fe | 4630 | tcg_gen_exit_tb(0); |
e80cfcfc FB |
4631 | break; |
4632 | } | |
cf495bcf | 4633 | } while ((gen_opc_ptr < gen_opc_end) && |
0f8a249a | 4634 | (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32)); |
e80cfcfc FB |
4635 | |
4636 | exit_gen_loop: | |
72cbca10 | 4637 | if (!dc->is_br) { |
5fafdf24 | 4638 | if (dc->pc != DYNAMIC_PC && |
72cbca10 FB |
4639 | (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { |
4640 | /* static PC and NPC: we can use direct chaining */ | |
46525e1f | 4641 | gen_branch(dc, dc->pc, dc->npc); |
72cbca10 FB |
4642 | } else { |
4643 | if (dc->pc != DYNAMIC_PC) | |
3475187d | 4644 | gen_jmp_im(dc->pc); |
72cbca10 | 4645 | save_npc(dc); |
57fec1fe | 4646 | tcg_gen_exit_tb(0); |
72cbca10 FB |
4647 | } |
4648 | } | |
cf495bcf | 4649 | *gen_opc_ptr = INDEX_op_end; |
e8af50a3 FB |
4650 | if (spc) { |
4651 | j = gen_opc_ptr - gen_opc_buf; | |
4652 | lj++; | |
4653 | while (lj <= j) | |
4654 | gen_opc_instr_start[lj++] = 0; | |
e8af50a3 FB |
4655 | #if 0 |
4656 | if (loglevel > 0) { | |
4657 | page_dump(logfile); | |
4658 | } | |
4659 | #endif | |
c3278b7b FB |
4660 | gen_opc_jump_pc[0] = dc->jump_pc[0]; |
4661 | gen_opc_jump_pc[1] = dc->jump_pc[1]; | |
e8af50a3 | 4662 | } else { |
e80cfcfc | 4663 | tb->size = last_pc + 4 - pc_start; |
e8af50a3 | 4664 | } |
7a3f1944 | 4665 | #ifdef DEBUG_DISAS |
e19e89a5 | 4666 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
0f8a249a BS |
4667 | fprintf(logfile, "--------------\n"); |
4668 | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start)); | |
4669 | target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0); | |
4670 | fprintf(logfile, "\n"); | |
cf495bcf | 4671 | } |
7a3f1944 | 4672 | #endif |
cf495bcf | 4673 | return 0; |
7a3f1944 FB |
4674 | } |
4675 | ||
cf495bcf | 4676 | int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb) |
7a3f1944 | 4677 | { |
e8af50a3 | 4678 | return gen_intermediate_code_internal(tb, 0, env); |
7a3f1944 FB |
4679 | } |
4680 | ||
cf495bcf | 4681 | int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb) |
7a3f1944 | 4682 | { |
e8af50a3 | 4683 | return gen_intermediate_code_internal(tb, 1, env); |
7a3f1944 FB |
4684 | } |
4685 | ||
e80cfcfc FB |
4686 | void cpu_reset(CPUSPARCState *env) |
4687 | { | |
bb05683b | 4688 | tlb_flush(env, 1); |
cf495bcf FB |
4689 | env->cwp = 0; |
4690 | env->wim = 1; | |
4691 | env->regwptr = env->regbase + (env->cwp * 16); | |
e8af50a3 | 4692 | #if defined(CONFIG_USER_ONLY) |
cf495bcf | 4693 | env->user_mode_only = 1; |
5ef54116 | 4694 | #ifdef TARGET_SPARC64 |
6ef905f6 BS |
4695 | env->cleanwin = NWINDOWS - 2; |
4696 | env->cansave = NWINDOWS - 2; | |
4697 | env->pstate = PS_RMO | PS_PEF | PS_IE; | |
4698 | env->asi = 0x82; // Primary no-fault | |
5ef54116 | 4699 | #endif |
e8af50a3 | 4700 | #else |
32af58f9 | 4701 | env->psret = 0; |
e8af50a3 | 4702 | env->psrs = 1; |
0bee699e | 4703 | env->psrps = 1; |
3475187d | 4704 | #ifdef TARGET_SPARC64 |
83469015 | 4705 | env->pstate = PS_PRIV; |
6f27aba6 | 4706 | env->hpstate = HS_PRIV; |
83469015 | 4707 | env->pc = 0x1fff0000000ULL; |
375ee38b | 4708 | env->tsptr = &env->ts[env->tl]; |
3475187d | 4709 | #else |
40ce0a9a | 4710 | env->pc = 0; |
32af58f9 | 4711 | env->mmuregs[0] &= ~(MMU_E | MMU_NF); |
6d5f237a | 4712 | env->mmuregs[0] |= env->mmu_bm; |
3475187d | 4713 | #endif |
83469015 | 4714 | env->npc = env->pc + 4; |
e8af50a3 | 4715 | #endif |
e80cfcfc FB |
4716 | } |
4717 | ||
aaed909a | 4718 | CPUSPARCState *cpu_sparc_init(const char *cpu_model) |
e80cfcfc FB |
4719 | { |
4720 | CPUSPARCState *env; | |
aaed909a | 4721 | const sparc_def_t *def; |
1a2fb1c0 | 4722 | static int inited; |
f5069b26 BS |
4723 | unsigned int i; |
4724 | static const char * const gregnames[8] = { | |
4725 | NULL, // g0 not used | |
4726 | "g1", | |
4727 | "g2", | |
4728 | "g3", | |
4729 | "g4", | |
4730 | "g5", | |
4731 | "g6", | |
4732 | "g7", | |
4733 | }; | |
aaed909a FB |
4734 | |
4735 | def = cpu_sparc_find_by_name(cpu_model); | |
4736 | if (!def) | |
4737 | return NULL; | |
e80cfcfc | 4738 | |
c68ea704 FB |
4739 | env = qemu_mallocz(sizeof(CPUSPARCState)); |
4740 | if (!env) | |
0f8a249a | 4741 | return NULL; |
c68ea704 | 4742 | cpu_exec_init(env); |
01ba9816 | 4743 | env->cpu_model_str = cpu_model; |
aaed909a FB |
4744 | env->version = def->iu_version; |
4745 | env->fsr = def->fpu_version; | |
4746 | #if !defined(TARGET_SPARC64) | |
4747 | env->mmu_bm = def->mmu_bm; | |
3deaeab7 BS |
4748 | env->mmu_ctpr_mask = def->mmu_ctpr_mask; |
4749 | env->mmu_cxr_mask = def->mmu_cxr_mask; | |
4750 | env->mmu_sfsr_mask = def->mmu_sfsr_mask; | |
4751 | env->mmu_trcr_mask = def->mmu_trcr_mask; | |
aaed909a FB |
4752 | env->mmuregs[0] |= def->mmu_version; |
4753 | cpu_sparc_set_id(env, 0); | |
4754 | #endif | |
1a2fb1c0 BS |
4755 | |
4756 | /* init various static tables */ | |
4757 | if (!inited) { | |
4758 | inited = 1; | |
4759 | ||
4760 | tcg_set_macro_func(&tcg_ctx, tcg_macro_func); | |
4761 | cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env"); | |
db4a4ea4 BS |
4762 | cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0, |
4763 | offsetof(CPUState, regwptr), | |
4764 | "regwptr"); | |
1a2fb1c0 BS |
4765 | //#if TARGET_LONG_BITS > HOST_LONG_BITS |
4766 | #ifdef TARGET_SPARC64 | |
4767 | cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL, | |
4768 | TCG_AREG0, offsetof(CPUState, t0), "T0"); | |
4769 | cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL, | |
4770 | TCG_AREG0, offsetof(CPUState, t1), "T1"); | |
4771 | cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL, | |
4772 | TCG_AREG0, offsetof(CPUState, t2), "T2"); | |
dc99a3f2 BS |
4773 | cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32, |
4774 | TCG_AREG0, offsetof(CPUState, xcc), | |
4775 | "xcc"); | |
1a2fb1c0 BS |
4776 | #else |
4777 | cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0"); | |
4778 | cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1"); | |
4779 | cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2"); | |
4780 | #endif | |
dc99a3f2 BS |
4781 | cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL, |
4782 | TCG_AREG0, offsetof(CPUState, cc_src), | |
4783 | "cc_src"); | |
d9bdab86 BS |
4784 | cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
4785 | offsetof(CPUState, cc_src2), | |
4786 | "cc_src2"); | |
dc99a3f2 BS |
4787 | cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL, |
4788 | TCG_AREG0, offsetof(CPUState, cc_dst), | |
4789 | "cc_dst"); | |
4790 | cpu_psr = tcg_global_mem_new(TCG_TYPE_I32, | |
4791 | TCG_AREG0, offsetof(CPUState, psr), | |
4792 | "psr"); | |
87e92502 BS |
4793 | cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL, |
4794 | TCG_AREG0, offsetof(CPUState, fsr), | |
4795 | "fsr"); | |
48d5c82b BS |
4796 | cpu_pc = tcg_global_mem_new(TCG_TYPE_TL, |
4797 | TCG_AREG0, offsetof(CPUState, pc), | |
4798 | "pc"); | |
4799 | cpu_npc = tcg_global_mem_new(TCG_TYPE_TL, | |
4800 | TCG_AREG0, offsetof(CPUState, npc), | |
4801 | "npc"); | |
f5069b26 BS |
4802 | for (i = 1; i < 8; i++) |
4803 | cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, | |
4804 | offsetof(CPUState, gregs[i]), | |
4805 | gregnames[i]); | |
1a2fb1c0 BS |
4806 | } |
4807 | ||
aaed909a FB |
4808 | cpu_reset(env); |
4809 | ||
4810 | return env; | |
4811 | } | |
4812 | ||
4813 | void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) | |
4814 | { | |
4815 | #if !defined(TARGET_SPARC64) | |
4816 | env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; | |
4817 | #endif | |
7a3f1944 FB |
4818 | } |
4819 | ||
62724a37 BS |
4820 | static const sparc_def_t sparc_defs[] = { |
4821 | #ifdef TARGET_SPARC64 | |
7d77bf20 BS |
4822 | { |
4823 | .name = "Fujitsu Sparc64", | |
4824 | .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24) | |
4825 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4826 | .fpu_version = 0x00000000, | |
4827 | .mmu_version = 0, | |
4828 | }, | |
4829 | { | |
4830 | .name = "Fujitsu Sparc64 III", | |
4831 | .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24) | |
4832 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4833 | .fpu_version = 0x00000000, | |
4834 | .mmu_version = 0, | |
4835 | }, | |
4836 | { | |
4837 | .name = "Fujitsu Sparc64 IV", | |
4838 | .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24) | |
4839 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4840 | .fpu_version = 0x00000000, | |
4841 | .mmu_version = 0, | |
4842 | }, | |
4843 | { | |
4844 | .name = "Fujitsu Sparc64 V", | |
4845 | .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24) | |
4846 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4847 | .fpu_version = 0x00000000, | |
4848 | .mmu_version = 0, | |
4849 | }, | |
4850 | { | |
4851 | .name = "TI UltraSparc I", | |
4852 | .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) | |
4853 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4854 | .fpu_version = 0x00000000, | |
4855 | .mmu_version = 0, | |
4856 | }, | |
62724a37 BS |
4857 | { |
4858 | .name = "TI UltraSparc II", | |
7d77bf20 BS |
4859 | .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24) |
4860 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4861 | .fpu_version = 0x00000000, | |
4862 | .mmu_version = 0, | |
4863 | }, | |
4864 | { | |
4865 | .name = "TI UltraSparc IIi", | |
4866 | .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24) | |
4867 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4868 | .fpu_version = 0x00000000, | |
4869 | .mmu_version = 0, | |
4870 | }, | |
4871 | { | |
4872 | .name = "TI UltraSparc IIe", | |
4873 | .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24) | |
4874 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4875 | .fpu_version = 0x00000000, | |
4876 | .mmu_version = 0, | |
4877 | }, | |
4878 | { | |
4879 | .name = "Sun UltraSparc III", | |
4880 | .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24) | |
4881 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4882 | .fpu_version = 0x00000000, | |
4883 | .mmu_version = 0, | |
4884 | }, | |
4885 | { | |
4886 | .name = "Sun UltraSparc III Cu", | |
4887 | .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24) | |
4888 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4889 | .fpu_version = 0x00000000, | |
4890 | .mmu_version = 0, | |
4891 | }, | |
4892 | { | |
4893 | .name = "Sun UltraSparc IIIi", | |
4894 | .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24) | |
4895 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4896 | .fpu_version = 0x00000000, | |
4897 | .mmu_version = 0, | |
4898 | }, | |
4899 | { | |
4900 | .name = "Sun UltraSparc IV", | |
4901 | .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24) | |
4902 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4903 | .fpu_version = 0x00000000, | |
4904 | .mmu_version = 0, | |
4905 | }, | |
4906 | { | |
4907 | .name = "Sun UltraSparc IV+", | |
4908 | .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24) | |
4909 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4910 | .fpu_version = 0x00000000, | |
4911 | .mmu_version = 0, | |
4912 | }, | |
4913 | { | |
4914 | .name = "Sun UltraSparc IIIi+", | |
4915 | .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24) | |
4916 | | (MAXTL << 8) | (NWINDOWS - 1)), | |
4917 | .fpu_version = 0x00000000, | |
4918 | .mmu_version = 0, | |
4919 | }, | |
4920 | { | |
4921 | .name = "NEC UltraSparc I", | |
4922 | .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) | |
62724a37 BS |
4923 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4924 | .fpu_version = 0x00000000, | |
4925 | .mmu_version = 0, | |
4926 | }, | |
4927 | #else | |
406f82e8 BS |
4928 | { |
4929 | .name = "Fujitsu MB86900", | |
4930 | .iu_version = 0x00 << 24, /* Impl 0, ver 0 */ | |
4931 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
4932 | .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */ | |
4933 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
4934 | .mmu_ctpr_mask = 0x007ffff0, |
4935 | .mmu_cxr_mask = 0x0000003f, | |
4936 | .mmu_sfsr_mask = 0xffffffff, | |
4937 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 | 4938 | }, |
62724a37 BS |
4939 | { |
4940 | .name = "Fujitsu MB86904", | |
4941 | .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ | |
4942 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
4943 | .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ | |
6d5f237a | 4944 | .mmu_bm = 0x00004000, |
3deaeab7 BS |
4945 | .mmu_ctpr_mask = 0x00ffffc0, |
4946 | .mmu_cxr_mask = 0x000000ff, | |
4947 | .mmu_sfsr_mask = 0x00016fff, | |
4948 | .mmu_trcr_mask = 0x00ffffff, | |
62724a37 | 4949 | }, |
e0353fe2 | 4950 | { |
5ef62c5c BS |
4951 | .name = "Fujitsu MB86907", |
4952 | .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ | |
4953 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
4954 | .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ | |
6d5f237a | 4955 | .mmu_bm = 0x00004000, |
3deaeab7 BS |
4956 | .mmu_ctpr_mask = 0xffffffc0, |
4957 | .mmu_cxr_mask = 0x000000ff, | |
4958 | .mmu_sfsr_mask = 0x00016fff, | |
4959 | .mmu_trcr_mask = 0xffffffff, | |
5ef62c5c | 4960 | }, |
406f82e8 BS |
4961 | { |
4962 | .name = "LSI L64811", | |
4963 | .iu_version = 0x10 << 24, /* Impl 1, ver 0 */ | |
4964 | .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */ | |
4965 | .mmu_version = 0x10 << 24, | |
4966 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
4967 | .mmu_ctpr_mask = 0x007ffff0, |
4968 | .mmu_cxr_mask = 0x0000003f, | |
4969 | .mmu_sfsr_mask = 0xffffffff, | |
4970 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 BS |
4971 | }, |
4972 | { | |
4973 | .name = "Cypress CY7C601", | |
4974 | .iu_version = 0x11 << 24, /* Impl 1, ver 1 */ | |
4975 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ | |
4976 | .mmu_version = 0x10 << 24, | |
4977 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
4978 | .mmu_ctpr_mask = 0x007ffff0, |
4979 | .mmu_cxr_mask = 0x0000003f, | |
4980 | .mmu_sfsr_mask = 0xffffffff, | |
4981 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 BS |
4982 | }, |
4983 | { | |
4984 | .name = "Cypress CY7C611", | |
4985 | .iu_version = 0x13 << 24, /* Impl 1, ver 3 */ | |
4986 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ | |
4987 | .mmu_version = 0x10 << 24, | |
4988 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
4989 | .mmu_ctpr_mask = 0x007ffff0, |
4990 | .mmu_cxr_mask = 0x0000003f, | |
4991 | .mmu_sfsr_mask = 0xffffffff, | |
4992 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 BS |
4993 | }, |
4994 | { | |
4995 | .name = "TI SuperSparc II", | |
4996 | .iu_version = 0x40000000, | |
4997 | .fpu_version = 0 << 17, | |
4998 | .mmu_version = 0x04000000, | |
4999 | .mmu_bm = 0x00002000, | |
3deaeab7 BS |
5000 | .mmu_ctpr_mask = 0xffffffc0, |
5001 | .mmu_cxr_mask = 0x0000ffff, | |
5002 | .mmu_sfsr_mask = 0xffffffff, | |
5003 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 | 5004 | }, |
5ef62c5c BS |
5005 | { |
5006 | .name = "TI MicroSparc I", | |
5007 | .iu_version = 0x41000000, | |
5008 | .fpu_version = 4 << 17, | |
5009 | .mmu_version = 0x41000000, | |
6d5f237a | 5010 | .mmu_bm = 0x00004000, |
3deaeab7 BS |
5011 | .mmu_ctpr_mask = 0x007ffff0, |
5012 | .mmu_cxr_mask = 0x0000003f, | |
5013 | .mmu_sfsr_mask = 0x00016fff, | |
5014 | .mmu_trcr_mask = 0x0000003f, | |
5ef62c5c BS |
5015 | }, |
5016 | { | |
406f82e8 BS |
5017 | .name = "TI MicroSparc II", |
5018 | .iu_version = 0x42000000, | |
5019 | .fpu_version = 4 << 17, | |
5020 | .mmu_version = 0x02000000, | |
5021 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
5022 | .mmu_ctpr_mask = 0x00ffffc0, |
5023 | .mmu_cxr_mask = 0x000000ff, | |
a3ffaf30 | 5024 | .mmu_sfsr_mask = 0x00016fff, |
3deaeab7 | 5025 | .mmu_trcr_mask = 0x00ffffff, |
406f82e8 BS |
5026 | }, |
5027 | { | |
5028 | .name = "TI MicroSparc IIep", | |
5029 | .iu_version = 0x42000000, | |
5030 | .fpu_version = 4 << 17, | |
5031 | .mmu_version = 0x04000000, | |
5032 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
5033 | .mmu_ctpr_mask = 0x00ffffc0, |
5034 | .mmu_cxr_mask = 0x000000ff, | |
5035 | .mmu_sfsr_mask = 0x00016bff, | |
5036 | .mmu_trcr_mask = 0x00ffffff, | |
406f82e8 BS |
5037 | }, |
5038 | { | |
5039 | .name = "TI SuperSparc 51", | |
5040 | .iu_version = 0x43000000, | |
5ef62c5c BS |
5041 | .fpu_version = 0 << 17, |
5042 | .mmu_version = 0x04000000, | |
6d5f237a | 5043 | .mmu_bm = 0x00002000, |
3deaeab7 BS |
5044 | .mmu_ctpr_mask = 0xffffffc0, |
5045 | .mmu_cxr_mask = 0x0000ffff, | |
5046 | .mmu_sfsr_mask = 0xffffffff, | |
5047 | .mmu_trcr_mask = 0xffffffff, | |
5ef62c5c BS |
5048 | }, |
5049 | { | |
406f82e8 BS |
5050 | .name = "TI SuperSparc 61", |
5051 | .iu_version = 0x44000000, | |
5052 | .fpu_version = 0 << 17, | |
5053 | .mmu_version = 0x04000000, | |
5054 | .mmu_bm = 0x00002000, | |
3deaeab7 BS |
5055 | .mmu_ctpr_mask = 0xffffffc0, |
5056 | .mmu_cxr_mask = 0x0000ffff, | |
5057 | .mmu_sfsr_mask = 0xffffffff, | |
5058 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 BS |
5059 | }, |
5060 | { | |
5061 | .name = "Ross RT625", | |
5ef62c5c BS |
5062 | .iu_version = 0x1e000000, |
5063 | .fpu_version = 1 << 17, | |
406f82e8 BS |
5064 | .mmu_version = 0x1e000000, |
5065 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
5066 | .mmu_ctpr_mask = 0x007ffff0, |
5067 | .mmu_cxr_mask = 0x0000003f, | |
5068 | .mmu_sfsr_mask = 0xffffffff, | |
5069 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 BS |
5070 | }, |
5071 | { | |
5072 | .name = "Ross RT620", | |
5073 | .iu_version = 0x1f000000, | |
5074 | .fpu_version = 1 << 17, | |
5075 | .mmu_version = 0x1f000000, | |
5076 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
5077 | .mmu_ctpr_mask = 0x007ffff0, |
5078 | .mmu_cxr_mask = 0x0000003f, | |
5079 | .mmu_sfsr_mask = 0xffffffff, | |
5080 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 BS |
5081 | }, |
5082 | { | |
5083 | .name = "BIT B5010", | |
5084 | .iu_version = 0x20000000, | |
5085 | .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */ | |
5086 | .mmu_version = 0x20000000, | |
5087 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
5088 | .mmu_ctpr_mask = 0x007ffff0, |
5089 | .mmu_cxr_mask = 0x0000003f, | |
5090 | .mmu_sfsr_mask = 0xffffffff, | |
5091 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 BS |
5092 | }, |
5093 | { | |
5094 | .name = "Matsushita MN10501", | |
5095 | .iu_version = 0x50000000, | |
5096 | .fpu_version = 0 << 17, | |
5097 | .mmu_version = 0x50000000, | |
5098 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
5099 | .mmu_ctpr_mask = 0x007ffff0, |
5100 | .mmu_cxr_mask = 0x0000003f, | |
5101 | .mmu_sfsr_mask = 0xffffffff, | |
5102 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 BS |
5103 | }, |
5104 | { | |
5105 | .name = "Weitek W8601", | |
5106 | .iu_version = 0x90 << 24, /* Impl 9, ver 0 */ | |
5107 | .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */ | |
5108 | .mmu_version = 0x10 << 24, | |
5109 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
5110 | .mmu_ctpr_mask = 0x007ffff0, |
5111 | .mmu_cxr_mask = 0x0000003f, | |
5112 | .mmu_sfsr_mask = 0xffffffff, | |
5113 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 BS |
5114 | }, |
5115 | { | |
5116 | .name = "LEON2", | |
5117 | .iu_version = 0xf2000000, | |
5118 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
5119 | .mmu_version = 0xf2000000, | |
5120 | .mmu_bm = 0x00004000, | |
3deaeab7 BS |
5121 | .mmu_ctpr_mask = 0x007ffff0, |
5122 | .mmu_cxr_mask = 0x0000003f, | |
5123 | .mmu_sfsr_mask = 0xffffffff, | |
5124 | .mmu_trcr_mask = 0xffffffff, | |
406f82e8 BS |
5125 | }, |
5126 | { | |
5127 | .name = "LEON3", | |
5128 | .iu_version = 0xf3000000, | |
5129 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
5130 | .mmu_version = 0xf3000000, | |
6d5f237a | 5131 | .mmu_bm = 0x00004000, |
3deaeab7 BS |
5132 | .mmu_ctpr_mask = 0x007ffff0, |
5133 | .mmu_cxr_mask = 0x0000003f, | |
5134 | .mmu_sfsr_mask = 0xffffffff, | |
5135 | .mmu_trcr_mask = 0xffffffff, | |
e0353fe2 | 5136 | }, |
62724a37 BS |
5137 | #endif |
5138 | }; | |
5139 | ||
aaed909a | 5140 | static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name) |
62724a37 | 5141 | { |
62724a37 BS |
5142 | unsigned int i; |
5143 | ||
62724a37 BS |
5144 | for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
5145 | if (strcasecmp(name, sparc_defs[i].name) == 0) { | |
aaed909a | 5146 | return &sparc_defs[i]; |
62724a37 BS |
5147 | } |
5148 | } | |
aaed909a | 5149 | return NULL; |
62724a37 BS |
5150 | } |
5151 | ||
5152 | void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) | |
5153 | { | |
5154 | unsigned int i; | |
5155 | ||
5156 | for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { | |
5157 | (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n", | |
5158 | sparc_defs[i].name, | |
5159 | sparc_defs[i].iu_version, | |
5160 | sparc_defs[i].fpu_version, | |
5161 | sparc_defs[i].mmu_version); | |
5162 | } | |
5163 | } | |
5164 | ||
7a3f1944 FB |
5165 | #define GET_FLAG(a,b) ((env->psr & a)?b:'-') |
5166 | ||
5fafdf24 | 5167 | void cpu_dump_state(CPUState *env, FILE *f, |
7fe48483 FB |
5168 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
5169 | int flags) | |
7a3f1944 | 5170 | { |
cf495bcf FB |
5171 | int i, x; |
5172 | ||
af7bf89b | 5173 | cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc); |
7fe48483 | 5174 | cpu_fprintf(f, "General Registers:\n"); |
cf495bcf | 5175 | for (i = 0; i < 4; i++) |
0f8a249a | 5176 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
7fe48483 | 5177 | cpu_fprintf(f, "\n"); |
cf495bcf | 5178 | for (; i < 8; i++) |
0f8a249a | 5179 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
7fe48483 | 5180 | cpu_fprintf(f, "\nCurrent Register Window:\n"); |
cf495bcf | 5181 | for (x = 0; x < 3; x++) { |
0f8a249a BS |
5182 | for (i = 0; i < 4; i++) |
5183 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", | |
5184 | (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i, | |
5185 | env->regwptr[i + x * 8]); | |
5186 | cpu_fprintf(f, "\n"); | |
5187 | for (; i < 8; i++) | |
5188 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", | |
5189 | (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i, | |
5190 | env->regwptr[i + x * 8]); | |
5191 | cpu_fprintf(f, "\n"); | |
cf495bcf | 5192 | } |
7fe48483 | 5193 | cpu_fprintf(f, "\nFloating Point Registers:\n"); |
e8af50a3 FB |
5194 | for (i = 0; i < 32; i++) { |
5195 | if ((i & 3) == 0) | |
7fe48483 FB |
5196 | cpu_fprintf(f, "%%f%02d:", i); |
5197 | cpu_fprintf(f, " %016lf", env->fpr[i]); | |
e8af50a3 | 5198 | if ((i & 3) == 3) |
7fe48483 | 5199 | cpu_fprintf(f, "\n"); |
e8af50a3 | 5200 | } |
ded3ab80 | 5201 | #ifdef TARGET_SPARC64 |
3299908c | 5202 | cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n", |
0f8a249a | 5203 | env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs); |
ded3ab80 | 5204 | cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n", |
0f8a249a BS |
5205 | env->cansave, env->canrestore, env->otherwin, env->wstate, |
5206 | env->cleanwin, NWINDOWS - 1 - env->cwp); | |
ded3ab80 | 5207 | #else |
7fe48483 | 5208 | cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env), |
0f8a249a BS |
5209 | GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), |
5210 | GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), | |
5211 | env->psrs?'S':'-', env->psrps?'P':'-', | |
5212 | env->psret?'E':'-', env->wim); | |
ded3ab80 | 5213 | #endif |
3475187d | 5214 | cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env)); |
7a3f1944 | 5215 | } |
edfcbd99 | 5216 | |
e80cfcfc | 5217 | #if defined(CONFIG_USER_ONLY) |
9b3c35e0 | 5218 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
edfcbd99 FB |
5219 | { |
5220 | return addr; | |
5221 | } | |
658138bc | 5222 | |
e80cfcfc | 5223 | #else |
af7bf89b FB |
5224 | extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot, |
5225 | int *access_index, target_ulong address, int rw, | |
6ebbf390 | 5226 | int mmu_idx); |
0fa85d43 | 5227 | |
9b3c35e0 | 5228 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
e80cfcfc | 5229 | { |
af7bf89b | 5230 | target_phys_addr_t phys_addr; |
e80cfcfc FB |
5231 | int prot, access_index; |
5232 | ||
9e31b9e2 BS |
5233 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, |
5234 | MMU_KERNEL_IDX) != 0) | |
5235 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, | |
5236 | 0, MMU_KERNEL_IDX) != 0) | |
6b1575b7 | 5237 | return -1; |
6c36d3fa BS |
5238 | if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED) |
5239 | return -1; | |
e80cfcfc FB |
5240 | return phys_addr; |
5241 | } | |
5242 | #endif | |
5243 | ||
658138bc FB |
5244 | void helper_flush(target_ulong addr) |
5245 | { | |
5246 | addr &= ~7; | |
5247 | tb_invalidate_page_range(addr, addr + 8); | |
5248 | } |