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Commit | Line | Data |
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7a3f1944 FB |
1 | /* |
2 | SPARC translation | |
3 | ||
4 | Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at> | |
3475187d | 5 | Copyright (C) 2003-2005 Fabrice Bellard |
7a3f1944 FB |
6 | |
7 | This library is free software; you can redistribute it and/or | |
8 | modify it under the terms of the GNU Lesser General Public | |
9 | License as published by the Free Software Foundation; either | |
10 | version 2 of the License, or (at your option) any later version. | |
11 | ||
12 | This library is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | Lesser General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU Lesser General Public | |
18 | License along with this library; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
7a3f1944 FB |
22 | #include <stdarg.h> |
23 | #include <stdlib.h> | |
24 | #include <stdio.h> | |
25 | #include <string.h> | |
26 | #include <inttypes.h> | |
27 | ||
28 | #include "cpu.h" | |
29 | #include "exec-all.h" | |
30 | #include "disas.h" | |
1a2fb1c0 | 31 | #include "helper.h" |
57fec1fe | 32 | #include "tcg-op.h" |
7a3f1944 FB |
33 | |
34 | #define DEBUG_DISAS | |
35 | ||
72cbca10 FB |
36 | #define DYNAMIC_PC 1 /* dynamic pc value */ |
37 | #define JUMP_PC 2 /* dynamic pc value which takes only two values | |
38 | according to jump_pc[T2] */ | |
39 | ||
1a2fb1c0 | 40 | /* global register indexes */ |
77f193da BS |
41 | static TCGv cpu_env, cpu_T[2], cpu_regwptr; |
42 | static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst; | |
48d5c82b | 43 | static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; |
6ae20372 | 44 | static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val; |
dc99a3f2 BS |
45 | #ifdef TARGET_SPARC64 |
46 | static TCGv cpu_xcc; | |
47 | #endif | |
1a2fb1c0 | 48 | /* local register indexes (only used inside old micro ops) */ |
8911f501 | 49 | static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64; |
1a2fb1c0 | 50 | |
7a3f1944 | 51 | typedef struct DisasContext { |
0f8a249a BS |
52 | target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */ |
53 | target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */ | |
72cbca10 | 54 | target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ |
cf495bcf | 55 | int is_br; |
e8af50a3 | 56 | int mem_idx; |
a80dde08 | 57 | int fpu_enabled; |
cf495bcf | 58 | struct TranslationBlock *tb; |
64a88d5d | 59 | uint32_t features; |
7a3f1944 FB |
60 | } DisasContext; |
61 | ||
3475187d | 62 | // This function uses non-native bit order |
7a3f1944 FB |
63 | #define GET_FIELD(X, FROM, TO) \ |
64 | ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) | |
65 | ||
3475187d FB |
66 | // This function uses the order in the manuals, i.e. bit 0 is 2^0 |
67 | #define GET_FIELD_SP(X, FROM, TO) \ | |
68 | GET_FIELD(X, 31 - (TO), 31 - (FROM)) | |
69 | ||
70 | #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) | |
46d38ba8 | 71 | #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1)) |
3475187d FB |
72 | |
73 | #ifdef TARGET_SPARC64 | |
19f329ad | 74 | #define FFPREG(r) (r) |
0387d928 | 75 | #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e)) |
1f587329 | 76 | #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c)) |
3475187d | 77 | #else |
19f329ad | 78 | #define FFPREG(r) (r) |
c185970a | 79 | #define DFPREG(r) (r & 0x1e) |
1f587329 | 80 | #define QFPREG(r) (r & 0x1c) |
3475187d FB |
81 | #endif |
82 | ||
83 | static int sign_extend(int x, int len) | |
84 | { | |
85 | len = 32 - len; | |
86 | return (x << len) >> len; | |
87 | } | |
88 | ||
7a3f1944 FB |
89 | #define IS_IMM (insn & (1<<13)) |
90 | ||
ff07ec83 BS |
91 | /* floating point registers moves */ |
92 | static void gen_op_load_fpr_FT0(unsigned int src) | |
93 | { | |
8911f501 BS |
94 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
95 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0)); | |
3475187d | 96 | } |
ff07ec83 BS |
97 | |
98 | static void gen_op_load_fpr_FT1(unsigned int src) | |
99 | { | |
8911f501 BS |
100 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
101 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1)); | |
e8af50a3 FB |
102 | } |
103 | ||
ff07ec83 BS |
104 | static void gen_op_store_FT0_fpr(unsigned int dst) |
105 | { | |
8911f501 BS |
106 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0)); |
107 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst])); | |
ff07ec83 BS |
108 | } |
109 | ||
110 | static void gen_op_load_fpr_DT0(unsigned int src) | |
111 | { | |
8911f501 | 112 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
77f193da BS |
113 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + |
114 | offsetof(CPU_DoubleU, l.upper)); | |
8911f501 | 115 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1])); |
77f193da BS |
116 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + |
117 | offsetof(CPU_DoubleU, l.lower)); | |
ff07ec83 BS |
118 | } |
119 | ||
120 | static void gen_op_load_fpr_DT1(unsigned int src) | |
121 | { | |
8911f501 | 122 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
77f193da BS |
123 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + |
124 | offsetof(CPU_DoubleU, l.upper)); | |
8911f501 | 125 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1])); |
77f193da BS |
126 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + |
127 | offsetof(CPU_DoubleU, l.lower)); | |
ff07ec83 BS |
128 | } |
129 | ||
130 | static void gen_op_store_DT0_fpr(unsigned int dst) | |
131 | { | |
77f193da BS |
132 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + |
133 | offsetof(CPU_DoubleU, l.upper)); | |
8911f501 | 134 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst])); |
77f193da BS |
135 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + |
136 | offsetof(CPU_DoubleU, l.lower)); | |
8911f501 | 137 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1])); |
ff07ec83 BS |
138 | } |
139 | ||
ff07ec83 BS |
140 | static void gen_op_load_fpr_QT0(unsigned int src) |
141 | { | |
8911f501 | 142 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
77f193da BS |
143 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
144 | offsetof(CPU_QuadU, l.upmost)); | |
8911f501 | 145 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1])); |
77f193da BS |
146 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
147 | offsetof(CPU_QuadU, l.upper)); | |
8911f501 | 148 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2])); |
77f193da BS |
149 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
150 | offsetof(CPU_QuadU, l.lower)); | |
8911f501 | 151 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3])); |
77f193da BS |
152 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
153 | offsetof(CPU_QuadU, l.lowest)); | |
ff07ec83 BS |
154 | } |
155 | ||
156 | static void gen_op_load_fpr_QT1(unsigned int src) | |
157 | { | |
8911f501 | 158 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
77f193da BS |
159 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + |
160 | offsetof(CPU_QuadU, l.upmost)); | |
8911f501 | 161 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1])); |
77f193da BS |
162 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + |
163 | offsetof(CPU_QuadU, l.upper)); | |
8911f501 | 164 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2])); |
77f193da BS |
165 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + |
166 | offsetof(CPU_QuadU, l.lower)); | |
8911f501 | 167 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3])); |
77f193da BS |
168 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + |
169 | offsetof(CPU_QuadU, l.lowest)); | |
ff07ec83 BS |
170 | } |
171 | ||
172 | static void gen_op_store_QT0_fpr(unsigned int dst) | |
173 | { | |
77f193da BS |
174 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
175 | offsetof(CPU_QuadU, l.upmost)); | |
8911f501 | 176 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst])); |
77f193da BS |
177 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
178 | offsetof(CPU_QuadU, l.upper)); | |
8911f501 | 179 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1])); |
77f193da BS |
180 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
181 | offsetof(CPU_QuadU, l.lower)); | |
8911f501 | 182 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2])); |
77f193da BS |
183 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + |
184 | offsetof(CPU_QuadU, l.lowest)); | |
8911f501 | 185 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3])); |
ff07ec83 | 186 | } |
1f587329 | 187 | |
81ad8ba2 BS |
188 | /* moves */ |
189 | #ifdef CONFIG_USER_ONLY | |
3475187d | 190 | #define supervisor(dc) 0 |
81ad8ba2 | 191 | #ifdef TARGET_SPARC64 |
e9ebed4d | 192 | #define hypervisor(dc) 0 |
81ad8ba2 | 193 | #endif |
3475187d | 194 | #else |
6f27aba6 | 195 | #define supervisor(dc) (dc->mem_idx >= 1) |
81ad8ba2 BS |
196 | #ifdef TARGET_SPARC64 |
197 | #define hypervisor(dc) (dc->mem_idx == 2) | |
6f27aba6 | 198 | #else |
3475187d | 199 | #endif |
81ad8ba2 BS |
200 | #endif |
201 | ||
1a2fb1c0 | 202 | #ifdef TARGET_ABI32 |
8911f501 | 203 | #define ABI32_MASK(addr) tcg_gen_andi_tl(addr, addr, 0xffffffffULL); |
1a2fb1c0 BS |
204 | #else |
205 | #define ABI32_MASK(addr) | |
206 | #endif | |
3391c818 | 207 | |
1a2fb1c0 | 208 | static inline void gen_movl_reg_TN(int reg, TCGv tn) |
81ad8ba2 | 209 | { |
1a2fb1c0 BS |
210 | if (reg == 0) |
211 | tcg_gen_movi_tl(tn, 0); | |
212 | else if (reg < 8) | |
f5069b26 | 213 | tcg_gen_mov_tl(tn, cpu_gregs[reg]); |
1a2fb1c0 | 214 | else { |
1a2fb1c0 | 215 | tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
81ad8ba2 BS |
216 | } |
217 | } | |
218 | ||
1a2fb1c0 | 219 | static inline void gen_movl_TN_reg(int reg, TCGv tn) |
81ad8ba2 | 220 | { |
1a2fb1c0 BS |
221 | if (reg == 0) |
222 | return; | |
223 | else if (reg < 8) | |
f5069b26 | 224 | tcg_gen_mov_tl(cpu_gregs[reg], tn); |
1a2fb1c0 | 225 | else { |
1a2fb1c0 | 226 | tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
81ad8ba2 BS |
227 | } |
228 | } | |
229 | ||
5fafdf24 | 230 | static inline void gen_goto_tb(DisasContext *s, int tb_num, |
6e256c93 FB |
231 | target_ulong pc, target_ulong npc) |
232 | { | |
233 | TranslationBlock *tb; | |
234 | ||
235 | tb = s->tb; | |
236 | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) && | |
237 | (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) { | |
238 | /* jump to same page: we can use a direct jump */ | |
57fec1fe | 239 | tcg_gen_goto_tb(tb_num); |
2f5680ee BS |
240 | tcg_gen_movi_tl(cpu_pc, pc); |
241 | tcg_gen_movi_tl(cpu_npc, npc); | |
57fec1fe | 242 | tcg_gen_exit_tb((long)tb + tb_num); |
6e256c93 FB |
243 | } else { |
244 | /* jump to another page: currently not optimized */ | |
2f5680ee BS |
245 | tcg_gen_movi_tl(cpu_pc, pc); |
246 | tcg_gen_movi_tl(cpu_npc, npc); | |
57fec1fe | 247 | tcg_gen_exit_tb(0); |
6e256c93 FB |
248 | } |
249 | } | |
250 | ||
19f329ad BS |
251 | // XXX suboptimal |
252 | static inline void gen_mov_reg_N(TCGv reg, TCGv src) | |
253 | { | |
8911f501 | 254 | tcg_gen_extu_i32_tl(reg, src); |
4b8b8b76 | 255 | tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT); |
19f329ad BS |
256 | tcg_gen_andi_tl(reg, reg, 0x1); |
257 | } | |
258 | ||
259 | static inline void gen_mov_reg_Z(TCGv reg, TCGv src) | |
260 | { | |
8911f501 | 261 | tcg_gen_extu_i32_tl(reg, src); |
4b8b8b76 | 262 | tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT); |
19f329ad BS |
263 | tcg_gen_andi_tl(reg, reg, 0x1); |
264 | } | |
265 | ||
266 | static inline void gen_mov_reg_V(TCGv reg, TCGv src) | |
267 | { | |
8911f501 | 268 | tcg_gen_extu_i32_tl(reg, src); |
4b8b8b76 | 269 | tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT); |
19f329ad BS |
270 | tcg_gen_andi_tl(reg, reg, 0x1); |
271 | } | |
272 | ||
273 | static inline void gen_mov_reg_C(TCGv reg, TCGv src) | |
274 | { | |
8911f501 | 275 | tcg_gen_extu_i32_tl(reg, src); |
4b8b8b76 | 276 | tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT); |
19f329ad BS |
277 | tcg_gen_andi_tl(reg, reg, 0x1); |
278 | } | |
279 | ||
ce5b3c3d | 280 | static inline void gen_cc_clear_icc(void) |
dc99a3f2 BS |
281 | { |
282 | tcg_gen_movi_i32(cpu_psr, 0); | |
ce5b3c3d BS |
283 | } |
284 | ||
dc99a3f2 | 285 | #ifdef TARGET_SPARC64 |
ce5b3c3d BS |
286 | static inline void gen_cc_clear_xcc(void) |
287 | { | |
dc99a3f2 | 288 | tcg_gen_movi_i32(cpu_xcc, 0); |
dc99a3f2 | 289 | } |
ce5b3c3d | 290 | #endif |
dc99a3f2 BS |
291 | |
292 | /* old op: | |
293 | if (!T0) | |
294 | env->psr |= PSR_ZERO; | |
295 | if ((int32_t) T0 < 0) | |
296 | env->psr |= PSR_NEG; | |
297 | */ | |
ce5b3c3d | 298 | static inline void gen_cc_NZ_icc(TCGv dst) |
dc99a3f2 | 299 | { |
8911f501 | 300 | TCGv r_temp; |
dc99a3f2 | 301 | int l1, l2; |
dc99a3f2 BS |
302 | |
303 | l1 = gen_new_label(); | |
304 | l2 = gen_new_label(); | |
8911f501 BS |
305 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
306 | tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL); | |
cb63669a | 307 | tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1); |
dc99a3f2 BS |
308 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO); |
309 | gen_set_label(l1); | |
bdf46ea2 | 310 | tcg_gen_ext_i32_tl(r_temp, dst); |
cb63669a | 311 | tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2); |
dc99a3f2 BS |
312 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG); |
313 | gen_set_label(l2); | |
ce5b3c3d BS |
314 | } |
315 | ||
dc99a3f2 | 316 | #ifdef TARGET_SPARC64 |
ce5b3c3d BS |
317 | static inline void gen_cc_NZ_xcc(TCGv dst) |
318 | { | |
319 | int l1, l2; | |
320 | ||
321 | l1 = gen_new_label(); | |
322 | l2 = gen_new_label(); | |
cb63669a | 323 | tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1); |
ce5b3c3d BS |
324 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO); |
325 | gen_set_label(l1); | |
cb63669a | 326 | tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2); |
ce5b3c3d BS |
327 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG); |
328 | gen_set_label(l2); | |
dc99a3f2 | 329 | } |
ce5b3c3d | 330 | #endif |
dc99a3f2 BS |
331 | |
332 | /* old op: | |
333 | if (T0 < src1) | |
334 | env->psr |= PSR_CARRY; | |
335 | */ | |
ce5b3c3d | 336 | static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1) |
dc99a3f2 | 337 | { |
8911f501 | 338 | TCGv r_temp; |
dc99a3f2 BS |
339 | int l1; |
340 | ||
341 | l1 = gen_new_label(); | |
8911f501 BS |
342 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
343 | tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL); | |
344 | tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1); | |
dc99a3f2 BS |
345 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
346 | gen_set_label(l1); | |
ce5b3c3d BS |
347 | } |
348 | ||
dc99a3f2 | 349 | #ifdef TARGET_SPARC64 |
ce5b3c3d BS |
350 | static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1) |
351 | { | |
352 | int l1; | |
dc99a3f2 | 353 | |
ce5b3c3d BS |
354 | l1 = gen_new_label(); |
355 | tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1); | |
356 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); | |
357 | gen_set_label(l1); | |
dc99a3f2 | 358 | } |
ce5b3c3d | 359 | #endif |
dc99a3f2 BS |
360 | |
361 | /* old op: | |
362 | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31)) | |
363 | env->psr |= PSR_OVF; | |
364 | */ | |
ce5b3c3d | 365 | static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 366 | { |
0425bee5 | 367 | TCGv r_temp; |
dc99a3f2 BS |
368 | |
369 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
dc99a3f2 BS |
370 | tcg_gen_xor_tl(r_temp, src1, src2); |
371 | tcg_gen_xori_tl(r_temp, r_temp, -1); | |
0425bee5 BS |
372 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
373 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
374 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); | |
653ccb80 BS |
375 | tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT); |
376 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); | |
377 | tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32); | |
ce5b3c3d BS |
378 | } |
379 | ||
dc99a3f2 | 380 | #ifdef TARGET_SPARC64 |
ce5b3c3d BS |
381 | static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2) |
382 | { | |
383 | TCGv r_temp; | |
ce5b3c3d BS |
384 | |
385 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
386 | tcg_gen_xor_tl(r_temp, src1, src2); | |
387 | tcg_gen_xori_tl(r_temp, r_temp, -1); | |
388 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); | |
389 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
390 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | |
653ccb80 BS |
391 | tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT); |
392 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); | |
393 | tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32); | |
dc99a3f2 | 394 | } |
ce5b3c3d | 395 | #endif |
dc99a3f2 BS |
396 | |
397 | static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) | |
398 | { | |
0425bee5 | 399 | TCGv r_temp; |
dc99a3f2 BS |
400 | int l1; |
401 | ||
402 | l1 = gen_new_label(); | |
403 | ||
404 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
dc99a3f2 BS |
405 | tcg_gen_xor_tl(r_temp, src1, src2); |
406 | tcg_gen_xori_tl(r_temp, r_temp, -1); | |
0425bee5 BS |
407 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
408 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
409 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); | |
cb63669a | 410 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1); |
2f5680ee | 411 | tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF)); |
dc99a3f2 | 412 | gen_set_label(l1); |
dc99a3f2 BS |
413 | } |
414 | ||
415 | static inline void gen_cc_V_tag(TCGv src1, TCGv src2) | |
416 | { | |
417 | int l1; | |
dc99a3f2 BS |
418 | |
419 | l1 = gen_new_label(); | |
0425bee5 BS |
420 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
421 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3); | |
cb63669a | 422 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1); |
dc99a3f2 BS |
423 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
424 | gen_set_label(l1); | |
425 | } | |
426 | ||
427 | static inline void gen_tag_tv(TCGv src1, TCGv src2) | |
428 | { | |
429 | int l1; | |
dc99a3f2 BS |
430 | |
431 | l1 = gen_new_label(); | |
0425bee5 BS |
432 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
433 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3); | |
cb63669a | 434 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1); |
2f5680ee | 435 | tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF)); |
dc99a3f2 BS |
436 | gen_set_label(l1); |
437 | } | |
438 | ||
4af984a7 | 439 | static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 440 | { |
4af984a7 | 441 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 | 442 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
4af984a7 | 443 | tcg_gen_add_tl(dst, src1, src2); |
ba28189b | 444 | tcg_gen_mov_tl(cpu_cc_dst, dst); |
ce5b3c3d | 445 | gen_cc_clear_icc(); |
ba28189b BS |
446 | gen_cc_NZ_icc(cpu_cc_dst); |
447 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); | |
448 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d BS |
449 | #ifdef TARGET_SPARC64 |
450 | gen_cc_clear_xcc(); | |
ba28189b BS |
451 | gen_cc_NZ_xcc(cpu_cc_dst); |
452 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); | |
453 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 454 | #endif |
dc99a3f2 BS |
455 | } |
456 | ||
4af984a7 | 457 | static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 458 | { |
4af984a7 | 459 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 | 460 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
dc99a3f2 | 461 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
4af984a7 | 462 | tcg_gen_add_tl(dst, src1, cpu_tmp0); |
ce5b3c3d | 463 | gen_cc_clear_icc(); |
4af984a7 | 464 | gen_cc_C_add_icc(dst, cpu_cc_src); |
ce5b3c3d BS |
465 | #ifdef TARGET_SPARC64 |
466 | gen_cc_clear_xcc(); | |
4af984a7 | 467 | gen_cc_C_add_xcc(dst, cpu_cc_src); |
ce5b3c3d | 468 | #endif |
6f551262 | 469 | tcg_gen_add_tl(dst, dst, cpu_cc_src2); |
ba28189b BS |
470 | tcg_gen_mov_tl(cpu_cc_dst, dst); |
471 | gen_cc_NZ_icc(cpu_cc_dst); | |
472 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); | |
473 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 474 | #ifdef TARGET_SPARC64 |
ba28189b BS |
475 | gen_cc_NZ_xcc(cpu_cc_dst); |
476 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); | |
477 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 478 | #endif |
dc99a3f2 BS |
479 | } |
480 | ||
4af984a7 | 481 | static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 482 | { |
4af984a7 | 483 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 | 484 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
4af984a7 | 485 | tcg_gen_add_tl(dst, src1, src2); |
ba28189b | 486 | tcg_gen_mov_tl(cpu_cc_dst, dst); |
ce5b3c3d | 487 | gen_cc_clear_icc(); |
ba28189b BS |
488 | gen_cc_NZ_icc(cpu_cc_dst); |
489 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); | |
490 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
6f551262 | 491 | gen_cc_V_tag(cpu_cc_src, cpu_cc_src2); |
ce5b3c3d BS |
492 | #ifdef TARGET_SPARC64 |
493 | gen_cc_clear_xcc(); | |
ba28189b BS |
494 | gen_cc_NZ_xcc(cpu_cc_dst); |
495 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); | |
496 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 497 | #endif |
dc99a3f2 BS |
498 | } |
499 | ||
4af984a7 | 500 | static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 501 | { |
4af984a7 | 502 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 BS |
503 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
504 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); | |
4af984a7 | 505 | tcg_gen_add_tl(dst, src1, src2); |
ba28189b | 506 | tcg_gen_mov_tl(cpu_cc_dst, dst); |
6f551262 | 507 | gen_add_tv(dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d | 508 | gen_cc_clear_icc(); |
ba28189b BS |
509 | gen_cc_NZ_icc(cpu_cc_dst); |
510 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); | |
ce5b3c3d BS |
511 | #ifdef TARGET_SPARC64 |
512 | gen_cc_clear_xcc(); | |
ba28189b BS |
513 | gen_cc_NZ_xcc(cpu_cc_dst); |
514 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); | |
515 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 516 | #endif |
dc99a3f2 BS |
517 | } |
518 | ||
519 | /* old op: | |
520 | if (src1 < T1) | |
521 | env->psr |= PSR_CARRY; | |
522 | */ | |
ce5b3c3d | 523 | static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2) |
dc99a3f2 | 524 | { |
8911f501 | 525 | TCGv r_temp1, r_temp2; |
dc99a3f2 BS |
526 | int l1; |
527 | ||
528 | l1 = gen_new_label(); | |
8911f501 BS |
529 | r_temp1 = tcg_temp_new(TCG_TYPE_TL); |
530 | r_temp2 = tcg_temp_new(TCG_TYPE_TL); | |
531 | tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL); | |
532 | tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL); | |
533 | tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1); | |
dc99a3f2 BS |
534 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
535 | gen_set_label(l1); | |
ce5b3c3d BS |
536 | } |
537 | ||
dc99a3f2 | 538 | #ifdef TARGET_SPARC64 |
ce5b3c3d BS |
539 | static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2) |
540 | { | |
541 | int l1; | |
dc99a3f2 | 542 | |
ce5b3c3d BS |
543 | l1 = gen_new_label(); |
544 | tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1); | |
545 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); | |
546 | gen_set_label(l1); | |
dc99a3f2 | 547 | } |
ce5b3c3d | 548 | #endif |
dc99a3f2 BS |
549 | |
550 | /* old op: | |
551 | if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31)) | |
552 | env->psr |= PSR_OVF; | |
553 | */ | |
ce5b3c3d | 554 | static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 555 | { |
0425bee5 | 556 | TCGv r_temp; |
dc99a3f2 BS |
557 | |
558 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
dc99a3f2 | 559 | tcg_gen_xor_tl(r_temp, src1, src2); |
0425bee5 BS |
560 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
561 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
562 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); | |
653ccb80 BS |
563 | tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT); |
564 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); | |
565 | tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32); | |
ce5b3c3d BS |
566 | } |
567 | ||
dc99a3f2 | 568 | #ifdef TARGET_SPARC64 |
ce5b3c3d BS |
569 | static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2) |
570 | { | |
571 | TCGv r_temp; | |
ce5b3c3d BS |
572 | |
573 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
574 | tcg_gen_xor_tl(r_temp, src1, src2); | |
575 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); | |
576 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
577 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | |
653ccb80 BS |
578 | tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT); |
579 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); | |
580 | tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32); | |
dc99a3f2 | 581 | } |
ce5b3c3d | 582 | #endif |
dc99a3f2 BS |
583 | |
584 | static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) | |
585 | { | |
0425bee5 | 586 | TCGv r_temp; |
dc99a3f2 BS |
587 | int l1; |
588 | ||
589 | l1 = gen_new_label(); | |
590 | ||
591 | r_temp = tcg_temp_new(TCG_TYPE_TL); | |
dc99a3f2 | 592 | tcg_gen_xor_tl(r_temp, src1, src2); |
0425bee5 BS |
593 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
594 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
595 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); | |
cb63669a | 596 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1); |
2f5680ee | 597 | tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF)); |
dc99a3f2 | 598 | gen_set_label(l1); |
dc99a3f2 BS |
599 | } |
600 | ||
4af984a7 | 601 | static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 602 | { |
4af984a7 | 603 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 | 604 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
4af984a7 | 605 | tcg_gen_sub_tl(dst, src1, src2); |
ba28189b | 606 | tcg_gen_mov_tl(cpu_cc_dst, dst); |
ce5b3c3d | 607 | gen_cc_clear_icc(); |
ba28189b | 608 | gen_cc_NZ_icc(cpu_cc_dst); |
6f551262 | 609 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
ba28189b | 610 | gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d BS |
611 | #ifdef TARGET_SPARC64 |
612 | gen_cc_clear_xcc(); | |
ba28189b | 613 | gen_cc_NZ_xcc(cpu_cc_dst); |
6f551262 | 614 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
ba28189b | 615 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d | 616 | #endif |
dc99a3f2 BS |
617 | } |
618 | ||
4af984a7 | 619 | static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 620 | { |
4af984a7 | 621 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 | 622 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
dc99a3f2 | 623 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
4af984a7 | 624 | tcg_gen_sub_tl(dst, src1, cpu_tmp0); |
ce5b3c3d | 625 | gen_cc_clear_icc(); |
4af984a7 | 626 | gen_cc_C_sub_icc(dst, cpu_cc_src); |
ce5b3c3d BS |
627 | #ifdef TARGET_SPARC64 |
628 | gen_cc_clear_xcc(); | |
4af984a7 | 629 | gen_cc_C_sub_xcc(dst, cpu_cc_src); |
ce5b3c3d | 630 | #endif |
6f551262 | 631 | tcg_gen_sub_tl(dst, dst, cpu_cc_src2); |
ba28189b BS |
632 | tcg_gen_mov_tl(cpu_cc_dst, dst); |
633 | gen_cc_NZ_icc(cpu_cc_dst); | |
634 | gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); | |
635 | gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 636 | #ifdef TARGET_SPARC64 |
ba28189b BS |
637 | gen_cc_NZ_xcc(cpu_cc_dst); |
638 | gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); | |
639 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
ce5b3c3d | 640 | #endif |
dc99a3f2 BS |
641 | } |
642 | ||
4af984a7 | 643 | static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 644 | { |
4af984a7 | 645 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 | 646 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
4af984a7 | 647 | tcg_gen_sub_tl(dst, src1, src2); |
ba28189b | 648 | tcg_gen_mov_tl(cpu_cc_dst, dst); |
ce5b3c3d | 649 | gen_cc_clear_icc(); |
ba28189b | 650 | gen_cc_NZ_icc(cpu_cc_dst); |
6f551262 | 651 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
ba28189b | 652 | gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
6f551262 | 653 | gen_cc_V_tag(cpu_cc_src, cpu_cc_src2); |
ce5b3c3d BS |
654 | #ifdef TARGET_SPARC64 |
655 | gen_cc_clear_xcc(); | |
ba28189b | 656 | gen_cc_NZ_xcc(cpu_cc_dst); |
6f551262 | 657 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
ba28189b | 658 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d | 659 | #endif |
dc99a3f2 BS |
660 | } |
661 | ||
4af984a7 | 662 | static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2) |
dc99a3f2 | 663 | { |
4af984a7 | 664 | tcg_gen_mov_tl(cpu_cc_src, src1); |
6f551262 BS |
665 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
666 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); | |
4af984a7 | 667 | tcg_gen_sub_tl(dst, src1, src2); |
ba28189b | 668 | tcg_gen_mov_tl(cpu_cc_dst, dst); |
6f551262 | 669 | gen_sub_tv(dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d | 670 | gen_cc_clear_icc(); |
ba28189b | 671 | gen_cc_NZ_icc(cpu_cc_dst); |
6f551262 | 672 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
ce5b3c3d BS |
673 | #ifdef TARGET_SPARC64 |
674 | gen_cc_clear_xcc(); | |
ba28189b | 675 | gen_cc_NZ_xcc(cpu_cc_dst); |
6f551262 | 676 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
ba28189b | 677 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
ce5b3c3d | 678 | #endif |
dc99a3f2 BS |
679 | } |
680 | ||
4af984a7 | 681 | static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) |
d9bdab86 | 682 | { |
7127fe84 | 683 | TCGv r_temp, r_temp2; |
6f551262 | 684 | int l1; |
d9bdab86 BS |
685 | |
686 | l1 = gen_new_label(); | |
d9bdab86 | 687 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
7127fe84 | 688 | r_temp2 = tcg_temp_new(TCG_TYPE_I32); |
d9bdab86 BS |
689 | |
690 | /* old op: | |
691 | if (!(env->y & 1)) | |
692 | T1 = 0; | |
693 | */ | |
6f551262 | 694 | tcg_gen_mov_tl(cpu_cc_src, src1); |
7127fe84 BS |
695 | tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y)); |
696 | tcg_gen_trunc_tl_i32(r_temp2, r_temp); | |
697 | tcg_gen_andi_i32(r_temp2, r_temp2, 0x1); | |
4af984a7 | 698 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
cb63669a | 699 | tcg_gen_brcondi_i32(TCG_COND_NE, r_temp2, 0, l1); |
d9bdab86 | 700 | tcg_gen_movi_tl(cpu_cc_src2, 0); |
6f551262 | 701 | gen_set_label(l1); |
d9bdab86 BS |
702 | |
703 | // b2 = T0 & 1; | |
704 | // env->y = (b2 << 31) | (env->y >> 1); | |
6f551262 | 705 | tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src); |
7127fe84 BS |
706 | tcg_gen_andi_i32(r_temp2, r_temp2, 0x1); |
707 | tcg_gen_shli_i32(r_temp2, r_temp2, 31); | |
8911f501 BS |
708 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y)); |
709 | tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1); | |
7127fe84 | 710 | tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2); |
8911f501 | 711 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y)); |
d9bdab86 BS |
712 | |
713 | // b1 = N ^ V; | |
714 | gen_mov_reg_N(cpu_tmp0, cpu_psr); | |
715 | gen_mov_reg_V(r_temp, cpu_psr); | |
716 | tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp); | |
717 | ||
718 | // T0 = (b1 << 31) | (T0 >> 1); | |
719 | // src1 = T0; | |
720 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31); | |
6f551262 | 721 | tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1); |
d9bdab86 BS |
722 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); |
723 | ||
724 | /* do addition and update flags */ | |
4af984a7 | 725 | tcg_gen_add_tl(dst, cpu_cc_src, cpu_cc_src2); |
ba28189b | 726 | tcg_gen_mov_tl(cpu_cc_dst, dst); |
d9bdab86 | 727 | |
ce5b3c3d | 728 | gen_cc_clear_icc(); |
ba28189b BS |
729 | gen_cc_NZ_icc(cpu_cc_dst); |
730 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); | |
731 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); | |
d9bdab86 BS |
732 | } |
733 | ||
4af984a7 | 734 | static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) |
8879d139 BS |
735 | { |
736 | TCGv r_temp, r_temp2; | |
737 | ||
738 | r_temp = tcg_temp_new(TCG_TYPE_I64); | |
739 | r_temp2 = tcg_temp_new(TCG_TYPE_I64); | |
740 | ||
4af984a7 BS |
741 | tcg_gen_extu_tl_i64(r_temp, src2); |
742 | tcg_gen_extu_tl_i64(r_temp2, src1); | |
8879d139 BS |
743 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
744 | ||
745 | tcg_gen_shri_i64(r_temp, r_temp2, 32); | |
746 | tcg_gen_trunc_i64_i32(r_temp, r_temp); | |
747 | tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); | |
748 | #ifdef TARGET_SPARC64 | |
4af984a7 | 749 | tcg_gen_mov_i64(dst, r_temp2); |
8879d139 | 750 | #else |
4af984a7 | 751 | tcg_gen_trunc_i64_tl(dst, r_temp2); |
8879d139 | 752 | #endif |
8879d139 BS |
753 | } |
754 | ||
4af984a7 | 755 | static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) |
8879d139 BS |
756 | { |
757 | TCGv r_temp, r_temp2; | |
758 | ||
759 | r_temp = tcg_temp_new(TCG_TYPE_I64); | |
760 | r_temp2 = tcg_temp_new(TCG_TYPE_I64); | |
761 | ||
4af984a7 BS |
762 | tcg_gen_ext_tl_i64(r_temp, src2); |
763 | tcg_gen_ext_tl_i64(r_temp2, src1); | |
8879d139 BS |
764 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
765 | ||
766 | tcg_gen_shri_i64(r_temp, r_temp2, 32); | |
767 | tcg_gen_trunc_i64_i32(r_temp, r_temp); | |
768 | tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); | |
769 | #ifdef TARGET_SPARC64 | |
4af984a7 | 770 | tcg_gen_mov_i64(dst, r_temp2); |
8879d139 | 771 | #else |
4af984a7 | 772 | tcg_gen_trunc_i64_tl(dst, r_temp2); |
8879d139 | 773 | #endif |
8879d139 BS |
774 | } |
775 | ||
1a7b60e7 | 776 | #ifdef TARGET_SPARC64 |
8911f501 | 777 | static inline void gen_trap_ifdivzero_tl(TCGv divisor) |
1a7b60e7 BS |
778 | { |
779 | int l1; | |
780 | ||
781 | l1 = gen_new_label(); | |
cb63669a | 782 | tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1); |
2f5680ee | 783 | tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_DIV_ZERO)); |
1a7b60e7 BS |
784 | gen_set_label(l1); |
785 | } | |
786 | ||
4af984a7 | 787 | static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2) |
1a7b60e7 BS |
788 | { |
789 | int l1, l2; | |
790 | ||
791 | l1 = gen_new_label(); | |
792 | l2 = gen_new_label(); | |
6f551262 BS |
793 | tcg_gen_mov_tl(cpu_cc_src, src1); |
794 | tcg_gen_mov_tl(cpu_cc_src2, src2); | |
4af984a7 | 795 | gen_trap_ifdivzero_tl(src2); |
cb63669a PB |
796 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1); |
797 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1); | |
4af984a7 | 798 | tcg_gen_movi_i64(dst, INT64_MIN); |
06b3e1b3 | 799 | tcg_gen_br(l2); |
1a7b60e7 | 800 | gen_set_label(l1); |
6f551262 | 801 | tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2); |
1a7b60e7 BS |
802 | gen_set_label(l2); |
803 | } | |
804 | #endif | |
805 | ||
4af984a7 | 806 | static inline void gen_op_div_cc(TCGv dst) |
dc99a3f2 BS |
807 | { |
808 | int l1; | |
dc99a3f2 | 809 | |
ba28189b | 810 | tcg_gen_mov_tl(cpu_cc_dst, dst); |
ce5b3c3d | 811 | gen_cc_clear_icc(); |
ba28189b | 812 | gen_cc_NZ_icc(cpu_cc_dst); |
dc99a3f2 | 813 | l1 = gen_new_label(); |
3b89f26c | 814 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2)); |
cb63669a | 815 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1); |
dc99a3f2 BS |
816 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
817 | gen_set_label(l1); | |
818 | } | |
819 | ||
4af984a7 | 820 | static inline void gen_op_logic_cc(TCGv dst) |
dc99a3f2 | 821 | { |
ba28189b BS |
822 | tcg_gen_mov_tl(cpu_cc_dst, dst); |
823 | ||
ce5b3c3d | 824 | gen_cc_clear_icc(); |
ba28189b | 825 | gen_cc_NZ_icc(cpu_cc_dst); |
ce5b3c3d BS |
826 | #ifdef TARGET_SPARC64 |
827 | gen_cc_clear_xcc(); | |
ba28189b | 828 | gen_cc_NZ_xcc(cpu_cc_dst); |
ce5b3c3d | 829 | #endif |
dc99a3f2 BS |
830 | } |
831 | ||
19f329ad BS |
832 | // 1 |
833 | static inline void gen_op_eval_ba(TCGv dst) | |
834 | { | |
835 | tcg_gen_movi_tl(dst, 1); | |
836 | } | |
837 | ||
838 | // Z | |
839 | static inline void gen_op_eval_be(TCGv dst, TCGv src) | |
840 | { | |
841 | gen_mov_reg_Z(dst, src); | |
842 | } | |
843 | ||
844 | // Z | (N ^ V) | |
845 | static inline void gen_op_eval_ble(TCGv dst, TCGv src) | |
846 | { | |
0425bee5 | 847 | gen_mov_reg_N(cpu_tmp0, src); |
19f329ad | 848 | gen_mov_reg_V(dst, src); |
0425bee5 BS |
849 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
850 | gen_mov_reg_Z(cpu_tmp0, src); | |
851 | tcg_gen_or_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
852 | } |
853 | ||
854 | // N ^ V | |
855 | static inline void gen_op_eval_bl(TCGv dst, TCGv src) | |
856 | { | |
0425bee5 | 857 | gen_mov_reg_V(cpu_tmp0, src); |
19f329ad | 858 | gen_mov_reg_N(dst, src); |
0425bee5 | 859 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
19f329ad BS |
860 | } |
861 | ||
862 | // C | Z | |
863 | static inline void gen_op_eval_bleu(TCGv dst, TCGv src) | |
864 | { | |
0425bee5 | 865 | gen_mov_reg_Z(cpu_tmp0, src); |
19f329ad | 866 | gen_mov_reg_C(dst, src); |
0425bee5 | 867 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
19f329ad BS |
868 | } |
869 | ||
870 | // C | |
871 | static inline void gen_op_eval_bcs(TCGv dst, TCGv src) | |
872 | { | |
873 | gen_mov_reg_C(dst, src); | |
874 | } | |
875 | ||
876 | // V | |
877 | static inline void gen_op_eval_bvs(TCGv dst, TCGv src) | |
878 | { | |
879 | gen_mov_reg_V(dst, src); | |
880 | } | |
881 | ||
882 | // 0 | |
883 | static inline void gen_op_eval_bn(TCGv dst) | |
884 | { | |
885 | tcg_gen_movi_tl(dst, 0); | |
886 | } | |
887 | ||
888 | // N | |
889 | static inline void gen_op_eval_bneg(TCGv dst, TCGv src) | |
890 | { | |
891 | gen_mov_reg_N(dst, src); | |
892 | } | |
893 | ||
894 | // !Z | |
895 | static inline void gen_op_eval_bne(TCGv dst, TCGv src) | |
896 | { | |
897 | gen_mov_reg_Z(dst, src); | |
898 | tcg_gen_xori_tl(dst, dst, 0x1); | |
899 | } | |
900 | ||
901 | // !(Z | (N ^ V)) | |
902 | static inline void gen_op_eval_bg(TCGv dst, TCGv src) | |
903 | { | |
0425bee5 | 904 | gen_mov_reg_N(cpu_tmp0, src); |
19f329ad | 905 | gen_mov_reg_V(dst, src); |
0425bee5 BS |
906 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
907 | gen_mov_reg_Z(cpu_tmp0, src); | |
908 | tcg_gen_or_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
909 | tcg_gen_xori_tl(dst, dst, 0x1); |
910 | } | |
911 | ||
912 | // !(N ^ V) | |
913 | static inline void gen_op_eval_bge(TCGv dst, TCGv src) | |
914 | { | |
0425bee5 | 915 | gen_mov_reg_V(cpu_tmp0, src); |
19f329ad | 916 | gen_mov_reg_N(dst, src); |
0425bee5 | 917 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
19f329ad BS |
918 | tcg_gen_xori_tl(dst, dst, 0x1); |
919 | } | |
920 | ||
921 | // !(C | Z) | |
922 | static inline void gen_op_eval_bgu(TCGv dst, TCGv src) | |
923 | { | |
0425bee5 | 924 | gen_mov_reg_Z(cpu_tmp0, src); |
19f329ad | 925 | gen_mov_reg_C(dst, src); |
0425bee5 | 926 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
19f329ad BS |
927 | tcg_gen_xori_tl(dst, dst, 0x1); |
928 | } | |
929 | ||
930 | // !C | |
931 | static inline void gen_op_eval_bcc(TCGv dst, TCGv src) | |
932 | { | |
933 | gen_mov_reg_C(dst, src); | |
934 | tcg_gen_xori_tl(dst, dst, 0x1); | |
935 | } | |
936 | ||
937 | // !N | |
938 | static inline void gen_op_eval_bpos(TCGv dst, TCGv src) | |
939 | { | |
940 | gen_mov_reg_N(dst, src); | |
941 | tcg_gen_xori_tl(dst, dst, 0x1); | |
942 | } | |
943 | ||
944 | // !V | |
945 | static inline void gen_op_eval_bvc(TCGv dst, TCGv src) | |
946 | { | |
947 | gen_mov_reg_V(dst, src); | |
948 | tcg_gen_xori_tl(dst, dst, 0x1); | |
949 | } | |
950 | ||
951 | /* | |
952 | FPSR bit field FCC1 | FCC0: | |
953 | 0 = | |
954 | 1 < | |
955 | 2 > | |
956 | 3 unordered | |
957 | */ | |
958 | static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, | |
959 | unsigned int fcc_offset) | |
960 | { | |
8911f501 | 961 | tcg_gen_extu_i32_tl(reg, src); |
4b8b8b76 | 962 | tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset); |
19f329ad BS |
963 | tcg_gen_andi_tl(reg, reg, 0x1); |
964 | } | |
965 | ||
966 | static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, | |
967 | unsigned int fcc_offset) | |
968 | { | |
8911f501 | 969 | tcg_gen_extu_i32_tl(reg, src); |
4b8b8b76 | 970 | tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset); |
19f329ad BS |
971 | tcg_gen_andi_tl(reg, reg, 0x1); |
972 | } | |
973 | ||
974 | // !0: FCC0 | FCC1 | |
975 | static inline void gen_op_eval_fbne(TCGv dst, TCGv src, | |
976 | unsigned int fcc_offset) | |
977 | { | |
19f329ad | 978 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
979 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
980 | tcg_gen_or_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
981 | } |
982 | ||
983 | // 1 or 2: FCC0 ^ FCC1 | |
984 | static inline void gen_op_eval_fblg(TCGv dst, TCGv src, | |
985 | unsigned int fcc_offset) | |
986 | { | |
19f329ad | 987 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
988 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
989 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
990 | } |
991 | ||
992 | // 1 or 3: FCC0 | |
993 | static inline void gen_op_eval_fbul(TCGv dst, TCGv src, | |
994 | unsigned int fcc_offset) | |
995 | { | |
996 | gen_mov_reg_FCC0(dst, src, fcc_offset); | |
997 | } | |
998 | ||
999 | // 1: FCC0 & !FCC1 | |
1000 | static inline void gen_op_eval_fbl(TCGv dst, TCGv src, | |
1001 | unsigned int fcc_offset) | |
1002 | { | |
19f329ad | 1003 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1004 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1005 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1); | |
1006 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1007 | } |
1008 | ||
1009 | // 2 or 3: FCC1 | |
1010 | static inline void gen_op_eval_fbug(TCGv dst, TCGv src, | |
1011 | unsigned int fcc_offset) | |
1012 | { | |
1013 | gen_mov_reg_FCC1(dst, src, fcc_offset); | |
1014 | } | |
1015 | ||
1016 | // 2: !FCC0 & FCC1 | |
1017 | static inline void gen_op_eval_fbg(TCGv dst, TCGv src, | |
1018 | unsigned int fcc_offset) | |
1019 | { | |
19f329ad BS |
1020 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1021 | tcg_gen_xori_tl(dst, dst, 0x1); | |
0425bee5 BS |
1022 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1023 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1024 | } |
1025 | ||
1026 | // 3: FCC0 & FCC1 | |
1027 | static inline void gen_op_eval_fbu(TCGv dst, TCGv src, | |
1028 | unsigned int fcc_offset) | |
1029 | { | |
19f329ad | 1030 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1031 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1032 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1033 | } |
1034 | ||
1035 | // 0: !(FCC0 | FCC1) | |
1036 | static inline void gen_op_eval_fbe(TCGv dst, TCGv src, | |
1037 | unsigned int fcc_offset) | |
1038 | { | |
19f329ad | 1039 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1040 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1041 | tcg_gen_or_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1042 | tcg_gen_xori_tl(dst, dst, 0x1); |
1043 | } | |
1044 | ||
1045 | // 0 or 3: !(FCC0 ^ FCC1) | |
1046 | static inline void gen_op_eval_fbue(TCGv dst, TCGv src, | |
1047 | unsigned int fcc_offset) | |
1048 | { | |
19f329ad | 1049 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1050 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1051 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1052 | tcg_gen_xori_tl(dst, dst, 0x1); |
1053 | } | |
1054 | ||
1055 | // 0 or 2: !FCC0 | |
1056 | static inline void gen_op_eval_fbge(TCGv dst, TCGv src, | |
1057 | unsigned int fcc_offset) | |
1058 | { | |
1059 | gen_mov_reg_FCC0(dst, src, fcc_offset); | |
1060 | tcg_gen_xori_tl(dst, dst, 0x1); | |
1061 | } | |
1062 | ||
1063 | // !1: !(FCC0 & !FCC1) | |
1064 | static inline void gen_op_eval_fbuge(TCGv dst, TCGv src, | |
1065 | unsigned int fcc_offset) | |
1066 | { | |
19f329ad | 1067 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1068 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1069 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1); | |
1070 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1071 | tcg_gen_xori_tl(dst, dst, 0x1); |
1072 | } | |
1073 | ||
1074 | // 0 or 1: !FCC1 | |
1075 | static inline void gen_op_eval_fble(TCGv dst, TCGv src, | |
1076 | unsigned int fcc_offset) | |
1077 | { | |
1078 | gen_mov_reg_FCC1(dst, src, fcc_offset); | |
1079 | tcg_gen_xori_tl(dst, dst, 0x1); | |
1080 | } | |
1081 | ||
1082 | // !2: !(!FCC0 & FCC1) | |
1083 | static inline void gen_op_eval_fbule(TCGv dst, TCGv src, | |
1084 | unsigned int fcc_offset) | |
1085 | { | |
19f329ad BS |
1086 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1087 | tcg_gen_xori_tl(dst, dst, 0x1); | |
0425bee5 BS |
1088 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1089 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1090 | tcg_gen_xori_tl(dst, dst, 0x1); |
1091 | } | |
1092 | ||
1093 | // !3: !(FCC0 & FCC1) | |
1094 | static inline void gen_op_eval_fbo(TCGv dst, TCGv src, | |
1095 | unsigned int fcc_offset) | |
1096 | { | |
19f329ad | 1097 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
0425bee5 BS |
1098 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1099 | tcg_gen_and_tl(dst, dst, cpu_tmp0); | |
19f329ad BS |
1100 | tcg_gen_xori_tl(dst, dst, 0x1); |
1101 | } | |
1102 | ||
46525e1f | 1103 | static inline void gen_branch2(DisasContext *dc, target_ulong pc1, |
19f329ad | 1104 | target_ulong pc2, TCGv r_cond) |
83469015 FB |
1105 | { |
1106 | int l1; | |
1107 | ||
1108 | l1 = gen_new_label(); | |
1109 | ||
cb63669a | 1110 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1); |
83469015 | 1111 | |
6e256c93 | 1112 | gen_goto_tb(dc, 0, pc1, pc1 + 4); |
83469015 FB |
1113 | |
1114 | gen_set_label(l1); | |
6e256c93 | 1115 | gen_goto_tb(dc, 1, pc2, pc2 + 4); |
83469015 FB |
1116 | } |
1117 | ||
46525e1f | 1118 | static inline void gen_branch_a(DisasContext *dc, target_ulong pc1, |
19f329ad | 1119 | target_ulong pc2, TCGv r_cond) |
83469015 FB |
1120 | { |
1121 | int l1; | |
1122 | ||
1123 | l1 = gen_new_label(); | |
1124 | ||
cb63669a | 1125 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1); |
83469015 | 1126 | |
6e256c93 | 1127 | gen_goto_tb(dc, 0, pc2, pc1); |
83469015 FB |
1128 | |
1129 | gen_set_label(l1); | |
6e256c93 | 1130 | gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8); |
83469015 FB |
1131 | } |
1132 | ||
19f329ad BS |
1133 | static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2, |
1134 | TCGv r_cond) | |
83469015 FB |
1135 | { |
1136 | int l1, l2; | |
1137 | ||
1138 | l1 = gen_new_label(); | |
1139 | l2 = gen_new_label(); | |
19f329ad | 1140 | |
cb63669a | 1141 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1); |
83469015 | 1142 | |
2f5680ee | 1143 | tcg_gen_movi_tl(cpu_npc, npc1); |
06b3e1b3 | 1144 | tcg_gen_br(l2); |
83469015 FB |
1145 | |
1146 | gen_set_label(l1); | |
2f5680ee | 1147 | tcg_gen_movi_tl(cpu_npc, npc2); |
83469015 FB |
1148 | gen_set_label(l2); |
1149 | } | |
1150 | ||
4af984a7 BS |
1151 | /* call this function before using the condition register as it may |
1152 | have been set for a jump */ | |
1153 | static inline void flush_cond(DisasContext *dc, TCGv cond) | |
83469015 FB |
1154 | { |
1155 | if (dc->npc == JUMP_PC) { | |
4af984a7 | 1156 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
83469015 FB |
1157 | dc->npc = DYNAMIC_PC; |
1158 | } | |
1159 | } | |
1160 | ||
4af984a7 | 1161 | static inline void save_npc(DisasContext *dc, TCGv cond) |
72cbca10 FB |
1162 | { |
1163 | if (dc->npc == JUMP_PC) { | |
4af984a7 | 1164 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
72cbca10 FB |
1165 | dc->npc = DYNAMIC_PC; |
1166 | } else if (dc->npc != DYNAMIC_PC) { | |
2f5680ee | 1167 | tcg_gen_movi_tl(cpu_npc, dc->npc); |
72cbca10 FB |
1168 | } |
1169 | } | |
1170 | ||
4af984a7 | 1171 | static inline void save_state(DisasContext *dc, TCGv cond) |
72cbca10 | 1172 | { |
2f5680ee | 1173 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
4af984a7 | 1174 | save_npc(dc, cond); |
72cbca10 FB |
1175 | } |
1176 | ||
4af984a7 | 1177 | static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond) |
0bee699e FB |
1178 | { |
1179 | if (dc->npc == JUMP_PC) { | |
4af984a7 | 1180 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
48d5c82b | 1181 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
0bee699e FB |
1182 | dc->pc = DYNAMIC_PC; |
1183 | } else if (dc->npc == DYNAMIC_PC) { | |
48d5c82b | 1184 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
0bee699e FB |
1185 | dc->pc = DYNAMIC_PC; |
1186 | } else { | |
1187 | dc->pc = dc->npc; | |
1188 | } | |
1189 | } | |
1190 | ||
38bc628b BS |
1191 | static inline void gen_op_next_insn(void) |
1192 | { | |
48d5c82b BS |
1193 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1194 | tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); | |
38bc628b BS |
1195 | } |
1196 | ||
19f329ad BS |
1197 | static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond) |
1198 | { | |
1199 | TCGv r_src; | |
3475187d | 1200 | |
3475187d | 1201 | #ifdef TARGET_SPARC64 |
19f329ad | 1202 | if (cc) |
dc99a3f2 | 1203 | r_src = cpu_xcc; |
19f329ad | 1204 | else |
dc99a3f2 | 1205 | r_src = cpu_psr; |
3475187d | 1206 | #else |
dc99a3f2 | 1207 | r_src = cpu_psr; |
3475187d | 1208 | #endif |
19f329ad BS |
1209 | switch (cond) { |
1210 | case 0x0: | |
1211 | gen_op_eval_bn(r_dst); | |
1212 | break; | |
1213 | case 0x1: | |
1214 | gen_op_eval_be(r_dst, r_src); | |
1215 | break; | |
1216 | case 0x2: | |
1217 | gen_op_eval_ble(r_dst, r_src); | |
1218 | break; | |
1219 | case 0x3: | |
1220 | gen_op_eval_bl(r_dst, r_src); | |
1221 | break; | |
1222 | case 0x4: | |
1223 | gen_op_eval_bleu(r_dst, r_src); | |
1224 | break; | |
1225 | case 0x5: | |
1226 | gen_op_eval_bcs(r_dst, r_src); | |
1227 | break; | |
1228 | case 0x6: | |
1229 | gen_op_eval_bneg(r_dst, r_src); | |
1230 | break; | |
1231 | case 0x7: | |
1232 | gen_op_eval_bvs(r_dst, r_src); | |
1233 | break; | |
1234 | case 0x8: | |
1235 | gen_op_eval_ba(r_dst); | |
1236 | break; | |
1237 | case 0x9: | |
1238 | gen_op_eval_bne(r_dst, r_src); | |
1239 | break; | |
1240 | case 0xa: | |
1241 | gen_op_eval_bg(r_dst, r_src); | |
1242 | break; | |
1243 | case 0xb: | |
1244 | gen_op_eval_bge(r_dst, r_src); | |
1245 | break; | |
1246 | case 0xc: | |
1247 | gen_op_eval_bgu(r_dst, r_src); | |
1248 | break; | |
1249 | case 0xd: | |
1250 | gen_op_eval_bcc(r_dst, r_src); | |
1251 | break; | |
1252 | case 0xe: | |
1253 | gen_op_eval_bpos(r_dst, r_src); | |
1254 | break; | |
1255 | case 0xf: | |
1256 | gen_op_eval_bvc(r_dst, r_src); | |
1257 | break; | |
1258 | } | |
1259 | } | |
7a3f1944 | 1260 | |
19f329ad | 1261 | static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) |
e8af50a3 | 1262 | { |
19f329ad BS |
1263 | unsigned int offset; |
1264 | ||
19f329ad BS |
1265 | switch (cc) { |
1266 | default: | |
1267 | case 0x0: | |
1268 | offset = 0; | |
1269 | break; | |
1270 | case 0x1: | |
1271 | offset = 32 - 10; | |
1272 | break; | |
1273 | case 0x2: | |
1274 | offset = 34 - 10; | |
1275 | break; | |
1276 | case 0x3: | |
1277 | offset = 36 - 10; | |
1278 | break; | |
1279 | } | |
1280 | ||
1281 | switch (cond) { | |
1282 | case 0x0: | |
1283 | gen_op_eval_bn(r_dst); | |
1284 | break; | |
1285 | case 0x1: | |
87e92502 | 1286 | gen_op_eval_fbne(r_dst, cpu_fsr, offset); |
19f329ad BS |
1287 | break; |
1288 | case 0x2: | |
87e92502 | 1289 | gen_op_eval_fblg(r_dst, cpu_fsr, offset); |
19f329ad BS |
1290 | break; |
1291 | case 0x3: | |
87e92502 | 1292 | gen_op_eval_fbul(r_dst, cpu_fsr, offset); |
19f329ad BS |
1293 | break; |
1294 | case 0x4: | |
87e92502 | 1295 | gen_op_eval_fbl(r_dst, cpu_fsr, offset); |
19f329ad BS |
1296 | break; |
1297 | case 0x5: | |
87e92502 | 1298 | gen_op_eval_fbug(r_dst, cpu_fsr, offset); |
19f329ad BS |
1299 | break; |
1300 | case 0x6: | |
87e92502 | 1301 | gen_op_eval_fbg(r_dst, cpu_fsr, offset); |
19f329ad BS |
1302 | break; |
1303 | case 0x7: | |
87e92502 | 1304 | gen_op_eval_fbu(r_dst, cpu_fsr, offset); |
19f329ad BS |
1305 | break; |
1306 | case 0x8: | |
1307 | gen_op_eval_ba(r_dst); | |
1308 | break; | |
1309 | case 0x9: | |
87e92502 | 1310 | gen_op_eval_fbe(r_dst, cpu_fsr, offset); |
19f329ad BS |
1311 | break; |
1312 | case 0xa: | |
87e92502 | 1313 | gen_op_eval_fbue(r_dst, cpu_fsr, offset); |
19f329ad BS |
1314 | break; |
1315 | case 0xb: | |
87e92502 | 1316 | gen_op_eval_fbge(r_dst, cpu_fsr, offset); |
19f329ad BS |
1317 | break; |
1318 | case 0xc: | |
87e92502 | 1319 | gen_op_eval_fbuge(r_dst, cpu_fsr, offset); |
19f329ad BS |
1320 | break; |
1321 | case 0xd: | |
87e92502 | 1322 | gen_op_eval_fble(r_dst, cpu_fsr, offset); |
19f329ad BS |
1323 | break; |
1324 | case 0xe: | |
87e92502 | 1325 | gen_op_eval_fbule(r_dst, cpu_fsr, offset); |
19f329ad BS |
1326 | break; |
1327 | case 0xf: | |
87e92502 | 1328 | gen_op_eval_fbo(r_dst, cpu_fsr, offset); |
19f329ad BS |
1329 | break; |
1330 | } | |
e8af50a3 | 1331 | } |
00f219bf | 1332 | |
19f329ad | 1333 | #ifdef TARGET_SPARC64 |
00f219bf BS |
1334 | // Inverted logic |
1335 | static const int gen_tcg_cond_reg[8] = { | |
1336 | -1, | |
1337 | TCG_COND_NE, | |
1338 | TCG_COND_GT, | |
1339 | TCG_COND_GE, | |
1340 | -1, | |
1341 | TCG_COND_EQ, | |
1342 | TCG_COND_LE, | |
1343 | TCG_COND_LT, | |
1344 | }; | |
19f329ad | 1345 | |
4af984a7 | 1346 | static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src) |
19f329ad | 1347 | { |
19f329ad BS |
1348 | int l1; |
1349 | ||
1350 | l1 = gen_new_label(); | |
0425bee5 | 1351 | tcg_gen_movi_tl(r_dst, 0); |
cb63669a | 1352 | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1); |
19f329ad BS |
1353 | tcg_gen_movi_tl(r_dst, 1); |
1354 | gen_set_label(l1); | |
1355 | } | |
3475187d | 1356 | #endif |
cf495bcf | 1357 | |
0bee699e | 1358 | /* XXX: potentially incorrect if dynamic npc */ |
4af984a7 BS |
1359 | static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc, |
1360 | TCGv r_cond) | |
7a3f1944 | 1361 | { |
cf495bcf | 1362 | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
af7bf89b | 1363 | target_ulong target = dc->pc + offset; |
5fafdf24 | 1364 | |
cf495bcf | 1365 | if (cond == 0x0) { |
0f8a249a BS |
1366 | /* unconditional not taken */ |
1367 | if (a) { | |
1368 | dc->pc = dc->npc + 4; | |
1369 | dc->npc = dc->pc + 4; | |
1370 | } else { | |
1371 | dc->pc = dc->npc; | |
1372 | dc->npc = dc->pc + 4; | |
1373 | } | |
cf495bcf | 1374 | } else if (cond == 0x8) { |
0f8a249a BS |
1375 | /* unconditional taken */ |
1376 | if (a) { | |
1377 | dc->pc = target; | |
1378 | dc->npc = dc->pc + 4; | |
1379 | } else { | |
1380 | dc->pc = dc->npc; | |
1381 | dc->npc = target; | |
1382 | } | |
cf495bcf | 1383 | } else { |
4af984a7 BS |
1384 | flush_cond(dc, r_cond); |
1385 | gen_cond(r_cond, cc, cond); | |
0f8a249a | 1386 | if (a) { |
4af984a7 | 1387 | gen_branch_a(dc, target, dc->npc, r_cond); |
cf495bcf | 1388 | dc->is_br = 1; |
0f8a249a | 1389 | } else { |
cf495bcf | 1390 | dc->pc = dc->npc; |
72cbca10 FB |
1391 | dc->jump_pc[0] = target; |
1392 | dc->jump_pc[1] = dc->npc + 4; | |
1393 | dc->npc = JUMP_PC; | |
0f8a249a | 1394 | } |
cf495bcf | 1395 | } |
7a3f1944 FB |
1396 | } |
1397 | ||
0bee699e | 1398 | /* XXX: potentially incorrect if dynamic npc */ |
4af984a7 BS |
1399 | static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc, |
1400 | TCGv r_cond) | |
e8af50a3 FB |
1401 | { |
1402 | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); | |
af7bf89b FB |
1403 | target_ulong target = dc->pc + offset; |
1404 | ||
e8af50a3 | 1405 | if (cond == 0x0) { |
0f8a249a BS |
1406 | /* unconditional not taken */ |
1407 | if (a) { | |
1408 | dc->pc = dc->npc + 4; | |
1409 | dc->npc = dc->pc + 4; | |
1410 | } else { | |
1411 | dc->pc = dc->npc; | |
1412 | dc->npc = dc->pc + 4; | |
1413 | } | |
e8af50a3 | 1414 | } else if (cond == 0x8) { |
0f8a249a BS |
1415 | /* unconditional taken */ |
1416 | if (a) { | |
1417 | dc->pc = target; | |
1418 | dc->npc = dc->pc + 4; | |
1419 | } else { | |
1420 | dc->pc = dc->npc; | |
1421 | dc->npc = target; | |
1422 | } | |
e8af50a3 | 1423 | } else { |
4af984a7 BS |
1424 | flush_cond(dc, r_cond); |
1425 | gen_fcond(r_cond, cc, cond); | |
0f8a249a | 1426 | if (a) { |
4af984a7 | 1427 | gen_branch_a(dc, target, dc->npc, r_cond); |
e8af50a3 | 1428 | dc->is_br = 1; |
0f8a249a | 1429 | } else { |
e8af50a3 FB |
1430 | dc->pc = dc->npc; |
1431 | dc->jump_pc[0] = target; | |
1432 | dc->jump_pc[1] = dc->npc + 4; | |
1433 | dc->npc = JUMP_PC; | |
0f8a249a | 1434 | } |
e8af50a3 FB |
1435 | } |
1436 | } | |
1437 | ||
3475187d FB |
1438 | #ifdef TARGET_SPARC64 |
1439 | /* XXX: potentially incorrect if dynamic npc */ | |
4af984a7 BS |
1440 | static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn, |
1441 | TCGv r_cond, TCGv r_reg) | |
7a3f1944 | 1442 | { |
3475187d FB |
1443 | unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); |
1444 | target_ulong target = dc->pc + offset; | |
1445 | ||
4af984a7 BS |
1446 | flush_cond(dc, r_cond); |
1447 | gen_cond_reg(r_cond, cond, r_reg); | |
3475187d | 1448 | if (a) { |
4af984a7 | 1449 | gen_branch_a(dc, target, dc->npc, r_cond); |
0f8a249a | 1450 | dc->is_br = 1; |
3475187d | 1451 | } else { |
0f8a249a BS |
1452 | dc->pc = dc->npc; |
1453 | dc->jump_pc[0] = target; | |
1454 | dc->jump_pc[1] = dc->npc + 4; | |
1455 | dc->npc = JUMP_PC; | |
3475187d | 1456 | } |
7a3f1944 FB |
1457 | } |
1458 | ||
3475187d | 1459 | static GenOpFunc * const gen_fcmps[4] = { |
7e8c2b6c BS |
1460 | helper_fcmps, |
1461 | helper_fcmps_fcc1, | |
1462 | helper_fcmps_fcc2, | |
1463 | helper_fcmps_fcc3, | |
3475187d FB |
1464 | }; |
1465 | ||
1466 | static GenOpFunc * const gen_fcmpd[4] = { | |
7e8c2b6c BS |
1467 | helper_fcmpd, |
1468 | helper_fcmpd_fcc1, | |
1469 | helper_fcmpd_fcc2, | |
1470 | helper_fcmpd_fcc3, | |
3475187d | 1471 | }; |
417454b0 | 1472 | |
1f587329 | 1473 | static GenOpFunc * const gen_fcmpq[4] = { |
7e8c2b6c BS |
1474 | helper_fcmpq, |
1475 | helper_fcmpq_fcc1, | |
1476 | helper_fcmpq_fcc2, | |
1477 | helper_fcmpq_fcc3, | |
1f587329 | 1478 | }; |
1f587329 | 1479 | |
417454b0 | 1480 | static GenOpFunc * const gen_fcmpes[4] = { |
7e8c2b6c BS |
1481 | helper_fcmpes, |
1482 | helper_fcmpes_fcc1, | |
1483 | helper_fcmpes_fcc2, | |
1484 | helper_fcmpes_fcc3, | |
417454b0 BS |
1485 | }; |
1486 | ||
1487 | static GenOpFunc * const gen_fcmped[4] = { | |
7e8c2b6c BS |
1488 | helper_fcmped, |
1489 | helper_fcmped_fcc1, | |
1490 | helper_fcmped_fcc2, | |
1491 | helper_fcmped_fcc3, | |
417454b0 BS |
1492 | }; |
1493 | ||
1f587329 | 1494 | static GenOpFunc * const gen_fcmpeq[4] = { |
7e8c2b6c BS |
1495 | helper_fcmpeq, |
1496 | helper_fcmpeq_fcc1, | |
1497 | helper_fcmpeq_fcc2, | |
1498 | helper_fcmpeq_fcc3, | |
1f587329 | 1499 | }; |
7e8c2b6c BS |
1500 | |
1501 | static inline void gen_op_fcmps(int fccno) | |
1502 | { | |
1503 | tcg_gen_helper_0_0(gen_fcmps[fccno]); | |
1504 | } | |
1505 | ||
1506 | static inline void gen_op_fcmpd(int fccno) | |
1507 | { | |
1508 | tcg_gen_helper_0_0(gen_fcmpd[fccno]); | |
1509 | } | |
1510 | ||
7e8c2b6c BS |
1511 | static inline void gen_op_fcmpq(int fccno) |
1512 | { | |
1513 | tcg_gen_helper_0_0(gen_fcmpq[fccno]); | |
1514 | } | |
7e8c2b6c BS |
1515 | |
1516 | static inline void gen_op_fcmpes(int fccno) | |
1517 | { | |
1518 | tcg_gen_helper_0_0(gen_fcmpes[fccno]); | |
1519 | } | |
1520 | ||
1521 | static inline void gen_op_fcmped(int fccno) | |
1522 | { | |
1523 | tcg_gen_helper_0_0(gen_fcmped[fccno]); | |
1524 | } | |
1525 | ||
7e8c2b6c BS |
1526 | static inline void gen_op_fcmpeq(int fccno) |
1527 | { | |
1528 | tcg_gen_helper_0_0(gen_fcmpeq[fccno]); | |
1529 | } | |
7e8c2b6c BS |
1530 | |
1531 | #else | |
1532 | ||
1533 | static inline void gen_op_fcmps(int fccno) | |
1534 | { | |
1535 | tcg_gen_helper_0_0(helper_fcmps); | |
1536 | } | |
1537 | ||
1538 | static inline void gen_op_fcmpd(int fccno) | |
1539 | { | |
1540 | tcg_gen_helper_0_0(helper_fcmpd); | |
1541 | } | |
1542 | ||
7e8c2b6c BS |
1543 | static inline void gen_op_fcmpq(int fccno) |
1544 | { | |
1545 | tcg_gen_helper_0_0(helper_fcmpq); | |
1546 | } | |
7e8c2b6c BS |
1547 | |
1548 | static inline void gen_op_fcmpes(int fccno) | |
1549 | { | |
1550 | tcg_gen_helper_0_0(helper_fcmpes); | |
1551 | } | |
1552 | ||
1553 | static inline void gen_op_fcmped(int fccno) | |
1554 | { | |
1555 | tcg_gen_helper_0_0(helper_fcmped); | |
1556 | } | |
1557 | ||
7e8c2b6c BS |
1558 | static inline void gen_op_fcmpeq(int fccno) |
1559 | { | |
1560 | tcg_gen_helper_0_0(helper_fcmpeq); | |
1561 | } | |
1562 | #endif | |
1563 | ||
134d77a1 BS |
1564 | static inline void gen_op_fpexception_im(int fsr_flags) |
1565 | { | |
87e92502 BS |
1566 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK); |
1567 | tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); | |
2f5680ee | 1568 | tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_FP_EXCP)); |
134d77a1 BS |
1569 | } |
1570 | ||
4af984a7 | 1571 | static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond) |
a80dde08 FB |
1572 | { |
1573 | #if !defined(CONFIG_USER_ONLY) | |
1574 | if (!dc->fpu_enabled) { | |
4af984a7 | 1575 | save_state(dc, r_cond); |
2f5680ee | 1576 | tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NFPU_INSN)); |
a80dde08 FB |
1577 | dc->is_br = 1; |
1578 | return 1; | |
1579 | } | |
1580 | #endif | |
1581 | return 0; | |
1582 | } | |
1583 | ||
7e8c2b6c BS |
1584 | static inline void gen_op_clear_ieee_excp_and_FTT(void) |
1585 | { | |
87e92502 | 1586 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK)); |
7e8c2b6c BS |
1587 | } |
1588 | ||
1589 | static inline void gen_clear_float_exceptions(void) | |
1590 | { | |
1591 | tcg_gen_helper_0_0(helper_clear_float_exceptions); | |
1592 | } | |
1593 | ||
1a2fb1c0 BS |
1594 | /* asi moves */ |
1595 | #ifdef TARGET_SPARC64 | |
0425bee5 | 1596 | static inline TCGv gen_get_asi(int insn, TCGv r_addr) |
1a2fb1c0 BS |
1597 | { |
1598 | int asi, offset; | |
0425bee5 | 1599 | TCGv r_asi; |
1a2fb1c0 | 1600 | |
1a2fb1c0 | 1601 | if (IS_IMM) { |
0425bee5 | 1602 | r_asi = tcg_temp_new(TCG_TYPE_I32); |
1a2fb1c0 | 1603 | offset = GET_FIELD(insn, 25, 31); |
0425bee5 BS |
1604 | tcg_gen_addi_tl(r_addr, r_addr, offset); |
1605 | tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi)); | |
1a2fb1c0 BS |
1606 | } else { |
1607 | asi = GET_FIELD(insn, 19, 26); | |
0425bee5 | 1608 | r_asi = tcg_const_i32(asi); |
1a2fb1c0 | 1609 | } |
0425bee5 BS |
1610 | return r_asi; |
1611 | } | |
1612 | ||
77f193da BS |
1613 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
1614 | int sign) | |
0425bee5 BS |
1615 | { |
1616 | TCGv r_asi; | |
1617 | ||
4af984a7 BS |
1618 | r_asi = gen_get_asi(insn, addr); |
1619 | tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, | |
0425bee5 | 1620 | tcg_const_i32(size), tcg_const_i32(sign)); |
1a2fb1c0 BS |
1621 | } |
1622 | ||
4af984a7 | 1623 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
1a2fb1c0 | 1624 | { |
0425bee5 | 1625 | TCGv r_asi; |
1a2fb1c0 | 1626 | |
4af984a7 BS |
1627 | r_asi = gen_get_asi(insn, addr); |
1628 | tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, tcg_const_i32(size)); | |
1a2fb1c0 BS |
1629 | } |
1630 | ||
4af984a7 | 1631 | static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd) |
1a2fb1c0 | 1632 | { |
0425bee5 | 1633 | TCGv r_asi; |
1a2fb1c0 | 1634 | |
4af984a7 BS |
1635 | r_asi = gen_get_asi(insn, addr); |
1636 | tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, tcg_const_i32(size), | |
0425bee5 | 1637 | tcg_const_i32(rd)); |
1a2fb1c0 BS |
1638 | } |
1639 | ||
4af984a7 | 1640 | static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd) |
1a2fb1c0 | 1641 | { |
0425bee5 | 1642 | TCGv r_asi; |
1a2fb1c0 | 1643 | |
31741a27 BS |
1644 | r_asi = gen_get_asi(insn, addr); |
1645 | tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, tcg_const_i32(size), | |
0425bee5 | 1646 | tcg_const_i32(rd)); |
1a2fb1c0 BS |
1647 | } |
1648 | ||
4af984a7 | 1649 | static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
1a2fb1c0 | 1650 | { |
0425bee5 | 1651 | TCGv r_temp, r_asi; |
1a2fb1c0 | 1652 | |
1a2fb1c0 | 1653 | r_temp = tcg_temp_new(TCG_TYPE_I32); |
4af984a7 BS |
1654 | r_asi = gen_get_asi(insn, addr); |
1655 | tcg_gen_helper_1_4(helper_ld_asi, r_temp, addr, r_asi, | |
0425bee5 | 1656 | tcg_const_i32(4), tcg_const_i32(0)); |
4af984a7 | 1657 | tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, |
0425bee5 | 1658 | tcg_const_i32(4)); |
4af984a7 | 1659 | tcg_gen_extu_i32_tl(dst, r_temp); |
1a2fb1c0 BS |
1660 | } |
1661 | ||
4af984a7 | 1662 | static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn) |
1a2fb1c0 | 1663 | { |
8911f501 | 1664 | TCGv r_asi; |
1a2fb1c0 | 1665 | |
4af984a7 BS |
1666 | r_asi = gen_get_asi(insn, addr); |
1667 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, | |
0425bee5 | 1668 | tcg_const_i32(8), tcg_const_i32(0)); |
4af984a7 | 1669 | tcg_gen_andi_i64(lo, cpu_tmp64, 0xffffffffULL); |
8911f501 | 1670 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32); |
4af984a7 | 1671 | tcg_gen_andi_i64(hi, cpu_tmp64, 0xffffffffULL); |
0425bee5 BS |
1672 | } |
1673 | ||
4af984a7 | 1674 | static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
0425bee5 | 1675 | { |
8911f501 | 1676 | TCGv r_temp, r_asi; |
0425bee5 | 1677 | |
0425bee5 BS |
1678 | r_temp = tcg_temp_new(TCG_TYPE_I32); |
1679 | gen_movl_reg_TN(rd + 1, r_temp); | |
4af984a7 | 1680 | tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, |
0425bee5 | 1681 | r_temp); |
4af984a7 BS |
1682 | r_asi = gen_get_asi(insn, addr); |
1683 | tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, | |
0425bee5 | 1684 | tcg_const_i32(8)); |
1a2fb1c0 BS |
1685 | } |
1686 | ||
77f193da BS |
1687 | static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
1688 | int rd) | |
1a2fb1c0 | 1689 | { |
1a2fb1c0 BS |
1690 | TCGv r_val1, r_asi; |
1691 | ||
ef28fd86 | 1692 | r_val1 = tcg_temp_new(TCG_TYPE_TL); |
1a2fb1c0 | 1693 | gen_movl_reg_TN(rd, r_val1); |
4af984a7 BS |
1694 | r_asi = gen_get_asi(insn, addr); |
1695 | tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi); | |
1a2fb1c0 BS |
1696 | } |
1697 | ||
77f193da BS |
1698 | static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
1699 | int rd) | |
1a2fb1c0 | 1700 | { |
8911f501 | 1701 | TCGv r_asi; |
1a2fb1c0 | 1702 | |
8911f501 | 1703 | gen_movl_reg_TN(rd, cpu_tmp64); |
4af984a7 BS |
1704 | r_asi = gen_get_asi(insn, addr); |
1705 | tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi); | |
1a2fb1c0 BS |
1706 | } |
1707 | ||
1708 | #elif !defined(CONFIG_USER_ONLY) | |
1709 | ||
77f193da BS |
1710 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
1711 | int sign) | |
1a2fb1c0 BS |
1712 | { |
1713 | int asi; | |
1a2fb1c0 | 1714 | |
1a2fb1c0 | 1715 | asi = GET_FIELD(insn, 19, 26); |
4af984a7 | 1716 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi), |
0425bee5 | 1717 | tcg_const_i32(size), tcg_const_i32(sign)); |
4af984a7 | 1718 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1a2fb1c0 BS |
1719 | } |
1720 | ||
4af984a7 | 1721 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
1a2fb1c0 BS |
1722 | { |
1723 | int asi; | |
1a2fb1c0 | 1724 | |
4af984a7 | 1725 | tcg_gen_extu_tl_i64(cpu_tmp64, src); |
1a2fb1c0 | 1726 | asi = GET_FIELD(insn, 19, 26); |
4af984a7 | 1727 | tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi), |
0425bee5 | 1728 | tcg_const_i32(size)); |
1a2fb1c0 BS |
1729 | } |
1730 | ||
4af984a7 | 1731 | static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
1a2fb1c0 BS |
1732 | { |
1733 | int asi; | |
0425bee5 | 1734 | TCGv r_temp; |
1a2fb1c0 | 1735 | |
1a2fb1c0 | 1736 | r_temp = tcg_temp_new(TCG_TYPE_I32); |
1a2fb1c0 | 1737 | asi = GET_FIELD(insn, 19, 26); |
4af984a7 | 1738 | tcg_gen_helper_1_4(helper_ld_asi, r_temp, addr, tcg_const_i32(asi), |
0425bee5 | 1739 | tcg_const_i32(4), tcg_const_i32(0)); |
4af984a7 | 1740 | tcg_gen_helper_0_4(helper_st_asi, addr, dst, tcg_const_i32(asi), |
0425bee5 | 1741 | tcg_const_i32(4)); |
4af984a7 | 1742 | tcg_gen_extu_i32_tl(dst, r_temp); |
1a2fb1c0 BS |
1743 | } |
1744 | ||
4af984a7 | 1745 | static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn) |
1a2fb1c0 BS |
1746 | { |
1747 | int asi; | |
1a2fb1c0 | 1748 | |
1a2fb1c0 | 1749 | asi = GET_FIELD(insn, 19, 26); |
4af984a7 | 1750 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi), |
0425bee5 | 1751 | tcg_const_i32(8), tcg_const_i32(0)); |
4af984a7 | 1752 | tcg_gen_trunc_i64_tl(lo, cpu_tmp64); |
8911f501 | 1753 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32); |
4af984a7 | 1754 | tcg_gen_trunc_i64_tl(hi, cpu_tmp64); |
0425bee5 BS |
1755 | } |
1756 | ||
4af984a7 | 1757 | static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
0425bee5 BS |
1758 | { |
1759 | int asi; | |
8911f501 | 1760 | TCGv r_temp; |
0425bee5 | 1761 | |
0425bee5 BS |
1762 | r_temp = tcg_temp_new(TCG_TYPE_I32); |
1763 | gen_movl_reg_TN(rd + 1, r_temp); | |
4af984a7 | 1764 | tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp); |
0425bee5 | 1765 | asi = GET_FIELD(insn, 19, 26); |
4af984a7 | 1766 | tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi), |
0425bee5 | 1767 | tcg_const_i32(8)); |
1a2fb1c0 BS |
1768 | } |
1769 | #endif | |
1770 | ||
1771 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) | |
4af984a7 | 1772 | static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn) |
1a2fb1c0 BS |
1773 | { |
1774 | int asi; | |
1a2fb1c0 | 1775 | |
4af984a7 | 1776 | gen_ld_asi(dst, addr, insn, 1, 0); |
1a2fb1c0 | 1777 | |
1a2fb1c0 | 1778 | asi = GET_FIELD(insn, 19, 26); |
4af984a7 | 1779 | tcg_gen_helper_0_4(helper_st_asi, addr, tcg_const_i64(0xffULL), |
0425bee5 | 1780 | tcg_const_i32(asi), tcg_const_i32(1)); |
1a2fb1c0 BS |
1781 | } |
1782 | #endif | |
1783 | ||
9322a4bf BS |
1784 | static inline TCGv get_src1(unsigned int insn, TCGv def) |
1785 | { | |
1786 | TCGv r_rs1 = def; | |
1787 | unsigned int rs1; | |
1788 | ||
1789 | rs1 = GET_FIELD(insn, 13, 17); | |
1790 | if (rs1 == 0) | |
1791 | //r_rs1 = tcg_const_tl(0); | |
1792 | tcg_gen_movi_tl(def, 0); | |
1793 | else if (rs1 < 8) | |
1794 | //r_rs1 = cpu_gregs[rs1]; | |
1795 | tcg_gen_mov_tl(def, cpu_gregs[rs1]); | |
1796 | else | |
1797 | tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong)); | |
1798 | return r_rs1; | |
1799 | } | |
1800 | ||
a49d9390 BS |
1801 | static inline TCGv get_src2(unsigned int insn, TCGv def) |
1802 | { | |
1803 | TCGv r_rs2 = def; | |
1804 | unsigned int rs2; | |
1805 | ||
1806 | if (IS_IMM) { /* immediate */ | |
1807 | rs2 = GET_FIELDs(insn, 19, 31); | |
1808 | r_rs2 = tcg_const_tl((int)rs2); | |
1809 | } else { /* register */ | |
1810 | rs2 = GET_FIELD(insn, 27, 31); | |
1811 | if (rs2 == 0) | |
1812 | r_rs2 = tcg_const_tl(0); | |
1813 | else if (rs2 < 8) | |
1814 | r_rs2 = cpu_gregs[rs2]; | |
1815 | else | |
1816 | tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong)); | |
1817 | } | |
1818 | return r_rs2; | |
1819 | } | |
1820 | ||
64a88d5d BS |
1821 | #define CHECK_IU_FEATURE(dc, FEATURE) \ |
1822 | if (!((dc)->features & CPU_FEATURE_ ## FEATURE)) \ | |
1823 | goto illegal_insn; | |
1824 | #define CHECK_FPU_FEATURE(dc, FEATURE) \ | |
1825 | if (!((dc)->features & CPU_FEATURE_ ## FEATURE)) \ | |
1826 | goto nfpu_insn; | |
1827 | ||
0bee699e | 1828 | /* before an instruction, dc->pc must be static */ |
cf495bcf FB |
1829 | static void disas_sparc_insn(DisasContext * dc) |
1830 | { | |
1831 | unsigned int insn, opc, rs1, rs2, rd; | |
7a3f1944 | 1832 | |
a8c768c0 BS |
1833 | if (unlikely(loglevel & CPU_LOG_TB_OP)) |
1834 | tcg_gen_debug_insn_start(dc->pc); | |
0fa85d43 | 1835 | insn = ldl_code(dc->pc); |
cf495bcf | 1836 | opc = GET_FIELD(insn, 0, 1); |
7a3f1944 | 1837 | |
cf495bcf | 1838 | rd = GET_FIELD(insn, 2, 6); |
6ae20372 BS |
1839 | |
1840 | cpu_dst = cpu_T[0]; | |
1841 | cpu_src1 = cpu_T[0]; // const | |
1842 | cpu_src2 = cpu_T[1]; // const | |
1843 | ||
1844 | // loads and stores | |
1845 | cpu_addr = cpu_T[0]; | |
1846 | cpu_val = cpu_T[1]; | |
1847 | ||
cf495bcf | 1848 | switch (opc) { |
0f8a249a BS |
1849 | case 0: /* branches/sethi */ |
1850 | { | |
1851 | unsigned int xop = GET_FIELD(insn, 7, 9); | |
1852 | int32_t target; | |
1853 | switch (xop) { | |
3475187d | 1854 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
1855 | case 0x1: /* V9 BPcc */ |
1856 | { | |
1857 | int cc; | |
1858 | ||
1859 | target = GET_FIELD_SP(insn, 0, 18); | |
1860 | target = sign_extend(target, 18); | |
1861 | target <<= 2; | |
1862 | cc = GET_FIELD_SP(insn, 20, 21); | |
1863 | if (cc == 0) | |
6ae20372 | 1864 | do_branch(dc, target, insn, 0, cpu_cond); |
0f8a249a | 1865 | else if (cc == 2) |
6ae20372 | 1866 | do_branch(dc, target, insn, 1, cpu_cond); |
0f8a249a BS |
1867 | else |
1868 | goto illegal_insn; | |
1869 | goto jmp_insn; | |
1870 | } | |
1871 | case 0x3: /* V9 BPr */ | |
1872 | { | |
1873 | target = GET_FIELD_SP(insn, 0, 13) | | |
13846e70 | 1874 | (GET_FIELD_SP(insn, 20, 21) << 14); |
0f8a249a BS |
1875 | target = sign_extend(target, 16); |
1876 | target <<= 2; | |
9322a4bf | 1877 | cpu_src1 = get_src1(insn, cpu_src1); |
6ae20372 | 1878 | do_branch_reg(dc, target, insn, cpu_cond, cpu_src1); |
0f8a249a BS |
1879 | goto jmp_insn; |
1880 | } | |
1881 | case 0x5: /* V9 FBPcc */ | |
1882 | { | |
1883 | int cc = GET_FIELD_SP(insn, 20, 21); | |
6ae20372 | 1884 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
a80dde08 | 1885 | goto jmp_insn; |
0f8a249a BS |
1886 | target = GET_FIELD_SP(insn, 0, 18); |
1887 | target = sign_extend(target, 19); | |
1888 | target <<= 2; | |
6ae20372 | 1889 | do_fbranch(dc, target, insn, cc, cpu_cond); |
0f8a249a BS |
1890 | goto jmp_insn; |
1891 | } | |
a4d17f19 | 1892 | #else |
0f8a249a BS |
1893 | case 0x7: /* CBN+x */ |
1894 | { | |
1895 | goto ncp_insn; | |
1896 | } | |
1897 | #endif | |
1898 | case 0x2: /* BN+x */ | |
1899 | { | |
1900 | target = GET_FIELD(insn, 10, 31); | |
1901 | target = sign_extend(target, 22); | |
1902 | target <<= 2; | |
6ae20372 | 1903 | do_branch(dc, target, insn, 0, cpu_cond); |
0f8a249a BS |
1904 | goto jmp_insn; |
1905 | } | |
1906 | case 0x6: /* FBN+x */ | |
1907 | { | |
6ae20372 | 1908 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
a80dde08 | 1909 | goto jmp_insn; |
0f8a249a BS |
1910 | target = GET_FIELD(insn, 10, 31); |
1911 | target = sign_extend(target, 22); | |
1912 | target <<= 2; | |
6ae20372 | 1913 | do_fbranch(dc, target, insn, 0, cpu_cond); |
0f8a249a BS |
1914 | goto jmp_insn; |
1915 | } | |
1916 | case 0x4: /* SETHI */ | |
0f8a249a | 1917 | if (rd) { // nop |
0f8a249a | 1918 | uint32_t value = GET_FIELD(insn, 10, 31); |
9c6c6662 | 1919 | gen_movl_TN_reg(rd, tcg_const_tl(value << 10)); |
0f8a249a | 1920 | } |
0f8a249a BS |
1921 | break; |
1922 | case 0x0: /* UNIMPL */ | |
1923 | default: | |
3475187d | 1924 | goto illegal_insn; |
0f8a249a BS |
1925 | } |
1926 | break; | |
1927 | } | |
1928 | break; | |
cf495bcf | 1929 | case 1: |
0f8a249a BS |
1930 | /*CALL*/ { |
1931 | target_long target = GET_FIELDs(insn, 2, 31) << 2; | |
cf495bcf | 1932 | |
48d5c82b | 1933 | gen_movl_TN_reg(15, tcg_const_tl(dc->pc)); |
0f8a249a | 1934 | target += dc->pc; |
6ae20372 | 1935 | gen_mov_pc_npc(dc, cpu_cond); |
0f8a249a BS |
1936 | dc->npc = target; |
1937 | } | |
1938 | goto jmp_insn; | |
1939 | case 2: /* FPU & Logical Operations */ | |
1940 | { | |
1941 | unsigned int xop = GET_FIELD(insn, 7, 12); | |
1942 | if (xop == 0x3a) { /* generate trap */ | |
cf495bcf | 1943 | int cond; |
3475187d | 1944 | |
9322a4bf | 1945 | cpu_src1 = get_src1(insn, cpu_src1); |
0f8a249a BS |
1946 | if (IS_IMM) { |
1947 | rs2 = GET_FIELD(insn, 25, 31); | |
6ae20372 | 1948 | tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2); |
cf495bcf FB |
1949 | } else { |
1950 | rs2 = GET_FIELD(insn, 27, 31); | |
0f8a249a | 1951 | if (rs2 != 0) { |
6ae20372 BS |
1952 | gen_movl_reg_TN(rs2, cpu_src2); |
1953 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); | |
6f551262 BS |
1954 | } else |
1955 | tcg_gen_mov_tl(cpu_dst, cpu_src1); | |
cf495bcf | 1956 | } |
cf495bcf FB |
1957 | cond = GET_FIELD(insn, 3, 6); |
1958 | if (cond == 0x8) { | |
6ae20372 BS |
1959 | save_state(dc, cpu_cond); |
1960 | tcg_gen_helper_0_1(helper_trap, cpu_dst); | |
af7bf89b | 1961 | } else if (cond != 0) { |
748b9d8e | 1962 | TCGv r_cond = tcg_temp_new(TCG_TYPE_TL); |
3475187d | 1963 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
1964 | /* V9 icc/xcc */ |
1965 | int cc = GET_FIELD_SP(insn, 11, 12); | |
748b9d8e | 1966 | |
6ae20372 | 1967 | save_state(dc, cpu_cond); |
0f8a249a | 1968 | if (cc == 0) |
748b9d8e | 1969 | gen_cond(r_cond, 0, cond); |
0f8a249a | 1970 | else if (cc == 2) |
748b9d8e | 1971 | gen_cond(r_cond, 1, cond); |
0f8a249a BS |
1972 | else |
1973 | goto illegal_insn; | |
3475187d | 1974 | #else |
6ae20372 | 1975 | save_state(dc, cpu_cond); |
748b9d8e | 1976 | gen_cond(r_cond, 0, cond); |
3475187d | 1977 | #endif |
6ae20372 | 1978 | tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond); |
cf495bcf | 1979 | } |
a80dde08 | 1980 | gen_op_next_insn(); |
57fec1fe | 1981 | tcg_gen_exit_tb(0); |
a80dde08 FB |
1982 | dc->is_br = 1; |
1983 | goto jmp_insn; | |
cf495bcf FB |
1984 | } else if (xop == 0x28) { |
1985 | rs1 = GET_FIELD(insn, 13, 17); | |
1986 | switch(rs1) { | |
1987 | case 0: /* rdy */ | |
65fe7b09 BS |
1988 | #ifndef TARGET_SPARC64 |
1989 | case 0x01 ... 0x0e: /* undefined in the SPARCv8 | |
1990 | manual, rdy on the microSPARC | |
1991 | II */ | |
1992 | case 0x0f: /* stbar in the SPARCv8 manual, | |
1993 | rdy on the microSPARC II */ | |
1994 | case 0x10 ... 0x1f: /* implementation-dependent in the | |
1995 | SPARCv8 manual, rdy on the | |
1996 | microSPARC II */ | |
1997 | #endif | |
77f193da BS |
1998 | tcg_gen_ld_tl(cpu_dst, cpu_env, |
1999 | offsetof(CPUSPARCState, y)); | |
6ae20372 | 2000 | gen_movl_TN_reg(rd, cpu_dst); |
cf495bcf | 2001 | break; |
3475187d | 2002 | #ifdef TARGET_SPARC64 |
0f8a249a | 2003 | case 0x2: /* V9 rdccr */ |
6ae20372 BS |
2004 | tcg_gen_helper_1_0(helper_rdccr, cpu_dst); |
2005 | gen_movl_TN_reg(rd, cpu_dst); | |
3475187d | 2006 | break; |
0f8a249a | 2007 | case 0x3: /* V9 rdasi */ |
77f193da BS |
2008 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2009 | offsetof(CPUSPARCState, asi)); | |
6ae20372 BS |
2010 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
2011 | gen_movl_TN_reg(rd, cpu_dst); | |
3475187d | 2012 | break; |
0f8a249a | 2013 | case 0x4: /* V9 rdtick */ |
ccd4a219 BS |
2014 | { |
2015 | TCGv r_tickptr; | |
2016 | ||
2017 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
2018 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
2019 | offsetof(CPUState, tick)); | |
6ae20372 | 2020 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst, |
ccd4a219 | 2021 | r_tickptr); |
6ae20372 | 2022 | gen_movl_TN_reg(rd, cpu_dst); |
ccd4a219 | 2023 | } |
3475187d | 2024 | break; |
0f8a249a | 2025 | case 0x5: /* V9 rdpc */ |
9c6c6662 | 2026 | gen_movl_TN_reg(rd, tcg_const_tl(dc->pc)); |
0f8a249a BS |
2027 | break; |
2028 | case 0x6: /* V9 rdfprs */ | |
77f193da BS |
2029 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2030 | offsetof(CPUSPARCState, fprs)); | |
6ae20372 BS |
2031 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
2032 | gen_movl_TN_reg(rd, cpu_dst); | |
3475187d | 2033 | break; |
65fe7b09 BS |
2034 | case 0xf: /* V9 membar */ |
2035 | break; /* no effect */ | |
0f8a249a | 2036 | case 0x13: /* Graphics Status */ |
6ae20372 | 2037 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
725cb90b | 2038 | goto jmp_insn; |
77f193da BS |
2039 | tcg_gen_ld_tl(cpu_dst, cpu_env, |
2040 | offsetof(CPUSPARCState, gsr)); | |
6ae20372 | 2041 | gen_movl_TN_reg(rd, cpu_dst); |
725cb90b | 2042 | break; |
0f8a249a | 2043 | case 0x17: /* Tick compare */ |
77f193da BS |
2044 | tcg_gen_ld_tl(cpu_dst, cpu_env, |
2045 | offsetof(CPUSPARCState, tick_cmpr)); | |
6ae20372 | 2046 | gen_movl_TN_reg(rd, cpu_dst); |
83469015 | 2047 | break; |
0f8a249a | 2048 | case 0x18: /* System tick */ |
ccd4a219 BS |
2049 | { |
2050 | TCGv r_tickptr; | |
2051 | ||
2052 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
2053 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
2054 | offsetof(CPUState, stick)); | |
6ae20372 | 2055 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst, |
ccd4a219 | 2056 | r_tickptr); |
6ae20372 | 2057 | gen_movl_TN_reg(rd, cpu_dst); |
ccd4a219 | 2058 | } |
83469015 | 2059 | break; |
0f8a249a | 2060 | case 0x19: /* System tick compare */ |
77f193da BS |
2061 | tcg_gen_ld_tl(cpu_dst, cpu_env, |
2062 | offsetof(CPUSPARCState, stick_cmpr)); | |
6ae20372 | 2063 | gen_movl_TN_reg(rd, cpu_dst); |
83469015 | 2064 | break; |
0f8a249a BS |
2065 | case 0x10: /* Performance Control */ |
2066 | case 0x11: /* Performance Instrumentation Counter */ | |
2067 | case 0x12: /* Dispatch Control */ | |
2068 | case 0x14: /* Softint set, WO */ | |
2069 | case 0x15: /* Softint clear, WO */ | |
2070 | case 0x16: /* Softint write */ | |
3475187d FB |
2071 | #endif |
2072 | default: | |
cf495bcf FB |
2073 | goto illegal_insn; |
2074 | } | |
e8af50a3 | 2075 | #if !defined(CONFIG_USER_ONLY) |
e9ebed4d | 2076 | } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ |
3475187d | 2077 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
2078 | if (!supervisor(dc)) |
2079 | goto priv_insn; | |
6ae20372 | 2080 | tcg_gen_helper_1_0(helper_rdpsr, cpu_dst); |
e9ebed4d BS |
2081 | #else |
2082 | if (!hypervisor(dc)) | |
2083 | goto priv_insn; | |
2084 | rs1 = GET_FIELD(insn, 13, 17); | |
2085 | switch (rs1) { | |
2086 | case 0: // hpstate | |
2087 | // gen_op_rdhpstate(); | |
2088 | break; | |
2089 | case 1: // htstate | |
2090 | // gen_op_rdhtstate(); | |
2091 | break; | |
2092 | case 3: // hintp | |
77f193da BS |
2093 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2094 | offsetof(CPUSPARCState, hintp)); | |
6ae20372 | 2095 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
e9ebed4d BS |
2096 | break; |
2097 | case 5: // htba | |
77f193da BS |
2098 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2099 | offsetof(CPUSPARCState, htba)); | |
6ae20372 | 2100 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
e9ebed4d BS |
2101 | break; |
2102 | case 6: // hver | |
77f193da BS |
2103 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2104 | offsetof(CPUSPARCState, hver)); | |
6ae20372 | 2105 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
e9ebed4d BS |
2106 | break; |
2107 | case 31: // hstick_cmpr | |
6ae20372 | 2108 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
77f193da BS |
2109 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
2110 | offsetof(CPUSPARCState, hstick_cmpr)); | |
e9ebed4d BS |
2111 | break; |
2112 | default: | |
2113 | goto illegal_insn; | |
2114 | } | |
2115 | #endif | |
6ae20372 | 2116 | gen_movl_TN_reg(rd, cpu_dst); |
e8af50a3 | 2117 | break; |
3475187d | 2118 | } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ |
0f8a249a BS |
2119 | if (!supervisor(dc)) |
2120 | goto priv_insn; | |
3475187d FB |
2121 | #ifdef TARGET_SPARC64 |
2122 | rs1 = GET_FIELD(insn, 13, 17); | |
0f8a249a BS |
2123 | switch (rs1) { |
2124 | case 0: // tpc | |
375ee38b BS |
2125 | { |
2126 | TCGv r_tsptr; | |
2127 | ||
2128 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
2129 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
2130 | offsetof(CPUState, tsptr)); | |
6ae20372 | 2131 | tcg_gen_ld_tl(cpu_dst, r_tsptr, |
375ee38b BS |
2132 | offsetof(trap_state, tpc)); |
2133 | } | |
0f8a249a BS |
2134 | break; |
2135 | case 1: // tnpc | |
375ee38b BS |
2136 | { |
2137 | TCGv r_tsptr; | |
2138 | ||
2139 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
2140 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
2141 | offsetof(CPUState, tsptr)); | |
6ae20372 | 2142 | tcg_gen_ld_tl(cpu_dst, r_tsptr, |
375ee38b BS |
2143 | offsetof(trap_state, tnpc)); |
2144 | } | |
0f8a249a BS |
2145 | break; |
2146 | case 2: // tstate | |
375ee38b BS |
2147 | { |
2148 | TCGv r_tsptr; | |
2149 | ||
2150 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
2151 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
2152 | offsetof(CPUState, tsptr)); | |
6ae20372 | 2153 | tcg_gen_ld_tl(cpu_dst, r_tsptr, |
375ee38b BS |
2154 | offsetof(trap_state, tstate)); |
2155 | } | |
0f8a249a BS |
2156 | break; |
2157 | case 3: // tt | |
375ee38b BS |
2158 | { |
2159 | TCGv r_tsptr; | |
2160 | ||
2161 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
2162 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
2163 | offsetof(CPUState, tsptr)); | |
6ae20372 | 2164 | tcg_gen_ld_i32(cpu_dst, r_tsptr, |
375ee38b BS |
2165 | offsetof(trap_state, tt)); |
2166 | } | |
0f8a249a BS |
2167 | break; |
2168 | case 4: // tick | |
ccd4a219 BS |
2169 | { |
2170 | TCGv r_tickptr; | |
2171 | ||
2172 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
2173 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
2174 | offsetof(CPUState, tick)); | |
6ae20372 | 2175 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst, |
ccd4a219 | 2176 | r_tickptr); |
6ae20372 | 2177 | gen_movl_TN_reg(rd, cpu_dst); |
ccd4a219 | 2178 | } |
0f8a249a BS |
2179 | break; |
2180 | case 5: // tba | |
77f193da BS |
2181 | tcg_gen_ld_tl(cpu_dst, cpu_env, |
2182 | offsetof(CPUSPARCState, tbr)); | |
0f8a249a BS |
2183 | break; |
2184 | case 6: // pstate | |
77f193da BS |
2185 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2186 | offsetof(CPUSPARCState, pstate)); | |
6ae20372 | 2187 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
0f8a249a BS |
2188 | break; |
2189 | case 7: // tl | |
77f193da BS |
2190 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2191 | offsetof(CPUSPARCState, tl)); | |
6ae20372 | 2192 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
0f8a249a BS |
2193 | break; |
2194 | case 8: // pil | |
77f193da BS |
2195 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2196 | offsetof(CPUSPARCState, psrpil)); | |
6ae20372 | 2197 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
0f8a249a BS |
2198 | break; |
2199 | case 9: // cwp | |
6ae20372 | 2200 | tcg_gen_helper_1_0(helper_rdcwp, cpu_dst); |
0f8a249a BS |
2201 | break; |
2202 | case 10: // cansave | |
77f193da BS |
2203 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2204 | offsetof(CPUSPARCState, cansave)); | |
6ae20372 | 2205 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
0f8a249a BS |
2206 | break; |
2207 | case 11: // canrestore | |
77f193da BS |
2208 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2209 | offsetof(CPUSPARCState, canrestore)); | |
6ae20372 | 2210 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
0f8a249a BS |
2211 | break; |
2212 | case 12: // cleanwin | |
77f193da BS |
2213 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2214 | offsetof(CPUSPARCState, cleanwin)); | |
6ae20372 | 2215 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
0f8a249a BS |
2216 | break; |
2217 | case 13: // otherwin | |
77f193da BS |
2218 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2219 | offsetof(CPUSPARCState, otherwin)); | |
6ae20372 | 2220 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
0f8a249a BS |
2221 | break; |
2222 | case 14: // wstate | |
77f193da BS |
2223 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2224 | offsetof(CPUSPARCState, wstate)); | |
6ae20372 | 2225 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
0f8a249a | 2226 | break; |
e9ebed4d | 2227 | case 16: // UA2005 gl |
77f193da BS |
2228 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2229 | offsetof(CPUSPARCState, gl)); | |
6ae20372 | 2230 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
e9ebed4d BS |
2231 | break; |
2232 | case 26: // UA2005 strand status | |
2233 | if (!hypervisor(dc)) | |
2234 | goto priv_insn; | |
77f193da BS |
2235 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2236 | offsetof(CPUSPARCState, ssr)); | |
6ae20372 | 2237 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
e9ebed4d | 2238 | break; |
0f8a249a | 2239 | case 31: // ver |
77f193da BS |
2240 | tcg_gen_ld_tl(cpu_dst, cpu_env, |
2241 | offsetof(CPUSPARCState, version)); | |
0f8a249a BS |
2242 | break; |
2243 | case 15: // fq | |
2244 | default: | |
2245 | goto illegal_insn; | |
2246 | } | |
3475187d | 2247 | #else |
77f193da BS |
2248 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2249 | offsetof(CPUSPARCState, wim)); | |
6ae20372 | 2250 | tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
3475187d | 2251 | #endif |
6ae20372 | 2252 | gen_movl_TN_reg(rd, cpu_dst); |
e8af50a3 | 2253 | break; |
3475187d FB |
2254 | } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ |
2255 | #ifdef TARGET_SPARC64 | |
72a9747b | 2256 | tcg_gen_helper_0_0(helper_flushw); |
3475187d | 2257 | #else |
0f8a249a BS |
2258 | if (!supervisor(dc)) |
2259 | goto priv_insn; | |
6ae20372 BS |
2260 | tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr)); |
2261 | gen_movl_TN_reg(rd, cpu_dst); | |
3475187d | 2262 | #endif |
e8af50a3 FB |
2263 | break; |
2264 | #endif | |
0f8a249a | 2265 | } else if (xop == 0x34) { /* FPU Operations */ |
6ae20372 | 2266 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
a80dde08 | 2267 | goto jmp_insn; |
0f8a249a | 2268 | gen_op_clear_ieee_excp_and_FTT(); |
e8af50a3 | 2269 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a BS |
2270 | rs2 = GET_FIELD(insn, 27, 31); |
2271 | xop = GET_FIELD(insn, 18, 26); | |
2272 | switch (xop) { | |
2273 | case 0x1: /* fmovs */ | |
2274 | gen_op_load_fpr_FT0(rs2); | |
2275 | gen_op_store_FT0_fpr(rd); | |
2276 | break; | |
2277 | case 0x5: /* fnegs */ | |
2278 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 2279 | tcg_gen_helper_0_0(helper_fnegs); |
0f8a249a BS |
2280 | gen_op_store_FT0_fpr(rd); |
2281 | break; | |
2282 | case 0x9: /* fabss */ | |
2283 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2284 | tcg_gen_helper_0_0(helper_fabss); |
0f8a249a BS |
2285 | gen_op_store_FT0_fpr(rd); |
2286 | break; | |
2287 | case 0x29: /* fsqrts */ | |
64a88d5d | 2288 | CHECK_FPU_FEATURE(dc, FSQRT); |
0f8a249a | 2289 | gen_op_load_fpr_FT1(rs2); |
7e8c2b6c BS |
2290 | gen_clear_float_exceptions(); |
2291 | tcg_gen_helper_0_0(helper_fsqrts); | |
2292 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); | |
0f8a249a BS |
2293 | gen_op_store_FT0_fpr(rd); |
2294 | break; | |
2295 | case 0x2a: /* fsqrtd */ | |
64a88d5d | 2296 | CHECK_FPU_FEATURE(dc, FSQRT); |
0f8a249a | 2297 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
7e8c2b6c BS |
2298 | gen_clear_float_exceptions(); |
2299 | tcg_gen_helper_0_0(helper_fsqrtd); | |
2300 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); | |
0f8a249a BS |
2301 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2302 | break; | |
2303 | case 0x2b: /* fsqrtq */ | |
64a88d5d | 2304 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2305 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
7e8c2b6c BS |
2306 | gen_clear_float_exceptions(); |
2307 | tcg_gen_helper_0_0(helper_fsqrtq); | |
2308 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); | |
1f587329 BS |
2309 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2310 | break; | |
0f8a249a BS |
2311 | case 0x41: |
2312 | gen_op_load_fpr_FT0(rs1); | |
2313 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2314 | gen_clear_float_exceptions(); |
44e7757c | 2315 | tcg_gen_helper_0_0(helper_fadds); |
7e8c2b6c | 2316 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2317 | gen_op_store_FT0_fpr(rd); |
2318 | break; | |
2319 | case 0x42: | |
2320 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
2321 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2322 | gen_clear_float_exceptions(); |
44e7757c | 2323 | tcg_gen_helper_0_0(helper_faddd); |
7e8c2b6c | 2324 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2325 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2326 | break; | |
2327 | case 0x43: /* faddq */ | |
64a88d5d | 2328 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 BS |
2329 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2330 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2331 | gen_clear_float_exceptions(); |
44e7757c | 2332 | tcg_gen_helper_0_0(helper_faddq); |
7e8c2b6c | 2333 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2334 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2335 | break; | |
0f8a249a BS |
2336 | case 0x45: |
2337 | gen_op_load_fpr_FT0(rs1); | |
2338 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2339 | gen_clear_float_exceptions(); |
44e7757c | 2340 | tcg_gen_helper_0_0(helper_fsubs); |
7e8c2b6c | 2341 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2342 | gen_op_store_FT0_fpr(rd); |
2343 | break; | |
2344 | case 0x46: | |
2345 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
2346 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2347 | gen_clear_float_exceptions(); |
44e7757c | 2348 | tcg_gen_helper_0_0(helper_fsubd); |
7e8c2b6c | 2349 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2350 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2351 | break; | |
2352 | case 0x47: /* fsubq */ | |
64a88d5d | 2353 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 BS |
2354 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2355 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2356 | gen_clear_float_exceptions(); |
44e7757c | 2357 | tcg_gen_helper_0_0(helper_fsubq); |
7e8c2b6c | 2358 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2359 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2360 | break; | |
64a88d5d BS |
2361 | case 0x49: /* fmuls */ |
2362 | CHECK_FPU_FEATURE(dc, FMUL); | |
0f8a249a BS |
2363 | gen_op_load_fpr_FT0(rs1); |
2364 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2365 | gen_clear_float_exceptions(); |
44e7757c | 2366 | tcg_gen_helper_0_0(helper_fmuls); |
7e8c2b6c | 2367 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2368 | gen_op_store_FT0_fpr(rd); |
2369 | break; | |
64a88d5d BS |
2370 | case 0x4a: /* fmuld */ |
2371 | CHECK_FPU_FEATURE(dc, FMUL); | |
0f8a249a BS |
2372 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2373 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2374 | gen_clear_float_exceptions(); |
44e7757c | 2375 | tcg_gen_helper_0_0(helper_fmuld); |
7e8c2b6c | 2376 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2382dc6b | 2377 | gen_op_store_DT0_fpr(DFPREG(rd)); |
0f8a249a BS |
2378 | break; |
2379 | case 0x4b: /* fmulq */ | |
64a88d5d BS |
2380 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2381 | CHECK_FPU_FEATURE(dc, FMUL); | |
1f587329 BS |
2382 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2383 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2384 | gen_clear_float_exceptions(); |
44e7757c | 2385 | tcg_gen_helper_0_0(helper_fmulq); |
7e8c2b6c | 2386 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2387 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2388 | break; | |
0f8a249a BS |
2389 | case 0x4d: |
2390 | gen_op_load_fpr_FT0(rs1); | |
2391 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2392 | gen_clear_float_exceptions(); |
44e7757c | 2393 | tcg_gen_helper_0_0(helper_fdivs); |
7e8c2b6c | 2394 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2395 | gen_op_store_FT0_fpr(rd); |
2396 | break; | |
2397 | case 0x4e: | |
2398 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
2399 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2400 | gen_clear_float_exceptions(); |
44e7757c | 2401 | tcg_gen_helper_0_0(helper_fdivd); |
7e8c2b6c | 2402 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2403 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2404 | break; | |
2405 | case 0x4f: /* fdivq */ | |
64a88d5d | 2406 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 BS |
2407 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2408 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2409 | gen_clear_float_exceptions(); |
44e7757c | 2410 | tcg_gen_helper_0_0(helper_fdivq); |
7e8c2b6c | 2411 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2412 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2413 | break; | |
0f8a249a BS |
2414 | case 0x69: |
2415 | gen_op_load_fpr_FT0(rs1); | |
2416 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2417 | gen_clear_float_exceptions(); |
44e7757c | 2418 | tcg_gen_helper_0_0(helper_fsmuld); |
7e8c2b6c | 2419 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2420 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2421 | break; | |
2422 | case 0x6e: /* fdmulq */ | |
64a88d5d | 2423 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 BS |
2424 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2425 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2426 | gen_clear_float_exceptions(); |
44e7757c | 2427 | tcg_gen_helper_0_0(helper_fdmulq); |
7e8c2b6c | 2428 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2429 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2430 | break; | |
0f8a249a BS |
2431 | case 0xc4: |
2432 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2433 | gen_clear_float_exceptions(); |
44e7757c | 2434 | tcg_gen_helper_0_0(helper_fitos); |
7e8c2b6c | 2435 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2436 | gen_op_store_FT0_fpr(rd); |
2437 | break; | |
2438 | case 0xc6: | |
2439 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2440 | gen_clear_float_exceptions(); |
44e7757c | 2441 | tcg_gen_helper_0_0(helper_fdtos); |
7e8c2b6c | 2442 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2443 | gen_op_store_FT0_fpr(rd); |
2444 | break; | |
2445 | case 0xc7: /* fqtos */ | |
64a88d5d | 2446 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2447 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
7e8c2b6c | 2448 | gen_clear_float_exceptions(); |
44e7757c | 2449 | tcg_gen_helper_0_0(helper_fqtos); |
7e8c2b6c | 2450 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2451 | gen_op_store_FT0_fpr(rd); |
2452 | break; | |
0f8a249a BS |
2453 | case 0xc8: |
2454 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 2455 | tcg_gen_helper_0_0(helper_fitod); |
0f8a249a BS |
2456 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2457 | break; | |
2458 | case 0xc9: | |
2459 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 2460 | tcg_gen_helper_0_0(helper_fstod); |
0f8a249a BS |
2461 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2462 | break; | |
2463 | case 0xcb: /* fqtod */ | |
64a88d5d | 2464 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2465 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
7e8c2b6c | 2466 | gen_clear_float_exceptions(); |
44e7757c | 2467 | tcg_gen_helper_0_0(helper_fqtod); |
7e8c2b6c | 2468 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2469 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2470 | break; | |
0f8a249a | 2471 | case 0xcc: /* fitoq */ |
64a88d5d | 2472 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2473 | gen_op_load_fpr_FT1(rs2); |
44e7757c | 2474 | tcg_gen_helper_0_0(helper_fitoq); |
1f587329 BS |
2475 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2476 | break; | |
0f8a249a | 2477 | case 0xcd: /* fstoq */ |
64a88d5d | 2478 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2479 | gen_op_load_fpr_FT1(rs2); |
44e7757c | 2480 | tcg_gen_helper_0_0(helper_fstoq); |
1f587329 BS |
2481 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2482 | break; | |
0f8a249a | 2483 | case 0xce: /* fdtoq */ |
64a88d5d | 2484 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2485 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
44e7757c | 2486 | tcg_gen_helper_0_0(helper_fdtoq); |
1f587329 BS |
2487 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2488 | break; | |
0f8a249a BS |
2489 | case 0xd1: |
2490 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2491 | gen_clear_float_exceptions(); |
44e7757c | 2492 | tcg_gen_helper_0_0(helper_fstoi); |
7e8c2b6c | 2493 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2494 | gen_op_store_FT0_fpr(rd); |
2495 | break; | |
2496 | case 0xd2: | |
2382dc6b | 2497 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
7e8c2b6c | 2498 | gen_clear_float_exceptions(); |
44e7757c | 2499 | tcg_gen_helper_0_0(helper_fdtoi); |
7e8c2b6c | 2500 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2501 | gen_op_store_FT0_fpr(rd); |
2502 | break; | |
2503 | case 0xd3: /* fqtoi */ | |
64a88d5d | 2504 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2505 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
7e8c2b6c | 2506 | gen_clear_float_exceptions(); |
44e7757c | 2507 | tcg_gen_helper_0_0(helper_fqtoi); |
7e8c2b6c | 2508 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2509 | gen_op_store_FT0_fpr(rd); |
2510 | break; | |
3475187d | 2511 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
2512 | case 0x2: /* V9 fmovd */ |
2513 | gen_op_load_fpr_DT0(DFPREG(rs2)); | |
2514 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
2515 | break; | |
1f587329 | 2516 | case 0x3: /* V9 fmovq */ |
64a88d5d | 2517 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 BS |
2518 | gen_op_load_fpr_QT0(QFPREG(rs2)); |
2519 | gen_op_store_QT0_fpr(QFPREG(rd)); | |
2520 | break; | |
0f8a249a BS |
2521 | case 0x6: /* V9 fnegd */ |
2522 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 2523 | tcg_gen_helper_0_0(helper_fnegd); |
0f8a249a BS |
2524 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2525 | break; | |
1f587329 | 2526 | case 0x7: /* V9 fnegq */ |
64a88d5d | 2527 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2528 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
44e7757c | 2529 | tcg_gen_helper_0_0(helper_fnegq); |
1f587329 BS |
2530 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2531 | break; | |
0f8a249a BS |
2532 | case 0xa: /* V9 fabsd */ |
2533 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2534 | tcg_gen_helper_0_0(helper_fabsd); |
0f8a249a BS |
2535 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2536 | break; | |
1f587329 | 2537 | case 0xb: /* V9 fabsq */ |
64a88d5d | 2538 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2539 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
7e8c2b6c | 2540 | tcg_gen_helper_0_0(helper_fabsq); |
1f587329 BS |
2541 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2542 | break; | |
0f8a249a BS |
2543 | case 0x81: /* V9 fstox */ |
2544 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2545 | gen_clear_float_exceptions(); |
44e7757c | 2546 | tcg_gen_helper_0_0(helper_fstox); |
7e8c2b6c | 2547 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2548 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2549 | break; | |
2550 | case 0x82: /* V9 fdtox */ | |
2551 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2552 | gen_clear_float_exceptions(); |
44e7757c | 2553 | tcg_gen_helper_0_0(helper_fdtox); |
7e8c2b6c | 2554 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2555 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2556 | break; | |
1f587329 | 2557 | case 0x83: /* V9 fqtox */ |
64a88d5d | 2558 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2559 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
7e8c2b6c | 2560 | gen_clear_float_exceptions(); |
44e7757c | 2561 | tcg_gen_helper_0_0(helper_fqtox); |
7e8c2b6c | 2562 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2563 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2564 | break; | |
0f8a249a BS |
2565 | case 0x84: /* V9 fxtos */ |
2566 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2567 | gen_clear_float_exceptions(); |
44e7757c | 2568 | tcg_gen_helper_0_0(helper_fxtos); |
7e8c2b6c | 2569 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2570 | gen_op_store_FT0_fpr(rd); |
2571 | break; | |
2572 | case 0x88: /* V9 fxtod */ | |
2573 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2574 | gen_clear_float_exceptions(); |
44e7757c | 2575 | tcg_gen_helper_0_0(helper_fxtod); |
7e8c2b6c | 2576 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
0f8a249a BS |
2577 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2578 | break; | |
0f8a249a | 2579 | case 0x8c: /* V9 fxtoq */ |
64a88d5d | 2580 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 2581 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
7e8c2b6c | 2582 | gen_clear_float_exceptions(); |
44e7757c | 2583 | tcg_gen_helper_0_0(helper_fxtoq); |
7e8c2b6c | 2584 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
1f587329 BS |
2585 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2586 | break; | |
0f8a249a BS |
2587 | #endif |
2588 | default: | |
2589 | goto illegal_insn; | |
2590 | } | |
2591 | } else if (xop == 0x35) { /* FPU Operations */ | |
3475187d | 2592 | #ifdef TARGET_SPARC64 |
0f8a249a | 2593 | int cond; |
3475187d | 2594 | #endif |
6ae20372 | 2595 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
a80dde08 | 2596 | goto jmp_insn; |
0f8a249a | 2597 | gen_op_clear_ieee_excp_and_FTT(); |
cf495bcf | 2598 | rs1 = GET_FIELD(insn, 13, 17); |
0f8a249a BS |
2599 | rs2 = GET_FIELD(insn, 27, 31); |
2600 | xop = GET_FIELD(insn, 18, 26); | |
3475187d | 2601 | #ifdef TARGET_SPARC64 |
0f8a249a | 2602 | if ((xop & 0x11f) == 0x005) { // V9 fmovsr |
dcf24905 BS |
2603 | int l1; |
2604 | ||
2605 | l1 = gen_new_label(); | |
0f8a249a | 2606 | cond = GET_FIELD_SP(insn, 14, 17); |
9322a4bf | 2607 | cpu_src1 = get_src1(insn, cpu_src1); |
cb63669a PB |
2608 | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2609 | 0, l1); | |
19f329ad | 2610 | gen_op_load_fpr_FT0(rs2); |
0f8a249a | 2611 | gen_op_store_FT0_fpr(rd); |
dcf24905 | 2612 | gen_set_label(l1); |
0f8a249a BS |
2613 | break; |
2614 | } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr | |
dcf24905 BS |
2615 | int l1; |
2616 | ||
2617 | l1 = gen_new_label(); | |
0f8a249a | 2618 | cond = GET_FIELD_SP(insn, 14, 17); |
9322a4bf | 2619 | cpu_src1 = get_src1(insn, cpu_src1); |
cb63669a PB |
2620 | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2621 | 0, l1); | |
19f329ad | 2622 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
2382dc6b | 2623 | gen_op_store_DT0_fpr(DFPREG(rd)); |
dcf24905 | 2624 | gen_set_label(l1); |
0f8a249a BS |
2625 | break; |
2626 | } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr | |
dcf24905 BS |
2627 | int l1; |
2628 | ||
64a88d5d | 2629 | CHECK_FPU_FEATURE(dc, FLOAT128); |
dcf24905 | 2630 | l1 = gen_new_label(); |
1f587329 | 2631 | cond = GET_FIELD_SP(insn, 14, 17); |
9322a4bf | 2632 | cpu_src1 = get_src1(insn, cpu_src1); |
cb63669a PB |
2633 | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2634 | 0, l1); | |
19f329ad | 2635 | gen_op_load_fpr_QT0(QFPREG(rs2)); |
1f587329 | 2636 | gen_op_store_QT0_fpr(QFPREG(rd)); |
dcf24905 | 2637 | gen_set_label(l1); |
1f587329 | 2638 | break; |
0f8a249a BS |
2639 | } |
2640 | #endif | |
2641 | switch (xop) { | |
3475187d | 2642 | #ifdef TARGET_SPARC64 |
19f329ad BS |
2643 | #define FMOVCC(size_FDQ, fcc) \ |
2644 | { \ | |
0425bee5 | 2645 | TCGv r_cond; \ |
19f329ad BS |
2646 | int l1; \ |
2647 | \ | |
2648 | l1 = gen_new_label(); \ | |
19f329ad | 2649 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ |
19f329ad BS |
2650 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2651 | gen_fcond(r_cond, fcc, cond); \ | |
cb63669a PB |
2652 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2653 | 0, l1); \ | |
77f193da BS |
2654 | glue(glue(gen_op_load_fpr_, size_FDQ), T0) \ |
2655 | (glue(size_FDQ, FPREG(rs2))); \ | |
2656 | glue(glue(gen_op_store_, size_FDQ), T0_fpr) \ | |
2657 | (glue(size_FDQ, FPREG(rd))); \ | |
19f329ad BS |
2658 | gen_set_label(l1); \ |
2659 | } | |
0f8a249a | 2660 | case 0x001: /* V9 fmovscc %fcc0 */ |
19f329ad | 2661 | FMOVCC(F, 0); |
0f8a249a BS |
2662 | break; |
2663 | case 0x002: /* V9 fmovdcc %fcc0 */ | |
19f329ad | 2664 | FMOVCC(D, 0); |
0f8a249a BS |
2665 | break; |
2666 | case 0x003: /* V9 fmovqcc %fcc0 */ | |
64a88d5d | 2667 | CHECK_FPU_FEATURE(dc, FLOAT128); |
19f329ad | 2668 | FMOVCC(Q, 0); |
1f587329 | 2669 | break; |
0f8a249a | 2670 | case 0x041: /* V9 fmovscc %fcc1 */ |
19f329ad | 2671 | FMOVCC(F, 1); |
0f8a249a BS |
2672 | break; |
2673 | case 0x042: /* V9 fmovdcc %fcc1 */ | |
19f329ad | 2674 | FMOVCC(D, 1); |
0f8a249a BS |
2675 | break; |
2676 | case 0x043: /* V9 fmovqcc %fcc1 */ | |
64a88d5d | 2677 | CHECK_FPU_FEATURE(dc, FLOAT128); |
19f329ad | 2678 | FMOVCC(Q, 1); |
1f587329 | 2679 | break; |
0f8a249a | 2680 | case 0x081: /* V9 fmovscc %fcc2 */ |
19f329ad | 2681 | FMOVCC(F, 2); |
0f8a249a BS |
2682 | break; |
2683 | case 0x082: /* V9 fmovdcc %fcc2 */ | |
19f329ad | 2684 | FMOVCC(D, 2); |
0f8a249a BS |
2685 | break; |
2686 | case 0x083: /* V9 fmovqcc %fcc2 */ | |
64a88d5d | 2687 | CHECK_FPU_FEATURE(dc, FLOAT128); |
19f329ad | 2688 | FMOVCC(Q, 2); |
1f587329 | 2689 | break; |
0f8a249a | 2690 | case 0x0c1: /* V9 fmovscc %fcc3 */ |
19f329ad | 2691 | FMOVCC(F, 3); |
0f8a249a BS |
2692 | break; |
2693 | case 0x0c2: /* V9 fmovdcc %fcc3 */ | |
19f329ad | 2694 | FMOVCC(D, 3); |
0f8a249a BS |
2695 | break; |
2696 | case 0x0c3: /* V9 fmovqcc %fcc3 */ | |
64a88d5d | 2697 | CHECK_FPU_FEATURE(dc, FLOAT128); |
19f329ad | 2698 | FMOVCC(Q, 3); |
1f587329 | 2699 | break; |
19f329ad BS |
2700 | #undef FMOVCC |
2701 | #define FMOVCC(size_FDQ, icc) \ | |
2702 | { \ | |
0425bee5 | 2703 | TCGv r_cond; \ |
19f329ad BS |
2704 | int l1; \ |
2705 | \ | |
2706 | l1 = gen_new_label(); \ | |
19f329ad | 2707 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ |
19f329ad BS |
2708 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2709 | gen_cond(r_cond, icc, cond); \ | |
cb63669a PB |
2710 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2711 | 0, l1); \ | |
77f193da BS |
2712 | glue(glue(gen_op_load_fpr_, size_FDQ), T0) \ |
2713 | (glue(size_FDQ, FPREG(rs2))); \ | |
2714 | glue(glue(gen_op_store_, size_FDQ), T0_fpr) \ | |
2715 | (glue(size_FDQ, FPREG(rd))); \ | |
19f329ad BS |
2716 | gen_set_label(l1); \ |
2717 | } | |
2718 | ||
0f8a249a | 2719 | case 0x101: /* V9 fmovscc %icc */ |
19f329ad | 2720 | FMOVCC(F, 0); |
0f8a249a BS |
2721 | break; |
2722 | case 0x102: /* V9 fmovdcc %icc */ | |
19f329ad | 2723 | FMOVCC(D, 0); |
0f8a249a | 2724 | case 0x103: /* V9 fmovqcc %icc */ |
64a88d5d BS |
2725 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2726 | FMOVCC(Q, 0); | |
1f587329 | 2727 | break; |
0f8a249a | 2728 | case 0x181: /* V9 fmovscc %xcc */ |
19f329ad | 2729 | FMOVCC(F, 1); |
0f8a249a BS |
2730 | break; |
2731 | case 0x182: /* V9 fmovdcc %xcc */ | |
19f329ad | 2732 | FMOVCC(D, 1); |
0f8a249a BS |
2733 | break; |
2734 | case 0x183: /* V9 fmovqcc %xcc */ | |
64a88d5d | 2735 | CHECK_FPU_FEATURE(dc, FLOAT128); |
19f329ad | 2736 | FMOVCC(Q, 1); |
1f587329 | 2737 | break; |
19f329ad | 2738 | #undef FMOVCC |
1f587329 BS |
2739 | #endif |
2740 | case 0x51: /* fcmps, V9 %fcc */ | |
0f8a249a BS |
2741 | gen_op_load_fpr_FT0(rs1); |
2742 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2743 | gen_op_fcmps(rd & 3); |
0f8a249a | 2744 | break; |
1f587329 | 2745 | case 0x52: /* fcmpd, V9 %fcc */ |
0f8a249a BS |
2746 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2747 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2748 | gen_op_fcmpd(rd & 3); |
0f8a249a | 2749 | break; |
1f587329 | 2750 | case 0x53: /* fcmpq, V9 %fcc */ |
64a88d5d | 2751 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 BS |
2752 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2753 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2754 | gen_op_fcmpq(rd & 3); |
1f587329 | 2755 | break; |
0f8a249a BS |
2756 | case 0x55: /* fcmpes, V9 %fcc */ |
2757 | gen_op_load_fpr_FT0(rs1); | |
2758 | gen_op_load_fpr_FT1(rs2); | |
7e8c2b6c | 2759 | gen_op_fcmpes(rd & 3); |
0f8a249a BS |
2760 | break; |
2761 | case 0x56: /* fcmped, V9 %fcc */ | |
2762 | gen_op_load_fpr_DT0(DFPREG(rs1)); | |
2763 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
7e8c2b6c | 2764 | gen_op_fcmped(rd & 3); |
0f8a249a | 2765 | break; |
1f587329 | 2766 | case 0x57: /* fcmpeq, V9 %fcc */ |
64a88d5d | 2767 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 BS |
2768 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2769 | gen_op_load_fpr_QT1(QFPREG(rs2)); | |
7e8c2b6c | 2770 | gen_op_fcmpeq(rd & 3); |
1f587329 | 2771 | break; |
0f8a249a BS |
2772 | default: |
2773 | goto illegal_insn; | |
2774 | } | |
0f8a249a BS |
2775 | } else if (xop == 0x2) { |
2776 | // clr/mov shortcut | |
e80cfcfc FB |
2777 | |
2778 | rs1 = GET_FIELD(insn, 13, 17); | |
0f8a249a | 2779 | if (rs1 == 0) { |
1a2fb1c0 | 2780 | // or %g0, x, y -> mov T0, x; mov y, T0 |
0f8a249a BS |
2781 | if (IS_IMM) { /* immediate */ |
2782 | rs2 = GET_FIELDs(insn, 19, 31); | |
9c6c6662 | 2783 | gen_movl_TN_reg(rd, tcg_const_tl((int)rs2)); |
0f8a249a BS |
2784 | } else { /* register */ |
2785 | rs2 = GET_FIELD(insn, 27, 31); | |
6ae20372 | 2786 | gen_movl_reg_TN(rs2, cpu_dst); |
9c6c6662 | 2787 | gen_movl_TN_reg(rd, cpu_dst); |
0f8a249a | 2788 | } |
0f8a249a | 2789 | } else { |
9322a4bf | 2790 | cpu_src1 = get_src1(insn, cpu_src1); |
0f8a249a | 2791 | if (IS_IMM) { /* immediate */ |
0f8a249a | 2792 | rs2 = GET_FIELDs(insn, 19, 31); |
6ae20372 | 2793 | tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2); |
9c6c6662 | 2794 | gen_movl_TN_reg(rd, cpu_dst); |
0f8a249a BS |
2795 | } else { /* register */ |
2796 | // or x, %g0, y -> mov T1, x; mov y, T1 | |
2797 | rs2 = GET_FIELD(insn, 27, 31); | |
2798 | if (rs2 != 0) { | |
6ae20372 BS |
2799 | gen_movl_reg_TN(rs2, cpu_src2); |
2800 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); | |
9c6c6662 | 2801 | gen_movl_TN_reg(rd, cpu_dst); |
6f551262 | 2802 | } else |
9c6c6662 | 2803 | gen_movl_TN_reg(rd, cpu_src1); |
0f8a249a | 2804 | } |
0f8a249a | 2805 | } |
83469015 | 2806 | #ifdef TARGET_SPARC64 |
0f8a249a | 2807 | } else if (xop == 0x25) { /* sll, V9 sllx */ |
9322a4bf | 2808 | cpu_src1 = get_src1(insn, cpu_src1); |
0f8a249a | 2809 | if (IS_IMM) { /* immediate */ |
83469015 | 2810 | rs2 = GET_FIELDs(insn, 20, 31); |
1a2fb1c0 | 2811 | if (insn & (1 << 12)) { |
6ae20372 | 2812 | tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f); |
1a2fb1c0 | 2813 | } else { |
6ae20372 BS |
2814 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); |
2815 | tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f); | |
1a2fb1c0 | 2816 | } |
0f8a249a | 2817 | } else { /* register */ |
83469015 | 2818 | rs2 = GET_FIELD(insn, 27, 31); |
6ae20372 | 2819 | gen_movl_reg_TN(rs2, cpu_src2); |
1a2fb1c0 | 2820 | if (insn & (1 << 12)) { |
6ae20372 BS |
2821 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); |
2822 | tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0); | |
1a2fb1c0 | 2823 | } else { |
6ae20372 BS |
2824 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); |
2825 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); | |
2826 | tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0); | |
1a2fb1c0 | 2827 | } |
83469015 | 2828 | } |
6ae20372 | 2829 | gen_movl_TN_reg(rd, cpu_dst); |
0f8a249a | 2830 | } else if (xop == 0x26) { /* srl, V9 srlx */ |
9322a4bf | 2831 | cpu_src1 = get_src1(insn, cpu_src1); |
0f8a249a | 2832 | if (IS_IMM) { /* immediate */ |
83469015 | 2833 | rs2 = GET_FIELDs(insn, 20, 31); |
1a2fb1c0 | 2834 | if (insn & (1 << 12)) { |
6ae20372 | 2835 | tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f); |
1a2fb1c0 | 2836 | } else { |
6ae20372 BS |
2837 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); |
2838 | tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f); | |
1a2fb1c0 | 2839 | } |
0f8a249a | 2840 | } else { /* register */ |
83469015 | 2841 | rs2 = GET_FIELD(insn, 27, 31); |
6ae20372 | 2842 | gen_movl_reg_TN(rs2, cpu_src2); |
1a2fb1c0 | 2843 | if (insn & (1 << 12)) { |
6ae20372 BS |
2844 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); |
2845 | tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0); | |
1a2fb1c0 | 2846 | } else { |
6ae20372 BS |
2847 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); |
2848 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); | |
2849 | tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0); | |
1a2fb1c0 | 2850 | } |
83469015 | 2851 | } |
6ae20372 | 2852 | gen_movl_TN_reg(rd, cpu_dst); |
0f8a249a | 2853 | } else if (xop == 0x27) { /* sra, V9 srax */ |
9322a4bf | 2854 | cpu_src1 = get_src1(insn, cpu_src1); |
0f8a249a | 2855 | if (IS_IMM) { /* immediate */ |
83469015 | 2856 | rs2 = GET_FIELDs(insn, 20, 31); |
1a2fb1c0 | 2857 | if (insn & (1 << 12)) { |
6ae20372 | 2858 | tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f); |
1a2fb1c0 | 2859 | } else { |
6ae20372 BS |
2860 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); |
2861 | tcg_gen_ext_i32_i64(cpu_dst, cpu_dst); | |
2862 | tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f); | |
1a2fb1c0 | 2863 | } |
0f8a249a | 2864 | } else { /* register */ |
83469015 | 2865 | rs2 = GET_FIELD(insn, 27, 31); |
6ae20372 | 2866 | gen_movl_reg_TN(rs2, cpu_src2); |
1a2fb1c0 | 2867 | if (insn & (1 << 12)) { |
6ae20372 BS |
2868 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); |
2869 | tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0); | |
1a2fb1c0 | 2870 | } else { |
6ae20372 BS |
2871 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); |
2872 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); | |
2873 | tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0); | |
1a2fb1c0 | 2874 | } |
83469015 | 2875 | } |
6ae20372 | 2876 | gen_movl_TN_reg(rd, cpu_dst); |
e80cfcfc | 2877 | #endif |
fcc72045 | 2878 | } else if (xop < 0x36) { |
9322a4bf | 2879 | cpu_src1 = get_src1(insn, cpu_src1); |
a49d9390 | 2880 | cpu_src2 = get_src2(insn, cpu_src2); |
cf495bcf FB |
2881 | if (xop < 0x20) { |
2882 | switch (xop & ~0x10) { | |
2883 | case 0x0: | |
2884 | if (xop & 0x10) | |
6ae20372 | 2885 | gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf | 2886 | else |
6ae20372 | 2887 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf FB |
2888 | break; |
2889 | case 0x1: | |
6ae20372 | 2890 | tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf | 2891 | if (xop & 0x10) |
6ae20372 | 2892 | gen_op_logic_cc(cpu_dst); |
cf495bcf FB |
2893 | break; |
2894 | case 0x2: | |
6ae20372 | 2895 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); |
0f8a249a | 2896 | if (xop & 0x10) |
6ae20372 | 2897 | gen_op_logic_cc(cpu_dst); |
0f8a249a | 2898 | break; |
cf495bcf | 2899 | case 0x3: |
6ae20372 | 2900 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf | 2901 | if (xop & 0x10) |
6ae20372 | 2902 | gen_op_logic_cc(cpu_dst); |
cf495bcf FB |
2903 | break; |
2904 | case 0x4: | |
2905 | if (xop & 0x10) | |
6ae20372 | 2906 | gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf | 2907 | else |
6ae20372 | 2908 | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf FB |
2909 | break; |
2910 | case 0x5: | |
6ae20372 BS |
2911 | tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1); |
2912 | tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
cf495bcf | 2913 | if (xop & 0x10) |
6ae20372 | 2914 | gen_op_logic_cc(cpu_dst); |
cf495bcf FB |
2915 | break; |
2916 | case 0x6: | |
6ae20372 BS |
2917 | tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1); |
2918 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
cf495bcf | 2919 | if (xop & 0x10) |
6ae20372 | 2920 | gen_op_logic_cc(cpu_dst); |
cf495bcf FB |
2921 | break; |
2922 | case 0x7: | |
6ae20372 BS |
2923 | tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1); |
2924 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
cf495bcf | 2925 | if (xop & 0x10) |
6ae20372 | 2926 | gen_op_logic_cc(cpu_dst); |
cf495bcf FB |
2927 | break; |
2928 | case 0x8: | |
cf495bcf | 2929 | if (xop & 0x10) |
6ae20372 | 2930 | gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2); |
38bc628b | 2931 | else { |
dc99a3f2 | 2932 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
6ae20372 BS |
2933 | tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0); |
2934 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
38bc628b | 2935 | } |
cf495bcf | 2936 | break; |
ded3ab80 | 2937 | #ifdef TARGET_SPARC64 |
0f8a249a | 2938 | case 0x9: /* V9 mulx */ |
6ae20372 | 2939 | tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2); |
ded3ab80 PB |
2940 | break; |
2941 | #endif | |
cf495bcf | 2942 | case 0xa: |
64a88d5d | 2943 | CHECK_IU_FEATURE(dc, MUL); |
6ae20372 | 2944 | gen_op_umul(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf | 2945 | if (xop & 0x10) |
6ae20372 | 2946 | gen_op_logic_cc(cpu_dst); |
cf495bcf FB |
2947 | break; |
2948 | case 0xb: | |
64a88d5d | 2949 | CHECK_IU_FEATURE(dc, MUL); |
6ae20372 | 2950 | gen_op_smul(cpu_dst, cpu_src1, cpu_src2); |
cf495bcf | 2951 | if (xop & 0x10) |
6ae20372 | 2952 | gen_op_logic_cc(cpu_dst); |
cf495bcf FB |
2953 | break; |
2954 | case 0xc: | |
cf495bcf | 2955 | if (xop & 0x10) |
6ae20372 | 2956 | gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2); |
38bc628b | 2957 | else { |
dc99a3f2 | 2958 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
6ae20372 BS |
2959 | tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0); |
2960 | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
38bc628b | 2961 | } |
cf495bcf | 2962 | break; |
ded3ab80 | 2963 | #ifdef TARGET_SPARC64 |
0f8a249a | 2964 | case 0xd: /* V9 udivx */ |
6ae20372 BS |
2965 | gen_trap_ifdivzero_tl(cpu_src2); |
2966 | tcg_gen_divu_i64(cpu_dst, cpu_src1, cpu_src2); | |
ded3ab80 PB |
2967 | break; |
2968 | #endif | |
cf495bcf | 2969 | case 0xe: |
64a88d5d | 2970 | CHECK_IU_FEATURE(dc, DIV); |
77f193da BS |
2971 | tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1, |
2972 | cpu_src2); | |
cf495bcf | 2973 | if (xop & 0x10) |
6ae20372 | 2974 | gen_op_div_cc(cpu_dst); |
cf495bcf FB |
2975 | break; |
2976 | case 0xf: | |
64a88d5d | 2977 | CHECK_IU_FEATURE(dc, DIV); |
77f193da BS |
2978 | tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1, |
2979 | cpu_src2); | |
cf495bcf | 2980 | if (xop & 0x10) |
6ae20372 | 2981 | gen_op_div_cc(cpu_dst); |
cf495bcf FB |
2982 | break; |
2983 | default: | |
2984 | goto illegal_insn; | |
2985 | } | |
6ae20372 | 2986 | gen_movl_TN_reg(rd, cpu_dst); |
cf495bcf FB |
2987 | } else { |
2988 | switch (xop) { | |
0f8a249a | 2989 | case 0x20: /* taddcc */ |
6ae20372 BS |
2990 | gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2); |
2991 | gen_movl_TN_reg(rd, cpu_dst); | |
0f8a249a BS |
2992 | break; |
2993 | case 0x21: /* tsubcc */ | |
6ae20372 BS |
2994 | gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2); |
2995 | gen_movl_TN_reg(rd, cpu_dst); | |
0f8a249a BS |
2996 | break; |
2997 | case 0x22: /* taddcctv */ | |
6ae20372 BS |
2998 | save_state(dc, cpu_cond); |
2999 | gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2); | |
3000 | gen_movl_TN_reg(rd, cpu_dst); | |
0f8a249a BS |
3001 | break; |
3002 | case 0x23: /* tsubcctv */ | |
6ae20372 BS |
3003 | save_state(dc, cpu_cond); |
3004 | gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2); | |
3005 | gen_movl_TN_reg(rd, cpu_dst); | |
0f8a249a | 3006 | break; |
cf495bcf | 3007 | case 0x24: /* mulscc */ |
6ae20372 BS |
3008 | gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2); |
3009 | gen_movl_TN_reg(rd, cpu_dst); | |
cf495bcf | 3010 | break; |
83469015 | 3011 | #ifndef TARGET_SPARC64 |
0f8a249a | 3012 | case 0x25: /* sll */ |
e35298cd BS |
3013 | if (IS_IMM) { /* immediate */ |
3014 | rs2 = GET_FIELDs(insn, 20, 31); | |
3015 | tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f); | |
3016 | } else { /* register */ | |
3017 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); | |
3018 | tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
3019 | } | |
6ae20372 | 3020 | gen_movl_TN_reg(rd, cpu_dst); |
cf495bcf | 3021 | break; |
83469015 | 3022 | case 0x26: /* srl */ |
e35298cd BS |
3023 | if (IS_IMM) { /* immediate */ |
3024 | rs2 = GET_FIELDs(insn, 20, 31); | |
3025 | tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f); | |
3026 | } else { /* register */ | |
3027 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); | |
3028 | tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
3029 | } | |
6ae20372 | 3030 | gen_movl_TN_reg(rd, cpu_dst); |
cf495bcf | 3031 | break; |
83469015 | 3032 | case 0x27: /* sra */ |
e35298cd BS |
3033 | if (IS_IMM) { /* immediate */ |
3034 | rs2 = GET_FIELDs(insn, 20, 31); | |
3035 | tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f); | |
3036 | } else { /* register */ | |
3037 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); | |
3038 | tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0); | |
3039 | } | |
6ae20372 | 3040 | gen_movl_TN_reg(rd, cpu_dst); |
cf495bcf | 3041 | break; |
83469015 | 3042 | #endif |
cf495bcf FB |
3043 | case 0x30: |
3044 | { | |
cf495bcf | 3045 | switch(rd) { |
3475187d | 3046 | case 0: /* wry */ |
6ae20372 | 3047 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
77f193da BS |
3048 | tcg_gen_st_tl(cpu_dst, cpu_env, |
3049 | offsetof(CPUSPARCState, y)); | |
cf495bcf | 3050 | break; |
65fe7b09 BS |
3051 | #ifndef TARGET_SPARC64 |
3052 | case 0x01 ... 0x0f: /* undefined in the | |
3053 | SPARCv8 manual, nop | |
3054 | on the microSPARC | |
3055 | II */ | |
3056 | case 0x10 ... 0x1f: /* implementation-dependent | |
3057 | in the SPARCv8 | |
3058 | manual, nop on the | |
3059 | microSPARC II */ | |
3060 | break; | |
3061 | #else | |
0f8a249a | 3062 | case 0x2: /* V9 wrccr */ |
6ae20372 BS |
3063 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3064 | tcg_gen_helper_0_1(helper_wrccr, cpu_dst); | |
0f8a249a BS |
3065 | break; |
3066 | case 0x3: /* V9 wrasi */ | |
6ae20372 BS |
3067 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3068 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); | |
77f193da BS |
3069 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3070 | offsetof(CPUSPARCState, asi)); | |
0f8a249a BS |
3071 | break; |
3072 | case 0x6: /* V9 wrfprs */ | |
6ae20372 BS |
3073 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3074 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); | |
77f193da BS |
3075 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3076 | offsetof(CPUSPARCState, fprs)); | |
6ae20372 | 3077 | save_state(dc, cpu_cond); |
3299908c | 3078 | gen_op_next_insn(); |
57fec1fe | 3079 | tcg_gen_exit_tb(0); |
3299908c | 3080 | dc->is_br = 1; |
0f8a249a BS |
3081 | break; |
3082 | case 0xf: /* V9 sir, nop if user */ | |
3475187d | 3083 | #if !defined(CONFIG_USER_ONLY) |
0f8a249a | 3084 | if (supervisor(dc)) |
1a2fb1c0 | 3085 | ; // XXX |
3475187d | 3086 | #endif |
0f8a249a BS |
3087 | break; |
3088 | case 0x13: /* Graphics Status */ | |
6ae20372 | 3089 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
725cb90b | 3090 | goto jmp_insn; |
6ae20372 | 3091 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
77f193da BS |
3092 | tcg_gen_st_tl(cpu_dst, cpu_env, |
3093 | offsetof(CPUSPARCState, gsr)); | |
0f8a249a BS |
3094 | break; |
3095 | case 0x17: /* Tick compare */ | |
83469015 | 3096 | #if !defined(CONFIG_USER_ONLY) |
0f8a249a BS |
3097 | if (!supervisor(dc)) |
3098 | goto illegal_insn; | |
83469015 | 3099 | #endif |
ccd4a219 BS |
3100 | { |
3101 | TCGv r_tickptr; | |
3102 | ||
6ae20372 BS |
3103 | tcg_gen_xor_tl(cpu_dst, cpu_src1, |
3104 | cpu_src2); | |
77f193da BS |
3105 | tcg_gen_st_tl(cpu_dst, cpu_env, |
3106 | offsetof(CPUSPARCState, | |
3107 | tick_cmpr)); | |
ccd4a219 BS |
3108 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3109 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
3110 | offsetof(CPUState, tick)); | |
3111 | tcg_gen_helper_0_2(helper_tick_set_limit, | |
6ae20372 | 3112 | r_tickptr, cpu_dst); |
ccd4a219 | 3113 | } |
0f8a249a BS |
3114 | break; |
3115 | case 0x18: /* System tick */ | |
83469015 | 3116 | #if !defined(CONFIG_USER_ONLY) |
0f8a249a BS |
3117 | if (!supervisor(dc)) |
3118 | goto illegal_insn; | |
83469015 | 3119 | #endif |
ccd4a219 BS |
3120 | { |
3121 | TCGv r_tickptr; | |
3122 | ||
6ae20372 BS |
3123 | tcg_gen_xor_tl(cpu_dst, cpu_src1, |
3124 | cpu_src2); | |
ccd4a219 BS |
3125 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3126 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
3127 | offsetof(CPUState, stick)); | |
3128 | tcg_gen_helper_0_2(helper_tick_set_count, | |
6ae20372 | 3129 | r_tickptr, cpu_dst); |
ccd4a219 | 3130 | } |
0f8a249a BS |
3131 | break; |
3132 | case 0x19: /* System tick compare */ | |
83469015 | 3133 | #if !defined(CONFIG_USER_ONLY) |
0f8a249a BS |
3134 | if (!supervisor(dc)) |
3135 | goto illegal_insn; | |
3475187d | 3136 | #endif |
ccd4a219 BS |
3137 | { |
3138 | TCGv r_tickptr; | |
3139 | ||
6ae20372 BS |
3140 | tcg_gen_xor_tl(cpu_dst, cpu_src1, |
3141 | cpu_src2); | |
77f193da BS |
3142 | tcg_gen_st_tl(cpu_dst, cpu_env, |
3143 | offsetof(CPUSPARCState, | |
3144 | stick_cmpr)); | |
ccd4a219 BS |
3145 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3146 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
3147 | offsetof(CPUState, stick)); | |
3148 | tcg_gen_helper_0_2(helper_tick_set_limit, | |
6ae20372 | 3149 | r_tickptr, cpu_dst); |
ccd4a219 | 3150 | } |
0f8a249a | 3151 | break; |
83469015 | 3152 | |
0f8a249a | 3153 | case 0x10: /* Performance Control */ |
77f193da BS |
3154 | case 0x11: /* Performance Instrumentation |
3155 | Counter */ | |
0f8a249a BS |
3156 | case 0x12: /* Dispatch Control */ |
3157 | case 0x14: /* Softint set */ | |
3158 | case 0x15: /* Softint clear */ | |
3159 | case 0x16: /* Softint write */ | |
83469015 | 3160 | #endif |
3475187d | 3161 | default: |
cf495bcf FB |
3162 | goto illegal_insn; |
3163 | } | |
3164 | } | |
3165 | break; | |
e8af50a3 | 3166 | #if !defined(CONFIG_USER_ONLY) |
af7bf89b | 3167 | case 0x31: /* wrpsr, V9 saved, restored */ |
e8af50a3 | 3168 | { |
0f8a249a BS |
3169 | if (!supervisor(dc)) |
3170 | goto priv_insn; | |
3475187d | 3171 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
3172 | switch (rd) { |
3173 | case 0: | |
72a9747b | 3174 | tcg_gen_helper_0_0(helper_saved); |
0f8a249a BS |
3175 | break; |
3176 | case 1: | |
72a9747b | 3177 | tcg_gen_helper_0_0(helper_restored); |
0f8a249a | 3178 | break; |
e9ebed4d BS |
3179 | case 2: /* UA2005 allclean */ |
3180 | case 3: /* UA2005 otherw */ | |
3181 | case 4: /* UA2005 normalw */ | |
3182 | case 5: /* UA2005 invalw */ | |
3183 | // XXX | |
0f8a249a | 3184 | default: |
3475187d FB |
3185 | goto illegal_insn; |
3186 | } | |
3187 | #else | |
6ae20372 BS |
3188 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3189 | tcg_gen_helper_0_1(helper_wrpsr, cpu_dst); | |
3190 | save_state(dc, cpu_cond); | |
9e61bde5 | 3191 | gen_op_next_insn(); |
57fec1fe | 3192 | tcg_gen_exit_tb(0); |
0f8a249a | 3193 | dc->is_br = 1; |
3475187d | 3194 | #endif |
e8af50a3 FB |
3195 | } |
3196 | break; | |
af7bf89b | 3197 | case 0x32: /* wrwim, V9 wrpr */ |
e8af50a3 | 3198 | { |
0f8a249a BS |
3199 | if (!supervisor(dc)) |
3200 | goto priv_insn; | |
6ae20372 | 3201 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3475187d | 3202 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
3203 | switch (rd) { |
3204 | case 0: // tpc | |
375ee38b BS |
3205 | { |
3206 | TCGv r_tsptr; | |
3207 | ||
3208 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
3209 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
3210 | offsetof(CPUState, tsptr)); | |
6ae20372 | 3211 | tcg_gen_st_tl(cpu_dst, r_tsptr, |
375ee38b BS |
3212 | offsetof(trap_state, tpc)); |
3213 | } | |
0f8a249a BS |
3214 | break; |
3215 | case 1: // tnpc | |
375ee38b BS |
3216 | { |
3217 | TCGv r_tsptr; | |
3218 | ||
3219 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
3220 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
3221 | offsetof(CPUState, tsptr)); | |
6ae20372 | 3222 | tcg_gen_st_tl(cpu_dst, r_tsptr, |
375ee38b BS |
3223 | offsetof(trap_state, tnpc)); |
3224 | } | |
0f8a249a BS |
3225 | break; |
3226 | case 2: // tstate | |
375ee38b BS |
3227 | { |
3228 | TCGv r_tsptr; | |
3229 | ||
3230 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
3231 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
3232 | offsetof(CPUState, tsptr)); | |
6ae20372 | 3233 | tcg_gen_st_tl(cpu_dst, r_tsptr, |
77f193da BS |
3234 | offsetof(trap_state, |
3235 | tstate)); | |
375ee38b | 3236 | } |
0f8a249a BS |
3237 | break; |
3238 | case 3: // tt | |
375ee38b BS |
3239 | { |
3240 | TCGv r_tsptr; | |
3241 | ||
3242 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); | |
3243 | tcg_gen_ld_ptr(r_tsptr, cpu_env, | |
3244 | offsetof(CPUState, tsptr)); | |
6ae20372 | 3245 | tcg_gen_st_i32(cpu_dst, r_tsptr, |
375ee38b BS |
3246 | offsetof(trap_state, tt)); |
3247 | } | |
0f8a249a BS |
3248 | break; |
3249 | case 4: // tick | |
ccd4a219 BS |
3250 | { |
3251 | TCGv r_tickptr; | |
3252 | ||
3253 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); | |
3254 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
3255 | offsetof(CPUState, tick)); | |
3256 | tcg_gen_helper_0_2(helper_tick_set_count, | |
6ae20372 | 3257 | r_tickptr, cpu_dst); |
ccd4a219 | 3258 | } |
0f8a249a BS |
3259 | break; |
3260 | case 5: // tba | |
77f193da BS |
3261 | tcg_gen_st_tl(cpu_dst, cpu_env, |
3262 | offsetof(CPUSPARCState, tbr)); | |
0f8a249a BS |
3263 | break; |
3264 | case 6: // pstate | |
6ae20372 BS |
3265 | save_state(dc, cpu_cond); |
3266 | tcg_gen_helper_0_1(helper_wrpstate, cpu_dst); | |
ded3ab80 | 3267 | gen_op_next_insn(); |
57fec1fe | 3268 | tcg_gen_exit_tb(0); |
ded3ab80 | 3269 | dc->is_br = 1; |
0f8a249a BS |
3270 | break; |
3271 | case 7: // tl | |
6ae20372 | 3272 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
77f193da BS |
3273 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3274 | offsetof(CPUSPARCState, tl)); | |
0f8a249a BS |
3275 | break; |
3276 | case 8: // pil | |
6ae20372 | 3277 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
77f193da BS |
3278 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3279 | offsetof(CPUSPARCState, | |
3280 | psrpil)); | |
0f8a249a BS |
3281 | break; |
3282 | case 9: // cwp | |
6ae20372 | 3283 | tcg_gen_helper_0_1(helper_wrcwp, cpu_dst); |
0f8a249a BS |
3284 | break; |
3285 | case 10: // cansave | |
6ae20372 | 3286 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
77f193da BS |
3287 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3288 | offsetof(CPUSPARCState, | |
3289 | cansave)); | |
0f8a249a BS |
3290 | break; |
3291 | case 11: // canrestore | |
6ae20372 | 3292 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
77f193da BS |
3293 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3294 | offsetof(CPUSPARCState, | |
3295 | canrestore)); | |
0f8a249a BS |
3296 | break; |
3297 | case 12: // cleanwin | |
6ae20372 | 3298 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
77f193da BS |
3299 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3300 | offsetof(CPUSPARCState, | |
3301 | cleanwin)); | |
0f8a249a BS |
3302 | break; |
3303 | case 13: // otherwin | |
6ae20372 | 3304 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
77f193da BS |
3305 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3306 | offsetof(CPUSPARCState, | |
3307 | otherwin)); | |
0f8a249a BS |
3308 | break; |
3309 | case 14: // wstate | |
6ae20372 | 3310 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
77f193da BS |
3311 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3312 | offsetof(CPUSPARCState, | |
3313 | wstate)); | |
0f8a249a | 3314 | break; |
e9ebed4d | 3315 | case 16: // UA2005 gl |
6ae20372 | 3316 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
77f193da BS |
3317 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3318 | offsetof(CPUSPARCState, gl)); | |
e9ebed4d BS |
3319 | break; |
3320 | case 26: // UA2005 strand status | |
3321 | if (!hypervisor(dc)) | |
3322 | goto priv_insn; | |
6ae20372 | 3323 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
77f193da BS |
3324 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3325 | offsetof(CPUSPARCState, ssr)); | |
e9ebed4d | 3326 | break; |
0f8a249a BS |
3327 | default: |
3328 | goto illegal_insn; | |
3329 | } | |
3475187d | 3330 | #else |
77f193da BS |
3331 | tcg_gen_andi_tl(cpu_dst, cpu_dst, |
3332 | ((1 << NWINDOWS) - 1)); | |
6ae20372 | 3333 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
77f193da BS |
3334 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3335 | offsetof(CPUSPARCState, wim)); | |
3475187d | 3336 | #endif |
e8af50a3 FB |
3337 | } |
3338 | break; | |
e9ebed4d | 3339 | case 0x33: /* wrtbr, UA2005 wrhpr */ |
e8af50a3 | 3340 | { |
e9ebed4d | 3341 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
3342 | if (!supervisor(dc)) |
3343 | goto priv_insn; | |
6ae20372 | 3344 | tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2); |
77f193da BS |
3345 | tcg_gen_st_tl(cpu_dst, cpu_env, |
3346 | offsetof(CPUSPARCState, tbr)); | |
e9ebed4d BS |
3347 | #else |
3348 | if (!hypervisor(dc)) | |
3349 | goto priv_insn; | |
6ae20372 | 3350 | tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2); |
e9ebed4d BS |
3351 | switch (rd) { |
3352 | case 0: // hpstate | |
3353 | // XXX gen_op_wrhpstate(); | |
6ae20372 | 3354 | save_state(dc, cpu_cond); |
e9ebed4d | 3355 | gen_op_next_insn(); |
57fec1fe | 3356 | tcg_gen_exit_tb(0); |
e9ebed4d BS |
3357 | dc->is_br = 1; |
3358 | break; | |
3359 | case 1: // htstate | |
3360 | // XXX gen_op_wrhtstate(); | |
3361 | break; | |
3362 | case 3: // hintp | |
6ae20372 | 3363 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
77f193da BS |
3364 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3365 | offsetof(CPUSPARCState, hintp)); | |
e9ebed4d BS |
3366 | break; |
3367 | case 5: // htba | |
6ae20372 | 3368 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
77f193da BS |
3369 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3370 | offsetof(CPUSPARCState, htba)); | |
e9ebed4d BS |
3371 | break; |
3372 | case 31: // hstick_cmpr | |
ccd4a219 BS |
3373 | { |
3374 | TCGv r_tickptr; | |
3375 | ||
77f193da BS |
3376 | tcg_gen_st_tl(cpu_dst, cpu_env, |
3377 | offsetof(CPUSPARCState, | |
3378 | hstick_cmpr)); | |
ccd4a219 BS |
3379 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3380 | tcg_gen_ld_ptr(r_tickptr, cpu_env, | |
3381 | offsetof(CPUState, hstick)); | |
3382 | tcg_gen_helper_0_2(helper_tick_set_limit, | |
6ae20372 | 3383 | r_tickptr, cpu_dst); |
ccd4a219 | 3384 | } |
e9ebed4d BS |
3385 | break; |
3386 | case 6: // hver readonly | |
3387 | default: | |
3388 | goto illegal_insn; | |
3389 | } | |
3390 | #endif | |
e8af50a3 FB |
3391 | } |
3392 | break; | |
3393 | #endif | |
3475187d | 3394 | #ifdef TARGET_SPARC64 |
0f8a249a BS |
3395 | case 0x2c: /* V9 movcc */ |
3396 | { | |
3397 | int cc = GET_FIELD_SP(insn, 11, 12); | |
3398 | int cond = GET_FIELD_SP(insn, 14, 17); | |
748b9d8e | 3399 | TCGv r_cond; |
00f219bf BS |
3400 | int l1; |
3401 | ||
748b9d8e | 3402 | r_cond = tcg_temp_new(TCG_TYPE_TL); |
0f8a249a BS |
3403 | if (insn & (1 << 18)) { |
3404 | if (cc == 0) | |
748b9d8e | 3405 | gen_cond(r_cond, 0, cond); |
0f8a249a | 3406 | else if (cc == 2) |
748b9d8e | 3407 | gen_cond(r_cond, 1, cond); |
0f8a249a BS |
3408 | else |
3409 | goto illegal_insn; | |
3410 | } else { | |
748b9d8e | 3411 | gen_fcond(r_cond, cc, cond); |
0f8a249a | 3412 | } |
00f219bf BS |
3413 | |
3414 | l1 = gen_new_label(); | |
3415 | ||
cb63669a | 3416 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1); |
00f219bf BS |
3417 | if (IS_IMM) { /* immediate */ |
3418 | rs2 = GET_FIELD_SPs(insn, 0, 10); | |
9c6c6662 | 3419 | gen_movl_TN_reg(rd, tcg_const_tl((int)rs2)); |
00f219bf BS |
3420 | } else { |
3421 | rs2 = GET_FIELD_SP(insn, 0, 4); | |
9c6c6662 BS |
3422 | gen_movl_reg_TN(rs2, cpu_tmp0); |
3423 | gen_movl_TN_reg(rd, cpu_tmp0); | |
00f219bf | 3424 | } |
00f219bf | 3425 | gen_set_label(l1); |
0f8a249a BS |
3426 | break; |
3427 | } | |
3428 | case 0x2d: /* V9 sdivx */ | |
6ae20372 BS |
3429 | gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2); |
3430 | gen_movl_TN_reg(rd, cpu_dst); | |
0f8a249a BS |
3431 | break; |
3432 | case 0x2e: /* V9 popc */ | |
3433 | { | |
a49d9390 | 3434 | cpu_src2 = get_src2(insn, cpu_src2); |
6ae20372 BS |
3435 | tcg_gen_helper_1_1(helper_popc, cpu_dst, |
3436 | cpu_src2); | |
3437 | gen_movl_TN_reg(rd, cpu_dst); | |
0f8a249a BS |
3438 | } |
3439 | case 0x2f: /* V9 movr */ | |
3440 | { | |
3441 | int cond = GET_FIELD_SP(insn, 10, 12); | |
00f219bf BS |
3442 | int l1; |
3443 | ||
9322a4bf | 3444 | cpu_src1 = get_src1(insn, cpu_src1); |
00f219bf BS |
3445 | |
3446 | l1 = gen_new_label(); | |
3447 | ||
cb63669a PB |
3448 | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], |
3449 | cpu_src1, 0, l1); | |
0f8a249a BS |
3450 | if (IS_IMM) { /* immediate */ |
3451 | rs2 = GET_FIELD_SPs(insn, 0, 9); | |
9c6c6662 | 3452 | gen_movl_TN_reg(rd, tcg_const_tl((int)rs2)); |
00f219bf | 3453 | } else { |
0f8a249a | 3454 | rs2 = GET_FIELD_SP(insn, 0, 4); |
9c6c6662 BS |
3455 | gen_movl_reg_TN(rs2, cpu_tmp0); |
3456 | gen_movl_TN_reg(rd, cpu_tmp0); | |
0f8a249a | 3457 | } |
00f219bf | 3458 | gen_set_label(l1); |
0f8a249a BS |
3459 | break; |
3460 | } | |
3461 | #endif | |
3462 | default: | |
3463 | goto illegal_insn; | |
3464 | } | |
3465 | } | |
3299908c BS |
3466 | } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ |
3467 | #ifdef TARGET_SPARC64 | |
3468 | int opf = GET_FIELD_SP(insn, 5, 13); | |
3469 | rs1 = GET_FIELD(insn, 13, 17); | |
3470 | rs2 = GET_FIELD(insn, 27, 31); | |
6ae20372 | 3471 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
e9ebed4d | 3472 | goto jmp_insn; |
3299908c BS |
3473 | |
3474 | switch (opf) { | |
e9ebed4d BS |
3475 | case 0x000: /* VIS I edge8cc */ |
3476 | case 0x001: /* VIS II edge8n */ | |
3477 | case 0x002: /* VIS I edge8lcc */ | |
3478 | case 0x003: /* VIS II edge8ln */ | |
3479 | case 0x004: /* VIS I edge16cc */ | |
3480 | case 0x005: /* VIS II edge16n */ | |
3481 | case 0x006: /* VIS I edge16lcc */ | |
3482 | case 0x007: /* VIS II edge16ln */ | |
3483 | case 0x008: /* VIS I edge32cc */ | |
3484 | case 0x009: /* VIS II edge32n */ | |
3485 | case 0x00a: /* VIS I edge32lcc */ | |
3486 | case 0x00b: /* VIS II edge32ln */ | |
3487 | // XXX | |
3488 | goto illegal_insn; | |
3489 | case 0x010: /* VIS I array8 */ | |
64a88d5d | 3490 | CHECK_FPU_FEATURE(dc, VIS1); |
9322a4bf | 3491 | cpu_src1 = get_src1(insn, cpu_src1); |
6ae20372 BS |
3492 | gen_movl_reg_TN(rs2, cpu_src2); |
3493 | tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1, | |
3494 | cpu_src2); | |
3495 | gen_movl_TN_reg(rd, cpu_dst); | |
e9ebed4d BS |
3496 | break; |
3497 | case 0x012: /* VIS I array16 */ | |
64a88d5d | 3498 | CHECK_FPU_FEATURE(dc, VIS1); |
9322a4bf | 3499 | cpu_src1 = get_src1(insn, cpu_src1); |
6ae20372 BS |
3500 | gen_movl_reg_TN(rs2, cpu_src2); |
3501 | tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1, | |
3502 | cpu_src2); | |
3503 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 1); | |
3504 | gen_movl_TN_reg(rd, cpu_dst); | |
e9ebed4d BS |
3505 | break; |
3506 | case 0x014: /* VIS I array32 */ | |
64a88d5d | 3507 | CHECK_FPU_FEATURE(dc, VIS1); |
9322a4bf | 3508 | cpu_src1 = get_src1(insn, cpu_src1); |
6ae20372 BS |
3509 | gen_movl_reg_TN(rs2, cpu_src2); |
3510 | tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1, | |
3511 | cpu_src2); | |
3512 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 2); | |
3513 | gen_movl_TN_reg(rd, cpu_dst); | |
e9ebed4d | 3514 | break; |
3299908c | 3515 | case 0x018: /* VIS I alignaddr */ |
64a88d5d | 3516 | CHECK_FPU_FEATURE(dc, VIS1); |
9322a4bf | 3517 | cpu_src1 = get_src1(insn, cpu_src1); |
6ae20372 BS |
3518 | gen_movl_reg_TN(rs2, cpu_src2); |
3519 | tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1, | |
3520 | cpu_src2); | |
3521 | gen_movl_TN_reg(rd, cpu_dst); | |
3299908c | 3522 | break; |
e9ebed4d | 3523 | case 0x019: /* VIS II bmask */ |
3299908c | 3524 | case 0x01a: /* VIS I alignaddrl */ |
3299908c | 3525 | // XXX |
e9ebed4d BS |
3526 | goto illegal_insn; |
3527 | case 0x020: /* VIS I fcmple16 */ | |
64a88d5d | 3528 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3529 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3530 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3531 | tcg_gen_helper_0_0(helper_fcmple16); |
2382dc6b | 3532 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3533 | break; |
3534 | case 0x022: /* VIS I fcmpne16 */ | |
64a88d5d | 3535 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3536 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3537 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3538 | tcg_gen_helper_0_0(helper_fcmpne16); |
2382dc6b | 3539 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3299908c | 3540 | break; |
e9ebed4d | 3541 | case 0x024: /* VIS I fcmple32 */ |
64a88d5d | 3542 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3543 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3544 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3545 | tcg_gen_helper_0_0(helper_fcmple32); |
2382dc6b | 3546 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3547 | break; |
3548 | case 0x026: /* VIS I fcmpne32 */ | |
64a88d5d | 3549 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3550 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3551 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3552 | tcg_gen_helper_0_0(helper_fcmpne32); |
2382dc6b | 3553 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3554 | break; |
3555 | case 0x028: /* VIS I fcmpgt16 */ | |
64a88d5d | 3556 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3557 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3558 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3559 | tcg_gen_helper_0_0(helper_fcmpgt16); |
2382dc6b | 3560 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3561 | break; |
3562 | case 0x02a: /* VIS I fcmpeq16 */ | |
64a88d5d | 3563 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3564 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3565 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3566 | tcg_gen_helper_0_0(helper_fcmpeq16); |
2382dc6b | 3567 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3568 | break; |
3569 | case 0x02c: /* VIS I fcmpgt32 */ | |
64a88d5d | 3570 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3571 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3572 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3573 | tcg_gen_helper_0_0(helper_fcmpgt32); |
2382dc6b | 3574 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3575 | break; |
3576 | case 0x02e: /* VIS I fcmpeq32 */ | |
64a88d5d | 3577 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3578 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3579 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3580 | tcg_gen_helper_0_0(helper_fcmpeq32); |
2382dc6b | 3581 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3582 | break; |
3583 | case 0x031: /* VIS I fmul8x16 */ | |
64a88d5d | 3584 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3585 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3586 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3587 | tcg_gen_helper_0_0(helper_fmul8x16); |
2382dc6b | 3588 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3589 | break; |
3590 | case 0x033: /* VIS I fmul8x16au */ | |
64a88d5d | 3591 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3592 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3593 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3594 | tcg_gen_helper_0_0(helper_fmul8x16au); |
2382dc6b | 3595 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3596 | break; |
3597 | case 0x035: /* VIS I fmul8x16al */ | |
64a88d5d | 3598 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3599 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3600 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3601 | tcg_gen_helper_0_0(helper_fmul8x16al); |
2382dc6b | 3602 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3603 | break; |
3604 | case 0x036: /* VIS I fmul8sux16 */ | |
64a88d5d | 3605 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3606 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3607 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3608 | tcg_gen_helper_0_0(helper_fmul8sux16); |
2382dc6b | 3609 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3610 | break; |
3611 | case 0x037: /* VIS I fmul8ulx16 */ | |
64a88d5d | 3612 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3613 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3614 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3615 | tcg_gen_helper_0_0(helper_fmul8ulx16); |
2382dc6b | 3616 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3617 | break; |
3618 | case 0x038: /* VIS I fmuld8sux16 */ | |
64a88d5d | 3619 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3620 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3621 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3622 | tcg_gen_helper_0_0(helper_fmuld8sux16); |
2382dc6b | 3623 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3624 | break; |
3625 | case 0x039: /* VIS I fmuld8ulx16 */ | |
64a88d5d | 3626 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3627 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3628 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3629 | tcg_gen_helper_0_0(helper_fmuld8ulx16); |
2382dc6b | 3630 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3631 | break; |
3632 | case 0x03a: /* VIS I fpack32 */ | |
3633 | case 0x03b: /* VIS I fpack16 */ | |
3634 | case 0x03d: /* VIS I fpackfix */ | |
3635 | case 0x03e: /* VIS I pdist */ | |
3636 | // XXX | |
3637 | goto illegal_insn; | |
3299908c | 3638 | case 0x048: /* VIS I faligndata */ |
64a88d5d | 3639 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3640 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3641 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3642 | tcg_gen_helper_0_0(helper_faligndata); |
2382dc6b | 3643 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3299908c | 3644 | break; |
e9ebed4d | 3645 | case 0x04b: /* VIS I fpmerge */ |
64a88d5d | 3646 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3647 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3648 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3649 | tcg_gen_helper_0_0(helper_fpmerge); |
2382dc6b | 3650 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3651 | break; |
3652 | case 0x04c: /* VIS II bshuffle */ | |
3653 | // XXX | |
3654 | goto illegal_insn; | |
3655 | case 0x04d: /* VIS I fexpand */ | |
64a88d5d | 3656 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3657 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3658 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3659 | tcg_gen_helper_0_0(helper_fexpand); |
2382dc6b | 3660 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3661 | break; |
3662 | case 0x050: /* VIS I fpadd16 */ | |
64a88d5d | 3663 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3664 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3665 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3666 | tcg_gen_helper_0_0(helper_fpadd16); |
2382dc6b | 3667 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3668 | break; |
3669 | case 0x051: /* VIS I fpadd16s */ | |
64a88d5d | 3670 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3671 | gen_op_load_fpr_FT0(rs1); |
3672 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3673 | tcg_gen_helper_0_0(helper_fpadd16s); |
e9ebed4d BS |
3674 | gen_op_store_FT0_fpr(rd); |
3675 | break; | |
3676 | case 0x052: /* VIS I fpadd32 */ | |
64a88d5d | 3677 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3678 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3679 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3680 | tcg_gen_helper_0_0(helper_fpadd32); |
2382dc6b | 3681 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3682 | break; |
3683 | case 0x053: /* VIS I fpadd32s */ | |
64a88d5d | 3684 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3685 | gen_op_load_fpr_FT0(rs1); |
3686 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3687 | tcg_gen_helper_0_0(helper_fpadd32s); |
e9ebed4d BS |
3688 | gen_op_store_FT0_fpr(rd); |
3689 | break; | |
3690 | case 0x054: /* VIS I fpsub16 */ | |
64a88d5d | 3691 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3692 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3693 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3694 | tcg_gen_helper_0_0(helper_fpsub16); |
2382dc6b | 3695 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3696 | break; |
3697 | case 0x055: /* VIS I fpsub16s */ | |
64a88d5d | 3698 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3699 | gen_op_load_fpr_FT0(rs1); |
3700 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3701 | tcg_gen_helper_0_0(helper_fpsub16s); |
e9ebed4d BS |
3702 | gen_op_store_FT0_fpr(rd); |
3703 | break; | |
3704 | case 0x056: /* VIS I fpsub32 */ | |
64a88d5d | 3705 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3706 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3707 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3708 | tcg_gen_helper_0_0(helper_fpadd32); |
2382dc6b | 3709 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3710 | break; |
3711 | case 0x057: /* VIS I fpsub32s */ | |
64a88d5d | 3712 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3713 | gen_op_load_fpr_FT0(rs1); |
3714 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3715 | tcg_gen_helper_0_0(helper_fpsub32s); |
e9ebed4d BS |
3716 | gen_op_store_FT0_fpr(rd); |
3717 | break; | |
3299908c | 3718 | case 0x060: /* VIS I fzero */ |
64a88d5d | 3719 | CHECK_FPU_FEATURE(dc, VIS1); |
44e7757c | 3720 | tcg_gen_helper_0_0(helper_movl_DT0_0); |
2382dc6b | 3721 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3299908c BS |
3722 | break; |
3723 | case 0x061: /* VIS I fzeros */ | |
64a88d5d | 3724 | CHECK_FPU_FEATURE(dc, VIS1); |
44e7757c | 3725 | tcg_gen_helper_0_0(helper_movl_FT0_0); |
3299908c BS |
3726 | gen_op_store_FT0_fpr(rd); |
3727 | break; | |
e9ebed4d | 3728 | case 0x062: /* VIS I fnor */ |
64a88d5d | 3729 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3730 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3731 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3732 | tcg_gen_helper_0_0(helper_fnor); |
2382dc6b | 3733 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3734 | break; |
3735 | case 0x063: /* VIS I fnors */ | |
64a88d5d | 3736 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3737 | gen_op_load_fpr_FT0(rs1); |
3738 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3739 | tcg_gen_helper_0_0(helper_fnors); |
e9ebed4d BS |
3740 | gen_op_store_FT0_fpr(rd); |
3741 | break; | |
3742 | case 0x064: /* VIS I fandnot2 */ | |
64a88d5d | 3743 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3744 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
3745 | gen_op_load_fpr_DT0(DFPREG(rs2)); | |
44e7757c | 3746 | tcg_gen_helper_0_0(helper_fandnot); |
2382dc6b | 3747 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3748 | break; |
3749 | case 0x065: /* VIS I fandnot2s */ | |
64a88d5d | 3750 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3751 | gen_op_load_fpr_FT1(rs1); |
3752 | gen_op_load_fpr_FT0(rs2); | |
44e7757c | 3753 | tcg_gen_helper_0_0(helper_fandnots); |
e9ebed4d BS |
3754 | gen_op_store_FT0_fpr(rd); |
3755 | break; | |
3756 | case 0x066: /* VIS I fnot2 */ | |
64a88d5d | 3757 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b | 3758 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
44e7757c | 3759 | tcg_gen_helper_0_0(helper_fnot); |
2382dc6b | 3760 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3761 | break; |
3762 | case 0x067: /* VIS I fnot2s */ | |
64a88d5d | 3763 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d | 3764 | gen_op_load_fpr_FT1(rs2); |
44e7757c | 3765 | tcg_gen_helper_0_0(helper_fnot); |
e9ebed4d BS |
3766 | gen_op_store_FT0_fpr(rd); |
3767 | break; | |
3768 | case 0x068: /* VIS I fandnot1 */ | |
64a88d5d | 3769 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3770 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3771 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3772 | tcg_gen_helper_0_0(helper_fandnot); |
2382dc6b | 3773 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3774 | break; |
3775 | case 0x069: /* VIS I fandnot1s */ | |
64a88d5d | 3776 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3777 | gen_op_load_fpr_FT0(rs1); |
3778 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3779 | tcg_gen_helper_0_0(helper_fandnots); |
e9ebed4d BS |
3780 | gen_op_store_FT0_fpr(rd); |
3781 | break; | |
3782 | case 0x06a: /* VIS I fnot1 */ | |
64a88d5d | 3783 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b | 3784 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
44e7757c | 3785 | tcg_gen_helper_0_0(helper_fnot); |
2382dc6b | 3786 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3787 | break; |
3788 | case 0x06b: /* VIS I fnot1s */ | |
64a88d5d | 3789 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d | 3790 | gen_op_load_fpr_FT1(rs1); |
44e7757c | 3791 | tcg_gen_helper_0_0(helper_fnot); |
e9ebed4d BS |
3792 | gen_op_store_FT0_fpr(rd); |
3793 | break; | |
3794 | case 0x06c: /* VIS I fxor */ | |
64a88d5d | 3795 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3796 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3797 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3798 | tcg_gen_helper_0_0(helper_fxor); |
2382dc6b | 3799 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3800 | break; |
3801 | case 0x06d: /* VIS I fxors */ | |
64a88d5d | 3802 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3803 | gen_op_load_fpr_FT0(rs1); |
3804 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3805 | tcg_gen_helper_0_0(helper_fxors); |
e9ebed4d BS |
3806 | gen_op_store_FT0_fpr(rd); |
3807 | break; | |
3808 | case 0x06e: /* VIS I fnand */ | |
64a88d5d | 3809 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3810 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3811 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3812 | tcg_gen_helper_0_0(helper_fnand); |
2382dc6b | 3813 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3814 | break; |
3815 | case 0x06f: /* VIS I fnands */ | |
64a88d5d | 3816 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3817 | gen_op_load_fpr_FT0(rs1); |
3818 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3819 | tcg_gen_helper_0_0(helper_fnands); |
e9ebed4d BS |
3820 | gen_op_store_FT0_fpr(rd); |
3821 | break; | |
3822 | case 0x070: /* VIS I fand */ | |
64a88d5d | 3823 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3824 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3825 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3826 | tcg_gen_helper_0_0(helper_fand); |
2382dc6b | 3827 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3828 | break; |
3829 | case 0x071: /* VIS I fands */ | |
64a88d5d | 3830 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3831 | gen_op_load_fpr_FT0(rs1); |
3832 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3833 | tcg_gen_helper_0_0(helper_fands); |
e9ebed4d BS |
3834 | gen_op_store_FT0_fpr(rd); |
3835 | break; | |
3836 | case 0x072: /* VIS I fxnor */ | |
64a88d5d | 3837 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3838 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3839 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3840 | tcg_gen_helper_0_0(helper_fxnor); |
2382dc6b | 3841 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3842 | break; |
3843 | case 0x073: /* VIS I fxnors */ | |
64a88d5d | 3844 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3845 | gen_op_load_fpr_FT0(rs1); |
3846 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3847 | tcg_gen_helper_0_0(helper_fxnors); |
e9ebed4d BS |
3848 | gen_op_store_FT0_fpr(rd); |
3849 | break; | |
3299908c | 3850 | case 0x074: /* VIS I fsrc1 */ |
64a88d5d | 3851 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3852 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3853 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
3299908c BS |
3854 | break; |
3855 | case 0x075: /* VIS I fsrc1s */ | |
64a88d5d | 3856 | CHECK_FPU_FEATURE(dc, VIS1); |
3299908c BS |
3857 | gen_op_load_fpr_FT0(rs1); |
3858 | gen_op_store_FT0_fpr(rd); | |
3859 | break; | |
e9ebed4d | 3860 | case 0x076: /* VIS I fornot2 */ |
64a88d5d | 3861 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3862 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
3863 | gen_op_load_fpr_DT0(DFPREG(rs2)); | |
44e7757c | 3864 | tcg_gen_helper_0_0(helper_fornot); |
2382dc6b | 3865 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3866 | break; |
3867 | case 0x077: /* VIS I fornot2s */ | |
64a88d5d | 3868 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3869 | gen_op_load_fpr_FT1(rs1); |
3870 | gen_op_load_fpr_FT0(rs2); | |
44e7757c | 3871 | tcg_gen_helper_0_0(helper_fornots); |
e9ebed4d BS |
3872 | gen_op_store_FT0_fpr(rd); |
3873 | break; | |
3299908c | 3874 | case 0x078: /* VIS I fsrc2 */ |
64a88d5d | 3875 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3876 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
3877 | gen_op_store_DT0_fpr(DFPREG(rd)); | |
3299908c BS |
3878 | break; |
3879 | case 0x079: /* VIS I fsrc2s */ | |
64a88d5d | 3880 | CHECK_FPU_FEATURE(dc, VIS1); |
3299908c BS |
3881 | gen_op_load_fpr_FT0(rs2); |
3882 | gen_op_store_FT0_fpr(rd); | |
3883 | break; | |
e9ebed4d | 3884 | case 0x07a: /* VIS I fornot1 */ |
64a88d5d | 3885 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3886 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3887 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3888 | tcg_gen_helper_0_0(helper_fornot); |
2382dc6b | 3889 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3890 | break; |
3891 | case 0x07b: /* VIS I fornot1s */ | |
64a88d5d | 3892 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3893 | gen_op_load_fpr_FT0(rs1); |
3894 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3895 | tcg_gen_helper_0_0(helper_fornots); |
e9ebed4d BS |
3896 | gen_op_store_FT0_fpr(rd); |
3897 | break; | |
3898 | case 0x07c: /* VIS I for */ | |
64a88d5d | 3899 | CHECK_FPU_FEATURE(dc, VIS1); |
2382dc6b BS |
3900 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3901 | gen_op_load_fpr_DT1(DFPREG(rs2)); | |
44e7757c | 3902 | tcg_gen_helper_0_0(helper_for); |
2382dc6b | 3903 | gen_op_store_DT0_fpr(DFPREG(rd)); |
e9ebed4d BS |
3904 | break; |
3905 | case 0x07d: /* VIS I fors */ | |
64a88d5d | 3906 | CHECK_FPU_FEATURE(dc, VIS1); |
e9ebed4d BS |
3907 | gen_op_load_fpr_FT0(rs1); |
3908 | gen_op_load_fpr_FT1(rs2); | |
44e7757c | 3909 | tcg_gen_helper_0_0(helper_fors); |
e9ebed4d BS |
3910 | gen_op_store_FT0_fpr(rd); |
3911 | break; | |
3299908c | 3912 | case 0x07e: /* VIS I fone */ |
64a88d5d | 3913 | CHECK_FPU_FEATURE(dc, VIS1); |
44e7757c | 3914 | tcg_gen_helper_0_0(helper_movl_DT0_1); |
2382dc6b | 3915 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3299908c BS |
3916 | break; |
3917 | case 0x07f: /* VIS I fones */ | |
64a88d5d | 3918 | CHECK_FPU_FEATURE(dc, VIS1); |
44e7757c | 3919 | tcg_gen_helper_0_0(helper_movl_FT0_1); |
3299908c BS |
3920 | gen_op_store_FT0_fpr(rd); |
3921 | break; | |
e9ebed4d BS |
3922 | case 0x080: /* VIS I shutdown */ |
3923 | case 0x081: /* VIS II siam */ | |
3924 | // XXX | |
3925 | goto illegal_insn; | |
3299908c BS |
3926 | default: |
3927 | goto illegal_insn; | |
3928 | } | |
3929 | #else | |
0f8a249a | 3930 | goto ncp_insn; |
3299908c BS |
3931 | #endif |
3932 | } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ | |
fcc72045 | 3933 | #ifdef TARGET_SPARC64 |
0f8a249a | 3934 | goto illegal_insn; |
fcc72045 | 3935 | #else |
0f8a249a | 3936 | goto ncp_insn; |
fcc72045 | 3937 | #endif |
3475187d | 3938 | #ifdef TARGET_SPARC64 |
0f8a249a | 3939 | } else if (xop == 0x39) { /* V9 return */ |
6ae20372 | 3940 | save_state(dc, cpu_cond); |
9322a4bf | 3941 | cpu_src1 = get_src1(insn, cpu_src1); |
0f8a249a BS |
3942 | if (IS_IMM) { /* immediate */ |
3943 | rs2 = GET_FIELDs(insn, 19, 31); | |
6ae20372 | 3944 | tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2); |
0f8a249a | 3945 | } else { /* register */ |
3475187d | 3946 | rs2 = GET_FIELD(insn, 27, 31); |
0f8a249a | 3947 | if (rs2) { |
6ae20372 BS |
3948 | gen_movl_reg_TN(rs2, cpu_src2); |
3949 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); | |
6f551262 BS |
3950 | } else |
3951 | tcg_gen_mov_tl(cpu_dst, cpu_src1); | |
3475187d | 3952 | } |
72a9747b | 3953 | tcg_gen_helper_0_0(helper_restore); |
6ae20372 | 3954 | gen_mov_pc_npc(dc, cpu_cond); |
77f193da BS |
3955 | tcg_gen_helper_0_2(helper_check_align, cpu_dst, |
3956 | tcg_const_i32(3)); | |
6ae20372 | 3957 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
0f8a249a BS |
3958 | dc->npc = DYNAMIC_PC; |
3959 | goto jmp_insn; | |
3475187d | 3960 | #endif |
0f8a249a | 3961 | } else { |
9322a4bf | 3962 | cpu_src1 = get_src1(insn, cpu_src1); |
0f8a249a BS |
3963 | if (IS_IMM) { /* immediate */ |
3964 | rs2 = GET_FIELDs(insn, 19, 31); | |
6ae20372 | 3965 | tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2); |
0f8a249a | 3966 | } else { /* register */ |
e80cfcfc | 3967 | rs2 = GET_FIELD(insn, 27, 31); |
0f8a249a | 3968 | if (rs2) { |
6ae20372 BS |
3969 | gen_movl_reg_TN(rs2, cpu_src2); |
3970 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); | |
6f551262 BS |
3971 | } else |
3972 | tcg_gen_mov_tl(cpu_dst, cpu_src1); | |
cf495bcf | 3973 | } |
0f8a249a BS |
3974 | switch (xop) { |
3975 | case 0x38: /* jmpl */ | |
3976 | { | |
9c6c6662 | 3977 | gen_movl_TN_reg(rd, tcg_const_tl(dc->pc)); |
6ae20372 | 3978 | gen_mov_pc_npc(dc, cpu_cond); |
77f193da BS |
3979 | tcg_gen_helper_0_2(helper_check_align, cpu_dst, |
3980 | tcg_const_i32(3)); | |
6ae20372 | 3981 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
0f8a249a BS |
3982 | dc->npc = DYNAMIC_PC; |
3983 | } | |
3984 | goto jmp_insn; | |
3475187d | 3985 | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) |
0f8a249a BS |
3986 | case 0x39: /* rett, V9 return */ |
3987 | { | |
3988 | if (!supervisor(dc)) | |
3989 | goto priv_insn; | |
6ae20372 | 3990 | gen_mov_pc_npc(dc, cpu_cond); |
77f193da BS |
3991 | tcg_gen_helper_0_2(helper_check_align, cpu_dst, |
3992 | tcg_const_i32(3)); | |
6ae20372 | 3993 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
0f8a249a | 3994 | dc->npc = DYNAMIC_PC; |
1a2fb1c0 | 3995 | tcg_gen_helper_0_0(helper_rett); |
0f8a249a BS |
3996 | } |
3997 | goto jmp_insn; | |
3998 | #endif | |
3999 | case 0x3b: /* flush */ | |
64a88d5d BS |
4000 | if (!((dc)->features & CPU_FEATURE_FLUSH)) |
4001 | goto unimp_flush; | |
6ae20372 | 4002 | tcg_gen_helper_0_1(helper_flush, cpu_dst); |
0f8a249a BS |
4003 | break; |
4004 | case 0x3c: /* save */ | |
6ae20372 | 4005 | save_state(dc, cpu_cond); |
72a9747b | 4006 | tcg_gen_helper_0_0(helper_save); |
6ae20372 | 4007 | gen_movl_TN_reg(rd, cpu_dst); |
0f8a249a BS |
4008 | break; |
4009 | case 0x3d: /* restore */ | |
6ae20372 | 4010 | save_state(dc, cpu_cond); |
72a9747b | 4011 | tcg_gen_helper_0_0(helper_restore); |
6ae20372 | 4012 | gen_movl_TN_reg(rd, cpu_dst); |
0f8a249a | 4013 | break; |
3475187d | 4014 | #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64) |
0f8a249a BS |
4015 | case 0x3e: /* V9 done/retry */ |
4016 | { | |
4017 | switch (rd) { | |
4018 | case 0: | |
4019 | if (!supervisor(dc)) | |
4020 | goto priv_insn; | |
4021 | dc->npc = DYNAMIC_PC; | |
4022 | dc->pc = DYNAMIC_PC; | |
1a2fb1c0 | 4023 | tcg_gen_helper_0_0(helper_done); |
0f8a249a BS |
4024 | goto jmp_insn; |
4025 | case 1: | |
4026 | if (!supervisor(dc)) | |
4027 | goto priv_insn; | |
4028 | dc->npc = DYNAMIC_PC; | |
4029 | dc->pc = DYNAMIC_PC; | |
1a2fb1c0 | 4030 | tcg_gen_helper_0_0(helper_retry); |
0f8a249a BS |
4031 | goto jmp_insn; |
4032 | default: | |
4033 | goto illegal_insn; | |
4034 | } | |
4035 | } | |
4036 | break; | |
4037 | #endif | |
4038 | default: | |
4039 | goto illegal_insn; | |
4040 | } | |
cf495bcf | 4041 | } |
0f8a249a BS |
4042 | break; |
4043 | } | |
4044 | break; | |
4045 | case 3: /* load/store instructions */ | |
4046 | { | |
4047 | unsigned int xop = GET_FIELD(insn, 7, 12); | |
9322a4bf | 4048 | |
9322a4bf | 4049 | cpu_src1 = get_src1(insn, cpu_src1); |
81ad8ba2 BS |
4050 | if (xop == 0x3c || xop == 0x3e) |
4051 | { | |
4052 | rs2 = GET_FIELD(insn, 27, 31); | |
6ae20372 | 4053 | gen_movl_reg_TN(rs2, cpu_src2); |
81ad8ba2 BS |
4054 | } |
4055 | else if (IS_IMM) { /* immediate */ | |
0f8a249a | 4056 | rs2 = GET_FIELDs(insn, 19, 31); |
6ae20372 | 4057 | tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2); |
0f8a249a BS |
4058 | } else { /* register */ |
4059 | rs2 = GET_FIELD(insn, 27, 31); | |
0f8a249a | 4060 | if (rs2 != 0) { |
6ae20372 BS |
4061 | gen_movl_reg_TN(rs2, cpu_src2); |
4062 | tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2); | |
6f551262 BS |
4063 | } else |
4064 | tcg_gen_mov_tl(cpu_addr, cpu_src1); | |
0f8a249a | 4065 | } |
2f2ecb83 BS |
4066 | if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || |
4067 | (xop > 0x17 && xop <= 0x1d ) || | |
4068 | (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { | |
0f8a249a | 4069 | switch (xop) { |
1a2fb1c0 | 4070 | case 0x0: /* load unsigned word */ |
6ae20372 BS |
4071 | ABI32_MASK(cpu_addr); |
4072 | tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx); | |
0f8a249a BS |
4073 | break; |
4074 | case 0x1: /* load unsigned byte */ | |
6ae20372 BS |
4075 | ABI32_MASK(cpu_addr); |
4076 | tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx); | |
0f8a249a BS |
4077 | break; |
4078 | case 0x2: /* load unsigned halfword */ | |
6ae20372 BS |
4079 | ABI32_MASK(cpu_addr); |
4080 | tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx); | |
0f8a249a BS |
4081 | break; |
4082 | case 0x3: /* load double word */ | |
0f8a249a | 4083 | if (rd & 1) |
d4218d99 | 4084 | goto illegal_insn; |
1a2fb1c0 | 4085 | else { |
c2bc0e38 BS |
4086 | save_state(dc, cpu_cond); |
4087 | tcg_gen_helper_0_2(helper_check_align, cpu_addr, | |
4088 | tcg_const_i32(7)); // XXX remove | |
6ae20372 BS |
4089 | ABI32_MASK(cpu_addr); |
4090 | tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); | |
32b6c812 BS |
4091 | tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64); |
4092 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL); | |
4093 | gen_movl_TN_reg(rd + 1, cpu_tmp0); | |
8911f501 | 4094 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32); |
6ae20372 BS |
4095 | tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64); |
4096 | tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL); | |
1a2fb1c0 | 4097 | } |
0f8a249a BS |
4098 | break; |
4099 | case 0x9: /* load signed byte */ | |
6ae20372 BS |
4100 | ABI32_MASK(cpu_addr); |
4101 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); | |
0f8a249a BS |
4102 | break; |
4103 | case 0xa: /* load signed halfword */ | |
6ae20372 BS |
4104 | ABI32_MASK(cpu_addr); |
4105 | tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx); | |
0f8a249a BS |
4106 | break; |
4107 | case 0xd: /* ldstub -- XXX: should be atomically */ | |
6ae20372 BS |
4108 | ABI32_MASK(cpu_addr); |
4109 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); | |
77f193da BS |
4110 | tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_addr, |
4111 | dc->mem_idx); | |
0f8a249a | 4112 | break; |
77f193da BS |
4113 | case 0x0f: /* swap register with memory. Also |
4114 | atomically */ | |
64a88d5d | 4115 | CHECK_IU_FEATURE(dc, SWAP); |
6ae20372 BS |
4116 | gen_movl_reg_TN(rd, cpu_val); |
4117 | ABI32_MASK(cpu_addr); | |
4118 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); | |
4119 | tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); | |
4120 | tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32); | |
0f8a249a | 4121 | break; |
3475187d | 4122 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) |
0f8a249a | 4123 | case 0x10: /* load word alternate */ |
3475187d | 4124 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4125 | if (IS_IMM) |
4126 | goto illegal_insn; | |
4127 | if (!supervisor(dc)) | |
4128 | goto priv_insn; | |
6ea4a6c8 | 4129 | #endif |
c2bc0e38 | 4130 | save_state(dc, cpu_cond); |
6ae20372 | 4131 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0); |
0f8a249a BS |
4132 | break; |
4133 | case 0x11: /* load unsigned byte alternate */ | |
3475187d | 4134 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4135 | if (IS_IMM) |
4136 | goto illegal_insn; | |
4137 | if (!supervisor(dc)) | |
4138 | goto priv_insn; | |
4139 | #endif | |
c2bc0e38 | 4140 | save_state(dc, cpu_cond); |
6ae20372 | 4141 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0); |
0f8a249a BS |
4142 | break; |
4143 | case 0x12: /* load unsigned halfword alternate */ | |
3475187d | 4144 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4145 | if (IS_IMM) |
4146 | goto illegal_insn; | |
4147 | if (!supervisor(dc)) | |
4148 | goto priv_insn; | |
3475187d | 4149 | #endif |
c2bc0e38 | 4150 | save_state(dc, cpu_cond); |
6ae20372 | 4151 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0); |
0f8a249a BS |
4152 | break; |
4153 | case 0x13: /* load double word alternate */ | |
3475187d | 4154 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4155 | if (IS_IMM) |
4156 | goto illegal_insn; | |
4157 | if (!supervisor(dc)) | |
4158 | goto priv_insn; | |
3475187d | 4159 | #endif |
0f8a249a | 4160 | if (rd & 1) |
d4218d99 | 4161 | goto illegal_insn; |
c2bc0e38 | 4162 | save_state(dc, cpu_cond); |
6ae20372 | 4163 | gen_ldda_asi(cpu_tmp0, cpu_val, cpu_addr, insn); |
32b6c812 | 4164 | gen_movl_TN_reg(rd + 1, cpu_tmp0); |
0f8a249a BS |
4165 | break; |
4166 | case 0x19: /* load signed byte alternate */ | |
3475187d | 4167 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4168 | if (IS_IMM) |
4169 | goto illegal_insn; | |
4170 | if (!supervisor(dc)) | |
4171 | goto priv_insn; | |
4172 | #endif | |
c2bc0e38 | 4173 | save_state(dc, cpu_cond); |
6ae20372 | 4174 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1); |
0f8a249a BS |
4175 | break; |
4176 | case 0x1a: /* load signed halfword alternate */ | |
3475187d | 4177 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4178 | if (IS_IMM) |
4179 | goto illegal_insn; | |
4180 | if (!supervisor(dc)) | |
4181 | goto priv_insn; | |
3475187d | 4182 | #endif |
c2bc0e38 | 4183 | save_state(dc, cpu_cond); |
6ae20372 | 4184 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1); |
0f8a249a BS |
4185 | break; |
4186 | case 0x1d: /* ldstuba -- XXX: should be atomically */ | |
3475187d | 4187 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4188 | if (IS_IMM) |
4189 | goto illegal_insn; | |
4190 | if (!supervisor(dc)) | |
4191 | goto priv_insn; | |
4192 | #endif | |
c2bc0e38 | 4193 | save_state(dc, cpu_cond); |
6ae20372 | 4194 | gen_ldstub_asi(cpu_val, cpu_addr, insn); |
0f8a249a | 4195 | break; |
77f193da BS |
4196 | case 0x1f: /* swap reg with alt. memory. Also |
4197 | atomically */ | |
64a88d5d | 4198 | CHECK_IU_FEATURE(dc, SWAP); |
3475187d | 4199 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4200 | if (IS_IMM) |
4201 | goto illegal_insn; | |
4202 | if (!supervisor(dc)) | |
4203 | goto priv_insn; | |
6ea4a6c8 | 4204 | #endif |
c2bc0e38 | 4205 | save_state(dc, cpu_cond); |
6ae20372 BS |
4206 | gen_movl_reg_TN(rd, cpu_val); |
4207 | gen_swap_asi(cpu_val, cpu_addr, insn); | |
0f8a249a | 4208 | break; |
3475187d FB |
4209 | |
4210 | #ifndef TARGET_SPARC64 | |
0f8a249a BS |
4211 | case 0x30: /* ldc */ |
4212 | case 0x31: /* ldcsr */ | |
4213 | case 0x33: /* lddc */ | |
4214 | goto ncp_insn; | |
3475187d FB |
4215 | #endif |
4216 | #endif | |
4217 | #ifdef TARGET_SPARC64 | |
0f8a249a | 4218 | case 0x08: /* V9 ldsw */ |
6ae20372 BS |
4219 | ABI32_MASK(cpu_addr); |
4220 | tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx); | |
0f8a249a BS |
4221 | break; |
4222 | case 0x0b: /* V9 ldx */ | |
6ae20372 BS |
4223 | ABI32_MASK(cpu_addr); |
4224 | tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx); | |
0f8a249a BS |
4225 | break; |
4226 | case 0x18: /* V9 ldswa */ | |
c2bc0e38 | 4227 | save_state(dc, cpu_cond); |
6ae20372 | 4228 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1); |
0f8a249a BS |
4229 | break; |
4230 | case 0x1b: /* V9 ldxa */ | |
c2bc0e38 | 4231 | save_state(dc, cpu_cond); |
6ae20372 | 4232 | gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0); |
0f8a249a BS |
4233 | break; |
4234 | case 0x2d: /* V9 prefetch, no effect */ | |
4235 | goto skip_move; | |
4236 | case 0x30: /* V9 ldfa */ | |
c2bc0e38 | 4237 | save_state(dc, cpu_cond); |
6ae20372 | 4238 | gen_ldf_asi(cpu_addr, insn, 4, rd); |
81ad8ba2 | 4239 | goto skip_move; |
0f8a249a | 4240 | case 0x33: /* V9 lddfa */ |
c2bc0e38 | 4241 | save_state(dc, cpu_cond); |
6ae20372 | 4242 | gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd)); |
81ad8ba2 | 4243 | goto skip_move; |
0f8a249a BS |
4244 | case 0x3d: /* V9 prefetcha, no effect */ |
4245 | goto skip_move; | |
4246 | case 0x32: /* V9 ldqfa */ | |
64a88d5d | 4247 | CHECK_FPU_FEATURE(dc, FLOAT128); |
c2bc0e38 | 4248 | save_state(dc, cpu_cond); |
6ae20372 | 4249 | gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd)); |
1f587329 | 4250 | goto skip_move; |
0f8a249a BS |
4251 | #endif |
4252 | default: | |
4253 | goto illegal_insn; | |
4254 | } | |
6ae20372 | 4255 | gen_movl_TN_reg(rd, cpu_val); |
3475187d | 4256 | #ifdef TARGET_SPARC64 |
0f8a249a | 4257 | skip_move: ; |
3475187d | 4258 | #endif |
0f8a249a | 4259 | } else if (xop >= 0x20 && xop < 0x24) { |
6ae20372 | 4260 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
a80dde08 | 4261 | goto jmp_insn; |
c2bc0e38 | 4262 | save_state(dc, cpu_cond); |
0f8a249a BS |
4263 | switch (xop) { |
4264 | case 0x20: /* load fpreg */ | |
c2bc0e38 | 4265 | ABI32_MASK(cpu_addr); |
6ae20372 | 4266 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); |
ce8536e2 BS |
4267 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
4268 | offsetof(CPUState, fpr[rd])); | |
0f8a249a BS |
4269 | break; |
4270 | case 0x21: /* load fsr */ | |
c2bc0e38 | 4271 | ABI32_MASK(cpu_addr); |
6ae20372 | 4272 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); |
ce8536e2 BS |
4273 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
4274 | offsetof(CPUState, ft0)); | |
7e8c2b6c | 4275 | tcg_gen_helper_0_0(helper_ldfsr); |
0f8a249a BS |
4276 | break; |
4277 | case 0x22: /* load quad fpreg */ | |
64a88d5d | 4278 | CHECK_FPU_FEATURE(dc, FLOAT128); |
455f9004 PB |
4279 | tcg_gen_helper_0_2(helper_ldqf, cpu_addr, |
4280 | tcg_const_i32(dc->mem_idx)); | |
1f587329 BS |
4281 | gen_op_store_QT0_fpr(QFPREG(rd)); |
4282 | break; | |
0f8a249a | 4283 | case 0x23: /* load double fpreg */ |
7fa76c0b BS |
4284 | tcg_gen_helper_0_2(helper_lddf, cpu_addr, |
4285 | tcg_const_i32(dc->mem_idx)); | |
0f8a249a BS |
4286 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4287 | break; | |
4288 | default: | |
4289 | goto illegal_insn; | |
4290 | } | |
4291 | } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \ | |
4292 | xop == 0xe || xop == 0x1e) { | |
6ae20372 | 4293 | gen_movl_reg_TN(rd, cpu_val); |
0f8a249a | 4294 | switch (xop) { |
1a2fb1c0 | 4295 | case 0x4: /* store word */ |
6ae20372 BS |
4296 | ABI32_MASK(cpu_addr); |
4297 | tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); | |
0f8a249a | 4298 | break; |
1a2fb1c0 | 4299 | case 0x5: /* store byte */ |
6ae20372 BS |
4300 | ABI32_MASK(cpu_addr); |
4301 | tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx); | |
0f8a249a | 4302 | break; |
1a2fb1c0 | 4303 | case 0x6: /* store halfword */ |
6ae20372 BS |
4304 | ABI32_MASK(cpu_addr); |
4305 | tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx); | |
0f8a249a | 4306 | break; |
1a2fb1c0 | 4307 | case 0x7: /* store double word */ |
0f8a249a | 4308 | if (rd & 1) |
d4218d99 | 4309 | goto illegal_insn; |
1a2fb1c0 | 4310 | else { |
8911f501 | 4311 | TCGv r_low; |
1a2fb1c0 | 4312 | |
c2bc0e38 BS |
4313 | save_state(dc, cpu_cond); |
4314 | ABI32_MASK(cpu_addr); | |
4315 | tcg_gen_helper_0_2(helper_check_align, cpu_addr, | |
4316 | tcg_const_i32(7)); // XXX remove | |
1a2fb1c0 BS |
4317 | r_low = tcg_temp_new(TCG_TYPE_I32); |
4318 | gen_movl_reg_TN(rd + 1, r_low); | |
6ae20372 | 4319 | tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val, |
1a2fb1c0 | 4320 | r_low); |
6ae20372 | 4321 | tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); |
7fa76c0b | 4322 | } |
0f8a249a | 4323 | break; |
3475187d | 4324 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) |
1a2fb1c0 | 4325 | case 0x14: /* store word alternate */ |
3475187d | 4326 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4327 | if (IS_IMM) |
4328 | goto illegal_insn; | |
4329 | if (!supervisor(dc)) | |
4330 | goto priv_insn; | |
6ea4a6c8 | 4331 | #endif |
c2bc0e38 | 4332 | save_state(dc, cpu_cond); |
6ae20372 | 4333 | gen_st_asi(cpu_val, cpu_addr, insn, 4); |
d39c0b99 | 4334 | break; |
1a2fb1c0 | 4335 | case 0x15: /* store byte alternate */ |
3475187d | 4336 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4337 | if (IS_IMM) |
4338 | goto illegal_insn; | |
4339 | if (!supervisor(dc)) | |
4340 | goto priv_insn; | |
3475187d | 4341 | #endif |
c2bc0e38 | 4342 | save_state(dc, cpu_cond); |
6ae20372 | 4343 | gen_st_asi(cpu_val, cpu_addr, insn, 1); |
d39c0b99 | 4344 | break; |
1a2fb1c0 | 4345 | case 0x16: /* store halfword alternate */ |
3475187d | 4346 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4347 | if (IS_IMM) |
4348 | goto illegal_insn; | |
4349 | if (!supervisor(dc)) | |
4350 | goto priv_insn; | |
6ea4a6c8 | 4351 | #endif |
c2bc0e38 | 4352 | save_state(dc, cpu_cond); |
6ae20372 | 4353 | gen_st_asi(cpu_val, cpu_addr, insn, 2); |
d39c0b99 | 4354 | break; |
1a2fb1c0 | 4355 | case 0x17: /* store double word alternate */ |
3475187d | 4356 | #ifndef TARGET_SPARC64 |
0f8a249a BS |
4357 | if (IS_IMM) |
4358 | goto illegal_insn; | |
4359 | if (!supervisor(dc)) | |
4360 | goto priv_insn; | |
3475187d | 4361 | #endif |
0f8a249a | 4362 | if (rd & 1) |
d4218d99 | 4363 | goto illegal_insn; |
1a2fb1c0 | 4364 | else { |
c2bc0e38 | 4365 | save_state(dc, cpu_cond); |
6ae20372 | 4366 | gen_stda_asi(cpu_val, cpu_addr, insn, rd); |
1a2fb1c0 | 4367 | } |
d39c0b99 | 4368 | break; |
e80cfcfc | 4369 | #endif |
3475187d | 4370 | #ifdef TARGET_SPARC64 |
0f8a249a | 4371 | case 0x0e: /* V9 stx */ |
6ae20372 BS |
4372 | ABI32_MASK(cpu_addr); |
4373 | tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx); | |
0f8a249a BS |
4374 | break; |
4375 | case 0x1e: /* V9 stxa */ | |
c2bc0e38 | 4376 | save_state(dc, cpu_cond); |
6ae20372 | 4377 | gen_st_asi(cpu_val, cpu_addr, insn, 8); |
0f8a249a | 4378 | break; |
3475187d | 4379 | #endif |
0f8a249a BS |
4380 | default: |
4381 | goto illegal_insn; | |
4382 | } | |
4383 | } else if (xop > 0x23 && xop < 0x28) { | |
6ae20372 | 4384 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
a80dde08 | 4385 | goto jmp_insn; |
c2bc0e38 | 4386 | save_state(dc, cpu_cond); |
0f8a249a | 4387 | switch (xop) { |
ce8536e2 | 4388 | case 0x24: /* store fpreg */ |
c2bc0e38 | 4389 | ABI32_MASK(cpu_addr); |
ce8536e2 BS |
4390 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
4391 | offsetof(CPUState, fpr[rd])); | |
6ae20372 | 4392 | tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx); |
0f8a249a BS |
4393 | break; |
4394 | case 0x25: /* stfsr, V9 stxfsr */ | |
c2bc0e38 | 4395 | ABI32_MASK(cpu_addr); |
bb5529bb | 4396 | tcg_gen_helper_0_0(helper_stfsr); |
ce8536e2 BS |
4397 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
4398 | offsetof(CPUState, ft0)); | |
6ae20372 | 4399 | tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx); |
0f8a249a | 4400 | break; |
1f587329 BS |
4401 | case 0x26: |
4402 | #ifdef TARGET_SPARC64 | |
1f587329 | 4403 | /* V9 stqf, store quad fpreg */ |
64a88d5d | 4404 | CHECK_FPU_FEATURE(dc, FLOAT128); |
1f587329 | 4405 | gen_op_load_fpr_QT0(QFPREG(rd)); |
bcb0126f PB |
4406 | tcg_gen_helper_0_2(helper_stqf, cpu_addr, |
4407 | tcg_const_i32(dc->mem_idx)); | |
1f587329 | 4408 | break; |
1f587329 BS |
4409 | #else /* !TARGET_SPARC64 */ |
4410 | /* stdfq, store floating point queue */ | |
4411 | #if defined(CONFIG_USER_ONLY) | |
4412 | goto illegal_insn; | |
4413 | #else | |
0f8a249a BS |
4414 | if (!supervisor(dc)) |
4415 | goto priv_insn; | |
6ae20372 | 4416 | if (gen_trap_ifnofpu(dc, cpu_cond)) |
0f8a249a BS |
4417 | goto jmp_insn; |
4418 | goto nfq_insn; | |
1f587329 | 4419 | #endif |
0f8a249a | 4420 | #endif |
7fa76c0b | 4421 | case 0x27: /* store double fpreg */ |
3475187d | 4422 | gen_op_load_fpr_DT0(DFPREG(rd)); |
7fa76c0b BS |
4423 | tcg_gen_helper_0_2(helper_stdf, cpu_addr, |
4424 | tcg_const_i32(dc->mem_idx)); | |
0f8a249a BS |
4425 | break; |
4426 | default: | |
4427 | goto illegal_insn; | |
4428 | } | |
4429 | } else if (xop > 0x33 && xop < 0x3f) { | |
c2bc0e38 | 4430 | save_state(dc, cpu_cond); |
0f8a249a | 4431 | switch (xop) { |
a4d17f19 | 4432 | #ifdef TARGET_SPARC64 |
0f8a249a | 4433 | case 0x34: /* V9 stfa */ |
3391c818 | 4434 | gen_op_load_fpr_FT0(rd); |
6ae20372 | 4435 | gen_stf_asi(cpu_addr, insn, 4, rd); |
0f8a249a | 4436 | break; |
1f587329 | 4437 | case 0x36: /* V9 stqfa */ |
64a88d5d BS |
4438 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4439 | tcg_gen_helper_0_2(helper_check_align, cpu_addr, | |
4440 | tcg_const_i32(7)); | |
1f587329 | 4441 | gen_op_load_fpr_QT0(QFPREG(rd)); |
6ae20372 | 4442 | gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd)); |
1f587329 | 4443 | break; |
0f8a249a | 4444 | case 0x37: /* V9 stdfa */ |
3391c818 | 4445 | gen_op_load_fpr_DT0(DFPREG(rd)); |
6ae20372 | 4446 | gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd)); |
0f8a249a BS |
4447 | break; |
4448 | case 0x3c: /* V9 casa */ | |
6ae20372 BS |
4449 | gen_cas_asi(cpu_val, cpu_addr, cpu_val, insn, rd); |
4450 | gen_movl_TN_reg(rd, cpu_val); | |
0f8a249a BS |
4451 | break; |
4452 | case 0x3e: /* V9 casxa */ | |
6ae20372 BS |
4453 | gen_casx_asi(cpu_val, cpu_addr, cpu_val, insn, rd); |
4454 | gen_movl_TN_reg(rd, cpu_val); | |
0f8a249a | 4455 | break; |
a4d17f19 | 4456 | #else |
0f8a249a BS |
4457 | case 0x34: /* stc */ |
4458 | case 0x35: /* stcsr */ | |
4459 | case 0x36: /* stdcq */ | |
4460 | case 0x37: /* stdc */ | |
4461 | goto ncp_insn; | |
4462 | #endif | |
4463 | default: | |
4464 | goto illegal_insn; | |
4465 | } | |
e8af50a3 | 4466 | } |
0f8a249a BS |
4467 | else |
4468 | goto illegal_insn; | |
4469 | } | |
4470 | break; | |
cf495bcf FB |
4471 | } |
4472 | /* default case for non jump instructions */ | |
72cbca10 | 4473 | if (dc->npc == DYNAMIC_PC) { |
0f8a249a BS |
4474 | dc->pc = DYNAMIC_PC; |
4475 | gen_op_next_insn(); | |
72cbca10 FB |
4476 | } else if (dc->npc == JUMP_PC) { |
4477 | /* we can do a static jump */ | |
6ae20372 | 4478 | gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); |
72cbca10 FB |
4479 | dc->is_br = 1; |
4480 | } else { | |
0f8a249a BS |
4481 | dc->pc = dc->npc; |
4482 | dc->npc = dc->npc + 4; | |
cf495bcf | 4483 | } |
e80cfcfc | 4484 | jmp_insn: |
cf495bcf FB |
4485 | return; |
4486 | illegal_insn: | |
6ae20372 | 4487 | save_state(dc, cpu_cond); |
2f5680ee | 4488 | tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_ILL_INSN)); |
cf495bcf | 4489 | dc->is_br = 1; |
e8af50a3 | 4490 | return; |
64a88d5d BS |
4491 | unimp_flush: |
4492 | save_state(dc, cpu_cond); | |
4493 | tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_UNIMP_FLUSH)); | |
4494 | dc->is_br = 1; | |
4495 | return; | |
e80cfcfc | 4496 | #if !defined(CONFIG_USER_ONLY) |
e8af50a3 | 4497 | priv_insn: |
6ae20372 | 4498 | save_state(dc, cpu_cond); |
2f5680ee | 4499 | tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_PRIV_INSN)); |
e8af50a3 | 4500 | dc->is_br = 1; |
e80cfcfc | 4501 | return; |
64a88d5d | 4502 | #endif |
e80cfcfc | 4503 | nfpu_insn: |
6ae20372 | 4504 | save_state(dc, cpu_cond); |
e80cfcfc FB |
4505 | gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); |
4506 | dc->is_br = 1; | |
fcc72045 | 4507 | return; |
64a88d5d | 4508 | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) |
9143e598 | 4509 | nfq_insn: |
6ae20372 | 4510 | save_state(dc, cpu_cond); |
9143e598 BS |
4511 | gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); |
4512 | dc->is_br = 1; | |
4513 | return; | |
4514 | #endif | |
fcc72045 BS |
4515 | #ifndef TARGET_SPARC64 |
4516 | ncp_insn: | |
6ae20372 | 4517 | save_state(dc, cpu_cond); |
2f5680ee | 4518 | tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NCP_INSN)); |
fcc72045 BS |
4519 | dc->is_br = 1; |
4520 | return; | |
4521 | #endif | |
7a3f1944 FB |
4522 | } |
4523 | ||
cf495bcf | 4524 | static inline int gen_intermediate_code_internal(TranslationBlock * tb, |
0f8a249a | 4525 | int spc, CPUSPARCState *env) |
7a3f1944 | 4526 | { |
72cbca10 | 4527 | target_ulong pc_start, last_pc; |
cf495bcf FB |
4528 | uint16_t *gen_opc_end; |
4529 | DisasContext dc1, *dc = &dc1; | |
e8af50a3 | 4530 | int j, lj = -1; |
cf495bcf FB |
4531 | |
4532 | memset(dc, 0, sizeof(DisasContext)); | |
cf495bcf | 4533 | dc->tb = tb; |
72cbca10 | 4534 | pc_start = tb->pc; |
cf495bcf | 4535 | dc->pc = pc_start; |
e80cfcfc | 4536 | last_pc = dc->pc; |
72cbca10 | 4537 | dc->npc = (target_ulong) tb->cs_base; |
6f27aba6 | 4538 | dc->mem_idx = cpu_mmu_index(env); |
64a88d5d BS |
4539 | dc->features = env->features; |
4540 | if ((dc->features & CPU_FEATURE_FLOAT)) { | |
4541 | dc->fpu_enabled = cpu_fpu_enabled(env); | |
4542 | #if defined(CONFIG_USER_ONLY) | |
4543 | dc->features |= CPU_FEATURE_FLOAT128; | |
4544 | #endif | |
4545 | } else | |
4546 | dc->fpu_enabled = 0; | |
cf495bcf | 4547 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
cf495bcf | 4548 | |
1a2fb1c0 | 4549 | cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL); |
8911f501 BS |
4550 | cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32); |
4551 | cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64); | |
1a2fb1c0 | 4552 | |
cf495bcf | 4553 | do { |
e8af50a3 FB |
4554 | if (env->nb_breakpoints > 0) { |
4555 | for(j = 0; j < env->nb_breakpoints; j++) { | |
4556 | if (env->breakpoints[j] == dc->pc) { | |
0f8a249a | 4557 | if (dc->pc != pc_start) |
6ae20372 | 4558 | save_state(dc, cpu_cond); |
1a2fb1c0 | 4559 | tcg_gen_helper_0_0(helper_debug); |
57fec1fe | 4560 | tcg_gen_exit_tb(0); |
0f8a249a | 4561 | dc->is_br = 1; |
e80cfcfc | 4562 | goto exit_gen_loop; |
e8af50a3 FB |
4563 | } |
4564 | } | |
4565 | } | |
4566 | if (spc) { | |
4567 | if (loglevel > 0) | |
4568 | fprintf(logfile, "Search PC...\n"); | |
4569 | j = gen_opc_ptr - gen_opc_buf; | |
4570 | if (lj < j) { | |
4571 | lj++; | |
4572 | while (lj < j) | |
4573 | gen_opc_instr_start[lj++] = 0; | |
4574 | gen_opc_pc[lj] = dc->pc; | |
4575 | gen_opc_npc[lj] = dc->npc; | |
4576 | gen_opc_instr_start[lj] = 1; | |
4577 | } | |
4578 | } | |
0f8a249a BS |
4579 | last_pc = dc->pc; |
4580 | disas_sparc_insn(dc); | |
4581 | ||
4582 | if (dc->is_br) | |
4583 | break; | |
4584 | /* if the next PC is different, we abort now */ | |
4585 | if (dc->pc != (last_pc + 4)) | |
4586 | break; | |
d39c0b99 FB |
4587 | /* if we reach a page boundary, we stop generation so that the |
4588 | PC of a TT_TFAULT exception is always in the right page */ | |
4589 | if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) | |
4590 | break; | |
e80cfcfc FB |
4591 | /* if single step mode, we generate only one instruction and |
4592 | generate an exception */ | |
4593 | if (env->singlestep_enabled) { | |
2f5680ee | 4594 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
57fec1fe | 4595 | tcg_gen_exit_tb(0); |
e80cfcfc FB |
4596 | break; |
4597 | } | |
cf495bcf | 4598 | } while ((gen_opc_ptr < gen_opc_end) && |
0f8a249a | 4599 | (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32)); |
e80cfcfc FB |
4600 | |
4601 | exit_gen_loop: | |
72cbca10 | 4602 | if (!dc->is_br) { |
5fafdf24 | 4603 | if (dc->pc != DYNAMIC_PC && |
72cbca10 FB |
4604 | (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { |
4605 | /* static PC and NPC: we can use direct chaining */ | |
2f5680ee | 4606 | gen_goto_tb(dc, 0, dc->pc, dc->npc); |
72cbca10 FB |
4607 | } else { |
4608 | if (dc->pc != DYNAMIC_PC) | |
2f5680ee | 4609 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
6ae20372 | 4610 | save_npc(dc, cpu_cond); |
57fec1fe | 4611 | tcg_gen_exit_tb(0); |
72cbca10 FB |
4612 | } |
4613 | } | |
cf495bcf | 4614 | *gen_opc_ptr = INDEX_op_end; |
e8af50a3 FB |
4615 | if (spc) { |
4616 | j = gen_opc_ptr - gen_opc_buf; | |
4617 | lj++; | |
4618 | while (lj <= j) | |
4619 | gen_opc_instr_start[lj++] = 0; | |
e8af50a3 FB |
4620 | #if 0 |
4621 | if (loglevel > 0) { | |
4622 | page_dump(logfile); | |
4623 | } | |
4624 | #endif | |
c3278b7b FB |
4625 | gen_opc_jump_pc[0] = dc->jump_pc[0]; |
4626 | gen_opc_jump_pc[1] = dc->jump_pc[1]; | |
e8af50a3 | 4627 | } else { |
e80cfcfc | 4628 | tb->size = last_pc + 4 - pc_start; |
e8af50a3 | 4629 | } |
7a3f1944 | 4630 | #ifdef DEBUG_DISAS |
e19e89a5 | 4631 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
0f8a249a BS |
4632 | fprintf(logfile, "--------------\n"); |
4633 | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start)); | |
4634 | target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0); | |
4635 | fprintf(logfile, "\n"); | |
cf495bcf | 4636 | } |
7a3f1944 | 4637 | #endif |
cf495bcf | 4638 | return 0; |
7a3f1944 FB |
4639 | } |
4640 | ||
cf495bcf | 4641 | int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb) |
7a3f1944 | 4642 | { |
e8af50a3 | 4643 | return gen_intermediate_code_internal(tb, 0, env); |
7a3f1944 FB |
4644 | } |
4645 | ||
cf495bcf | 4646 | int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb) |
7a3f1944 | 4647 | { |
e8af50a3 | 4648 | return gen_intermediate_code_internal(tb, 1, env); |
7a3f1944 FB |
4649 | } |
4650 | ||
c48fcb47 | 4651 | void gen_intermediate_code_init(CPUSPARCState *env) |
e80cfcfc | 4652 | { |
f5069b26 | 4653 | unsigned int i; |
c48fcb47 | 4654 | static int inited; |
f5069b26 BS |
4655 | static const char * const gregnames[8] = { |
4656 | NULL, // g0 not used | |
4657 | "g1", | |
4658 | "g2", | |
4659 | "g3", | |
4660 | "g4", | |
4661 | "g5", | |
4662 | "g6", | |
4663 | "g7", | |
4664 | }; | |
aaed909a | 4665 | |
1a2fb1c0 BS |
4666 | /* init various static tables */ |
4667 | if (!inited) { | |
4668 | inited = 1; | |
4669 | ||
1a2fb1c0 | 4670 | cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env"); |
db4a4ea4 BS |
4671 | cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0, |
4672 | offsetof(CPUState, regwptr), | |
4673 | "regwptr"); | |
1a2fb1c0 | 4674 | #ifdef TARGET_SPARC64 |
dc99a3f2 BS |
4675 | cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32, |
4676 | TCG_AREG0, offsetof(CPUState, xcc), | |
4677 | "xcc"); | |
1a2fb1c0 | 4678 | #endif |
7c60cc4b FB |
4679 | /* XXX: T0 and T1 should be temporaries */ |
4680 | cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL, | |
4681 | TCG_AREG0, offsetof(CPUState, t0), "T0"); | |
4682 | cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL, | |
4683 | TCG_AREG0, offsetof(CPUState, t1), "T1"); | |
4684 | cpu_cond = tcg_global_mem_new(TCG_TYPE_TL, | |
77f193da BS |
4685 | TCG_AREG0, offsetof(CPUState, cond), |
4686 | "cond"); | |
dc99a3f2 BS |
4687 | cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL, |
4688 | TCG_AREG0, offsetof(CPUState, cc_src), | |
4689 | "cc_src"); | |
d9bdab86 BS |
4690 | cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
4691 | offsetof(CPUState, cc_src2), | |
4692 | "cc_src2"); | |
dc99a3f2 BS |
4693 | cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL, |
4694 | TCG_AREG0, offsetof(CPUState, cc_dst), | |
4695 | "cc_dst"); | |
4696 | cpu_psr = tcg_global_mem_new(TCG_TYPE_I32, | |
4697 | TCG_AREG0, offsetof(CPUState, psr), | |
4698 | "psr"); | |
87e92502 BS |
4699 | cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL, |
4700 | TCG_AREG0, offsetof(CPUState, fsr), | |
4701 | "fsr"); | |
48d5c82b BS |
4702 | cpu_pc = tcg_global_mem_new(TCG_TYPE_TL, |
4703 | TCG_AREG0, offsetof(CPUState, pc), | |
4704 | "pc"); | |
4705 | cpu_npc = tcg_global_mem_new(TCG_TYPE_TL, | |
4706 | TCG_AREG0, offsetof(CPUState, npc), | |
4707 | "npc"); | |
f5069b26 BS |
4708 | for (i = 1; i < 8; i++) |
4709 | cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, | |
4710 | offsetof(CPUState, gregs[i]), | |
4711 | gregnames[i]); | |
c9e03d8f BS |
4712 | /* register helpers */ |
4713 | ||
4714 | #undef DEF_HELPER | |
4715 | #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); | |
4716 | #include "helper.h" | |
1a2fb1c0 | 4717 | } |
658138bc | 4718 | } |
d2856f1a AJ |
4719 | |
4720 | void gen_pc_load(CPUState *env, TranslationBlock *tb, | |
4721 | unsigned long searched_pc, int pc_pos, void *puc) | |
4722 | { | |
4723 | target_ulong npc; | |
4724 | env->pc = gen_opc_pc[pc_pos]; | |
4725 | npc = gen_opc_npc[pc_pos]; | |
4726 | if (npc == 1) { | |
4727 | /* dynamic NPC: already stored */ | |
4728 | } else if (npc == 2) { | |
4729 | target_ulong t2 = (target_ulong)(unsigned long)puc; | |
4730 | /* jump PC: use T2 and the jump targets of the translation */ | |
4731 | if (t2) | |
4732 | env->npc = gen_opc_jump_pc[0]; | |
4733 | else | |
4734 | env->npc = gen_opc_jump_pc[1]; | |
4735 | } else { | |
4736 | env->npc = npc; | |
4737 | } | |
4738 | } |