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7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
7a3f1944
FB		 23 TODO-list:
24
3475187d 25 Rest of V9 instructions, VIS instructions
bd497938 26 NPC/PC static optimisations (use JUMP_TB when possible)
7a3f1944 27 Optimize synthetic instructions
3475187d 28 128-bit float
bd497938 29*/
7a3f1944
FB		 30
31#include <stdarg.h>
32#include <stdlib.h>
33#include <stdio.h>
34#include <string.h>
35#include <inttypes.h>
36
37#include "cpu.h"
38#include "exec-all.h"
39#include "disas.h"
40
41#define DEBUG_DISAS
42
72cbca10
FB		 43#define DYNAMIC_PC 1 /* dynamic pc value */
44#define JUMP_PC 2 /* dynamic pc value which takes only two values
45 according to jump_pc[T2] */
46
7a3f1944 47typedef struct DisasContext {
72cbca10
FB		 48 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
49 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
50 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 51 int is_br;
e8af50a3 52 int mem_idx;
a80dde08 53 int fpu_enabled;
cf495bcf 54 struct TranslationBlock *tb;
7a3f1944
FB		 55} DisasContext;
56
62724a37
BS		 57struct sparc_def_t {
58 const unsigned char *name;
59 target_ulong iu_version;
60 uint32_t fpu_version;
61 uint32_t mmu_version;
62};
63
7a3f1944
FB		 64static uint16_t *gen_opc_ptr;
65static uint32_t *gen_opparam_ptr;
66extern FILE *logfile;
67extern int loglevel;
68
69enum {
70#define DEF(s,n,copy_size) INDEX_op_ ## s,
71#include "opc.h"
72#undef DEF
cf495bcf 73 NB_OPS
7a3f1944
FB		 74};
75
76#include "gen-op.h"
77
3475187d 78// This function uses non-native bit order
7a3f1944
FB		 79#define GET_FIELD(X, FROM, TO) \
80 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
81
3475187d
FB		 82// This function uses the order in the manuals, i.e. bit 0 is 2^0
83#define GET_FIELD_SP(X, FROM, TO) \
84 GET_FIELD(X, 31 - (TO), 31 - (FROM))
85
86#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
87#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), 32 - ((b) - (a) + 1))
88
89#ifdef TARGET_SPARC64
90#define DFPREG(r) (((r & 1) << 6) | (r & 0x1e))
91#else
c185970a 92#define DFPREG(r) (r & 0x1e)
3475187d
FB		 93#endif
94
83469015
FB		 95#ifdef USE_DIRECT_JUMP
96#define TBPARAM(x)
97#else
98#define TBPARAM(x) (long)(x)
99#endif
100
3475187d
FB		 101static int sign_extend(int x, int len)
102{
103 len = 32 - len;
104 return (x << len) >> len;
105}
106
7a3f1944
FB		 107#define IS_IMM (insn & (1<<13))
108
cf495bcf 109static void disas_sparc_insn(DisasContext * dc);
7a3f1944 110
a68156d0 111static GenOpFunc * const gen_op_movl_TN_reg[2][32] = {
cf495bcf
FB		 112 {
113 gen_op_movl_g0_T0,
114 gen_op_movl_g1_T0,
115 gen_op_movl_g2_T0,
116 gen_op_movl_g3_T0,
117 gen_op_movl_g4_T0,
118 gen_op_movl_g5_T0,
119 gen_op_movl_g6_T0,
120 gen_op_movl_g7_T0,
121 gen_op_movl_o0_T0,
122 gen_op_movl_o1_T0,
123 gen_op_movl_o2_T0,
124 gen_op_movl_o3_T0,
125 gen_op_movl_o4_T0,
126 gen_op_movl_o5_T0,
127 gen_op_movl_o6_T0,
128 gen_op_movl_o7_T0,
129 gen_op_movl_l0_T0,
130 gen_op_movl_l1_T0,
131 gen_op_movl_l2_T0,
132 gen_op_movl_l3_T0,
133 gen_op_movl_l4_T0,
134 gen_op_movl_l5_T0,
135 gen_op_movl_l6_T0,
136 gen_op_movl_l7_T0,
137 gen_op_movl_i0_T0,
138 gen_op_movl_i1_T0,
139 gen_op_movl_i2_T0,
140 gen_op_movl_i3_T0,
141 gen_op_movl_i4_T0,
142 gen_op_movl_i5_T0,
143 gen_op_movl_i6_T0,
144 gen_op_movl_i7_T0,
145 },
146 {
147 gen_op_movl_g0_T1,
148 gen_op_movl_g1_T1,
149 gen_op_movl_g2_T1,
150 gen_op_movl_g3_T1,
151 gen_op_movl_g4_T1,
152 gen_op_movl_g5_T1,
153 gen_op_movl_g6_T1,
154 gen_op_movl_g7_T1,
155 gen_op_movl_o0_T1,
156 gen_op_movl_o1_T1,
157 gen_op_movl_o2_T1,
158 gen_op_movl_o3_T1,
159 gen_op_movl_o4_T1,
160 gen_op_movl_o5_T1,
161 gen_op_movl_o6_T1,
162 gen_op_movl_o7_T1,
163 gen_op_movl_l0_T1,
164 gen_op_movl_l1_T1,
165 gen_op_movl_l2_T1,
166 gen_op_movl_l3_T1,
167 gen_op_movl_l4_T1,
168 gen_op_movl_l5_T1,
169 gen_op_movl_l6_T1,
170 gen_op_movl_l7_T1,
171 gen_op_movl_i0_T1,
172 gen_op_movl_i1_T1,
173 gen_op_movl_i2_T1,
174 gen_op_movl_i3_T1,
175 gen_op_movl_i4_T1,
176 gen_op_movl_i5_T1,
177 gen_op_movl_i6_T1,
178 gen_op_movl_i7_T1,
179 }
7a3f1944
FB		 180};
181
a68156d0 182static GenOpFunc * const gen_op_movl_reg_TN[3][32] = {
cf495bcf
FB		 183 {
184 gen_op_movl_T0_g0,
185 gen_op_movl_T0_g1,
186 gen_op_movl_T0_g2,
187 gen_op_movl_T0_g3,
188 gen_op_movl_T0_g4,
189 gen_op_movl_T0_g5,
190 gen_op_movl_T0_g6,
191 gen_op_movl_T0_g7,
192 gen_op_movl_T0_o0,
193 gen_op_movl_T0_o1,
194 gen_op_movl_T0_o2,
195 gen_op_movl_T0_o3,
196 gen_op_movl_T0_o4,
197 gen_op_movl_T0_o5,
198 gen_op_movl_T0_o6,
199 gen_op_movl_T0_o7,
200 gen_op_movl_T0_l0,
201 gen_op_movl_T0_l1,
202 gen_op_movl_T0_l2,
203 gen_op_movl_T0_l3,
204 gen_op_movl_T0_l4,
205 gen_op_movl_T0_l5,
206 gen_op_movl_T0_l6,
207 gen_op_movl_T0_l7,
208 gen_op_movl_T0_i0,
209 gen_op_movl_T0_i1,
210 gen_op_movl_T0_i2,
211 gen_op_movl_T0_i3,
212 gen_op_movl_T0_i4,
213 gen_op_movl_T0_i5,
214 gen_op_movl_T0_i6,
215 gen_op_movl_T0_i7,
216 },
217 {
218 gen_op_movl_T1_g0,
219 gen_op_movl_T1_g1,
220 gen_op_movl_T1_g2,
221 gen_op_movl_T1_g3,
222 gen_op_movl_T1_g4,
223 gen_op_movl_T1_g5,
224 gen_op_movl_T1_g6,
225 gen_op_movl_T1_g7,
226 gen_op_movl_T1_o0,
227 gen_op_movl_T1_o1,
228 gen_op_movl_T1_o2,
229 gen_op_movl_T1_o3,
230 gen_op_movl_T1_o4,
231 gen_op_movl_T1_o5,
232 gen_op_movl_T1_o6,
233 gen_op_movl_T1_o7,
234 gen_op_movl_T1_l0,
235 gen_op_movl_T1_l1,
236 gen_op_movl_T1_l2,
237 gen_op_movl_T1_l3,
238 gen_op_movl_T1_l4,
239 gen_op_movl_T1_l5,
240 gen_op_movl_T1_l6,
241 gen_op_movl_T1_l7,
242 gen_op_movl_T1_i0,
243 gen_op_movl_T1_i1,
244 gen_op_movl_T1_i2,
245 gen_op_movl_T1_i3,
246 gen_op_movl_T1_i4,
247 gen_op_movl_T1_i5,
248 gen_op_movl_T1_i6,
249 gen_op_movl_T1_i7,
250 },
251 {
252 gen_op_movl_T2_g0,
253 gen_op_movl_T2_g1,
254 gen_op_movl_T2_g2,
255 gen_op_movl_T2_g3,
256 gen_op_movl_T2_g4,
257 gen_op_movl_T2_g5,
258 gen_op_movl_T2_g6,
259 gen_op_movl_T2_g7,
260 gen_op_movl_T2_o0,
261 gen_op_movl_T2_o1,
262 gen_op_movl_T2_o2,
263 gen_op_movl_T2_o3,
264 gen_op_movl_T2_o4,
265 gen_op_movl_T2_o5,
266 gen_op_movl_T2_o6,
267 gen_op_movl_T2_o7,
268 gen_op_movl_T2_l0,
269 gen_op_movl_T2_l1,
270 gen_op_movl_T2_l2,
271 gen_op_movl_T2_l3,
272 gen_op_movl_T2_l4,
273 gen_op_movl_T2_l5,
274 gen_op_movl_T2_l6,
275 gen_op_movl_T2_l7,
276 gen_op_movl_T2_i0,
277 gen_op_movl_T2_i1,
278 gen_op_movl_T2_i2,
279 gen_op_movl_T2_i3,
280 gen_op_movl_T2_i4,
281 gen_op_movl_T2_i5,
282 gen_op_movl_T2_i6,
283 gen_op_movl_T2_i7,
284 }
7a3f1944
FB		 285};
286
a68156d0 287static GenOpFunc1 * const gen_op_movl_TN_im[3] = {
cf495bcf
FB		 288 gen_op_movl_T0_im,
289 gen_op_movl_T1_im,
290 gen_op_movl_T2_im
7a3f1944
FB		 291};
292
3475187d
FB		 293// Sign extending version
294static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {
295 gen_op_movl_T0_sim,
296 gen_op_movl_T1_sim,
297 gen_op_movl_T2_sim
298};
299
300#ifdef TARGET_SPARC64
301#define GEN32(func, NAME) \
a68156d0 302static GenOpFunc * const NAME ## _table [64] = { \
3475187d
FB		 303NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
304NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
305NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
306NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
307NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
308NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
309NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
310NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
311NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
312NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
313NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
314NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
315}; \
316static inline void func(int n) \
317{ \
318 NAME ## _table[n](); \
319}
320#else
e8af50a3 321#define GEN32(func, NAME) \
a68156d0 322static GenOpFunc *const NAME ## _table [32] = { \
e8af50a3
FB		 323NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
324NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
325NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
326NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
327NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
328NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
329NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
330NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
331}; \
332static inline void func(int n) \
333{ \
334 NAME ## _table[n](); \
335}
3475187d 336#endif
e8af50a3
FB		 337
338/* floating point registers moves */
339GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
340GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
e8af50a3
FB		 341GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
342GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
e8af50a3
FB		 343
344GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
345GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
e8af50a3
FB		 346GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
347GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
e8af50a3 348
3475187d
FB		 349#ifdef TARGET_SPARC64
350// 'a' versions allowed to user depending on asi
351#if defined(CONFIG_USER_ONLY)
352#define supervisor(dc) 0
e9ebed4d 353#define hypervisor(dc) 0
3475187d
FB		 354#define gen_op_ldst(name) gen_op_##name##_raw()
355#define OP_LD_TABLE(width) \
356 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
357 { \
358 int asi, offset; \
359 \
360 if (IS_IMM) { \
361 offset = GET_FIELD(insn, 25, 31); \
362 if (is_ld) \
363 gen_op_ld_asi_reg(offset, size, sign); \
364 else \
365 gen_op_st_asi_reg(offset, size, sign); \
366 return; \
367 } \
368 asi = GET_FIELD(insn, 19, 26); \
369 switch (asi) { \
370 case 0x80: /* Primary address space */ \
371 gen_op_##width##_raw(); \
372 break; \
725cb90b
FB		 373 case 0x82: /* Primary address space, non-faulting load */ \
374 gen_op_##width##_raw(); \
375 break; \
3475187d
FB		 376 default: \
377 break; \
378 } \
379 }
380
381#else
382#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
383#define OP_LD_TABLE(width) \
a68156d0 384 static GenOpFunc * const gen_op_##width[] = { \
3475187d
FB		 385 &gen_op_##width##_user, \
386 &gen_op_##width##_kernel, \
387 }; \
388 \
389 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
390 { \
391 int asi, offset; \
392 \
393 if (IS_IMM) { \
394 offset = GET_FIELD(insn, 25, 31); \
395 if (is_ld) \
396 gen_op_ld_asi_reg(offset, size, sign); \
397 else \
398 gen_op_st_asi_reg(offset, size, sign); \
399 return; \
400 } \
401 asi = GET_FIELD(insn, 19, 26); \
402 if (is_ld) \
403 gen_op_ld_asi(asi, size, sign); \
404 else \
405 gen_op_st_asi(asi, size, sign); \
406 }
407
408#define supervisor(dc) (dc->mem_idx == 1)
e9ebed4d 409#define hypervisor(dc) (dc->mem_idx == 2)
3475187d
FB		 410#endif
411#else
e8af50a3
FB		 412#if defined(CONFIG_USER_ONLY)
413#define gen_op_ldst(name) gen_op_##name##_raw()
0fa85d43 414#define OP_LD_TABLE(width)
e8af50a3
FB		 415#define supervisor(dc) 0
416#else
417#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
418#define OP_LD_TABLE(width) \
a68156d0 419static GenOpFunc * const gen_op_##width[] = { \
e8af50a3
FB		 420 &gen_op_##width##_user, \
421 &gen_op_##width##_kernel, \
422}; \
423 \
424static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
425{ \
426 int asi; \
427 \
428 asi = GET_FIELD(insn, 19, 26); \
429 switch (asi) { \
430 case 10: /* User data access */ \
431 gen_op_##width##_user(); \
432 break; \
433 case 11: /* Supervisor data access */ \
434 gen_op_##width##_kernel(); \
435 break; \
436 case 0x20 ... 0x2f: /* MMU passthrough */ \
437 if (is_ld) \
438 gen_op_ld_asi(asi, size, sign); \
439 else \
440 gen_op_st_asi(asi, size, sign); \
441 break; \
442 default: \
443 if (is_ld) \
444 gen_op_ld_asi(asi, size, sign); \
445 else \
446 gen_op_st_asi(asi, size, sign); \
447 break; \
448 } \
449}
450
451#define supervisor(dc) (dc->mem_idx == 1)
452#endif
3475187d 453#endif
e8af50a3
FB		 454
455OP_LD_TABLE(ld);
456OP_LD_TABLE(st);
457OP_LD_TABLE(ldub);
458OP_LD_TABLE(lduh);
459OP_LD_TABLE(ldsb);
460OP_LD_TABLE(ldsh);
461OP_LD_TABLE(stb);
462OP_LD_TABLE(sth);
463OP_LD_TABLE(std);
464OP_LD_TABLE(ldstub);
465OP_LD_TABLE(swap);
466OP_LD_TABLE(ldd);
467OP_LD_TABLE(stf);
468OP_LD_TABLE(stdf);
469OP_LD_TABLE(ldf);
470OP_LD_TABLE(lddf);
471
3475187d
FB		 472#ifdef TARGET_SPARC64
473OP_LD_TABLE(ldsw);
474OP_LD_TABLE(ldx);
475OP_LD_TABLE(stx);
476OP_LD_TABLE(cas);
477OP_LD_TABLE(casx);
478#endif
479
480static inline void gen_movl_imm_TN(int reg, uint32_t imm)
7a3f1944 481{
83469015 482 gen_op_movl_TN_im[reg](imm);
7a3f1944
FB		 483}
484
3475187d 485static inline void gen_movl_imm_T1(uint32_t val)
7a3f1944 486{
cf495bcf 487 gen_movl_imm_TN(1, val);
7a3f1944
FB		 488}
489
3475187d 490static inline void gen_movl_imm_T0(uint32_t val)
7a3f1944 491{
cf495bcf 492 gen_movl_imm_TN(0, val);
7a3f1944
FB		 493}
494
3475187d
FB		 495static inline void gen_movl_simm_TN(int reg, int32_t imm)
496{
497 gen_op_movl_TN_sim[reg](imm);
498}
499
500static inline void gen_movl_simm_T1(int32_t val)
501{
502 gen_movl_simm_TN(1, val);
503}
504
505static inline void gen_movl_simm_T0(int32_t val)
506{
507 gen_movl_simm_TN(0, val);
508}
509
cf495bcf 510static inline void gen_movl_reg_TN(int reg, int t)
7a3f1944 511{
cf495bcf
FB		 512 if (reg)
513 gen_op_movl_reg_TN[t][reg] ();
514 else
515 gen_movl_imm_TN(t, 0);
7a3f1944
FB		 516}
517
cf495bcf 518static inline void gen_movl_reg_T0(int reg)
7a3f1944 519{
cf495bcf 520 gen_movl_reg_TN(reg, 0);
7a3f1944
FB		 521}
522
cf495bcf 523static inline void gen_movl_reg_T1(int reg)
7a3f1944 524{
cf495bcf 525 gen_movl_reg_TN(reg, 1);
7a3f1944
FB		 526}
527
cf495bcf 528static inline void gen_movl_reg_T2(int reg)
7a3f1944 529{
cf495bcf 530 gen_movl_reg_TN(reg, 2);
7a3f1944
FB		 531}
532
cf495bcf 533static inline void gen_movl_TN_reg(int reg, int t)
7a3f1944 534{
cf495bcf
FB		 535 if (reg)
536 gen_op_movl_TN_reg[t][reg] ();
7a3f1944
FB		 537}
538
cf495bcf 539static inline void gen_movl_T0_reg(int reg)
7a3f1944 540{
cf495bcf 541 gen_movl_TN_reg(reg, 0);
7a3f1944
FB		 542}
543
cf495bcf 544static inline void gen_movl_T1_reg(int reg)
7a3f1944 545{
cf495bcf 546 gen_movl_TN_reg(reg, 1);
7a3f1944
FB		 547}
548
3475187d
FB		 549static inline void gen_jmp_im(target_ulong pc)
550{
551#ifdef TARGET_SPARC64
552 if (pc == (uint32_t)pc) {
553 gen_op_jmp_im(pc);
554 } else {
555 gen_op_jmp_im64(pc >> 32, pc);
556 }
557#else
558 gen_op_jmp_im(pc);
559#endif
560}
561
562static inline void gen_movl_npc_im(target_ulong npc)
563{
564#ifdef TARGET_SPARC64
565 if (npc == (uint32_t)npc) {
566 gen_op_movl_npc_im(npc);
567 } else {
568 gen_op_movq_npc_im64(npc >> 32, npc);
569 }
570#else
571 gen_op_movl_npc_im(npc);
572#endif
573}
574
6e256c93
FB		 575static inline void gen_goto_tb(DisasContext *s, int tb_num,
576 target_ulong pc, target_ulong npc)
577{
578 TranslationBlock *tb;
579
580 tb = s->tb;
581 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
582 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
583 /* jump to same page: we can use a direct jump */
584 if (tb_num == 0)
585 gen_op_goto_tb0(TBPARAM(tb));
586 else
587 gen_op_goto_tb1(TBPARAM(tb));
588 gen_jmp_im(pc);
589 gen_movl_npc_im(npc);
590 gen_op_movl_T0_im((long)tb + tb_num);
591 gen_op_exit_tb();
592 } else {
593 /* jump to another page: currently not optimized */
594 gen_jmp_im(pc);
595 gen_movl_npc_im(npc);
596 gen_op_movl_T0_0();
597 gen_op_exit_tb();
598 }
599}
600
46525e1f
BS		 601static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
602 target_ulong pc2)
83469015
FB		 603{
604 int l1;
605
606 l1 = gen_new_label();
607
608 gen_op_jz_T2_label(l1);
609
6e256c93 610 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 611
612 gen_set_label(l1);
6e256c93 613 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 614}
615
46525e1f
BS		 616static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
617 target_ulong pc2)
83469015
FB		 618{
619 int l1;
620
621 l1 = gen_new_label();
622
623 gen_op_jz_T2_label(l1);
624
6e256c93 625 gen_goto_tb(dc, 0, pc2, pc1);
83469015
FB		 626
627 gen_set_label(l1);
6e256c93 628 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
83469015
FB		 629}
630
46525e1f
BS		 631static inline void gen_branch(DisasContext *dc, target_ulong pc,
632 target_ulong npc)
83469015 633{
6e256c93 634 gen_goto_tb(dc, 0, pc, npc);
83469015
FB		 635}
636
46525e1f 637static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2)
83469015
FB		 638{
639 int l1, l2;
640
641 l1 = gen_new_label();
642 l2 = gen_new_label();
643 gen_op_jz_T2_label(l1);
644
645 gen_movl_npc_im(npc1);
646 gen_op_jmp_label(l2);
647
648 gen_set_label(l1);
649 gen_movl_npc_im(npc2);
650 gen_set_label(l2);
651}
652
653/* call this function before using T2 as it may have been set for a jump */
654static inline void flush_T2(DisasContext * dc)
655{
656 if (dc->npc == JUMP_PC) {
46525e1f 657 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
83469015
FB		 658 dc->npc = DYNAMIC_PC;
659 }
660}
661
72cbca10
FB		 662static inline void save_npc(DisasContext * dc)
663{
664 if (dc->npc == JUMP_PC) {
46525e1f 665 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
72cbca10
FB		 666 dc->npc = DYNAMIC_PC;
667 } else if (dc->npc != DYNAMIC_PC) {
3475187d 668 gen_movl_npc_im(dc->npc);
72cbca10
FB		 669 }
670}
671
672static inline void save_state(DisasContext * dc)
673{
3475187d 674 gen_jmp_im(dc->pc);
72cbca10
FB		 675 save_npc(dc);
676}
677
0bee699e
FB		 678static inline void gen_mov_pc_npc(DisasContext * dc)
679{
680 if (dc->npc == JUMP_PC) {
46525e1f 681 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
0bee699e
FB		 682 gen_op_mov_pc_npc();
683 dc->pc = DYNAMIC_PC;
684 } else if (dc->npc == DYNAMIC_PC) {
685 gen_op_mov_pc_npc();
686 dc->pc = DYNAMIC_PC;
687 } else {
688 dc->pc = dc->npc;
689 }
690}
691
3475187d
FB		 692static GenOpFunc * const gen_cond[2][16] = {
693 {
9bad0425 694 gen_op_eval_bn,
3475187d
FB		 695 gen_op_eval_be,
696 gen_op_eval_ble,
697 gen_op_eval_bl,
698 gen_op_eval_bleu,
699 gen_op_eval_bcs,
700 gen_op_eval_bneg,
701 gen_op_eval_bvs,
9bad0425 702 gen_op_eval_ba,
3475187d
FB		 703 gen_op_eval_bne,
704 gen_op_eval_bg,
705 gen_op_eval_bge,
706 gen_op_eval_bgu,
707 gen_op_eval_bcc,
708 gen_op_eval_bpos,
709 gen_op_eval_bvc,
710 },
711 {
712#ifdef TARGET_SPARC64
9bad0425 713 gen_op_eval_bn,
3475187d
FB		 714 gen_op_eval_xbe,
715 gen_op_eval_xble,
716 gen_op_eval_xbl,
717 gen_op_eval_xbleu,
718 gen_op_eval_xbcs,
719 gen_op_eval_xbneg,
720 gen_op_eval_xbvs,
9bad0425 721 gen_op_eval_ba,
3475187d
FB		 722 gen_op_eval_xbne,
723 gen_op_eval_xbg,
724 gen_op_eval_xbge,
725 gen_op_eval_xbgu,
726 gen_op_eval_xbcc,
727 gen_op_eval_xbpos,
728 gen_op_eval_xbvc,
729#endif
730 },
731};
732
733static GenOpFunc * const gen_fcond[4][16] = {
734 {
9bad0425 735 gen_op_eval_bn,
3475187d
FB		 736 gen_op_eval_fbne,
737 gen_op_eval_fblg,
738 gen_op_eval_fbul,
739 gen_op_eval_fbl,
740 gen_op_eval_fbug,
741 gen_op_eval_fbg,
742 gen_op_eval_fbu,
9bad0425 743 gen_op_eval_ba,
3475187d
FB		 744 gen_op_eval_fbe,
745 gen_op_eval_fbue,
746 gen_op_eval_fbge,
747 gen_op_eval_fbuge,
748 gen_op_eval_fble,
749 gen_op_eval_fbule,
750 gen_op_eval_fbo,
751 },
752#ifdef TARGET_SPARC64
753 {
9bad0425 754 gen_op_eval_bn,
3475187d
FB		 755 gen_op_eval_fbne_fcc1,
756 gen_op_eval_fblg_fcc1,
757 gen_op_eval_fbul_fcc1,
758 gen_op_eval_fbl_fcc1,
759 gen_op_eval_fbug_fcc1,
760 gen_op_eval_fbg_fcc1,
761 gen_op_eval_fbu_fcc1,
9bad0425 762 gen_op_eval_ba,
3475187d
FB		 763 gen_op_eval_fbe_fcc1,
764 gen_op_eval_fbue_fcc1,
765 gen_op_eval_fbge_fcc1,
766 gen_op_eval_fbuge_fcc1,
767 gen_op_eval_fble_fcc1,
768 gen_op_eval_fbule_fcc1,
769 gen_op_eval_fbo_fcc1,
770 },
771 {
9bad0425 772 gen_op_eval_bn,
3475187d
FB		 773 gen_op_eval_fbne_fcc2,
774 gen_op_eval_fblg_fcc2,
775 gen_op_eval_fbul_fcc2,
776 gen_op_eval_fbl_fcc2,
777 gen_op_eval_fbug_fcc2,
778 gen_op_eval_fbg_fcc2,
779 gen_op_eval_fbu_fcc2,
9bad0425 780 gen_op_eval_ba,
3475187d
FB		 781 gen_op_eval_fbe_fcc2,
782 gen_op_eval_fbue_fcc2,
783 gen_op_eval_fbge_fcc2,
784 gen_op_eval_fbuge_fcc2,
785 gen_op_eval_fble_fcc2,
786 gen_op_eval_fbule_fcc2,
787 gen_op_eval_fbo_fcc2,
788 },
789 {
9bad0425 790 gen_op_eval_bn,
3475187d
FB		 791 gen_op_eval_fbne_fcc3,
792 gen_op_eval_fblg_fcc3,
793 gen_op_eval_fbul_fcc3,
794 gen_op_eval_fbl_fcc3,
795 gen_op_eval_fbug_fcc3,
796 gen_op_eval_fbg_fcc3,
797 gen_op_eval_fbu_fcc3,
9bad0425 798 gen_op_eval_ba,
3475187d
FB		 799 gen_op_eval_fbe_fcc3,
800 gen_op_eval_fbue_fcc3,
801 gen_op_eval_fbge_fcc3,
802 gen_op_eval_fbuge_fcc3,
803 gen_op_eval_fble_fcc3,
804 gen_op_eval_fbule_fcc3,
805 gen_op_eval_fbo_fcc3,
806 },
807#else
808 {}, {}, {},
809#endif
810};
7a3f1944 811
3475187d
FB		 812#ifdef TARGET_SPARC64
813static void gen_cond_reg(int cond)
e8af50a3
FB		 814{
815 switch (cond) {
e8af50a3 816 case 0x1:
3475187d 817 gen_op_eval_brz();
e8af50a3
FB		 818 break;
819 case 0x2:
3475187d 820 gen_op_eval_brlez();
e8af50a3
FB		 821 break;
822 case 0x3:
3475187d 823 gen_op_eval_brlz();
e8af50a3
FB		 824 break;
825 case 0x5:
3475187d 826 gen_op_eval_brnz();
e8af50a3
FB		 827 break;
828 case 0x6:
3475187d 829 gen_op_eval_brgz();
e8af50a3
FB		 830 break;
831 default:
3475187d
FB		 832 case 0x7:
833 gen_op_eval_brgez();
e8af50a3
FB		 834 break;
835 }
836}
3475187d 837#endif
cf495bcf 838
0bee699e 839/* XXX: potentially incorrect if dynamic npc */
3475187d 840static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 841{
cf495bcf 842 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 843 target_ulong target = dc->pc + offset;
3475187d 844
cf495bcf
FB		 845 if (cond == 0x0) {
846 /* unconditional not taken */
847 if (a) {
0bee699e 848 dc->pc = dc->npc + 4;
cf495bcf
FB		 849 dc->npc = dc->pc + 4;
850 } else {
851 dc->pc = dc->npc;
852 dc->npc = dc->pc + 4;
853 }
854 } else if (cond == 0x8) {
855 /* unconditional taken */
856 if (a) {
72cbca10 857 dc->pc = target;
cf495bcf
FB		 858 dc->npc = dc->pc + 4;
859 } else {
860 dc->pc = dc->npc;
72cbca10 861 dc->npc = target;
cf495bcf
FB		 862 }
863 } else {
72cbca10 864 flush_T2(dc);
3475187d 865 gen_cond[cc][cond]();
cf495bcf 866 if (a) {
46525e1f 867 gen_branch_a(dc, target, dc->npc);
cf495bcf 868 dc->is_br = 1;
cf495bcf
FB		 869 } else {
870 dc->pc = dc->npc;
72cbca10
FB		 871 dc->jump_pc[0] = target;
872 dc->jump_pc[1] = dc->npc + 4;
873 dc->npc = JUMP_PC;
cf495bcf
FB		 874 }
875 }
7a3f1944
FB		 876}
877
0bee699e 878/* XXX: potentially incorrect if dynamic npc */
3475187d 879static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 880{
881 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 882 target_ulong target = dc->pc + offset;
883
e8af50a3
FB		 884 if (cond == 0x0) {
885 /* unconditional not taken */
886 if (a) {
887 dc->pc = dc->npc + 4;
888 dc->npc = dc->pc + 4;
889 } else {
890 dc->pc = dc->npc;
891 dc->npc = dc->pc + 4;
892 }
893 } else if (cond == 0x8) {
894 /* unconditional taken */
895 if (a) {
896 dc->pc = target;
897 dc->npc = dc->pc + 4;
898 } else {
899 dc->pc = dc->npc;
900 dc->npc = target;
901 }
902 } else {
903 flush_T2(dc);
3475187d 904 gen_fcond[cc][cond]();
e8af50a3 905 if (a) {
46525e1f 906 gen_branch_a(dc, target, dc->npc);
e8af50a3
FB		 907 dc->is_br = 1;
908 } else {
909 dc->pc = dc->npc;
910 dc->jump_pc[0] = target;
911 dc->jump_pc[1] = dc->npc + 4;
912 dc->npc = JUMP_PC;
913 }
914 }
915}
916
3475187d
FB		 917#ifdef TARGET_SPARC64
918/* XXX: potentially incorrect if dynamic npc */
919static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
7a3f1944 920{
3475187d
FB		 921 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
922 target_ulong target = dc->pc + offset;
923
924 flush_T2(dc);
925 gen_cond_reg(cond);
926 if (a) {
46525e1f 927 gen_branch_a(dc, target, dc->npc);
3475187d
FB		 928 dc->is_br = 1;
929 } else {
930 dc->pc = dc->npc;
931 dc->jump_pc[0] = target;
932 dc->jump_pc[1] = dc->npc + 4;
933 dc->npc = JUMP_PC;
934 }
7a3f1944
FB		 935}
936
3475187d
FB		 937static GenOpFunc * const gen_fcmps[4] = {
938 gen_op_fcmps,
939 gen_op_fcmps_fcc1,
940 gen_op_fcmps_fcc2,
941 gen_op_fcmps_fcc3,
942};
943
944static GenOpFunc * const gen_fcmpd[4] = {
945 gen_op_fcmpd,
946 gen_op_fcmpd_fcc1,
947 gen_op_fcmpd_fcc2,
948 gen_op_fcmpd_fcc3,
949};
417454b0
BS		 950
951static GenOpFunc * const gen_fcmpes[4] = {
952 gen_op_fcmpes,
953 gen_op_fcmpes_fcc1,
954 gen_op_fcmpes_fcc2,
955 gen_op_fcmpes_fcc3,
956};
957
958static GenOpFunc * const gen_fcmped[4] = {
959 gen_op_fcmped,
960 gen_op_fcmped_fcc1,
961 gen_op_fcmped_fcc2,
962 gen_op_fcmped_fcc3,
963};
964
3475187d
FB		 965#endif
966
a80dde08
FB		 967static int gen_trap_ifnofpu(DisasContext * dc)
968{
969#if !defined(CONFIG_USER_ONLY)
970 if (!dc->fpu_enabled) {
971 save_state(dc);
972 gen_op_exception(TT_NFPU_INSN);
973 dc->is_br = 1;
974 return 1;
975 }
976#endif
977 return 0;
978}
979
0bee699e 980/* before an instruction, dc->pc must be static */
cf495bcf
FB		 981static void disas_sparc_insn(DisasContext * dc)
982{
983 unsigned int insn, opc, rs1, rs2, rd;
7a3f1944 984
0fa85d43 985 insn = ldl_code(dc->pc);
cf495bcf 986 opc = GET_FIELD(insn, 0, 1);
7a3f1944 987
cf495bcf
FB		 988 rd = GET_FIELD(insn, 2, 6);
989 switch (opc) {
990 case 0: /* branches/sethi */
991 {
992 unsigned int xop = GET_FIELD(insn, 7, 9);
af7bf89b 993 int32_t target;
cf495bcf 994 switch (xop) {
3475187d 995#ifdef TARGET_SPARC64
af7bf89b 996 case 0x1: /* V9 BPcc */
3475187d
FB		 997 {
998 int cc;
999
1000 target = GET_FIELD_SP(insn, 0, 18);
3475187d 1001 target = sign_extend(target, 18);
ee6c0b51 1002 target <<= 2;
3475187d
FB		 1003 cc = GET_FIELD_SP(insn, 20, 21);
1004 if (cc == 0)
1005 do_branch(dc, target, insn, 0);
1006 else if (cc == 2)
1007 do_branch(dc, target, insn, 1);
1008 else
1009 goto illegal_insn;
1010 goto jmp_insn;
1011 }
af7bf89b 1012 case 0x3: /* V9 BPr */
3475187d
FB		 1013 {
1014 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 1015 (GET_FIELD_SP(insn, 20, 21) << 14);
3475187d 1016 target = sign_extend(target, 16);
ee6c0b51 1017 target <<= 2;
3475187d 1018 rs1 = GET_FIELD(insn, 13, 17);
83469015 1019 gen_movl_reg_T0(rs1);
3475187d
FB		 1020 do_branch_reg(dc, target, insn);
1021 goto jmp_insn;
1022 }
af7bf89b 1023 case 0x5: /* V9 FBPcc */
3475187d
FB		 1024 {
1025 int cc = GET_FIELD_SP(insn, 20, 21);
a80dde08
FB		 1026 if (gen_trap_ifnofpu(dc))
1027 goto jmp_insn;
3475187d 1028 target = GET_FIELD_SP(insn, 0, 18);
3475187d 1029 target = sign_extend(target, 19);
ee6c0b51 1030 target <<= 2;
3475187d
FB		 1031 do_fbranch(dc, target, insn, cc);
1032 goto jmp_insn;
1033 }
a4d17f19
BS		 1034#else
1035 case 0x7: /* CBN+x */
1036 {
1037 goto ncp_insn;
1038 }
3475187d 1039#endif
cf495bcf 1040 case 0x2: /* BN+x */
7a3f1944 1041 {
3475187d 1042 target = GET_FIELD(insn, 10, 31);
cf495bcf 1043 target = sign_extend(target, 22);
ee6c0b51 1044 target <<= 2;
3475187d 1045 do_branch(dc, target, insn, 0);
cf495bcf 1046 goto jmp_insn;
7a3f1944 1047 }
e8af50a3
FB		 1048 case 0x6: /* FBN+x */
1049 {
a80dde08
FB		 1050 if (gen_trap_ifnofpu(dc))
1051 goto jmp_insn;
3475187d 1052 target = GET_FIELD(insn, 10, 31);
e8af50a3 1053 target = sign_extend(target, 22);
ee6c0b51 1054 target <<= 2;
3475187d 1055 do_fbranch(dc, target, insn, 0);
e8af50a3
FB		 1056 goto jmp_insn;
1057 }
cf495bcf 1058 case 0x4: /* SETHI */
e80cfcfc
FB		 1059#define OPTIM
1060#if defined(OPTIM)
1061 if (rd) { // nop
1062#endif
3475187d
FB		 1063 uint32_t value = GET_FIELD(insn, 10, 31);
1064 gen_movl_imm_T0(value << 10);
e80cfcfc
FB		 1065 gen_movl_T0_reg(rd);
1066#if defined(OPTIM)
1067 }
1068#endif
cf495bcf 1069 break;
3475187d
FB		 1070 case 0x0: /* UNIMPL */
1071 default:
1072 goto illegal_insn;
cf495bcf
FB		 1073 }
1074 break;
1075 }
af7bf89b 1076 break;
cf495bcf
FB		 1077 case 1:
1078 /*CALL*/ {
af7bf89b 1079 target_long target = GET_FIELDs(insn, 2, 31) << 2;
cf495bcf 1080
83469015
FB		 1081#ifdef TARGET_SPARC64
1082 if (dc->pc == (uint32_t)dc->pc) {
1083 gen_op_movl_T0_im(dc->pc);
1084 } else {
1085 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1086 }
1087#else
af7bf89b 1088 gen_op_movl_T0_im(dc->pc);
83469015 1089#endif
cf495bcf 1090 gen_movl_T0_reg(15);
af7bf89b 1091 target += dc->pc;
0bee699e 1092 gen_mov_pc_npc(dc);
72cbca10 1093 dc->npc = target;
cf495bcf
FB		 1094 }
1095 goto jmp_insn;
1096 case 2: /* FPU & Logical Operations */
1097 {
1098 unsigned int xop = GET_FIELD(insn, 7, 12);
1099 if (xop == 0x3a) { /* generate trap */
1100 int cond;
3475187d 1101
cf495bcf
FB		 1102 rs1 = GET_FIELD(insn, 13, 17);
1103 gen_movl_reg_T0(rs1);
1104 if (IS_IMM) {
e8af50a3 1105 rs2 = GET_FIELD(insn, 25, 31);
e80cfcfc 1106#if defined(OPTIM)
e8af50a3 1107 if (rs2 != 0) {
e80cfcfc 1108#endif
3475187d 1109 gen_movl_simm_T1(rs2);
e80cfcfc
FB		 1110 gen_op_add_T1_T0();
1111#if defined(OPTIM)
e8af50a3 1112 }
e80cfcfc 1113#endif
cf495bcf
FB		 1114 } else {
1115 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc
FB		 1116#if defined(OPTIM)
1117 if (rs2 != 0) {
1118#endif
1119 gen_movl_reg_T1(rs2);
1120 gen_op_add_T1_T0();
1121#if defined(OPTIM)
1122 }
1123#endif
cf495bcf 1124 }
cf495bcf
FB		 1125 cond = GET_FIELD(insn, 3, 6);
1126 if (cond == 0x8) {
a80dde08 1127 save_state(dc);
cf495bcf 1128 gen_op_trap_T0();
af7bf89b 1129 } else if (cond != 0) {
3475187d
FB		 1130#ifdef TARGET_SPARC64
1131 /* V9 icc/xcc */
1132 int cc = GET_FIELD_SP(insn, 11, 12);
a80dde08
FB		 1133 flush_T2(dc);
1134 save_state(dc);
3475187d
FB		 1135 if (cc == 0)
1136 gen_cond[0][cond]();
1137 else if (cc == 2)
1138 gen_cond[1][cond]();
1139 else
1140 goto illegal_insn;
1141#else
a80dde08
FB		 1142 flush_T2(dc);
1143 save_state(dc);
3475187d
FB		 1144 gen_cond[0][cond]();
1145#endif
cf495bcf
FB		 1146 gen_op_trapcc_T0();
1147 }
a80dde08
FB		 1148 gen_op_next_insn();
1149 gen_op_movl_T0_0();
1150 gen_op_exit_tb();
1151 dc->is_br = 1;
1152 goto jmp_insn;
cf495bcf
FB		 1153 } else if (xop == 0x28) {
1154 rs1 = GET_FIELD(insn, 13, 17);
1155 switch(rs1) {
1156 case 0: /* rdy */
65fe7b09
BS		 1157#ifndef TARGET_SPARC64
1158 case 0x01 ... 0x0e: /* undefined in the SPARCv8
1159 manual, rdy on the microSPARC
1160 II */
1161 case 0x0f: /* stbar in the SPARCv8 manual,
1162 rdy on the microSPARC II */
1163 case 0x10 ... 0x1f: /* implementation-dependent in the
1164 SPARCv8 manual, rdy on the
1165 microSPARC II */
1166#endif
1167 gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
cf495bcf
FB		 1168 gen_movl_T0_reg(rd);
1169 break;
3475187d 1170#ifdef TARGET_SPARC64
af7bf89b 1171 case 0x2: /* V9 rdccr */
3475187d
FB		 1172 gen_op_rdccr();
1173 gen_movl_T0_reg(rd);
1174 break;
af7bf89b 1175 case 0x3: /* V9 rdasi */
3475187d
FB		 1176 gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
1177 gen_movl_T0_reg(rd);
1178 break;
af7bf89b 1179 case 0x4: /* V9 rdtick */
3475187d
FB		 1180 gen_op_rdtick();
1181 gen_movl_T0_reg(rd);
1182 break;
af7bf89b 1183 case 0x5: /* V9 rdpc */
ded3ab80
PB		 1184 if (dc->pc == (uint32_t)dc->pc) {
1185 gen_op_movl_T0_im(dc->pc);
1186 } else {
1187 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1188 }
3475187d
FB		 1189 gen_movl_T0_reg(rd);
1190 break;
af7bf89b 1191 case 0x6: /* V9 rdfprs */
3475187d
FB		 1192 gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
1193 gen_movl_T0_reg(rd);
1194 break;
65fe7b09
BS		 1195 case 0xf: /* V9 membar */
1196 break; /* no effect */
725cb90b
FB		 1197 case 0x13: /* Graphics Status */
1198 if (gen_trap_ifnofpu(dc))
1199 goto jmp_insn;
1200 gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
1201 gen_movl_T0_reg(rd);
1202 break;
83469015
FB		 1203 case 0x17: /* Tick compare */
1204 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
1205 gen_movl_T0_reg(rd);
1206 break;
1207 case 0x18: /* System tick */
20c9f095 1208 gen_op_rdstick();
83469015
FB		 1209 gen_movl_T0_reg(rd);
1210 break;
1211 case 0x19: /* System tick compare */
1212 gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
1213 gen_movl_T0_reg(rd);
1214 break;
1215 case 0x10: /* Performance Control */
1216 case 0x11: /* Performance Instrumentation Counter */
1217 case 0x12: /* Dispatch Control */
83469015
FB		 1218 case 0x14: /* Softint set, WO */
1219 case 0x15: /* Softint clear, WO */
1220 case 0x16: /* Softint write */
3475187d
FB		 1221#endif
1222 default:
cf495bcf
FB		 1223 goto illegal_insn;
1224 }
e8af50a3 1225#if !defined(CONFIG_USER_ONLY)
e9ebed4d 1226 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 1227#ifndef TARGET_SPARC64
e8af50a3
FB		 1228 if (!supervisor(dc))
1229 goto priv_insn;
1230 gen_op_rdpsr();
e9ebed4d
BS		 1231#else
1232 if (!hypervisor(dc))
1233 goto priv_insn;
1234 rs1 = GET_FIELD(insn, 13, 17);
1235 switch (rs1) {
1236 case 0: // hpstate
1237 // gen_op_rdhpstate();
1238 break;
1239 case 1: // htstate
1240 // gen_op_rdhtstate();
1241 break;
1242 case 3: // hintp
1243 gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp));
1244 break;
1245 case 5: // htba
1246 gen_op_movl_T0_env(offsetof(CPUSPARCState, htba));
1247 break;
1248 case 6: // hver
1249 gen_op_movl_T0_env(offsetof(CPUSPARCState, hver));
1250 break;
1251 case 31: // hstick_cmpr
1252 gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
1253 break;
1254 default:
1255 goto illegal_insn;
1256 }
1257#endif
e8af50a3
FB		 1258 gen_movl_T0_reg(rd);
1259 break;
3475187d 1260 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
e8af50a3
FB		 1261 if (!supervisor(dc))
1262 goto priv_insn;
3475187d
FB		 1263#ifdef TARGET_SPARC64
1264 rs1 = GET_FIELD(insn, 13, 17);
1265 switch (rs1) {
1266 case 0: // tpc
1267 gen_op_rdtpc();
1268 break;
1269 case 1: // tnpc
1270 gen_op_rdtnpc();
1271 break;
1272 case 2: // tstate
1273 gen_op_rdtstate();
1274 break;
1275 case 3: // tt
1276 gen_op_rdtt();
1277 break;
1278 case 4: // tick
1279 gen_op_rdtick();
1280 break;
1281 case 5: // tba
1282 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1283 break;
1284 case 6: // pstate
1285 gen_op_rdpstate();
1286 break;
1287 case 7: // tl
1288 gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1289 break;
1290 case 8: // pil
1291 gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1292 break;
1293 case 9: // cwp
1294 gen_op_rdcwp();
1295 break;
1296 case 10: // cansave
1297 gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1298 break;
1299 case 11: // canrestore
1300 gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1301 break;
1302 case 12: // cleanwin
1303 gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1304 break;
1305 case 13: // otherwin
1306 gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1307 break;
1308 case 14: // wstate
1309 gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1310 break;
e9ebed4d
BS		 1311 case 16: // UA2005 gl
1312 gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
1313 break;
1314 case 26: // UA2005 strand status
1315 if (!hypervisor(dc))
1316 goto priv_insn;
1317 gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
1318 break;
3475187d
FB		 1319 case 31: // ver
1320 gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1321 break;
1322 case 15: // fq
1323 default:
1324 goto illegal_insn;
1325 }
1326#else
1327 gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
1328#endif
e8af50a3
FB		 1329 gen_movl_T0_reg(rd);
1330 break;
3475187d
FB		 1331 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1332#ifdef TARGET_SPARC64
1333 gen_op_flushw();
1334#else
e8af50a3
FB		 1335 if (!supervisor(dc))
1336 goto priv_insn;
3475187d 1337 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
e8af50a3 1338 gen_movl_T0_reg(rd);
3475187d 1339#endif
e8af50a3
FB		 1340 break;
1341#endif
e80cfcfc 1342 } else if (xop == 0x34) { /* FPU Operations */
a80dde08
FB		 1343 if (gen_trap_ifnofpu(dc))
1344 goto jmp_insn;
417454b0 1345 gen_op_clear_ieee_excp_and_FTT();
e8af50a3
FB		 1346 rs1 = GET_FIELD(insn, 13, 17);
1347 rs2 = GET_FIELD(insn, 27, 31);
1348 xop = GET_FIELD(insn, 18, 26);
1349 switch (xop) {
1350 case 0x1: /* fmovs */
1351 gen_op_load_fpr_FT0(rs2);
1352 gen_op_store_FT0_fpr(rd);
1353 break;
1354 case 0x5: /* fnegs */
1355 gen_op_load_fpr_FT1(rs2);
1356 gen_op_fnegs();
1357 gen_op_store_FT0_fpr(rd);
1358 break;
1359 case 0x9: /* fabss */
1360 gen_op_load_fpr_FT1(rs2);
1361 gen_op_fabss();
1362 gen_op_store_FT0_fpr(rd);
1363 break;
1364 case 0x29: /* fsqrts */
1365 gen_op_load_fpr_FT1(rs2);
1366 gen_op_fsqrts();
1367 gen_op_store_FT0_fpr(rd);
1368 break;
1369 case 0x2a: /* fsqrtd */
3475187d 1370 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1371 gen_op_fsqrtd();
3475187d 1372 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1373 break;
e80cfcfc
FB		 1374 case 0x2b: /* fsqrtq */
1375 goto nfpu_insn;
e8af50a3
FB		 1376 case 0x41:
1377 gen_op_load_fpr_FT0(rs1);
1378 gen_op_load_fpr_FT1(rs2);
1379 gen_op_fadds();
1380 gen_op_store_FT0_fpr(rd);
1381 break;
1382 case 0x42:
3475187d
FB		 1383 gen_op_load_fpr_DT0(DFPREG(rs1));
1384 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1385 gen_op_faddd();
3475187d 1386 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1387 break;
e80cfcfc
FB		 1388 case 0x43: /* faddq */
1389 goto nfpu_insn;
e8af50a3
FB		 1390 case 0x45:
1391 gen_op_load_fpr_FT0(rs1);
1392 gen_op_load_fpr_FT1(rs2);
1393 gen_op_fsubs();
1394 gen_op_store_FT0_fpr(rd);
1395 break;
1396 case 0x46:
3475187d
FB		 1397 gen_op_load_fpr_DT0(DFPREG(rs1));
1398 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1399 gen_op_fsubd();
3475187d 1400 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1401 break;
e80cfcfc
FB		 1402 case 0x47: /* fsubq */
1403 goto nfpu_insn;
e8af50a3
FB		 1404 case 0x49:
1405 gen_op_load_fpr_FT0(rs1);
1406 gen_op_load_fpr_FT1(rs2);
1407 gen_op_fmuls();
1408 gen_op_store_FT0_fpr(rd);
1409 break;
1410 case 0x4a:
3475187d
FB		 1411 gen_op_load_fpr_DT0(DFPREG(rs1));
1412 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3
FB		 1413 gen_op_fmuld();
1414 gen_op_store_DT0_fpr(rd);
1415 break;
e80cfcfc
FB		 1416 case 0x4b: /* fmulq */
1417 goto nfpu_insn;
e8af50a3
FB		 1418 case 0x4d:
1419 gen_op_load_fpr_FT0(rs1);
1420 gen_op_load_fpr_FT1(rs2);
1421 gen_op_fdivs();
1422 gen_op_store_FT0_fpr(rd);
1423 break;
1424 case 0x4e:
3475187d
FB		 1425 gen_op_load_fpr_DT0(DFPREG(rs1));
1426 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1427 gen_op_fdivd();
3475187d 1428 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1429 break;
e80cfcfc
FB		 1430 case 0x4f: /* fdivq */
1431 goto nfpu_insn;
e8af50a3
FB		 1432 case 0x69:
1433 gen_op_load_fpr_FT0(rs1);
1434 gen_op_load_fpr_FT1(rs2);
1435 gen_op_fsmuld();
3475187d 1436 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1437 break;
e80cfcfc
FB		 1438 case 0x6e: /* fdmulq */
1439 goto nfpu_insn;
e8af50a3
FB		 1440 case 0xc4:
1441 gen_op_load_fpr_FT1(rs2);
1442 gen_op_fitos();
1443 gen_op_store_FT0_fpr(rd);
1444 break;
1445 case 0xc6:
3475187d 1446 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3
FB		 1447 gen_op_fdtos();
1448 gen_op_store_FT0_fpr(rd);
1449 break;
e80cfcfc
FB		 1450 case 0xc7: /* fqtos */
1451 goto nfpu_insn;
e8af50a3
FB		 1452 case 0xc8:
1453 gen_op_load_fpr_FT1(rs2);
1454 gen_op_fitod();
3475187d 1455 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3
FB		 1456 break;
1457 case 0xc9:
1458 gen_op_load_fpr_FT1(rs2);
1459 gen_op_fstod();
3475187d 1460 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1461 break;
e80cfcfc
FB		 1462 case 0xcb: /* fqtod */
1463 goto nfpu_insn;
1464 case 0xcc: /* fitoq */
1465 goto nfpu_insn;
1466 case 0xcd: /* fstoq */
1467 goto nfpu_insn;
1468 case 0xce: /* fdtoq */
1469 goto nfpu_insn;
e8af50a3
FB		 1470 case 0xd1:
1471 gen_op_load_fpr_FT1(rs2);
1472 gen_op_fstoi();
1473 gen_op_store_FT0_fpr(rd);
1474 break;
1475 case 0xd2:
1476 gen_op_load_fpr_DT1(rs2);
1477 gen_op_fdtoi();
1478 gen_op_store_FT0_fpr(rd);
1479 break;
e80cfcfc
FB		 1480 case 0xd3: /* fqtoi */
1481 goto nfpu_insn;
3475187d 1482#ifdef TARGET_SPARC64
af7bf89b 1483 case 0x2: /* V9 fmovd */
3475187d
FB		 1484 gen_op_load_fpr_DT0(DFPREG(rs2));
1485 gen_op_store_DT0_fpr(DFPREG(rd));
1486 break;
af7bf89b 1487 case 0x6: /* V9 fnegd */
3475187d
FB		 1488 gen_op_load_fpr_DT1(DFPREG(rs2));
1489 gen_op_fnegd();
1490 gen_op_store_DT0_fpr(DFPREG(rd));
1491 break;
af7bf89b 1492 case 0xa: /* V9 fabsd */
3475187d
FB		 1493 gen_op_load_fpr_DT1(DFPREG(rs2));
1494 gen_op_fabsd();
1495 gen_op_store_DT0_fpr(DFPREG(rd));
1496 break;
af7bf89b 1497 case 0x81: /* V9 fstox */
3475187d
FB		 1498 gen_op_load_fpr_FT1(rs2);
1499 gen_op_fstox();
1500 gen_op_store_DT0_fpr(DFPREG(rd));
1501 break;
af7bf89b 1502 case 0x82: /* V9 fdtox */
3475187d
FB		 1503 gen_op_load_fpr_DT1(DFPREG(rs2));
1504 gen_op_fdtox();
1505 gen_op_store_DT0_fpr(DFPREG(rd));
1506 break;
af7bf89b 1507 case 0x84: /* V9 fxtos */
3475187d
FB		 1508 gen_op_load_fpr_DT1(DFPREG(rs2));
1509 gen_op_fxtos();
1510 gen_op_store_FT0_fpr(rd);
1511 break;
af7bf89b 1512 case 0x88: /* V9 fxtod */
3475187d
FB		 1513 gen_op_load_fpr_DT1(DFPREG(rs2));
1514 gen_op_fxtod();
1515 gen_op_store_DT0_fpr(DFPREG(rd));
1516 break;
af7bf89b
FB		 1517 case 0x3: /* V9 fmovq */
1518 case 0x7: /* V9 fnegq */
1519 case 0xb: /* V9 fabsq */
1520 case 0x83: /* V9 fqtox */
1521 case 0x8c: /* V9 fxtoq */
3475187d
FB		 1522 goto nfpu_insn;
1523#endif
1524 default:
e8af50a3
FB		 1525 goto illegal_insn;
1526 }
e80cfcfc 1527 } else if (xop == 0x35) { /* FPU Operations */
3475187d
FB		 1528#ifdef TARGET_SPARC64
1529 int cond;
1530#endif
a80dde08
FB		 1531 if (gen_trap_ifnofpu(dc))
1532 goto jmp_insn;
417454b0 1533 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 1534 rs1 = GET_FIELD(insn, 13, 17);
e80cfcfc
FB		 1535 rs2 = GET_FIELD(insn, 27, 31);
1536 xop = GET_FIELD(insn, 18, 26);
3475187d
FB		 1537#ifdef TARGET_SPARC64
1538 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
1539 cond = GET_FIELD_SP(insn, 14, 17);
1540 gen_op_load_fpr_FT0(rd);
1541 gen_op_load_fpr_FT1(rs2);
1542 rs1 = GET_FIELD(insn, 13, 17);
1543 gen_movl_reg_T0(rs1);
1544 flush_T2(dc);
1545 gen_cond_reg(cond);
1546 gen_op_fmovs_cc();
1547 gen_op_store_FT0_fpr(rd);
1548 break;
1549 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
1550 cond = GET_FIELD_SP(insn, 14, 17);
1551 gen_op_load_fpr_DT0(rd);
1552 gen_op_load_fpr_DT1(rs2);
1553 flush_T2(dc);
1554 rs1 = GET_FIELD(insn, 13, 17);
1555 gen_movl_reg_T0(rs1);
1556 gen_cond_reg(cond);
1557 gen_op_fmovs_cc();
1558 gen_op_store_DT0_fpr(rd);
1559 break;
1560 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1561 goto nfpu_insn;
1562 }
1563#endif
e80cfcfc 1564 switch (xop) {
3475187d
FB		 1565#ifdef TARGET_SPARC64
1566 case 0x001: /* V9 fmovscc %fcc0 */
1567 cond = GET_FIELD_SP(insn, 14, 17);
1568 gen_op_load_fpr_FT0(rd);
1569 gen_op_load_fpr_FT1(rs2);
1570 flush_T2(dc);
1571 gen_fcond[0][cond]();
1572 gen_op_fmovs_cc();
1573 gen_op_store_FT0_fpr(rd);
1574 break;
1575 case 0x002: /* V9 fmovdcc %fcc0 */
1576 cond = GET_FIELD_SP(insn, 14, 17);
1577 gen_op_load_fpr_DT0(rd);
1578 gen_op_load_fpr_DT1(rs2);
1579 flush_T2(dc);
1580 gen_fcond[0][cond]();
1581 gen_op_fmovd_cc();
1582 gen_op_store_DT0_fpr(rd);
1583 break;
1584 case 0x003: /* V9 fmovqcc %fcc0 */
1585 goto nfpu_insn;
1586 case 0x041: /* V9 fmovscc %fcc1 */
1587 cond = GET_FIELD_SP(insn, 14, 17);
1588 gen_op_load_fpr_FT0(rd);
1589 gen_op_load_fpr_FT1(rs2);
1590 flush_T2(dc);
1591 gen_fcond[1][cond]();
1592 gen_op_fmovs_cc();
1593 gen_op_store_FT0_fpr(rd);
1594 break;
1595 case 0x042: /* V9 fmovdcc %fcc1 */
1596 cond = GET_FIELD_SP(insn, 14, 17);
1597 gen_op_load_fpr_DT0(rd);
1598 gen_op_load_fpr_DT1(rs2);
1599 flush_T2(dc);
1600 gen_fcond[1][cond]();
1601 gen_op_fmovd_cc();
1602 gen_op_store_DT0_fpr(rd);
1603 break;
1604 case 0x043: /* V9 fmovqcc %fcc1 */
1605 goto nfpu_insn;
1606 case 0x081: /* V9 fmovscc %fcc2 */
1607 cond = GET_FIELD_SP(insn, 14, 17);
1608 gen_op_load_fpr_FT0(rd);
1609 gen_op_load_fpr_FT1(rs2);
1610 flush_T2(dc);
1611 gen_fcond[2][cond]();
1612 gen_op_fmovs_cc();
1613 gen_op_store_FT0_fpr(rd);
1614 break;
1615 case 0x082: /* V9 fmovdcc %fcc2 */
1616 cond = GET_FIELD_SP(insn, 14, 17);
1617 gen_op_load_fpr_DT0(rd);
1618 gen_op_load_fpr_DT1(rs2);
1619 flush_T2(dc);
1620 gen_fcond[2][cond]();
1621 gen_op_fmovd_cc();
1622 gen_op_store_DT0_fpr(rd);
1623 break;
1624 case 0x083: /* V9 fmovqcc %fcc2 */
1625 goto nfpu_insn;
1626 case 0x0c1: /* V9 fmovscc %fcc3 */
1627 cond = GET_FIELD_SP(insn, 14, 17);
1628 gen_op_load_fpr_FT0(rd);
1629 gen_op_load_fpr_FT1(rs2);
1630 flush_T2(dc);
1631 gen_fcond[3][cond]();
1632 gen_op_fmovs_cc();
1633 gen_op_store_FT0_fpr(rd);
1634 break;
1635 case 0x0c2: /* V9 fmovdcc %fcc3 */
1636 cond = GET_FIELD_SP(insn, 14, 17);
1637 gen_op_load_fpr_DT0(rd);
1638 gen_op_load_fpr_DT1(rs2);
1639 flush_T2(dc);
1640 gen_fcond[3][cond]();
1641 gen_op_fmovd_cc();
1642 gen_op_store_DT0_fpr(rd);
1643 break;
1644 case 0x0c3: /* V9 fmovqcc %fcc3 */
1645 goto nfpu_insn;
1646 case 0x101: /* V9 fmovscc %icc */
1647 cond = GET_FIELD_SP(insn, 14, 17);
1648 gen_op_load_fpr_FT0(rd);
1649 gen_op_load_fpr_FT1(rs2);
1650 flush_T2(dc);
1651 gen_cond[0][cond]();
1652 gen_op_fmovs_cc();
1653 gen_op_store_FT0_fpr(rd);
1654 break;
1655 case 0x102: /* V9 fmovdcc %icc */
1656 cond = GET_FIELD_SP(insn, 14, 17);
1657 gen_op_load_fpr_DT0(rd);
1658 gen_op_load_fpr_DT1(rs2);
1659 flush_T2(dc);
1660 gen_cond[0][cond]();
1661 gen_op_fmovd_cc();
1662 gen_op_store_DT0_fpr(rd);
1663 break;
1664 case 0x103: /* V9 fmovqcc %icc */
1665 goto nfpu_insn;
1666 case 0x181: /* V9 fmovscc %xcc */
1667 cond = GET_FIELD_SP(insn, 14, 17);
1668 gen_op_load_fpr_FT0(rd);
1669 gen_op_load_fpr_FT1(rs2);
1670 flush_T2(dc);
1671 gen_cond[1][cond]();
1672 gen_op_fmovs_cc();
1673 gen_op_store_FT0_fpr(rd);
1674 break;
1675 case 0x182: /* V9 fmovdcc %xcc */
1676 cond = GET_FIELD_SP(insn, 14, 17);
1677 gen_op_load_fpr_DT0(rd);
1678 gen_op_load_fpr_DT1(rs2);
1679 flush_T2(dc);
1680 gen_cond[1][cond]();
1681 gen_op_fmovd_cc();
1682 gen_op_store_DT0_fpr(rd);
1683 break;
1684 case 0x183: /* V9 fmovqcc %xcc */
1685 goto nfpu_insn;
1686#endif
1687 case 0x51: /* V9 %fcc */
e80cfcfc
FB		 1688 gen_op_load_fpr_FT0(rs1);
1689 gen_op_load_fpr_FT1(rs2);
3475187d
FB		 1690#ifdef TARGET_SPARC64
1691 gen_fcmps[rd & 3]();
1692#else
e80cfcfc 1693 gen_op_fcmps();
3475187d 1694#endif
e80cfcfc 1695 break;
3475187d
FB		 1696 case 0x52: /* V9 %fcc */
1697 gen_op_load_fpr_DT0(DFPREG(rs1));
1698 gen_op_load_fpr_DT1(DFPREG(rs2));
1699#ifdef TARGET_SPARC64
1700 gen_fcmpd[rd & 3]();
1701#else
e80cfcfc 1702 gen_op_fcmpd();
3475187d 1703#endif
e80cfcfc
FB		 1704 break;
1705 case 0x53: /* fcmpq */
1706 goto nfpu_insn;
3475187d 1707 case 0x55: /* fcmpes, V9 %fcc */
e80cfcfc
FB		 1708 gen_op_load_fpr_FT0(rs1);
1709 gen_op_load_fpr_FT1(rs2);
3475187d 1710#ifdef TARGET_SPARC64
417454b0 1711 gen_fcmpes[rd & 3]();
3475187d 1712#else
417454b0 1713 gen_op_fcmpes();
3475187d 1714#endif
e80cfcfc 1715 break;
3475187d
FB		 1716 case 0x56: /* fcmped, V9 %fcc */
1717 gen_op_load_fpr_DT0(DFPREG(rs1));
1718 gen_op_load_fpr_DT1(DFPREG(rs2));
1719#ifdef TARGET_SPARC64
417454b0 1720 gen_fcmped[rd & 3]();
3475187d 1721#else
417454b0 1722 gen_op_fcmped();
3475187d 1723#endif
e80cfcfc
FB		 1724 break;
1725 case 0x57: /* fcmpeq */
1726 goto nfpu_insn;
1727 default:
1728 goto illegal_insn;
1729 }
1730#if defined(OPTIM)
1731 } else if (xop == 0x2) {
1732 // clr/mov shortcut
1733
1734 rs1 = GET_FIELD(insn, 13, 17);
1735 if (rs1 == 0) {
1736 // or %g0, x, y -> mov T1, x; mov y, T1
1737 if (IS_IMM) { /* immediate */
1738 rs2 = GET_FIELDs(insn, 19, 31);
3475187d 1739 gen_movl_simm_T1(rs2);
e80cfcfc
FB		 1740 } else { /* register */
1741 rs2 = GET_FIELD(insn, 27, 31);
1742 gen_movl_reg_T1(rs2);
1743 }
1744 gen_movl_T1_reg(rd);
1745 } else {
1746 gen_movl_reg_T0(rs1);
1747 if (IS_IMM) { /* immediate */
1748 // or x, #0, y -> mov T1, x; mov y, T1
1749 rs2 = GET_FIELDs(insn, 19, 31);
1750 if (rs2 != 0) {
3475187d 1751 gen_movl_simm_T1(rs2);
e80cfcfc
FB		 1752 gen_op_or_T1_T0();
1753 }
1754 } else { /* register */
1755 // or x, %g0, y -> mov T1, x; mov y, T1
1756 rs2 = GET_FIELD(insn, 27, 31);
1757 if (rs2 != 0) {
1758 gen_movl_reg_T1(rs2);
1759 gen_op_or_T1_T0();
1760 }
1761 }
1762 gen_movl_T0_reg(rd);
1763 }
83469015
FB		 1764#endif
1765#ifdef TARGET_SPARC64
8a08f9a8 1766 } else if (xop == 0x25) { /* sll, V9 sllx */
83469015
FB		 1767 rs1 = GET_FIELD(insn, 13, 17);
1768 gen_movl_reg_T0(rs1);
1769 if (IS_IMM) { /* immediate */
1770 rs2 = GET_FIELDs(insn, 20, 31);
1771 gen_movl_simm_T1(rs2);
1772 } else { /* register */
1773 rs2 = GET_FIELD(insn, 27, 31);
1774 gen_movl_reg_T1(rs2);
1775 }
8a08f9a8
BS		 1776 if (insn & (1 << 12))
1777 gen_op_sllx();
1778 else
1779 gen_op_sll();
83469015
FB		 1780 gen_movl_T0_reg(rd);
1781 } else if (xop == 0x26) { /* srl, V9 srlx */
1782 rs1 = GET_FIELD(insn, 13, 17);
1783 gen_movl_reg_T0(rs1);
1784 if (IS_IMM) { /* immediate */
1785 rs2 = GET_FIELDs(insn, 20, 31);
1786 gen_movl_simm_T1(rs2);
1787 } else { /* register */
1788 rs2 = GET_FIELD(insn, 27, 31);
1789 gen_movl_reg_T1(rs2);
1790 }
1791 if (insn & (1 << 12))
1792 gen_op_srlx();
1793 else
1794 gen_op_srl();
1795 gen_movl_T0_reg(rd);
1796 } else if (xop == 0x27) { /* sra, V9 srax */
1797 rs1 = GET_FIELD(insn, 13, 17);
1798 gen_movl_reg_T0(rs1);
1799 if (IS_IMM) { /* immediate */
1800 rs2 = GET_FIELDs(insn, 20, 31);
1801 gen_movl_simm_T1(rs2);
1802 } else { /* register */
1803 rs2 = GET_FIELD(insn, 27, 31);
1804 gen_movl_reg_T1(rs2);
1805 }
1806 if (insn & (1 << 12))
1807 gen_op_srax();
1808 else
1809 gen_op_sra();
1810 gen_movl_T0_reg(rd);
e80cfcfc 1811#endif
fcc72045 1812 } else if (xop < 0x36) {
e80cfcfc
FB		 1813 rs1 = GET_FIELD(insn, 13, 17);
1814 gen_movl_reg_T0(rs1);
1815 if (IS_IMM) { /* immediate */
cf495bcf 1816 rs2 = GET_FIELDs(insn, 19, 31);
3475187d 1817 gen_movl_simm_T1(rs2);
cf495bcf
FB		 1818 } else { /* register */
1819 rs2 = GET_FIELD(insn, 27, 31);
1820 gen_movl_reg_T1(rs2);
1821 }
1822 if (xop < 0x20) {
1823 switch (xop & ~0x10) {
1824 case 0x0:
1825 if (xop & 0x10)
1826 gen_op_add_T1_T0_cc();
1827 else
1828 gen_op_add_T1_T0();
1829 break;
1830 case 0x1:
1831 gen_op_and_T1_T0();
1832 if (xop & 0x10)
1833 gen_op_logic_T0_cc();
1834 break;
1835 case 0x2:
e80cfcfc
FB		 1836 gen_op_or_T1_T0();
1837 if (xop & 0x10)
1838 gen_op_logic_T0_cc();
1839 break;
cf495bcf
FB		 1840 case 0x3:
1841 gen_op_xor_T1_T0();
1842 if (xop & 0x10)
1843 gen_op_logic_T0_cc();
1844 break;
1845 case 0x4:
1846 if (xop & 0x10)
1847 gen_op_sub_T1_T0_cc();
1848 else
1849 gen_op_sub_T1_T0();
1850 break;
1851 case 0x5:
1852 gen_op_andn_T1_T0();
1853 if (xop & 0x10)
1854 gen_op_logic_T0_cc();
1855 break;
1856 case 0x6:
1857 gen_op_orn_T1_T0();
1858 if (xop & 0x10)
1859 gen_op_logic_T0_cc();
1860 break;
1861 case 0x7:
1862 gen_op_xnor_T1_T0();
1863 if (xop & 0x10)
1864 gen_op_logic_T0_cc();
1865 break;
1866 case 0x8:
cf495bcf 1867 if (xop & 0x10)
af7bf89b
FB		 1868 gen_op_addx_T1_T0_cc();
1869 else
1870 gen_op_addx_T1_T0();
cf495bcf 1871 break;
ded3ab80
PB		 1872#ifdef TARGET_SPARC64
1873 case 0x9: /* V9 mulx */
1874 gen_op_mulx_T1_T0();
1875 break;
1876#endif
cf495bcf
FB		 1877 case 0xa:
1878 gen_op_umul_T1_T0();
1879 if (xop & 0x10)
1880 gen_op_logic_T0_cc();
1881 break;
1882 case 0xb:
1883 gen_op_smul_T1_T0();
1884 if (xop & 0x10)
1885 gen_op_logic_T0_cc();
1886 break;
1887 case 0xc:
cf495bcf 1888 if (xop & 0x10)
af7bf89b
FB		 1889 gen_op_subx_T1_T0_cc();
1890 else
1891 gen_op_subx_T1_T0();
cf495bcf 1892 break;
ded3ab80
PB		 1893#ifdef TARGET_SPARC64
1894 case 0xd: /* V9 udivx */
1895 gen_op_udivx_T1_T0();
1896 break;
1897#endif
cf495bcf
FB		 1898 case 0xe:
1899 gen_op_udiv_T1_T0();
1900 if (xop & 0x10)
1901 gen_op_div_cc();
1902 break;
1903 case 0xf:
1904 gen_op_sdiv_T1_T0();
1905 if (xop & 0x10)
1906 gen_op_div_cc();
1907 break;
1908 default:
1909 goto illegal_insn;
1910 }
e80cfcfc 1911 gen_movl_T0_reg(rd);
cf495bcf
FB		 1912 } else {
1913 switch (xop) {
e80cfcfc 1914 case 0x20: /* taddcc */
e32f879d
BS		 1915 gen_op_tadd_T1_T0_cc();
1916 gen_movl_T0_reg(rd);
1917 break;
e80cfcfc 1918 case 0x21: /* tsubcc */
e32f879d
BS		 1919 gen_op_tsub_T1_T0_cc();
1920 gen_movl_T0_reg(rd);
1921 break;
e80cfcfc 1922 case 0x22: /* taddcctv */
e32f879d
BS		 1923 gen_op_tadd_T1_T0_ccTV();
1924 gen_movl_T0_reg(rd);
1925 break;
e80cfcfc 1926 case 0x23: /* tsubcctv */
e32f879d
BS		 1927 gen_op_tsub_T1_T0_ccTV();
1928 gen_movl_T0_reg(rd);
1929 break;
cf495bcf
FB		 1930 case 0x24: /* mulscc */
1931 gen_op_mulscc_T1_T0();
1932 gen_movl_T0_reg(rd);
1933 break;
83469015
FB		 1934#ifndef TARGET_SPARC64
1935 case 0x25: /* sll */
3475187d 1936 gen_op_sll();
cf495bcf
FB		 1937 gen_movl_T0_reg(rd);
1938 break;
83469015 1939 case 0x26: /* srl */
3475187d 1940 gen_op_srl();
cf495bcf
FB		 1941 gen_movl_T0_reg(rd);
1942 break;
83469015 1943 case 0x27: /* sra */
3475187d 1944 gen_op_sra();
cf495bcf
FB		 1945 gen_movl_T0_reg(rd);
1946 break;
83469015 1947#endif
cf495bcf
FB		 1948 case 0x30:
1949 {
cf495bcf 1950 switch(rd) {
3475187d
FB		 1951 case 0: /* wry */
1952 gen_op_xor_T1_T0();
1953 gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
cf495bcf 1954 break;
65fe7b09
BS		 1955#ifndef TARGET_SPARC64
1956 case 0x01 ... 0x0f: /* undefined in the
1957 SPARCv8 manual, nop
1958 on the microSPARC
1959 II */
1960 case 0x10 ... 0x1f: /* implementation-dependent
1961 in the SPARCv8
1962 manual, nop on the
1963 microSPARC II */
1964 break;
1965#else
af7bf89b 1966 case 0x2: /* V9 wrccr */
3475187d
FB		 1967 gen_op_wrccr();
1968 break;
af7bf89b 1969 case 0x3: /* V9 wrasi */
3475187d
FB		 1970 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
1971 break;
af7bf89b 1972 case 0x6: /* V9 wrfprs */
3299908c 1973 gen_op_xor_T1_T0();
3475187d 1974 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
3299908c
BS		 1975 save_state(dc);
1976 gen_op_next_insn();
1977 gen_op_movl_T0_0();
1978 gen_op_exit_tb();
1979 dc->is_br = 1;
3475187d
FB		 1980 break;
1981 case 0xf: /* V9 sir, nop if user */
1982#if !defined(CONFIG_USER_ONLY)
1983 if (supervisor(dc))
1984 gen_op_sir();
1985#endif
1986 break;
725cb90b
FB		 1987 case 0x13: /* Graphics Status */
1988 if (gen_trap_ifnofpu(dc))
1989 goto jmp_insn;
1990 gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
1991 break;
83469015
FB		 1992 case 0x17: /* Tick compare */
1993#if !defined(CONFIG_USER_ONLY)
1994 if (!supervisor(dc))
1995 goto illegal_insn;
1996#endif
20c9f095
BS		 1997 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
1998 gen_op_wrtick_cmpr();
83469015
FB		 1999 break;
2000 case 0x18: /* System tick */
2001#if !defined(CONFIG_USER_ONLY)
2002 if (!supervisor(dc))
2003 goto illegal_insn;
2004#endif
20c9f095 2005 gen_op_wrstick();
83469015
FB		 2006 break;
2007 case 0x19: /* System tick compare */
2008#if !defined(CONFIG_USER_ONLY)
2009 if (!supervisor(dc))
2010 goto illegal_insn;
3475187d 2011#endif
20c9f095
BS		 2012 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
2013 gen_op_wrstick_cmpr();
83469015
FB		 2014 break;
2015
3475187d
FB		 2016 case 0x10: /* Performance Control */
2017 case 0x11: /* Performance Instrumentation Counter */
2018 case 0x12: /* Dispatch Control */
3475187d
FB		 2019 case 0x14: /* Softint set */
2020 case 0x15: /* Softint clear */
2021 case 0x16: /* Softint write */
83469015 2022#endif
3475187d 2023 default:
cf495bcf
FB		 2024 goto illegal_insn;
2025 }
2026 }
2027 break;
e8af50a3 2028#if !defined(CONFIG_USER_ONLY)
af7bf89b 2029 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3
FB		 2030 {
2031 if (!supervisor(dc))
2032 goto priv_insn;
3475187d
FB		 2033#ifdef TARGET_SPARC64
2034 switch (rd) {
2035 case 0:
2036 gen_op_saved();
2037 break;
2038 case 1:
2039 gen_op_restored();
2040 break;
e9ebed4d
BS		 2041 case 2: /* UA2005 allclean */
2042 case 3: /* UA2005 otherw */
2043 case 4: /* UA2005 normalw */
2044 case 5: /* UA2005 invalw */
2045 // XXX
3475187d
FB		 2046 default:
2047 goto illegal_insn;
2048 }
2049#else
e8af50a3
FB		 2050 gen_op_xor_T1_T0();
2051 gen_op_wrpsr();
9e61bde5
FB		 2052 save_state(dc);
2053 gen_op_next_insn();
2054 gen_op_movl_T0_0();
2055 gen_op_exit_tb();
2056 dc->is_br = 1;
3475187d 2057#endif
e8af50a3
FB		 2058 }
2059 break;
af7bf89b 2060 case 0x32: /* wrwim, V9 wrpr */
e8af50a3
FB		 2061 {
2062 if (!supervisor(dc))
2063 goto priv_insn;
2064 gen_op_xor_T1_T0();
3475187d
FB		 2065#ifdef TARGET_SPARC64
2066 switch (rd) {
2067 case 0: // tpc
2068 gen_op_wrtpc();
2069 break;
2070 case 1: // tnpc
2071 gen_op_wrtnpc();
2072 break;
2073 case 2: // tstate
2074 gen_op_wrtstate();
2075 break;
2076 case 3: // tt
2077 gen_op_wrtt();
2078 break;
2079 case 4: // tick
2080 gen_op_wrtick();
2081 break;
2082 case 5: // tba
83469015 2083 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
3475187d
FB		 2084 break;
2085 case 6: // pstate
2086 gen_op_wrpstate();
ded3ab80
PB		 2087 save_state(dc);
2088 gen_op_next_insn();
2089 gen_op_movl_T0_0();
2090 gen_op_exit_tb();
2091 dc->is_br = 1;
3475187d
FB		 2092 break;
2093 case 7: // tl
2094 gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
2095 break;
2096 case 8: // pil
2097 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
2098 break;
2099 case 9: // cwp
2100 gen_op_wrcwp();
2101 break;
2102 case 10: // cansave
2103 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
2104 break;
2105 case 11: // canrestore
2106 gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
2107 break;
2108 case 12: // cleanwin
2109 gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
2110 break;
2111 case 13: // otherwin
2112 gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
2113 break;
2114 case 14: // wstate
2115 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
2116 break;
e9ebed4d
BS		 2117 case 16: // UA2005 gl
2118 gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
2119 break;
2120 case 26: // UA2005 strand status
2121 if (!hypervisor(dc))
2122 goto priv_insn;
2123 gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
2124 break;
3475187d
FB		 2125 default:
2126 goto illegal_insn;
2127 }
2128#else
c688a6eb 2129 gen_op_wrwim();
3475187d 2130#endif
e8af50a3
FB		 2131 }
2132 break;
e9ebed4d 2133 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 2134 {
e9ebed4d 2135#ifndef TARGET_SPARC64
e8af50a3
FB		 2136 if (!supervisor(dc))
2137 goto priv_insn;
2138 gen_op_xor_T1_T0();
e9ebed4d
BS		 2139 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2140#else
2141 if (!hypervisor(dc))
2142 goto priv_insn;
2143 gen_op_xor_T1_T0();
2144 switch (rd) {
2145 case 0: // hpstate
2146 // XXX gen_op_wrhpstate();
2147 save_state(dc);
2148 gen_op_next_insn();
2149 gen_op_movl_T0_0();
2150 gen_op_exit_tb();
2151 dc->is_br = 1;
2152 break;
2153 case 1: // htstate
2154 // XXX gen_op_wrhtstate();
2155 break;
2156 case 3: // hintp
2157 gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp));
2158 break;
2159 case 5: // htba
2160 gen_op_movl_env_T0(offsetof(CPUSPARCState, htba));
2161 break;
2162 case 31: // hstick_cmpr
20c9f095
BS		 2163 gen_op_movtl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
2164 gen_op_wrhstick_cmpr();
e9ebed4d
BS		 2165 break;
2166 case 6: // hver readonly
2167 default:
2168 goto illegal_insn;
2169 }
2170#endif
e8af50a3
FB		 2171 }
2172 break;
2173#endif
3475187d 2174#ifdef TARGET_SPARC64
af7bf89b 2175 case 0x2c: /* V9 movcc */
3475187d
FB		 2176 {
2177 int cc = GET_FIELD_SP(insn, 11, 12);
2178 int cond = GET_FIELD_SP(insn, 14, 17);
2179 if (IS_IMM) { /* immediate */
2180 rs2 = GET_FIELD_SPs(insn, 0, 10);
2181 gen_movl_simm_T1(rs2);
2182 }
2183 else {
2184 rs2 = GET_FIELD_SP(insn, 0, 4);
2185 gen_movl_reg_T1(rs2);
2186 }
2187 gen_movl_reg_T0(rd);
2188 flush_T2(dc);
2189 if (insn & (1 << 18)) {
2190 if (cc == 0)
2191 gen_cond[0][cond]();
2192 else if (cc == 2)
2193 gen_cond[1][cond]();
2194 else
2195 goto illegal_insn;
2196 } else {
2197 gen_fcond[cc][cond]();
2198 }
2199 gen_op_mov_cc();
2200 gen_movl_T0_reg(rd);
2201 break;
2202 }
af7bf89b 2203 case 0x2d: /* V9 sdivx */
3475187d
FB		 2204 gen_op_sdivx_T1_T0();
2205 gen_movl_T0_reg(rd);
2206 break;
af7bf89b 2207 case 0x2e: /* V9 popc */
3475187d
FB		 2208 {
2209 if (IS_IMM) { /* immediate */
2210 rs2 = GET_FIELD_SPs(insn, 0, 12);
2211 gen_movl_simm_T1(rs2);
2212 // XXX optimize: popc(constant)
2213 }
2214 else {
2215 rs2 = GET_FIELD_SP(insn, 0, 4);
2216 gen_movl_reg_T1(rs2);
2217 }
2218 gen_op_popc();
2219 gen_movl_T0_reg(rd);
2220 }
af7bf89b 2221 case 0x2f: /* V9 movr */
3475187d
FB		 2222 {
2223 int cond = GET_FIELD_SP(insn, 10, 12);
2224 rs1 = GET_FIELD(insn, 13, 17);
2225 flush_T2(dc);
2226 gen_movl_reg_T0(rs1);
2227 gen_cond_reg(cond);
2228 if (IS_IMM) { /* immediate */
2229 rs2 = GET_FIELD_SPs(insn, 0, 10);
2230 gen_movl_simm_T1(rs2);
2231 }
2232 else {
2233 rs2 = GET_FIELD_SP(insn, 0, 4);
2234 gen_movl_reg_T1(rs2);
2235 }
2236 gen_movl_reg_T0(rd);
2237 gen_op_mov_cc();
2238 gen_movl_T0_reg(rd);
2239 break;
2240 }
3475187d
FB		 2241#endif
2242 default:
e80cfcfc
FB		 2243 goto illegal_insn;
2244 }
2245 }
3299908c
BS		 2246 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
2247#ifdef TARGET_SPARC64
2248 int opf = GET_FIELD_SP(insn, 5, 13);
2249 rs1 = GET_FIELD(insn, 13, 17);
2250 rs2 = GET_FIELD(insn, 27, 31);
e9ebed4d
BS		 2251 if (gen_trap_ifnofpu(dc))
2252 goto jmp_insn;
3299908c
BS		 2253
2254 switch (opf) {
e9ebed4d
BS		 2255 case 0x000: /* VIS I edge8cc */
2256 case 0x001: /* VIS II edge8n */
2257 case 0x002: /* VIS I edge8lcc */
2258 case 0x003: /* VIS II edge8ln */
2259 case 0x004: /* VIS I edge16cc */
2260 case 0x005: /* VIS II edge16n */
2261 case 0x006: /* VIS I edge16lcc */
2262 case 0x007: /* VIS II edge16ln */
2263 case 0x008: /* VIS I edge32cc */
2264 case 0x009: /* VIS II edge32n */
2265 case 0x00a: /* VIS I edge32lcc */
2266 case 0x00b: /* VIS II edge32ln */
2267 // XXX
2268 goto illegal_insn;
2269 case 0x010: /* VIS I array8 */
2270 gen_movl_reg_T0(rs1);
2271 gen_movl_reg_T1(rs2);
2272 gen_op_array8();
2273 gen_movl_T0_reg(rd);
2274 break;
2275 case 0x012: /* VIS I array16 */
2276 gen_movl_reg_T0(rs1);
2277 gen_movl_reg_T1(rs2);
2278 gen_op_array16();
2279 gen_movl_T0_reg(rd);
2280 break;
2281 case 0x014: /* VIS I array32 */
2282 gen_movl_reg_T0(rs1);
2283 gen_movl_reg_T1(rs2);
2284 gen_op_array32();
2285 gen_movl_T0_reg(rd);
2286 break;
3299908c 2287 case 0x018: /* VIS I alignaddr */
3299908c
BS		 2288 gen_movl_reg_T0(rs1);
2289 gen_movl_reg_T1(rs2);
2290 gen_op_alignaddr();
2291 gen_movl_T0_reg(rd);
2292 break;
e9ebed4d 2293 case 0x019: /* VIS II bmask */
3299908c 2294 case 0x01a: /* VIS I alignaddrl */
3299908c 2295 // XXX
e9ebed4d
BS		 2296 goto illegal_insn;
2297 case 0x020: /* VIS I fcmple16 */
2298 gen_op_load_fpr_DT0(rs1);
2299 gen_op_load_fpr_DT1(rs2);
2300 gen_op_fcmple16();
2301 gen_op_store_DT0_fpr(rd);
2302 break;
2303 case 0x022: /* VIS I fcmpne16 */
2304 gen_op_load_fpr_DT0(rs1);
2305 gen_op_load_fpr_DT1(rs2);
2306 gen_op_fcmpne16();
2307 gen_op_store_DT0_fpr(rd);
3299908c 2308 break;
e9ebed4d
BS		 2309 case 0x024: /* VIS I fcmple32 */
2310 gen_op_load_fpr_DT0(rs1);
2311 gen_op_load_fpr_DT1(rs2);
2312 gen_op_fcmple32();
2313 gen_op_store_DT0_fpr(rd);
2314 break;
2315 case 0x026: /* VIS I fcmpne32 */
2316 gen_op_load_fpr_DT0(rs1);
2317 gen_op_load_fpr_DT1(rs2);
2318 gen_op_fcmpne32();
2319 gen_op_store_DT0_fpr(rd);
2320 break;
2321 case 0x028: /* VIS I fcmpgt16 */
2322 gen_op_load_fpr_DT0(rs1);
2323 gen_op_load_fpr_DT1(rs2);
2324 gen_op_fcmpgt16();
2325 gen_op_store_DT0_fpr(rd);
2326 break;
2327 case 0x02a: /* VIS I fcmpeq16 */
2328 gen_op_load_fpr_DT0(rs1);
2329 gen_op_load_fpr_DT1(rs2);
2330 gen_op_fcmpeq16();
2331 gen_op_store_DT0_fpr(rd);
2332 break;
2333 case 0x02c: /* VIS I fcmpgt32 */
2334 gen_op_load_fpr_DT0(rs1);
2335 gen_op_load_fpr_DT1(rs2);
2336 gen_op_fcmpgt32();
2337 gen_op_store_DT0_fpr(rd);
2338 break;
2339 case 0x02e: /* VIS I fcmpeq32 */
2340 gen_op_load_fpr_DT0(rs1);
2341 gen_op_load_fpr_DT1(rs2);
2342 gen_op_fcmpeq32();
2343 gen_op_store_DT0_fpr(rd);
2344 break;
2345 case 0x031: /* VIS I fmul8x16 */
2346 gen_op_load_fpr_DT0(rs1);
2347 gen_op_load_fpr_DT1(rs2);
2348 gen_op_fmul8x16();
2349 gen_op_store_DT0_fpr(rd);
2350 break;
2351 case 0x033: /* VIS I fmul8x16au */
2352 gen_op_load_fpr_DT0(rs1);
2353 gen_op_load_fpr_DT1(rs2);
2354 gen_op_fmul8x16au();
2355 gen_op_store_DT0_fpr(rd);
2356 break;
2357 case 0x035: /* VIS I fmul8x16al */
2358 gen_op_load_fpr_DT0(rs1);
2359 gen_op_load_fpr_DT1(rs2);
2360 gen_op_fmul8x16al();
2361 gen_op_store_DT0_fpr(rd);
2362 break;
2363 case 0x036: /* VIS I fmul8sux16 */
2364 gen_op_load_fpr_DT0(rs1);
2365 gen_op_load_fpr_DT1(rs2);
2366 gen_op_fmul8sux16();
2367 gen_op_store_DT0_fpr(rd);
2368 break;
2369 case 0x037: /* VIS I fmul8ulx16 */
2370 gen_op_load_fpr_DT0(rs1);
2371 gen_op_load_fpr_DT1(rs2);
2372 gen_op_fmul8ulx16();
2373 gen_op_store_DT0_fpr(rd);
2374 break;
2375 case 0x038: /* VIS I fmuld8sux16 */
2376 gen_op_load_fpr_DT0(rs1);
2377 gen_op_load_fpr_DT1(rs2);
2378 gen_op_fmuld8sux16();
2379 gen_op_store_DT0_fpr(rd);
2380 break;
2381 case 0x039: /* VIS I fmuld8ulx16 */
2382 gen_op_load_fpr_DT0(rs1);
2383 gen_op_load_fpr_DT1(rs2);
2384 gen_op_fmuld8ulx16();
2385 gen_op_store_DT0_fpr(rd);
2386 break;
2387 case 0x03a: /* VIS I fpack32 */
2388 case 0x03b: /* VIS I fpack16 */
2389 case 0x03d: /* VIS I fpackfix */
2390 case 0x03e: /* VIS I pdist */
2391 // XXX
2392 goto illegal_insn;
3299908c 2393 case 0x048: /* VIS I faligndata */
3299908c
BS		 2394 gen_op_load_fpr_DT0(rs1);
2395 gen_op_load_fpr_DT1(rs2);
2396 gen_op_faligndata();
2397 gen_op_store_DT0_fpr(rd);
2398 break;
e9ebed4d
BS		 2399 case 0x04b: /* VIS I fpmerge */
2400 gen_op_load_fpr_DT0(rs1);
2401 gen_op_load_fpr_DT1(rs2);
2402 gen_op_fpmerge();
2403 gen_op_store_DT0_fpr(rd);
2404 break;
2405 case 0x04c: /* VIS II bshuffle */
2406 // XXX
2407 goto illegal_insn;
2408 case 0x04d: /* VIS I fexpand */
2409 gen_op_load_fpr_DT0(rs1);
2410 gen_op_load_fpr_DT1(rs2);
2411 gen_op_fexpand();
2412 gen_op_store_DT0_fpr(rd);
2413 break;
2414 case 0x050: /* VIS I fpadd16 */
2415 gen_op_load_fpr_DT0(rs1);
2416 gen_op_load_fpr_DT1(rs2);
2417 gen_op_fpadd16();
2418 gen_op_store_DT0_fpr(rd);
2419 break;
2420 case 0x051: /* VIS I fpadd16s */
2421 gen_op_load_fpr_FT0(rs1);
2422 gen_op_load_fpr_FT1(rs2);
2423 gen_op_fpadd16s();
2424 gen_op_store_FT0_fpr(rd);
2425 break;
2426 case 0x052: /* VIS I fpadd32 */
2427 gen_op_load_fpr_DT0(rs1);
2428 gen_op_load_fpr_DT1(rs2);
2429 gen_op_fpadd32();
2430 gen_op_store_DT0_fpr(rd);
2431 break;
2432 case 0x053: /* VIS I fpadd32s */
2433 gen_op_load_fpr_FT0(rs1);
2434 gen_op_load_fpr_FT1(rs2);
2435 gen_op_fpadd32s();
2436 gen_op_store_FT0_fpr(rd);
2437 break;
2438 case 0x054: /* VIS I fpsub16 */
2439 gen_op_load_fpr_DT0(rs1);
2440 gen_op_load_fpr_DT1(rs2);
2441 gen_op_fpsub16();
2442 gen_op_store_DT0_fpr(rd);
2443 break;
2444 case 0x055: /* VIS I fpsub16s */
2445 gen_op_load_fpr_FT0(rs1);
2446 gen_op_load_fpr_FT1(rs2);
2447 gen_op_fpsub16s();
2448 gen_op_store_FT0_fpr(rd);
2449 break;
2450 case 0x056: /* VIS I fpsub32 */
2451 gen_op_load_fpr_DT0(rs1);
2452 gen_op_load_fpr_DT1(rs2);
2453 gen_op_fpadd32();
2454 gen_op_store_DT0_fpr(rd);
2455 break;
2456 case 0x057: /* VIS I fpsub32s */
2457 gen_op_load_fpr_FT0(rs1);
2458 gen_op_load_fpr_FT1(rs2);
2459 gen_op_fpsub32s();
2460 gen_op_store_FT0_fpr(rd);
2461 break;
3299908c 2462 case 0x060: /* VIS I fzero */
3299908c
BS		 2463 gen_op_movl_DT0_0();
2464 gen_op_store_DT0_fpr(rd);
2465 break;
2466 case 0x061: /* VIS I fzeros */
3299908c
BS		 2467 gen_op_movl_FT0_0();
2468 gen_op_store_FT0_fpr(rd);
2469 break;
e9ebed4d
BS		 2470 case 0x062: /* VIS I fnor */
2471 gen_op_load_fpr_DT0(rs1);
2472 gen_op_load_fpr_DT1(rs2);
2473 gen_op_fnor();
2474 gen_op_store_DT0_fpr(rd);
2475 break;
2476 case 0x063: /* VIS I fnors */
2477 gen_op_load_fpr_FT0(rs1);
2478 gen_op_load_fpr_FT1(rs2);
2479 gen_op_fnors();
2480 gen_op_store_FT0_fpr(rd);
2481 break;
2482 case 0x064: /* VIS I fandnot2 */
2483 gen_op_load_fpr_DT1(rs1);
2484 gen_op_load_fpr_DT0(rs2);
2485 gen_op_fandnot();
2486 gen_op_store_DT0_fpr(rd);
2487 break;
2488 case 0x065: /* VIS I fandnot2s */
2489 gen_op_load_fpr_FT1(rs1);
2490 gen_op_load_fpr_FT0(rs2);
2491 gen_op_fandnots();
2492 gen_op_store_FT0_fpr(rd);
2493 break;
2494 case 0x066: /* VIS I fnot2 */
2495 gen_op_load_fpr_DT1(rs2);
2496 gen_op_fnot();
2497 gen_op_store_DT0_fpr(rd);
2498 break;
2499 case 0x067: /* VIS I fnot2s */
2500 gen_op_load_fpr_FT1(rs2);
2501 gen_op_fnot();
2502 gen_op_store_FT0_fpr(rd);
2503 break;
2504 case 0x068: /* VIS I fandnot1 */
2505 gen_op_load_fpr_DT0(rs1);
2506 gen_op_load_fpr_DT1(rs2);
2507 gen_op_fandnot();
2508 gen_op_store_DT0_fpr(rd);
2509 break;
2510 case 0x069: /* VIS I fandnot1s */
2511 gen_op_load_fpr_FT0(rs1);
2512 gen_op_load_fpr_FT1(rs2);
2513 gen_op_fandnots();
2514 gen_op_store_FT0_fpr(rd);
2515 break;
2516 case 0x06a: /* VIS I fnot1 */
2517 gen_op_load_fpr_DT1(rs1);
2518 gen_op_fnot();
2519 gen_op_store_DT0_fpr(rd);
2520 break;
2521 case 0x06b: /* VIS I fnot1s */
2522 gen_op_load_fpr_FT1(rs1);
2523 gen_op_fnot();
2524 gen_op_store_FT0_fpr(rd);
2525 break;
2526 case 0x06c: /* VIS I fxor */
2527 gen_op_load_fpr_DT0(rs1);
2528 gen_op_load_fpr_DT1(rs2);
2529 gen_op_fxor();
2530 gen_op_store_DT0_fpr(rd);
2531 break;
2532 case 0x06d: /* VIS I fxors */
2533 gen_op_load_fpr_FT0(rs1);
2534 gen_op_load_fpr_FT1(rs2);
2535 gen_op_fxors();
2536 gen_op_store_FT0_fpr(rd);
2537 break;
2538 case 0x06e: /* VIS I fnand */
2539 gen_op_load_fpr_DT0(rs1);
2540 gen_op_load_fpr_DT1(rs2);
2541 gen_op_fnand();
2542 gen_op_store_DT0_fpr(rd);
2543 break;
2544 case 0x06f: /* VIS I fnands */
2545 gen_op_load_fpr_FT0(rs1);
2546 gen_op_load_fpr_FT1(rs2);
2547 gen_op_fnands();
2548 gen_op_store_FT0_fpr(rd);
2549 break;
2550 case 0x070: /* VIS I fand */
2551 gen_op_load_fpr_DT0(rs1);
2552 gen_op_load_fpr_DT1(rs2);
2553 gen_op_fand();
2554 gen_op_store_DT0_fpr(rd);
2555 break;
2556 case 0x071: /* VIS I fands */
2557 gen_op_load_fpr_FT0(rs1);
2558 gen_op_load_fpr_FT1(rs2);
2559 gen_op_fands();
2560 gen_op_store_FT0_fpr(rd);
2561 break;
2562 case 0x072: /* VIS I fxnor */
2563 gen_op_load_fpr_DT0(rs1);
2564 gen_op_load_fpr_DT1(rs2);
2565 gen_op_fxnor();
2566 gen_op_store_DT0_fpr(rd);
2567 break;
2568 case 0x073: /* VIS I fxnors */
2569 gen_op_load_fpr_FT0(rs1);
2570 gen_op_load_fpr_FT1(rs2);
2571 gen_op_fxnors();
2572 gen_op_store_FT0_fpr(rd);
2573 break;
3299908c 2574 case 0x074: /* VIS I fsrc1 */
3299908c
BS		 2575 gen_op_load_fpr_DT0(rs1);
2576 gen_op_store_DT0_fpr(rd);
2577 break;
2578 case 0x075: /* VIS I fsrc1s */
3299908c
BS		 2579 gen_op_load_fpr_FT0(rs1);
2580 gen_op_store_FT0_fpr(rd);
2581 break;
e9ebed4d
BS		 2582 case 0x076: /* VIS I fornot2 */
2583 gen_op_load_fpr_DT1(rs1);
2584 gen_op_load_fpr_DT0(rs2);
2585 gen_op_fornot();
2586 gen_op_store_DT0_fpr(rd);
2587 break;
2588 case 0x077: /* VIS I fornot2s */
2589 gen_op_load_fpr_FT1(rs1);
2590 gen_op_load_fpr_FT0(rs2);
2591 gen_op_fornots();
2592 gen_op_store_FT0_fpr(rd);
2593 break;
3299908c 2594 case 0x078: /* VIS I fsrc2 */
3299908c
BS		 2595 gen_op_load_fpr_DT0(rs2);
2596 gen_op_store_DT0_fpr(rd);
2597 break;
2598 case 0x079: /* VIS I fsrc2s */
3299908c
BS		 2599 gen_op_load_fpr_FT0(rs2);
2600 gen_op_store_FT0_fpr(rd);
2601 break;
e9ebed4d
BS		 2602 case 0x07a: /* VIS I fornot1 */
2603 gen_op_load_fpr_DT0(rs1);
2604 gen_op_load_fpr_DT1(rs2);
2605 gen_op_fornot();
2606 gen_op_store_DT0_fpr(rd);
2607 break;
2608 case 0x07b: /* VIS I fornot1s */
2609 gen_op_load_fpr_FT0(rs1);
2610 gen_op_load_fpr_FT1(rs2);
2611 gen_op_fornots();
2612 gen_op_store_FT0_fpr(rd);
2613 break;
2614 case 0x07c: /* VIS I for */
2615 gen_op_load_fpr_DT0(rs1);
2616 gen_op_load_fpr_DT1(rs2);
2617 gen_op_for();
2618 gen_op_store_DT0_fpr(rd);
2619 break;
2620 case 0x07d: /* VIS I fors */
2621 gen_op_load_fpr_FT0(rs1);
2622 gen_op_load_fpr_FT1(rs2);
2623 gen_op_fors();
2624 gen_op_store_FT0_fpr(rd);
2625 break;
3299908c 2626 case 0x07e: /* VIS I fone */
3299908c
BS		 2627 gen_op_movl_DT0_1();
2628 gen_op_store_DT0_fpr(rd);
2629 break;
2630 case 0x07f: /* VIS I fones */
3299908c
BS		 2631 gen_op_movl_FT0_1();
2632 gen_op_store_FT0_fpr(rd);
2633 break;
e9ebed4d
BS		 2634 case 0x080: /* VIS I shutdown */
2635 case 0x081: /* VIS II siam */
2636 // XXX
2637 goto illegal_insn;
3299908c
BS		 2638 default:
2639 goto illegal_insn;
2640 }
2641#else
2642 goto ncp_insn;
2643#endif
2644 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045
BS		 2645#ifdef TARGET_SPARC64
2646 goto illegal_insn;
2647#else
2648 goto ncp_insn;
2649#endif
3475187d
FB		 2650#ifdef TARGET_SPARC64
2651 } else if (xop == 0x39) { /* V9 return */
3475187d
FB		 2652 rs1 = GET_FIELD(insn, 13, 17);
2653 gen_movl_reg_T0(rs1);
2654 if (IS_IMM) { /* immediate */
2655 rs2 = GET_FIELDs(insn, 19, 31);
2656#if defined(OPTIM)
2657 if (rs2) {
2658#endif
2659 gen_movl_simm_T1(rs2);
2660 gen_op_add_T1_T0();
2661#if defined(OPTIM)
2662 }
2663#endif
2664 } else { /* register */
2665 rs2 = GET_FIELD(insn, 27, 31);
2666#if defined(OPTIM)
2667 if (rs2) {
2668#endif
2669 gen_movl_reg_T1(rs2);
2670 gen_op_add_T1_T0();
2671#if defined(OPTIM)
2672 }
2673#endif
2674 }
83469015 2675 gen_op_restore();
3475187d
FB		 2676 gen_mov_pc_npc(dc);
2677 gen_op_movl_npc_T0();
2678 dc->npc = DYNAMIC_PC;
2679 goto jmp_insn;
2680#endif
e80cfcfc
FB		 2681 } else {
2682 rs1 = GET_FIELD(insn, 13, 17);
2683 gen_movl_reg_T0(rs1);
2684 if (IS_IMM) { /* immediate */
2685 rs2 = GET_FIELDs(insn, 19, 31);
2686#if defined(OPTIM)
2687 if (rs2) {
e8af50a3 2688#endif
3475187d 2689 gen_movl_simm_T1(rs2);
e80cfcfc
FB		 2690 gen_op_add_T1_T0();
2691#if defined(OPTIM)
2692 }
e8af50a3 2693#endif
e80cfcfc
FB		 2694 } else { /* register */
2695 rs2 = GET_FIELD(insn, 27, 31);
2696#if defined(OPTIM)
2697 if (rs2) {
2698#endif
2699 gen_movl_reg_T1(rs2);
2700 gen_op_add_T1_T0();
2701#if defined(OPTIM)
2702 }
e8af50a3 2703#endif
cf495bcf 2704 }
e80cfcfc
FB		 2705 switch (xop) {
2706 case 0x38: /* jmpl */
2707 {
e80cfcfc 2708 if (rd != 0) {
ded3ab80
PB		 2709#ifdef TARGET_SPARC64
2710 if (dc->pc == (uint32_t)dc->pc) {
2711 gen_op_movl_T1_im(dc->pc);
2712 } else {
2713 gen_op_movq_T1_im64(dc->pc >> 32, dc->pc);
2714 }
2715#else
0bee699e 2716 gen_op_movl_T1_im(dc->pc);
ded3ab80 2717#endif
0bee699e 2718 gen_movl_T1_reg(rd);
e80cfcfc 2719 }
0bee699e
FB		 2720 gen_mov_pc_npc(dc);
2721 gen_op_movl_npc_T0();
e80cfcfc
FB		 2722 dc->npc = DYNAMIC_PC;
2723 }
2724 goto jmp_insn;
3475187d 2725#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
af7bf89b 2726 case 0x39: /* rett, V9 return */
e80cfcfc
FB		 2727 {
2728 if (!supervisor(dc))
2729 goto priv_insn;
0bee699e 2730 gen_mov_pc_npc(dc);
e80cfcfc 2731 gen_op_movl_npc_T0();
0bee699e 2732 dc->npc = DYNAMIC_PC;
e80cfcfc
FB		 2733 gen_op_rett();
2734 }
0bee699e 2735 goto jmp_insn;
e80cfcfc
FB		 2736#endif
2737 case 0x3b: /* flush */
2738 gen_op_flush_T0();
2739 break;
2740 case 0x3c: /* save */
2741 save_state(dc);
2742 gen_op_save();
2743 gen_movl_T0_reg(rd);
2744 break;
2745 case 0x3d: /* restore */
2746 save_state(dc);
2747 gen_op_restore();
2748 gen_movl_T0_reg(rd);
2749 break;
3475187d 2750#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
af7bf89b 2751 case 0x3e: /* V9 done/retry */
3475187d
FB		 2752 {
2753 switch (rd) {
2754 case 0:
2755 if (!supervisor(dc))
2756 goto priv_insn;
83469015
FB		 2757 dc->npc = DYNAMIC_PC;
2758 dc->pc = DYNAMIC_PC;
3475187d 2759 gen_op_done();
83469015 2760 goto jmp_insn;
3475187d
FB		 2761 case 1:
2762 if (!supervisor(dc))
2763 goto priv_insn;
83469015
FB		 2764 dc->npc = DYNAMIC_PC;
2765 dc->pc = DYNAMIC_PC;
3475187d 2766 gen_op_retry();
83469015 2767 goto jmp_insn;
3475187d
FB		 2768 default:
2769 goto illegal_insn;
2770 }
2771 }
2772 break;
2773#endif
2774 default:
e80cfcfc
FB		 2775 goto illegal_insn;
2776 }
cf495bcf
FB		 2777 }
2778 break;
2779 }
af7bf89b 2780 break;
cf495bcf
FB		 2781 case 3: /* load/store instructions */
2782 {
2783 unsigned int xop = GET_FIELD(insn, 7, 12);
2784 rs1 = GET_FIELD(insn, 13, 17);
2371aaa2 2785 save_state(dc);
cf495bcf
FB		 2786 gen_movl_reg_T0(rs1);
2787 if (IS_IMM) { /* immediate */
2788 rs2 = GET_FIELDs(insn, 19, 31);
e80cfcfc 2789#if defined(OPTIM)
e8af50a3 2790 if (rs2 != 0) {
e80cfcfc 2791#endif
3475187d 2792 gen_movl_simm_T1(rs2);
e8af50a3 2793 gen_op_add_T1_T0();
e80cfcfc 2794#if defined(OPTIM)
e8af50a3 2795 }
e80cfcfc 2796#endif
cf495bcf
FB		 2797 } else { /* register */
2798 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc
FB		 2799#if defined(OPTIM)
2800 if (rs2 != 0) {
2801#endif
2802 gen_movl_reg_T1(rs2);
2803 gen_op_add_T1_T0();
2804#if defined(OPTIM)
2805 }
2806#endif
cf495bcf 2807 }
2f2ecb83
BS		 2808 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
2809 (xop > 0x17 && xop <= 0x1d ) ||
2810 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
cf495bcf
FB		 2811 switch (xop) {
2812 case 0x0: /* load word */
e8af50a3 2813 gen_op_ldst(ld);
cf495bcf
FB		 2814 break;
2815 case 0x1: /* load unsigned byte */
e8af50a3 2816 gen_op_ldst(ldub);
cf495bcf
FB		 2817 break;
2818 case 0x2: /* load unsigned halfword */
e8af50a3 2819 gen_op_ldst(lduh);
cf495bcf
FB		 2820 break;
2821 case 0x3: /* load double word */
d4218d99
BS		 2822 if (rd & 1)
2823 goto illegal_insn;
e8af50a3 2824 gen_op_ldst(ldd);
cf495bcf
FB		 2825 gen_movl_T0_reg(rd + 1);
2826 break;
2827 case 0x9: /* load signed byte */
e8af50a3 2828 gen_op_ldst(ldsb);
cf495bcf
FB		 2829 break;
2830 case 0xa: /* load signed halfword */
e8af50a3 2831 gen_op_ldst(ldsh);
cf495bcf
FB		 2832 break;
2833 case 0xd: /* ldstub -- XXX: should be atomically */
e8af50a3 2834 gen_op_ldst(ldstub);
cf495bcf
FB		 2835 break;
2836 case 0x0f: /* swap register with memory. Also atomically */
e80cfcfc 2837 gen_movl_reg_T1(rd);
e8af50a3
FB		 2838 gen_op_ldst(swap);
2839 break;
3475187d 2840#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
e8af50a3 2841 case 0x10: /* load word alternate */
3475187d 2842#ifndef TARGET_SPARC64
d4218d99
BS		 2843 if (IS_IMM)
2844 goto illegal_insn;
e8af50a3
FB		 2845 if (!supervisor(dc))
2846 goto priv_insn;
3475187d 2847#endif
e8af50a3
FB		 2848 gen_op_lda(insn, 1, 4, 0);
2849 break;
2850 case 0x11: /* load unsigned byte alternate */
3475187d 2851#ifndef TARGET_SPARC64
d4218d99
BS		 2852 if (IS_IMM)
2853 goto illegal_insn;
e8af50a3
FB		 2854 if (!supervisor(dc))
2855 goto priv_insn;
3475187d 2856#endif
e8af50a3
FB		 2857 gen_op_lduba(insn, 1, 1, 0);
2858 break;
2859 case 0x12: /* load unsigned halfword alternate */
3475187d 2860#ifndef TARGET_SPARC64
d4218d99
BS		 2861 if (IS_IMM)
2862 goto illegal_insn;
e8af50a3
FB		 2863 if (!supervisor(dc))
2864 goto priv_insn;
3475187d 2865#endif
e8af50a3
FB		 2866 gen_op_lduha(insn, 1, 2, 0);
2867 break;
2868 case 0x13: /* load double word alternate */
3475187d 2869#ifndef TARGET_SPARC64
d4218d99
BS		 2870 if (IS_IMM)
2871 goto illegal_insn;
e8af50a3
FB		 2872 if (!supervisor(dc))
2873 goto priv_insn;
3475187d 2874#endif
d4218d99
BS		 2875 if (rd & 1)
2876 goto illegal_insn;
e8af50a3
FB		 2877 gen_op_ldda(insn, 1, 8, 0);
2878 gen_movl_T0_reg(rd + 1);
2879 break;
2880 case 0x19: /* load signed byte alternate */
3475187d 2881#ifndef TARGET_SPARC64
d4218d99
BS		 2882 if (IS_IMM)
2883 goto illegal_insn;
e8af50a3
FB		 2884 if (!supervisor(dc))
2885 goto priv_insn;
3475187d 2886#endif
e8af50a3
FB		 2887 gen_op_ldsba(insn, 1, 1, 1);
2888 break;
2889 case 0x1a: /* load signed halfword alternate */
3475187d 2890#ifndef TARGET_SPARC64
d4218d99
BS		 2891 if (IS_IMM)
2892 goto illegal_insn;
e8af50a3
FB		 2893 if (!supervisor(dc))
2894 goto priv_insn;
3475187d 2895#endif
e8af50a3
FB		 2896 gen_op_ldsha(insn, 1, 2 ,1);
2897 break;
2898 case 0x1d: /* ldstuba -- XXX: should be atomically */
3475187d 2899#ifndef TARGET_SPARC64
d4218d99
BS		 2900 if (IS_IMM)
2901 goto illegal_insn;
e8af50a3
FB		 2902 if (!supervisor(dc))
2903 goto priv_insn;
3475187d 2904#endif
e8af50a3
FB		 2905 gen_op_ldstuba(insn, 1, 1, 0);
2906 break;
2907 case 0x1f: /* swap reg with alt. memory. Also atomically */
3475187d 2908#ifndef TARGET_SPARC64
d4218d99
BS		 2909 if (IS_IMM)
2910 goto illegal_insn;
e8af50a3
FB		 2911 if (!supervisor(dc))
2912 goto priv_insn;
3475187d 2913#endif
e80cfcfc 2914 gen_movl_reg_T1(rd);
e8af50a3 2915 gen_op_swapa(insn, 1, 4, 0);
cf495bcf 2916 break;
3475187d
FB		 2917
2918#ifndef TARGET_SPARC64
fcc72045
BS		 2919 case 0x30: /* ldc */
2920 case 0x31: /* ldcsr */
2921 case 0x33: /* lddc */
fcc72045 2922 goto ncp_insn;
0fa85d43
FB		 2923 /* avoid warnings */
2924 (void) &gen_op_stfa;
2925 (void) &gen_op_stdfa;
2926 (void) &gen_op_ldfa;
2927 (void) &gen_op_lddfa;
3475187d
FB		 2928#else
2929#if !defined(CONFIG_USER_ONLY)
2930 (void) &gen_op_cas;
2931 (void) &gen_op_casx;
e80cfcfc 2932#endif
3475187d
FB		 2933#endif
2934#endif
2935#ifdef TARGET_SPARC64
af7bf89b 2936 case 0x08: /* V9 ldsw */
3475187d
FB		 2937 gen_op_ldst(ldsw);
2938 break;
af7bf89b 2939 case 0x0b: /* V9 ldx */
3475187d
FB		 2940 gen_op_ldst(ldx);
2941 break;
af7bf89b 2942 case 0x18: /* V9 ldswa */
3475187d
FB		 2943 gen_op_ldswa(insn, 1, 4, 1);
2944 break;
af7bf89b 2945 case 0x1b: /* V9 ldxa */
3475187d
FB		 2946 gen_op_ldxa(insn, 1, 8, 0);
2947 break;
2948 case 0x2d: /* V9 prefetch, no effect */
2949 goto skip_move;
af7bf89b 2950 case 0x30: /* V9 ldfa */
3475187d
FB		 2951 gen_op_ldfa(insn, 1, 8, 0); // XXX
2952 break;
af7bf89b 2953 case 0x33: /* V9 lddfa */
3475187d 2954 gen_op_lddfa(insn, 1, 8, 0); // XXX
af7bf89b 2955
3475187d
FB		 2956 break;
2957 case 0x3d: /* V9 prefetcha, no effect */
2958 goto skip_move;
af7bf89b 2959 case 0x32: /* V9 ldqfa */
3475187d
FB		 2960 goto nfpu_insn;
2961#endif
2962 default:
e80cfcfc 2963 goto illegal_insn;
7a3f1944 2964 }
cf495bcf 2965 gen_movl_T1_reg(rd);
3475187d
FB		 2966#ifdef TARGET_SPARC64
2967 skip_move: ;
2968#endif
e8af50a3 2969 } else if (xop >= 0x20 && xop < 0x24) {
a80dde08
FB		 2970 if (gen_trap_ifnofpu(dc))
2971 goto jmp_insn;
e8af50a3
FB		 2972 switch (xop) {
2973 case 0x20: /* load fpreg */
2974 gen_op_ldst(ldf);
2975 gen_op_store_FT0_fpr(rd);
2976 break;
2977 case 0x21: /* load fsr */
9e61bde5 2978 gen_op_ldst(ldf);
e8af50a3
FB		 2979 gen_op_ldfsr();
2980 break;
af7bf89b
FB		 2981 case 0x22: /* load quad fpreg */
2982 goto nfpu_insn;
e8af50a3
FB		 2983 case 0x23: /* load double fpreg */
2984 gen_op_ldst(lddf);
3475187d 2985 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 2986 break;
e80cfcfc
FB		 2987 default:
2988 goto illegal_insn;
e8af50a3 2989 }
3475187d
FB		 2990 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
2991 xop == 0xe || xop == 0x1e) {
cf495bcf
FB		 2992 gen_movl_reg_T1(rd);
2993 switch (xop) {
2994 case 0x4:
e8af50a3 2995 gen_op_ldst(st);
cf495bcf
FB		 2996 break;
2997 case 0x5:
e8af50a3 2998 gen_op_ldst(stb);
cf495bcf
FB		 2999 break;
3000 case 0x6:
e8af50a3 3001 gen_op_ldst(sth);
cf495bcf
FB		 3002 break;
3003 case 0x7:
d4218d99
BS		 3004 if (rd & 1)
3005 goto illegal_insn;
72cbca10 3006 flush_T2(dc);
cf495bcf 3007 gen_movl_reg_T2(rd + 1);
e8af50a3
FB		 3008 gen_op_ldst(std);
3009 break;
3475187d 3010#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
e8af50a3 3011 case 0x14:
3475187d 3012#ifndef TARGET_SPARC64
d4218d99
BS		 3013 if (IS_IMM)
3014 goto illegal_insn;
e8af50a3
FB		 3015 if (!supervisor(dc))
3016 goto priv_insn;
3475187d 3017#endif
e8af50a3 3018 gen_op_sta(insn, 0, 4, 0);
d39c0b99 3019 break;
e8af50a3 3020 case 0x15:
3475187d 3021#ifndef TARGET_SPARC64
d4218d99
BS		 3022 if (IS_IMM)
3023 goto illegal_insn;
e8af50a3
FB		 3024 if (!supervisor(dc))
3025 goto priv_insn;
3475187d 3026#endif
e8af50a3 3027 gen_op_stba(insn, 0, 1, 0);
d39c0b99 3028 break;
e8af50a3 3029 case 0x16:
3475187d 3030#ifndef TARGET_SPARC64
d4218d99
BS		 3031 if (IS_IMM)
3032 goto illegal_insn;
e8af50a3
FB		 3033 if (!supervisor(dc))
3034 goto priv_insn;
3475187d 3035#endif
e8af50a3 3036 gen_op_stha(insn, 0, 2, 0);
d39c0b99 3037 break;
e8af50a3 3038 case 0x17:
3475187d 3039#ifndef TARGET_SPARC64
d4218d99
BS		 3040 if (IS_IMM)
3041 goto illegal_insn;
e8af50a3
FB		 3042 if (!supervisor(dc))
3043 goto priv_insn;
3475187d 3044#endif
d4218d99
BS		 3045 if (rd & 1)
3046 goto illegal_insn;
e8af50a3
FB		 3047 flush_T2(dc);
3048 gen_movl_reg_T2(rd + 1);
3049 gen_op_stda(insn, 0, 8, 0);
d39c0b99 3050 break;
e80cfcfc 3051#endif
3475187d 3052#ifdef TARGET_SPARC64
af7bf89b 3053 case 0x0e: /* V9 stx */
3475187d
FB		 3054 gen_op_ldst(stx);
3055 break;
af7bf89b 3056 case 0x1e: /* V9 stxa */
3475187d
FB		 3057 gen_op_stxa(insn, 0, 8, 0); // XXX
3058 break;
3059#endif
3060 default:
e80cfcfc 3061 goto illegal_insn;
7a3f1944 3062 }
e8af50a3 3063 } else if (xop > 0x23 && xop < 0x28) {
a80dde08
FB		 3064 if (gen_trap_ifnofpu(dc))
3065 goto jmp_insn;
e8af50a3
FB		 3066 switch (xop) {
3067 case 0x24:
3068 gen_op_load_fpr_FT0(rd);
3069 gen_op_ldst(stf);
3070 break;
af7bf89b 3071 case 0x25: /* stfsr, V9 stxfsr */
e8af50a3 3072 gen_op_stfsr();
9e61bde5 3073 gen_op_ldst(stf);
e8af50a3 3074 break;
9143e598 3075#if !defined(CONFIG_USER_ONLY)
af7bf89b 3076 case 0x26: /* stdfq */
9143e598
BS		 3077 if (!supervisor(dc))
3078 goto priv_insn;
3079 if (gen_trap_ifnofpu(dc))
3080 goto jmp_insn;
3081 goto nfq_insn;
3082#endif
e8af50a3 3083 case 0x27:
3475187d 3084 gen_op_load_fpr_DT0(DFPREG(rd));
e8af50a3
FB		 3085 gen_op_ldst(stdf);
3086 break;
e80cfcfc 3087 default:
3475187d
FB		 3088 goto illegal_insn;
3089 }
3090 } else if (xop > 0x33 && xop < 0x3f) {
3475187d 3091 switch (xop) {
a4d17f19 3092#ifdef TARGET_SPARC64
af7bf89b 3093 case 0x34: /* V9 stfa */
3475187d
FB		 3094 gen_op_stfa(insn, 0, 0, 0); // XXX
3095 break;
af7bf89b 3096 case 0x37: /* V9 stdfa */
3475187d
FB		 3097 gen_op_stdfa(insn, 0, 0, 0); // XXX
3098 break;
af7bf89b 3099 case 0x3c: /* V9 casa */
3475187d
FB		 3100 gen_op_casa(insn, 0, 4, 0); // XXX
3101 break;
af7bf89b 3102 case 0x3e: /* V9 casxa */
3475187d
FB		 3103 gen_op_casxa(insn, 0, 8, 0); // XXX
3104 break;
af7bf89b 3105 case 0x36: /* V9 stqfa */
3475187d 3106 goto nfpu_insn;
a4d17f19
BS		 3107#else
3108 case 0x34: /* stc */
3109 case 0x35: /* stcsr */
3110 case 0x36: /* stdcq */
3111 case 0x37: /* stdc */
3112 goto ncp_insn;
3113#endif
3475187d 3114 default:
e80cfcfc 3115 goto illegal_insn;
e8af50a3 3116 }
e8af50a3 3117 }
e80cfcfc
FB		 3118 else
3119 goto illegal_insn;
7a3f1944 3120 }
af7bf89b 3121 break;
cf495bcf
FB		 3122 }
3123 /* default case for non jump instructions */
72cbca10
FB		 3124 if (dc->npc == DYNAMIC_PC) {
3125 dc->pc = DYNAMIC_PC;
3126 gen_op_next_insn();
3127 } else if (dc->npc == JUMP_PC) {
3128 /* we can do a static jump */
46525e1f 3129 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1]);
72cbca10
FB		 3130 dc->is_br = 1;
3131 } else {
cf495bcf
FB		 3132 dc->pc = dc->npc;
3133 dc->npc = dc->npc + 4;
cf495bcf 3134 }
e80cfcfc 3135 jmp_insn:
cf495bcf
FB		 3136 return;
3137 illegal_insn:
72cbca10 3138 save_state(dc);
cf495bcf
FB		 3139 gen_op_exception(TT_ILL_INSN);
3140 dc->is_br = 1;
e8af50a3 3141 return;
e80cfcfc 3142#if !defined(CONFIG_USER_ONLY)
e8af50a3
FB		 3143 priv_insn:
3144 save_state(dc);
3145 gen_op_exception(TT_PRIV_INSN);
3146 dc->is_br = 1;
e80cfcfc
FB		 3147 return;
3148#endif
3149 nfpu_insn:
3150 save_state(dc);
3151 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
3152 dc->is_br = 1;
fcc72045 3153 return;
9143e598
BS		 3154#if !defined(CONFIG_USER_ONLY)
3155 nfq_insn:
3156 save_state(dc);
3157 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
3158 dc->is_br = 1;
3159 return;
3160#endif
fcc72045
BS		 3161#ifndef TARGET_SPARC64
3162 ncp_insn:
3163 save_state(dc);
3164 gen_op_exception(TT_NCP_INSN);
3165 dc->is_br = 1;
3166 return;
3167#endif
7a3f1944
FB		 3168}
3169
cf495bcf 3170static inline int gen_intermediate_code_internal(TranslationBlock * tb,
e8af50a3 3171 int spc, CPUSPARCState *env)
7a3f1944 3172{
72cbca10 3173 target_ulong pc_start, last_pc;
cf495bcf
FB		 3174 uint16_t *gen_opc_end;
3175 DisasContext dc1, *dc = &dc1;
e8af50a3 3176 int j, lj = -1;
cf495bcf
FB		 3177
3178 memset(dc, 0, sizeof(DisasContext));
cf495bcf 3179 dc->tb = tb;
72cbca10 3180 pc_start = tb->pc;
cf495bcf 3181 dc->pc = pc_start;
e80cfcfc 3182 last_pc = dc->pc;
72cbca10 3183 dc->npc = (target_ulong) tb->cs_base;
e8af50a3
FB		 3184#if defined(CONFIG_USER_ONLY)
3185 dc->mem_idx = 0;
a80dde08 3186 dc->fpu_enabled = 1;
e8af50a3
FB		 3187#else
3188 dc->mem_idx = ((env->psrs) != 0);
a80dde08
FB		 3189#ifdef TARGET_SPARC64
3190 dc->fpu_enabled = (((env->pstate & PS_PEF) != 0) && ((env->fprs & FPRS_FEF) != 0));
3191#else
3192 dc->fpu_enabled = ((env->psref) != 0);
3193#endif
e8af50a3 3194#endif
cf495bcf
FB		 3195 gen_opc_ptr = gen_opc_buf;
3196 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3197 gen_opparam_ptr = gen_opparam_buf;
83469015 3198 nb_gen_labels = 0;
cf495bcf
FB		 3199
3200 do {
e8af50a3
FB		 3201 if (env->nb_breakpoints > 0) {
3202 for(j = 0; j < env->nb_breakpoints; j++) {
3203 if (env->breakpoints[j] == dc->pc) {
e80cfcfc
FB		 3204 if (dc->pc != pc_start)
3205 save_state(dc);
3206 gen_op_debug();
3207 gen_op_movl_T0_0();
3208 gen_op_exit_tb();
3209 dc->is_br = 1;
3210 goto exit_gen_loop;
e8af50a3
FB		 3211 }
3212 }
3213 }
3214 if (spc) {
3215 if (loglevel > 0)
3216 fprintf(logfile, "Search PC...\n");
3217 j = gen_opc_ptr - gen_opc_buf;
3218 if (lj < j) {
3219 lj++;
3220 while (lj < j)
3221 gen_opc_instr_start[lj++] = 0;
3222 gen_opc_pc[lj] = dc->pc;
3223 gen_opc_npc[lj] = dc->npc;
3224 gen_opc_instr_start[lj] = 1;
3225 }
3226 }
cf495bcf
FB		 3227 last_pc = dc->pc;
3228 disas_sparc_insn(dc);
3475187d 3229
cf495bcf
FB		 3230 if (dc->is_br)
3231 break;
3232 /* if the next PC is different, we abort now */
3233 if (dc->pc != (last_pc + 4))
3234 break;
d39c0b99
FB		 3235 /* if we reach a page boundary, we stop generation so that the
3236 PC of a TT_TFAULT exception is always in the right page */
3237 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
3238 break;
e80cfcfc
FB		 3239 /* if single step mode, we generate only one instruction and
3240 generate an exception */
3241 if (env->singlestep_enabled) {
3475187d 3242 gen_jmp_im(dc->pc);
e80cfcfc
FB		 3243 gen_op_movl_T0_0();
3244 gen_op_exit_tb();
3245 break;
3246 }
cf495bcf
FB		 3247 } while ((gen_opc_ptr < gen_opc_end) &&
3248 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
e80cfcfc
FB		 3249
3250 exit_gen_loop:
72cbca10
FB		 3251 if (!dc->is_br) {
3252 if (dc->pc != DYNAMIC_PC &&
3253 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
3254 /* static PC and NPC: we can use direct chaining */
46525e1f 3255 gen_branch(dc, dc->pc, dc->npc);
72cbca10
FB		 3256 } else {
3257 if (dc->pc != DYNAMIC_PC)
3475187d 3258 gen_jmp_im(dc->pc);
72cbca10
FB		 3259 save_npc(dc);
3260 gen_op_movl_T0_0();
3261 gen_op_exit_tb();
3262 }
3263 }
cf495bcf 3264 *gen_opc_ptr = INDEX_op_end;
e8af50a3
FB		 3265 if (spc) {
3266 j = gen_opc_ptr - gen_opc_buf;
3267 lj++;
3268 while (lj <= j)
3269 gen_opc_instr_start[lj++] = 0;
3270 tb->size = 0;
3271#if 0
3272 if (loglevel > 0) {
3273 page_dump(logfile);
3274 }
3275#endif
c3278b7b
FB		 3276 gen_opc_jump_pc[0] = dc->jump_pc[0];
3277 gen_opc_jump_pc[1] = dc->jump_pc[1];
e8af50a3 3278 } else {
e80cfcfc 3279 tb->size = last_pc + 4 - pc_start;
e8af50a3 3280 }
7a3f1944 3281#ifdef DEBUG_DISAS
e19e89a5 3282 if (loglevel & CPU_LOG_TB_IN_ASM) {
cf495bcf 3283 fprintf(logfile, "--------------\n");
0fa85d43
FB		 3284 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3285 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
cf495bcf 3286 fprintf(logfile, "\n");
e19e89a5
FB		 3287 if (loglevel & CPU_LOG_TB_OP) {
3288 fprintf(logfile, "OP:\n");
3289 dump_ops(gen_opc_buf, gen_opparam_buf);
3290 fprintf(logfile, "\n");
3291 }
cf495bcf 3292 }
7a3f1944 3293#endif
cf495bcf 3294 return 0;
7a3f1944
FB		 3295}
3296
cf495bcf 3297int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 3298{
e8af50a3 3299 return gen_intermediate_code_internal(tb, 0, env);
7a3f1944
FB		 3300}
3301
cf495bcf 3302int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 3303{
e8af50a3 3304 return gen_intermediate_code_internal(tb, 1, env);
7a3f1944
FB		 3305}
3306
e80cfcfc 3307extern int ram_size;
cf495bcf 3308
e80cfcfc
FB		 3309void cpu_reset(CPUSPARCState *env)
3310{
bb05683b 3311 tlb_flush(env, 1);
cf495bcf
FB		 3312 env->cwp = 0;
3313 env->wim = 1;
3314 env->regwptr = env->regbase + (env->cwp * 16);
e8af50a3 3315#if defined(CONFIG_USER_ONLY)
cf495bcf 3316 env->user_mode_only = 1;
5ef54116
FB		 3317#ifdef TARGET_SPARC64
3318 env->cleanwin = NWINDOWS - 1;
3319 env->cansave = NWINDOWS - 1;
3320#endif
e8af50a3 3321#else
32af58f9 3322 env->psret = 0;
e8af50a3 3323 env->psrs = 1;
0bee699e 3324 env->psrps = 1;
3475187d 3325#ifdef TARGET_SPARC64
83469015 3326 env->pstate = PS_PRIV;
83469015 3327 env->pc = 0x1fff0000000ULL;
3475187d 3328#else
83469015 3329 env->pc = 0xffd00000;
32af58f9 3330 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
3475187d 3331#endif
83469015 3332 env->npc = env->pc + 4;
e8af50a3 3333#endif
e80cfcfc
FB		 3334}
3335
3336CPUSPARCState *cpu_sparc_init(void)
3337{
3338 CPUSPARCState *env;
3339
c68ea704
FB		 3340 env = qemu_mallocz(sizeof(CPUSPARCState));
3341 if (!env)
3342 return NULL;
3343 cpu_exec_init(env);
e80cfcfc 3344 cpu_reset(env);
cf495bcf 3345 return (env);
7a3f1944
FB		 3346}
3347
62724a37
BS		 3348static const sparc_def_t sparc_defs[] = {
3349#ifdef TARGET_SPARC64
3350 {
3351 .name = "TI UltraSparc II",
3352 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0 << 24)
3353 | (MAXTL << 8) | (NWINDOWS - 1)),
3354 .fpu_version = 0x00000000,
3355 .mmu_version = 0,
3356 },
3357#else
3358 {
3359 .name = "Fujitsu MB86904",
3360 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
3361 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3362 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
3363 },
e0353fe2 3364 {
5ef62c5c
BS		 3365 .name = "Fujitsu MB86907",
3366 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
3367 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3368 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
3369 },
3370 {
3371 .name = "TI MicroSparc I",
3372 .iu_version = 0x41000000,
3373 .fpu_version = 4 << 17,
3374 .mmu_version = 0x41000000,
3375 },
3376 {
e0353fe2
BS		 3377 .name = "TI SuperSparc II",
3378 .iu_version = 0x40000000,
5ef62c5c
BS		 3379 .fpu_version = 0 << 17,
3380 .mmu_version = 0x04000000,
3381 },
3382 {
3383 .name = "Ross RT620",
3384 .iu_version = 0x1e000000,
3385 .fpu_version = 1 << 17,
3386 .mmu_version = 0x17000000,
e0353fe2 3387 },
62724a37
BS		 3388#endif
3389};
3390
3391int sparc_find_by_name(const unsigned char *name, const sparc_def_t **def)
3392{
3393 int ret;
3394 unsigned int i;
3395
3396 ret = -1;
3397 *def = NULL;
3398 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
3399 if (strcasecmp(name, sparc_defs[i].name) == 0) {
3400 *def = &sparc_defs[i];
3401 ret = 0;
3402 break;
3403 }
3404 }
3405
3406 return ret;
3407}
3408
3409void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3410{
3411 unsigned int i;
3412
3413 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
3414 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n",
3415 sparc_defs[i].name,
3416 sparc_defs[i].iu_version,
3417 sparc_defs[i].fpu_version,
3418 sparc_defs[i].mmu_version);
3419 }
3420}
3421
3422int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def)
3423{
3424 env->version = def->iu_version;
3425 env->fsr = def->fpu_version;
3426#if !defined(TARGET_SPARC64)
3427 env->mmuregs[0] = def->mmu_version;
3428#endif
3429 return 0;
3430}
3431
7a3f1944
FB		 3432#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
3433
7fe48483
FB		 3434void cpu_dump_state(CPUState *env, FILE *f,
3435 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
3436 int flags)
7a3f1944 3437{
cf495bcf
FB		 3438 int i, x;
3439
af7bf89b 3440 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
7fe48483 3441 cpu_fprintf(f, "General Registers:\n");
cf495bcf 3442 for (i = 0; i < 4; i++)
af7bf89b 3443 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 3444 cpu_fprintf(f, "\n");
cf495bcf 3445 for (; i < 8; i++)
af7bf89b 3446 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 3447 cpu_fprintf(f, "\nCurrent Register Window:\n");
cf495bcf
FB		 3448 for (x = 0; x < 3; x++) {
3449 for (i = 0; i < 4; i++)
af7bf89b 3450 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
cf495bcf
FB		 3451 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
3452 env->regwptr[i + x * 8]);
7fe48483 3453 cpu_fprintf(f, "\n");
cf495bcf 3454 for (; i < 8; i++)
af7bf89b 3455 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
cf495bcf
FB		 3456 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
3457 env->regwptr[i + x * 8]);
7fe48483 3458 cpu_fprintf(f, "\n");
cf495bcf 3459 }
7fe48483 3460 cpu_fprintf(f, "\nFloating Point Registers:\n");
e8af50a3
FB		 3461 for (i = 0; i < 32; i++) {
3462 if ((i & 3) == 0)
7fe48483
FB		 3463 cpu_fprintf(f, "%%f%02d:", i);
3464 cpu_fprintf(f, " %016lf", env->fpr[i]);
e8af50a3 3465 if ((i & 3) == 3)
7fe48483 3466 cpu_fprintf(f, "\n");
e8af50a3 3467 }
ded3ab80 3468#ifdef TARGET_SPARC64
3299908c
BS		 3469 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
3470 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
ded3ab80
PB		 3471 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
3472 env->cansave, env->canrestore, env->otherwin, env->wstate,
3473 env->cleanwin, NWINDOWS - 1 - env->cwp);
3474#else
7fe48483 3475 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
cf495bcf
FB		 3476 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
3477 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
e8af50a3
FB		 3478 env->psrs?'S':'-', env->psrps?'P':'-',
3479 env->psret?'E':'-', env->wim);
ded3ab80 3480#endif
3475187d 3481 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
7a3f1944 3482}
edfcbd99 3483
e80cfcfc 3484#if defined(CONFIG_USER_ONLY)
9b3c35e0 3485target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
edfcbd99
FB		 3486{
3487 return addr;
3488}
658138bc 3489
e80cfcfc 3490#else
af7bf89b
FB		 3491extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
3492 int *access_index, target_ulong address, int rw,
0fa85d43
FB		 3493 int is_user);
3494
9b3c35e0 3495target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
e80cfcfc 3496{
af7bf89b 3497 target_phys_addr_t phys_addr;
e80cfcfc
FB		 3498 int prot, access_index;
3499
3500 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
6b1575b7
FB		 3501 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 0, 0) != 0)
3502 return -1;
6c36d3fa
BS		 3503 if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
3504 return -1;
e80cfcfc
FB		 3505 return phys_addr;
3506}
3507#endif
3508
658138bc
FB		 3509void helper_flush(target_ulong addr)
3510{
3511 addr &= ~7;
3512 tb_invalidate_page_range(addr, addr + 8);
3513}
Qemu copy for testing