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6e64da3c | 1 | /* |
4f23a1e6 | 2 | * Copyright (C) 2010-2012 Guan Xuetao |
6e64da3c GX |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
c3a8baa9 AF |
7 | * |
8 | * Contributions from 2012-04-01 on are considered under GPL version 2, | |
9 | * or (at your option) any later version. | |
6e64da3c | 10 | */ |
6e64da3c GX |
11 | |
12 | #include "cpu.h" | |
022c62cb | 13 | #include "exec/gdbstub.h" |
6e64da3c | 14 | #include "helper.h" |
1de7afc9 | 15 | #include "qemu/host-utils.h" |
74880fe2 | 16 | #ifndef CONFIG_USER_ONLY |
28ecbaee | 17 | #include "ui/console.h" |
74880fe2 | 18 | #endif |
6e64da3c | 19 | |
527d9979 GX |
20 | #undef DEBUG_UC32 |
21 | ||
22 | #ifdef DEBUG_UC32 | |
23 | #define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__) | |
24 | #else | |
25 | #define DPRINTF(fmt, ...) do {} while (0) | |
26 | #endif | |
27 | ||
eb23b556 | 28 | CPUUniCore32State *uc32_cpu_init(const char *cpu_model) |
6e64da3c | 29 | { |
ae0f5e9e | 30 | UniCore32CPU *cpu; |
eb23b556 | 31 | CPUUniCore32State *env; |
6e64da3c GX |
32 | static int inited = 1; |
33 | ||
ae0f5e9e AF |
34 | if (object_class_by_name(cpu_model) == NULL) { |
35 | return NULL; | |
36 | } | |
37 | cpu = UNICORE32_CPU(object_new(cpu_model)); | |
38 | env = &cpu->env; | |
6e64da3c | 39 | |
6e64da3c GX |
40 | if (inited) { |
41 | inited = 0; | |
42 | uc32_translate_init(); | |
43 | } | |
44 | ||
6e64da3c GX |
45 | qemu_init_vcpu(env); |
46 | return env; | |
47 | } | |
48 | ||
49 | uint32_t HELPER(clo)(uint32_t x) | |
50 | { | |
51 | return clo32(x); | |
52 | } | |
53 | ||
54 | uint32_t HELPER(clz)(uint32_t x) | |
55 | { | |
56 | return clz32(x); | |
57 | } | |
58 | ||
527d9979 GX |
59 | #ifndef CONFIG_USER_ONLY |
60 | void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg, | |
61 | uint32_t cop) | |
4f23a1e6 | 62 | { |
527d9979 GX |
63 | /* |
64 | * movc pp.nn, rn, #imm9 | |
65 | * rn: UCOP_REG_D | |
66 | * nn: UCOP_REG_N | |
67 | * 1: sys control reg. | |
68 | * 2: page table base reg. | |
69 | * 3: data fault status reg. | |
70 | * 4: insn fault status reg. | |
71 | * 5: cache op. reg. | |
72 | * 6: tlb op. reg. | |
73 | * imm9: split UCOP_IMM10 with bit5 is 0 | |
74 | */ | |
75 | switch (creg) { | |
76 | case 1: | |
77 | if (cop != 0) { | |
78 | goto unrecognized; | |
79 | } | |
80 | env->cp0.c1_sys = val; | |
81 | break; | |
82 | case 2: | |
83 | if (cop != 0) { | |
84 | goto unrecognized; | |
85 | } | |
86 | env->cp0.c2_base = val; | |
87 | break; | |
88 | case 3: | |
89 | if (cop != 0) { | |
90 | goto unrecognized; | |
91 | } | |
92 | env->cp0.c3_faultstatus = val; | |
93 | break; | |
94 | case 4: | |
95 | if (cop != 0) { | |
96 | goto unrecognized; | |
97 | } | |
98 | env->cp0.c4_faultaddr = val; | |
99 | break; | |
100 | case 5: | |
101 | switch (cop) { | |
102 | case 28: | |
103 | DPRINTF("Invalidate Entire I&D cache\n"); | |
104 | return; | |
105 | case 20: | |
106 | DPRINTF("Invalidate Entire Icache\n"); | |
107 | return; | |
108 | case 12: | |
109 | DPRINTF("Invalidate Entire Dcache\n"); | |
110 | return; | |
111 | case 10: | |
112 | DPRINTF("Clean Entire Dcache\n"); | |
113 | return; | |
114 | case 14: | |
115 | DPRINTF("Flush Entire Dcache\n"); | |
116 | return; | |
117 | case 13: | |
118 | DPRINTF("Invalidate Dcache line\n"); | |
119 | return; | |
120 | case 11: | |
121 | DPRINTF("Clean Dcache line\n"); | |
122 | return; | |
123 | case 15: | |
124 | DPRINTF("Flush Dcache line\n"); | |
125 | return; | |
126 | } | |
127 | break; | |
128 | case 6: | |
129 | if ((cop <= 6) && (cop >= 2)) { | |
130 | /* invalid all tlb */ | |
131 | tlb_flush(env, 1); | |
132 | return; | |
133 | } | |
134 | break; | |
135 | default: | |
136 | goto unrecognized; | |
4f23a1e6 | 137 | } |
6e64da3c | 138 | return; |
527d9979 GX |
139 | unrecognized: |
140 | DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n", | |
141 | creg, cop); | |
6e64da3c GX |
142 | } |
143 | ||
527d9979 | 144 | uint32_t helper_cp0_get(CPUUniCore32State *env, uint32_t creg, uint32_t cop) |
6e64da3c | 145 | { |
527d9979 GX |
146 | /* |
147 | * movc rd, pp.nn, #imm9 | |
148 | * rd: UCOP_REG_D | |
149 | * nn: UCOP_REG_N | |
150 | * 0: cpuid and cachetype | |
151 | * 1: sys control reg. | |
152 | * 2: page table base reg. | |
153 | * 3: data fault status reg. | |
154 | * 4: insn fault status reg. | |
155 | * imm9: split UCOP_IMM10 with bit5 is 0 | |
156 | */ | |
157 | switch (creg) { | |
158 | case 0: | |
159 | switch (cop) { | |
160 | case 0: | |
161 | return env->cp0.c0_cpuid; | |
162 | case 1: | |
163 | return env->cp0.c0_cachetype; | |
164 | } | |
165 | break; | |
166 | case 1: | |
167 | if (cop == 0) { | |
168 | return env->cp0.c1_sys; | |
169 | } | |
170 | break; | |
171 | case 2: | |
172 | if (cop == 0) { | |
173 | return env->cp0.c2_base; | |
174 | } | |
175 | break; | |
176 | case 3: | |
177 | if (cop == 0) { | |
178 | return env->cp0.c3_faultstatus; | |
179 | } | |
180 | break; | |
181 | case 4: | |
182 | if (cop == 0) { | |
183 | return env->cp0.c4_faultaddr; | |
184 | } | |
185 | break; | |
186 | } | |
187 | DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n", | |
188 | creg, cop); | |
6e64da3c GX |
189 | return 0; |
190 | } | |
191 | ||
ff5928d0 GX |
192 | #ifdef CONFIG_CURSES |
193 | /* | |
194 | * FIXME: | |
195 | * 1. curses windows will be blank when switching back | |
196 | * 2. backspace is not handled yet | |
197 | */ | |
198 | static void putc_on_screen(unsigned char ch) | |
199 | { | |
200 | static WINDOW *localwin; | |
201 | static int init; | |
202 | ||
203 | if (!init) { | |
204 | /* Assume 80 * 30 screen to minimize the implementation */ | |
205 | localwin = newwin(30, 80, 0, 0); | |
206 | scrollok(localwin, TRUE); | |
207 | init = TRUE; | |
208 | } | |
209 | ||
210 | if (isprint(ch)) { | |
211 | wprintw(localwin, "%c", ch); | |
212 | } else { | |
213 | switch (ch) { | |
214 | case '\n': | |
215 | wprintw(localwin, "%c", ch); | |
216 | break; | |
217 | case '\r': | |
218 | /* If '\r' is put before '\n', the curses window will destroy the | |
219 | * last print line. And meanwhile, '\n' implifies '\r' inside. */ | |
220 | break; | |
221 | default: /* Not handled, so just print it hex code */ | |
222 | wprintw(localwin, "-- 0x%x --", ch); | |
223 | } | |
224 | } | |
225 | ||
226 | wrefresh(localwin); | |
227 | } | |
228 | #else | |
229 | #define putc_on_screen(c) do { } while (0) | |
230 | #endif | |
231 | ||
527d9979 | 232 | void helper_cp1_putc(target_ulong x) |
6e64da3c | 233 | { |
ff5928d0 GX |
234 | putc_on_screen((unsigned char)x); /* Output to screen */ |
235 | DPRINTF("%c", x); /* Output to stdout */ | |
6e64da3c | 236 | } |
527d9979 | 237 | #endif |
6e64da3c | 238 | |
527d9979 GX |
239 | #ifdef CONFIG_USER_ONLY |
240 | void switch_mode(CPUUniCore32State *env, int mode) | |
6e64da3c | 241 | { |
527d9979 GX |
242 | if (mode != ASR_MODE_USER) { |
243 | cpu_abort(env, "Tried to switch out of user mode\n"); | |
244 | } | |
6e64da3c GX |
245 | } |
246 | ||
527d9979 | 247 | void do_interrupt(CPUUniCore32State *env) |
6e64da3c | 248 | { |
527d9979 | 249 | cpu_abort(env, "NO interrupt in user mode\n"); |
6e64da3c GX |
250 | } |
251 | ||
527d9979 GX |
252 | int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, |
253 | int access_type, int mmu_idx) | |
6e64da3c | 254 | { |
527d9979 GX |
255 | cpu_abort(env, "NO mmu fault in user mode\n"); |
256 | return 1; | |
6e64da3c | 257 | } |
527d9979 | 258 | #endif |