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tcg/optimize: fix setcond2 optimization
[qemu.git] / target-xtensa / cpu.c
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1/*
2 * QEMU Xtensa CPU
3 *
5087a72c 4 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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5 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
15be3171 31#include "cpu.h"
a4633e16 32#include "qemu-common.h"
004a5690 33#include "migration/vmstate.h"
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34
35
36/* CPUClass::reset() */
37static void xtensa_cpu_reset(CPUState *s)
38{
39 XtensaCPU *cpu = XTENSA_CPU(s);
40 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
41 CPUXtensaState *env = &cpu->env;
42
43 xcc->parent_reset(s);
44
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45 env->exception_taken = 0;
46 env->pc = env->config->exception_vector[EXC_RESET];
47 env->sregs[LITBASE] &= ~1;
48 env->sregs[PS] = xtensa_option_enabled(env->config,
49 XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
50 env->sregs[VECBASE] = env->config->vecbase;
51 env->sregs[IBREAKENABLE] = 0;
4e41d2f5 52 env->sregs[CACHEATTR] = 0x22222222;
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53 env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
54 XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
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55
56 env->pending_irq_level = 0;
57 reset_mmu(env);
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58}
59
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60static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
61{
62 XtensaCPU *cpu = XTENSA_CPU(dev);
63 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
64
65 qemu_init_vcpu(&cpu->env);
66
67 xcc->parent_realize(dev, errp);
68}
69
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70static void xtensa_cpu_initfn(Object *obj)
71{
c05efcb1 72 CPUState *cs = CPU(obj);
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73 XtensaCPU *cpu = XTENSA_CPU(obj);
74 CPUXtensaState *env = &cpu->env;
25733ead 75 static bool tcg_inited;
e554bbc6 76
c05efcb1 77 cs->env_ptr = env;
e554bbc6 78 cpu_exec_init(env);
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79
80 if (tcg_enabled() && !tcg_inited) {
81 tcg_inited = true;
82 xtensa_translate_init();
83 cpu_set_debug_excp_handler(xtensa_breakpoint_handler);
84 }
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85}
86
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87static const VMStateDescription vmstate_xtensa_cpu = {
88 .name = "cpu",
89 .unmigratable = 1,
90};
91
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92static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
93{
004a5690 94 DeviceClass *dc = DEVICE_CLASS(oc);
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95 CPUClass *cc = CPU_CLASS(oc);
96 XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
97
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98 xcc->parent_realize = dc->realize;
99 dc->realize = xtensa_cpu_realizefn;
100
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101 xcc->parent_reset = cc->reset;
102 cc->reset = xtensa_cpu_reset;
004a5690 103
97a8ea5a 104 cc->do_interrupt = xtensa_cpu_do_interrupt;
004a5690 105 dc->vmsd = &vmstate_xtensa_cpu;
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106}
107
108static const TypeInfo xtensa_cpu_type_info = {
109 .name = TYPE_XTENSA_CPU,
110 .parent = TYPE_CPU,
111 .instance_size = sizeof(XtensaCPU),
e554bbc6 112 .instance_init = xtensa_cpu_initfn,
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113 .abstract = false,
114 .class_size = sizeof(XtensaCPUClass),
115 .class_init = xtensa_cpu_class_init,
116};
117
118static void xtensa_cpu_register_types(void)
119{
120 type_register_static(&xtensa_cpu_type_info);
121}
122
123type_init(xtensa_cpu_register_types)