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a4633e16 AF |
1 | /* |
2 | * QEMU Xtensa CPU | |
3 | * | |
5087a72c | 4 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. |
a4633e16 AF |
5 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
6 | * All rights reserved. | |
7 | * | |
8 | * Redistribution and use in source and binary forms, with or without | |
9 | * modification, are permitted provided that the following conditions are met: | |
10 | * * Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions and the following disclaimer. | |
12 | * * Redistributions in binary form must reproduce the above copyright | |
13 | * notice, this list of conditions and the following disclaimer in the | |
14 | * documentation and/or other materials provided with the distribution. | |
15 | * * Neither the name of the Open Source and Linux Lab nor the | |
16 | * names of its contributors may be used to endorse or promote products | |
17 | * derived from this software without specific prior written permission. | |
18 | * | |
19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
23 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
26 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
29 | */ | |
30 | ||
15be3171 | 31 | #include "cpu.h" |
a4633e16 | 32 | #include "qemu-common.h" |
004a5690 | 33 | #include "migration/vmstate.h" |
a4633e16 AF |
34 | |
35 | ||
f45748f1 AF |
36 | static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) |
37 | { | |
38 | XtensaCPU *cpu = XTENSA_CPU(cs); | |
39 | ||
40 | cpu->env.pc = value; | |
41 | } | |
42 | ||
a4633e16 AF |
43 | /* CPUClass::reset() */ |
44 | static void xtensa_cpu_reset(CPUState *s) | |
45 | { | |
46 | XtensaCPU *cpu = XTENSA_CPU(s); | |
47 | XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu); | |
48 | CPUXtensaState *env = &cpu->env; | |
49 | ||
50 | xcc->parent_reset(s); | |
51 | ||
5087a72c AF |
52 | env->exception_taken = 0; |
53 | env->pc = env->config->exception_vector[EXC_RESET]; | |
54 | env->sregs[LITBASE] &= ~1; | |
55 | env->sregs[PS] = xtensa_option_enabled(env->config, | |
56 | XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; | |
57 | env->sregs[VECBASE] = env->config->vecbase; | |
58 | env->sregs[IBREAKENABLE] = 0; | |
4e41d2f5 | 59 | env->sregs[CACHEATTR] = 0x22222222; |
fcc803d1 MF |
60 | env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, |
61 | XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; | |
5087a72c AF |
62 | |
63 | env->pending_irq_level = 0; | |
64 | reset_mmu(env); | |
a4633e16 AF |
65 | } |
66 | ||
67cce561 AF |
67 | static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) |
68 | { | |
69 | ObjectClass *oc; | |
70 | char *typename; | |
71 | ||
72 | if (cpu_model == NULL) { | |
73 | return NULL; | |
74 | } | |
75 | ||
76 | typename = g_strdup_printf("%s-" TYPE_XTENSA_CPU, cpu_model); | |
77 | oc = object_class_by_name(typename); | |
78 | g_free(typename); | |
79 | if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) || | |
80 | object_class_is_abstract(oc)) { | |
81 | return NULL; | |
82 | } | |
83 | return oc; | |
84 | } | |
85 | ||
5f6c9643 AF |
86 | static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp) |
87 | { | |
a0e372f0 | 88 | CPUState *cs = CPU(dev); |
5f6c9643 AF |
89 | XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev); |
90 | ||
a0e372f0 AF |
91 | cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs; |
92 | ||
14a10fc3 AF |
93 | qemu_init_vcpu(cs); |
94 | ||
5f6c9643 AF |
95 | xcc->parent_realize(dev, errp); |
96 | } | |
97 | ||
e554bbc6 AF |
98 | static void xtensa_cpu_initfn(Object *obj) |
99 | { | |
c05efcb1 | 100 | CPUState *cs = CPU(obj); |
e554bbc6 | 101 | XtensaCPU *cpu = XTENSA_CPU(obj); |
67cce561 | 102 | XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj); |
e554bbc6 | 103 | CPUXtensaState *env = &cpu->env; |
25733ead | 104 | static bool tcg_inited; |
e554bbc6 | 105 | |
c05efcb1 | 106 | cs->env_ptr = env; |
67cce561 | 107 | env->config = xcc->config; |
e554bbc6 | 108 | cpu_exec_init(env); |
25733ead AF |
109 | |
110 | if (tcg_enabled() && !tcg_inited) { | |
111 | tcg_inited = true; | |
112 | xtensa_translate_init(); | |
113 | cpu_set_debug_excp_handler(xtensa_breakpoint_handler); | |
114 | } | |
e554bbc6 AF |
115 | } |
116 | ||
004a5690 AF |
117 | static const VMStateDescription vmstate_xtensa_cpu = { |
118 | .name = "cpu", | |
119 | .unmigratable = 1, | |
120 | }; | |
121 | ||
a4633e16 AF |
122 | static void xtensa_cpu_class_init(ObjectClass *oc, void *data) |
123 | { | |
004a5690 | 124 | DeviceClass *dc = DEVICE_CLASS(oc); |
a4633e16 AF |
125 | CPUClass *cc = CPU_CLASS(oc); |
126 | XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc); | |
127 | ||
5f6c9643 AF |
128 | xcc->parent_realize = dc->realize; |
129 | dc->realize = xtensa_cpu_realizefn; | |
130 | ||
a4633e16 AF |
131 | xcc->parent_reset = cc->reset; |
132 | cc->reset = xtensa_cpu_reset; | |
004a5690 | 133 | |
67cce561 | 134 | cc->class_by_name = xtensa_cpu_class_by_name; |
97a8ea5a | 135 | cc->do_interrupt = xtensa_cpu_do_interrupt; |
878096ee | 136 | cc->dump_state = xtensa_cpu_dump_state; |
f45748f1 | 137 | cc->set_pc = xtensa_cpu_set_pc; |
5b50e790 AF |
138 | cc->gdb_read_register = xtensa_cpu_gdb_read_register; |
139 | cc->gdb_write_register = xtensa_cpu_gdb_write_register; | |
00b941e5 AF |
140 | #ifndef CONFIG_USER_ONLY |
141 | cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug; | |
142 | #endif | |
004a5690 | 143 | dc->vmsd = &vmstate_xtensa_cpu; |
a4633e16 AF |
144 | } |
145 | ||
146 | static const TypeInfo xtensa_cpu_type_info = { | |
147 | .name = TYPE_XTENSA_CPU, | |
148 | .parent = TYPE_CPU, | |
149 | .instance_size = sizeof(XtensaCPU), | |
e554bbc6 | 150 | .instance_init = xtensa_cpu_initfn, |
67cce561 | 151 | .abstract = true, |
a4633e16 AF |
152 | .class_size = sizeof(XtensaCPUClass), |
153 | .class_init = xtensa_cpu_class_init, | |
154 | }; | |
155 | ||
156 | static void xtensa_cpu_register_types(void) | |
157 | { | |
158 | type_register_static(&xtensa_cpu_type_info); | |
159 | } | |
160 | ||
161 | type_init(xtensa_cpu_register_types) |