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2328826b MF |
1 | /* |
2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * * Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * * Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * * Neither the name of the Open Source and Linux Lab nor the | |
13 | * names of its contributors may be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
28 | #ifndef CPU_XTENSA_H | |
29 | #define CPU_XTENSA_H | |
30 | ||
31 | #define TARGET_LONG_BITS 32 | |
32 | #define ELF_MACHINE EM_XTENSA | |
33 | ||
34 | #define CPUState struct CPUXtensaState | |
35 | ||
36 | #include "config.h" | |
37 | #include "qemu-common.h" | |
38 | #include "cpu-defs.h" | |
39 | ||
40 | #define TARGET_HAS_ICE 1 | |
41 | ||
42 | #define NB_MMU_MODES 4 | |
43 | ||
44 | #define TARGET_PHYS_ADDR_SPACE_BITS 32 | |
45 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
46 | #define TARGET_PAGE_BITS 12 | |
47 | ||
dedc5eae MF |
48 | enum { |
49 | /* Additional instructions */ | |
50 | XTENSA_OPTION_CODE_DENSITY, | |
51 | XTENSA_OPTION_LOOP, | |
52 | XTENSA_OPTION_EXTENDED_L32R, | |
53 | XTENSA_OPTION_16_BIT_IMUL, | |
54 | XTENSA_OPTION_32_BIT_IMUL, | |
55 | XTENSA_OPTION_32_BIT_IDIV, | |
56 | XTENSA_OPTION_MAC16, | |
57 | XTENSA_OPTION_MISC_OP, | |
58 | XTENSA_OPTION_COPROCESSOR, | |
59 | XTENSA_OPTION_BOOLEAN, | |
60 | XTENSA_OPTION_FP_COPROCESSOR, | |
61 | XTENSA_OPTION_MP_SYNCHRO, | |
62 | XTENSA_OPTION_CONDITIONAL_STORE, | |
63 | ||
64 | /* Interrupts and exceptions */ | |
65 | XTENSA_OPTION_EXCEPTION, | |
66 | XTENSA_OPTION_RELOCATABLE_VECTOR, | |
67 | XTENSA_OPTION_UNALIGNED_EXCEPTION, | |
68 | XTENSA_OPTION_INTERRUPT, | |
69 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, | |
70 | XTENSA_OPTION_TIMER_INTERRUPT, | |
71 | ||
72 | /* Local memory */ | |
73 | XTENSA_OPTION_ICACHE, | |
74 | XTENSA_OPTION_ICACHE_TEST, | |
75 | XTENSA_OPTION_ICACHE_INDEX_LOCK, | |
76 | XTENSA_OPTION_DCACHE, | |
77 | XTENSA_OPTION_DCACHE_TEST, | |
78 | XTENSA_OPTION_DCACHE_INDEX_LOCK, | |
79 | XTENSA_OPTION_IRAM, | |
80 | XTENSA_OPTION_IROM, | |
81 | XTENSA_OPTION_DRAM, | |
82 | XTENSA_OPTION_DROM, | |
83 | XTENSA_OPTION_XLMI, | |
84 | XTENSA_OPTION_HW_ALIGNMENT, | |
85 | XTENSA_OPTION_MEMORY_ECC_PARITY, | |
86 | ||
87 | /* Memory protection and translation */ | |
88 | XTENSA_OPTION_REGION_PROTECTION, | |
89 | XTENSA_OPTION_REGION_TRANSLATION, | |
90 | XTENSA_OPTION_MMU, | |
91 | ||
92 | /* Other */ | |
93 | XTENSA_OPTION_WINDOWED_REGISTER, | |
94 | XTENSA_OPTION_PROCESSOR_INTERFACE, | |
95 | XTENSA_OPTION_MISC_SR, | |
96 | XTENSA_OPTION_THREAD_POINTER, | |
97 | XTENSA_OPTION_PROCESSOR_ID, | |
98 | XTENSA_OPTION_DEBUG, | |
99 | XTENSA_OPTION_TRACE_PORT, | |
100 | }; | |
101 | ||
2af3da91 MF |
102 | enum { |
103 | THREADPTR = 231, | |
104 | FCR = 232, | |
105 | FSR = 233, | |
106 | }; | |
107 | ||
dedc5eae MF |
108 | typedef struct XtensaConfig { |
109 | const char *name; | |
110 | uint64_t options; | |
111 | } XtensaConfig; | |
112 | ||
2328826b | 113 | typedef struct CPUXtensaState { |
dedc5eae | 114 | const XtensaConfig *config; |
2328826b MF |
115 | uint32_t regs[16]; |
116 | uint32_t pc; | |
117 | uint32_t sregs[256]; | |
2af3da91 | 118 | uint32_t uregs[256]; |
2328826b MF |
119 | |
120 | CPU_COMMON | |
121 | } CPUXtensaState; | |
122 | ||
123 | #define cpu_init cpu_xtensa_init | |
124 | #define cpu_exec cpu_xtensa_exec | |
125 | #define cpu_gen_code cpu_xtensa_gen_code | |
126 | #define cpu_signal_handler cpu_xtensa_signal_handler | |
127 | #define cpu_list xtensa_cpu_list | |
128 | ||
129 | CPUXtensaState *cpu_xtensa_init(const char *cpu_model); | |
130 | void xtensa_translate_init(void); | |
131 | int cpu_xtensa_exec(CPUXtensaState *s); | |
132 | void do_interrupt(CPUXtensaState *s); | |
133 | int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); | |
134 | void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf); | |
135 | ||
dedc5eae MF |
136 | #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) |
137 | ||
138 | static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt) | |
139 | { | |
140 | return (config->options & XTENSA_OPTION_BIT(opt)) != 0; | |
141 | } | |
142 | ||
2328826b MF |
143 | static inline int cpu_mmu_index(CPUState *env) |
144 | { | |
145 | return 0; | |
146 | } | |
147 | ||
148 | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, | |
149 | target_ulong *cs_base, int *flags) | |
150 | { | |
151 | *pc = env->pc; | |
152 | *cs_base = 0; | |
153 | *flags = 0; | |
154 | } | |
155 | ||
156 | #include "cpu-all.h" | |
157 | #include "exec-all.h" | |
158 | ||
159 | static inline int cpu_has_work(CPUState *env) | |
160 | { | |
161 | return 1; | |
162 | } | |
163 | ||
164 | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) | |
165 | { | |
166 | env->pc = tb->pc; | |
167 | } | |
168 | ||
169 | #endif |