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2328826b MF |
1 | /* |
2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * * Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * * Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * * Neither the name of the Open Source and Linux Lab nor the | |
13 | * names of its contributors may be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
28 | #ifndef CPU_XTENSA_H | |
29 | #define CPU_XTENSA_H | |
30 | ||
31 | #define TARGET_LONG_BITS 32 | |
32 | #define ELF_MACHINE EM_XTENSA | |
33 | ||
34 | #define CPUState struct CPUXtensaState | |
35 | ||
36 | #include "config.h" | |
37 | #include "qemu-common.h" | |
38 | #include "cpu-defs.h" | |
39 | ||
40 | #define TARGET_HAS_ICE 1 | |
41 | ||
42 | #define NB_MMU_MODES 4 | |
43 | ||
44 | #define TARGET_PHYS_ADDR_SPACE_BITS 32 | |
45 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
46 | #define TARGET_PAGE_BITS 12 | |
47 | ||
dedc5eae MF |
48 | enum { |
49 | /* Additional instructions */ | |
50 | XTENSA_OPTION_CODE_DENSITY, | |
51 | XTENSA_OPTION_LOOP, | |
52 | XTENSA_OPTION_EXTENDED_L32R, | |
53 | XTENSA_OPTION_16_BIT_IMUL, | |
54 | XTENSA_OPTION_32_BIT_IMUL, | |
55 | XTENSA_OPTION_32_BIT_IDIV, | |
56 | XTENSA_OPTION_MAC16, | |
57 | XTENSA_OPTION_MISC_OP, | |
58 | XTENSA_OPTION_COPROCESSOR, | |
59 | XTENSA_OPTION_BOOLEAN, | |
60 | XTENSA_OPTION_FP_COPROCESSOR, | |
61 | XTENSA_OPTION_MP_SYNCHRO, | |
62 | XTENSA_OPTION_CONDITIONAL_STORE, | |
63 | ||
64 | /* Interrupts and exceptions */ | |
65 | XTENSA_OPTION_EXCEPTION, | |
66 | XTENSA_OPTION_RELOCATABLE_VECTOR, | |
67 | XTENSA_OPTION_UNALIGNED_EXCEPTION, | |
68 | XTENSA_OPTION_INTERRUPT, | |
69 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, | |
70 | XTENSA_OPTION_TIMER_INTERRUPT, | |
71 | ||
72 | /* Local memory */ | |
73 | XTENSA_OPTION_ICACHE, | |
74 | XTENSA_OPTION_ICACHE_TEST, | |
75 | XTENSA_OPTION_ICACHE_INDEX_LOCK, | |
76 | XTENSA_OPTION_DCACHE, | |
77 | XTENSA_OPTION_DCACHE_TEST, | |
78 | XTENSA_OPTION_DCACHE_INDEX_LOCK, | |
79 | XTENSA_OPTION_IRAM, | |
80 | XTENSA_OPTION_IROM, | |
81 | XTENSA_OPTION_DRAM, | |
82 | XTENSA_OPTION_DROM, | |
83 | XTENSA_OPTION_XLMI, | |
84 | XTENSA_OPTION_HW_ALIGNMENT, | |
85 | XTENSA_OPTION_MEMORY_ECC_PARITY, | |
86 | ||
87 | /* Memory protection and translation */ | |
88 | XTENSA_OPTION_REGION_PROTECTION, | |
89 | XTENSA_OPTION_REGION_TRANSLATION, | |
90 | XTENSA_OPTION_MMU, | |
91 | ||
92 | /* Other */ | |
93 | XTENSA_OPTION_WINDOWED_REGISTER, | |
94 | XTENSA_OPTION_PROCESSOR_INTERFACE, | |
95 | XTENSA_OPTION_MISC_SR, | |
96 | XTENSA_OPTION_THREAD_POINTER, | |
97 | XTENSA_OPTION_PROCESSOR_ID, | |
98 | XTENSA_OPTION_DEBUG, | |
99 | XTENSA_OPTION_TRACE_PORT, | |
100 | }; | |
101 | ||
2af3da91 MF |
102 | enum { |
103 | THREADPTR = 231, | |
104 | FCR = 232, | |
105 | FSR = 233, | |
106 | }; | |
107 | ||
3580ecad | 108 | enum { |
797d780b MF |
109 | LBEG = 0, |
110 | LEND = 1, | |
111 | LCOUNT = 2, | |
3580ecad | 112 | SAR = 3, |
809377aa | 113 | SCOMPARE1 = 12, |
553e44f9 MF |
114 | WINDOW_BASE = 72, |
115 | WINDOW_START = 73, | |
40643d7c MF |
116 | EPC1 = 177, |
117 | DEPC = 192, | |
118 | EXCSAVE1 = 209, | |
f0a548b9 | 119 | PS = 230, |
40643d7c MF |
120 | EXCCAUSE = 232, |
121 | EXCVADDR = 238, | |
3580ecad MF |
122 | }; |
123 | ||
f0a548b9 MF |
124 | #define PS_INTLEVEL 0xf |
125 | #define PS_INTLEVEL_SHIFT 0 | |
126 | ||
127 | #define PS_EXCM 0x10 | |
128 | #define PS_UM 0x20 | |
129 | ||
130 | #define PS_RING 0xc0 | |
131 | #define PS_RING_SHIFT 6 | |
132 | ||
133 | #define PS_OWB 0xf00 | |
134 | #define PS_OWB_SHIFT 8 | |
135 | ||
136 | #define PS_CALLINC 0x30000 | |
137 | #define PS_CALLINC_SHIFT 16 | |
138 | #define PS_CALLINC_LEN 2 | |
139 | ||
140 | #define PS_WOE 0x40000 | |
141 | ||
553e44f9 MF |
142 | #define MAX_NAREG 64 |
143 | ||
40643d7c MF |
144 | enum { |
145 | /* Static vectors */ | |
146 | EXC_RESET, | |
147 | EXC_MEMORY_ERROR, | |
148 | ||
149 | /* Dynamic vectors */ | |
150 | EXC_WINDOW_OVERFLOW4, | |
151 | EXC_WINDOW_UNDERFLOW4, | |
152 | EXC_WINDOW_OVERFLOW8, | |
153 | EXC_WINDOW_UNDERFLOW8, | |
154 | EXC_WINDOW_OVERFLOW12, | |
155 | EXC_WINDOW_UNDERFLOW12, | |
156 | EXC_IRQ, | |
157 | EXC_KERNEL, | |
158 | EXC_USER, | |
159 | EXC_DOUBLE, | |
160 | EXC_MAX | |
161 | }; | |
162 | ||
163 | enum { | |
164 | ILLEGAL_INSTRUCTION_CAUSE = 0, | |
165 | SYSCALL_CAUSE, | |
166 | INSTRUCTION_FETCH_ERROR_CAUSE, | |
167 | LOAD_STORE_ERROR_CAUSE, | |
168 | LEVEL1_INTERRUPT_CAUSE, | |
169 | ALLOCA_CAUSE, | |
170 | INTEGER_DIVIDE_BY_ZERO_CAUSE, | |
171 | PRIVILEGED_CAUSE = 8, | |
172 | LOAD_STORE_ALIGNMENT_CAUSE, | |
173 | ||
174 | INSTR_PIF_DATA_ERROR_CAUSE = 12, | |
175 | LOAD_STORE_PIF_DATA_ERROR_CAUSE, | |
176 | INSTR_PIF_ADDR_ERROR_CAUSE, | |
177 | LOAD_STORE_PIF_ADDR_ERROR_CAUSE, | |
178 | ||
179 | INST_TLB_MISS_CAUSE, | |
180 | INST_TLB_MULTI_HIT_CAUSE, | |
181 | INST_FETCH_PRIVILEGE_CAUSE, | |
182 | INST_FETCH_PROHIBITED_CAUSE = 20, | |
183 | LOAD_STORE_TLB_MISS_CAUSE = 24, | |
184 | LOAD_STORE_TLB_MULTI_HIT_CAUSE, | |
185 | LOAD_STORE_PRIVILEGE_CAUSE, | |
186 | LOAD_PROHIBITED_CAUSE = 28, | |
187 | STORE_PROHIBITED_CAUSE, | |
188 | ||
189 | COPROCESSOR0_DISABLED = 32, | |
190 | }; | |
191 | ||
dedc5eae MF |
192 | typedef struct XtensaConfig { |
193 | const char *name; | |
194 | uint64_t options; | |
553e44f9 | 195 | unsigned nareg; |
40643d7c MF |
196 | int excm_level; |
197 | int ndepc; | |
198 | uint32_t exception_vector[EXC_MAX]; | |
dedc5eae MF |
199 | } XtensaConfig; |
200 | ||
2328826b | 201 | typedef struct CPUXtensaState { |
dedc5eae | 202 | const XtensaConfig *config; |
2328826b MF |
203 | uint32_t regs[16]; |
204 | uint32_t pc; | |
205 | uint32_t sregs[256]; | |
2af3da91 | 206 | uint32_t uregs[256]; |
553e44f9 | 207 | uint32_t phys_regs[MAX_NAREG]; |
2328826b | 208 | |
40643d7c MF |
209 | int exception_taken; |
210 | ||
2328826b MF |
211 | CPU_COMMON |
212 | } CPUXtensaState; | |
213 | ||
214 | #define cpu_init cpu_xtensa_init | |
215 | #define cpu_exec cpu_xtensa_exec | |
216 | #define cpu_gen_code cpu_xtensa_gen_code | |
217 | #define cpu_signal_handler cpu_xtensa_signal_handler | |
218 | #define cpu_list xtensa_cpu_list | |
219 | ||
220 | CPUXtensaState *cpu_xtensa_init(const char *cpu_model); | |
221 | void xtensa_translate_init(void); | |
222 | int cpu_xtensa_exec(CPUXtensaState *s); | |
223 | void do_interrupt(CPUXtensaState *s); | |
224 | int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); | |
225 | void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf); | |
553e44f9 MF |
226 | void xtensa_sync_window_from_phys(CPUState *env); |
227 | void xtensa_sync_phys_from_window(CPUState *env); | |
2328826b | 228 | |
dedc5eae MF |
229 | #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) |
230 | ||
231 | static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt) | |
232 | { | |
233 | return (config->options & XTENSA_OPTION_BIT(opt)) != 0; | |
234 | } | |
235 | ||
40643d7c MF |
236 | static inline int xtensa_get_cintlevel(const CPUState *env) |
237 | { | |
238 | int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT; | |
239 | if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) { | |
240 | level = env->config->excm_level; | |
241 | } | |
242 | return level; | |
243 | } | |
244 | ||
f0a548b9 MF |
245 | static inline int xtensa_get_ring(const CPUState *env) |
246 | { | |
247 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
248 | return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; | |
249 | } else { | |
250 | return 0; | |
251 | } | |
252 | } | |
253 | ||
254 | static inline int xtensa_get_cring(const CPUState *env) | |
255 | { | |
256 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) && | |
257 | (env->sregs[PS] & PS_EXCM) == 0) { | |
258 | return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; | |
259 | } else { | |
260 | return 0; | |
261 | } | |
262 | } | |
263 | ||
264 | /* MMU modes definitions */ | |
265 | #define MMU_MODE0_SUFFIX _ring0 | |
266 | #define MMU_MODE1_SUFFIX _ring1 | |
267 | #define MMU_MODE2_SUFFIX _ring2 | |
268 | #define MMU_MODE3_SUFFIX _ring3 | |
269 | ||
2328826b MF |
270 | static inline int cpu_mmu_index(CPUState *env) |
271 | { | |
f0a548b9 | 272 | return xtensa_get_cring(env); |
2328826b MF |
273 | } |
274 | ||
f0a548b9 MF |
275 | #define XTENSA_TBFLAG_RING_MASK 0x3 |
276 | #define XTENSA_TBFLAG_EXCM 0x4 | |
277 | ||
2328826b MF |
278 | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
279 | target_ulong *cs_base, int *flags) | |
280 | { | |
281 | *pc = env->pc; | |
282 | *cs_base = 0; | |
283 | *flags = 0; | |
f0a548b9 MF |
284 | *flags |= xtensa_get_ring(env); |
285 | if (env->sregs[PS] & PS_EXCM) { | |
286 | *flags |= XTENSA_TBFLAG_EXCM; | |
287 | } | |
2328826b MF |
288 | } |
289 | ||
290 | #include "cpu-all.h" | |
291 | #include "exec-all.h" | |
292 | ||
293 | static inline int cpu_has_work(CPUState *env) | |
294 | { | |
295 | return 1; | |
296 | } | |
297 | ||
298 | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) | |
299 | { | |
300 | env->pc = tb->pc; | |
301 | } | |
302 | ||
303 | #endif |