[qemu.git] / target-xtensa / cpu.h

/*
 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of the Open Source and Linux Lab nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef CPU_XTENSA_H
#define CPU_XTENSA_H

#define TARGET_LONG_BITS 32
#define ELF_MACHINE EM_XTENSA

#define CPUArchState struct CPUXtensaState

#include "config.h"
#include "qemu-common.h"
#include "cpu-defs.h"
#include "fpu/softfloat.h"

#define TARGET_HAS_ICE 1

#define NB_MMU_MODES 4

#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define TARGET_PAGE_BITS 12

enum {
    /* Additional instructions */
    XTENSA_OPTION_CODE_DENSITY,
    XTENSA_OPTION_LOOP,
    XTENSA_OPTION_EXTENDED_L32R,
    XTENSA_OPTION_16_BIT_IMUL,
    XTENSA_OPTION_32_BIT_IMUL,
    XTENSA_OPTION_32_BIT_IMUL_HIGH,
    XTENSA_OPTION_32_BIT_IDIV,
    XTENSA_OPTION_MAC16,
    XTENSA_OPTION_MISC_OP_NSA,
    XTENSA_OPTION_MISC_OP_MINMAX,
    XTENSA_OPTION_MISC_OP_SEXT,
    XTENSA_OPTION_MISC_OP_CLAMPS,
    XTENSA_OPTION_COPROCESSOR,
    XTENSA_OPTION_BOOLEAN,
    XTENSA_OPTION_FP_COPROCESSOR,
    XTENSA_OPTION_MP_SYNCHRO,
    XTENSA_OPTION_CONDITIONAL_STORE,
    XTENSA_OPTION_ATOMCTL,

    /* Interrupts and exceptions */
    XTENSA_OPTION_EXCEPTION,
    XTENSA_OPTION_RELOCATABLE_VECTOR,
    XTENSA_OPTION_UNALIGNED_EXCEPTION,
    XTENSA_OPTION_INTERRUPT,
    XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
    XTENSA_OPTION_TIMER_INTERRUPT,

    /* Local memory */
    XTENSA_OPTION_ICACHE,
    XTENSA_OPTION_ICACHE_TEST,
    XTENSA_OPTION_ICACHE_INDEX_LOCK,
    XTENSA_OPTION_DCACHE,
    XTENSA_OPTION_DCACHE_TEST,
    XTENSA_OPTION_DCACHE_INDEX_LOCK,
    XTENSA_OPTION_IRAM,
    XTENSA_OPTION_IROM,
    XTENSA_OPTION_DRAM,
    XTENSA_OPTION_DROM,
    XTENSA_OPTION_XLMI,
    XTENSA_OPTION_HW_ALIGNMENT,
    XTENSA_OPTION_MEMORY_ECC_PARITY,

    /* Memory protection and translation */
    XTENSA_OPTION_REGION_PROTECTION,
    XTENSA_OPTION_REGION_TRANSLATION,
    XTENSA_OPTION_MMU,

    /* Other */
    XTENSA_OPTION_WINDOWED_REGISTER,
    XTENSA_OPTION_PROCESSOR_INTERFACE,
    XTENSA_OPTION_MISC_SR,
    XTENSA_OPTION_THREAD_POINTER,
    XTENSA_OPTION_PROCESSOR_ID,
    XTENSA_OPTION_DEBUG,
    XTENSA_OPTION_TRACE_PORT,
};

enum {
    THREADPTR = 231,
    FCR = 232,
    FSR = 233,
};

enum {
    LBEG = 0,
    LEND = 1,
    LCOUNT = 2,
    SAR = 3,
    BR = 4,
    LITBASE = 5,
    SCOMPARE1 = 12,
    ACCLO = 16,
    ACCHI = 17,
    MR = 32,
    WINDOW_BASE = 72,
    WINDOW_START = 73,
    PTEVADDR = 83,
    RASID = 90,
    ITLBCFG = 91,
    DTLBCFG = 92,
    IBREAKENABLE = 96,
    ATOMCTL = 99,
    IBREAKA = 128,
    DBREAKA = 144,
    DBREAKC = 160,
    EPC1 = 177,
    DEPC = 192,
    EPS2 = 194,
    EXCSAVE1 = 209,
    CPENABLE = 224,
    INTSET = 226,
    INTCLEAR = 227,
    INTENABLE = 228,
    PS = 230,
    VECBASE = 231,
    EXCCAUSE = 232,
    DEBUGCAUSE = 233,
    CCOUNT = 234,
    PRID = 235,
    ICOUNT = 236,
    ICOUNTLEVEL = 237,
    EXCVADDR = 238,
    CCOMPARE = 240,
};

#define PS_INTLEVEL 0xf
#define PS_INTLEVEL_SHIFT 0

#define PS_EXCM 0x10
#define PS_UM 0x20

#define PS_RING 0xc0
#define PS_RING_SHIFT 6

#define PS_OWB 0xf00
#define PS_OWB_SHIFT 8

#define PS_CALLINC 0x30000
#define PS_CALLINC_SHIFT 16
#define PS_CALLINC_LEN 2

#define PS_WOE 0x40000

#define DEBUGCAUSE_IC 0x1
#define DEBUGCAUSE_IB 0x2
#define DEBUGCAUSE_DB 0x4
#define DEBUGCAUSE_BI 0x8
#define DEBUGCAUSE_BN 0x10
#define DEBUGCAUSE_DI 0x20
#define DEBUGCAUSE_DBNUM 0xf00
#define DEBUGCAUSE_DBNUM_SHIFT 8

#define DBREAKC_SB 0x80000000
#define DBREAKC_LB 0x40000000
#define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
#define DBREAKC_MASK 0x3f

#define MAX_NAREG 64
#define MAX_NINTERRUPT 32
#define MAX_NLEVEL 6
#define MAX_NNMI 1
#define MAX_NCCOMPARE 3
#define MAX_TLB_WAY_SIZE 8
#define MAX_NDBREAK 2

#define REGION_PAGE_MASK 0xe0000000

#define PAGE_CACHE_MASK    0x700
#define PAGE_CACHE_SHIFT   8
#define PAGE_CACHE_INVALID 0x000
#define PAGE_CACHE_BYPASS  0x100
#define PAGE_CACHE_WT      0x200
#define PAGE_CACHE_WB      0x400
#define PAGE_CACHE_ISOLATE 0x600

enum {
    /* Static vectors */
    EXC_RESET,
    EXC_MEMORY_ERROR,

    /* Dynamic vectors */
    EXC_WINDOW_OVERFLOW4,
    EXC_WINDOW_UNDERFLOW4,
    EXC_WINDOW_OVERFLOW8,
    EXC_WINDOW_UNDERFLOW8,
    EXC_WINDOW_OVERFLOW12,
    EXC_WINDOW_UNDERFLOW12,
    EXC_IRQ,
    EXC_KERNEL,
    EXC_USER,
    EXC_DOUBLE,
    EXC_DEBUG,
    EXC_MAX
};

enum {
    ILLEGAL_INSTRUCTION_CAUSE = 0,
    SYSCALL_CAUSE,
    INSTRUCTION_FETCH_ERROR_CAUSE,
    LOAD_STORE_ERROR_CAUSE,
    LEVEL1_INTERRUPT_CAUSE,
    ALLOCA_CAUSE,
    INTEGER_DIVIDE_BY_ZERO_CAUSE,
    PRIVILEGED_CAUSE = 8,
    LOAD_STORE_ALIGNMENT_CAUSE,

    INSTR_PIF_DATA_ERROR_CAUSE = 12,
    LOAD_STORE_PIF_DATA_ERROR_CAUSE,
    INSTR_PIF_ADDR_ERROR_CAUSE,
    LOAD_STORE_PIF_ADDR_ERROR_CAUSE,

    INST_TLB_MISS_CAUSE,
    INST_TLB_MULTI_HIT_CAUSE,
    INST_FETCH_PRIVILEGE_CAUSE,
    INST_FETCH_PROHIBITED_CAUSE = 20,
    LOAD_STORE_TLB_MISS_CAUSE = 24,
    LOAD_STORE_TLB_MULTI_HIT_CAUSE,
    LOAD_STORE_PRIVILEGE_CAUSE,
    LOAD_PROHIBITED_CAUSE = 28,
    STORE_PROHIBITED_CAUSE,

    COPROCESSOR0_DISABLED = 32,
};

typedef enum {
    INTTYPE_LEVEL,
    INTTYPE_EDGE,
    INTTYPE_NMI,
    INTTYPE_SOFTWARE,
    INTTYPE_TIMER,
    INTTYPE_DEBUG,
    INTTYPE_WRITE_ERR,
    INTTYPE_MAX
} interrupt_type;

typedef struct xtensa_tlb_entry {
    uint32_t vaddr;
    uint32_t paddr;
    uint8_t asid;
    uint8_t attr;
    bool variable;
} xtensa_tlb_entry;

typedef struct xtensa_tlb {
    unsigned nways;
    const unsigned way_size[10];
    bool varway56;
    unsigned nrefillentries;
} xtensa_tlb;

typedef struct XtensaGdbReg {
    int targno;
    int type;
    int group;
} XtensaGdbReg;

typedef struct XtensaGdbRegmap {
    int num_regs;
    int num_core_regs;
    /* PC + a + ar + sr + ur */
    XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
} XtensaGdbRegmap;

typedef struct XtensaConfig {
    const char *name;
    uint64_t options;
    XtensaGdbRegmap gdb_regmap;
    unsigned nareg;
    int excm_level;
    int ndepc;
    uint32_t vecbase;
    uint32_t exception_vector[EXC_MAX];
    unsigned ninterrupt;
    unsigned nlevel;
    uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
    uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
    uint32_t inttype_mask[INTTYPE_MAX];
    struct {
        uint32_t level;
        interrupt_type inttype;
    } interrupt[MAX_NINTERRUPT];
    unsigned nccompare;
    uint32_t timerint[MAX_NCCOMPARE];
    unsigned nextint;
    unsigned extint[MAX_NINTERRUPT];

    unsigned debug_level;
    unsigned nibreak;
    unsigned ndbreak;

    uint32_t clock_freq_khz;

    xtensa_tlb itlb;
    xtensa_tlb dtlb;
} XtensaConfig;

typedef struct XtensaConfigList {
    const XtensaConfig *config;
    struct XtensaConfigList *next;
} XtensaConfigList;

typedef struct CPUXtensaState {
    const XtensaConfig *config;
    uint32_t regs[16];
    uint32_t pc;
    uint32_t sregs[256];
    uint32_t uregs[256];
    uint32_t phys_regs[MAX_NAREG];
    float32 fregs[16];
    float_status fp_status;

    xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
    xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
    unsigned autorefill_idx;

    int pending_irq_level; /* level of last raised IRQ */
    void **irq_inputs;
    QEMUTimer *ccompare_timer;
    uint32_t wake_ccount;
    int64_t halt_clock;

    int exception_taken;

    /* Watchpoints for DBREAK registers */
    CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];

    CPU_COMMON
} CPUXtensaState;

#include "cpu-qom.h"

#define cpu_exec cpu_xtensa_exec
#define cpu_gen_code cpu_xtensa_gen_code
#define cpu_signal_handler cpu_xtensa_signal_handler
#define cpu_list xtensa_cpu_list

#ifdef TARGET_WORDS_BIGENDIAN
#define XTENSA_DEFAULT_CPU_MODEL "fsf"
#else
#define XTENSA_DEFAULT_CPU_MODEL "dc232b"
#endif

XtensaCPU *cpu_xtensa_init(const char *cpu_model);

static inline CPUXtensaState *cpu_init(const char *cpu_model)
{
    XtensaCPU *cpu = cpu_xtensa_init(cpu_model);
    if (cpu == NULL) {
        return NULL;
    }
    return &cpu->env;
}

void xtensa_translate_init(void);
int cpu_xtensa_exec(CPUXtensaState *s);
void xtensa_register_core(XtensaConfigList *node);
void do_interrupt(CPUXtensaState *s);
void check_interrupts(CPUXtensaState *s);
void xtensa_irq_init(CPUXtensaState *env);
void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);
void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d);
void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
void xtensa_rearm_ccompare_timer(CPUXtensaState *env);
int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
void xtensa_sync_window_from_phys(CPUXtensaState *env);
void xtensa_sync_phys_from_window(CPUXtensaState *env);
uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
        uint32_t *vpn, uint32_t wi, uint32_t *ei);
int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
        uint32_t *pwi, uint32_t *pei, uint8_t *pring);
void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
        xtensa_tlb_entry *entry, bool dtlb,
        unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
        unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
        uint32_t vaddr, int is_write, int mmu_idx,
        uint32_t *paddr, uint32_t *page_size, unsigned *access);
void reset_mmu(CPUXtensaState *env);
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);


#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))

static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
        uint64_t opt)
{
    return (config->options & opt) != 0;
}

static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
{
    return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
}

static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
{
    int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
    if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
        level = env->config->excm_level;
    }
    return level;
}

static inline int xtensa_get_ring(const CPUXtensaState *env)
{
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
        return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
    } else {
        return 0;
    }
}

static inline int xtensa_get_cring(const CPUXtensaState *env)
{
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
            (env->sregs[PS] & PS_EXCM) == 0) {
        return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
    } else {
        return 0;
    }
}

static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
        bool dtlb, unsigned wi, unsigned ei)
{
    return dtlb ?
        env->dtlb[wi] + ei :
        env->itlb[wi] + ei;
}

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _ring0
#define MMU_MODE1_SUFFIX _ring1
#define MMU_MODE2_SUFFIX _ring2
#define MMU_MODE3_SUFFIX _ring3

static inline int cpu_mmu_index(CPUXtensaState *env)
{
    return xtensa_get_cring(env);
}

#define XTENSA_TBFLAG_RING_MASK 0x3
#define XTENSA_TBFLAG_EXCM 0x4
#define XTENSA_TBFLAG_LITBASE 0x8
#define XTENSA_TBFLAG_DEBUG 0x10
#define XTENSA_TBFLAG_ICOUNT 0x20
#define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
#define XTENSA_TBFLAG_CPENABLE_SHIFT 6

static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
        target_ulong *cs_base, int *flags)
{
    *pc = env->pc;
    *cs_base = 0;
    *flags = 0;
    *flags |= xtensa_get_ring(env);
    if (env->sregs[PS] & PS_EXCM) {
        *flags |= XTENSA_TBFLAG_EXCM;
    }
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
            (env->sregs[LITBASE] & 1)) {
        *flags |= XTENSA_TBFLAG_LITBASE;
    }
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
        if (xtensa_get_cintlevel(env) < env->config->debug_level) {
            *flags |= XTENSA_TBFLAG_DEBUG;
        }
        if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
            *flags |= XTENSA_TBFLAG_ICOUNT;
        }
    }
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
        *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
    }
}

#include "cpu-all.h"
#include "exec-all.h"

static inline int cpu_has_work(CPUState *cpu)
{
    CPUXtensaState *env = &XTENSA_CPU(cpu)->env;

    return env->pending_irq_level;
}

static inline void cpu_pc_from_tb(CPUXtensaState *env, TranslationBlock *tb)
{
    env->pc = tb->pc;
}

#endif
Commit	Line	Data
2328826b MF	1	/*
	2	* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
	3	* All rights reserved.
	4	*
	5	* Redistribution and use in source and binary forms, with or without
	6	* modification, are permitted provided that the following conditions are met:
	7	* * Redistributions of source code must retain the above copyright
	8	* notice, this list of conditions and the following disclaimer.
	9	* * Redistributions in binary form must reproduce the above copyright
	10	* notice, this list of conditions and the following disclaimer in the
	11	* documentation and/or other materials provided with the distribution.
	12	* * Neither the name of the Open Source and Linux Lab nor the
	13	* names of its contributors may be used to endorse or promote products
	14	* derived from this software without specific prior written permission.
	15	*
	16	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	17	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	18	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	19	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	20	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	21	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	22	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	23	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	24	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	25	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	26	*/
	27
	28	#ifndef CPU_XTENSA_H
	29	#define CPU_XTENSA_H
	30
	31	#define TARGET_LONG_BITS 32
	32	#define ELF_MACHINE EM_XTENSA
	33
9349b4f9	34	#define CPUArchState struct CPUXtensaState
2328826b MF	35
	36	#include "config.h"
	37	#include "qemu-common.h"
	38	#include "cpu-defs.h"
dd519cbe	39	#include "fpu/softfloat.h"
2328826b MF	40
	41	#define TARGET_HAS_ICE 1
	42
	43	#define NB_MMU_MODES 4
	44
	45	#define TARGET_PHYS_ADDR_SPACE_BITS 32
	46	#define TARGET_VIRT_ADDR_SPACE_BITS 32
	47	#define TARGET_PAGE_BITS 12
	48
dedc5eae MF	49	enum {
	50	/* Additional instructions */
	51	XTENSA_OPTION_CODE_DENSITY,
	52	XTENSA_OPTION_LOOP,
	53	XTENSA_OPTION_EXTENDED_L32R,
	54	XTENSA_OPTION_16_BIT_IMUL,
	55	XTENSA_OPTION_32_BIT_IMUL,
7f65f4b0	56	XTENSA_OPTION_32_BIT_IMUL_HIGH,
dedc5eae MF	57	XTENSA_OPTION_32_BIT_IDIV,
dedc5eae MF	58	XTENSA_OPTION_MAC16,
7f65f4b0 MF	59	XTENSA_OPTION_MISC_OP_NSA,
	60	XTENSA_OPTION_MISC_OP_MINMAX,
	61	XTENSA_OPTION_MISC_OP_SEXT,
	62	XTENSA_OPTION_MISC_OP_CLAMPS,
dedc5eae MF	63	XTENSA_OPTION_COPROCESSOR,
	64	XTENSA_OPTION_BOOLEAN,
	65	XTENSA_OPTION_FP_COPROCESSOR,
	66	XTENSA_OPTION_MP_SYNCHRO,
	67	XTENSA_OPTION_CONDITIONAL_STORE,
fcc803d1	68	XTENSA_OPTION_ATOMCTL,
dedc5eae MF	69
	70	/* Interrupts and exceptions */
	71	XTENSA_OPTION_EXCEPTION,
	72	XTENSA_OPTION_RELOCATABLE_VECTOR,
	73	XTENSA_OPTION_UNALIGNED_EXCEPTION,
	74	XTENSA_OPTION_INTERRUPT,
	75	XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
	76	XTENSA_OPTION_TIMER_INTERRUPT,
	77
	78	/* Local memory */
	79	XTENSA_OPTION_ICACHE,
	80	XTENSA_OPTION_ICACHE_TEST,
	81	XTENSA_OPTION_ICACHE_INDEX_LOCK,
	82	XTENSA_OPTION_DCACHE,
	83	XTENSA_OPTION_DCACHE_TEST,
	84	XTENSA_OPTION_DCACHE_INDEX_LOCK,
	85	XTENSA_OPTION_IRAM,
	86	XTENSA_OPTION_IROM,
	87	XTENSA_OPTION_DRAM,
	88	XTENSA_OPTION_DROM,
	89	XTENSA_OPTION_XLMI,
	90	XTENSA_OPTION_HW_ALIGNMENT,
	91	XTENSA_OPTION_MEMORY_ECC_PARITY,
	92
	93	/* Memory protection and translation */
	94	XTENSA_OPTION_REGION_PROTECTION,
	95	XTENSA_OPTION_REGION_TRANSLATION,
	96	XTENSA_OPTION_MMU,
	97
	98	/* Other */
	99	XTENSA_OPTION_WINDOWED_REGISTER,
	100	XTENSA_OPTION_PROCESSOR_INTERFACE,
	101	XTENSA_OPTION_MISC_SR,
	102	XTENSA_OPTION_THREAD_POINTER,
	103	XTENSA_OPTION_PROCESSOR_ID,
	104	XTENSA_OPTION_DEBUG,
	105	XTENSA_OPTION_TRACE_PORT,
	106	};
	107
2af3da91 MF	108	enum {
	109	THREADPTR = 231,
	110	FCR = 232,
	111	FSR = 233,
	112	};
	113
3580ecad	114	enum {
797d780b MF	115	LBEG = 0,
	116	LEND = 1,
	117	LCOUNT = 2,
3580ecad	118	SAR = 3,
4dd85b6b	119	BR = 4,
6ad6dbf7	120	LITBASE = 5,
809377aa	121	SCOMPARE1 = 12,
6825b6c3 MF	122	ACCLO = 16,
	123	ACCHI = 17,
	124	MR = 32,
553e44f9 MF	125	WINDOW_BASE = 72,
553e44f9 MF	126	WINDOW_START = 73,
b67ea0cd MF	127	PTEVADDR = 83,
	128	RASID = 90,
	129	ITLBCFG = 91,
	130	DTLBCFG = 92,
e61dc8f7	131	IBREAKENABLE = 96,
fcc803d1	132	ATOMCTL = 99,
e61dc8f7	133	IBREAKA = 128,
f14c4b5f MF	134	DBREAKA = 144,
f14c4b5f MF	135	DBREAKC = 160,
40643d7c MF	136	EPC1 = 177,
40643d7c MF	137	DEPC = 192,
b994e91b	138	EPS2 = 194,
40643d7c	139	EXCSAVE1 = 209,
f3df4c04	140	CPENABLE = 224,
b994e91b MF	141	INTSET = 226,
	142	INTCLEAR = 227,
	143	INTENABLE = 228,
f0a548b9	144	PS = 230,
97836cee	145	VECBASE = 231,
40643d7c	146	EXCCAUSE = 232,
ab58c5b4	147	DEBUGCAUSE = 233,
b994e91b	148	CCOUNT = 234,
f3df4c04	149	PRID = 235,
35b5c044 MF	150	ICOUNT = 236,
35b5c044 MF	151	ICOUNTLEVEL = 237,
40643d7c	152	EXCVADDR = 238,
b994e91b	153	CCOMPARE = 240,
3580ecad MF	154	};
3580ecad MF	155
f0a548b9 MF	156	#define PS_INTLEVEL 0xf
	157	#define PS_INTLEVEL_SHIFT 0
	158
	159	#define PS_EXCM 0x10
	160	#define PS_UM 0x20
	161
	162	#define PS_RING 0xc0
	163	#define PS_RING_SHIFT 6
	164
	165	#define PS_OWB 0xf00
	166	#define PS_OWB_SHIFT 8
	167
	168	#define PS_CALLINC 0x30000
	169	#define PS_CALLINC_SHIFT 16
	170	#define PS_CALLINC_LEN 2
	171
	172	#define PS_WOE 0x40000
	173
ab58c5b4 MF	174	#define DEBUGCAUSE_IC 0x1
	175	#define DEBUGCAUSE_IB 0x2
	176	#define DEBUGCAUSE_DB 0x4
	177	#define DEBUGCAUSE_BI 0x8
	178	#define DEBUGCAUSE_BN 0x10
	179	#define DEBUGCAUSE_DI 0x20
	180	#define DEBUGCAUSE_DBNUM 0xf00
	181	#define DEBUGCAUSE_DBNUM_SHIFT 8
	182
f14c4b5f MF	183	#define DBREAKC_SB 0x80000000
	184	#define DBREAKC_LB 0x40000000
	185	#define DBREAKC_SB_LB (DBREAKC_SB \| DBREAKC_LB)
	186	#define DBREAKC_MASK 0x3f
	187
553e44f9	188	#define MAX_NAREG 64
b994e91b MF	189	#define MAX_NINTERRUPT 32
	190	#define MAX_NLEVEL 6
	191	#define MAX_NNMI 1
	192	#define MAX_NCCOMPARE 3
b67ea0cd	193	#define MAX_TLB_WAY_SIZE 8
f14c4b5f	194	#define MAX_NDBREAK 2
b67ea0cd MF	195
b67ea0cd MF	196	#define REGION_PAGE_MASK 0xe0000000
553e44f9	197
fcc803d1 MF	198	#define PAGE_CACHE_MASK 0x700
	199	#define PAGE_CACHE_SHIFT 8
	200	#define PAGE_CACHE_INVALID 0x000
	201	#define PAGE_CACHE_BYPASS 0x100
	202	#define PAGE_CACHE_WT 0x200
	203	#define PAGE_CACHE_WB 0x400
	204	#define PAGE_CACHE_ISOLATE 0x600
	205
40643d7c MF	206	enum {
	207	/* Static vectors */
	208	EXC_RESET,
	209	EXC_MEMORY_ERROR,
	210
	211	/* Dynamic vectors */
	212	EXC_WINDOW_OVERFLOW4,
	213	EXC_WINDOW_UNDERFLOW4,
	214	EXC_WINDOW_OVERFLOW8,
	215	EXC_WINDOW_UNDERFLOW8,
	216	EXC_WINDOW_OVERFLOW12,
	217	EXC_WINDOW_UNDERFLOW12,
	218	EXC_IRQ,
	219	EXC_KERNEL,
	220	EXC_USER,
	221	EXC_DOUBLE,
e61dc8f7	222	EXC_DEBUG,
40643d7c MF	223	EXC_MAX
	224	};
	225
	226	enum {
	227	ILLEGAL_INSTRUCTION_CAUSE = 0,
	228	SYSCALL_CAUSE,
	229	INSTRUCTION_FETCH_ERROR_CAUSE,
	230	LOAD_STORE_ERROR_CAUSE,
	231	LEVEL1_INTERRUPT_CAUSE,
	232	ALLOCA_CAUSE,
	233	INTEGER_DIVIDE_BY_ZERO_CAUSE,
	234	PRIVILEGED_CAUSE = 8,
	235	LOAD_STORE_ALIGNMENT_CAUSE,
	236
	237	INSTR_PIF_DATA_ERROR_CAUSE = 12,
	238	LOAD_STORE_PIF_DATA_ERROR_CAUSE,
	239	INSTR_PIF_ADDR_ERROR_CAUSE,
	240	LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
	241
	242	INST_TLB_MISS_CAUSE,
	243	INST_TLB_MULTI_HIT_CAUSE,
	244	INST_FETCH_PRIVILEGE_CAUSE,
	245	INST_FETCH_PROHIBITED_CAUSE = 20,
	246	LOAD_STORE_TLB_MISS_CAUSE = 24,
	247	LOAD_STORE_TLB_MULTI_HIT_CAUSE,
	248	LOAD_STORE_PRIVILEGE_CAUSE,
	249	LOAD_PROHIBITED_CAUSE = 28,
	250	STORE_PROHIBITED_CAUSE,
	251
	252	COPROCESSOR0_DISABLED = 32,
	253	};
	254
b994e91b MF	255	typedef enum {
	256	INTTYPE_LEVEL,
	257	INTTYPE_EDGE,
	258	INTTYPE_NMI,
	259	INTTYPE_SOFTWARE,
	260	INTTYPE_TIMER,
	261	INTTYPE_DEBUG,
	262	INTTYPE_WRITE_ERR,
	263	INTTYPE_MAX
	264	} interrupt_type;
	265
b67ea0cd MF	266	typedef struct xtensa_tlb_entry {
	267	uint32_t vaddr;
	268	uint32_t paddr;
	269	uint8_t asid;
	270	uint8_t attr;
	271	bool variable;
	272	} xtensa_tlb_entry;
	273
	274	typedef struct xtensa_tlb {
	275	unsigned nways;
	276	const unsigned way_size[10];
	277	bool varway56;
	278	unsigned nrefillentries;
	279	} xtensa_tlb;
	280
ccfcaba6 MF	281	typedef struct XtensaGdbReg {
	282	int targno;
	283	int type;
	284	int group;
	285	} XtensaGdbReg;
	286
	287	typedef struct XtensaGdbRegmap {
	288	int num_regs;
	289	int num_core_regs;
	290	/* PC + a + ar + sr + ur */
	291	XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
	292	} XtensaGdbRegmap;
	293
dedc5eae MF	294	typedef struct XtensaConfig {
	295	const char *name;
	296	uint64_t options;
ccfcaba6	297	XtensaGdbRegmap gdb_regmap;
553e44f9	298	unsigned nareg;
40643d7c MF	299	int excm_level;
40643d7c MF	300	int ndepc;
97836cee	301	uint32_t vecbase;
40643d7c	302	uint32_t exception_vector[EXC_MAX];
b994e91b MF	303	unsigned ninterrupt;
	304	unsigned nlevel;
	305	uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
	306	uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
	307	uint32_t inttype_mask[INTTYPE_MAX];
	308	struct {
	309	uint32_t level;
	310	interrupt_type inttype;
	311	} interrupt[MAX_NINTERRUPT];
	312	unsigned nccompare;
	313	uint32_t timerint[MAX_NCCOMPARE];
b8929a54 MF	314	unsigned nextint;
b8929a54 MF	315	unsigned extint[MAX_NINTERRUPT];
ab58c5b4 MF	316
	317	unsigned debug_level;
	318	unsigned nibreak;
	319	unsigned ndbreak;
	320
b994e91b	321	uint32_t clock_freq_khz;
b67ea0cd MF	322
	323	xtensa_tlb itlb;
	324	xtensa_tlb dtlb;
dedc5eae MF	325	} XtensaConfig;
dedc5eae MF	326
ac8b7db4 MF	327	typedef struct XtensaConfigList {
	328	const XtensaConfig *config;
	329	struct XtensaConfigList *next;
	330	} XtensaConfigList;
	331
2328826b	332	typedef struct CPUXtensaState {
dedc5eae	333	const XtensaConfig *config;
2328826b MF	334	uint32_t regs[16];
	335	uint32_t pc;
	336	uint32_t sregs[256];
2af3da91	337	uint32_t uregs[256];
553e44f9	338	uint32_t phys_regs[MAX_NAREG];
dd519cbe MF	339	float32 fregs[16];
dd519cbe MF	340	float_status fp_status;
2328826b	341
b67ea0cd MF	342	xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
	343	xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
	344	unsigned autorefill_idx;
	345
b994e91b MF	346	int pending_irq_level; /* level of last raised IRQ */
	347	void **irq_inputs;
	348	QEMUTimer *ccompare_timer;
	349	uint32_t wake_ccount;
	350	int64_t halt_clock;
	351
40643d7c MF	352	int exception_taken;
40643d7c MF	353
f14c4b5f MF	354	/* Watchpoints for DBREAK registers */
	355	CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
	356
2328826b MF	357	CPU_COMMON
	358	} CPUXtensaState;
	359
15be3171 AF	360	#include "cpu-qom.h"
15be3171 AF	361
2328826b MF	362	#define cpu_exec cpu_xtensa_exec
	363	#define cpu_gen_code cpu_xtensa_gen_code
	364	#define cpu_signal_handler cpu_xtensa_signal_handler
	365	#define cpu_list xtensa_cpu_list
	366
e38077ff MF	367	#ifdef TARGET_WORDS_BIGENDIAN
	368	#define XTENSA_DEFAULT_CPU_MODEL "fsf"
	369	#else
	370	#define XTENSA_DEFAULT_CPU_MODEL "dc232b"
	371	#endif
	372
15be3171 AF	373	XtensaCPU cpu_xtensa_init(const char cpu_model);
	374
	375	static inline CPUXtensaState cpu_init(const char cpu_model)
	376	{
	377	XtensaCPU *cpu = cpu_xtensa_init(cpu_model);
	378	if (cpu == NULL) {
	379	return NULL;
	380	}
	381	return &cpu->env;
	382	}
	383
2328826b MF	384	void xtensa_translate_init(void);
2328826b MF	385	int cpu_xtensa_exec(CPUXtensaState *s);
ac8b7db4	386	void xtensa_register_core(XtensaConfigList *node);
2328826b	387	void do_interrupt(CPUXtensaState *s);
b994e91b	388	void check_interrupts(CPUXtensaState *s);
97129ac8 AF	389	void xtensa_irq_init(CPUXtensaState *env);
	390	void xtensa_get_extint(CPUXtensaState env, unsigned extint);
	391	void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d);
	392	void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
	393	void xtensa_rearm_ccompare_timer(CPUXtensaState *env);
2328826b MF	394	int cpu_xtensa_signal_handler(int host_signum, void pinfo, void puc);
2328826b MF	395	void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
97129ac8 AF	396	void xtensa_sync_window_from_phys(CPUXtensaState *env);
	397	void xtensa_sync_phys_from_window(CPUXtensaState *env);
	398	uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
	399	void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
b67ea0cd	400	uint32_t vpn, uint32_t wi, uint32_t ei);
97129ac8	401	int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
b67ea0cd	402	uint32_t pwi, uint32_t pei, uint8_t *pring);
16bde77a MF	403	void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
	404	xtensa_tlb_entry *entry, bool dtlb,
	405	unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
97129ac8	406	void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
b67ea0cd	407	unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
ae4e7982	408	int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
b67ea0cd MF	409	uint32_t vaddr, int is_write, int mmu_idx,
b67ea0cd MF	410	uint32_t paddr, uint32_t page_size, unsigned *access);
5087a72c	411	void reset_mmu(CPUXtensaState *env);
97129ac8 AF	412	void dump_mmu(FILE f, fprintf_function cpu_fprintf, CPUXtensaState env);
97129ac8 AF	413	void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
b67ea0cd	414
2328826b	415
dedc5eae MF	416	#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
dedc5eae MF	417
b67ea0cd MF	418	static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
	419	uint64_t opt)
	420	{
	421	return (config->options & opt) != 0;
	422	}
	423
dedc5eae MF	424	static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
dedc5eae MF	425	{
b67ea0cd	426	return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
dedc5eae MF	427	}
dedc5eae MF	428
97129ac8	429	static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
40643d7c MF	430	{
	431	int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
	432	if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
	433	level = env->config->excm_level;
	434	}
	435	return level;
	436	}
	437
97129ac8	438	static inline int xtensa_get_ring(const CPUXtensaState *env)
f0a548b9 MF	439	{
	440	if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
	441	return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
	442	} else {
	443	return 0;
	444	}
	445	}
	446
97129ac8	447	static inline int xtensa_get_cring(const CPUXtensaState *env)
f0a548b9 MF	448	{
	449	if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
	450	(env->sregs[PS] & PS_EXCM) == 0) {
	451	return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
	452	} else {
	453	return 0;
	454	}
	455	}
	456
97129ac8	457	static inline xtensa_tlb_entry xtensa_tlb_get_entry(CPUXtensaState env,
b67ea0cd MF	458	bool dtlb, unsigned wi, unsigned ei)
	459	{
	460	return dtlb ?
	461	env->dtlb[wi] + ei :
	462	env->itlb[wi] + ei;
	463	}
	464
f0a548b9 MF	465	/* MMU modes definitions */
	466	#define MMU_MODE0_SUFFIX _ring0
	467	#define MMU_MODE1_SUFFIX _ring1
	468	#define MMU_MODE2_SUFFIX _ring2
	469	#define MMU_MODE3_SUFFIX _ring3
	470
97129ac8	471	static inline int cpu_mmu_index(CPUXtensaState *env)
2328826b	472	{
f0a548b9	473	return xtensa_get_cring(env);
2328826b MF	474	}
2328826b MF	475
f0a548b9 MF	476	#define XTENSA_TBFLAG_RING_MASK 0x3
f0a548b9 MF	477	#define XTENSA_TBFLAG_EXCM 0x4
6ad6dbf7	478	#define XTENSA_TBFLAG_LITBASE 0x8
e61dc8f7	479	#define XTENSA_TBFLAG_DEBUG 0x10
35b5c044	480	#define XTENSA_TBFLAG_ICOUNT 0x20
ef04a846 MF	481	#define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
ef04a846 MF	482	#define XTENSA_TBFLAG_CPENABLE_SHIFT 6
f0a548b9	483
97129ac8	484	static inline void cpu_get_tb_cpu_state(CPUXtensaState env, target_ulong pc,
2328826b MF	485	target_ulong cs_base, int flags)
	486	{
	487	*pc = env->pc;
	488	*cs_base = 0;
	489	*flags = 0;
f0a548b9 MF	490	*flags \|= xtensa_get_ring(env);
	491	if (env->sregs[PS] & PS_EXCM) {
	492	*flags \|= XTENSA_TBFLAG_EXCM;
	493	}
6ad6dbf7 MF	494	if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
	495	(env->sregs[LITBASE] & 1)) {
	496	*flags \|= XTENSA_TBFLAG_LITBASE;
	497	}
e61dc8f7 MF	498	if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
	499	if (xtensa_get_cintlevel(env) < env->config->debug_level) {
	500	*flags \|= XTENSA_TBFLAG_DEBUG;
	501	}
35b5c044 MF	502	if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
	503	*flags \|= XTENSA_TBFLAG_ICOUNT;
	504	}
e61dc8f7	505	}
ef04a846 MF	506	if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
	507	*flags \|= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
	508	}
2328826b MF	509	}
	510
	511	#include "cpu-all.h"
	512	#include "exec-all.h"
	513
3993c6bd	514	static inline int cpu_has_work(CPUState *cpu)
2328826b	515	{
3993c6bd AF	516	CPUXtensaState *env = &XTENSA_CPU(cpu)->env;
3993c6bd AF	517
b994e91b	518	return env->pending_irq_level;
2328826b MF	519	}
2328826b MF	520
97129ac8	521	static inline void cpu_pc_from_tb(CPUXtensaState env, TranslationBlock tb)
2328826b MF	522	{
	523	env->pc = tb->pc;
	524	}
	525
	526	#endif