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2328826b MF |
1 | /* |
2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * * Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * * Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * * Neither the name of the Open Source and Linux Lab nor the | |
13 | * names of its contributors may be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
28 | #include "cpu.h" | |
29 | #include "exec-all.h" | |
30 | #include "gdbstub.h" | |
2328826b MF |
31 | #include "host-utils.h" |
32 | #if !defined(CONFIG_USER_ONLY) | |
33 | #include "hw/loader.h" | |
34 | #endif | |
35 | ||
97129ac8 | 36 | static void reset_mmu(CPUXtensaState *env); |
b67ea0cd | 37 | |
1bba0dc9 | 38 | void cpu_state_reset(CPUXtensaState *env) |
2328826b | 39 | { |
40643d7c MF |
40 | env->exception_taken = 0; |
41 | env->pc = env->config->exception_vector[EXC_RESET]; | |
6ad6dbf7 | 42 | env->sregs[LITBASE] &= ~1; |
b994e91b MF |
43 | env->sregs[PS] = xtensa_option_enabled(env->config, |
44 | XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; | |
97836cee | 45 | env->sregs[VECBASE] = env->config->vecbase; |
e61dc8f7 | 46 | env->sregs[IBREAKENABLE] = 0; |
b994e91b MF |
47 | |
48 | env->pending_irq_level = 0; | |
b67ea0cd | 49 | reset_mmu(env); |
2328826b MF |
50 | } |
51 | ||
ac8b7db4 MF |
52 | static struct XtensaConfigList *xtensa_cores; |
53 | ||
54 | void xtensa_register_core(XtensaConfigList *node) | |
55 | { | |
56 | node->next = xtensa_cores; | |
57 | xtensa_cores = node; | |
58 | } | |
dedc5eae | 59 | |
97129ac8 | 60 | static uint32_t check_hw_breakpoints(CPUXtensaState *env) |
f14c4b5f MF |
61 | { |
62 | unsigned i; | |
63 | ||
64 | for (i = 0; i < env->config->ndbreak; ++i) { | |
65 | if (env->cpu_watchpoint[i] && | |
66 | env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) { | |
67 | return DEBUGCAUSE_DB | (i << DEBUGCAUSE_DBNUM_SHIFT); | |
68 | } | |
69 | } | |
70 | return 0; | |
71 | } | |
72 | ||
73 | static CPUDebugExcpHandler *prev_debug_excp_handler; | |
74 | ||
97129ac8 | 75 | static void breakpoint_handler(CPUXtensaState *env) |
f14c4b5f MF |
76 | { |
77 | if (env->watchpoint_hit) { | |
78 | if (env->watchpoint_hit->flags & BP_CPU) { | |
79 | uint32_t cause; | |
80 | ||
81 | env->watchpoint_hit = NULL; | |
82 | cause = check_hw_breakpoints(env); | |
83 | if (cause) { | |
84 | debug_exception_env(env, cause); | |
85 | } | |
86 | cpu_resume_from_signal(env, NULL); | |
87 | } | |
88 | } | |
89 | if (prev_debug_excp_handler) { | |
90 | prev_debug_excp_handler(env); | |
91 | } | |
92 | } | |
93 | ||
2328826b MF |
94 | CPUXtensaState *cpu_xtensa_init(const char *cpu_model) |
95 | { | |
96 | static int tcg_inited; | |
f14c4b5f | 97 | static int debug_handler_inited; |
a4633e16 | 98 | XtensaCPU *cpu; |
2328826b | 99 | CPUXtensaState *env; |
dedc5eae | 100 | const XtensaConfig *config = NULL; |
ac8b7db4 | 101 | XtensaConfigList *core = xtensa_cores; |
dedc5eae | 102 | |
ac8b7db4 MF |
103 | for (; core; core = core->next) |
104 | if (strcmp(core->config->name, cpu_model) == 0) { | |
105 | config = core->config; | |
dedc5eae MF |
106 | break; |
107 | } | |
108 | ||
109 | if (config == NULL) { | |
110 | return NULL; | |
111 | } | |
2328826b | 112 | |
a4633e16 AF |
113 | cpu = XTENSA_CPU(object_new(TYPE_XTENSA_CPU)); |
114 | env = &cpu->env; | |
dedc5eae | 115 | env->config = config; |
2328826b MF |
116 | cpu_exec_init(env); |
117 | ||
118 | if (!tcg_inited) { | |
119 | tcg_inited = 1; | |
120 | xtensa_translate_init(); | |
121 | } | |
122 | ||
f14c4b5f MF |
123 | if (!debug_handler_inited && tcg_enabled()) { |
124 | debug_handler_inited = 1; | |
125 | prev_debug_excp_handler = | |
126 | cpu_set_debug_excp_handler(breakpoint_handler); | |
127 | } | |
128 | ||
b994e91b | 129 | xtensa_irq_init(env); |
2328826b MF |
130 | qemu_init_vcpu(env); |
131 | return env; | |
132 | } | |
133 | ||
134 | ||
135 | void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
136 | { | |
ac8b7db4 | 137 | XtensaConfigList *core = xtensa_cores; |
dedc5eae | 138 | cpu_fprintf(f, "Available CPUs:\n"); |
ac8b7db4 MF |
139 | for (; core; core = core->next) { |
140 | cpu_fprintf(f, " %s\n", core->config->name); | |
dedc5eae | 141 | } |
2328826b MF |
142 | } |
143 | ||
97129ac8 | 144 | target_phys_addr_t cpu_get_phys_page_debug(CPUXtensaState *env, target_ulong addr) |
2328826b | 145 | { |
b67ea0cd MF |
146 | uint32_t paddr; |
147 | uint32_t page_size; | |
148 | unsigned access; | |
149 | ||
150 | if (xtensa_get_physical_addr(env, addr, 0, 0, | |
151 | &paddr, &page_size, &access) == 0) { | |
152 | return paddr; | |
153 | } | |
154 | if (xtensa_get_physical_addr(env, addr, 2, 0, | |
155 | &paddr, &page_size, &access) == 0) { | |
156 | return paddr; | |
157 | } | |
158 | return ~0; | |
2328826b MF |
159 | } |
160 | ||
97129ac8 | 161 | static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector) |
97836cee MF |
162 | { |
163 | if (xtensa_option_enabled(env->config, | |
164 | XTENSA_OPTION_RELOCATABLE_VECTOR)) { | |
165 | return vector - env->config->vecbase + env->sregs[VECBASE]; | |
166 | } else { | |
167 | return vector; | |
168 | } | |
169 | } | |
170 | ||
b994e91b MF |
171 | /*! |
172 | * Handle penging IRQ. | |
173 | * For the high priority interrupt jump to the corresponding interrupt vector. | |
174 | * For the level-1 interrupt convert it to either user, kernel or double | |
175 | * exception with the 'level-1 interrupt' exception cause. | |
176 | */ | |
97129ac8 | 177 | static void handle_interrupt(CPUXtensaState *env) |
b994e91b MF |
178 | { |
179 | int level = env->pending_irq_level; | |
180 | ||
181 | if (level > xtensa_get_cintlevel(env) && | |
182 | level <= env->config->nlevel && | |
183 | (env->config->level_mask[level] & | |
184 | env->sregs[INTSET] & | |
185 | env->sregs[INTENABLE])) { | |
186 | if (level > 1) { | |
187 | env->sregs[EPC1 + level - 1] = env->pc; | |
188 | env->sregs[EPS2 + level - 2] = env->sregs[PS]; | |
189 | env->sregs[PS] = | |
190 | (env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM; | |
97836cee MF |
191 | env->pc = relocated_vector(env, |
192 | env->config->interrupt_vector[level]); | |
b994e91b MF |
193 | } else { |
194 | env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE; | |
195 | ||
196 | if (env->sregs[PS] & PS_EXCM) { | |
197 | if (env->config->ndepc) { | |
198 | env->sregs[DEPC] = env->pc; | |
199 | } else { | |
200 | env->sregs[EPC1] = env->pc; | |
201 | } | |
202 | env->exception_index = EXC_DOUBLE; | |
203 | } else { | |
204 | env->sregs[EPC1] = env->pc; | |
205 | env->exception_index = | |
206 | (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL; | |
207 | } | |
208 | env->sregs[PS] |= PS_EXCM; | |
209 | } | |
210 | env->exception_taken = 1; | |
211 | } | |
212 | } | |
213 | ||
97129ac8 | 214 | void do_interrupt(CPUXtensaState *env) |
2328826b | 215 | { |
b994e91b MF |
216 | if (env->exception_index == EXC_IRQ) { |
217 | qemu_log_mask(CPU_LOG_INT, | |
218 | "%s(EXC_IRQ) level = %d, cintlevel = %d, " | |
219 | "pc = %08x, a0 = %08x, ps = %08x, " | |
220 | "intset = %08x, intenable = %08x, " | |
221 | "ccount = %08x\n", | |
222 | __func__, env->pending_irq_level, xtensa_get_cintlevel(env), | |
223 | env->pc, env->regs[0], env->sregs[PS], | |
224 | env->sregs[INTSET], env->sregs[INTENABLE], | |
225 | env->sregs[CCOUNT]); | |
226 | handle_interrupt(env); | |
227 | } | |
228 | ||
40643d7c MF |
229 | switch (env->exception_index) { |
230 | case EXC_WINDOW_OVERFLOW4: | |
231 | case EXC_WINDOW_UNDERFLOW4: | |
232 | case EXC_WINDOW_OVERFLOW8: | |
233 | case EXC_WINDOW_UNDERFLOW8: | |
234 | case EXC_WINDOW_OVERFLOW12: | |
235 | case EXC_WINDOW_UNDERFLOW12: | |
236 | case EXC_KERNEL: | |
237 | case EXC_USER: | |
238 | case EXC_DOUBLE: | |
e61dc8f7 | 239 | case EXC_DEBUG: |
b994e91b MF |
240 | qemu_log_mask(CPU_LOG_INT, "%s(%d) " |
241 | "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n", | |
242 | __func__, env->exception_index, | |
243 | env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]); | |
40643d7c | 244 | if (env->config->exception_vector[env->exception_index]) { |
97836cee MF |
245 | env->pc = relocated_vector(env, |
246 | env->config->exception_vector[env->exception_index]); | |
40643d7c MF |
247 | env->exception_taken = 1; |
248 | } else { | |
249 | qemu_log("%s(pc = %08x) bad exception_index: %d\n", | |
250 | __func__, env->pc, env->exception_index); | |
251 | } | |
252 | break; | |
253 | ||
b994e91b MF |
254 | case EXC_IRQ: |
255 | break; | |
256 | ||
257 | default: | |
258 | qemu_log("%s(pc = %08x) unknown exception_index: %d\n", | |
259 | __func__, env->pc, env->exception_index); | |
260 | break; | |
40643d7c | 261 | } |
b994e91b | 262 | check_interrupts(env); |
2328826b | 263 | } |
b67ea0cd | 264 | |
97129ac8 | 265 | static void reset_tlb_mmu_all_ways(CPUXtensaState *env, |
b67ea0cd MF |
266 | const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) |
267 | { | |
268 | unsigned wi, ei; | |
269 | ||
270 | for (wi = 0; wi < tlb->nways; ++wi) { | |
271 | for (ei = 0; ei < tlb->way_size[wi]; ++ei) { | |
272 | entry[wi][ei].asid = 0; | |
273 | entry[wi][ei].variable = true; | |
274 | } | |
275 | } | |
276 | } | |
277 | ||
97129ac8 | 278 | static void reset_tlb_mmu_ways56(CPUXtensaState *env, |
b67ea0cd MF |
279 | const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) |
280 | { | |
281 | if (!tlb->varway56) { | |
282 | static const xtensa_tlb_entry way5[] = { | |
283 | { | |
284 | .vaddr = 0xd0000000, | |
285 | .paddr = 0, | |
286 | .asid = 1, | |
287 | .attr = 7, | |
288 | .variable = false, | |
289 | }, { | |
290 | .vaddr = 0xd8000000, | |
291 | .paddr = 0, | |
292 | .asid = 1, | |
293 | .attr = 3, | |
294 | .variable = false, | |
295 | } | |
296 | }; | |
297 | static const xtensa_tlb_entry way6[] = { | |
298 | { | |
299 | .vaddr = 0xe0000000, | |
300 | .paddr = 0xf0000000, | |
301 | .asid = 1, | |
302 | .attr = 7, | |
303 | .variable = false, | |
304 | }, { | |
305 | .vaddr = 0xf0000000, | |
306 | .paddr = 0xf0000000, | |
307 | .asid = 1, | |
308 | .attr = 3, | |
309 | .variable = false, | |
310 | } | |
311 | }; | |
312 | memcpy(entry[5], way5, sizeof(way5)); | |
313 | memcpy(entry[6], way6, sizeof(way6)); | |
314 | } else { | |
315 | uint32_t ei; | |
316 | for (ei = 0; ei < 8; ++ei) { | |
317 | entry[6][ei].vaddr = ei << 29; | |
318 | entry[6][ei].paddr = ei << 29; | |
319 | entry[6][ei].asid = 1; | |
0fdd2e1d | 320 | entry[6][ei].attr = 3; |
b67ea0cd MF |
321 | } |
322 | } | |
323 | } | |
324 | ||
97129ac8 | 325 | static void reset_tlb_region_way0(CPUXtensaState *env, |
b67ea0cd MF |
326 | xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) |
327 | { | |
328 | unsigned ei; | |
329 | ||
330 | for (ei = 0; ei < 8; ++ei) { | |
331 | entry[0][ei].vaddr = ei << 29; | |
332 | entry[0][ei].paddr = ei << 29; | |
333 | entry[0][ei].asid = 1; | |
334 | entry[0][ei].attr = 2; | |
335 | entry[0][ei].variable = true; | |
336 | } | |
337 | } | |
338 | ||
97129ac8 | 339 | static void reset_mmu(CPUXtensaState *env) |
b67ea0cd MF |
340 | { |
341 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
342 | env->sregs[RASID] = 0x04030201; | |
343 | env->sregs[ITLBCFG] = 0; | |
344 | env->sregs[DTLBCFG] = 0; | |
345 | env->autorefill_idx = 0; | |
346 | reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb); | |
347 | reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb); | |
348 | reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb); | |
349 | reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb); | |
350 | } else { | |
351 | reset_tlb_region_way0(env, env->itlb); | |
352 | reset_tlb_region_way0(env, env->dtlb); | |
353 | } | |
354 | } | |
355 | ||
97129ac8 | 356 | static unsigned get_ring(const CPUXtensaState *env, uint8_t asid) |
b67ea0cd MF |
357 | { |
358 | unsigned i; | |
359 | for (i = 0; i < 4; ++i) { | |
360 | if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) { | |
361 | return i; | |
362 | } | |
363 | } | |
364 | return 0xff; | |
365 | } | |
366 | ||
367 | /*! | |
368 | * Lookup xtensa TLB for the given virtual address. | |
369 | * See ISA, 4.6.2.2 | |
370 | * | |
371 | * \param pwi: [out] way index | |
372 | * \param pei: [out] entry index | |
373 | * \param pring: [out] access ring | |
374 | * \return 0 if ok, exception cause code otherwise | |
375 | */ | |
97129ac8 | 376 | int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb, |
b67ea0cd MF |
377 | uint32_t *pwi, uint32_t *pei, uint8_t *pring) |
378 | { | |
379 | const xtensa_tlb *tlb = dtlb ? | |
380 | &env->config->dtlb : &env->config->itlb; | |
381 | const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ? | |
382 | env->dtlb : env->itlb; | |
383 | ||
384 | int nhits = 0; | |
385 | unsigned wi; | |
386 | ||
387 | for (wi = 0; wi < tlb->nways; ++wi) { | |
388 | uint32_t vpn; | |
389 | uint32_t ei; | |
390 | split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei); | |
391 | if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) { | |
392 | unsigned ring = get_ring(env, entry[wi][ei].asid); | |
393 | if (ring < 4) { | |
394 | if (++nhits > 1) { | |
395 | return dtlb ? | |
396 | LOAD_STORE_TLB_MULTI_HIT_CAUSE : | |
397 | INST_TLB_MULTI_HIT_CAUSE; | |
398 | } | |
399 | *pwi = wi; | |
400 | *pei = ei; | |
401 | *pring = ring; | |
402 | } | |
403 | } | |
404 | } | |
405 | return nhits ? 0 : | |
406 | (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE); | |
407 | } | |
408 | ||
409 | /*! | |
410 | * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask. | |
411 | * See ISA, 4.6.5.10 | |
412 | */ | |
413 | static unsigned mmu_attr_to_access(uint32_t attr) | |
414 | { | |
415 | unsigned access = 0; | |
416 | if (attr < 12) { | |
417 | access |= PAGE_READ; | |
418 | if (attr & 0x1) { | |
419 | access |= PAGE_EXEC; | |
420 | } | |
421 | if (attr & 0x2) { | |
422 | access |= PAGE_WRITE; | |
423 | } | |
424 | } else if (attr == 13) { | |
425 | access |= PAGE_READ | PAGE_WRITE; | |
426 | } | |
427 | return access; | |
428 | } | |
429 | ||
430 | /*! | |
431 | * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask. | |
432 | * See ISA, 4.6.3.3 | |
433 | */ | |
434 | static unsigned region_attr_to_access(uint32_t attr) | |
435 | { | |
436 | unsigned access = 0; | |
437 | if ((attr < 6 && attr != 3) || attr == 14) { | |
438 | access |= PAGE_READ | PAGE_WRITE; | |
439 | } | |
440 | if (attr > 0 && attr < 6) { | |
441 | access |= PAGE_EXEC; | |
442 | } | |
443 | return access; | |
444 | } | |
445 | ||
446 | static bool is_access_granted(unsigned access, int is_write) | |
447 | { | |
448 | switch (is_write) { | |
449 | case 0: | |
450 | return access & PAGE_READ; | |
451 | ||
452 | case 1: | |
453 | return access & PAGE_WRITE; | |
454 | ||
455 | case 2: | |
456 | return access & PAGE_EXEC; | |
457 | ||
458 | default: | |
459 | return 0; | |
460 | } | |
461 | } | |
462 | ||
97129ac8 | 463 | static int autorefill_mmu(CPUXtensaState *env, uint32_t vaddr, bool dtlb, |
b67ea0cd MF |
464 | uint32_t *wi, uint32_t *ei, uint8_t *ring); |
465 | ||
97129ac8 | 466 | static int get_physical_addr_mmu(CPUXtensaState *env, |
b67ea0cd MF |
467 | uint32_t vaddr, int is_write, int mmu_idx, |
468 | uint32_t *paddr, uint32_t *page_size, unsigned *access) | |
469 | { | |
470 | bool dtlb = is_write != 2; | |
471 | uint32_t wi; | |
472 | uint32_t ei; | |
473 | uint8_t ring; | |
474 | int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring); | |
475 | ||
476 | if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) && | |
477 | (mmu_idx != 0 || ((vaddr ^ env->sregs[PTEVADDR]) & 0xffc00000)) && | |
478 | autorefill_mmu(env, vaddr, dtlb, &wi, &ei, &ring) == 0) { | |
479 | ret = 0; | |
480 | } | |
481 | if (ret != 0) { | |
482 | return ret; | |
483 | } | |
484 | ||
485 | const xtensa_tlb_entry *entry = | |
486 | xtensa_tlb_get_entry(env, dtlb, wi, ei); | |
487 | ||
488 | if (ring < mmu_idx) { | |
489 | return dtlb ? | |
490 | LOAD_STORE_PRIVILEGE_CAUSE : | |
491 | INST_FETCH_PRIVILEGE_CAUSE; | |
492 | } | |
493 | ||
494 | *access = mmu_attr_to_access(entry->attr); | |
495 | if (!is_access_granted(*access, is_write)) { | |
496 | return dtlb ? | |
497 | (is_write ? | |
498 | STORE_PROHIBITED_CAUSE : | |
499 | LOAD_PROHIBITED_CAUSE) : | |
500 | INST_FETCH_PROHIBITED_CAUSE; | |
501 | } | |
502 | ||
503 | *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi)); | |
504 | *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; | |
505 | ||
506 | return 0; | |
507 | } | |
508 | ||
97129ac8 | 509 | static int autorefill_mmu(CPUXtensaState *env, uint32_t vaddr, bool dtlb, |
b67ea0cd MF |
510 | uint32_t *wi, uint32_t *ei, uint8_t *ring) |
511 | { | |
512 | uint32_t paddr; | |
513 | uint32_t page_size; | |
514 | unsigned access; | |
515 | uint32_t pt_vaddr = | |
516 | (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc; | |
517 | int ret = get_physical_addr_mmu(env, pt_vaddr, 0, 0, | |
518 | &paddr, &page_size, &access); | |
519 | ||
520 | qemu_log("%s: trying autorefill(%08x) -> %08x\n", __func__, | |
521 | vaddr, ret ? ~0 : paddr); | |
522 | ||
523 | if (ret == 0) { | |
524 | uint32_t vpn; | |
525 | uint32_t pte = ldl_phys(paddr); | |
526 | ||
527 | *ring = (pte >> 4) & 0x3; | |
528 | *wi = (++env->autorefill_idx) & 0x3; | |
529 | split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, *wi, ei); | |
530 | xtensa_tlb_set_entry(env, dtlb, *wi, *ei, vpn, pte); | |
531 | qemu_log("%s: autorefill(%08x): %08x -> %08x\n", | |
532 | __func__, vaddr, vpn, pte); | |
533 | } | |
534 | return ret; | |
535 | } | |
536 | ||
97129ac8 | 537 | static int get_physical_addr_region(CPUXtensaState *env, |
b67ea0cd MF |
538 | uint32_t vaddr, int is_write, int mmu_idx, |
539 | uint32_t *paddr, uint32_t *page_size, unsigned *access) | |
540 | { | |
541 | bool dtlb = is_write != 2; | |
542 | uint32_t wi = 0; | |
543 | uint32_t ei = (vaddr >> 29) & 0x7; | |
544 | const xtensa_tlb_entry *entry = | |
545 | xtensa_tlb_get_entry(env, dtlb, wi, ei); | |
546 | ||
547 | *access = region_attr_to_access(entry->attr); | |
548 | if (!is_access_granted(*access, is_write)) { | |
549 | return dtlb ? | |
550 | (is_write ? | |
551 | STORE_PROHIBITED_CAUSE : | |
552 | LOAD_PROHIBITED_CAUSE) : | |
553 | INST_FETCH_PROHIBITED_CAUSE; | |
554 | } | |
555 | ||
556 | *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK); | |
557 | *page_size = ~REGION_PAGE_MASK + 1; | |
558 | ||
559 | return 0; | |
560 | } | |
561 | ||
562 | /*! | |
563 | * Convert virtual address to physical addr. | |
564 | * MMU may issue pagewalk and change xtensa autorefill TLB way entry. | |
565 | * | |
566 | * \return 0 if ok, exception cause code otherwise | |
567 | */ | |
97129ac8 | 568 | int xtensa_get_physical_addr(CPUXtensaState *env, |
b67ea0cd MF |
569 | uint32_t vaddr, int is_write, int mmu_idx, |
570 | uint32_t *paddr, uint32_t *page_size, unsigned *access) | |
571 | { | |
572 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
573 | return get_physical_addr_mmu(env, vaddr, is_write, mmu_idx, | |
574 | paddr, page_size, access); | |
575 | } else if (xtensa_option_bits_enabled(env->config, | |
576 | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | | |
577 | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) { | |
578 | return get_physical_addr_region(env, vaddr, is_write, mmu_idx, | |
579 | paddr, page_size, access); | |
580 | } else { | |
581 | *paddr = vaddr; | |
582 | *page_size = TARGET_PAGE_SIZE; | |
583 | *access = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
584 | return 0; | |
585 | } | |
586 | } | |
692f737c MF |
587 | |
588 | static void dump_tlb(FILE *f, fprintf_function cpu_fprintf, | |
97129ac8 | 589 | CPUXtensaState *env, bool dtlb) |
692f737c MF |
590 | { |
591 | unsigned wi, ei; | |
592 | const xtensa_tlb *conf = | |
593 | dtlb ? &env->config->dtlb : &env->config->itlb; | |
594 | unsigned (*attr_to_access)(uint32_t) = | |
595 | xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ? | |
596 | mmu_attr_to_access : region_attr_to_access; | |
597 | ||
598 | for (wi = 0; wi < conf->nways; ++wi) { | |
599 | uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; | |
600 | const char *sz_text; | |
601 | bool print_header = true; | |
602 | ||
603 | if (sz >= 0x100000) { | |
604 | sz >>= 20; | |
605 | sz_text = "MB"; | |
606 | } else { | |
607 | sz >>= 10; | |
608 | sz_text = "KB"; | |
609 | } | |
610 | ||
611 | for (ei = 0; ei < conf->way_size[wi]; ++ei) { | |
612 | const xtensa_tlb_entry *entry = | |
613 | xtensa_tlb_get_entry(env, dtlb, wi, ei); | |
614 | ||
615 | if (entry->asid) { | |
616 | unsigned access = attr_to_access(entry->attr); | |
617 | ||
618 | if (print_header) { | |
619 | print_header = false; | |
620 | cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text); | |
621 | cpu_fprintf(f, | |
622 | "\tVaddr Paddr ASID Attr RWX\n" | |
623 | "\t---------- ---------- ---- ---- ---\n"); | |
624 | } | |
625 | cpu_fprintf(f, | |
626 | "\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c\n", | |
627 | entry->vaddr, | |
628 | entry->paddr, | |
629 | entry->asid, | |
630 | entry->attr, | |
631 | (access & PAGE_READ) ? 'R' : '-', | |
632 | (access & PAGE_WRITE) ? 'W' : '-', | |
633 | (access & PAGE_EXEC) ? 'X' : '-'); | |
634 | } | |
635 | } | |
636 | } | |
637 | } | |
638 | ||
97129ac8 | 639 | void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env) |
692f737c MF |
640 | { |
641 | if (xtensa_option_bits_enabled(env->config, | |
642 | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | | |
643 | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) | | |
644 | XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) { | |
645 | ||
646 | cpu_fprintf(f, "ITLB:\n"); | |
647 | dump_tlb(f, cpu_fprintf, env, false); | |
648 | cpu_fprintf(f, "\nDTLB:\n"); | |
649 | dump_tlb(f, cpu_fprintf, env, true); | |
650 | } else { | |
651 | cpu_fprintf(f, "No TLB for this CPU core\n"); | |
652 | } | |
653 | } |