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2328826b MF |
1 | /* |
2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * * Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * * Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * * Neither the name of the Open Source and Linux Lab nor the | |
13 | * names of its contributors may be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
28 | #include "cpu.h" | |
16c1deae | 29 | #include "helper.h" |
3580ecad | 30 | #include "host-utils.h" |
2328826b | 31 | |
f492b82d MF |
32 | static void do_unaligned_access(CPUXtensaState *env, |
33 | target_ulong addr, int is_write, int is_user, uintptr_t retaddr); | |
5b4e481b MF |
34 | |
35 | #define ALIGNED_ONLY | |
2328826b MF |
36 | #define MMUSUFFIX _mmu |
37 | ||
38 | #define SHIFT 0 | |
39 | #include "softmmu_template.h" | |
40 | ||
41 | #define SHIFT 1 | |
42 | #include "softmmu_template.h" | |
43 | ||
44 | #define SHIFT 2 | |
45 | #include "softmmu_template.h" | |
46 | ||
47 | #define SHIFT 3 | |
48 | #include "softmmu_template.h" | |
49 | ||
f492b82d | 50 | static void do_restore_state(CPUXtensaState *env, uintptr_t pc) |
5b4e481b MF |
51 | { |
52 | TranslationBlock *tb; | |
5b4e481b MF |
53 | |
54 | tb = tb_find_pc(pc); | |
55 | if (tb) { | |
56 | cpu_restore_state(tb, env, pc); | |
57 | } | |
58 | } | |
59 | ||
f492b82d MF |
60 | static void do_unaligned_access(CPUXtensaState *env, |
61 | target_ulong addr, int is_write, int is_user, uintptr_t retaddr) | |
5b4e481b MF |
62 | { |
63 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) && | |
64 | !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) { | |
f492b82d MF |
65 | do_restore_state(env, retaddr); |
66 | HELPER(exception_cause_vaddr)(env, | |
5b4e481b MF |
67 | env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr); |
68 | } | |
69 | } | |
70 | ||
f492b82d MF |
71 | void tlb_fill(CPUXtensaState *env, |
72 | target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr) | |
2328826b | 73 | { |
f492b82d MF |
74 | uint32_t paddr; |
75 | uint32_t page_size; | |
76 | unsigned access; | |
77 | int ret = xtensa_get_physical_addr(env, true, vaddr, is_write, mmu_idx, | |
78 | &paddr, &page_size, &access); | |
b67ea0cd | 79 | |
f492b82d MF |
80 | qemu_log("%s(%08x, %d, %d) -> %08x, ret = %d\n", __func__, |
81 | vaddr, is_write, mmu_idx, paddr, ret); | |
b67ea0cd | 82 | |
f492b82d MF |
83 | if (ret == 0) { |
84 | tlb_set_page(env, | |
85 | vaddr & TARGET_PAGE_MASK, | |
86 | paddr & TARGET_PAGE_MASK, | |
87 | access, mmu_idx, page_size); | |
88 | } else { | |
89 | do_restore_state(env, retaddr); | |
90 | HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); | |
b67ea0cd | 91 | } |
2328826b | 92 | } |
dedc5eae | 93 | |
3d0be8a5 MF |
94 | static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) |
95 | { | |
96 | uint32_t paddr; | |
97 | uint32_t page_size; | |
98 | unsigned access; | |
ae4e7982 | 99 | int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0, |
3d0be8a5 MF |
100 | &paddr, &page_size, &access); |
101 | if (ret == 0) { | |
102 | tb_invalidate_phys_addr(paddr); | |
103 | } | |
104 | } | |
105 | ||
f492b82d | 106 | void HELPER(exception)(CPUXtensaState *env, uint32_t excp) |
dedc5eae MF |
107 | { |
108 | env->exception_index = excp; | |
109 | cpu_loop_exit(env); | |
110 | } | |
3580ecad | 111 | |
f492b82d | 112 | void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause) |
40643d7c MF |
113 | { |
114 | uint32_t vector; | |
115 | ||
116 | env->pc = pc; | |
117 | if (env->sregs[PS] & PS_EXCM) { | |
118 | if (env->config->ndepc) { | |
119 | env->sregs[DEPC] = pc; | |
120 | } else { | |
121 | env->sregs[EPC1] = pc; | |
122 | } | |
123 | vector = EXC_DOUBLE; | |
124 | } else { | |
125 | env->sregs[EPC1] = pc; | |
126 | vector = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL; | |
127 | } | |
128 | ||
129 | env->sregs[EXCCAUSE] = cause; | |
130 | env->sregs[PS] |= PS_EXCM; | |
131 | ||
f492b82d | 132 | HELPER(exception)(env, vector); |
40643d7c MF |
133 | } |
134 | ||
f492b82d MF |
135 | void HELPER(exception_cause_vaddr)(CPUXtensaState *env, |
136 | uint32_t pc, uint32_t cause, uint32_t vaddr) | |
40643d7c MF |
137 | { |
138 | env->sregs[EXCVADDR] = vaddr; | |
f492b82d | 139 | HELPER(exception_cause)(env, pc, cause); |
40643d7c MF |
140 | } |
141 | ||
f492b82d | 142 | void debug_exception_env(CPUXtensaState *env, uint32_t cause) |
f14c4b5f | 143 | { |
f492b82d MF |
144 | if (xtensa_get_cintlevel(env) < env->config->debug_level) { |
145 | HELPER(debug_exception)(env, env->pc, cause); | |
f14c4b5f MF |
146 | } |
147 | } | |
148 | ||
f492b82d | 149 | void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause) |
e61dc8f7 MF |
150 | { |
151 | unsigned level = env->config->debug_level; | |
152 | ||
153 | env->pc = pc; | |
154 | env->sregs[DEBUGCAUSE] = cause; | |
155 | env->sregs[EPC1 + level - 1] = pc; | |
156 | env->sregs[EPS2 + level - 2] = env->sregs[PS]; | |
157 | env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM | | |
158 | (level << PS_INTLEVEL_SHIFT); | |
f492b82d | 159 | HELPER(exception)(env, EXC_DEBUG); |
e61dc8f7 MF |
160 | } |
161 | ||
3580ecad MF |
162 | uint32_t HELPER(nsa)(uint32_t v) |
163 | { | |
164 | if (v & 0x80000000) { | |
165 | v = ~v; | |
166 | } | |
167 | return v ? clz32(v) - 1 : 31; | |
168 | } | |
169 | ||
170 | uint32_t HELPER(nsau)(uint32_t v) | |
171 | { | |
172 | return v ? clz32(v) : 32; | |
173 | } | |
553e44f9 | 174 | |
97129ac8 | 175 | static void copy_window_from_phys(CPUXtensaState *env, |
553e44f9 MF |
176 | uint32_t window, uint32_t phys, uint32_t n) |
177 | { | |
178 | assert(phys < env->config->nareg); | |
179 | if (phys + n <= env->config->nareg) { | |
180 | memcpy(env->regs + window, env->phys_regs + phys, | |
181 | n * sizeof(uint32_t)); | |
182 | } else { | |
183 | uint32_t n1 = env->config->nareg - phys; | |
184 | memcpy(env->regs + window, env->phys_regs + phys, | |
185 | n1 * sizeof(uint32_t)); | |
186 | memcpy(env->regs + window + n1, env->phys_regs, | |
187 | (n - n1) * sizeof(uint32_t)); | |
188 | } | |
189 | } | |
190 | ||
97129ac8 | 191 | static void copy_phys_from_window(CPUXtensaState *env, |
553e44f9 MF |
192 | uint32_t phys, uint32_t window, uint32_t n) |
193 | { | |
194 | assert(phys < env->config->nareg); | |
195 | if (phys + n <= env->config->nareg) { | |
196 | memcpy(env->phys_regs + phys, env->regs + window, | |
197 | n * sizeof(uint32_t)); | |
198 | } else { | |
199 | uint32_t n1 = env->config->nareg - phys; | |
200 | memcpy(env->phys_regs + phys, env->regs + window, | |
201 | n1 * sizeof(uint32_t)); | |
202 | memcpy(env->phys_regs, env->regs + window + n1, | |
203 | (n - n1) * sizeof(uint32_t)); | |
204 | } | |
205 | } | |
206 | ||
207 | ||
97129ac8 | 208 | static inline unsigned windowbase_bound(unsigned a, const CPUXtensaState *env) |
553e44f9 MF |
209 | { |
210 | return a & (env->config->nareg / 4 - 1); | |
211 | } | |
212 | ||
97129ac8 | 213 | static inline unsigned windowstart_bit(unsigned a, const CPUXtensaState *env) |
553e44f9 MF |
214 | { |
215 | return 1 << windowbase_bound(a, env); | |
216 | } | |
217 | ||
97129ac8 | 218 | void xtensa_sync_window_from_phys(CPUXtensaState *env) |
553e44f9 MF |
219 | { |
220 | copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16); | |
221 | } | |
222 | ||
97129ac8 | 223 | void xtensa_sync_phys_from_window(CPUXtensaState *env) |
553e44f9 MF |
224 | { |
225 | copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16); | |
226 | } | |
227 | ||
f492b82d | 228 | static void rotate_window_abs(CPUXtensaState *env, uint32_t position) |
553e44f9 MF |
229 | { |
230 | xtensa_sync_phys_from_window(env); | |
231 | env->sregs[WINDOW_BASE] = windowbase_bound(position, env); | |
232 | xtensa_sync_window_from_phys(env); | |
233 | } | |
234 | ||
f492b82d | 235 | static void rotate_window(CPUXtensaState *env, uint32_t delta) |
553e44f9 | 236 | { |
f492b82d | 237 | rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta); |
553e44f9 MF |
238 | } |
239 | ||
f492b82d | 240 | void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v) |
553e44f9 | 241 | { |
f492b82d | 242 | rotate_window_abs(env, v); |
553e44f9 MF |
243 | } |
244 | ||
f492b82d | 245 | void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm) |
553e44f9 MF |
246 | { |
247 | int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT; | |
248 | if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) { | |
249 | qemu_log("Illegal entry instruction(pc = %08x), PS = %08x\n", | |
250 | pc, env->sregs[PS]); | |
f492b82d | 251 | HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE); |
553e44f9 MF |
252 | } else { |
253 | env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3); | |
f492b82d | 254 | rotate_window(env, callinc); |
553e44f9 MF |
255 | env->sregs[WINDOW_START] |= |
256 | windowstart_bit(env->sregs[WINDOW_BASE], env); | |
257 | } | |
258 | } | |
259 | ||
f492b82d | 260 | void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w) |
553e44f9 MF |
261 | { |
262 | uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env); | |
263 | uint32_t windowstart = env->sregs[WINDOW_START]; | |
264 | uint32_t m, n; | |
265 | ||
266 | if ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) { | |
267 | return; | |
268 | } | |
269 | ||
270 | for (n = 1; ; ++n) { | |
271 | if (n > w) { | |
272 | return; | |
273 | } | |
274 | if (windowstart & windowstart_bit(windowbase + n, env)) { | |
275 | break; | |
276 | } | |
277 | } | |
278 | ||
279 | m = windowbase_bound(windowbase + n, env); | |
f492b82d | 280 | rotate_window(env, n); |
553e44f9 MF |
281 | env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) | |
282 | (windowbase << PS_OWB_SHIFT) | PS_EXCM; | |
283 | env->sregs[EPC1] = env->pc = pc; | |
284 | ||
285 | if (windowstart & windowstart_bit(m + 1, env)) { | |
f492b82d | 286 | HELPER(exception)(env, EXC_WINDOW_OVERFLOW4); |
553e44f9 | 287 | } else if (windowstart & windowstart_bit(m + 2, env)) { |
f492b82d | 288 | HELPER(exception)(env, EXC_WINDOW_OVERFLOW8); |
553e44f9 | 289 | } else { |
f492b82d | 290 | HELPER(exception)(env, EXC_WINDOW_OVERFLOW12); |
553e44f9 MF |
291 | } |
292 | } | |
293 | ||
f492b82d | 294 | uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc) |
553e44f9 MF |
295 | { |
296 | int n = (env->regs[0] >> 30) & 0x3; | |
297 | int m = 0; | |
298 | uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env); | |
299 | uint32_t windowstart = env->sregs[WINDOW_START]; | |
300 | uint32_t ret_pc = 0; | |
301 | ||
302 | if (windowstart & windowstart_bit(windowbase - 1, env)) { | |
303 | m = 1; | |
304 | } else if (windowstart & windowstart_bit(windowbase - 2, env)) { | |
305 | m = 2; | |
306 | } else if (windowstart & windowstart_bit(windowbase - 3, env)) { | |
307 | m = 3; | |
308 | } | |
309 | ||
310 | if (n == 0 || (m != 0 && m != n) || | |
311 | ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) { | |
312 | qemu_log("Illegal retw instruction(pc = %08x), " | |
313 | "PS = %08x, m = %d, n = %d\n", | |
314 | pc, env->sregs[PS], m, n); | |
f492b82d | 315 | HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE); |
553e44f9 MF |
316 | } else { |
317 | int owb = windowbase; | |
318 | ||
319 | ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff); | |
320 | ||
f492b82d | 321 | rotate_window(env, -n); |
553e44f9 MF |
322 | if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) { |
323 | env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env); | |
324 | } else { | |
325 | /* window underflow */ | |
326 | env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) | | |
327 | (windowbase << PS_OWB_SHIFT) | PS_EXCM; | |
328 | env->sregs[EPC1] = env->pc = pc; | |
329 | ||
330 | if (n == 1) { | |
f492b82d | 331 | HELPER(exception)(env, EXC_WINDOW_UNDERFLOW4); |
553e44f9 | 332 | } else if (n == 2) { |
f492b82d | 333 | HELPER(exception)(env, EXC_WINDOW_UNDERFLOW8); |
553e44f9 | 334 | } else if (n == 3) { |
f492b82d | 335 | HELPER(exception)(env, EXC_WINDOW_UNDERFLOW12); |
553e44f9 MF |
336 | } |
337 | } | |
338 | } | |
339 | return ret_pc; | |
340 | } | |
341 | ||
f492b82d | 342 | void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4) |
553e44f9 | 343 | { |
f492b82d | 344 | rotate_window(env, imm4); |
553e44f9 MF |
345 | } |
346 | ||
f492b82d | 347 | void HELPER(restore_owb)(CPUXtensaState *env) |
553e44f9 | 348 | { |
f492b82d | 349 | rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT); |
553e44f9 MF |
350 | } |
351 | ||
f492b82d | 352 | void HELPER(movsp)(CPUXtensaState *env, uint32_t pc) |
553e44f9 MF |
353 | { |
354 | if ((env->sregs[WINDOW_START] & | |
355 | (windowstart_bit(env->sregs[WINDOW_BASE] - 3, env) | | |
356 | windowstart_bit(env->sregs[WINDOW_BASE] - 2, env) | | |
357 | windowstart_bit(env->sregs[WINDOW_BASE] - 1, env))) == 0) { | |
f492b82d | 358 | HELPER(exception_cause)(env, pc, ALLOCA_CAUSE); |
553e44f9 MF |
359 | } |
360 | } | |
361 | ||
f492b82d | 362 | void HELPER(wsr_lbeg)(CPUXtensaState *env, uint32_t v) |
797d780b MF |
363 | { |
364 | if (env->sregs[LBEG] != v) { | |
3d0be8a5 | 365 | tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1); |
797d780b MF |
366 | env->sregs[LBEG] = v; |
367 | } | |
368 | } | |
369 | ||
f492b82d | 370 | void HELPER(wsr_lend)(CPUXtensaState *env, uint32_t v) |
797d780b MF |
371 | { |
372 | if (env->sregs[LEND] != v) { | |
3d0be8a5 | 373 | tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1); |
797d780b | 374 | env->sregs[LEND] = v; |
3d0be8a5 | 375 | tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1); |
797d780b MF |
376 | } |
377 | } | |
378 | ||
f492b82d | 379 | void HELPER(dump_state)(CPUXtensaState *env) |
553e44f9 MF |
380 | { |
381 | cpu_dump_state(env, stderr, fprintf, 0); | |
382 | } | |
b994e91b | 383 | |
f492b82d | 384 | void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel) |
b994e91b MF |
385 | { |
386 | env->pc = pc; | |
387 | env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | | |
388 | (intlevel << PS_INTLEVEL_SHIFT); | |
389 | check_interrupts(env); | |
390 | if (env->pending_irq_level) { | |
391 | cpu_loop_exit(env); | |
392 | return; | |
393 | } | |
394 | ||
b994e91b MF |
395 | env->halt_clock = qemu_get_clock_ns(vm_clock); |
396 | env->halted = 1; | |
890c6333 MF |
397 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) { |
398 | xtensa_rearm_ccompare_timer(env); | |
399 | } | |
f492b82d | 400 | HELPER(exception)(env, EXCP_HLT); |
b994e91b MF |
401 | } |
402 | ||
f492b82d | 403 | void HELPER(timer_irq)(CPUXtensaState *env, uint32_t id, uint32_t active) |
b994e91b MF |
404 | { |
405 | xtensa_timer_irq(env, id, active); | |
406 | } | |
407 | ||
f492b82d | 408 | void HELPER(advance_ccount)(CPUXtensaState *env, uint32_t d) |
b994e91b MF |
409 | { |
410 | xtensa_advance_ccount(env, d); | |
411 | } | |
412 | ||
97129ac8 | 413 | void HELPER(check_interrupts)(CPUXtensaState *env) |
b994e91b MF |
414 | { |
415 | check_interrupts(env); | |
416 | } | |
b67ea0cd | 417 | |
fcc803d1 MF |
418 | /*! |
419 | * Check vaddr accessibility/cache attributes and raise an exception if | |
420 | * specified by the ATOMCTL SR. | |
421 | * | |
422 | * Note: local memory exclusion is not implemented | |
423 | */ | |
424 | void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr) | |
425 | { | |
426 | uint32_t paddr, page_size, access; | |
427 | uint32_t atomctl = env->sregs[ATOMCTL]; | |
428 | int rc = xtensa_get_physical_addr(env, true, vaddr, 1, | |
429 | xtensa_get_cring(env), &paddr, &page_size, &access); | |
430 | ||
431 | /* | |
432 | * s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions, | |
433 | * see opcode description in the ISA | |
434 | */ | |
435 | if (rc == 0 && | |
436 | (access & (PAGE_READ | PAGE_WRITE)) != (PAGE_READ | PAGE_WRITE)) { | |
437 | rc = STORE_PROHIBITED_CAUSE; | |
438 | } | |
439 | ||
440 | if (rc) { | |
441 | HELPER(exception_cause_vaddr)(env, pc, rc, vaddr); | |
442 | } | |
443 | ||
444 | /* | |
445 | * When data cache is not configured use ATOMCTL bypass field. | |
446 | * See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL) | |
447 | * under the Conditional Store Option. | |
448 | */ | |
449 | if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) { | |
450 | access = PAGE_CACHE_BYPASS; | |
451 | } | |
452 | ||
453 | switch (access & PAGE_CACHE_MASK) { | |
454 | case PAGE_CACHE_WB: | |
455 | atomctl >>= 2; | |
456 | case PAGE_CACHE_WT: | |
457 | atomctl >>= 2; | |
458 | case PAGE_CACHE_BYPASS: | |
459 | if ((atomctl & 0x3) == 0) { | |
460 | HELPER(exception_cause_vaddr)(env, pc, | |
461 | LOAD_STORE_ERROR_CAUSE, vaddr); | |
462 | } | |
463 | break; | |
464 | ||
465 | case PAGE_CACHE_ISOLATE: | |
466 | HELPER(exception_cause_vaddr)(env, pc, | |
467 | LOAD_STORE_ERROR_CAUSE, vaddr); | |
468 | break; | |
469 | ||
470 | default: | |
471 | break; | |
472 | } | |
473 | } | |
474 | ||
f492b82d | 475 | void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) |
b67ea0cd MF |
476 | { |
477 | v = (v & 0xffffff00) | 0x1; | |
478 | if (v != env->sregs[RASID]) { | |
479 | env->sregs[RASID] = v; | |
480 | tlb_flush(env, 1); | |
481 | } | |
482 | } | |
483 | ||
97129ac8 | 484 | static uint32_t get_page_size(const CPUXtensaState *env, bool dtlb, uint32_t way) |
b67ea0cd MF |
485 | { |
486 | uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG]; | |
487 | ||
488 | switch (way) { | |
489 | case 4: | |
490 | return (tlbcfg >> 16) & 0x3; | |
491 | ||
492 | case 5: | |
493 | return (tlbcfg >> 20) & 0x1; | |
494 | ||
495 | case 6: | |
496 | return (tlbcfg >> 24) & 0x1; | |
497 | ||
498 | default: | |
499 | return 0; | |
500 | } | |
501 | } | |
502 | ||
503 | /*! | |
504 | * Get bit mask for the virtual address bits translated by the TLB way | |
505 | */ | |
97129ac8 | 506 | uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way) |
b67ea0cd MF |
507 | { |
508 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
509 | bool varway56 = dtlb ? | |
510 | env->config->dtlb.varway56 : | |
511 | env->config->itlb.varway56; | |
512 | ||
513 | switch (way) { | |
514 | case 4: | |
515 | return 0xfff00000 << get_page_size(env, dtlb, way) * 2; | |
516 | ||
517 | case 5: | |
518 | if (varway56) { | |
519 | return 0xf8000000 << get_page_size(env, dtlb, way); | |
520 | } else { | |
521 | return 0xf8000000; | |
522 | } | |
523 | ||
524 | case 6: | |
525 | if (varway56) { | |
526 | return 0xf0000000 << (1 - get_page_size(env, dtlb, way)); | |
527 | } else { | |
528 | return 0xf0000000; | |
529 | } | |
530 | ||
531 | default: | |
532 | return 0xfffff000; | |
533 | } | |
534 | } else { | |
535 | return REGION_PAGE_MASK; | |
536 | } | |
537 | } | |
538 | ||
539 | /*! | |
540 | * Get bit mask for the 'VPN without index' field. | |
541 | * See ISA, 4.6.5.6, data format for RxTLB0 | |
542 | */ | |
97129ac8 | 543 | static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way) |
b67ea0cd MF |
544 | { |
545 | if (way < 4) { | |
546 | bool is32 = (dtlb ? | |
547 | env->config->dtlb.nrefillentries : | |
548 | env->config->itlb.nrefillentries) == 32; | |
549 | return is32 ? 0xffff8000 : 0xffffc000; | |
550 | } else if (way == 4) { | |
551 | return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2; | |
552 | } else if (way <= 6) { | |
553 | uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way); | |
554 | bool varway56 = dtlb ? | |
555 | env->config->dtlb.varway56 : | |
556 | env->config->itlb.varway56; | |
557 | ||
558 | if (varway56) { | |
559 | return mask << (way == 5 ? 2 : 3); | |
560 | } else { | |
561 | return mask << 1; | |
562 | } | |
563 | } else { | |
564 | return 0xfffff000; | |
565 | } | |
566 | } | |
567 | ||
568 | /*! | |
569 | * Split virtual address into VPN (with index) and entry index | |
570 | * for the given TLB way | |
571 | */ | |
97129ac8 | 572 | void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb, |
b67ea0cd MF |
573 | uint32_t *vpn, uint32_t wi, uint32_t *ei) |
574 | { | |
575 | bool varway56 = dtlb ? | |
576 | env->config->dtlb.varway56 : | |
577 | env->config->itlb.varway56; | |
578 | ||
579 | if (!dtlb) { | |
580 | wi &= 7; | |
581 | } | |
582 | ||
583 | if (wi < 4) { | |
584 | bool is32 = (dtlb ? | |
585 | env->config->dtlb.nrefillentries : | |
586 | env->config->itlb.nrefillentries) == 32; | |
587 | *ei = (v >> 12) & (is32 ? 0x7 : 0x3); | |
588 | } else { | |
589 | switch (wi) { | |
590 | case 4: | |
591 | { | |
592 | uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2; | |
593 | *ei = (v >> eibase) & 0x3; | |
594 | } | |
595 | break; | |
596 | ||
597 | case 5: | |
598 | if (varway56) { | |
599 | uint32_t eibase = 27 + get_page_size(env, dtlb, wi); | |
600 | *ei = (v >> eibase) & 0x3; | |
601 | } else { | |
602 | *ei = (v >> 27) & 0x1; | |
603 | } | |
604 | break; | |
605 | ||
606 | case 6: | |
607 | if (varway56) { | |
608 | uint32_t eibase = 29 - get_page_size(env, dtlb, wi); | |
609 | *ei = (v >> eibase) & 0x7; | |
610 | } else { | |
611 | *ei = (v >> 28) & 0x1; | |
612 | } | |
613 | break; | |
614 | ||
615 | default: | |
616 | *ei = 0; | |
617 | break; | |
618 | } | |
619 | } | |
620 | *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi); | |
621 | } | |
622 | ||
623 | /*! | |
624 | * Split TLB address into TLB way, entry index and VPN (with index). | |
625 | * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format | |
626 | */ | |
f492b82d | 627 | static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb, |
b67ea0cd MF |
628 | uint32_t *vpn, uint32_t *wi, uint32_t *ei) |
629 | { | |
630 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
631 | *wi = v & (dtlb ? 0xf : 0x7); | |
632 | split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei); | |
633 | } else { | |
634 | *vpn = v & REGION_PAGE_MASK; | |
635 | *wi = 0; | |
636 | *ei = (v >> 29) & 0x7; | |
637 | } | |
638 | } | |
639 | ||
f492b82d MF |
640 | static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env, |
641 | uint32_t v, bool dtlb, uint32_t *pwi) | |
b67ea0cd MF |
642 | { |
643 | uint32_t vpn; | |
644 | uint32_t wi; | |
645 | uint32_t ei; | |
646 | ||
f492b82d | 647 | split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); |
b67ea0cd MF |
648 | if (pwi) { |
649 | *pwi = wi; | |
650 | } | |
651 | return xtensa_tlb_get_entry(env, dtlb, wi, ei); | |
652 | } | |
653 | ||
f492b82d | 654 | uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) |
b67ea0cd MF |
655 | { |
656 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
657 | uint32_t wi; | |
f492b82d | 658 | const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); |
b67ea0cd MF |
659 | return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid; |
660 | } else { | |
661 | return v & REGION_PAGE_MASK; | |
662 | } | |
663 | } | |
664 | ||
f492b82d | 665 | uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) |
b67ea0cd | 666 | { |
f492b82d | 667 | const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL); |
b67ea0cd MF |
668 | return entry->paddr | entry->attr; |
669 | } | |
670 | ||
f492b82d | 671 | void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) |
b67ea0cd MF |
672 | { |
673 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
674 | uint32_t wi; | |
f492b82d | 675 | xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); |
b67ea0cd MF |
676 | if (entry->variable && entry->asid) { |
677 | tlb_flush_page(env, entry->vaddr); | |
678 | entry->asid = 0; | |
679 | } | |
680 | } | |
681 | } | |
682 | ||
f492b82d | 683 | uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) |
b67ea0cd MF |
684 | { |
685 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
686 | uint32_t wi; | |
687 | uint32_t ei; | |
688 | uint8_t ring; | |
689 | int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring); | |
690 | ||
691 | switch (res) { | |
692 | case 0: | |
693 | if (ring >= xtensa_get_ring(env)) { | |
694 | return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8); | |
695 | } | |
696 | break; | |
697 | ||
698 | case INST_TLB_MULTI_HIT_CAUSE: | |
699 | case LOAD_STORE_TLB_MULTI_HIT_CAUSE: | |
f492b82d | 700 | HELPER(exception_cause_vaddr)(env, env->pc, res, v); |
b67ea0cd MF |
701 | break; |
702 | } | |
703 | return 0; | |
704 | } else { | |
705 | return (v & REGION_PAGE_MASK) | 0x1; | |
706 | } | |
707 | } | |
708 | ||
16bde77a MF |
709 | void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, |
710 | xtensa_tlb_entry *entry, bool dtlb, | |
711 | unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) | |
712 | { | |
713 | entry->vaddr = vpn; | |
714 | entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi); | |
715 | entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff; | |
716 | entry->attr = pte & 0xf; | |
717 | } | |
718 | ||
97129ac8 | 719 | void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, |
b67ea0cd MF |
720 | unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) |
721 | { | |
722 | xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); | |
723 | ||
724 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
725 | if (entry->variable) { | |
726 | if (entry->asid) { | |
727 | tlb_flush_page(env, entry->vaddr); | |
728 | } | |
16bde77a | 729 | xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte); |
e323bdef | 730 | tlb_flush_page(env, entry->vaddr); |
b67ea0cd MF |
731 | } else { |
732 | qemu_log("%s %d, %d, %d trying to set immutable entry\n", | |
733 | __func__, dtlb, wi, ei); | |
734 | } | |
735 | } else { | |
736 | tlb_flush_page(env, entry->vaddr); | |
737 | if (xtensa_option_enabled(env->config, | |
738 | XTENSA_OPTION_REGION_TRANSLATION)) { | |
739 | entry->paddr = pte & REGION_PAGE_MASK; | |
740 | } | |
741 | entry->attr = pte & 0xf; | |
742 | } | |
743 | } | |
744 | ||
f492b82d | 745 | void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb) |
b67ea0cd MF |
746 | { |
747 | uint32_t vpn; | |
748 | uint32_t wi; | |
749 | uint32_t ei; | |
f492b82d | 750 | split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); |
b67ea0cd MF |
751 | xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p); |
752 | } | |
e61dc8f7 MF |
753 | |
754 | ||
f492b82d | 755 | void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v) |
e61dc8f7 MF |
756 | { |
757 | uint32_t change = v ^ env->sregs[IBREAKENABLE]; | |
758 | unsigned i; | |
759 | ||
760 | for (i = 0; i < env->config->nibreak; ++i) { | |
761 | if (change & (1 << i)) { | |
3d0be8a5 | 762 | tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]); |
e61dc8f7 MF |
763 | } |
764 | } | |
765 | env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1); | |
766 | } | |
767 | ||
f492b82d | 768 | void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) |
e61dc8f7 MF |
769 | { |
770 | if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) { | |
3d0be8a5 MF |
771 | tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]); |
772 | tb_invalidate_virtual_addr(env, v); | |
e61dc8f7 MF |
773 | } |
774 | env->sregs[IBREAKA + i] = v; | |
775 | } | |
f14c4b5f | 776 | |
f492b82d MF |
777 | static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka, |
778 | uint32_t dbreakc) | |
f14c4b5f MF |
779 | { |
780 | int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; | |
781 | uint32_t mask = dbreakc | ~DBREAKC_MASK; | |
782 | ||
783 | if (env->cpu_watchpoint[i]) { | |
784 | cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]); | |
785 | } | |
786 | if (dbreakc & DBREAKC_SB) { | |
787 | flags |= BP_MEM_WRITE; | |
788 | } | |
789 | if (dbreakc & DBREAKC_LB) { | |
790 | flags |= BP_MEM_READ; | |
791 | } | |
792 | /* contiguous mask after inversion is one less than some power of 2 */ | |
793 | if ((~mask + 1) & ~mask) { | |
794 | qemu_log("DBREAKC mask is not contiguous: 0x%08x\n", dbreakc); | |
795 | /* cut mask after the first zero bit */ | |
796 | mask = 0xffffffff << (32 - clo32(mask)); | |
797 | } | |
798 | if (cpu_watchpoint_insert(env, dbreaka & mask, ~mask + 1, | |
799 | flags, &env->cpu_watchpoint[i])) { | |
800 | env->cpu_watchpoint[i] = NULL; | |
801 | qemu_log("Failed to set data breakpoint at 0x%08x/%d\n", | |
802 | dbreaka & mask, ~mask + 1); | |
803 | } | |
804 | } | |
805 | ||
f492b82d | 806 | void HELPER(wsr_dbreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) |
f14c4b5f MF |
807 | { |
808 | uint32_t dbreakc = env->sregs[DBREAKC + i]; | |
809 | ||
810 | if ((dbreakc & DBREAKC_SB_LB) && | |
811 | env->sregs[DBREAKA + i] != v) { | |
f492b82d | 812 | set_dbreak(env, i, v, dbreakc); |
f14c4b5f MF |
813 | } |
814 | env->sregs[DBREAKA + i] = v; | |
815 | } | |
816 | ||
f492b82d | 817 | void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v) |
f14c4b5f MF |
818 | { |
819 | if ((env->sregs[DBREAKC + i] ^ v) & (DBREAKC_SB_LB | DBREAKC_MASK)) { | |
820 | if (v & DBREAKC_SB_LB) { | |
f492b82d | 821 | set_dbreak(env, i, env->sregs[DBREAKA + i], v); |
f14c4b5f MF |
822 | } else { |
823 | if (env->cpu_watchpoint[i]) { | |
824 | cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]); | |
825 | env->cpu_watchpoint[i] = NULL; | |
826 | } | |
827 | } | |
828 | } | |
829 | env->sregs[DBREAKC + i] = v; | |
830 | } | |
dd519cbe MF |
831 | |
832 | void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v) | |
833 | { | |
834 | static const int rounding_mode[] = { | |
835 | float_round_nearest_even, | |
836 | float_round_to_zero, | |
837 | float_round_up, | |
838 | float_round_down, | |
839 | }; | |
840 | ||
841 | env->uregs[FCR] = v & 0xfffff07f; | |
842 | set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status); | |
843 | } | |
0b6df838 MF |
844 | |
845 | float32 HELPER(abs_s)(float32 v) | |
846 | { | |
847 | return float32_abs(v); | |
848 | } | |
849 | ||
850 | float32 HELPER(neg_s)(float32 v) | |
851 | { | |
852 | return float32_chs(v); | |
853 | } | |
854 | ||
855 | float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b) | |
856 | { | |
857 | return float32_add(a, b, &env->fp_status); | |
858 | } | |
859 | ||
860 | float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b) | |
861 | { | |
862 | return float32_sub(a, b, &env->fp_status); | |
863 | } | |
864 | ||
865 | float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b) | |
866 | { | |
867 | return float32_mul(a, b, &env->fp_status); | |
868 | } | |
869 | ||
870 | float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c) | |
871 | { | |
872 | return float32_muladd(b, c, a, 0, | |
873 | &env->fp_status); | |
874 | } | |
875 | ||
876 | float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c) | |
877 | { | |
878 | return float32_muladd(b, c, a, float_muladd_negate_product, | |
879 | &env->fp_status); | |
880 | } | |
b7ee8c6a MF |
881 | |
882 | uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale) | |
883 | { | |
884 | float_status fp_status = {0}; | |
885 | ||
886 | set_float_rounding_mode(rounding_mode, &fp_status); | |
887 | return float32_to_int32( | |
888 | float32_scalbn(v, scale, &fp_status), &fp_status); | |
889 | } | |
890 | ||
891 | uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale) | |
892 | { | |
893 | float_status fp_status = {0}; | |
894 | float32 res; | |
895 | ||
896 | set_float_rounding_mode(rounding_mode, &fp_status); | |
897 | ||
898 | res = float32_scalbn(v, scale, &fp_status); | |
899 | ||
900 | if (float32_is_neg(v) && !float32_is_any_nan(v)) { | |
901 | return float32_to_int32(res, &fp_status); | |
902 | } else { | |
903 | return float32_to_uint32(res, &fp_status); | |
904 | } | |
905 | } | |
906 | ||
907 | float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale) | |
908 | { | |
909 | return float32_scalbn(int32_to_float32(v, &env->fp_status), | |
910 | (int32_t)scale, &env->fp_status); | |
911 | } | |
912 | ||
913 | float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale) | |
914 | { | |
915 | return float32_scalbn(uint32_to_float32(v, &env->fp_status), | |
916 | (int32_t)scale, &env->fp_status); | |
917 | } | |
4e273869 MF |
918 | |
919 | static inline void set_br(CPUXtensaState *env, bool v, uint32_t br) | |
920 | { | |
921 | if (v) { | |
922 | env->sregs[BR] |= br; | |
923 | } else { | |
924 | env->sregs[BR] &= ~br; | |
925 | } | |
926 | } | |
927 | ||
928 | void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) | |
929 | { | |
930 | set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br); | |
931 | } | |
932 | ||
933 | void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) | |
934 | { | |
935 | set_br(env, float32_eq_quiet(a, b, &env->fp_status), br); | |
936 | } | |
937 | ||
938 | void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) | |
939 | { | |
940 | int v = float32_compare_quiet(a, b, &env->fp_status); | |
941 | set_br(env, v == float_relation_equal || v == float_relation_unordered, br); | |
942 | } | |
943 | ||
944 | void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) | |
945 | { | |
946 | set_br(env, float32_lt_quiet(a, b, &env->fp_status), br); | |
947 | } | |
948 | ||
949 | void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) | |
950 | { | |
951 | int v = float32_compare_quiet(a, b, &env->fp_status); | |
952 | set_br(env, v == float_relation_less || v == float_relation_unordered, br); | |
953 | } | |
954 | ||
955 | void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) | |
956 | { | |
957 | set_br(env, float32_le_quiet(a, b, &env->fp_status), br); | |
958 | } | |
959 | ||
960 | void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) | |
961 | { | |
962 | int v = float32_compare_quiet(a, b, &env->fp_status); | |
963 | set_br(env, v != float_relation_greater, br); | |
964 | } |