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target-xtensa: extract core configuration from overlay
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1/*
2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \
29 a1, a2, a3, a4, a5, a6) \
30 { .targno = (no), .type = (typ), .group = (grp) },
31
32#ifndef XCHAL_HAVE_DIV32
33#define XCHAL_HAVE_DIV32 0
34#endif
35
36#ifndef XCHAL_UNALIGNED_LOAD_HW
37#define XCHAL_UNALIGNED_LOAD_HW 0
38#endif
39
40#ifndef XCHAL_HAVE_VECBASE
41#define XCHAL_HAVE_VECBASE 0
42#define XCHAL_VECBASE_RESET_VADDR 0
43#endif
44
45#define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0)
46
47#define XTENSA_OPTIONS ( \
48 XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) | \
49 XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) | \
50 XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) | \
51 XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) | \
52 XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) | \
53 XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) | \
54 XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) | \
55 XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) | \
56 XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) | \
57 XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) | \
58 XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) | \
59 XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) | \
60 XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
61 XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
62 XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
63 XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
64 /* Interrupts and exceptions */ \
65 XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \
66 XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \
67 XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \
68 XTENSA_OPTION_UNALIGNED_EXCEPTION) | \
69 XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) | \
70 XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \
71 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \
72 XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \
73 /* Local memory, TODO */ \
74 XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \
75 /* Memory protection and translation */ \
76 XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
77 XTENSA_OPTION_REGION_PROTECTION) | \
78 XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \
79 XTENSA_OPTION_REGION_TRANSLATION) | \
80 XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \
81 /* Other, TODO */ \
82 XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \
83 XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG))
84
85#ifndef XCHAL_WINDOW_OF4_VECOFS
86#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
87#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
88#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
89#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
90#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
91#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
92#endif
93
94#define EXCEPTION_VECTORS { \
95 [EXC_RESET] = XCHAL_RESET_VECTOR_VADDR, \
96 [EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
97 XCHAL_WINDOW_VECTORS_VADDR, \
98 [EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
99 XCHAL_WINDOW_VECTORS_VADDR, \
100 [EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \
101 XCHAL_WINDOW_VECTORS_VADDR, \
102 [EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \
103 XCHAL_WINDOW_VECTORS_VADDR, \
104 [EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
105 XCHAL_WINDOW_VECTORS_VADDR, \
106 [EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
107 XCHAL_WINDOW_VECTORS_VADDR, \
108 [EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
109 [EXC_USER] = XCHAL_USER_VECTOR_VADDR, \
110 [EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \
111 }
112
113#define INTERRUPT_VECTORS { \
114 0, \
115 0, \
116 XCHAL_INTLEVEL2_VECTOR_VADDR, \
117 XCHAL_INTLEVEL3_VECTOR_VADDR, \
118 XCHAL_INTLEVEL4_VECTOR_VADDR, \
119 XCHAL_INTLEVEL5_VECTOR_VADDR, \
120 XCHAL_INTLEVEL6_VECTOR_VADDR, \
121 XCHAL_INTLEVEL7_VECTOR_VADDR, \
122 }
123
124#define LEVEL_MASKS { \
125 [1] = XCHAL_INTLEVEL1_MASK, \
126 [2] = XCHAL_INTLEVEL2_MASK, \
127 [3] = XCHAL_INTLEVEL3_MASK, \
128 [4] = XCHAL_INTLEVEL4_MASK, \
129 [5] = XCHAL_INTLEVEL5_MASK, \
130 [6] = XCHAL_INTLEVEL6_MASK, \
131 [7] = XCHAL_INTLEVEL7_MASK, \
132 }
133
134#define INTTYPE_MASKS { \
135 [INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \
136 [INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \
137 [INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \
138 }
139
140#define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL
141#define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE
142#define XTHAL_INTTYPE_NMI INTTYPE_NMI
143#define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE
144#define XTHAL_INTTYPE_TIMER INTTYPE_TIMER
145#define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG
146#define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR
147#define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR
148
149
150#define INTERRUPT(i) { \
151 .level = XCHAL_INT ## i ## _LEVEL, \
152 .inttype = XCHAL_INT ## i ## _TYPE, \
153 }
154
155#define INTERRUPTS { \
156 [0] = INTERRUPT(0), \
157 [1] = INTERRUPT(1), \
158 [2] = INTERRUPT(2), \
159 [3] = INTERRUPT(3), \
160 [4] = INTERRUPT(4), \
161 [5] = INTERRUPT(5), \
162 [6] = INTERRUPT(6), \
163 [7] = INTERRUPT(7), \
164 [8] = INTERRUPT(8), \
165 [9] = INTERRUPT(9), \
166 [10] = INTERRUPT(10), \
167 [11] = INTERRUPT(11), \
168 [12] = INTERRUPT(12), \
169 [13] = INTERRUPT(13), \
170 [14] = INTERRUPT(14), \
171 [15] = INTERRUPT(15), \
172 [16] = INTERRUPT(16), \
173 [17] = INTERRUPT(17), \
174 [18] = INTERRUPT(18), \
175 [19] = INTERRUPT(19), \
176 [20] = INTERRUPT(20), \
177 [21] = INTERRUPT(21), \
178 [22] = INTERRUPT(22), \
179 [23] = INTERRUPT(23), \
180 [24] = INTERRUPT(24), \
181 [25] = INTERRUPT(25), \
182 [26] = INTERRUPT(26), \
183 [27] = INTERRUPT(27), \
184 [28] = INTERRUPT(28), \
185 [29] = INTERRUPT(29), \
186 [30] = INTERRUPT(30), \
187 [31] = INTERRUPT(31), \
188 }
189
190#define TIMERINTS { \
191 [0] = XCHAL_TIMER0_INTERRUPT, \
192 [1] = XCHAL_TIMER1_INTERRUPT, \
193 [2] = XCHAL_TIMER2_INTERRUPT, \
194 }
195
196#define EXTINTS { \
197 [0] = XCHAL_EXTINT0_NUM, \
198 [1] = XCHAL_EXTINT1_NUM, \
199 [2] = XCHAL_EXTINT2_NUM, \
200 [3] = XCHAL_EXTINT3_NUM, \
201 [4] = XCHAL_EXTINT4_NUM, \
202 [5] = XCHAL_EXTINT5_NUM, \
203 [6] = XCHAL_EXTINT6_NUM, \
204 [7] = XCHAL_EXTINT7_NUM, \
205 [8] = XCHAL_EXTINT8_NUM, \
206 [9] = XCHAL_EXTINT9_NUM, \
207 [10] = XCHAL_EXTINT10_NUM, \
208 [11] = XCHAL_EXTINT11_NUM, \
209 [12] = XCHAL_EXTINT12_NUM, \
210 [13] = XCHAL_EXTINT13_NUM, \
211 [14] = XCHAL_EXTINT14_NUM, \
212 [15] = XCHAL_EXTINT15_NUM, \
213 [16] = XCHAL_EXTINT16_NUM, \
214 [17] = XCHAL_EXTINT17_NUM, \
215 [18] = XCHAL_EXTINT18_NUM, \
216 [19] = XCHAL_EXTINT19_NUM, \
217 [20] = XCHAL_EXTINT20_NUM, \
218 [21] = XCHAL_EXTINT21_NUM, \
219 [22] = XCHAL_EXTINT22_NUM, \
220 [23] = XCHAL_EXTINT23_NUM, \
221 [24] = XCHAL_EXTINT24_NUM, \
222 [25] = XCHAL_EXTINT25_NUM, \
223 [26] = XCHAL_EXTINT26_NUM, \
224 [27] = XCHAL_EXTINT27_NUM, \
225 [28] = XCHAL_EXTINT28_NUM, \
226 [29] = XCHAL_EXTINT29_NUM, \
227 [30] = XCHAL_EXTINT30_NUM, \
228 [31] = XCHAL_EXTINT31_NUM, \
229 }
230
231#define EXCEPTIONS_SECTION \
232 .excm_level = XCHAL_EXCM_LEVEL, \
233 .vecbase = XCHAL_VECBASE_RESET_VADDR, \
234 .exception_vector = EXCEPTION_VECTORS
235
236#define INTERRUPTS_SECTION \
237 .ninterrupt = XCHAL_NUM_INTERRUPTS, \
238 .nlevel = XCHAL_NUM_INTLEVELS, \
239 .interrupt_vector = INTERRUPT_VECTORS, \
240 .level_mask = LEVEL_MASKS, \
241 .inttype_mask = INTTYPE_MASKS, \
242 .interrupt = INTERRUPTS, \
243 .nccompare = XCHAL_NUM_TIMERS, \
244 .timerint = TIMERINTS, \
245 .nextint = XCHAL_NUM_EXTINTERRUPTS, \
246 .extint = EXTINTS
247
248#define TLB_TEMPLATE(ways, refill_way_size, way56) { \
249 .nways = ways, \
250 .way_size = { \
251 (refill_way_size), (refill_way_size), \
252 (refill_way_size), (refill_way_size), \
253 4, 2, 2, 1, 1, 1, \
254 }, \
255 .varway56 = (way56), \
256 .nrefillentries = (refill_way_size) * 4, \
257 }
258
259#define ITLB(varway56) \
260 TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56)
261
262#define DTLB(varway56) \
263 TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)
264
265#if XCHAL_HAVE_PTP_MMU
266#define TLB_SECTION \
267 .itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
268 .dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
269#else
270#endif
271
272#if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
273#define REGISTER_CORE(core) \
274 static void __attribute__((constructor)) register_core(void) \
275 { \
276 static XtensaConfigList node = { \
277 .config = &core, \
278 }; \
279 xtensa_register_core(&node); \
280 }
281#else
282#define REGISTER_CORE(core)
283#endif
284
285
286#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
287#define XCHAL_INTLEVEL2_VECTOR_VADDR 0
288#endif
289#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3
290#define XCHAL_INTLEVEL3_VECTOR_VADDR 0
291#endif
292#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4
293#define XCHAL_INTLEVEL4_VECTOR_VADDR 0
294#endif
295#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5
296#define XCHAL_INTLEVEL5_VECTOR_VADDR 0
297#endif
298#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6
299#define XCHAL_INTLEVEL6_VECTOR_VADDR 0
300#endif
301#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7
302#define XCHAL_INTLEVEL7_VECTOR_VADDR 0
303#endif
304
305
306#if XCHAL_NUM_INTERRUPTS <= 0
307#define XCHAL_INT0_LEVEL 0
308#define XCHAL_INT0_TYPE 0
309#endif
310#if XCHAL_NUM_INTERRUPTS <= 1
311#define XCHAL_INT1_LEVEL 0
312#define XCHAL_INT1_TYPE 0
313#endif
314#if XCHAL_NUM_INTERRUPTS <= 2
315#define XCHAL_INT2_LEVEL 0
316#define XCHAL_INT2_TYPE 0
317#endif
318#if XCHAL_NUM_INTERRUPTS <= 3
319#define XCHAL_INT3_LEVEL 0
320#define XCHAL_INT3_TYPE 0
321#endif
322#if XCHAL_NUM_INTERRUPTS <= 4
323#define XCHAL_INT4_LEVEL 0
324#define XCHAL_INT4_TYPE 0
325#endif
326#if XCHAL_NUM_INTERRUPTS <= 5
327#define XCHAL_INT5_LEVEL 0
328#define XCHAL_INT5_TYPE 0
329#endif
330#if XCHAL_NUM_INTERRUPTS <= 6
331#define XCHAL_INT6_LEVEL 0
332#define XCHAL_INT6_TYPE 0
333#endif
334#if XCHAL_NUM_INTERRUPTS <= 7
335#define XCHAL_INT7_LEVEL 0
336#define XCHAL_INT7_TYPE 0
337#endif
338#if XCHAL_NUM_INTERRUPTS <= 8
339#define XCHAL_INT8_LEVEL 0
340#define XCHAL_INT8_TYPE 0
341#endif
342#if XCHAL_NUM_INTERRUPTS <= 9
343#define XCHAL_INT9_LEVEL 0
344#define XCHAL_INT9_TYPE 0
345#endif
346#if XCHAL_NUM_INTERRUPTS <= 10
347#define XCHAL_INT10_LEVEL 0
348#define XCHAL_INT10_TYPE 0
349#endif
350#if XCHAL_NUM_INTERRUPTS <= 11
351#define XCHAL_INT11_LEVEL 0
352#define XCHAL_INT11_TYPE 0
353#endif
354#if XCHAL_NUM_INTERRUPTS <= 12
355#define XCHAL_INT12_LEVEL 0
356#define XCHAL_INT12_TYPE 0
357#endif
358#if XCHAL_NUM_INTERRUPTS <= 13
359#define XCHAL_INT13_LEVEL 0
360#define XCHAL_INT13_TYPE 0
361#endif
362#if XCHAL_NUM_INTERRUPTS <= 14
363#define XCHAL_INT14_LEVEL 0
364#define XCHAL_INT14_TYPE 0
365#endif
366#if XCHAL_NUM_INTERRUPTS <= 15
367#define XCHAL_INT15_LEVEL 0
368#define XCHAL_INT15_TYPE 0
369#endif
370#if XCHAL_NUM_INTERRUPTS <= 16
371#define XCHAL_INT16_LEVEL 0
372#define XCHAL_INT16_TYPE 0
373#endif
374#if XCHAL_NUM_INTERRUPTS <= 17
375#define XCHAL_INT17_LEVEL 0
376#define XCHAL_INT17_TYPE 0
377#endif
378#if XCHAL_NUM_INTERRUPTS <= 18
379#define XCHAL_INT18_LEVEL 0
380#define XCHAL_INT18_TYPE 0
381#endif
382#if XCHAL_NUM_INTERRUPTS <= 19
383#define XCHAL_INT19_LEVEL 0
384#define XCHAL_INT19_TYPE 0
385#endif
386#if XCHAL_NUM_INTERRUPTS <= 20
387#define XCHAL_INT20_LEVEL 0
388#define XCHAL_INT20_TYPE 0
389#endif
390#if XCHAL_NUM_INTERRUPTS <= 21
391#define XCHAL_INT21_LEVEL 0
392#define XCHAL_INT21_TYPE 0
393#endif
394#if XCHAL_NUM_INTERRUPTS <= 22
395#define XCHAL_INT22_LEVEL 0
396#define XCHAL_INT22_TYPE 0
397#endif
398#if XCHAL_NUM_INTERRUPTS <= 23
399#define XCHAL_INT23_LEVEL 0
400#define XCHAL_INT23_TYPE 0
401#endif
402#if XCHAL_NUM_INTERRUPTS <= 24
403#define XCHAL_INT24_LEVEL 0
404#define XCHAL_INT24_TYPE 0
405#endif
406#if XCHAL_NUM_INTERRUPTS <= 25
407#define XCHAL_INT25_LEVEL 0
408#define XCHAL_INT25_TYPE 0
409#endif
410#if XCHAL_NUM_INTERRUPTS <= 26
411#define XCHAL_INT26_LEVEL 0
412#define XCHAL_INT26_TYPE 0
413#endif
414#if XCHAL_NUM_INTERRUPTS <= 27
415#define XCHAL_INT27_LEVEL 0
416#define XCHAL_INT27_TYPE 0
417#endif
418#if XCHAL_NUM_INTERRUPTS <= 28
419#define XCHAL_INT28_LEVEL 0
420#define XCHAL_INT28_TYPE 0
421#endif
422#if XCHAL_NUM_INTERRUPTS <= 29
423#define XCHAL_INT29_LEVEL 0
424#define XCHAL_INT29_TYPE 0
425#endif
426#if XCHAL_NUM_INTERRUPTS <= 30
427#define XCHAL_INT30_LEVEL 0
428#define XCHAL_INT30_TYPE 0
429#endif
430#if XCHAL_NUM_INTERRUPTS <= 31
431#define XCHAL_INT31_LEVEL 0
432#define XCHAL_INT31_TYPE 0
433#endif
434
435
436#if XCHAL_NUM_EXTINTERRUPTS <= 0
437#define XCHAL_EXTINT0_NUM 0
438#endif
439#if XCHAL_NUM_EXTINTERRUPTS <= 1
440#define XCHAL_EXTINT1_NUM 0
441#endif
442#if XCHAL_NUM_EXTINTERRUPTS <= 2
443#define XCHAL_EXTINT2_NUM 0
444#endif
445#if XCHAL_NUM_EXTINTERRUPTS <= 3
446#define XCHAL_EXTINT3_NUM 0
447#endif
448#if XCHAL_NUM_EXTINTERRUPTS <= 4
449#define XCHAL_EXTINT4_NUM 0
450#endif
451#if XCHAL_NUM_EXTINTERRUPTS <= 5
452#define XCHAL_EXTINT5_NUM 0
453#endif
454#if XCHAL_NUM_EXTINTERRUPTS <= 6
455#define XCHAL_EXTINT6_NUM 0
456#endif
457#if XCHAL_NUM_EXTINTERRUPTS <= 7
458#define XCHAL_EXTINT7_NUM 0
459#endif
460#if XCHAL_NUM_EXTINTERRUPTS <= 8
461#define XCHAL_EXTINT8_NUM 0
462#endif
463#if XCHAL_NUM_EXTINTERRUPTS <= 9
464#define XCHAL_EXTINT9_NUM 0
465#endif
466#if XCHAL_NUM_EXTINTERRUPTS <= 10
467#define XCHAL_EXTINT10_NUM 0
468#endif
469#if XCHAL_NUM_EXTINTERRUPTS <= 11
470#define XCHAL_EXTINT11_NUM 0
471#endif
472#if XCHAL_NUM_EXTINTERRUPTS <= 12
473#define XCHAL_EXTINT12_NUM 0
474#endif
475#if XCHAL_NUM_EXTINTERRUPTS <= 13
476#define XCHAL_EXTINT13_NUM 0
477#endif
478#if XCHAL_NUM_EXTINTERRUPTS <= 14
479#define XCHAL_EXTINT14_NUM 0
480#endif
481#if XCHAL_NUM_EXTINTERRUPTS <= 15
482#define XCHAL_EXTINT15_NUM 0
483#endif
484#if XCHAL_NUM_EXTINTERRUPTS <= 16
485#define XCHAL_EXTINT16_NUM 0
486#endif
487#if XCHAL_NUM_EXTINTERRUPTS <= 17
488#define XCHAL_EXTINT17_NUM 0
489#endif
490#if XCHAL_NUM_EXTINTERRUPTS <= 18
491#define XCHAL_EXTINT18_NUM 0
492#endif
493#if XCHAL_NUM_EXTINTERRUPTS <= 19
494#define XCHAL_EXTINT19_NUM 0
495#endif
496#if XCHAL_NUM_EXTINTERRUPTS <= 20
497#define XCHAL_EXTINT20_NUM 0
498#endif
499#if XCHAL_NUM_EXTINTERRUPTS <= 21
500#define XCHAL_EXTINT21_NUM 0
501#endif
502#if XCHAL_NUM_EXTINTERRUPTS <= 22
503#define XCHAL_EXTINT22_NUM 0
504#endif
505#if XCHAL_NUM_EXTINTERRUPTS <= 23
506#define XCHAL_EXTINT23_NUM 0
507#endif
508#if XCHAL_NUM_EXTINTERRUPTS <= 24
509#define XCHAL_EXTINT24_NUM 0
510#endif
511#if XCHAL_NUM_EXTINTERRUPTS <= 25
512#define XCHAL_EXTINT25_NUM 0
513#endif
514#if XCHAL_NUM_EXTINTERRUPTS <= 26
515#define XCHAL_EXTINT26_NUM 0
516#endif
517#if XCHAL_NUM_EXTINTERRUPTS <= 27
518#define XCHAL_EXTINT27_NUM 0
519#endif
520#if XCHAL_NUM_EXTINTERRUPTS <= 28
521#define XCHAL_EXTINT28_NUM 0
522#endif
523#if XCHAL_NUM_EXTINTERRUPTS <= 29
524#define XCHAL_EXTINT29_NUM 0
525#endif
526#if XCHAL_NUM_EXTINTERRUPTS <= 30
527#define XCHAL_EXTINT30_NUM 0
528#endif
529#if XCHAL_NUM_EXTINTERRUPTS <= 31
530#define XCHAL_EXTINT31_NUM 0
531#endif
532
533
534#define XTHAL_TIMER_UNCONFIGURED 0