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exec: let cpu_watchpoint_insert accept larger watchpoints
[qemu.git] / target-xtensa / translate.c
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2328826b
MF		 1/*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <stdio.h>
32
33#include "cpu.h"
34#include "exec-all.h"
35#include "disas.h"
36#include "tcg-op.h"
37#include "qemu-log.h"
1ddeaa5d 38#include "sysemu.h"
2328826b 39
dedc5eae
MF		 40#include "helpers.h"
41#define GEN_HELPER 1
42#include "helpers.h"
43
44typedef struct DisasContext {
45 const XtensaConfig *config;
46 TranslationBlock *tb;
47 uint32_t pc;
48 uint32_t next_pc;
f0a548b9
MF		 49 int cring;
50 int ring;
797d780b
MF		 51 uint32_t lbeg;
52 uint32_t lend;
6ad6dbf7 53 TCGv_i32 litbase;
dedc5eae
MF		 54 int is_jmp;
55 int singlestep_enabled;
3580ecad
MF		 56
57 bool sar_5bit;
58 bool sar_m32_5bit;
59 bool sar_m32_allocated;
60 TCGv_i32 sar_m32;
b994e91b
MF		 61
62 uint32_t ccount_delta;
772177c1 63 unsigned used_window;
e61dc8f7
MF		 64
65 bool debug;
35b5c044
MF		 66 bool icount;
67 TCGv_i32 next_icount;
dedc5eae
MF		 68} DisasContext;
69
70static TCGv_ptr cpu_env;
71static TCGv_i32 cpu_pc;
72static TCGv_i32 cpu_R[16];
2af3da91
MF		 73static TCGv_i32 cpu_SR[256];
74static TCGv_i32 cpu_UR[256];
dedc5eae
MF		 75
76#include "gen-icount.h"
2328826b 77
2af3da91 78static const char * const sregnames[256] = {
797d780b
MF		 79 [LBEG] = "LBEG",
80 [LEND] = "LEND",
81 [LCOUNT] = "LCOUNT",
3580ecad 82 [SAR] = "SAR",
4dd85b6b 83 [BR] = "BR",
6ad6dbf7 84 [LITBASE] = "LITBASE",
809377aa 85 [SCOMPARE1] = "SCOMPARE1",
6825b6c3
MF		 86 [ACCLO] = "ACCLO",
87 [ACCHI] = "ACCHI",
88 [MR] = "MR0",
89 [MR + 1] = "MR1",
90 [MR + 2] = "MR2",
91 [MR + 3] = "MR3",
553e44f9
MF		 92 [WINDOW_BASE] = "WINDOW_BASE",
93 [WINDOW_START] = "WINDOW_START",
b67ea0cd
MF		 94 [PTEVADDR] = "PTEVADDR",
95 [RASID] = "RASID",
96 [ITLBCFG] = "ITLBCFG",
97 [DTLBCFG] = "DTLBCFG",
e61dc8f7
MF		 98 [IBREAKENABLE] = "IBREAKENABLE",
99 [IBREAKA] = "IBREAKA0",
100 [IBREAKA + 1] = "IBREAKA1",
40643d7c 101 [EPC1] = "EPC1",
b994e91b
MF		 102 [EPC1 + 1] = "EPC2",
103 [EPC1 + 2] = "EPC3",
104 [EPC1 + 3] = "EPC4",
105 [EPC1 + 4] = "EPC5",
106 [EPC1 + 5] = "EPC6",
107 [EPC1 + 6] = "EPC7",
40643d7c 108 [DEPC] = "DEPC",
b994e91b
MF		 109 [EPS2] = "EPS2",
110 [EPS2 + 1] = "EPS3",
111 [EPS2 + 2] = "EPS4",
112 [EPS2 + 3] = "EPS5",
113 [EPS2 + 4] = "EPS6",
114 [EPS2 + 5] = "EPS7",
40643d7c 115 [EXCSAVE1] = "EXCSAVE1",
b994e91b
MF		 116 [EXCSAVE1 + 1] = "EXCSAVE2",
117 [EXCSAVE1 + 2] = "EXCSAVE3",
118 [EXCSAVE1 + 3] = "EXCSAVE4",
119 [EXCSAVE1 + 4] = "EXCSAVE5",
120 [EXCSAVE1 + 5] = "EXCSAVE6",
121 [EXCSAVE1 + 6] = "EXCSAVE7",
f3df4c04 122 [CPENABLE] = "CPENABLE",
b994e91b
MF		 123 [INTSET] = "INTSET",
124 [INTCLEAR] = "INTCLEAR",
125 [INTENABLE] = "INTENABLE",
f0a548b9 126 [PS] = "PS",
97836cee 127 [VECBASE] = "VECBASE",
40643d7c 128 [EXCCAUSE] = "EXCCAUSE",
ab58c5b4 129 [DEBUGCAUSE] = "DEBUGCAUSE",
b994e91b 130 [CCOUNT] = "CCOUNT",
f3df4c04 131 [PRID] = "PRID",
35b5c044
MF		 132 [ICOUNT] = "ICOUNT",
133 [ICOUNTLEVEL] = "ICOUNTLEVEL",
40643d7c 134 [EXCVADDR] = "EXCVADDR",
b994e91b
MF		 135 [CCOMPARE] = "CCOMPARE0",
136 [CCOMPARE + 1] = "CCOMPARE1",
137 [CCOMPARE + 2] = "CCOMPARE2",
2af3da91
MF		 138};
139
140static const char * const uregnames[256] = {
141 [THREADPTR] = "THREADPTR",
142 [FCR] = "FCR",
143 [FSR] = "FSR",
144};
145
2328826b
MF		 146void xtensa_translate_init(void)
147{
dedc5eae
MF		 148 static const char * const regnames[] = {
149 "ar0", "ar1", "ar2", "ar3",
150 "ar4", "ar5", "ar6", "ar7",
151 "ar8", "ar9", "ar10", "ar11",
152 "ar12", "ar13", "ar14", "ar15",
153 };
154 int i;
155
156 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
157 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
158 offsetof(CPUState, pc), "pc");
159
160 for (i = 0; i < 16; i++) {
161 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
162 offsetof(CPUState, regs[i]),
163 regnames[i]);
164 }
2af3da91
MF		 165
166 for (i = 0; i < 256; ++i) {
167 if (sregnames[i]) {
168 cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
169 offsetof(CPUState, sregs[i]),
170 sregnames[i]);
171 }
172 }
173
174 for (i = 0; i < 256; ++i) {
175 if (uregnames[i]) {
176 cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
177 offsetof(CPUState, uregs[i]),
178 uregnames[i]);
179 }
180 }
dedc5eae
MF		 181#define GEN_HELPER 2
182#include "helpers.h"
183}
184
b67ea0cd
MF		 185static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
186{
187 return xtensa_option_bits_enabled(dc->config, opt);
188}
189
dedc5eae
MF		 190static inline bool option_enabled(DisasContext *dc, int opt)
191{
192 return xtensa_option_enabled(dc->config, opt);
193}
194
6ad6dbf7
MF		 195static void init_litbase(DisasContext *dc)
196{
197 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
198 dc->litbase = tcg_temp_local_new_i32();
199 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
200 }
201}
202
203static void reset_litbase(DisasContext *dc)
204{
205 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
206 tcg_temp_free(dc->litbase);
207 }
208}
209
3580ecad
MF		 210static void init_sar_tracker(DisasContext *dc)
211{
212 dc->sar_5bit = false;
213 dc->sar_m32_5bit = false;
214 dc->sar_m32_allocated = false;
215}
216
217static void reset_sar_tracker(DisasContext *dc)
218{
219 if (dc->sar_m32_allocated) {
220 tcg_temp_free(dc->sar_m32);
221 }
222}
223
224static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
225{
226 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
227 if (dc->sar_m32_5bit) {
228 tcg_gen_discard_i32(dc->sar_m32);
229 }
230 dc->sar_5bit = true;
231 dc->sar_m32_5bit = false;
232}
233
234static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
235{
236 TCGv_i32 tmp = tcg_const_i32(32);
237 if (!dc->sar_m32_allocated) {
238 dc->sar_m32 = tcg_temp_local_new_i32();
239 dc->sar_m32_allocated = true;
240 }
241 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
242 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
243 dc->sar_5bit = false;
244 dc->sar_m32_5bit = true;
245 tcg_temp_free(tmp);
246}
247
b994e91b
MF		 248static void gen_advance_ccount(DisasContext *dc)
249{
250 if (dc->ccount_delta > 0) {
251 TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
252 dc->ccount_delta = 0;
253 gen_helper_advance_ccount(tmp);
254 tcg_temp_free(tmp);
255 }
256}
257
772177c1
MF		 258static void reset_used_window(DisasContext *dc)
259{
260 dc->used_window = 0;
261}
262
b994e91b 263static void gen_exception(DisasContext *dc, int excp)
dedc5eae
MF		 264{
265 TCGv_i32 tmp = tcg_const_i32(excp);
b994e91b 266 gen_advance_ccount(dc);
dedc5eae
MF		 267 gen_helper_exception(tmp);
268 tcg_temp_free(tmp);
269}
270
40643d7c
MF		 271static void gen_exception_cause(DisasContext *dc, uint32_t cause)
272{
273 TCGv_i32 tpc = tcg_const_i32(dc->pc);
274 TCGv_i32 tcause = tcg_const_i32(cause);
b994e91b 275 gen_advance_ccount(dc);
40643d7c
MF		 276 gen_helper_exception_cause(tpc, tcause);
277 tcg_temp_free(tpc);
278 tcg_temp_free(tcause);
6b814719
MF		 279 if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
280 cause == SYSCALL_CAUSE) {
281 dc->is_jmp = DISAS_UPDATE;
282 }
40643d7c
MF		 283}
284
5b4e481b
MF		 285static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
286 TCGv_i32 vaddr)
287{
288 TCGv_i32 tpc = tcg_const_i32(dc->pc);
289 TCGv_i32 tcause = tcg_const_i32(cause);
b994e91b 290 gen_advance_ccount(dc);
5b4e481b
MF		 291 gen_helper_exception_cause_vaddr(tpc, tcause, vaddr);
292 tcg_temp_free(tpc);
293 tcg_temp_free(tcause);
294}
295
e61dc8f7
MF		 296static void gen_debug_exception(DisasContext *dc, uint32_t cause)
297{
298 TCGv_i32 tpc = tcg_const_i32(dc->pc);
299 TCGv_i32 tcause = tcg_const_i32(cause);
300 gen_advance_ccount(dc);
301 gen_helper_debug_exception(tpc, tcause);
302 tcg_temp_free(tpc);
303 tcg_temp_free(tcause);
304 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
305 dc->is_jmp = DISAS_UPDATE;
306 }
307}
308
40643d7c
MF		 309static void gen_check_privilege(DisasContext *dc)
310{
311 if (dc->cring) {
312 gen_exception_cause(dc, PRIVILEGED_CAUSE);
6b814719 313 dc->is_jmp = DISAS_UPDATE;
40643d7c
MF		 314 }
315}
316
dedc5eae
MF		 317static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
318{
319 tcg_gen_mov_i32(cpu_pc, dest);
35b5c044
MF		 320 gen_advance_ccount(dc);
321 if (dc->icount) {
322 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
323 }
dedc5eae 324 if (dc->singlestep_enabled) {
b994e91b 325 gen_exception(dc, EXCP_DEBUG);
dedc5eae
MF		 326 } else {
327 if (slot >= 0) {
328 tcg_gen_goto_tb(slot);
329 tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);
330 } else {
331 tcg_gen_exit_tb(0);
332 }
333 }
334 dc->is_jmp = DISAS_UPDATE;
335}
336
67882fd1
MF		 337static void gen_jump(DisasContext *dc, TCGv dest)
338{
339 gen_jump_slot(dc, dest, -1);
340}
341
dedc5eae
MF		 342static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
343{
344 TCGv_i32 tmp = tcg_const_i32(dest);
345 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
346 slot = -1;
347 }
348 gen_jump_slot(dc, tmp, slot);
349 tcg_temp_free(tmp);
350}
351
553e44f9
MF		 352static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
353 int slot)
354{
355 TCGv_i32 tcallinc = tcg_const_i32(callinc);
356
357 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
358 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
359 tcg_temp_free(tcallinc);
360 tcg_gen_movi_i32(cpu_R[callinc << 2],
361 (callinc << 30) | (dc->next_pc & 0x3fffffff));
362 gen_jump_slot(dc, dest, slot);
363}
364
365static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
366{
367 gen_callw_slot(dc, callinc, dest, -1);
368}
369
370static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
371{
372 TCGv_i32 tmp = tcg_const_i32(dest);
373 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
374 slot = -1;
375 }
376 gen_callw_slot(dc, callinc, tmp, slot);
377 tcg_temp_free(tmp);
378}
379
797d780b
MF		 380static bool gen_check_loop_end(DisasContext *dc, int slot)
381{
382 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
383 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
384 dc->next_pc == dc->lend) {
385 int label = gen_new_label();
386
387 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
388 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
389 gen_jumpi(dc, dc->lbeg, slot);
390 gen_set_label(label);
391 gen_jumpi(dc, dc->next_pc, -1);
392 return true;
393 }
394 return false;
395}
396
397static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
398{
399 if (!gen_check_loop_end(dc, slot)) {
400 gen_jumpi(dc, dc->next_pc, slot);
401 }
402}
403
bd57fb91
MF		 404static void gen_brcond(DisasContext *dc, TCGCond cond,
405 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
406{
407 int label = gen_new_label();
408
409 tcg_gen_brcond_i32(cond, t0, t1, label);
797d780b 410 gen_jumpi_check_loop_end(dc, 0);
bd57fb91
MF		 411 gen_set_label(label);
412 gen_jumpi(dc, dc->pc + offset, 1);
413}
414
415static void gen_brcondi(DisasContext *dc, TCGCond cond,
416 TCGv_i32 t0, uint32_t t1, uint32_t offset)
417{
418 TCGv_i32 tmp = tcg_const_i32(t1);
419 gen_brcond(dc, cond, t0, tmp, offset);
420 tcg_temp_free(tmp);
421}
422
b994e91b
MF		 423static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
424{
425 gen_advance_ccount(dc);
426 tcg_gen_mov_i32(d, cpu_SR[sr]);
427}
428
b67ea0cd
MF		 429static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
430{
431 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
432 tcg_gen_or_i32(d, d, cpu_SR[sr]);
433 tcg_gen_andi_i32(d, d, 0xfffffffc);
434}
435
b8132eff
MF		 436static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
437{
438 static void (* const rsr_handler[256])(DisasContext *dc,
439 TCGv_i32 d, uint32_t sr) = {
b994e91b 440 [CCOUNT] = gen_rsr_ccount,
b67ea0cd 441 [PTEVADDR] = gen_rsr_ptevaddr,
b8132eff
MF		 442 };
443
444 if (sregnames[sr]) {
445 if (rsr_handler[sr]) {
446 rsr_handler[sr](dc, d, sr);
447 } else {
448 tcg_gen_mov_i32(d, cpu_SR[sr]);
449 }
450 } else {
451 qemu_log("RSR %d not implemented, ", sr);
452 }
453}
454
797d780b
MF		 455static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
456{
457 gen_helper_wsr_lbeg(s);
458}
459
460static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
461{
462 gen_helper_wsr_lend(s);
463}
464
3580ecad
MF		 465static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
466{
467 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
468 if (dc->sar_m32_5bit) {
469 tcg_gen_discard_i32(dc->sar_m32);
470 }
471 dc->sar_5bit = false;
472 dc->sar_m32_5bit = false;
473}
474
4dd85b6b
MF		 475static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
476{
477 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
478}
479
6ad6dbf7
MF		 480static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
481{
482 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
483 /* This can change tb->flags, so exit tb */
484 gen_jumpi_check_loop_end(dc, -1);
485}
486
6825b6c3
MF		 487static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
488{
489 tcg_gen_ext8s_i32(cpu_SR[sr], s);
490}
491
553e44f9
MF		 492static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
493{
494 gen_helper_wsr_windowbase(v);
772177c1
MF		 495 reset_used_window(dc);
496}
497
498static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
499{
53a72dfd 500 tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
772177c1 501 reset_used_window(dc);
553e44f9
MF		 502}
503
b67ea0cd
MF		 504static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
505{
506 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
507}
508
509static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
510{
511 gen_helper_wsr_rasid(v);
512 /* This can change tb->flags, so exit tb */
513 gen_jumpi_check_loop_end(dc, -1);
514}
515
516static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
517{
518 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
519}
520
e61dc8f7
MF		 521static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
522{
523 gen_helper_wsr_ibreakenable(v);
524 gen_jumpi_check_loop_end(dc, 0);
525}
526
527static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
528{
529 unsigned id = sr - IBREAKA;
530
531 if (id < dc->config->nibreak) {
532 TCGv_i32 tmp = tcg_const_i32(id);
533 gen_helper_wsr_ibreaka(tmp, v);
534 tcg_temp_free(tmp);
535 gen_jumpi_check_loop_end(dc, 0);
536 }
537}
538
b994e91b
MF		 539static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
540{
541 tcg_gen_andi_i32(cpu_SR[sr], v,
542 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
543 gen_helper_check_interrupts(cpu_env);
544 gen_jumpi_check_loop_end(dc, 0);
545}
546
547static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
548{
549 TCGv_i32 tmp = tcg_temp_new_i32();
550
551 tcg_gen_andi_i32(tmp, v,
552 dc->config->inttype_mask[INTTYPE_EDGE] |
553 dc->config->inttype_mask[INTTYPE_NMI] |
554 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
555 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
556 tcg_temp_free(tmp);
557 gen_helper_check_interrupts(cpu_env);
558}
559
560static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
561{
562 tcg_gen_mov_i32(cpu_SR[sr], v);
563 gen_helper_check_interrupts(cpu_env);
564 gen_jumpi_check_loop_end(dc, 0);
565}
566
f0a548b9
MF		 567static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
568{
569 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
570 PS_UM | PS_EXCM | PS_INTLEVEL;
571
572 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
573 mask |= PS_RING;
574 }
575 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
772177c1 576 reset_used_window(dc);
b994e91b
MF		 577 gen_helper_check_interrupts(cpu_env);
578 /* This can change mmu index and tb->flags, so exit tb */
797d780b 579 gen_jumpi_check_loop_end(dc, -1);
f0a548b9
MF		 580}
581
ab58c5b4
MF		 582static void gen_wsr_debugcause(DisasContext *dc, uint32_t sr, TCGv_i32 v)
583{
584}
585
f3df4c04
MF		 586static void gen_wsr_prid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
587{
588}
589
35b5c044
MF		 590static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
591{
592 if (dc->icount) {
593 tcg_gen_mov_i32(dc->next_icount, v);
594 } else {
595 tcg_gen_mov_i32(cpu_SR[sr], v);
596 }
597}
598
599static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
600{
601 tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
602 /* This can change tb->flags, so exit tb */
603 gen_jumpi_check_loop_end(dc, -1);
604}
605
b994e91b
MF		 606static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
607{
608 uint32_t id = sr - CCOMPARE;
609 if (id < dc->config->nccompare) {
610 uint32_t int_bit = 1 << dc->config->timerint[id];
611 gen_advance_ccount(dc);
612 tcg_gen_mov_i32(cpu_SR[sr], v);
613 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
614 gen_helper_check_interrupts(cpu_env);
615 }
616}
617
b8132eff
MF		 618static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
619{
620 static void (* const wsr_handler[256])(DisasContext *dc,
621 uint32_t sr, TCGv_i32 v) = {
797d780b
MF		 622 [LBEG] = gen_wsr_lbeg,
623 [LEND] = gen_wsr_lend,
3580ecad 624 [SAR] = gen_wsr_sar,
4dd85b6b 625 [BR] = gen_wsr_br,
6ad6dbf7 626 [LITBASE] = gen_wsr_litbase,
6825b6c3 627 [ACCHI] = gen_wsr_acchi,
553e44f9 628 [WINDOW_BASE] = gen_wsr_windowbase,
772177c1 629 [WINDOW_START] = gen_wsr_windowstart,
b67ea0cd
MF		 630 [PTEVADDR] = gen_wsr_ptevaddr,
631 [RASID] = gen_wsr_rasid,
632 [ITLBCFG] = gen_wsr_tlbcfg,
633 [DTLBCFG] = gen_wsr_tlbcfg,
e61dc8f7
MF		 634 [IBREAKENABLE] = gen_wsr_ibreakenable,
635 [IBREAKA] = gen_wsr_ibreaka,
636 [IBREAKA + 1] = gen_wsr_ibreaka,
b994e91b
MF		 637 [INTSET] = gen_wsr_intset,
638 [INTCLEAR] = gen_wsr_intclear,
639 [INTENABLE] = gen_wsr_intenable,
f0a548b9 640 [PS] = gen_wsr_ps,
ab58c5b4 641 [DEBUGCAUSE] = gen_wsr_debugcause,
f3df4c04 642 [PRID] = gen_wsr_prid,
35b5c044
MF		 643 [ICOUNT] = gen_wsr_icount,
644 [ICOUNTLEVEL] = gen_wsr_icountlevel,
b994e91b
MF		 645 [CCOMPARE] = gen_wsr_ccompare,
646 [CCOMPARE + 1] = gen_wsr_ccompare,
647 [CCOMPARE + 2] = gen_wsr_ccompare,
b8132eff
MF		 648 };
649
650 if (sregnames[sr]) {
651 if (wsr_handler[sr]) {
652 wsr_handler[sr](dc, sr, s);
653 } else {
654 tcg_gen_mov_i32(cpu_SR[sr], s);
655 }
656 } else {
657 qemu_log("WSR %d not implemented, ", sr);
658 }
659}
660
5b4e481b
MF		 661static void gen_load_store_alignment(DisasContext *dc, int shift,
662 TCGv_i32 addr, bool no_hw_alignment)
663{
664 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
665 tcg_gen_andi_i32(addr, addr, ~0 << shift);
666 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
667 no_hw_alignment) {
668 int label = gen_new_label();
669 TCGv_i32 tmp = tcg_temp_new_i32();
670 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
671 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
672 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
673 gen_set_label(label);
674 tcg_temp_free(tmp);
675 }
676}
677
b994e91b
MF		 678static void gen_waiti(DisasContext *dc, uint32_t imm4)
679{
680 TCGv_i32 pc = tcg_const_i32(dc->next_pc);
681 TCGv_i32 intlevel = tcg_const_i32(imm4);
682 gen_advance_ccount(dc);
683 gen_helper_waiti(pc, intlevel);
684 tcg_temp_free(pc);
685 tcg_temp_free(intlevel);
686}
687
772177c1
MF		 688static void gen_window_check1(DisasContext *dc, unsigned r1)
689{
690 if (dc->tb->flags & XTENSA_TBFLAG_EXCM) {
691 return;
692 }
693 if (option_enabled(dc, XTENSA_OPTION_WINDOWED_REGISTER) &&
694 r1 / 4 > dc->used_window) {
695 TCGv_i32 pc = tcg_const_i32(dc->pc);
696 TCGv_i32 w = tcg_const_i32(r1 / 4);
697
698 dc->used_window = r1 / 4;
699 gen_advance_ccount(dc);
700 gen_helper_window_check(pc, w);
701
702 tcg_temp_free(w);
703 tcg_temp_free(pc);
704 }
705}
706
707static void gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
708{
709 gen_window_check1(dc, r1 > r2 ? r1 : r2);
710}
711
712static void gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
713 unsigned r3)
714{
715 gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
716}
717
6825b6c3
MF		 718static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
719{
720 TCGv_i32 m = tcg_temp_new_i32();
721
722 if (hi) {
723 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
724 } else {
725 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
726 }
727 return m;
728}
729
dedc5eae
MF		 730static void disas_xtensa_insn(DisasContext *dc)
731{
b67ea0cd
MF		 732#define HAS_OPTION_BITS(opt) do { \
733 if (!option_bits_enabled(dc, opt)) { \
734 qemu_log("Option is not enabled %s:%d\n", \
735 __FILE__, __LINE__); \
dedc5eae
MF		 736 goto invalid_opcode; \
737 } \
738 } while (0)
739
b67ea0cd
MF		 740#define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
741
91a5bb76
MF		 742#define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
743#define RESERVED() do { \
744 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
745 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
746 goto invalid_opcode; \
747 } while (0)
748
749
dedc5eae
MF		 750#ifdef TARGET_WORDS_BIGENDIAN
751#define OP0 (((b0) & 0xf0) >> 4)
752#define OP1 (((b2) & 0xf0) >> 4)
753#define OP2 ((b2) & 0xf)
754#define RRR_R ((b1) & 0xf)
755#define RRR_S (((b1) & 0xf0) >> 4)
756#define RRR_T ((b0) & 0xf)
757#else
758#define OP0 (((b0) & 0xf))
759#define OP1 (((b2) & 0xf))
760#define OP2 (((b2) & 0xf0) >> 4)
761#define RRR_R (((b1) & 0xf0) >> 4)
762#define RRR_S (((b1) & 0xf))
763#define RRR_T (((b0) & 0xf0) >> 4)
764#endif
6825b6c3
MF		 765#define RRR_X ((RRR_R & 0x4) >> 2)
766#define RRR_Y ((RRR_T & 0x4) >> 2)
767#define RRR_W (RRR_R & 0x3)
dedc5eae
MF		 768
769#define RRRN_R RRR_R
770#define RRRN_S RRR_S
771#define RRRN_T RRR_T
772
773#define RRI8_R RRR_R
774#define RRI8_S RRR_S
775#define RRI8_T RRR_T
776#define RRI8_IMM8 (b2)
777#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
778
779#ifdef TARGET_WORDS_BIGENDIAN
780#define RI16_IMM16 (((b1) << 8) | (b2))
781#else
782#define RI16_IMM16 (((b2) << 8) | (b1))
783#endif
784
785#ifdef TARGET_WORDS_BIGENDIAN
786#define CALL_N (((b0) & 0xc) >> 2)
787#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
788#else
789#define CALL_N (((b0) & 0x30) >> 4)
790#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
791#endif
792#define CALL_OFFSET_SE \
793 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
794
795#define CALLX_N CALL_N
796#ifdef TARGET_WORDS_BIGENDIAN
797#define CALLX_M ((b0) & 0x3)
798#else
799#define CALLX_M (((b0) & 0xc0) >> 6)
800#endif
801#define CALLX_S RRR_S
802
803#define BRI12_M CALLX_M
804#define BRI12_S RRR_S
805#ifdef TARGET_WORDS_BIGENDIAN
806#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
807#else
808#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
809#endif
810#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
811
812#define BRI8_M BRI12_M
813#define BRI8_R RRI8_R
814#define BRI8_S RRI8_S
815#define BRI8_IMM8 RRI8_IMM8
816#define BRI8_IMM8_SE RRI8_IMM8_SE
817
818#define RSR_SR (b1)
819
820 uint8_t b0 = ldub_code(dc->pc);
821 uint8_t b1 = ldub_code(dc->pc + 1);
a044ec2a 822 uint8_t b2 = 0;
dedc5eae 823
bd57fb91
MF		 824 static const uint32_t B4CONST[] = {
825 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
826 };
827
828 static const uint32_t B4CONSTU[] = {
829 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
830 };
831
dedc5eae
MF		 832 if (OP0 >= 8) {
833 dc->next_pc = dc->pc + 2;
834 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
835 } else {
836 dc->next_pc = dc->pc + 3;
a044ec2a 837 b2 = ldub_code(dc->pc + 2);
dedc5eae
MF		 838 }
839
840 switch (OP0) {
841 case 0: /*QRST*/
842 switch (OP1) {
843 case 0: /*RST0*/
844 switch (OP2) {
845 case 0: /*ST0*/
846 if ((RRR_R & 0xc) == 0x8) {
847 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
848 }
849
850 switch (RRR_R) {
851 case 0: /*SNM0*/
5da4a6a8
MF		 852 switch (CALLX_M) {
853 case 0: /*ILL*/
40643d7c 854 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
5da4a6a8
MF		 855 break;
856
857 case 1: /*reserved*/
91a5bb76 858 RESERVED();
5da4a6a8
MF		 859 break;
860
861 case 2: /*JR*/
862 switch (CALLX_N) {
863 case 0: /*RET*/
864 case 2: /*JX*/
772177c1 865 gen_window_check1(dc, CALLX_S);
5da4a6a8
MF		 866 gen_jump(dc, cpu_R[CALLX_S]);
867 break;
868
869 case 1: /*RETWw*/
870 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 871 {
872 TCGv_i32 tmp = tcg_const_i32(dc->pc);
b994e91b 873 gen_advance_ccount(dc);
553e44f9
MF		 874 gen_helper_retw(tmp, tmp);
875 gen_jump(dc, tmp);
876 tcg_temp_free(tmp);
877 }
5da4a6a8
MF		 878 break;
879
880 case 3: /*reserved*/
91a5bb76 881 RESERVED();
5da4a6a8
MF		 882 break;
883 }
884 break;
885
886 case 3: /*CALLX*/
772177c1 887 gen_window_check2(dc, CALLX_S, CALLX_N << 2);
5da4a6a8
MF		 888 switch (CALLX_N) {
889 case 0: /*CALLX0*/
890 {
891 TCGv_i32 tmp = tcg_temp_new_i32();
892 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
893 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
894 gen_jump(dc, tmp);
895 tcg_temp_free(tmp);
896 }
897 break;
898
899 case 1: /*CALLX4w*/
900 case 2: /*CALLX8w*/
901 case 3: /*CALLX12w*/
902 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 903 {
904 TCGv_i32 tmp = tcg_temp_new_i32();
905
906 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
907 gen_callw(dc, CALLX_N, tmp);
908 tcg_temp_free(tmp);
909 }
5da4a6a8
MF		 910 break;
911 }
912 break;
913 }
dedc5eae
MF		 914 break;
915
916 case 1: /*MOVSPw*/
917 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
772177c1 918 gen_window_check2(dc, RRR_T, RRR_S);
553e44f9
MF		 919 {
920 TCGv_i32 pc = tcg_const_i32(dc->pc);
b994e91b 921 gen_advance_ccount(dc);
553e44f9
MF		 922 gen_helper_movsp(pc);
923 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
924 tcg_temp_free(pc);
925 }
dedc5eae
MF		 926 break;
927
928 case 2: /*SYNC*/
28067b22
MF		 929 switch (RRR_T) {
930 case 0: /*ISYNC*/
931 break;
932
933 case 1: /*RSYNC*/
934 break;
935
936 case 2: /*ESYNC*/
937 break;
938
939 case 3: /*DSYNC*/
940 break;
941
942 case 8: /*EXCW*/
943 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
944 break;
945
946 case 12: /*MEMW*/
947 break;
948
949 case 13: /*EXTW*/
950 break;
951
952 case 15: /*NOP*/
953 break;
954
955 default: /*reserved*/
956 RESERVED();
957 break;
958 }
91a5bb76
MF		 959 break;
960
961 case 3: /*RFEIx*/
40643d7c
MF		 962 switch (RRR_T) {
963 case 0: /*RFETx*/
964 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
965 switch (RRR_S) {
966 case 0: /*RFEx*/
967 gen_check_privilege(dc);
968 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
b994e91b 969 gen_helper_check_interrupts(cpu_env);
40643d7c
MF		 970 gen_jump(dc, cpu_SR[EPC1]);
971 break;
972
973 case 1: /*RFUEx*/
974 RESERVED();
975 break;
976
977 case 2: /*RFDEx*/
978 gen_check_privilege(dc);
979 gen_jump(dc, cpu_SR[
980 dc->config->ndepc ? DEPC : EPC1]);
981 break;
982
983 case 4: /*RFWOw*/
984 case 5: /*RFWUw*/
985 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 986 gen_check_privilege(dc);
987 {
988 TCGv_i32 tmp = tcg_const_i32(1);
989
990 tcg_gen_andi_i32(
991 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
992 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
993
994 if (RRR_S == 4) {
995 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
996 cpu_SR[WINDOW_START], tmp);
997 } else {
998 tcg_gen_or_i32(cpu_SR[WINDOW_START],
999 cpu_SR[WINDOW_START], tmp);
1000 }
1001
1002 gen_helper_restore_owb();
b994e91b 1003 gen_helper_check_interrupts(cpu_env);
553e44f9
MF		 1004 gen_jump(dc, cpu_SR[EPC1]);
1005
1006 tcg_temp_free(tmp);
1007 }
40643d7c
MF		 1008 break;
1009
1010 default: /*reserved*/
1011 RESERVED();
1012 break;
1013 }
1014 break;
1015
1016 case 1: /*RFIx*/
1017 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
b994e91b
MF		 1018 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
1019 gen_check_privilege(dc);
1020 tcg_gen_mov_i32(cpu_SR[PS],
1021 cpu_SR[EPS2 + RRR_S - 2]);
1022 gen_helper_check_interrupts(cpu_env);
1023 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
1024 } else {
1025 qemu_log("RFI %d is illegal\n", RRR_S);
1026 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1027 }
40643d7c
MF		 1028 break;
1029
1030 case 2: /*RFME*/
1031 TBD();
1032 break;
1033
1034 default: /*reserved*/
1035 RESERVED();
1036 break;
1037
1038 }
91a5bb76
MF		 1039 break;
1040
1041 case 4: /*BREAKx*/
e61dc8f7
MF		 1042 HAS_OPTION(XTENSA_OPTION_DEBUG);
1043 if (dc->debug) {
1044 gen_debug_exception(dc, DEBUGCAUSE_BI);
1045 }
91a5bb76
MF		 1046 break;
1047
1048 case 5: /*SYSCALLx*/
1049 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
40643d7c
MF		 1050 switch (RRR_S) {
1051 case 0: /*SYSCALLx*/
1052 gen_exception_cause(dc, SYSCALL_CAUSE);
1053 break;
1054
1055 case 1: /*SIMCALL*/
1ddeaa5d
MF		 1056 if (semihosting_enabled) {
1057 gen_check_privilege(dc);
1058 gen_helper_simcall(cpu_env);
1059 } else {
1060 qemu_log("SIMCALL but semihosting is disabled\n");
1061 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1062 }
40643d7c
MF		 1063 break;
1064
1065 default:
1066 RESERVED();
1067 break;
1068 }
91a5bb76
MF		 1069 break;
1070
1071 case 6: /*RSILx*/
1072 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
40643d7c 1073 gen_check_privilege(dc);
772177c1 1074 gen_window_check1(dc, RRR_T);
40643d7c 1075 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
b994e91b 1076 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
40643d7c 1077 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
b994e91b
MF		 1078 gen_helper_check_interrupts(cpu_env);
1079 gen_jumpi_check_loop_end(dc, 0);
91a5bb76
MF		 1080 break;
1081
1082 case 7: /*WAITIx*/
1083 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
b994e91b
MF		 1084 gen_check_privilege(dc);
1085 gen_waiti(dc, RRR_S);
91a5bb76
MF		 1086 break;
1087
1088 case 8: /*ANY4p*/
91a5bb76 1089 case 9: /*ALL4p*/
91a5bb76 1090 case 10: /*ANY8p*/
91a5bb76
MF		 1091 case 11: /*ALL8p*/
1092 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 1093 {
1094 const unsigned shift = (RRR_R & 2) ? 8 : 4;
1095 TCGv_i32 mask = tcg_const_i32(
1096 ((1 << shift) - 1) << RRR_S);
1097 TCGv_i32 tmp = tcg_temp_new_i32();
1098
1099 tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
1100 if (RRR_R & 1) { /*ALL*/
1101 tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
1102 } else { /*ANY*/
1103 tcg_gen_add_i32(tmp, tmp, mask);
1104 }
1105 tcg_gen_shri_i32(tmp, tmp, RRR_S + shift);
1106 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
1107 tmp, RRR_T, 1);
1108 tcg_temp_free(mask);
1109 tcg_temp_free(tmp);
1110 }
91a5bb76
MF		 1111 break;
1112
1113 default: /*reserved*/
1114 RESERVED();
dedc5eae
MF		 1115 break;
1116
1117 }
1118 break;
1119
1120 case 1: /*AND*/
772177c1 1121 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1122 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1123 break;
1124
1125 case 2: /*OR*/
772177c1 1126 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1127 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1128 break;
1129
1130 case 3: /*XOR*/
772177c1 1131 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1132 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1133 break;
1134
1135 case 4: /*ST1*/
3580ecad
MF		 1136 switch (RRR_R) {
1137 case 0: /*SSR*/
772177c1 1138 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1139 gen_right_shift_sar(dc, cpu_R[RRR_S]);
1140 break;
1141
1142 case 1: /*SSL*/
772177c1 1143 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1144 gen_left_shift_sar(dc, cpu_R[RRR_S]);
1145 break;
1146
1147 case 2: /*SSA8L*/
772177c1 1148 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1149 {
1150 TCGv_i32 tmp = tcg_temp_new_i32();
1151 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1152 gen_right_shift_sar(dc, tmp);
1153 tcg_temp_free(tmp);
1154 }
1155 break;
1156
1157 case 3: /*SSA8B*/
772177c1 1158 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1159 {
1160 TCGv_i32 tmp = tcg_temp_new_i32();
1161 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1162 gen_left_shift_sar(dc, tmp);
1163 tcg_temp_free(tmp);
1164 }
1165 break;
1166
1167 case 4: /*SSAI*/
1168 {
1169 TCGv_i32 tmp = tcg_const_i32(
1170 RRR_S | ((RRR_T & 1) << 4));
1171 gen_right_shift_sar(dc, tmp);
1172 tcg_temp_free(tmp);
1173 }
1174 break;
1175
1176 case 6: /*RER*/
91a5bb76 1177 TBD();
3580ecad
MF		 1178 break;
1179
1180 case 7: /*WER*/
91a5bb76 1181 TBD();
3580ecad
MF		 1182 break;
1183
1184 case 8: /*ROTWw*/
1185 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1186 gen_check_privilege(dc);
1187 {
1188 TCGv_i32 tmp = tcg_const_i32(
1189 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
1190 gen_helper_rotw(tmp);
1191 tcg_temp_free(tmp);
772177c1 1192 reset_used_window(dc);
553e44f9 1193 }
3580ecad
MF		 1194 break;
1195
1196 case 14: /*NSAu*/
7f65f4b0 1197 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
772177c1 1198 gen_window_check2(dc, RRR_S, RRR_T);
3580ecad
MF		 1199 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1200 break;
1201
1202 case 15: /*NSAUu*/
7f65f4b0 1203 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
772177c1 1204 gen_window_check2(dc, RRR_S, RRR_T);
3580ecad
MF		 1205 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1206 break;
1207
1208 default: /*reserved*/
91a5bb76 1209 RESERVED();
3580ecad
MF		 1210 break;
1211 }
dedc5eae
MF		 1212 break;
1213
1214 case 5: /*TLB*/
b67ea0cd
MF		 1215 HAS_OPTION_BITS(
1216 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
1217 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1218 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION));
1219 gen_check_privilege(dc);
1220 gen_window_check2(dc, RRR_S, RRR_T);
1221 {
1222 TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0);
1223
1224 switch (RRR_R & 7) {
1225 case 3: /*RITLB0*/ /*RDTLB0*/
1226 gen_helper_rtlb0(cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1227 break;
1228
1229 case 4: /*IITLB*/ /*IDTLB*/
1230 gen_helper_itlb(cpu_R[RRR_S], dtlb);
1231 /* This could change memory mapping, so exit tb */
1232 gen_jumpi_check_loop_end(dc, -1);
1233 break;
1234
1235 case 5: /*PITLB*/ /*PDTLB*/
1236 tcg_gen_movi_i32(cpu_pc, dc->pc);
1237 gen_helper_ptlb(cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1238 break;
1239
1240 case 6: /*WITLB*/ /*WDTLB*/
1241 gen_helper_wtlb(cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1242 /* This could change memory mapping, so exit tb */
1243 gen_jumpi_check_loop_end(dc, -1);
1244 break;
1245
1246 case 7: /*RITLB1*/ /*RDTLB1*/
1247 gen_helper_rtlb1(cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1248 break;
1249
1250 default:
1251 tcg_temp_free(dtlb);
1252 RESERVED();
1253 break;
1254 }
1255 tcg_temp_free(dtlb);
1256 }
dedc5eae
MF		 1257 break;
1258
1259 case 6: /*RT0*/
772177c1 1260 gen_window_check2(dc, RRR_R, RRR_T);
f331fe5e
MF		 1261 switch (RRR_S) {
1262 case 0: /*NEG*/
1263 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1264 break;
1265
1266 case 1: /*ABS*/
1267 {
1268 int label = gen_new_label();
1269 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1270 tcg_gen_brcondi_i32(
1271 TCG_COND_GE, cpu_R[RRR_R], 0, label);
1272 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1273 gen_set_label(label);
1274 }
1275 break;
1276
1277 default: /*reserved*/
91a5bb76 1278 RESERVED();
f331fe5e
MF		 1279 break;
1280 }
dedc5eae
MF		 1281 break;
1282
1283 case 7: /*reserved*/
91a5bb76 1284 RESERVED();
dedc5eae
MF		 1285 break;
1286
1287 case 8: /*ADD*/
772177c1 1288 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1289 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1290 break;
1291
1292 case 9: /*ADD**/
1293 case 10:
1294 case 11:
772177c1 1295 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1296 {
1297 TCGv_i32 tmp = tcg_temp_new_i32();
1298 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1299 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1300 tcg_temp_free(tmp);
1301 }
1302 break;
1303
1304 case 12: /*SUB*/
772177c1 1305 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1306 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1307 break;
1308
1309 case 13: /*SUB**/
1310 case 14:
1311 case 15:
772177c1 1312 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1313 {
1314 TCGv_i32 tmp = tcg_temp_new_i32();
1315 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1316 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1317 tcg_temp_free(tmp);
1318 }
1319 break;
1320 }
1321 break;
1322
1323 case 1: /*RST1*/
3580ecad
MF		 1324 switch (OP2) {
1325 case 0: /*SLLI*/
1326 case 1:
772177c1 1327 gen_window_check2(dc, RRR_R, RRR_S);
3580ecad
MF		 1328 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1329 32 - (RRR_T | ((OP2 & 1) << 4)));
1330 break;
1331
1332 case 2: /*SRAI*/
1333 case 3:
772177c1 1334 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1335 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1336 RRR_S | ((OP2 & 1) << 4));
1337 break;
1338
1339 case 4: /*SRLI*/
772177c1 1340 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1341 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1342 break;
1343
1344 case 6: /*XSR*/
1345 {
1346 TCGv_i32 tmp = tcg_temp_new_i32();
40643d7c
MF		 1347 if (RSR_SR >= 64) {
1348 gen_check_privilege(dc);
1349 }
772177c1 1350 gen_window_check1(dc, RRR_T);
3580ecad
MF		 1351 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1352 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1353 gen_wsr(dc, RSR_SR, tmp);
1354 tcg_temp_free(tmp);
91a5bb76
MF		 1355 if (!sregnames[RSR_SR]) {
1356 TBD();
1357 }
3580ecad
MF		 1358 }
1359 break;
1360
1361 /*
1362 * Note: 64 bit ops are used here solely because SAR values
1363 * have range 0..63
1364 */
1365#define gen_shift_reg(cmd, reg) do { \
1366 TCGv_i64 tmp = tcg_temp_new_i64(); \
1367 tcg_gen_extu_i32_i64(tmp, reg); \
1368 tcg_gen_##cmd##_i64(v, v, tmp); \
1369 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1370 tcg_temp_free_i64(v); \
1371 tcg_temp_free_i64(tmp); \
1372 } while (0)
1373
1374#define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1375
1376 case 8: /*SRC*/
772177c1 1377 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
3580ecad
MF		 1378 {
1379 TCGv_i64 v = tcg_temp_new_i64();
1380 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1381 gen_shift(shr);
1382 }
1383 break;
1384
1385 case 9: /*SRL*/
772177c1 1386 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1387 if (dc->sar_5bit) {
1388 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1389 } else {
1390 TCGv_i64 v = tcg_temp_new_i64();
1391 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1392 gen_shift(shr);
1393 }
1394 break;
1395
1396 case 10: /*SLL*/
772177c1 1397 gen_window_check2(dc, RRR_R, RRR_S);
3580ecad
MF		 1398 if (dc->sar_m32_5bit) {
1399 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1400 } else {
1401 TCGv_i64 v = tcg_temp_new_i64();
1402 TCGv_i32 s = tcg_const_i32(32);
1403 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1404 tcg_gen_andi_i32(s, s, 0x3f);
1405 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1406 gen_shift_reg(shl, s);
1407 tcg_temp_free(s);
1408 }
1409 break;
1410
1411 case 11: /*SRA*/
772177c1 1412 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1413 if (dc->sar_5bit) {
1414 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1415 } else {
1416 TCGv_i64 v = tcg_temp_new_i64();
1417 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1418 gen_shift(sar);
1419 }
1420 break;
1421#undef gen_shift
1422#undef gen_shift_reg
1423
1424 case 12: /*MUL16U*/
1425 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
772177c1 1426 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
3580ecad
MF		 1427 {
1428 TCGv_i32 v1 = tcg_temp_new_i32();
1429 TCGv_i32 v2 = tcg_temp_new_i32();
1430 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1431 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1432 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1433 tcg_temp_free(v2);
1434 tcg_temp_free(v1);
1435 }
1436 break;
1437
1438 case 13: /*MUL16S*/
1439 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
772177c1 1440 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
3580ecad
MF		 1441 {
1442 TCGv_i32 v1 = tcg_temp_new_i32();
1443 TCGv_i32 v2 = tcg_temp_new_i32();
1444 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1445 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1446 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1447 tcg_temp_free(v2);
1448 tcg_temp_free(v1);
1449 }
1450 break;
1451
1452 default: /*reserved*/
91a5bb76 1453 RESERVED();
3580ecad
MF		 1454 break;
1455 }
dedc5eae
MF		 1456 break;
1457
1458 case 2: /*RST2*/
4dd85b6b
MF		 1459 if (OP2 >= 8) {
1460 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1461 }
772177c1 1462
f76ebf55
MF		 1463 if (OP2 >= 12) {
1464 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
1465 int label = gen_new_label();
1466 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1467 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1468 gen_set_label(label);
1469 }
1470
1471 switch (OP2) {
4dd85b6b
MF		 1472#define BOOLEAN_LOGIC(fn, r, s, t) \
1473 do { \
1474 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1475 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1476 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1477 \
1478 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1479 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1480 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1481 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1482 tcg_temp_free(tmp1); \
1483 tcg_temp_free(tmp2); \
1484 } while (0)
1485
1486 case 0: /*ANDBp*/
1487 BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T);
1488 break;
1489
1490 case 1: /*ANDBCp*/
1491 BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T);
1492 break;
1493
1494 case 2: /*ORBp*/
1495 BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T);
1496 break;
1497
1498 case 3: /*ORBCp*/
1499 BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T);
1500 break;
1501
1502 case 4: /*XORBp*/
1503 BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T);
1504 break;
1505
1506#undef BOOLEAN_LOGIC
1507
f76ebf55
MF		 1508 case 8: /*MULLi*/
1509 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1510 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1511 break;
1512
1513 case 10: /*MULUHi*/
1514 case 11: /*MULSHi*/
7f65f4b0 1515 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
f76ebf55
MF		 1516 {
1517 TCGv_i64 r = tcg_temp_new_i64();
1518 TCGv_i64 s = tcg_temp_new_i64();
1519 TCGv_i64 t = tcg_temp_new_i64();
1520
1521 if (OP2 == 10) {
1522 tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]);
1523 tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]);
1524 } else {
1525 tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]);
1526 tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]);
1527 }
1528 tcg_gen_mul_i64(r, s, t);
1529 tcg_gen_shri_i64(r, r, 32);
1530 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r);
1531
1532 tcg_temp_free_i64(r);
1533 tcg_temp_free_i64(s);
1534 tcg_temp_free_i64(t);
1535 }
1536 break;
1537
1538 case 12: /*QUOUi*/
1539 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1540 break;
1541
1542 case 13: /*QUOSi*/
1543 case 15: /*REMSi*/
1544 {
1545 int label1 = gen_new_label();
1546 int label2 = gen_new_label();
1547
1548 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1549 label1);
1550 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1551 label1);
1552 tcg_gen_movi_i32(cpu_R[RRR_R],
1553 OP2 == 13 ? 0x80000000 : 0);
1554 tcg_gen_br(label2);
1555 gen_set_label(label1);
1556 if (OP2 == 13) {
1557 tcg_gen_div_i32(cpu_R[RRR_R],
1558 cpu_R[RRR_S], cpu_R[RRR_T]);
1559 } else {
1560 tcg_gen_rem_i32(cpu_R[RRR_R],
1561 cpu_R[RRR_S], cpu_R[RRR_T]);
1562 }
1563 gen_set_label(label2);
1564 }
1565 break;
1566
1567 case 14: /*REMUi*/
1568 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1569 break;
1570
1571 default: /*reserved*/
1572 RESERVED();
1573 break;
1574 }
dedc5eae
MF		 1575 break;
1576
1577 case 3: /*RST3*/
b8132eff
MF		 1578 switch (OP2) {
1579 case 0: /*RSR*/
40643d7c
MF		 1580 if (RSR_SR >= 64) {
1581 gen_check_privilege(dc);
1582 }
772177c1 1583 gen_window_check1(dc, RRR_T);
b8132eff 1584 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
91a5bb76
MF		 1585 if (!sregnames[RSR_SR]) {
1586 TBD();
1587 }
b8132eff
MF		 1588 break;
1589
1590 case 1: /*WSR*/
40643d7c
MF		 1591 if (RSR_SR >= 64) {
1592 gen_check_privilege(dc);
1593 }
772177c1 1594 gen_window_check1(dc, RRR_T);
b8132eff 1595 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
91a5bb76
MF		 1596 if (!sregnames[RSR_SR]) {
1597 TBD();
1598 }
b8132eff
MF		 1599 break;
1600
1601 case 2: /*SEXTu*/
7f65f4b0 1602 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT);
772177c1 1603 gen_window_check2(dc, RRR_R, RRR_S);
b8132eff
MF		 1604 {
1605 int shift = 24 - RRR_T;
1606
1607 if (shift == 24) {
1608 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1609 } else if (shift == 16) {
1610 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1611 } else {
1612 TCGv_i32 tmp = tcg_temp_new_i32();
1613 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1614 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1615 tcg_temp_free(tmp);
1616 }
1617 }
1618 break;
1619
1620 case 3: /*CLAMPSu*/
7f65f4b0 1621 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS);
772177c1 1622 gen_window_check2(dc, RRR_R, RRR_S);
b8132eff
MF		 1623 {
1624 TCGv_i32 tmp1 = tcg_temp_new_i32();
1625 TCGv_i32 tmp2 = tcg_temp_new_i32();
1626 int label = gen_new_label();
1627
1628 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1629 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1630 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
1631 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1632 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp2, 0, label);
1633
1634 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
1635 tcg_gen_xori_i32(cpu_R[RRR_R], tmp1,
1636 0xffffffff >> (25 - RRR_T));
1637
1638 gen_set_label(label);
1639
1640 tcg_temp_free(tmp1);
1641 tcg_temp_free(tmp2);
1642 }
1643 break;
1644
1645 case 4: /*MINu*/
1646 case 5: /*MAXu*/
1647 case 6: /*MINUu*/
1648 case 7: /*MAXUu*/
7f65f4b0 1649 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX);
772177c1 1650 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
b8132eff
MF		 1651 {
1652 static const TCGCond cond[] = {
1653 TCG_COND_LE,
1654 TCG_COND_GE,
1655 TCG_COND_LEU,
1656 TCG_COND_GEU
1657 };
1658 int label = gen_new_label();
1659
1660 if (RRR_R != RRR_T) {
1661 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1662 tcg_gen_brcond_i32(cond[OP2 - 4],
1663 cpu_R[RRR_S], cpu_R[RRR_T], label);
1664 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1665 } else {
1666 tcg_gen_brcond_i32(cond[OP2 - 4],
1667 cpu_R[RRR_T], cpu_R[RRR_S], label);
1668 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1669 }
1670 gen_set_label(label);
1671 }
1672 break;
1673
1674 case 8: /*MOVEQZ*/
1675 case 9: /*MOVNEZ*/
1676 case 10: /*MOVLTZ*/
1677 case 11: /*MOVGEZ*/
772177c1 1678 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
b8132eff
MF		 1679 {
1680 static const TCGCond cond[] = {
1681 TCG_COND_NE,
1682 TCG_COND_EQ,
1683 TCG_COND_GE,
1684 TCG_COND_LT
1685 };
1686 int label = gen_new_label();
1687 tcg_gen_brcondi_i32(cond[OP2 - 8], cpu_R[RRR_T], 0, label);
1688 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1689 gen_set_label(label);
1690 }
1691 break;
1692
1693 case 12: /*MOVFp*/
b8132eff
MF		 1694 case 13: /*MOVTp*/
1695 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 1696 gen_window_check2(dc, RRR_R, RRR_S);
1697 {
1698 int label = gen_new_label();
1699 TCGv_i32 tmp = tcg_temp_new_i32();
1700
1701 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
1702 tcg_gen_brcondi_i32(
1703 OP2 & 1 ? TCG_COND_EQ : TCG_COND_NE,
1704 tmp, 0, label);
1705 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1706 gen_set_label(label);
1707 tcg_temp_free(tmp);
1708 }
b8132eff
MF		 1709 break;
1710
1711 case 14: /*RUR*/
772177c1 1712 gen_window_check1(dc, RRR_R);
b8132eff
MF		 1713 {
1714 int st = (RRR_S << 4) + RRR_T;
1715 if (uregnames[st]) {
1716 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1717 } else {
1718 qemu_log("RUR %d not implemented, ", st);
91a5bb76 1719 TBD();
b8132eff
MF		 1720 }
1721 }
1722 break;
1723
1724 case 15: /*WUR*/
772177c1 1725 gen_window_check1(dc, RRR_T);
b8132eff
MF		 1726 {
1727 if (uregnames[RSR_SR]) {
1728 tcg_gen_mov_i32(cpu_UR[RSR_SR], cpu_R[RRR_T]);
1729 } else {
1730 qemu_log("WUR %d not implemented, ", RSR_SR);
91a5bb76 1731 TBD();
b8132eff
MF		 1732 }
1733 }
1734 break;
1735
1736 }
dedc5eae
MF		 1737 break;
1738
1739 case 4: /*EXTUI*/
1740 case 5:
772177c1 1741 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1742 {
1743 int shiftimm = RRR_S | (OP1 << 4);
1744 int maskimm = (1 << (OP2 + 1)) - 1;
1745
1746 TCGv_i32 tmp = tcg_temp_new_i32();
1747 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1748 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
1749 tcg_temp_free(tmp);
1750 }
dedc5eae
MF		 1751 break;
1752
1753 case 6: /*CUST0*/
91a5bb76 1754 RESERVED();
dedc5eae
MF		 1755 break;
1756
1757 case 7: /*CUST1*/
91a5bb76 1758 RESERVED();
dedc5eae
MF		 1759 break;
1760
1761 case 8: /*LSCXp*/
1762 HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
91a5bb76 1763 TBD();
dedc5eae
MF		 1764 break;
1765
1766 case 9: /*LSC4*/
772177c1 1767 gen_window_check2(dc, RRR_S, RRR_T);
553e44f9
MF		 1768 switch (OP2) {
1769 case 0: /*L32E*/
1770 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1771 gen_check_privilege(dc);
1772 {
1773 TCGv_i32 addr = tcg_temp_new_i32();
1774 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1775 (0xffffffc0 | (RRR_R << 2)));
1776 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1777 tcg_temp_free(addr);
1778 }
1779 break;
1780
1781 case 4: /*S32E*/
1782 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1783 gen_check_privilege(dc);
1784 {
1785 TCGv_i32 addr = tcg_temp_new_i32();
1786 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1787 (0xffffffc0 | (RRR_R << 2)));
1788 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1789 tcg_temp_free(addr);
1790 }
1791 break;
1792
1793 default:
1794 RESERVED();
1795 break;
1796 }
dedc5eae
MF		 1797 break;
1798
1799 case 10: /*FP0*/
1800 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
91a5bb76 1801 TBD();
dedc5eae
MF		 1802 break;
1803
1804 case 11: /*FP1*/
1805 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
91a5bb76 1806 TBD();
dedc5eae
MF		 1807 break;
1808
1809 default: /*reserved*/
91a5bb76 1810 RESERVED();
dedc5eae
MF		 1811 break;
1812 }
1813 break;
1814
1815 case 1: /*L32R*/
772177c1 1816 gen_window_check1(dc, RRR_T);
dedc5eae
MF		 1817 {
1818 TCGv_i32 tmp = tcg_const_i32(
6ad6dbf7
MF		 1819 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
1820 0 : ((dc->pc + 3) & ~3)) +
1821 (0xfffc0000 | (RI16_IMM16 << 2)));
dedc5eae 1822
6ad6dbf7
MF		 1823 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
1824 tcg_gen_add_i32(tmp, tmp, dc->litbase);
1825 }
f0a548b9 1826 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
dedc5eae
MF		 1827 tcg_temp_free(tmp);
1828 }
1829 break;
1830
1831 case 2: /*LSAI*/
809377aa
MF		 1832#define gen_load_store(type, shift) do { \
1833 TCGv_i32 addr = tcg_temp_new_i32(); \
772177c1 1834 gen_window_check2(dc, RRI8_S, RRI8_T); \
809377aa 1835 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
5b4e481b
MF		 1836 if (shift) { \
1837 gen_load_store_alignment(dc, shift, addr, false); \
1838 } \
f0a548b9 1839 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
809377aa
MF		 1840 tcg_temp_free(addr); \
1841 } while (0)
1842
1843 switch (RRI8_R) {
1844 case 0: /*L8UI*/
1845 gen_load_store(ld8u, 0);
1846 break;
1847
1848 case 1: /*L16UI*/
1849 gen_load_store(ld16u, 1);
1850 break;
1851
1852 case 2: /*L32I*/
1853 gen_load_store(ld32u, 2);
1854 break;
1855
1856 case 4: /*S8I*/
1857 gen_load_store(st8, 0);
1858 break;
1859
1860 case 5: /*S16I*/
1861 gen_load_store(st16, 1);
1862 break;
1863
1864 case 6: /*S32I*/
1865 gen_load_store(st32, 2);
1866 break;
1867
1868 case 7: /*CACHEc*/
8ffc2d0d
MF		 1869 if (RRI8_T < 8) {
1870 HAS_OPTION(XTENSA_OPTION_DCACHE);
1871 }
1872
1873 switch (RRI8_T) {
1874 case 0: /*DPFRc*/
1875 break;
1876
1877 case 1: /*DPFWc*/
1878 break;
1879
1880 case 2: /*DPFROc*/
1881 break;
1882
1883 case 3: /*DPFWOc*/
1884 break;
1885
1886 case 4: /*DHWBc*/
1887 break;
1888
1889 case 5: /*DHWBIc*/
1890 break;
1891
1892 case 6: /*DHIc*/
1893 break;
1894
1895 case 7: /*DIIc*/
1896 break;
1897
1898 case 8: /*DCEc*/
1899 switch (OP1) {
1900 case 0: /*DPFLl*/
1901 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1902 break;
1903
1904 case 2: /*DHUl*/
1905 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1906 break;
1907
1908 case 3: /*DIUl*/
1909 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1910 break;
1911
1912 case 4: /*DIWBc*/
1913 HAS_OPTION(XTENSA_OPTION_DCACHE);
1914 break;
1915
1916 case 5: /*DIWBIc*/
1917 HAS_OPTION(XTENSA_OPTION_DCACHE);
1918 break;
1919
1920 default: /*reserved*/
1921 RESERVED();
1922 break;
1923
1924 }
1925 break;
1926
1927 case 12: /*IPFc*/
1928 HAS_OPTION(XTENSA_OPTION_ICACHE);
1929 break;
1930
1931 case 13: /*ICEc*/
1932 switch (OP1) {
1933 case 0: /*IPFLl*/
1934 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1935 break;
1936
1937 case 2: /*IHUl*/
1938 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1939 break;
1940
1941 case 3: /*IIUl*/
1942 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1943 break;
1944
1945 default: /*reserved*/
1946 RESERVED();
1947 break;
1948 }
1949 break;
1950
1951 case 14: /*IHIc*/
1952 HAS_OPTION(XTENSA_OPTION_ICACHE);
1953 break;
1954
1955 case 15: /*IIIc*/
1956 HAS_OPTION(XTENSA_OPTION_ICACHE);
1957 break;
1958
1959 default: /*reserved*/
1960 RESERVED();
1961 break;
1962 }
809377aa
MF		 1963 break;
1964
1965 case 9: /*L16SI*/
1966 gen_load_store(ld16s, 1);
1967 break;
5b4e481b 1968#undef gen_load_store
809377aa
MF		 1969
1970 case 10: /*MOVI*/
772177c1 1971 gen_window_check1(dc, RRI8_T);
809377aa
MF		 1972 tcg_gen_movi_i32(cpu_R[RRI8_T],
1973 RRI8_IMM8 | (RRI8_S << 8) |
1974 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
1975 break;
1976
5b4e481b
MF		 1977#define gen_load_store_no_hw_align(type) do { \
1978 TCGv_i32 addr = tcg_temp_local_new_i32(); \
772177c1 1979 gen_window_check2(dc, RRI8_S, RRI8_T); \
5b4e481b
MF		 1980 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
1981 gen_load_store_alignment(dc, 2, addr, true); \
1982 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
1983 tcg_temp_free(addr); \
1984 } while (0)
1985
809377aa
MF		 1986 case 11: /*L32AIy*/
1987 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 1988 gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
809377aa
MF		 1989 break;
1990
1991 case 12: /*ADDI*/
772177c1 1992 gen_window_check2(dc, RRI8_S, RRI8_T);
809377aa
MF		 1993 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
1994 break;
1995
1996 case 13: /*ADDMI*/
772177c1 1997 gen_window_check2(dc, RRI8_S, RRI8_T);
809377aa
MF		 1998 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE << 8);
1999 break;
2000
2001 case 14: /*S32C1Iy*/
7f65f4b0 2002 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
772177c1 2003 gen_window_check2(dc, RRI8_S, RRI8_T);
809377aa
MF		 2004 {
2005 int label = gen_new_label();
2006 TCGv_i32 tmp = tcg_temp_local_new_i32();
2007 TCGv_i32 addr = tcg_temp_local_new_i32();
2008
2009 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
2010 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
5b4e481b 2011 gen_load_store_alignment(dc, 2, addr, true);
f0a548b9 2012 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
809377aa
MF		 2013 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
2014 cpu_SR[SCOMPARE1], label);
2015
f0a548b9 2016 tcg_gen_qemu_st32(tmp, addr, dc->cring);
809377aa
MF		 2017
2018 gen_set_label(label);
2019 tcg_temp_free(addr);
2020 tcg_temp_free(tmp);
2021 }
2022 break;
2023
2024 case 15: /*S32RIy*/
2025 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 2026 gen_load_store_no_hw_align(st32); /*TODO release?*/
809377aa 2027 break;
5b4e481b 2028#undef gen_load_store_no_hw_align
809377aa
MF		 2029
2030 default: /*reserved*/
91a5bb76 2031 RESERVED();
809377aa
MF		 2032 break;
2033 }
dedc5eae
MF		 2034 break;
2035
2036 case 3: /*LSCIp*/
2037 HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
91a5bb76 2038 TBD();
dedc5eae
MF		 2039 break;
2040
2041 case 4: /*MAC16d*/
2042 HAS_OPTION(XTENSA_OPTION_MAC16);
6825b6c3
MF		 2043 {
2044 enum {
2045 MAC16_UMUL = 0x0,
2046 MAC16_MUL = 0x4,
2047 MAC16_MULA = 0x8,
2048 MAC16_MULS = 0xc,
2049 MAC16_NONE = 0xf,
2050 } op = OP1 & 0xc;
2051 bool is_m1_sr = (OP2 & 0x3) == 2;
2052 bool is_m2_sr = (OP2 & 0xc) == 0;
2053 uint32_t ld_offset = 0;
2054
2055 if (OP2 > 9) {
2056 RESERVED();
2057 }
2058
2059 switch (OP2 & 2) {
2060 case 0: /*MACI?/MACC?*/
2061 is_m1_sr = true;
2062 ld_offset = (OP2 & 1) ? -4 : 4;
2063
2064 if (OP2 >= 8) { /*MACI/MACC*/
2065 if (OP1 == 0) { /*LDINC/LDDEC*/
2066 op = MAC16_NONE;
2067 } else {
2068 RESERVED();
2069 }
2070 } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/
2071 RESERVED();
2072 }
2073 break;
2074
2075 case 2: /*MACD?/MACA?*/
2076 if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/
2077 RESERVED();
2078 }
2079 break;
2080 }
2081
2082 if (op != MAC16_NONE) {
2083 if (!is_m1_sr) {
2084 gen_window_check1(dc, RRR_S);
2085 }
2086 if (!is_m2_sr) {
2087 gen_window_check1(dc, RRR_T);
2088 }
2089 }
2090
2091 {
2092 TCGv_i32 vaddr = tcg_temp_new_i32();
2093 TCGv_i32 mem32 = tcg_temp_new_i32();
2094
2095 if (ld_offset) {
2096 gen_window_check1(dc, RRR_S);
2097 tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset);
2098 gen_load_store_alignment(dc, 2, vaddr, false);
2099 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
2100 }
2101 if (op != MAC16_NONE) {
2102 TCGv_i32 m1 = gen_mac16_m(
2103 is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S],
2104 OP1 & 1, op == MAC16_UMUL);
2105 TCGv_i32 m2 = gen_mac16_m(
2106 is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T],
2107 OP1 & 2, op == MAC16_UMUL);
2108
2109 if (op == MAC16_MUL || op == MAC16_UMUL) {
2110 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
2111 if (op == MAC16_UMUL) {
2112 tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
2113 } else {
2114 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
2115 }
2116 } else {
2117 TCGv_i32 res = tcg_temp_new_i32();
2118 TCGv_i64 res64 = tcg_temp_new_i64();
2119 TCGv_i64 tmp = tcg_temp_new_i64();
2120
2121 tcg_gen_mul_i32(res, m1, m2);
2122 tcg_gen_ext_i32_i64(res64, res);
2123 tcg_gen_concat_i32_i64(tmp,
2124 cpu_SR[ACCLO], cpu_SR[ACCHI]);
2125 if (op == MAC16_MULA) {
2126 tcg_gen_add_i64(tmp, tmp, res64);
2127 } else {
2128 tcg_gen_sub_i64(tmp, tmp, res64);
2129 }
2130 tcg_gen_trunc_i64_i32(cpu_SR[ACCLO], tmp);
2131 tcg_gen_shri_i64(tmp, tmp, 32);
2132 tcg_gen_trunc_i64_i32(cpu_SR[ACCHI], tmp);
2133 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
2134
2135 tcg_temp_free(res);
2136 tcg_temp_free_i64(res64);
2137 tcg_temp_free_i64(tmp);
2138 }
2139 tcg_temp_free(m1);
2140 tcg_temp_free(m2);
2141 }
2142 if (ld_offset) {
2143 tcg_gen_mov_i32(cpu_R[RRR_S], vaddr);
2144 tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32);
2145 }
2146 tcg_temp_free(vaddr);
2147 tcg_temp_free(mem32);
2148 }
2149 }
dedc5eae
MF		 2150 break;
2151
2152 case 5: /*CALLN*/
2153 switch (CALL_N) {
2154 case 0: /*CALL0*/
2155 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
2156 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2157 break;
2158
2159 case 1: /*CALL4w*/
2160 case 2: /*CALL8w*/
2161 case 3: /*CALL12w*/
2162 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
772177c1 2163 gen_window_check1(dc, CALL_N << 2);
553e44f9
MF		 2164 gen_callwi(dc, CALL_N,
2165 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
dedc5eae
MF		 2166 break;
2167 }
2168 break;
2169
2170 case 6: /*SI*/
2171 switch (CALL_N) {
2172 case 0: /*J*/
2173 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
2174 break;
2175
bd57fb91 2176 case 1: /*BZ*/
772177c1 2177 gen_window_check1(dc, BRI12_S);
bd57fb91
MF		 2178 {
2179 static const TCGCond cond[] = {
2180 TCG_COND_EQ, /*BEQZ*/
2181 TCG_COND_NE, /*BNEZ*/
2182 TCG_COND_LT, /*BLTZ*/
2183 TCG_COND_GE, /*BGEZ*/
2184 };
2185
2186 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
2187 4 + BRI12_IMM12_SE);
2188 }
2189 break;
2190
2191 case 2: /*BI0*/
772177c1 2192 gen_window_check1(dc, BRI8_S);
bd57fb91
MF		 2193 {
2194 static const TCGCond cond[] = {
2195 TCG_COND_EQ, /*BEQI*/
2196 TCG_COND_NE, /*BNEI*/
2197 TCG_COND_LT, /*BLTI*/
2198 TCG_COND_GE, /*BGEI*/
2199 };
2200
2201 gen_brcondi(dc, cond[BRI8_M & 3],
2202 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
2203 }
2204 break;
2205
2206 case 3: /*BI1*/
2207 switch (BRI8_M) {
2208 case 0: /*ENTRYw*/
2209 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 2210 {
2211 TCGv_i32 pc = tcg_const_i32(dc->pc);
2212 TCGv_i32 s = tcg_const_i32(BRI12_S);
2213 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
b994e91b 2214 gen_advance_ccount(dc);
553e44f9
MF		 2215 gen_helper_entry(pc, s, imm);
2216 tcg_temp_free(imm);
2217 tcg_temp_free(s);
2218 tcg_temp_free(pc);
772177c1 2219 reset_used_window(dc);
553e44f9 2220 }
bd57fb91
MF		 2221 break;
2222
2223 case 1: /*B1*/
2224 switch (BRI8_R) {
2225 case 0: /*BFp*/
bd57fb91
MF		 2226 case 1: /*BTp*/
2227 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 2228 {
2229 TCGv_i32 tmp = tcg_temp_new_i32();
2230 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
2231 gen_brcondi(dc,
2232 BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
2233 tmp, 0, 4 + RRI8_IMM8_SE);
2234 tcg_temp_free(tmp);
2235 }
bd57fb91
MF		 2236 break;
2237
2238 case 8: /*LOOP*/
bd57fb91 2239 case 9: /*LOOPNEZ*/
bd57fb91 2240 case 10: /*LOOPGTZ*/
797d780b 2241 HAS_OPTION(XTENSA_OPTION_LOOP);
772177c1 2242 gen_window_check1(dc, RRI8_S);
797d780b
MF		 2243 {
2244 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
2245 TCGv_i32 tmp = tcg_const_i32(lend);
2246
2247 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
2248 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
2249 gen_wsr_lend(dc, LEND, tmp);
2250 tcg_temp_free(tmp);
2251
2252 if (BRI8_R > 8) {
2253 int label = gen_new_label();
2254 tcg_gen_brcondi_i32(
2255 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
2256 cpu_R[RRI8_S], 0, label);
2257 gen_jumpi(dc, lend, 1);
2258 gen_set_label(label);
2259 }
2260
2261 gen_jumpi(dc, dc->next_pc, 0);
2262 }
bd57fb91
MF		 2263 break;
2264
2265 default: /*reserved*/
91a5bb76 2266 RESERVED();
bd57fb91
MF		 2267 break;
2268
2269 }
2270 break;
2271
2272 case 2: /*BLTUI*/
2273 case 3: /*BGEUI*/
772177c1 2274 gen_window_check1(dc, BRI8_S);
bd57fb91
MF		 2275 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
2276 cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
2277 break;
2278 }
2279 break;
2280
dedc5eae
MF		 2281 }
2282 break;
2283
2284 case 7: /*B*/
bd57fb91
MF		 2285 {
2286 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
2287
2288 switch (RRI8_R & 7) {
2289 case 0: /*BNONE*/ /*BANY*/
772177c1 2290 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2291 {
2292 TCGv_i32 tmp = tcg_temp_new_i32();
2293 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2294 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2295 tcg_temp_free(tmp);
2296 }
2297 break;
2298
2299 case 1: /*BEQ*/ /*BNE*/
2300 case 2: /*BLT*/ /*BGE*/
2301 case 3: /*BLTU*/ /*BGEU*/
772177c1 2302 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2303 {
2304 static const TCGCond cond[] = {
2305 [1] = TCG_COND_EQ,
2306 [2] = TCG_COND_LT,
2307 [3] = TCG_COND_LTU,
2308 [9] = TCG_COND_NE,
2309 [10] = TCG_COND_GE,
2310 [11] = TCG_COND_GEU,
2311 };
2312 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
2313 4 + RRI8_IMM8_SE);
2314 }
2315 break;
2316
2317 case 4: /*BALL*/ /*BNALL*/
772177c1 2318 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2319 {
2320 TCGv_i32 tmp = tcg_temp_new_i32();
2321 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2322 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
2323 4 + RRI8_IMM8_SE);
2324 tcg_temp_free(tmp);
2325 }
2326 break;
2327
2328 case 5: /*BBC*/ /*BBS*/
772177c1 2329 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2330 {
2331 TCGv_i32 bit = tcg_const_i32(1);
2332 TCGv_i32 tmp = tcg_temp_new_i32();
2333 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
2334 tcg_gen_shl_i32(bit, bit, tmp);
2335 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
2336 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2337 tcg_temp_free(tmp);
2338 tcg_temp_free(bit);
2339 }
2340 break;
2341
2342 case 6: /*BBCI*/ /*BBSI*/
2343 case 7:
772177c1 2344 gen_window_check1(dc, RRI8_S);
bd57fb91
MF		 2345 {
2346 TCGv_i32 tmp = tcg_temp_new_i32();
2347 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
2348 1 << (((RRI8_R & 1) << 4) | RRI8_T));
2349 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2350 tcg_temp_free(tmp);
2351 }
2352 break;
2353
2354 }
2355 }
dedc5eae
MF		 2356 break;
2357
67882fd1
MF		 2358#define gen_narrow_load_store(type) do { \
2359 TCGv_i32 addr = tcg_temp_new_i32(); \
772177c1 2360 gen_window_check2(dc, RRRN_S, RRRN_T); \
67882fd1 2361 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
5b4e481b 2362 gen_load_store_alignment(dc, 2, addr, false); \
f0a548b9 2363 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
67882fd1
MF		 2364 tcg_temp_free(addr); \
2365 } while (0)
2366
dedc5eae 2367 case 8: /*L32I.Nn*/
67882fd1 2368 gen_narrow_load_store(ld32u);
dedc5eae
MF		 2369 break;
2370
2371 case 9: /*S32I.Nn*/
67882fd1 2372 gen_narrow_load_store(st32);
dedc5eae 2373 break;
67882fd1 2374#undef gen_narrow_load_store
dedc5eae
MF		 2375
2376 case 10: /*ADD.Nn*/
772177c1 2377 gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T);
67882fd1 2378 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
dedc5eae
MF		 2379 break;
2380
2381 case 11: /*ADDI.Nn*/
772177c1 2382 gen_window_check2(dc, RRRN_R, RRRN_S);
67882fd1 2383 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
dedc5eae
MF		 2384 break;
2385
2386 case 12: /*ST2n*/
772177c1 2387 gen_window_check1(dc, RRRN_S);
67882fd1
MF		 2388 if (RRRN_T < 8) { /*MOVI.Nn*/
2389 tcg_gen_movi_i32(cpu_R[RRRN_S],
2390 RRRN_R | (RRRN_T << 4) |
2391 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
2392 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
bd57fb91
MF		 2393 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
2394
2395 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
2396 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
67882fd1 2397 }
dedc5eae
MF		 2398 break;
2399
2400 case 13: /*ST3n*/
67882fd1
MF		 2401 switch (RRRN_R) {
2402 case 0: /*MOV.Nn*/
772177c1 2403 gen_window_check2(dc, RRRN_S, RRRN_T);
67882fd1
MF		 2404 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
2405 break;
2406
2407 case 15: /*S3*/
2408 switch (RRRN_T) {
2409 case 0: /*RET.Nn*/
2410 gen_jump(dc, cpu_R[0]);
2411 break;
2412
2413 case 1: /*RETW.Nn*/
91a5bb76 2414 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 2415 {
2416 TCGv_i32 tmp = tcg_const_i32(dc->pc);
b994e91b 2417 gen_advance_ccount(dc);
553e44f9
MF		 2418 gen_helper_retw(tmp, tmp);
2419 gen_jump(dc, tmp);
2420 tcg_temp_free(tmp);
2421 }
67882fd1
MF		 2422 break;
2423
2424 case 2: /*BREAK.Nn*/
e61dc8f7
MF		 2425 HAS_OPTION(XTENSA_OPTION_DEBUG);
2426 if (dc->debug) {
2427 gen_debug_exception(dc, DEBUGCAUSE_BN);
2428 }
67882fd1
MF		 2429 break;
2430
2431 case 3: /*NOP.Nn*/
2432 break;
2433
2434 case 6: /*ILL.Nn*/
40643d7c 2435 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
67882fd1
MF		 2436 break;
2437
2438 default: /*reserved*/
91a5bb76 2439 RESERVED();
67882fd1
MF		 2440 break;
2441 }
2442 break;
2443
2444 default: /*reserved*/
91a5bb76 2445 RESERVED();
67882fd1
MF		 2446 break;
2447 }
dedc5eae
MF		 2448 break;
2449
2450 default: /*reserved*/
91a5bb76 2451 RESERVED();
dedc5eae
MF		 2452 break;
2453 }
2454
797d780b 2455 gen_check_loop_end(dc, 0);
dedc5eae 2456 dc->pc = dc->next_pc;
797d780b 2457
dedc5eae
MF		 2458 return;
2459
2460invalid_opcode:
2461 qemu_log("INVALID(pc = %08x)\n", dc->pc);
6b814719 2462 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
dedc5eae
MF		 2463#undef HAS_OPTION
2464}
2465
2466static void check_breakpoint(CPUState *env, DisasContext *dc)
2467{
2468 CPUBreakpoint *bp;
2469
2470 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
2471 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
2472 if (bp->pc == dc->pc) {
2473 tcg_gen_movi_i32(cpu_pc, dc->pc);
b994e91b 2474 gen_exception(dc, EXCP_DEBUG);
dedc5eae
MF		 2475 dc->is_jmp = DISAS_UPDATE;
2476 }
2477 }
2478 }
2479}
2480
e61dc8f7
MF		 2481static void gen_ibreak_check(CPUState *env, DisasContext *dc)
2482{
2483 unsigned i;
2484
2485 for (i = 0; i < dc->config->nibreak; ++i) {
2486 if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
2487 env->sregs[IBREAKA + i] == dc->pc) {
2488 gen_debug_exception(dc, DEBUGCAUSE_IB);
2489 break;
2490 }
2491 }
2492}
2493
dedc5eae
MF		 2494static void gen_intermediate_code_internal(
2495 CPUState *env, TranslationBlock *tb, int search_pc)
2496{
2497 DisasContext dc;
2498 int insn_count = 0;
2499 int j, lj = -1;
2500 uint16_t *gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2501 int max_insns = tb->cflags & CF_COUNT_MASK;
2502 uint32_t pc_start = tb->pc;
2503 uint32_t next_page_start =
2504 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2505
2506 if (max_insns == 0) {
2507 max_insns = CF_COUNT_MASK;
2508 }
2509
2510 dc.config = env->config;
2511 dc.singlestep_enabled = env->singlestep_enabled;
2512 dc.tb = tb;
2513 dc.pc = pc_start;
f0a548b9
MF		 2514 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
2515 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
797d780b
MF		 2516 dc.lbeg = env->sregs[LBEG];
2517 dc.lend = env->sregs[LEND];
dedc5eae 2518 dc.is_jmp = DISAS_NEXT;
b994e91b 2519 dc.ccount_delta = 0;
e61dc8f7 2520 dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG;
35b5c044 2521 dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
dedc5eae 2522
6ad6dbf7 2523 init_litbase(&dc);
3580ecad 2524 init_sar_tracker(&dc);
772177c1 2525 reset_used_window(&dc);
35b5c044
MF		 2526 if (dc.icount) {
2527 dc.next_icount = tcg_temp_local_new_i32();
2528 }
3580ecad 2529
dedc5eae
MF		 2530 gen_icount_start();
2531
40643d7c
MF		 2532 if (env->singlestep_enabled && env->exception_taken) {
2533 env->exception_taken = 0;
2534 tcg_gen_movi_i32(cpu_pc, dc.pc);
b994e91b 2535 gen_exception(&dc, EXCP_DEBUG);
40643d7c
MF		 2536 }
2537
dedc5eae
MF		 2538 do {
2539 check_breakpoint(env, &dc);
2540
2541 if (search_pc) {
2542 j = gen_opc_ptr - gen_opc_buf;
2543 if (lj < j) {
2544 lj++;
2545 while (lj < j) {
2546 gen_opc_instr_start[lj++] = 0;
2547 }
2548 }
2549 gen_opc_pc[lj] = dc.pc;
2550 gen_opc_instr_start[lj] = 1;
2551 gen_opc_icount[lj] = insn_count;
2552 }
2553
2554 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
2555 tcg_gen_debug_insn_start(dc.pc);
2556 }
2557
b994e91b
MF		 2558 ++dc.ccount_delta;
2559
2560 if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
2561 gen_io_start();
2562 }
2563
35b5c044
MF		 2564 if (dc.icount) {
2565 int label = gen_new_label();
2566
2567 tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1);
2568 tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label);
2569 tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]);
2570 if (dc.debug) {
2571 gen_debug_exception(&dc, DEBUGCAUSE_IC);
2572 }
2573 gen_set_label(label);
2574 }
2575
e61dc8f7
MF		 2576 if (dc.debug) {
2577 gen_ibreak_check(env, &dc);
2578 }
2579
dedc5eae
MF		 2580 disas_xtensa_insn(&dc);
2581 ++insn_count;
35b5c044
MF		 2582 if (dc.icount) {
2583 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
2584 }
dedc5eae
MF		 2585 if (env->singlestep_enabled) {
2586 tcg_gen_movi_i32(cpu_pc, dc.pc);
b994e91b 2587 gen_exception(&dc, EXCP_DEBUG);
dedc5eae
MF		 2588 break;
2589 }
2590 } while (dc.is_jmp == DISAS_NEXT &&
2591 insn_count < max_insns &&
2592 dc.pc < next_page_start &&
2593 gen_opc_ptr < gen_opc_end);
2594
6ad6dbf7 2595 reset_litbase(&dc);
3580ecad 2596 reset_sar_tracker(&dc);
35b5c044
MF		 2597 if (dc.icount) {
2598 tcg_temp_free(dc.next_icount);
2599 }
3580ecad 2600
b994e91b
MF		 2601 if (tb->cflags & CF_LAST_IO) {
2602 gen_io_end();
2603 }
2604
dedc5eae
MF		 2605 if (dc.is_jmp == DISAS_NEXT) {
2606 gen_jumpi(&dc, dc.pc, 0);
2607 }
2608 gen_icount_end(tb, insn_count);
2609 *gen_opc_ptr = INDEX_op_end;
2610
2611 if (!search_pc) {
2612 tb->size = dc.pc - pc_start;
2613 tb->icount = insn_count;
2614 }
2328826b
MF		 2615}
2616
2617void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
2618{
dedc5eae 2619 gen_intermediate_code_internal(env, tb, 0);
2328826b
MF		 2620}
2621
2622void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
2623{
dedc5eae 2624 gen_intermediate_code_internal(env, tb, 1);
2328826b
MF		 2625}
2626
2627void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
2628 int flags)
2629{
2af3da91
MF		 2630 int i, j;
2631
2632 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
2633
2634 for (i = j = 0; i < 256; ++i) {
2635 if (sregnames[i]) {
2636 cpu_fprintf(f, "%s=%08x%c", sregnames[i], env->sregs[i],
2637 (j++ % 4) == 3 ? '\n' : ' ');
2638 }
2639 }
2640
2641 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2642
2643 for (i = j = 0; i < 256; ++i) {
2644 if (uregnames[i]) {
2645 cpu_fprintf(f, "%s=%08x%c", uregnames[i], env->uregs[i],
2646 (j++ % 4) == 3 ? '\n' : ' ');
2647 }
2648 }
2328826b 2649
2af3da91 2650 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2328826b
MF		 2651
2652 for (i = 0; i < 16; ++i) {
2653 cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
2654 (i % 4) == 3 ? '\n' : ' ');
2655 }
553e44f9
MF		 2656
2657 cpu_fprintf(f, "\n");
2658
2659 for (i = 0; i < env->config->nareg; ++i) {
2660 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
2661 (i % 4) == 3 ? '\n' : ' ');
2662 }
2328826b
MF		 2663}
2664
2665void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
2666{
2667 env->pc = gen_opc_pc[pc_pos];
2668}
Qemu copy for testing