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target-xtensa: better control rsr/wsr/xsr access to SRs
[qemu.git] / target-xtensa / translate.c
CommitLineData
2328826b
MF		 1/*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <stdio.h>
32
33#include "cpu.h"
34#include "exec-all.h"
35#include "disas.h"
36#include "tcg-op.h"
37#include "qemu-log.h"
1ddeaa5d 38#include "sysemu.h"
2328826b 39
16c1deae 40#include "helper.h"
dedc5eae 41#define GEN_HELPER 1
16c1deae 42#include "helper.h"
dedc5eae
MF		 43
44typedef struct DisasContext {
45 const XtensaConfig *config;
46 TranslationBlock *tb;
47 uint32_t pc;
48 uint32_t next_pc;
f0a548b9
MF		 49 int cring;
50 int ring;
797d780b
MF		 51 uint32_t lbeg;
52 uint32_t lend;
6ad6dbf7 53 TCGv_i32 litbase;
dedc5eae
MF		 54 int is_jmp;
55 int singlestep_enabled;
3580ecad
MF		 56
57 bool sar_5bit;
58 bool sar_m32_5bit;
59 bool sar_m32_allocated;
60 TCGv_i32 sar_m32;
b994e91b
MF		 61
62 uint32_t ccount_delta;
772177c1 63 unsigned used_window;
e61dc8f7
MF		 64
65 bool debug;
35b5c044
MF		 66 bool icount;
67 TCGv_i32 next_icount;
ef04a846
MF		 68
69 unsigned cpenable;
dedc5eae
MF		 70} DisasContext;
71
72static TCGv_ptr cpu_env;
73static TCGv_i32 cpu_pc;
74static TCGv_i32 cpu_R[16];
dd519cbe 75static TCGv_i32 cpu_FR[16];
2af3da91
MF		 76static TCGv_i32 cpu_SR[256];
77static TCGv_i32 cpu_UR[256];
dedc5eae
MF		 78
79#include "gen-icount.h"
2328826b 80
fe0bd475
MF		 81typedef struct XtensaReg {
82 const char *name;
83 uint64_t opt_bits;
53593e90
MF		 84 enum {
85 SR_R = 1,
86 SR_W = 2,
87 SR_X = 4,
88 SR_RW = 3,
89 SR_RWX = 7,
90 } access;
fe0bd475
MF		 91} XtensaReg;
92
53593e90 93#define XTENSA_REG_ACCESS(regname, opt, acc) { \
fe0bd475
MF		 94 .name = (regname), \
95 .opt_bits = XTENSA_OPTION_BIT(opt), \
53593e90 96 .access = (acc), \
fe0bd475
MF		 97 }
98
53593e90
MF		 99#define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
100
fe0bd475
MF		 101#define XTENSA_REG_BITS(regname, opt) { \
102 .name = (regname), \
103 .opt_bits = (opt), \
53593e90 104 .access = SR_RWX, \
fe0bd475
MF		 105 }
106
107static const XtensaReg sregnames[256] = {
108 [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP),
109 [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP),
110 [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP),
111 [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL),
112 [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN),
113 [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R),
114 [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE),
115 [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16),
116 [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16),
117 [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16),
118 [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16),
119 [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16),
120 [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16),
121 [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER),
122 [WINDOW_START] = XTENSA_REG("WINDOW_START",
123 XTENSA_OPTION_WINDOWED_REGISTER),
124 [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU),
125 [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU),
126 [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU),
127 [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU),
128 [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG),
129 [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR),
130 [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL),
131 [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG),
132 [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG),
133 [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG),
134 [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG),
135 [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG),
136 [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG),
137 [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION),
138 [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
139 [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
140 [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
141 [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
142 [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
143 [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
144 [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION),
145 [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
146 [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
147 [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
148 [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
149 [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
150 [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
151 [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION),
152 [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2",
153 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
154 [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3",
155 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
156 [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4",
157 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
158 [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5",
159 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
160 [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6",
161 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
162 [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7",
163 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
164 [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR),
53593e90
MF		 165 [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW),
166 [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W),
fe0bd475
MF		 167 [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT),
168 [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL),
169 [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR),
170 [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION),
53593e90 171 [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R),
fe0bd475 172 [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT),
53593e90 173 [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R),
fe0bd475
MF		 174 [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG),
175 [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG),
176 [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION),
177 [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT),
178 [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1",
179 XTENSA_OPTION_TIMER_INTERRUPT),
180 [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2",
181 XTENSA_OPTION_TIMER_INTERRUPT),
2af3da91
MF		 182};
183
fe0bd475
MF		 184static const XtensaReg uregnames[256] = {
185 [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER),
186 [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR),
187 [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR),
2af3da91
MF		 188};
189
2328826b
MF		 190void xtensa_translate_init(void)
191{
dedc5eae
MF		 192 static const char * const regnames[] = {
193 "ar0", "ar1", "ar2", "ar3",
194 "ar4", "ar5", "ar6", "ar7",
195 "ar8", "ar9", "ar10", "ar11",
196 "ar12", "ar13", "ar14", "ar15",
197 };
dd519cbe
MF		 198 static const char * const fregnames[] = {
199 "f0", "f1", "f2", "f3",
200 "f4", "f5", "f6", "f7",
201 "f8", "f9", "f10", "f11",
202 "f12", "f13", "f14", "f15",
203 };
dedc5eae
MF		 204 int i;
205
206 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
207 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
97129ac8 208 offsetof(CPUXtensaState, pc), "pc");
dedc5eae
MF		 209
210 for (i = 0; i < 16; i++) {
211 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
97129ac8 212 offsetof(CPUXtensaState, regs[i]),
dedc5eae
MF		 213 regnames[i]);
214 }
2af3da91 215
dd519cbe
MF		 216 for (i = 0; i < 16; i++) {
217 cpu_FR[i] = tcg_global_mem_new_i32(TCG_AREG0,
218 offsetof(CPUXtensaState, fregs[i]),
219 fregnames[i]);
220 }
221
2af3da91 222 for (i = 0; i < 256; ++i) {
fe0bd475 223 if (sregnames[i].name) {
2af3da91 224 cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
97129ac8 225 offsetof(CPUXtensaState, sregs[i]),
fe0bd475 226 sregnames[i].name);
2af3da91
MF		 227 }
228 }
229
230 for (i = 0; i < 256; ++i) {
fe0bd475 231 if (uregnames[i].name) {
2af3da91 232 cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
97129ac8 233 offsetof(CPUXtensaState, uregs[i]),
fe0bd475 234 uregnames[i].name);
2af3da91
MF		 235 }
236 }
dedc5eae 237#define GEN_HELPER 2
16c1deae 238#include "helper.h"
dedc5eae
MF		 239}
240
b67ea0cd
MF		 241static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
242{
243 return xtensa_option_bits_enabled(dc->config, opt);
244}
245
dedc5eae
MF		 246static inline bool option_enabled(DisasContext *dc, int opt)
247{
248 return xtensa_option_enabled(dc->config, opt);
249}
250
6ad6dbf7
MF		 251static void init_litbase(DisasContext *dc)
252{
253 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
254 dc->litbase = tcg_temp_local_new_i32();
255 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
256 }
257}
258
259static void reset_litbase(DisasContext *dc)
260{
261 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
262 tcg_temp_free(dc->litbase);
263 }
264}
265
3580ecad
MF		 266static void init_sar_tracker(DisasContext *dc)
267{
268 dc->sar_5bit = false;
269 dc->sar_m32_5bit = false;
270 dc->sar_m32_allocated = false;
271}
272
273static void reset_sar_tracker(DisasContext *dc)
274{
275 if (dc->sar_m32_allocated) {
276 tcg_temp_free(dc->sar_m32);
277 }
278}
279
280static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
281{
282 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
283 if (dc->sar_m32_5bit) {
284 tcg_gen_discard_i32(dc->sar_m32);
285 }
286 dc->sar_5bit = true;
287 dc->sar_m32_5bit = false;
288}
289
290static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
291{
292 TCGv_i32 tmp = tcg_const_i32(32);
293 if (!dc->sar_m32_allocated) {
294 dc->sar_m32 = tcg_temp_local_new_i32();
295 dc->sar_m32_allocated = true;
296 }
297 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
298 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
299 dc->sar_5bit = false;
300 dc->sar_m32_5bit = true;
301 tcg_temp_free(tmp);
302}
303
b994e91b
MF		 304static void gen_advance_ccount(DisasContext *dc)
305{
306 if (dc->ccount_delta > 0) {
307 TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
308 dc->ccount_delta = 0;
f492b82d 309 gen_helper_advance_ccount(cpu_env, tmp);
b994e91b
MF		 310 tcg_temp_free(tmp);
311 }
312}
313
772177c1
MF		 314static void reset_used_window(DisasContext *dc)
315{
316 dc->used_window = 0;
317}
318
b994e91b 319static void gen_exception(DisasContext *dc, int excp)
dedc5eae
MF		 320{
321 TCGv_i32 tmp = tcg_const_i32(excp);
b994e91b 322 gen_advance_ccount(dc);
f492b82d 323 gen_helper_exception(cpu_env, tmp);
dedc5eae
MF		 324 tcg_temp_free(tmp);
325}
326
40643d7c
MF		 327static void gen_exception_cause(DisasContext *dc, uint32_t cause)
328{
329 TCGv_i32 tpc = tcg_const_i32(dc->pc);
330 TCGv_i32 tcause = tcg_const_i32(cause);
b994e91b 331 gen_advance_ccount(dc);
f492b82d 332 gen_helper_exception_cause(cpu_env, tpc, tcause);
40643d7c
MF		 333 tcg_temp_free(tpc);
334 tcg_temp_free(tcause);
6b814719
MF		 335 if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
336 cause == SYSCALL_CAUSE) {
337 dc->is_jmp = DISAS_UPDATE;
338 }
40643d7c
MF		 339}
340
5b4e481b
MF		 341static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
342 TCGv_i32 vaddr)
343{
344 TCGv_i32 tpc = tcg_const_i32(dc->pc);
345 TCGv_i32 tcause = tcg_const_i32(cause);
b994e91b 346 gen_advance_ccount(dc);
f492b82d 347 gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr);
5b4e481b
MF		 348 tcg_temp_free(tpc);
349 tcg_temp_free(tcause);
350}
351
e61dc8f7
MF		 352static void gen_debug_exception(DisasContext *dc, uint32_t cause)
353{
354 TCGv_i32 tpc = tcg_const_i32(dc->pc);
355 TCGv_i32 tcause = tcg_const_i32(cause);
356 gen_advance_ccount(dc);
f492b82d 357 gen_helper_debug_exception(cpu_env, tpc, tcause);
e61dc8f7
MF		 358 tcg_temp_free(tpc);
359 tcg_temp_free(tcause);
360 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
361 dc->is_jmp = DISAS_UPDATE;
362 }
363}
364
40643d7c
MF		 365static void gen_check_privilege(DisasContext *dc)
366{
367 if (dc->cring) {
368 gen_exception_cause(dc, PRIVILEGED_CAUSE);
6b814719 369 dc->is_jmp = DISAS_UPDATE;
40643d7c
MF		 370 }
371}
372
ef04a846
MF		 373static void gen_check_cpenable(DisasContext *dc, unsigned cp)
374{
375 if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) &&
376 !(dc->cpenable & (1 << cp))) {
377 gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp);
378 dc->is_jmp = DISAS_UPDATE;
379 }
380}
381
dedc5eae
MF		 382static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
383{
384 tcg_gen_mov_i32(cpu_pc, dest);
35b5c044
MF		 385 gen_advance_ccount(dc);
386 if (dc->icount) {
387 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
388 }
dedc5eae 389 if (dc->singlestep_enabled) {
b994e91b 390 gen_exception(dc, EXCP_DEBUG);
dedc5eae
MF		 391 } else {
392 if (slot >= 0) {
393 tcg_gen_goto_tb(slot);
394 tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);
395 } else {
396 tcg_gen_exit_tb(0);
397 }
398 }
399 dc->is_jmp = DISAS_UPDATE;
400}
401
67882fd1
MF		 402static void gen_jump(DisasContext *dc, TCGv dest)
403{
404 gen_jump_slot(dc, dest, -1);
405}
406
dedc5eae
MF		 407static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
408{
409 TCGv_i32 tmp = tcg_const_i32(dest);
410 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
411 slot = -1;
412 }
413 gen_jump_slot(dc, tmp, slot);
414 tcg_temp_free(tmp);
415}
416
553e44f9
MF		 417static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
418 int slot)
419{
420 TCGv_i32 tcallinc = tcg_const_i32(callinc);
421
422 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
423 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
424 tcg_temp_free(tcallinc);
425 tcg_gen_movi_i32(cpu_R[callinc << 2],
426 (callinc << 30) | (dc->next_pc & 0x3fffffff));
427 gen_jump_slot(dc, dest, slot);
428}
429
430static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
431{
432 gen_callw_slot(dc, callinc, dest, -1);
433}
434
435static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
436{
437 TCGv_i32 tmp = tcg_const_i32(dest);
438 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
439 slot = -1;
440 }
441 gen_callw_slot(dc, callinc, tmp, slot);
442 tcg_temp_free(tmp);
443}
444
797d780b
MF		 445static bool gen_check_loop_end(DisasContext *dc, int slot)
446{
447 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
448 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
449 dc->next_pc == dc->lend) {
450 int label = gen_new_label();
451
d865f307 452 gen_advance_ccount(dc);
797d780b
MF		 453 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
454 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
455 gen_jumpi(dc, dc->lbeg, slot);
456 gen_set_label(label);
457 gen_jumpi(dc, dc->next_pc, -1);
458 return true;
459 }
460 return false;
461}
462
463static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
464{
465 if (!gen_check_loop_end(dc, slot)) {
466 gen_jumpi(dc, dc->next_pc, slot);
467 }
468}
469
bd57fb91
MF		 470static void gen_brcond(DisasContext *dc, TCGCond cond,
471 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
472{
473 int label = gen_new_label();
474
d865f307 475 gen_advance_ccount(dc);
bd57fb91 476 tcg_gen_brcond_i32(cond, t0, t1, label);
797d780b 477 gen_jumpi_check_loop_end(dc, 0);
bd57fb91
MF		 478 gen_set_label(label);
479 gen_jumpi(dc, dc->pc + offset, 1);
480}
481
482static void gen_brcondi(DisasContext *dc, TCGCond cond,
483 TCGv_i32 t0, uint32_t t1, uint32_t offset)
484{
485 TCGv_i32 tmp = tcg_const_i32(t1);
486 gen_brcond(dc, cond, t0, tmp, offset);
487 tcg_temp_free(tmp);
488}
489
53593e90 490static void gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
fe0bd475
MF		 491{
492 if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {
493 if (sregnames[sr].name) {
494 qemu_log("SR %s is not configured\n", sregnames[sr].name);
495 } else {
496 qemu_log("SR %d is not implemented\n", sr);
497 }
498 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
53593e90
MF		 499 } else if (!(sregnames[sr].access & access)) {
500 static const char * const access_text[] = {
501 [SR_R] = "rsr",
502 [SR_W] = "wsr",
503 [SR_X] = "xsr",
504 };
505 assert(access < ARRAY_SIZE(access_text) && access_text[access]);
506 qemu_log("SR %s is not available for %s\n", sregnames[sr].name,
507 access_text[access]);
508 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
fe0bd475
MF		 509 }
510}
511
b994e91b
MF		 512static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
513{
514 gen_advance_ccount(dc);
515 tcg_gen_mov_i32(d, cpu_SR[sr]);
516}
517
b67ea0cd
MF		 518static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
519{
520 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
521 tcg_gen_or_i32(d, d, cpu_SR[sr]);
522 tcg_gen_andi_i32(d, d, 0xfffffffc);
523}
524
b8132eff
MF		 525static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
526{
527 static void (* const rsr_handler[256])(DisasContext *dc,
528 TCGv_i32 d, uint32_t sr) = {
b994e91b 529 [CCOUNT] = gen_rsr_ccount,
b67ea0cd 530 [PTEVADDR] = gen_rsr_ptevaddr,
b8132eff
MF		 531 };
532
fe0bd475
MF		 533 if (rsr_handler[sr]) {
534 rsr_handler[sr](dc, d, sr);
b8132eff 535 } else {
fe0bd475 536 tcg_gen_mov_i32(d, cpu_SR[sr]);
b8132eff
MF		 537 }
538}
539
797d780b
MF		 540static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
541{
f492b82d 542 gen_helper_wsr_lbeg(cpu_env, s);
3d0be8a5 543 gen_jumpi_check_loop_end(dc, 0);
797d780b
MF		 544}
545
546static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
547{
f492b82d 548 gen_helper_wsr_lend(cpu_env, s);
3d0be8a5 549 gen_jumpi_check_loop_end(dc, 0);
797d780b
MF		 550}
551
3580ecad
MF		 552static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
553{
554 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
555 if (dc->sar_m32_5bit) {
556 tcg_gen_discard_i32(dc->sar_m32);
557 }
558 dc->sar_5bit = false;
559 dc->sar_m32_5bit = false;
560}
561
4dd85b6b
MF		 562static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
563{
564 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
565}
566
6ad6dbf7
MF		 567static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
568{
569 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
570 /* This can change tb->flags, so exit tb */
571 gen_jumpi_check_loop_end(dc, -1);
572}
573
6825b6c3
MF		 574static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
575{
576 tcg_gen_ext8s_i32(cpu_SR[sr], s);
577}
578
553e44f9
MF		 579static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
580{
f492b82d 581 gen_helper_wsr_windowbase(cpu_env, v);
772177c1
MF		 582 reset_used_window(dc);
583}
584
585static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
586{
53a72dfd 587 tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
772177c1 588 reset_used_window(dc);
553e44f9
MF		 589}
590
b67ea0cd
MF		 591static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
592{
593 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
594}
595
596static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
597{
f492b82d 598 gen_helper_wsr_rasid(cpu_env, v);
b67ea0cd
MF		 599 /* This can change tb->flags, so exit tb */
600 gen_jumpi_check_loop_end(dc, -1);
601}
602
603static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
604{
605 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
606}
607
e61dc8f7
MF		 608static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
609{
f492b82d 610 gen_helper_wsr_ibreakenable(cpu_env, v);
e61dc8f7
MF		 611 gen_jumpi_check_loop_end(dc, 0);
612}
613
fcc803d1
MF		 614static void gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
615{
616 tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f);
617}
618
e61dc8f7
MF		 619static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
620{
621 unsigned id = sr - IBREAKA;
622
623 if (id < dc->config->nibreak) {
624 TCGv_i32 tmp = tcg_const_i32(id);
f492b82d 625 gen_helper_wsr_ibreaka(cpu_env, tmp, v);
e61dc8f7
MF		 626 tcg_temp_free(tmp);
627 gen_jumpi_check_loop_end(dc, 0);
628 }
629}
630
f14c4b5f
MF		 631static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
632{
633 unsigned id = sr - DBREAKA;
634
635 if (id < dc->config->ndbreak) {
636 TCGv_i32 tmp = tcg_const_i32(id);
f492b82d 637 gen_helper_wsr_dbreaka(cpu_env, tmp, v);
f14c4b5f
MF		 638 tcg_temp_free(tmp);
639 }
640}
641
642static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
643{
644 unsigned id = sr - DBREAKC;
645
646 if (id < dc->config->ndbreak) {
647 TCGv_i32 tmp = tcg_const_i32(id);
f492b82d 648 gen_helper_wsr_dbreakc(cpu_env, tmp, v);
f14c4b5f
MF		 649 tcg_temp_free(tmp);
650 }
651}
652
ef04a846
MF		 653static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
654{
655 tcg_gen_andi_i32(cpu_SR[sr], v, 0xff);
656 /* This can change tb->flags, so exit tb */
657 gen_jumpi_check_loop_end(dc, -1);
658}
659
b994e91b
MF		 660static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
661{
662 tcg_gen_andi_i32(cpu_SR[sr], v,
663 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
664 gen_helper_check_interrupts(cpu_env);
665 gen_jumpi_check_loop_end(dc, 0);
666}
667
668static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
669{
670 TCGv_i32 tmp = tcg_temp_new_i32();
671
672 tcg_gen_andi_i32(tmp, v,
673 dc->config->inttype_mask[INTTYPE_EDGE] |
674 dc->config->inttype_mask[INTTYPE_NMI] |
675 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
676 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
677 tcg_temp_free(tmp);
678 gen_helper_check_interrupts(cpu_env);
679}
680
681static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
682{
683 tcg_gen_mov_i32(cpu_SR[sr], v);
684 gen_helper_check_interrupts(cpu_env);
685 gen_jumpi_check_loop_end(dc, 0);
686}
687
f0a548b9
MF		 688static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
689{
690 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
691 PS_UM | PS_EXCM | PS_INTLEVEL;
692
693 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
694 mask |= PS_RING;
695 }
696 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
772177c1 697 reset_used_window(dc);
b994e91b
MF		 698 gen_helper_check_interrupts(cpu_env);
699 /* This can change mmu index and tb->flags, so exit tb */
797d780b 700 gen_jumpi_check_loop_end(dc, -1);
f0a548b9
MF		 701}
702
35b5c044
MF		 703static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
704{
705 if (dc->icount) {
706 tcg_gen_mov_i32(dc->next_icount, v);
707 } else {
708 tcg_gen_mov_i32(cpu_SR[sr], v);
709 }
710}
711
712static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
713{
714 tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
715 /* This can change tb->flags, so exit tb */
716 gen_jumpi_check_loop_end(dc, -1);
717}
718
b994e91b
MF		 719static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
720{
721 uint32_t id = sr - CCOMPARE;
722 if (id < dc->config->nccompare) {
723 uint32_t int_bit = 1 << dc->config->timerint[id];
724 gen_advance_ccount(dc);
725 tcg_gen_mov_i32(cpu_SR[sr], v);
726 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
727 gen_helper_check_interrupts(cpu_env);
728 }
729}
730
b8132eff
MF		 731static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
732{
733 static void (* const wsr_handler[256])(DisasContext *dc,
734 uint32_t sr, TCGv_i32 v) = {
797d780b
MF		 735 [LBEG] = gen_wsr_lbeg,
736 [LEND] = gen_wsr_lend,
3580ecad 737 [SAR] = gen_wsr_sar,
4dd85b6b 738 [BR] = gen_wsr_br,
6ad6dbf7 739 [LITBASE] = gen_wsr_litbase,
6825b6c3 740 [ACCHI] = gen_wsr_acchi,
553e44f9 741 [WINDOW_BASE] = gen_wsr_windowbase,
772177c1 742 [WINDOW_START] = gen_wsr_windowstart,
b67ea0cd
MF		 743 [PTEVADDR] = gen_wsr_ptevaddr,
744 [RASID] = gen_wsr_rasid,
745 [ITLBCFG] = gen_wsr_tlbcfg,
746 [DTLBCFG] = gen_wsr_tlbcfg,
e61dc8f7 747 [IBREAKENABLE] = gen_wsr_ibreakenable,
fcc803d1 748 [ATOMCTL] = gen_wsr_atomctl,
e61dc8f7
MF		 749 [IBREAKA] = gen_wsr_ibreaka,
750 [IBREAKA + 1] = gen_wsr_ibreaka,
f14c4b5f
MF		 751 [DBREAKA] = gen_wsr_dbreaka,
752 [DBREAKA + 1] = gen_wsr_dbreaka,
753 [DBREAKC] = gen_wsr_dbreakc,
754 [DBREAKC + 1] = gen_wsr_dbreakc,
ef04a846 755 [CPENABLE] = gen_wsr_cpenable,
b994e91b
MF		 756 [INTSET] = gen_wsr_intset,
757 [INTCLEAR] = gen_wsr_intclear,
758 [INTENABLE] = gen_wsr_intenable,
f0a548b9 759 [PS] = gen_wsr_ps,
35b5c044
MF		 760 [ICOUNT] = gen_wsr_icount,
761 [ICOUNTLEVEL] = gen_wsr_icountlevel,
b994e91b
MF		 762 [CCOMPARE] = gen_wsr_ccompare,
763 [CCOMPARE + 1] = gen_wsr_ccompare,
764 [CCOMPARE + 2] = gen_wsr_ccompare,
b8132eff
MF		 765 };
766
fe0bd475
MF		 767 if (wsr_handler[sr]) {
768 wsr_handler[sr](dc, sr, s);
b8132eff 769 } else {
fe0bd475 770 tcg_gen_mov_i32(cpu_SR[sr], s);
b8132eff
MF		 771 }
772}
773
dd519cbe
MF		 774static void gen_wur(uint32_t ur, TCGv_i32 s)
775{
776 switch (ur) {
777 case FCR:
778 gen_helper_wur_fcr(cpu_env, s);
779 break;
780
781 case FSR:
782 tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80);
783 break;
784
785 default:
786 tcg_gen_mov_i32(cpu_UR[ur], s);
787 break;
788 }
789}
790
5b4e481b
MF		 791static void gen_load_store_alignment(DisasContext *dc, int shift,
792 TCGv_i32 addr, bool no_hw_alignment)
793{
794 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
795 tcg_gen_andi_i32(addr, addr, ~0 << shift);
796 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
797 no_hw_alignment) {
798 int label = gen_new_label();
799 TCGv_i32 tmp = tcg_temp_new_i32();
800 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
801 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
802 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
803 gen_set_label(label);
804 tcg_temp_free(tmp);
805 }
806}
807
b994e91b
MF		 808static void gen_waiti(DisasContext *dc, uint32_t imm4)
809{
810 TCGv_i32 pc = tcg_const_i32(dc->next_pc);
811 TCGv_i32 intlevel = tcg_const_i32(imm4);
812 gen_advance_ccount(dc);
f492b82d 813 gen_helper_waiti(cpu_env, pc, intlevel);
b994e91b
MF		 814 tcg_temp_free(pc);
815 tcg_temp_free(intlevel);
816}
817
772177c1
MF		 818static void gen_window_check1(DisasContext *dc, unsigned r1)
819{
820 if (dc->tb->flags & XTENSA_TBFLAG_EXCM) {
821 return;
822 }
823 if (option_enabled(dc, XTENSA_OPTION_WINDOWED_REGISTER) &&
824 r1 / 4 > dc->used_window) {
825 TCGv_i32 pc = tcg_const_i32(dc->pc);
826 TCGv_i32 w = tcg_const_i32(r1 / 4);
827
828 dc->used_window = r1 / 4;
829 gen_advance_ccount(dc);
f492b82d 830 gen_helper_window_check(cpu_env, pc, w);
772177c1
MF		 831
832 tcg_temp_free(w);
833 tcg_temp_free(pc);
834 }
835}
836
837static void gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
838{
839 gen_window_check1(dc, r1 > r2 ? r1 : r2);
840}
841
842static void gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
843 unsigned r3)
844{
845 gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
846}
847
6825b6c3
MF		 848static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
849{
850 TCGv_i32 m = tcg_temp_new_i32();
851
852 if (hi) {
853 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
854 } else {
855 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
856 }
857 return m;
858}
859
0c4fabea 860static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
dedc5eae 861{
b67ea0cd
MF		 862#define HAS_OPTION_BITS(opt) do { \
863 if (!option_bits_enabled(dc, opt)) { \
864 qemu_log("Option is not enabled %s:%d\n", \
865 __FILE__, __LINE__); \
dedc5eae
MF		 866 goto invalid_opcode; \
867 } \
868 } while (0)
869
b67ea0cd
MF		 870#define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
871
91a5bb76
MF		 872#define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
873#define RESERVED() do { \
874 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
875 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
876 goto invalid_opcode; \
877 } while (0)
878
879
dedc5eae
MF		 880#ifdef TARGET_WORDS_BIGENDIAN
881#define OP0 (((b0) & 0xf0) >> 4)
882#define OP1 (((b2) & 0xf0) >> 4)
883#define OP2 ((b2) & 0xf)
884#define RRR_R ((b1) & 0xf)
885#define RRR_S (((b1) & 0xf0) >> 4)
886#define RRR_T ((b0) & 0xf)
887#else
888#define OP0 (((b0) & 0xf))
889#define OP1 (((b2) & 0xf))
890#define OP2 (((b2) & 0xf0) >> 4)
891#define RRR_R (((b1) & 0xf0) >> 4)
892#define RRR_S (((b1) & 0xf))
893#define RRR_T (((b0) & 0xf0) >> 4)
894#endif
6825b6c3
MF		 895#define RRR_X ((RRR_R & 0x4) >> 2)
896#define RRR_Y ((RRR_T & 0x4) >> 2)
897#define RRR_W (RRR_R & 0x3)
dedc5eae
MF		 898
899#define RRRN_R RRR_R
900#define RRRN_S RRR_S
901#define RRRN_T RRR_T
902
903#define RRI8_R RRR_R
904#define RRI8_S RRR_S
905#define RRI8_T RRR_T
906#define RRI8_IMM8 (b2)
907#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
908
909#ifdef TARGET_WORDS_BIGENDIAN
910#define RI16_IMM16 (((b1) << 8) | (b2))
911#else
912#define RI16_IMM16 (((b2) << 8) | (b1))
913#endif
914
915#ifdef TARGET_WORDS_BIGENDIAN
916#define CALL_N (((b0) & 0xc) >> 2)
917#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
918#else
919#define CALL_N (((b0) & 0x30) >> 4)
920#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
921#endif
922#define CALL_OFFSET_SE \
923 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
924
925#define CALLX_N CALL_N
926#ifdef TARGET_WORDS_BIGENDIAN
927#define CALLX_M ((b0) & 0x3)
928#else
929#define CALLX_M (((b0) & 0xc0) >> 6)
930#endif
931#define CALLX_S RRR_S
932
933#define BRI12_M CALLX_M
934#define BRI12_S RRR_S
935#ifdef TARGET_WORDS_BIGENDIAN
936#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
937#else
938#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
939#endif
940#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
941
942#define BRI8_M BRI12_M
943#define BRI8_R RRI8_R
944#define BRI8_S RRI8_S
945#define BRI8_IMM8 RRI8_IMM8
946#define BRI8_IMM8_SE RRI8_IMM8_SE
947
948#define RSR_SR (b1)
949
0c4fabea
BS		 950 uint8_t b0 = cpu_ldub_code(env, dc->pc);
951 uint8_t b1 = cpu_ldub_code(env, dc->pc + 1);
a044ec2a 952 uint8_t b2 = 0;
dedc5eae 953
bd57fb91
MF		 954 static const uint32_t B4CONST[] = {
955 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
956 };
957
958 static const uint32_t B4CONSTU[] = {
959 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
960 };
961
dedc5eae
MF		 962 if (OP0 >= 8) {
963 dc->next_pc = dc->pc + 2;
964 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
965 } else {
966 dc->next_pc = dc->pc + 3;
0c4fabea 967 b2 = cpu_ldub_code(env, dc->pc + 2);
dedc5eae
MF		 968 }
969
970 switch (OP0) {
971 case 0: /*QRST*/
972 switch (OP1) {
973 case 0: /*RST0*/
974 switch (OP2) {
975 case 0: /*ST0*/
976 if ((RRR_R & 0xc) == 0x8) {
977 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
978 }
979
980 switch (RRR_R) {
981 case 0: /*SNM0*/
5da4a6a8
MF		 982 switch (CALLX_M) {
983 case 0: /*ILL*/
40643d7c 984 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
5da4a6a8
MF		 985 break;
986
987 case 1: /*reserved*/
91a5bb76 988 RESERVED();
5da4a6a8
MF		 989 break;
990
991 case 2: /*JR*/
992 switch (CALLX_N) {
993 case 0: /*RET*/
994 case 2: /*JX*/
772177c1 995 gen_window_check1(dc, CALLX_S);
5da4a6a8
MF		 996 gen_jump(dc, cpu_R[CALLX_S]);
997 break;
998
999 case 1: /*RETWw*/
1000 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1001 {
1002 TCGv_i32 tmp = tcg_const_i32(dc->pc);
b994e91b 1003 gen_advance_ccount(dc);
f492b82d 1004 gen_helper_retw(tmp, cpu_env, tmp);
553e44f9
MF		 1005 gen_jump(dc, tmp);
1006 tcg_temp_free(tmp);
1007 }
5da4a6a8
MF		 1008 break;
1009
1010 case 3: /*reserved*/
91a5bb76 1011 RESERVED();
5da4a6a8
MF		 1012 break;
1013 }
1014 break;
1015
1016 case 3: /*CALLX*/
772177c1 1017 gen_window_check2(dc, CALLX_S, CALLX_N << 2);
5da4a6a8
MF		 1018 switch (CALLX_N) {
1019 case 0: /*CALLX0*/
1020 {
1021 TCGv_i32 tmp = tcg_temp_new_i32();
1022 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1023 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
1024 gen_jump(dc, tmp);
1025 tcg_temp_free(tmp);
1026 }
1027 break;
1028
1029 case 1: /*CALLX4w*/
1030 case 2: /*CALLX8w*/
1031 case 3: /*CALLX12w*/
1032 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1033 {
1034 TCGv_i32 tmp = tcg_temp_new_i32();
1035
1036 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1037 gen_callw(dc, CALLX_N, tmp);
1038 tcg_temp_free(tmp);
1039 }
5da4a6a8
MF		 1040 break;
1041 }
1042 break;
1043 }
dedc5eae
MF		 1044 break;
1045
1046 case 1: /*MOVSPw*/
1047 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
772177c1 1048 gen_window_check2(dc, RRR_T, RRR_S);
553e44f9
MF		 1049 {
1050 TCGv_i32 pc = tcg_const_i32(dc->pc);
b994e91b 1051 gen_advance_ccount(dc);
f492b82d 1052 gen_helper_movsp(cpu_env, pc);
553e44f9
MF		 1053 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
1054 tcg_temp_free(pc);
1055 }
dedc5eae
MF		 1056 break;
1057
1058 case 2: /*SYNC*/
28067b22
MF		 1059 switch (RRR_T) {
1060 case 0: /*ISYNC*/
1061 break;
1062
1063 case 1: /*RSYNC*/
1064 break;
1065
1066 case 2: /*ESYNC*/
1067 break;
1068
1069 case 3: /*DSYNC*/
1070 break;
1071
1072 case 8: /*EXCW*/
1073 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1074 break;
1075
1076 case 12: /*MEMW*/
1077 break;
1078
1079 case 13: /*EXTW*/
1080 break;
1081
1082 case 15: /*NOP*/
1083 break;
1084
1085 default: /*reserved*/
1086 RESERVED();
1087 break;
1088 }
91a5bb76
MF		 1089 break;
1090
1091 case 3: /*RFEIx*/
40643d7c
MF		 1092 switch (RRR_T) {
1093 case 0: /*RFETx*/
1094 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1095 switch (RRR_S) {
1096 case 0: /*RFEx*/
1097 gen_check_privilege(dc);
1098 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
b994e91b 1099 gen_helper_check_interrupts(cpu_env);
40643d7c
MF		 1100 gen_jump(dc, cpu_SR[EPC1]);
1101 break;
1102
1103 case 1: /*RFUEx*/
1104 RESERVED();
1105 break;
1106
1107 case 2: /*RFDEx*/
1108 gen_check_privilege(dc);
1109 gen_jump(dc, cpu_SR[
1110 dc->config->ndepc ? DEPC : EPC1]);
1111 break;
1112
1113 case 4: /*RFWOw*/
1114 case 5: /*RFWUw*/
1115 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1116 gen_check_privilege(dc);
1117 {
1118 TCGv_i32 tmp = tcg_const_i32(1);
1119
1120 tcg_gen_andi_i32(
1121 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1122 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
1123
1124 if (RRR_S == 4) {
1125 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
1126 cpu_SR[WINDOW_START], tmp);
1127 } else {
1128 tcg_gen_or_i32(cpu_SR[WINDOW_START],
1129 cpu_SR[WINDOW_START], tmp);
1130 }
1131
f492b82d 1132 gen_helper_restore_owb(cpu_env);
b994e91b 1133 gen_helper_check_interrupts(cpu_env);
553e44f9
MF		 1134 gen_jump(dc, cpu_SR[EPC1]);
1135
1136 tcg_temp_free(tmp);
1137 }
40643d7c
MF		 1138 break;
1139
1140 default: /*reserved*/
1141 RESERVED();
1142 break;
1143 }
1144 break;
1145
1146 case 1: /*RFIx*/
1147 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
b994e91b
MF		 1148 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
1149 gen_check_privilege(dc);
1150 tcg_gen_mov_i32(cpu_SR[PS],
1151 cpu_SR[EPS2 + RRR_S - 2]);
1152 gen_helper_check_interrupts(cpu_env);
1153 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
1154 } else {
1155 qemu_log("RFI %d is illegal\n", RRR_S);
1156 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1157 }
40643d7c
MF		 1158 break;
1159
1160 case 2: /*RFME*/
1161 TBD();
1162 break;
1163
1164 default: /*reserved*/
1165 RESERVED();
1166 break;
1167
1168 }
91a5bb76
MF		 1169 break;
1170
1171 case 4: /*BREAKx*/
e61dc8f7
MF		 1172 HAS_OPTION(XTENSA_OPTION_DEBUG);
1173 if (dc->debug) {
1174 gen_debug_exception(dc, DEBUGCAUSE_BI);
1175 }
91a5bb76
MF		 1176 break;
1177
1178 case 5: /*SYSCALLx*/
1179 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
40643d7c
MF		 1180 switch (RRR_S) {
1181 case 0: /*SYSCALLx*/
1182 gen_exception_cause(dc, SYSCALL_CAUSE);
1183 break;
1184
1185 case 1: /*SIMCALL*/
1ddeaa5d
MF		 1186 if (semihosting_enabled) {
1187 gen_check_privilege(dc);
1188 gen_helper_simcall(cpu_env);
1189 } else {
1190 qemu_log("SIMCALL but semihosting is disabled\n");
1191 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1192 }
40643d7c
MF		 1193 break;
1194
1195 default:
1196 RESERVED();
1197 break;
1198 }
91a5bb76
MF		 1199 break;
1200
1201 case 6: /*RSILx*/
1202 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
40643d7c 1203 gen_check_privilege(dc);
772177c1 1204 gen_window_check1(dc, RRR_T);
40643d7c 1205 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
b994e91b 1206 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
40643d7c 1207 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
b994e91b
MF		 1208 gen_helper_check_interrupts(cpu_env);
1209 gen_jumpi_check_loop_end(dc, 0);
91a5bb76
MF		 1210 break;
1211
1212 case 7: /*WAITIx*/
1213 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
b994e91b
MF		 1214 gen_check_privilege(dc);
1215 gen_waiti(dc, RRR_S);
91a5bb76
MF		 1216 break;
1217
1218 case 8: /*ANY4p*/
91a5bb76 1219 case 9: /*ALL4p*/
91a5bb76 1220 case 10: /*ANY8p*/
91a5bb76
MF		 1221 case 11: /*ALL8p*/
1222 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 1223 {
1224 const unsigned shift = (RRR_R & 2) ? 8 : 4;
1225 TCGv_i32 mask = tcg_const_i32(
1226 ((1 << shift) - 1) << RRR_S);
1227 TCGv_i32 tmp = tcg_temp_new_i32();
1228
1229 tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
1230 if (RRR_R & 1) { /*ALL*/
1231 tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
1232 } else { /*ANY*/
1233 tcg_gen_add_i32(tmp, tmp, mask);
1234 }
1235 tcg_gen_shri_i32(tmp, tmp, RRR_S + shift);
1236 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
1237 tmp, RRR_T, 1);
1238 tcg_temp_free(mask);
1239 tcg_temp_free(tmp);
1240 }
91a5bb76
MF		 1241 break;
1242
1243 default: /*reserved*/
1244 RESERVED();
dedc5eae
MF		 1245 break;
1246
1247 }
1248 break;
1249
1250 case 1: /*AND*/
772177c1 1251 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1252 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1253 break;
1254
1255 case 2: /*OR*/
772177c1 1256 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1257 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1258 break;
1259
1260 case 3: /*XOR*/
772177c1 1261 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1262 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1263 break;
1264
1265 case 4: /*ST1*/
3580ecad
MF		 1266 switch (RRR_R) {
1267 case 0: /*SSR*/
772177c1 1268 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1269 gen_right_shift_sar(dc, cpu_R[RRR_S]);
1270 break;
1271
1272 case 1: /*SSL*/
772177c1 1273 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1274 gen_left_shift_sar(dc, cpu_R[RRR_S]);
1275 break;
1276
1277 case 2: /*SSA8L*/
772177c1 1278 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1279 {
1280 TCGv_i32 tmp = tcg_temp_new_i32();
1281 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1282 gen_right_shift_sar(dc, tmp);
1283 tcg_temp_free(tmp);
1284 }
1285 break;
1286
1287 case 3: /*SSA8B*/
772177c1 1288 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1289 {
1290 TCGv_i32 tmp = tcg_temp_new_i32();
1291 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1292 gen_left_shift_sar(dc, tmp);
1293 tcg_temp_free(tmp);
1294 }
1295 break;
1296
1297 case 4: /*SSAI*/
1298 {
1299 TCGv_i32 tmp = tcg_const_i32(
1300 RRR_S | ((RRR_T & 1) << 4));
1301 gen_right_shift_sar(dc, tmp);
1302 tcg_temp_free(tmp);
1303 }
1304 break;
1305
1306 case 6: /*RER*/
91a5bb76 1307 TBD();
3580ecad
MF		 1308 break;
1309
1310 case 7: /*WER*/
91a5bb76 1311 TBD();
3580ecad
MF		 1312 break;
1313
1314 case 8: /*ROTWw*/
1315 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1316 gen_check_privilege(dc);
1317 {
1318 TCGv_i32 tmp = tcg_const_i32(
1319 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
f492b82d 1320 gen_helper_rotw(cpu_env, tmp);
553e44f9 1321 tcg_temp_free(tmp);
772177c1 1322 reset_used_window(dc);
553e44f9 1323 }
3580ecad
MF		 1324 break;
1325
1326 case 14: /*NSAu*/
7f65f4b0 1327 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
772177c1 1328 gen_window_check2(dc, RRR_S, RRR_T);
3580ecad
MF		 1329 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1330 break;
1331
1332 case 15: /*NSAUu*/
7f65f4b0 1333 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
772177c1 1334 gen_window_check2(dc, RRR_S, RRR_T);
3580ecad
MF		 1335 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1336 break;
1337
1338 default: /*reserved*/
91a5bb76 1339 RESERVED();
3580ecad
MF		 1340 break;
1341 }
dedc5eae
MF		 1342 break;
1343
1344 case 5: /*TLB*/
b67ea0cd
MF		 1345 HAS_OPTION_BITS(
1346 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
1347 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1348 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION));
1349 gen_check_privilege(dc);
1350 gen_window_check2(dc, RRR_S, RRR_T);
1351 {
1352 TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0);
1353
1354 switch (RRR_R & 7) {
1355 case 3: /*RITLB0*/ /*RDTLB0*/
f492b82d
MF		 1356 gen_helper_rtlb0(cpu_R[RRR_T],
1357 cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1358 break;
1359
1360 case 4: /*IITLB*/ /*IDTLB*/
f492b82d 1361 gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1362 /* This could change memory mapping, so exit tb */
1363 gen_jumpi_check_loop_end(dc, -1);
1364 break;
1365
1366 case 5: /*PITLB*/ /*PDTLB*/
1367 tcg_gen_movi_i32(cpu_pc, dc->pc);
f492b82d
MF		 1368 gen_helper_ptlb(cpu_R[RRR_T],
1369 cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1370 break;
1371
1372 case 6: /*WITLB*/ /*WDTLB*/
f492b82d
MF		 1373 gen_helper_wtlb(
1374 cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1375 /* This could change memory mapping, so exit tb */
1376 gen_jumpi_check_loop_end(dc, -1);
1377 break;
1378
1379 case 7: /*RITLB1*/ /*RDTLB1*/
f492b82d
MF		 1380 gen_helper_rtlb1(cpu_R[RRR_T],
1381 cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1382 break;
1383
1384 default:
1385 tcg_temp_free(dtlb);
1386 RESERVED();
1387 break;
1388 }
1389 tcg_temp_free(dtlb);
1390 }
dedc5eae
MF		 1391 break;
1392
1393 case 6: /*RT0*/
772177c1 1394 gen_window_check2(dc, RRR_R, RRR_T);
f331fe5e
MF		 1395 switch (RRR_S) {
1396 case 0: /*NEG*/
1397 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1398 break;
1399
1400 case 1: /*ABS*/
1401 {
1402 int label = gen_new_label();
1403 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1404 tcg_gen_brcondi_i32(
1405 TCG_COND_GE, cpu_R[RRR_R], 0, label);
1406 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1407 gen_set_label(label);
1408 }
1409 break;
1410
1411 default: /*reserved*/
91a5bb76 1412 RESERVED();
f331fe5e
MF		 1413 break;
1414 }
dedc5eae
MF		 1415 break;
1416
1417 case 7: /*reserved*/
91a5bb76 1418 RESERVED();
dedc5eae
MF		 1419 break;
1420
1421 case 8: /*ADD*/
772177c1 1422 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1423 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1424 break;
1425
1426 case 9: /*ADD**/
1427 case 10:
1428 case 11:
772177c1 1429 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1430 {
1431 TCGv_i32 tmp = tcg_temp_new_i32();
1432 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1433 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1434 tcg_temp_free(tmp);
1435 }
1436 break;
1437
1438 case 12: /*SUB*/
772177c1 1439 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1440 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1441 break;
1442
1443 case 13: /*SUB**/
1444 case 14:
1445 case 15:
772177c1 1446 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1447 {
1448 TCGv_i32 tmp = tcg_temp_new_i32();
1449 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1450 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1451 tcg_temp_free(tmp);
1452 }
1453 break;
1454 }
1455 break;
1456
1457 case 1: /*RST1*/
3580ecad
MF		 1458 switch (OP2) {
1459 case 0: /*SLLI*/
1460 case 1:
772177c1 1461 gen_window_check2(dc, RRR_R, RRR_S);
3580ecad
MF		 1462 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1463 32 - (RRR_T | ((OP2 & 1) << 4)));
1464 break;
1465
1466 case 2: /*SRAI*/
1467 case 3:
772177c1 1468 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1469 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1470 RRR_S | ((OP2 & 1) << 4));
1471 break;
1472
1473 case 4: /*SRLI*/
772177c1 1474 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1475 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1476 break;
1477
1478 case 6: /*XSR*/
1479 {
1480 TCGv_i32 tmp = tcg_temp_new_i32();
53593e90 1481 gen_check_sr(dc, RSR_SR, SR_X);
40643d7c
MF		 1482 if (RSR_SR >= 64) {
1483 gen_check_privilege(dc);
1484 }
772177c1 1485 gen_window_check1(dc, RRR_T);
3580ecad
MF		 1486 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1487 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1488 gen_wsr(dc, RSR_SR, tmp);
1489 tcg_temp_free(tmp);
1490 }
1491 break;
1492
1493 /*
1494 * Note: 64 bit ops are used here solely because SAR values
1495 * have range 0..63
1496 */
1497#define gen_shift_reg(cmd, reg) do { \
1498 TCGv_i64 tmp = tcg_temp_new_i64(); \
1499 tcg_gen_extu_i32_i64(tmp, reg); \
1500 tcg_gen_##cmd##_i64(v, v, tmp); \
1501 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1502 tcg_temp_free_i64(v); \
1503 tcg_temp_free_i64(tmp); \
1504 } while (0)
1505
1506#define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1507
1508 case 8: /*SRC*/
772177c1 1509 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
3580ecad
MF		 1510 {
1511 TCGv_i64 v = tcg_temp_new_i64();
1512 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1513 gen_shift(shr);
1514 }
1515 break;
1516
1517 case 9: /*SRL*/
772177c1 1518 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1519 if (dc->sar_5bit) {
1520 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1521 } else {
1522 TCGv_i64 v = tcg_temp_new_i64();
1523 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1524 gen_shift(shr);
1525 }
1526 break;
1527
1528 case 10: /*SLL*/
772177c1 1529 gen_window_check2(dc, RRR_R, RRR_S);
3580ecad
MF		 1530 if (dc->sar_m32_5bit) {
1531 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1532 } else {
1533 TCGv_i64 v = tcg_temp_new_i64();
1534 TCGv_i32 s = tcg_const_i32(32);
1535 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1536 tcg_gen_andi_i32(s, s, 0x3f);
1537 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1538 gen_shift_reg(shl, s);
1539 tcg_temp_free(s);
1540 }
1541 break;
1542
1543 case 11: /*SRA*/
772177c1 1544 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1545 if (dc->sar_5bit) {
1546 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1547 } else {
1548 TCGv_i64 v = tcg_temp_new_i64();
1549 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1550 gen_shift(sar);
1551 }
1552 break;
1553#undef gen_shift
1554#undef gen_shift_reg
1555
1556 case 12: /*MUL16U*/
1557 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
772177c1 1558 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
3580ecad
MF		 1559 {
1560 TCGv_i32 v1 = tcg_temp_new_i32();
1561 TCGv_i32 v2 = tcg_temp_new_i32();
1562 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1563 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1564 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1565 tcg_temp_free(v2);
1566 tcg_temp_free(v1);
1567 }
1568 break;
1569
1570 case 13: /*MUL16S*/
1571 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
772177c1 1572 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
3580ecad
MF		 1573 {
1574 TCGv_i32 v1 = tcg_temp_new_i32();
1575 TCGv_i32 v2 = tcg_temp_new_i32();
1576 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1577 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1578 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1579 tcg_temp_free(v2);
1580 tcg_temp_free(v1);
1581 }
1582 break;
1583
1584 default: /*reserved*/
91a5bb76 1585 RESERVED();
3580ecad
MF		 1586 break;
1587 }
dedc5eae
MF		 1588 break;
1589
1590 case 2: /*RST2*/
4dd85b6b
MF		 1591 if (OP2 >= 8) {
1592 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1593 }
772177c1 1594
f76ebf55
MF		 1595 if (OP2 >= 12) {
1596 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
1597 int label = gen_new_label();
1598 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1599 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1600 gen_set_label(label);
1601 }
1602
1603 switch (OP2) {
4dd85b6b
MF		 1604#define BOOLEAN_LOGIC(fn, r, s, t) \
1605 do { \
1606 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1607 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1608 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1609 \
1610 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1611 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1612 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1613 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1614 tcg_temp_free(tmp1); \
1615 tcg_temp_free(tmp2); \
1616 } while (0)
1617
1618 case 0: /*ANDBp*/
1619 BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T);
1620 break;
1621
1622 case 1: /*ANDBCp*/
1623 BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T);
1624 break;
1625
1626 case 2: /*ORBp*/
1627 BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T);
1628 break;
1629
1630 case 3: /*ORBCp*/
1631 BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T);
1632 break;
1633
1634 case 4: /*XORBp*/
1635 BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T);
1636 break;
1637
1638#undef BOOLEAN_LOGIC
1639
f76ebf55
MF		 1640 case 8: /*MULLi*/
1641 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1642 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1643 break;
1644
1645 case 10: /*MULUHi*/
1646 case 11: /*MULSHi*/
7f65f4b0 1647 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
f76ebf55
MF		 1648 {
1649 TCGv_i64 r = tcg_temp_new_i64();
1650 TCGv_i64 s = tcg_temp_new_i64();
1651 TCGv_i64 t = tcg_temp_new_i64();
1652
1653 if (OP2 == 10) {
1654 tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]);
1655 tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]);
1656 } else {
1657 tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]);
1658 tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]);
1659 }
1660 tcg_gen_mul_i64(r, s, t);
1661 tcg_gen_shri_i64(r, r, 32);
1662 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r);
1663
1664 tcg_temp_free_i64(r);
1665 tcg_temp_free_i64(s);
1666 tcg_temp_free_i64(t);
1667 }
1668 break;
1669
1670 case 12: /*QUOUi*/
1671 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1672 break;
1673
1674 case 13: /*QUOSi*/
1675 case 15: /*REMSi*/
1676 {
1677 int label1 = gen_new_label();
1678 int label2 = gen_new_label();
1679
1680 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1681 label1);
1682 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1683 label1);
1684 tcg_gen_movi_i32(cpu_R[RRR_R],
1685 OP2 == 13 ? 0x80000000 : 0);
1686 tcg_gen_br(label2);
1687 gen_set_label(label1);
1688 if (OP2 == 13) {
1689 tcg_gen_div_i32(cpu_R[RRR_R],
1690 cpu_R[RRR_S], cpu_R[RRR_T]);
1691 } else {
1692 tcg_gen_rem_i32(cpu_R[RRR_R],
1693 cpu_R[RRR_S], cpu_R[RRR_T]);
1694 }
1695 gen_set_label(label2);
1696 }
1697 break;
1698
1699 case 14: /*REMUi*/
1700 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1701 break;
1702
1703 default: /*reserved*/
1704 RESERVED();
1705 break;
1706 }
dedc5eae
MF		 1707 break;
1708
1709 case 3: /*RST3*/
b8132eff
MF		 1710 switch (OP2) {
1711 case 0: /*RSR*/
53593e90 1712 gen_check_sr(dc, RSR_SR, SR_R);
40643d7c
MF		 1713 if (RSR_SR >= 64) {
1714 gen_check_privilege(dc);
1715 }
772177c1 1716 gen_window_check1(dc, RRR_T);
b8132eff
MF		 1717 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1718 break;
1719
1720 case 1: /*WSR*/
53593e90 1721 gen_check_sr(dc, RSR_SR, SR_W);
40643d7c
MF		 1722 if (RSR_SR >= 64) {
1723 gen_check_privilege(dc);
1724 }
772177c1 1725 gen_window_check1(dc, RRR_T);
b8132eff
MF		 1726 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
1727 break;
1728
1729 case 2: /*SEXTu*/
7f65f4b0 1730 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT);
772177c1 1731 gen_window_check2(dc, RRR_R, RRR_S);
b8132eff
MF		 1732 {
1733 int shift = 24 - RRR_T;
1734
1735 if (shift == 24) {
1736 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1737 } else if (shift == 16) {
1738 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1739 } else {
1740 TCGv_i32 tmp = tcg_temp_new_i32();
1741 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1742 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1743 tcg_temp_free(tmp);
1744 }
1745 }
1746 break;
1747
1748 case 3: /*CLAMPSu*/
7f65f4b0 1749 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS);
772177c1 1750 gen_window_check2(dc, RRR_R, RRR_S);
b8132eff
MF		 1751 {
1752 TCGv_i32 tmp1 = tcg_temp_new_i32();
1753 TCGv_i32 tmp2 = tcg_temp_new_i32();
1754 int label = gen_new_label();
1755
1756 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1757 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1758 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
1759 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1760 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp2, 0, label);
1761
1762 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
1763 tcg_gen_xori_i32(cpu_R[RRR_R], tmp1,
1764 0xffffffff >> (25 - RRR_T));
1765
1766 gen_set_label(label);
1767
1768 tcg_temp_free(tmp1);
1769 tcg_temp_free(tmp2);
1770 }
1771 break;
1772
1773 case 4: /*MINu*/
1774 case 5: /*MAXu*/
1775 case 6: /*MINUu*/
1776 case 7: /*MAXUu*/
7f65f4b0 1777 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX);
772177c1 1778 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
b8132eff
MF		 1779 {
1780 static const TCGCond cond[] = {
1781 TCG_COND_LE,
1782 TCG_COND_GE,
1783 TCG_COND_LEU,
1784 TCG_COND_GEU
1785 };
1786 int label = gen_new_label();
1787
1788 if (RRR_R != RRR_T) {
1789 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1790 tcg_gen_brcond_i32(cond[OP2 - 4],
1791 cpu_R[RRR_S], cpu_R[RRR_T], label);
1792 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1793 } else {
1794 tcg_gen_brcond_i32(cond[OP2 - 4],
1795 cpu_R[RRR_T], cpu_R[RRR_S], label);
1796 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1797 }
1798 gen_set_label(label);
1799 }
1800 break;
1801
1802 case 8: /*MOVEQZ*/
1803 case 9: /*MOVNEZ*/
1804 case 10: /*MOVLTZ*/
1805 case 11: /*MOVGEZ*/
772177c1 1806 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
b8132eff
MF		 1807 {
1808 static const TCGCond cond[] = {
1809 TCG_COND_NE,
1810 TCG_COND_EQ,
1811 TCG_COND_GE,
1812 TCG_COND_LT
1813 };
1814 int label = gen_new_label();
1815 tcg_gen_brcondi_i32(cond[OP2 - 8], cpu_R[RRR_T], 0, label);
1816 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1817 gen_set_label(label);
1818 }
1819 break;
1820
1821 case 12: /*MOVFp*/
b8132eff
MF		 1822 case 13: /*MOVTp*/
1823 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 1824 gen_window_check2(dc, RRR_R, RRR_S);
1825 {
1826 int label = gen_new_label();
1827 TCGv_i32 tmp = tcg_temp_new_i32();
1828
1829 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
1830 tcg_gen_brcondi_i32(
1831 OP2 & 1 ? TCG_COND_EQ : TCG_COND_NE,
1832 tmp, 0, label);
1833 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1834 gen_set_label(label);
1835 tcg_temp_free(tmp);
1836 }
b8132eff
MF		 1837 break;
1838
1839 case 14: /*RUR*/
772177c1 1840 gen_window_check1(dc, RRR_R);
b8132eff
MF		 1841 {
1842 int st = (RRR_S << 4) + RRR_T;
fe0bd475 1843 if (uregnames[st].name) {
b8132eff
MF		 1844 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1845 } else {
1846 qemu_log("RUR %d not implemented, ", st);
91a5bb76 1847 TBD();
b8132eff
MF		 1848 }
1849 }
1850 break;
1851
1852 case 15: /*WUR*/
772177c1 1853 gen_window_check1(dc, RRR_T);
fe0bd475 1854 if (uregnames[RSR_SR].name) {
dd519cbe
MF		 1855 gen_wur(RSR_SR, cpu_R[RRR_T]);
1856 } else {
1857 qemu_log("WUR %d not implemented, ", RSR_SR);
1858 TBD();
b8132eff
MF		 1859 }
1860 break;
1861
1862 }
dedc5eae
MF		 1863 break;
1864
1865 case 4: /*EXTUI*/
1866 case 5:
772177c1 1867 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad 1868 {
f9cb5045 1869 int shiftimm = RRR_S | ((OP1 & 1) << 4);
3580ecad
MF		 1870 int maskimm = (1 << (OP2 + 1)) - 1;
1871
1872 TCGv_i32 tmp = tcg_temp_new_i32();
f783cb22
AJ		 1873 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1874 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
3580ecad
MF		 1875 tcg_temp_free(tmp);
1876 }
dedc5eae
MF		 1877 break;
1878
1879 case 6: /*CUST0*/
91a5bb76 1880 RESERVED();
dedc5eae
MF		 1881 break;
1882
1883 case 7: /*CUST1*/
91a5bb76 1884 RESERVED();
dedc5eae
MF		 1885 break;
1886
1887 case 8: /*LSCXp*/
9ed7ae12
MF		 1888 switch (OP2) {
1889 case 0: /*LSXf*/
1890 case 1: /*LSXUf*/
1891 case 4: /*SSXf*/
1892 case 5: /*SSXUf*/
1893 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1894 gen_window_check2(dc, RRR_S, RRR_T);
ef04a846 1895 gen_check_cpenable(dc, 0);
9ed7ae12
MF		 1896 {
1897 TCGv_i32 addr = tcg_temp_new_i32();
1898 tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]);
1899 gen_load_store_alignment(dc, 2, addr, false);
1900 if (OP2 & 0x4) {
1901 tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring);
1902 } else {
1903 tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring);
1904 }
1905 if (OP2 & 0x1) {
1906 tcg_gen_mov_i32(cpu_R[RRR_S], addr);
1907 }
1908 tcg_temp_free(addr);
1909 }
1910 break;
1911
1912 default: /*reserved*/
1913 RESERVED();
1914 break;
1915 }
dedc5eae
MF		 1916 break;
1917
1918 case 9: /*LSC4*/
772177c1 1919 gen_window_check2(dc, RRR_S, RRR_T);
553e44f9
MF		 1920 switch (OP2) {
1921 case 0: /*L32E*/
1922 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1923 gen_check_privilege(dc);
1924 {
1925 TCGv_i32 addr = tcg_temp_new_i32();
1926 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1927 (0xffffffc0 | (RRR_R << 2)));
1928 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1929 tcg_temp_free(addr);
1930 }
1931 break;
1932
1933 case 4: /*S32E*/
1934 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1935 gen_check_privilege(dc);
1936 {
1937 TCGv_i32 addr = tcg_temp_new_i32();
1938 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1939 (0xffffffc0 | (RRR_R << 2)));
1940 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1941 tcg_temp_free(addr);
1942 }
1943 break;
1944
1945 default:
1946 RESERVED();
1947 break;
1948 }
dedc5eae
MF		 1949 break;
1950
1951 case 10: /*FP0*/
1952 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
0b6df838
MF		 1953 switch (OP2) {
1954 case 0: /*ADD.Sf*/
ef04a846 1955 gen_check_cpenable(dc, 0);
0b6df838
MF		 1956 gen_helper_add_s(cpu_FR[RRR_R], cpu_env,
1957 cpu_FR[RRR_S], cpu_FR[RRR_T]);
1958 break;
1959
1960 case 1: /*SUB.Sf*/
ef04a846 1961 gen_check_cpenable(dc, 0);
0b6df838
MF		 1962 gen_helper_sub_s(cpu_FR[RRR_R], cpu_env,
1963 cpu_FR[RRR_S], cpu_FR[RRR_T]);
1964 break;
1965
1966 case 2: /*MUL.Sf*/
ef04a846 1967 gen_check_cpenable(dc, 0);
0b6df838
MF		 1968 gen_helper_mul_s(cpu_FR[RRR_R], cpu_env,
1969 cpu_FR[RRR_S], cpu_FR[RRR_T]);
1970 break;
1971
1972 case 4: /*MADD.Sf*/
ef04a846 1973 gen_check_cpenable(dc, 0);
0b6df838
MF		 1974 gen_helper_madd_s(cpu_FR[RRR_R], cpu_env,
1975 cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]);
1976 break;
1977
1978 case 5: /*MSUB.Sf*/
ef04a846 1979 gen_check_cpenable(dc, 0);
0b6df838
MF		 1980 gen_helper_msub_s(cpu_FR[RRR_R], cpu_env,
1981 cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]);
1982 break;
1983
b7ee8c6a
MF		 1984 case 8: /*ROUND.Sf*/
1985 case 9: /*TRUNC.Sf*/
1986 case 10: /*FLOOR.Sf*/
1987 case 11: /*CEIL.Sf*/
1988 case 14: /*UTRUNC.Sf*/
1989 gen_window_check1(dc, RRR_R);
ef04a846 1990 gen_check_cpenable(dc, 0);
b7ee8c6a
MF		 1991 {
1992 static const unsigned rounding_mode_const[] = {
1993 float_round_nearest_even,
1994 float_round_to_zero,
1995 float_round_down,
1996 float_round_up,
1997 [6] = float_round_to_zero,
1998 };
1999 TCGv_i32 rounding_mode = tcg_const_i32(
2000 rounding_mode_const[OP2 & 7]);
2001 TCGv_i32 scale = tcg_const_i32(RRR_T);
2002
2003 if (OP2 == 14) {
2004 gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S],
2005 rounding_mode, scale);
2006 } else {
2007 gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S],
2008 rounding_mode, scale);
2009 }
2010
2011 tcg_temp_free(rounding_mode);
2012 tcg_temp_free(scale);
2013 }
2014 break;
2015
2016 case 12: /*FLOAT.Sf*/
2017 case 13: /*UFLOAT.Sf*/
2018 gen_window_check1(dc, RRR_S);
ef04a846 2019 gen_check_cpenable(dc, 0);
b7ee8c6a
MF		 2020 {
2021 TCGv_i32 scale = tcg_const_i32(-RRR_T);
2022
2023 if (OP2 == 13) {
2024 gen_helper_uitof(cpu_FR[RRR_R], cpu_env,
2025 cpu_R[RRR_S], scale);
2026 } else {
2027 gen_helper_itof(cpu_FR[RRR_R], cpu_env,
2028 cpu_R[RRR_S], scale);
2029 }
2030 tcg_temp_free(scale);
2031 }
2032 break;
2033
0b6df838
MF		 2034 case 15: /*FP1OP*/
2035 switch (RRR_T) {
2036 case 0: /*MOV.Sf*/
ef04a846 2037 gen_check_cpenable(dc, 0);
0b6df838
MF		 2038 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2039 break;
2040
2041 case 1: /*ABS.Sf*/
ef04a846 2042 gen_check_cpenable(dc, 0);
0b6df838
MF		 2043 gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2044 break;
2045
2046 case 4: /*RFRf*/
2047 gen_window_check1(dc, RRR_R);
ef04a846 2048 gen_check_cpenable(dc, 0);
0b6df838
MF		 2049 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]);
2050 break;
2051
2052 case 5: /*WFRf*/
2053 gen_window_check1(dc, RRR_S);
ef04a846 2054 gen_check_cpenable(dc, 0);
0b6df838
MF		 2055 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]);
2056 break;
2057
2058 case 6: /*NEG.Sf*/
ef04a846 2059 gen_check_cpenable(dc, 0);
0b6df838
MF		 2060 gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2061 break;
2062
2063 default: /*reserved*/
2064 RESERVED();
2065 break;
2066 }
2067 break;
2068
2069 default: /*reserved*/
2070 RESERVED();
2071 break;
2072 }
dedc5eae
MF		 2073 break;
2074
2075 case 11: /*FP1*/
2076 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
4e273869
MF		 2077
2078#define gen_compare(rel, br, a, b) \
2079 do { \
2080 TCGv_i32 bit = tcg_const_i32(1 << br); \
2081 \
ef04a846 2082 gen_check_cpenable(dc, 0); \
4e273869
MF		 2083 gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
2084 tcg_temp_free(bit); \
2085 } while (0)
2086
2087 switch (OP2) {
2088 case 1: /*UN.Sf*/
2089 gen_compare(un_s, RRR_R, RRR_S, RRR_T);
2090 break;
2091
2092 case 2: /*OEQ.Sf*/
2093 gen_compare(oeq_s, RRR_R, RRR_S, RRR_T);
2094 break;
2095
2096 case 3: /*UEQ.Sf*/
2097 gen_compare(ueq_s, RRR_R, RRR_S, RRR_T);
2098 break;
2099
2100 case 4: /*OLT.Sf*/
2101 gen_compare(olt_s, RRR_R, RRR_S, RRR_T);
2102 break;
2103
2104 case 5: /*ULT.Sf*/
2105 gen_compare(ult_s, RRR_R, RRR_S, RRR_T);
2106 break;
2107
2108 case 6: /*OLE.Sf*/
2109 gen_compare(ole_s, RRR_R, RRR_S, RRR_T);
2110 break;
2111
2112 case 7: /*ULE.Sf*/
2113 gen_compare(ule_s, RRR_R, RRR_S, RRR_T);
2114 break;
2115
2116#undef gen_compare
2117
2118 case 8: /*MOVEQZ.Sf*/
2119 case 9: /*MOVNEZ.Sf*/
2120 case 10: /*MOVLTZ.Sf*/
2121 case 11: /*MOVGEZ.Sf*/
2122 gen_window_check1(dc, RRR_T);
ef04a846 2123 gen_check_cpenable(dc, 0);
4e273869
MF		 2124 {
2125 static const TCGCond cond[] = {
2126 TCG_COND_NE,
2127 TCG_COND_EQ,
2128 TCG_COND_GE,
2129 TCG_COND_LT
2130 };
2131 int label = gen_new_label();
2132 tcg_gen_brcondi_i32(cond[OP2 - 8], cpu_R[RRR_T], 0, label);
2133 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2134 gen_set_label(label);
2135 }
2136 break;
2137
2138 case 12: /*MOVF.Sf*/
2139 case 13: /*MOVT.Sf*/
2140 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
ef04a846 2141 gen_check_cpenable(dc, 0);
4e273869
MF		 2142 {
2143 int label = gen_new_label();
2144 TCGv_i32 tmp = tcg_temp_new_i32();
2145
2146 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
2147 tcg_gen_brcondi_i32(
2148 OP2 & 1 ? TCG_COND_EQ : TCG_COND_NE,
2149 tmp, 0, label);
2150 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2151 gen_set_label(label);
2152 tcg_temp_free(tmp);
2153 }
2154 break;
2155
2156 default: /*reserved*/
2157 RESERVED();
2158 break;
2159 }
dedc5eae
MF		 2160 break;
2161
2162 default: /*reserved*/
91a5bb76 2163 RESERVED();
dedc5eae
MF		 2164 break;
2165 }
2166 break;
2167
2168 case 1: /*L32R*/
772177c1 2169 gen_window_check1(dc, RRR_T);
dedc5eae
MF		 2170 {
2171 TCGv_i32 tmp = tcg_const_i32(
6ad6dbf7
MF		 2172 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
2173 0 : ((dc->pc + 3) & ~3)) +
2174 (0xfffc0000 | (RI16_IMM16 << 2)));
dedc5eae 2175
6ad6dbf7
MF		 2176 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
2177 tcg_gen_add_i32(tmp, tmp, dc->litbase);
2178 }
f0a548b9 2179 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
dedc5eae
MF		 2180 tcg_temp_free(tmp);
2181 }
2182 break;
2183
2184 case 2: /*LSAI*/
809377aa
MF		 2185#define gen_load_store(type, shift) do { \
2186 TCGv_i32 addr = tcg_temp_new_i32(); \
772177c1 2187 gen_window_check2(dc, RRI8_S, RRI8_T); \
809377aa 2188 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
5b4e481b
MF		 2189 if (shift) { \
2190 gen_load_store_alignment(dc, shift, addr, false); \
2191 } \
f0a548b9 2192 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
809377aa
MF		 2193 tcg_temp_free(addr); \
2194 } while (0)
2195
2196 switch (RRI8_R) {
2197 case 0: /*L8UI*/
2198 gen_load_store(ld8u, 0);
2199 break;
2200
2201 case 1: /*L16UI*/
2202 gen_load_store(ld16u, 1);
2203 break;
2204
2205 case 2: /*L32I*/
2206 gen_load_store(ld32u, 2);
2207 break;
2208
2209 case 4: /*S8I*/
2210 gen_load_store(st8, 0);
2211 break;
2212
2213 case 5: /*S16I*/
2214 gen_load_store(st16, 1);
2215 break;
2216
2217 case 6: /*S32I*/
2218 gen_load_store(st32, 2);
2219 break;
2220
2221 case 7: /*CACHEc*/
8ffc2d0d
MF		 2222 if (RRI8_T < 8) {
2223 HAS_OPTION(XTENSA_OPTION_DCACHE);
2224 }
2225
2226 switch (RRI8_T) {
2227 case 0: /*DPFRc*/
2228 break;
2229
2230 case 1: /*DPFWc*/
2231 break;
2232
2233 case 2: /*DPFROc*/
2234 break;
2235
2236 case 3: /*DPFWOc*/
2237 break;
2238
2239 case 4: /*DHWBc*/
2240 break;
2241
2242 case 5: /*DHWBIc*/
2243 break;
2244
2245 case 6: /*DHIc*/
2246 break;
2247
2248 case 7: /*DIIc*/
2249 break;
2250
2251 case 8: /*DCEc*/
2252 switch (OP1) {
2253 case 0: /*DPFLl*/
2254 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2255 break;
2256
2257 case 2: /*DHUl*/
2258 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2259 break;
2260
2261 case 3: /*DIUl*/
2262 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2263 break;
2264
2265 case 4: /*DIWBc*/
2266 HAS_OPTION(XTENSA_OPTION_DCACHE);
2267 break;
2268
2269 case 5: /*DIWBIc*/
2270 HAS_OPTION(XTENSA_OPTION_DCACHE);
2271 break;
2272
2273 default: /*reserved*/
2274 RESERVED();
2275 break;
2276
2277 }
2278 break;
2279
2280 case 12: /*IPFc*/
2281 HAS_OPTION(XTENSA_OPTION_ICACHE);
2282 break;
2283
2284 case 13: /*ICEc*/
2285 switch (OP1) {
2286 case 0: /*IPFLl*/
2287 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2288 break;
2289
2290 case 2: /*IHUl*/
2291 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2292 break;
2293
2294 case 3: /*IIUl*/
2295 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2296 break;
2297
2298 default: /*reserved*/
2299 RESERVED();
2300 break;
2301 }
2302 break;
2303
2304 case 14: /*IHIc*/
2305 HAS_OPTION(XTENSA_OPTION_ICACHE);
2306 break;
2307
2308 case 15: /*IIIc*/
2309 HAS_OPTION(XTENSA_OPTION_ICACHE);
2310 break;
2311
2312 default: /*reserved*/
2313 RESERVED();
2314 break;
2315 }
809377aa
MF		 2316 break;
2317
2318 case 9: /*L16SI*/
2319 gen_load_store(ld16s, 1);
2320 break;
5b4e481b 2321#undef gen_load_store
809377aa
MF		 2322
2323 case 10: /*MOVI*/
772177c1 2324 gen_window_check1(dc, RRI8_T);
809377aa
MF		 2325 tcg_gen_movi_i32(cpu_R[RRI8_T],
2326 RRI8_IMM8 | (RRI8_S << 8) |
2327 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
2328 break;
2329
5b4e481b
MF		 2330#define gen_load_store_no_hw_align(type) do { \
2331 TCGv_i32 addr = tcg_temp_local_new_i32(); \
772177c1 2332 gen_window_check2(dc, RRI8_S, RRI8_T); \
5b4e481b
MF		 2333 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2334 gen_load_store_alignment(dc, 2, addr, true); \
2335 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2336 tcg_temp_free(addr); \
2337 } while (0)
2338
809377aa
MF		 2339 case 11: /*L32AIy*/
2340 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 2341 gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
809377aa
MF		 2342 break;
2343
2344 case 12: /*ADDI*/
772177c1 2345 gen_window_check2(dc, RRI8_S, RRI8_T);
809377aa
MF		 2346 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
2347 break;
2348
2349 case 13: /*ADDMI*/
772177c1 2350 gen_window_check2(dc, RRI8_S, RRI8_T);
809377aa
MF		 2351 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE << 8);
2352 break;
2353
2354 case 14: /*S32C1Iy*/
7f65f4b0 2355 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
772177c1 2356 gen_window_check2(dc, RRI8_S, RRI8_T);
809377aa
MF		 2357 {
2358 int label = gen_new_label();
2359 TCGv_i32 tmp = tcg_temp_local_new_i32();
2360 TCGv_i32 addr = tcg_temp_local_new_i32();
fcc803d1 2361 TCGv_i32 tpc;
809377aa
MF		 2362
2363 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
2364 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
5b4e481b 2365 gen_load_store_alignment(dc, 2, addr, true);
fcc803d1
MF		 2366
2367 gen_advance_ccount(dc);
2368 tpc = tcg_const_i32(dc->pc);
2369 gen_helper_check_atomctl(cpu_env, tpc, addr);
f0a548b9 2370 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
809377aa
MF		 2371 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
2372 cpu_SR[SCOMPARE1], label);
2373
f0a548b9 2374 tcg_gen_qemu_st32(tmp, addr, dc->cring);
809377aa
MF		 2375
2376 gen_set_label(label);
fcc803d1 2377 tcg_temp_free(tpc);
809377aa
MF		 2378 tcg_temp_free(addr);
2379 tcg_temp_free(tmp);
2380 }
2381 break;
2382
2383 case 15: /*S32RIy*/
2384 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 2385 gen_load_store_no_hw_align(st32); /*TODO release?*/
809377aa 2386 break;
5b4e481b 2387#undef gen_load_store_no_hw_align
809377aa
MF		 2388
2389 default: /*reserved*/
91a5bb76 2390 RESERVED();
809377aa
MF		 2391 break;
2392 }
dedc5eae
MF		 2393 break;
2394
2395 case 3: /*LSCIp*/
9ed7ae12
MF		 2396 switch (RRI8_R) {
2397 case 0: /*LSIf*/
2398 case 4: /*SSIf*/
2399 case 8: /*LSIUf*/
2400 case 12: /*SSIUf*/
2401 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2402 gen_window_check1(dc, RRI8_S);
ef04a846 2403 gen_check_cpenable(dc, 0);
9ed7ae12
MF		 2404 {
2405 TCGv_i32 addr = tcg_temp_new_i32();
2406 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2407 gen_load_store_alignment(dc, 2, addr, false);
2408 if (RRI8_R & 0x4) {
2409 tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring);
2410 } else {
2411 tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring);
2412 }
2413 if (RRI8_R & 0x8) {
2414 tcg_gen_mov_i32(cpu_R[RRI8_S], addr);
2415 }
2416 tcg_temp_free(addr);
2417 }
2418 break;
2419
2420 default: /*reserved*/
2421 RESERVED();
2422 break;
2423 }
dedc5eae
MF		 2424 break;
2425
2426 case 4: /*MAC16d*/
2427 HAS_OPTION(XTENSA_OPTION_MAC16);
6825b6c3
MF		 2428 {
2429 enum {
2430 MAC16_UMUL = 0x0,
2431 MAC16_MUL = 0x4,
2432 MAC16_MULA = 0x8,
2433 MAC16_MULS = 0xc,
2434 MAC16_NONE = 0xf,
2435 } op = OP1 & 0xc;
2436 bool is_m1_sr = (OP2 & 0x3) == 2;
2437 bool is_m2_sr = (OP2 & 0xc) == 0;
2438 uint32_t ld_offset = 0;
2439
2440 if (OP2 > 9) {
2441 RESERVED();
2442 }
2443
2444 switch (OP2 & 2) {
2445 case 0: /*MACI?/MACC?*/
2446 is_m1_sr = true;
2447 ld_offset = (OP2 & 1) ? -4 : 4;
2448
2449 if (OP2 >= 8) { /*MACI/MACC*/
2450 if (OP1 == 0) { /*LDINC/LDDEC*/
2451 op = MAC16_NONE;
2452 } else {
2453 RESERVED();
2454 }
2455 } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/
2456 RESERVED();
2457 }
2458 break;
2459
2460 case 2: /*MACD?/MACA?*/
2461 if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/
2462 RESERVED();
2463 }
2464 break;
2465 }
2466
2467 if (op != MAC16_NONE) {
2468 if (!is_m1_sr) {
2469 gen_window_check1(dc, RRR_S);
2470 }
2471 if (!is_m2_sr) {
2472 gen_window_check1(dc, RRR_T);
2473 }
2474 }
2475
2476 {
2477 TCGv_i32 vaddr = tcg_temp_new_i32();
2478 TCGv_i32 mem32 = tcg_temp_new_i32();
2479
2480 if (ld_offset) {
2481 gen_window_check1(dc, RRR_S);
2482 tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset);
2483 gen_load_store_alignment(dc, 2, vaddr, false);
2484 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
2485 }
2486 if (op != MAC16_NONE) {
2487 TCGv_i32 m1 = gen_mac16_m(
2488 is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S],
2489 OP1 & 1, op == MAC16_UMUL);
2490 TCGv_i32 m2 = gen_mac16_m(
2491 is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T],
2492 OP1 & 2, op == MAC16_UMUL);
2493
2494 if (op == MAC16_MUL || op == MAC16_UMUL) {
2495 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
2496 if (op == MAC16_UMUL) {
2497 tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
2498 } else {
2499 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
2500 }
2501 } else {
2502 TCGv_i32 res = tcg_temp_new_i32();
2503 TCGv_i64 res64 = tcg_temp_new_i64();
2504 TCGv_i64 tmp = tcg_temp_new_i64();
2505
2506 tcg_gen_mul_i32(res, m1, m2);
2507 tcg_gen_ext_i32_i64(res64, res);
2508 tcg_gen_concat_i32_i64(tmp,
2509 cpu_SR[ACCLO], cpu_SR[ACCHI]);
2510 if (op == MAC16_MULA) {
2511 tcg_gen_add_i64(tmp, tmp, res64);
2512 } else {
2513 tcg_gen_sub_i64(tmp, tmp, res64);
2514 }
2515 tcg_gen_trunc_i64_i32(cpu_SR[ACCLO], tmp);
2516 tcg_gen_shri_i64(tmp, tmp, 32);
2517 tcg_gen_trunc_i64_i32(cpu_SR[ACCHI], tmp);
2518 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
2519
2520 tcg_temp_free(res);
2521 tcg_temp_free_i64(res64);
2522 tcg_temp_free_i64(tmp);
2523 }
2524 tcg_temp_free(m1);
2525 tcg_temp_free(m2);
2526 }
2527 if (ld_offset) {
2528 tcg_gen_mov_i32(cpu_R[RRR_S], vaddr);
2529 tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32);
2530 }
2531 tcg_temp_free(vaddr);
2532 tcg_temp_free(mem32);
2533 }
2534 }
dedc5eae
MF		 2535 break;
2536
2537 case 5: /*CALLN*/
2538 switch (CALL_N) {
2539 case 0: /*CALL0*/
2540 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
2541 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2542 break;
2543
2544 case 1: /*CALL4w*/
2545 case 2: /*CALL8w*/
2546 case 3: /*CALL12w*/
2547 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
772177c1 2548 gen_window_check1(dc, CALL_N << 2);
553e44f9
MF		 2549 gen_callwi(dc, CALL_N,
2550 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
dedc5eae
MF		 2551 break;
2552 }
2553 break;
2554
2555 case 6: /*SI*/
2556 switch (CALL_N) {
2557 case 0: /*J*/
2558 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
2559 break;
2560
bd57fb91 2561 case 1: /*BZ*/
772177c1 2562 gen_window_check1(dc, BRI12_S);
bd57fb91
MF		 2563 {
2564 static const TCGCond cond[] = {
2565 TCG_COND_EQ, /*BEQZ*/
2566 TCG_COND_NE, /*BNEZ*/
2567 TCG_COND_LT, /*BLTZ*/
2568 TCG_COND_GE, /*BGEZ*/
2569 };
2570
2571 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
2572 4 + BRI12_IMM12_SE);
2573 }
2574 break;
2575
2576 case 2: /*BI0*/
772177c1 2577 gen_window_check1(dc, BRI8_S);
bd57fb91
MF		 2578 {
2579 static const TCGCond cond[] = {
2580 TCG_COND_EQ, /*BEQI*/
2581 TCG_COND_NE, /*BNEI*/
2582 TCG_COND_LT, /*BLTI*/
2583 TCG_COND_GE, /*BGEI*/
2584 };
2585
2586 gen_brcondi(dc, cond[BRI8_M & 3],
2587 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
2588 }
2589 break;
2590
2591 case 3: /*BI1*/
2592 switch (BRI8_M) {
2593 case 0: /*ENTRYw*/
2594 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 2595 {
2596 TCGv_i32 pc = tcg_const_i32(dc->pc);
2597 TCGv_i32 s = tcg_const_i32(BRI12_S);
2598 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
b994e91b 2599 gen_advance_ccount(dc);
f492b82d 2600 gen_helper_entry(cpu_env, pc, s, imm);
553e44f9
MF		 2601 tcg_temp_free(imm);
2602 tcg_temp_free(s);
2603 tcg_temp_free(pc);
772177c1 2604 reset_used_window(dc);
553e44f9 2605 }
bd57fb91
MF		 2606 break;
2607
2608 case 1: /*B1*/
2609 switch (BRI8_R) {
2610 case 0: /*BFp*/
bd57fb91
MF		 2611 case 1: /*BTp*/
2612 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 2613 {
2614 TCGv_i32 tmp = tcg_temp_new_i32();
2615 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
2616 gen_brcondi(dc,
2617 BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
2618 tmp, 0, 4 + RRI8_IMM8_SE);
2619 tcg_temp_free(tmp);
2620 }
bd57fb91
MF		 2621 break;
2622
2623 case 8: /*LOOP*/
bd57fb91 2624 case 9: /*LOOPNEZ*/
bd57fb91 2625 case 10: /*LOOPGTZ*/
797d780b 2626 HAS_OPTION(XTENSA_OPTION_LOOP);
772177c1 2627 gen_window_check1(dc, RRI8_S);
797d780b
MF		 2628 {
2629 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
2630 TCGv_i32 tmp = tcg_const_i32(lend);
2631
2632 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
2633 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
f492b82d 2634 gen_helper_wsr_lend(cpu_env, tmp);
797d780b
MF		 2635 tcg_temp_free(tmp);
2636
2637 if (BRI8_R > 8) {
2638 int label = gen_new_label();
2639 tcg_gen_brcondi_i32(
2640 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
2641 cpu_R[RRI8_S], 0, label);
2642 gen_jumpi(dc, lend, 1);
2643 gen_set_label(label);
2644 }
2645
2646 gen_jumpi(dc, dc->next_pc, 0);
2647 }
bd57fb91
MF		 2648 break;
2649
2650 default: /*reserved*/
91a5bb76 2651 RESERVED();
bd57fb91
MF		 2652 break;
2653
2654 }
2655 break;
2656
2657 case 2: /*BLTUI*/
2658 case 3: /*BGEUI*/
772177c1 2659 gen_window_check1(dc, BRI8_S);
bd57fb91
MF		 2660 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
2661 cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
2662 break;
2663 }
2664 break;
2665
dedc5eae
MF		 2666 }
2667 break;
2668
2669 case 7: /*B*/
bd57fb91
MF		 2670 {
2671 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
2672
2673 switch (RRI8_R & 7) {
2674 case 0: /*BNONE*/ /*BANY*/
772177c1 2675 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2676 {
2677 TCGv_i32 tmp = tcg_temp_new_i32();
2678 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2679 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2680 tcg_temp_free(tmp);
2681 }
2682 break;
2683
2684 case 1: /*BEQ*/ /*BNE*/
2685 case 2: /*BLT*/ /*BGE*/
2686 case 3: /*BLTU*/ /*BGEU*/
772177c1 2687 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2688 {
2689 static const TCGCond cond[] = {
2690 [1] = TCG_COND_EQ,
2691 [2] = TCG_COND_LT,
2692 [3] = TCG_COND_LTU,
2693 [9] = TCG_COND_NE,
2694 [10] = TCG_COND_GE,
2695 [11] = TCG_COND_GEU,
2696 };
2697 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
2698 4 + RRI8_IMM8_SE);
2699 }
2700 break;
2701
2702 case 4: /*BALL*/ /*BNALL*/
772177c1 2703 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2704 {
2705 TCGv_i32 tmp = tcg_temp_new_i32();
2706 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2707 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
2708 4 + RRI8_IMM8_SE);
2709 tcg_temp_free(tmp);
2710 }
2711 break;
2712
2713 case 5: /*BBC*/ /*BBS*/
772177c1 2714 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91 2715 {
7ff7563f
MF		 2716#ifdef TARGET_WORDS_BIGENDIAN
2717 TCGv_i32 bit = tcg_const_i32(0x80000000);
2718#else
2719 TCGv_i32 bit = tcg_const_i32(0x00000001);
2720#endif
bd57fb91
MF		 2721 TCGv_i32 tmp = tcg_temp_new_i32();
2722 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
7ff7563f
MF		 2723#ifdef TARGET_WORDS_BIGENDIAN
2724 tcg_gen_shr_i32(bit, bit, tmp);
2725#else
bd57fb91 2726 tcg_gen_shl_i32(bit, bit, tmp);
7ff7563f 2727#endif
bd57fb91
MF		 2728 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
2729 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2730 tcg_temp_free(tmp);
2731 tcg_temp_free(bit);
2732 }
2733 break;
2734
2735 case 6: /*BBCI*/ /*BBSI*/
2736 case 7:
772177c1 2737 gen_window_check1(dc, RRI8_S);
bd57fb91
MF		 2738 {
2739 TCGv_i32 tmp = tcg_temp_new_i32();
2740 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
7ff7563f
MF		 2741#ifdef TARGET_WORDS_BIGENDIAN
2742 0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T));
2743#else
2744 0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T));
2745#endif
bd57fb91
MF		 2746 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2747 tcg_temp_free(tmp);
2748 }
2749 break;
2750
2751 }
2752 }
dedc5eae
MF		 2753 break;
2754
67882fd1
MF		 2755#define gen_narrow_load_store(type) do { \
2756 TCGv_i32 addr = tcg_temp_new_i32(); \
772177c1 2757 gen_window_check2(dc, RRRN_S, RRRN_T); \
67882fd1 2758 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
5b4e481b 2759 gen_load_store_alignment(dc, 2, addr, false); \
f0a548b9 2760 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
67882fd1
MF		 2761 tcg_temp_free(addr); \
2762 } while (0)
2763
dedc5eae 2764 case 8: /*L32I.Nn*/
67882fd1 2765 gen_narrow_load_store(ld32u);
dedc5eae
MF		 2766 break;
2767
2768 case 9: /*S32I.Nn*/
67882fd1 2769 gen_narrow_load_store(st32);
dedc5eae 2770 break;
67882fd1 2771#undef gen_narrow_load_store
dedc5eae
MF		 2772
2773 case 10: /*ADD.Nn*/
772177c1 2774 gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T);
67882fd1 2775 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
dedc5eae
MF		 2776 break;
2777
2778 case 11: /*ADDI.Nn*/
772177c1 2779 gen_window_check2(dc, RRRN_R, RRRN_S);
67882fd1 2780 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
dedc5eae
MF		 2781 break;
2782
2783 case 12: /*ST2n*/
772177c1 2784 gen_window_check1(dc, RRRN_S);
67882fd1
MF		 2785 if (RRRN_T < 8) { /*MOVI.Nn*/
2786 tcg_gen_movi_i32(cpu_R[RRRN_S],
2787 RRRN_R | (RRRN_T << 4) |
2788 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
2789 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
bd57fb91
MF		 2790 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
2791
2792 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
2793 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
67882fd1 2794 }
dedc5eae
MF		 2795 break;
2796
2797 case 13: /*ST3n*/
67882fd1
MF		 2798 switch (RRRN_R) {
2799 case 0: /*MOV.Nn*/
772177c1 2800 gen_window_check2(dc, RRRN_S, RRRN_T);
67882fd1
MF		 2801 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
2802 break;
2803
2804 case 15: /*S3*/
2805 switch (RRRN_T) {
2806 case 0: /*RET.Nn*/
2807 gen_jump(dc, cpu_R[0]);
2808 break;
2809
2810 case 1: /*RETW.Nn*/
91a5bb76 2811 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 2812 {
2813 TCGv_i32 tmp = tcg_const_i32(dc->pc);
b994e91b 2814 gen_advance_ccount(dc);
f492b82d 2815 gen_helper_retw(tmp, cpu_env, tmp);
553e44f9
MF		 2816 gen_jump(dc, tmp);
2817 tcg_temp_free(tmp);
2818 }
67882fd1
MF		 2819 break;
2820
2821 case 2: /*BREAK.Nn*/
e61dc8f7
MF		 2822 HAS_OPTION(XTENSA_OPTION_DEBUG);
2823 if (dc->debug) {
2824 gen_debug_exception(dc, DEBUGCAUSE_BN);
2825 }
67882fd1
MF		 2826 break;
2827
2828 case 3: /*NOP.Nn*/
2829 break;
2830
2831 case 6: /*ILL.Nn*/
40643d7c 2832 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
67882fd1
MF		 2833 break;
2834
2835 default: /*reserved*/
91a5bb76 2836 RESERVED();
67882fd1
MF		 2837 break;
2838 }
2839 break;
2840
2841 default: /*reserved*/
91a5bb76 2842 RESERVED();
67882fd1
MF		 2843 break;
2844 }
dedc5eae
MF		 2845 break;
2846
2847 default: /*reserved*/
91a5bb76 2848 RESERVED();
dedc5eae
MF		 2849 break;
2850 }
2851
c26032b2
MF		 2852 if (dc->is_jmp == DISAS_NEXT) {
2853 gen_check_loop_end(dc, 0);
2854 }
dedc5eae 2855 dc->pc = dc->next_pc;
797d780b 2856
dedc5eae
MF		 2857 return;
2858
2859invalid_opcode:
2860 qemu_log("INVALID(pc = %08x)\n", dc->pc);
6b814719 2861 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
dedc5eae
MF		 2862#undef HAS_OPTION
2863}
2864
97129ac8 2865static void check_breakpoint(CPUXtensaState *env, DisasContext *dc)
dedc5eae
MF		 2866{
2867 CPUBreakpoint *bp;
2868
2869 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
2870 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
2871 if (bp->pc == dc->pc) {
2872 tcg_gen_movi_i32(cpu_pc, dc->pc);
b994e91b 2873 gen_exception(dc, EXCP_DEBUG);
dedc5eae
MF		 2874 dc->is_jmp = DISAS_UPDATE;
2875 }
2876 }
2877 }
2878}
2879
97129ac8 2880static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
e61dc8f7
MF		 2881{
2882 unsigned i;
2883
2884 for (i = 0; i < dc->config->nibreak; ++i) {
2885 if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
2886 env->sregs[IBREAKA + i] == dc->pc) {
2887 gen_debug_exception(dc, DEBUGCAUSE_IB);
2888 break;
2889 }
2890 }
2891}
2892
dedc5eae 2893static void gen_intermediate_code_internal(
97129ac8 2894 CPUXtensaState *env, TranslationBlock *tb, int search_pc)
dedc5eae
MF		 2895{
2896 DisasContext dc;
2897 int insn_count = 0;
2898 int j, lj = -1;
92414b31 2899 uint16_t *gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
dedc5eae
MF		 2900 int max_insns = tb->cflags & CF_COUNT_MASK;
2901 uint32_t pc_start = tb->pc;
2902 uint32_t next_page_start =
2903 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2904
2905 if (max_insns == 0) {
2906 max_insns = CF_COUNT_MASK;
2907 }
2908
2909 dc.config = env->config;
2910 dc.singlestep_enabled = env->singlestep_enabled;
2911 dc.tb = tb;
2912 dc.pc = pc_start;
f0a548b9
MF		 2913 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
2914 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
797d780b
MF		 2915 dc.lbeg = env->sregs[LBEG];
2916 dc.lend = env->sregs[LEND];
dedc5eae 2917 dc.is_jmp = DISAS_NEXT;
b994e91b 2918 dc.ccount_delta = 0;
e61dc8f7 2919 dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG;
35b5c044 2920 dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
ef04a846
MF		 2921 dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
2922 XTENSA_TBFLAG_CPENABLE_SHIFT;
dedc5eae 2923
6ad6dbf7 2924 init_litbase(&dc);
3580ecad 2925 init_sar_tracker(&dc);
772177c1 2926 reset_used_window(&dc);
35b5c044
MF		 2927 if (dc.icount) {
2928 dc.next_icount = tcg_temp_local_new_i32();
2929 }
3580ecad 2930
dedc5eae
MF		 2931 gen_icount_start();
2932
40643d7c
MF		 2933 if (env->singlestep_enabled && env->exception_taken) {
2934 env->exception_taken = 0;
2935 tcg_gen_movi_i32(cpu_pc, dc.pc);
b994e91b 2936 gen_exception(&dc, EXCP_DEBUG);
40643d7c
MF		 2937 }
2938
dedc5eae
MF		 2939 do {
2940 check_breakpoint(env, &dc);
2941
2942 if (search_pc) {
92414b31 2943 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
dedc5eae
MF		 2944 if (lj < j) {
2945 lj++;
2946 while (lj < j) {
ab1103de 2947 tcg_ctx.gen_opc_instr_start[lj++] = 0;
dedc5eae
MF		 2948 }
2949 }
25983cad 2950 tcg_ctx.gen_opc_pc[lj] = dc.pc;
ab1103de 2951 tcg_ctx.gen_opc_instr_start[lj] = 1;
c9c99c22 2952 tcg_ctx.gen_opc_icount[lj] = insn_count;
dedc5eae
MF		 2953 }
2954
fdefe51c 2955 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
dedc5eae
MF		 2956 tcg_gen_debug_insn_start(dc.pc);
2957 }
2958
b994e91b
MF		 2959 ++dc.ccount_delta;
2960
2961 if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
2962 gen_io_start();
2963 }
2964
35b5c044
MF		 2965 if (dc.icount) {
2966 int label = gen_new_label();
2967
2968 tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1);
2969 tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label);
2970 tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]);
2971 if (dc.debug) {
2972 gen_debug_exception(&dc, DEBUGCAUSE_IC);
2973 }
2974 gen_set_label(label);
2975 }
2976
e61dc8f7
MF		 2977 if (dc.debug) {
2978 gen_ibreak_check(env, &dc);
2979 }
2980
0c4fabea 2981 disas_xtensa_insn(env, &dc);
dedc5eae 2982 ++insn_count;
35b5c044
MF		 2983 if (dc.icount) {
2984 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
2985 }
dedc5eae
MF		 2986 if (env->singlestep_enabled) {
2987 tcg_gen_movi_i32(cpu_pc, dc.pc);
b994e91b 2988 gen_exception(&dc, EXCP_DEBUG);
dedc5eae
MF		 2989 break;
2990 }
2991 } while (dc.is_jmp == DISAS_NEXT &&
2992 insn_count < max_insns &&
2993 dc.pc < next_page_start &&
efd7f486 2994 tcg_ctx.gen_opc_ptr < gen_opc_end);
dedc5eae 2995
6ad6dbf7 2996 reset_litbase(&dc);
3580ecad 2997 reset_sar_tracker(&dc);
35b5c044
MF		 2998 if (dc.icount) {
2999 tcg_temp_free(dc.next_icount);
3000 }
3580ecad 3001
b994e91b
MF		 3002 if (tb->cflags & CF_LAST_IO) {
3003 gen_io_end();
3004 }
3005
dedc5eae
MF		 3006 if (dc.is_jmp == DISAS_NEXT) {
3007 gen_jumpi(&dc, dc.pc, 0);
3008 }
3009 gen_icount_end(tb, insn_count);
efd7f486 3010 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
dedc5eae
MF		 3011
3012 if (!search_pc) {
3013 tb->size = dc.pc - pc_start;
3014 tb->icount = insn_count;
3015 }
2328826b
MF		 3016}
3017
97129ac8 3018void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
2328826b 3019{
dedc5eae 3020 gen_intermediate_code_internal(env, tb, 0);
2328826b
MF		 3021}
3022
97129ac8 3023void gen_intermediate_code_pc(CPUXtensaState *env, TranslationBlock *tb)
2328826b 3024{
dedc5eae 3025 gen_intermediate_code_internal(env, tb, 1);
2328826b
MF		 3026}
3027
97129ac8 3028void cpu_dump_state(CPUXtensaState *env, FILE *f, fprintf_function cpu_fprintf,
2328826b
MF		 3029 int flags)
3030{
2af3da91
MF		 3031 int i, j;
3032
3033 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
3034
3035 for (i = j = 0; i < 256; ++i) {
fe0bd475
MF		 3036 if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) {
3037 cpu_fprintf(f, "%12s=%08x%c", sregnames[i].name, env->sregs[i],
2af3da91
MF		 3038 (j++ % 4) == 3 ? '\n' : ' ');
3039 }
3040 }
3041
3042 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
3043
3044 for (i = j = 0; i < 256; ++i) {
fe0bd475
MF		 3045 if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)) {
3046 cpu_fprintf(f, "%s=%08x%c", uregnames[i].name, env->uregs[i],
2af3da91
MF		 3047 (j++ % 4) == 3 ? '\n' : ' ');
3048 }
3049 }
2328826b 3050
2af3da91 3051 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2328826b
MF		 3052
3053 for (i = 0; i < 16; ++i) {
fe0bd475 3054 cpu_fprintf(f, " A%02d=%08x%c", i, env->regs[i],
2328826b
MF		 3055 (i % 4) == 3 ? '\n' : ' ');
3056 }
553e44f9
MF		 3057
3058 cpu_fprintf(f, "\n");
3059
3060 for (i = 0; i < env->config->nareg; ++i) {
3061 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
3062 (i % 4) == 3 ? '\n' : ' ');
3063 }
dd519cbe
MF		 3064
3065 if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
3066 cpu_fprintf(f, "\n");
3067
3068 for (i = 0; i < 16; ++i) {
3069 cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
3070 float32_val(env->fregs[i]),
3071 *(float *)&env->fregs[i], (i % 2) == 1 ? '\n' : ' ');
3072 }
3073 }
2328826b
MF		 3074}
3075
97129ac8 3076void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, int pc_pos)
2328826b 3077{
25983cad 3078 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
2328826b 3079}
Qemu copy for testing