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2328826b MF |
1 | /* |
2 | * Xtensa ISA: | |
3 | * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm | |
4 | * | |
5 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
6 | * All rights reserved. | |
7 | * | |
8 | * Redistribution and use in source and binary forms, with or without | |
9 | * modification, are permitted provided that the following conditions are met: | |
10 | * * Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions and the following disclaimer. | |
12 | * * Redistributions in binary form must reproduce the above copyright | |
13 | * notice, this list of conditions and the following disclaimer in the | |
14 | * documentation and/or other materials provided with the distribution. | |
15 | * * Neither the name of the Open Source and Linux Lab nor the | |
16 | * names of its contributors may be used to endorse or promote products | |
17 | * derived from this software without specific prior written permission. | |
18 | * | |
19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
23 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
26 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
29 | */ | |
30 | ||
31 | #include <stdio.h> | |
32 | ||
33 | #include "cpu.h" | |
022c62cb | 34 | #include "exec/exec-all.h" |
76cad711 | 35 | #include "disas/disas.h" |
2328826b | 36 | #include "tcg-op.h" |
1de7afc9 | 37 | #include "qemu/log.h" |
9c17d615 | 38 | #include "sysemu/sysemu.h" |
2328826b | 39 | |
16c1deae | 40 | #include "helper.h" |
dedc5eae | 41 | #define GEN_HELPER 1 |
16c1deae | 42 | #include "helper.h" |
dedc5eae MF |
43 | |
44 | typedef struct DisasContext { | |
45 | const XtensaConfig *config; | |
46 | TranslationBlock *tb; | |
47 | uint32_t pc; | |
48 | uint32_t next_pc; | |
f0a548b9 MF |
49 | int cring; |
50 | int ring; | |
797d780b MF |
51 | uint32_t lbeg; |
52 | uint32_t lend; | |
6ad6dbf7 | 53 | TCGv_i32 litbase; |
dedc5eae MF |
54 | int is_jmp; |
55 | int singlestep_enabled; | |
3580ecad MF |
56 | |
57 | bool sar_5bit; | |
58 | bool sar_m32_5bit; | |
59 | bool sar_m32_allocated; | |
60 | TCGv_i32 sar_m32; | |
b994e91b MF |
61 | |
62 | uint32_t ccount_delta; | |
772177c1 | 63 | unsigned used_window; |
e61dc8f7 MF |
64 | |
65 | bool debug; | |
35b5c044 MF |
66 | bool icount; |
67 | TCGv_i32 next_icount; | |
ef04a846 MF |
68 | |
69 | unsigned cpenable; | |
dedc5eae MF |
70 | } DisasContext; |
71 | ||
72 | static TCGv_ptr cpu_env; | |
73 | static TCGv_i32 cpu_pc; | |
74 | static TCGv_i32 cpu_R[16]; | |
dd519cbe | 75 | static TCGv_i32 cpu_FR[16]; |
2af3da91 MF |
76 | static TCGv_i32 cpu_SR[256]; |
77 | static TCGv_i32 cpu_UR[256]; | |
dedc5eae | 78 | |
022c62cb | 79 | #include "exec/gen-icount.h" |
2328826b | 80 | |
fe0bd475 MF |
81 | typedef struct XtensaReg { |
82 | const char *name; | |
83 | uint64_t opt_bits; | |
53593e90 MF |
84 | enum { |
85 | SR_R = 1, | |
86 | SR_W = 2, | |
87 | SR_X = 4, | |
88 | SR_RW = 3, | |
89 | SR_RWX = 7, | |
90 | } access; | |
fe0bd475 MF |
91 | } XtensaReg; |
92 | ||
53593e90 | 93 | #define XTENSA_REG_ACCESS(regname, opt, acc) { \ |
fe0bd475 MF |
94 | .name = (regname), \ |
95 | .opt_bits = XTENSA_OPTION_BIT(opt), \ | |
53593e90 | 96 | .access = (acc), \ |
fe0bd475 MF |
97 | } |
98 | ||
53593e90 MF |
99 | #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX) |
100 | ||
fe0bd475 MF |
101 | #define XTENSA_REG_BITS(regname, opt) { \ |
102 | .name = (regname), \ | |
103 | .opt_bits = (opt), \ | |
53593e90 | 104 | .access = SR_RWX, \ |
fe0bd475 MF |
105 | } |
106 | ||
107 | static const XtensaReg sregnames[256] = { | |
108 | [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP), | |
109 | [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP), | |
110 | [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP), | |
111 | [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL), | |
112 | [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN), | |
113 | [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R), | |
114 | [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE), | |
115 | [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16), | |
116 | [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16), | |
117 | [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16), | |
118 | [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16), | |
119 | [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16), | |
120 | [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16), | |
121 | [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER), | |
122 | [WINDOW_START] = XTENSA_REG("WINDOW_START", | |
123 | XTENSA_OPTION_WINDOWED_REGISTER), | |
124 | [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU), | |
125 | [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU), | |
126 | [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU), | |
127 | [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU), | |
128 | [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG), | |
129 | [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR), | |
130 | [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL), | |
131 | [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG), | |
132 | [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG), | |
133 | [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG), | |
134 | [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG), | |
135 | [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG), | |
136 | [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG), | |
137 | [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION), | |
138 | [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
139 | [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
140 | [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
141 | [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
142 | [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
143 | [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
144 | [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION), | |
145 | [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
146 | [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
147 | [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
148 | [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
149 | [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
150 | [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
151 | [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION), | |
152 | [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2", | |
153 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
154 | [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3", | |
155 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
156 | [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4", | |
157 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
158 | [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5", | |
159 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
160 | [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6", | |
161 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
162 | [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7", | |
163 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), | |
164 | [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR), | |
53593e90 MF |
165 | [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW), |
166 | [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W), | |
fe0bd475 MF |
167 | [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT), |
168 | [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL), | |
169 | [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR), | |
170 | [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION), | |
53593e90 | 171 | [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R), |
fe0bd475 | 172 | [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT), |
53593e90 | 173 | [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R), |
fe0bd475 MF |
174 | [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG), |
175 | [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG), | |
176 | [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION), | |
177 | [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT), | |
178 | [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1", | |
179 | XTENSA_OPTION_TIMER_INTERRUPT), | |
180 | [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2", | |
181 | XTENSA_OPTION_TIMER_INTERRUPT), | |
b7909d81 MF |
182 | [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR), |
183 | [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR), | |
184 | [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR), | |
185 | [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR), | |
2af3da91 MF |
186 | }; |
187 | ||
fe0bd475 MF |
188 | static const XtensaReg uregnames[256] = { |
189 | [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER), | |
190 | [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR), | |
191 | [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR), | |
2af3da91 MF |
192 | }; |
193 | ||
2328826b MF |
194 | void xtensa_translate_init(void) |
195 | { | |
dedc5eae MF |
196 | static const char * const regnames[] = { |
197 | "ar0", "ar1", "ar2", "ar3", | |
198 | "ar4", "ar5", "ar6", "ar7", | |
199 | "ar8", "ar9", "ar10", "ar11", | |
200 | "ar12", "ar13", "ar14", "ar15", | |
201 | }; | |
dd519cbe MF |
202 | static const char * const fregnames[] = { |
203 | "f0", "f1", "f2", "f3", | |
204 | "f4", "f5", "f6", "f7", | |
205 | "f8", "f9", "f10", "f11", | |
206 | "f12", "f13", "f14", "f15", | |
207 | }; | |
dedc5eae MF |
208 | int i; |
209 | ||
210 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); | |
211 | cpu_pc = tcg_global_mem_new_i32(TCG_AREG0, | |
97129ac8 | 212 | offsetof(CPUXtensaState, pc), "pc"); |
dedc5eae MF |
213 | |
214 | for (i = 0; i < 16; i++) { | |
215 | cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0, | |
97129ac8 | 216 | offsetof(CPUXtensaState, regs[i]), |
dedc5eae MF |
217 | regnames[i]); |
218 | } | |
2af3da91 | 219 | |
dd519cbe MF |
220 | for (i = 0; i < 16; i++) { |
221 | cpu_FR[i] = tcg_global_mem_new_i32(TCG_AREG0, | |
222 | offsetof(CPUXtensaState, fregs[i]), | |
223 | fregnames[i]); | |
224 | } | |
225 | ||
2af3da91 | 226 | for (i = 0; i < 256; ++i) { |
fe0bd475 | 227 | if (sregnames[i].name) { |
2af3da91 | 228 | cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0, |
97129ac8 | 229 | offsetof(CPUXtensaState, sregs[i]), |
fe0bd475 | 230 | sregnames[i].name); |
2af3da91 MF |
231 | } |
232 | } | |
233 | ||
234 | for (i = 0; i < 256; ++i) { | |
fe0bd475 | 235 | if (uregnames[i].name) { |
2af3da91 | 236 | cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0, |
97129ac8 | 237 | offsetof(CPUXtensaState, uregs[i]), |
fe0bd475 | 238 | uregnames[i].name); |
2af3da91 MF |
239 | } |
240 | } | |
dedc5eae | 241 | #define GEN_HELPER 2 |
16c1deae | 242 | #include "helper.h" |
dedc5eae MF |
243 | } |
244 | ||
b67ea0cd MF |
245 | static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt) |
246 | { | |
247 | return xtensa_option_bits_enabled(dc->config, opt); | |
248 | } | |
249 | ||
dedc5eae MF |
250 | static inline bool option_enabled(DisasContext *dc, int opt) |
251 | { | |
252 | return xtensa_option_enabled(dc->config, opt); | |
253 | } | |
254 | ||
6ad6dbf7 MF |
255 | static void init_litbase(DisasContext *dc) |
256 | { | |
257 | if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { | |
258 | dc->litbase = tcg_temp_local_new_i32(); | |
259 | tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000); | |
260 | } | |
261 | } | |
262 | ||
263 | static void reset_litbase(DisasContext *dc) | |
264 | { | |
265 | if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { | |
266 | tcg_temp_free(dc->litbase); | |
267 | } | |
268 | } | |
269 | ||
3580ecad MF |
270 | static void init_sar_tracker(DisasContext *dc) |
271 | { | |
272 | dc->sar_5bit = false; | |
273 | dc->sar_m32_5bit = false; | |
274 | dc->sar_m32_allocated = false; | |
275 | } | |
276 | ||
277 | static void reset_sar_tracker(DisasContext *dc) | |
278 | { | |
279 | if (dc->sar_m32_allocated) { | |
280 | tcg_temp_free(dc->sar_m32); | |
281 | } | |
282 | } | |
283 | ||
284 | static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa) | |
285 | { | |
286 | tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f); | |
287 | if (dc->sar_m32_5bit) { | |
288 | tcg_gen_discard_i32(dc->sar_m32); | |
289 | } | |
290 | dc->sar_5bit = true; | |
291 | dc->sar_m32_5bit = false; | |
292 | } | |
293 | ||
294 | static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa) | |
295 | { | |
296 | TCGv_i32 tmp = tcg_const_i32(32); | |
297 | if (!dc->sar_m32_allocated) { | |
298 | dc->sar_m32 = tcg_temp_local_new_i32(); | |
299 | dc->sar_m32_allocated = true; | |
300 | } | |
301 | tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f); | |
302 | tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32); | |
303 | dc->sar_5bit = false; | |
304 | dc->sar_m32_5bit = true; | |
305 | tcg_temp_free(tmp); | |
306 | } | |
307 | ||
908c67fc | 308 | static void gen_advance_ccount_cond(DisasContext *dc) |
b994e91b MF |
309 | { |
310 | if (dc->ccount_delta > 0) { | |
311 | TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta); | |
f492b82d | 312 | gen_helper_advance_ccount(cpu_env, tmp); |
b994e91b MF |
313 | tcg_temp_free(tmp); |
314 | } | |
315 | } | |
316 | ||
908c67fc MF |
317 | static void gen_advance_ccount(DisasContext *dc) |
318 | { | |
319 | gen_advance_ccount_cond(dc); | |
320 | dc->ccount_delta = 0; | |
321 | } | |
322 | ||
772177c1 MF |
323 | static void reset_used_window(DisasContext *dc) |
324 | { | |
325 | dc->used_window = 0; | |
326 | } | |
327 | ||
b994e91b | 328 | static void gen_exception(DisasContext *dc, int excp) |
dedc5eae MF |
329 | { |
330 | TCGv_i32 tmp = tcg_const_i32(excp); | |
b994e91b | 331 | gen_advance_ccount(dc); |
f492b82d | 332 | gen_helper_exception(cpu_env, tmp); |
dedc5eae MF |
333 | tcg_temp_free(tmp); |
334 | } | |
335 | ||
40643d7c MF |
336 | static void gen_exception_cause(DisasContext *dc, uint32_t cause) |
337 | { | |
338 | TCGv_i32 tpc = tcg_const_i32(dc->pc); | |
339 | TCGv_i32 tcause = tcg_const_i32(cause); | |
b994e91b | 340 | gen_advance_ccount(dc); |
f492b82d | 341 | gen_helper_exception_cause(cpu_env, tpc, tcause); |
40643d7c MF |
342 | tcg_temp_free(tpc); |
343 | tcg_temp_free(tcause); | |
6b814719 MF |
344 | if (cause == ILLEGAL_INSTRUCTION_CAUSE || |
345 | cause == SYSCALL_CAUSE) { | |
346 | dc->is_jmp = DISAS_UPDATE; | |
347 | } | |
40643d7c MF |
348 | } |
349 | ||
5b4e481b MF |
350 | static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause, |
351 | TCGv_i32 vaddr) | |
352 | { | |
353 | TCGv_i32 tpc = tcg_const_i32(dc->pc); | |
354 | TCGv_i32 tcause = tcg_const_i32(cause); | |
b994e91b | 355 | gen_advance_ccount(dc); |
f492b82d | 356 | gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr); |
5b4e481b MF |
357 | tcg_temp_free(tpc); |
358 | tcg_temp_free(tcause); | |
359 | } | |
360 | ||
e61dc8f7 MF |
361 | static void gen_debug_exception(DisasContext *dc, uint32_t cause) |
362 | { | |
363 | TCGv_i32 tpc = tcg_const_i32(dc->pc); | |
364 | TCGv_i32 tcause = tcg_const_i32(cause); | |
365 | gen_advance_ccount(dc); | |
f492b82d | 366 | gen_helper_debug_exception(cpu_env, tpc, tcause); |
e61dc8f7 MF |
367 | tcg_temp_free(tpc); |
368 | tcg_temp_free(tcause); | |
369 | if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) { | |
370 | dc->is_jmp = DISAS_UPDATE; | |
371 | } | |
372 | } | |
373 | ||
40643d7c MF |
374 | static void gen_check_privilege(DisasContext *dc) |
375 | { | |
376 | if (dc->cring) { | |
377 | gen_exception_cause(dc, PRIVILEGED_CAUSE); | |
6b814719 | 378 | dc->is_jmp = DISAS_UPDATE; |
40643d7c MF |
379 | } |
380 | } | |
381 | ||
ef04a846 MF |
382 | static void gen_check_cpenable(DisasContext *dc, unsigned cp) |
383 | { | |
384 | if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && | |
385 | !(dc->cpenable & (1 << cp))) { | |
386 | gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp); | |
387 | dc->is_jmp = DISAS_UPDATE; | |
388 | } | |
389 | } | |
390 | ||
dedc5eae MF |
391 | static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot) |
392 | { | |
393 | tcg_gen_mov_i32(cpu_pc, dest); | |
35b5c044 MF |
394 | gen_advance_ccount(dc); |
395 | if (dc->icount) { | |
396 | tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); | |
397 | } | |
dedc5eae | 398 | if (dc->singlestep_enabled) { |
b994e91b | 399 | gen_exception(dc, EXCP_DEBUG); |
dedc5eae MF |
400 | } else { |
401 | if (slot >= 0) { | |
402 | tcg_gen_goto_tb(slot); | |
8cfd0495 | 403 | tcg_gen_exit_tb((uintptr_t)dc->tb + slot); |
dedc5eae MF |
404 | } else { |
405 | tcg_gen_exit_tb(0); | |
406 | } | |
407 | } | |
408 | dc->is_jmp = DISAS_UPDATE; | |
409 | } | |
410 | ||
67882fd1 MF |
411 | static void gen_jump(DisasContext *dc, TCGv dest) |
412 | { | |
413 | gen_jump_slot(dc, dest, -1); | |
414 | } | |
415 | ||
dedc5eae MF |
416 | static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot) |
417 | { | |
418 | TCGv_i32 tmp = tcg_const_i32(dest); | |
419 | if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) { | |
420 | slot = -1; | |
421 | } | |
422 | gen_jump_slot(dc, tmp, slot); | |
423 | tcg_temp_free(tmp); | |
424 | } | |
425 | ||
553e44f9 MF |
426 | static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest, |
427 | int slot) | |
428 | { | |
429 | TCGv_i32 tcallinc = tcg_const_i32(callinc); | |
430 | ||
431 | tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS], | |
432 | tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN); | |
433 | tcg_temp_free(tcallinc); | |
434 | tcg_gen_movi_i32(cpu_R[callinc << 2], | |
435 | (callinc << 30) | (dc->next_pc & 0x3fffffff)); | |
436 | gen_jump_slot(dc, dest, slot); | |
437 | } | |
438 | ||
439 | static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest) | |
440 | { | |
441 | gen_callw_slot(dc, callinc, dest, -1); | |
442 | } | |
443 | ||
444 | static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot) | |
445 | { | |
446 | TCGv_i32 tmp = tcg_const_i32(dest); | |
447 | if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) { | |
448 | slot = -1; | |
449 | } | |
450 | gen_callw_slot(dc, callinc, tmp, slot); | |
451 | tcg_temp_free(tmp); | |
452 | } | |
453 | ||
797d780b MF |
454 | static bool gen_check_loop_end(DisasContext *dc, int slot) |
455 | { | |
456 | if (option_enabled(dc, XTENSA_OPTION_LOOP) && | |
457 | !(dc->tb->flags & XTENSA_TBFLAG_EXCM) && | |
458 | dc->next_pc == dc->lend) { | |
459 | int label = gen_new_label(); | |
460 | ||
d865f307 | 461 | gen_advance_ccount(dc); |
797d780b MF |
462 | tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label); |
463 | tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1); | |
464 | gen_jumpi(dc, dc->lbeg, slot); | |
465 | gen_set_label(label); | |
466 | gen_jumpi(dc, dc->next_pc, -1); | |
467 | return true; | |
468 | } | |
469 | return false; | |
470 | } | |
471 | ||
472 | static void gen_jumpi_check_loop_end(DisasContext *dc, int slot) | |
473 | { | |
474 | if (!gen_check_loop_end(dc, slot)) { | |
475 | gen_jumpi(dc, dc->next_pc, slot); | |
476 | } | |
477 | } | |
478 | ||
bd57fb91 MF |
479 | static void gen_brcond(DisasContext *dc, TCGCond cond, |
480 | TCGv_i32 t0, TCGv_i32 t1, uint32_t offset) | |
481 | { | |
482 | int label = gen_new_label(); | |
483 | ||
d865f307 | 484 | gen_advance_ccount(dc); |
bd57fb91 | 485 | tcg_gen_brcond_i32(cond, t0, t1, label); |
797d780b | 486 | gen_jumpi_check_loop_end(dc, 0); |
bd57fb91 MF |
487 | gen_set_label(label); |
488 | gen_jumpi(dc, dc->pc + offset, 1); | |
489 | } | |
490 | ||
491 | static void gen_brcondi(DisasContext *dc, TCGCond cond, | |
492 | TCGv_i32 t0, uint32_t t1, uint32_t offset) | |
493 | { | |
494 | TCGv_i32 tmp = tcg_const_i32(t1); | |
495 | gen_brcond(dc, cond, t0, tmp, offset); | |
496 | tcg_temp_free(tmp); | |
497 | } | |
498 | ||
0857a06e | 499 | static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access) |
fe0bd475 MF |
500 | { |
501 | if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) { | |
502 | if (sregnames[sr].name) { | |
503 | qemu_log("SR %s is not configured\n", sregnames[sr].name); | |
504 | } else { | |
505 | qemu_log("SR %d is not implemented\n", sr); | |
506 | } | |
507 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); | |
0857a06e | 508 | return false; |
53593e90 MF |
509 | } else if (!(sregnames[sr].access & access)) { |
510 | static const char * const access_text[] = { | |
511 | [SR_R] = "rsr", | |
512 | [SR_W] = "wsr", | |
513 | [SR_X] = "xsr", | |
514 | }; | |
515 | assert(access < ARRAY_SIZE(access_text) && access_text[access]); | |
516 | qemu_log("SR %s is not available for %s\n", sregnames[sr].name, | |
517 | access_text[access]); | |
518 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); | |
0857a06e | 519 | return false; |
fe0bd475 | 520 | } |
0857a06e | 521 | return true; |
fe0bd475 MF |
522 | } |
523 | ||
b994e91b MF |
524 | static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr) |
525 | { | |
526 | gen_advance_ccount(dc); | |
527 | tcg_gen_mov_i32(d, cpu_SR[sr]); | |
528 | } | |
529 | ||
b67ea0cd MF |
530 | static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr) |
531 | { | |
532 | tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10); | |
533 | tcg_gen_or_i32(d, d, cpu_SR[sr]); | |
534 | tcg_gen_andi_i32(d, d, 0xfffffffc); | |
535 | } | |
536 | ||
b8132eff MF |
537 | static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr) |
538 | { | |
539 | static void (* const rsr_handler[256])(DisasContext *dc, | |
540 | TCGv_i32 d, uint32_t sr) = { | |
b994e91b | 541 | [CCOUNT] = gen_rsr_ccount, |
b67ea0cd | 542 | [PTEVADDR] = gen_rsr_ptevaddr, |
b8132eff MF |
543 | }; |
544 | ||
fe0bd475 MF |
545 | if (rsr_handler[sr]) { |
546 | rsr_handler[sr](dc, d, sr); | |
b8132eff | 547 | } else { |
fe0bd475 | 548 | tcg_gen_mov_i32(d, cpu_SR[sr]); |
b8132eff MF |
549 | } |
550 | } | |
551 | ||
797d780b MF |
552 | static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
553 | { | |
f492b82d | 554 | gen_helper_wsr_lbeg(cpu_env, s); |
3d0be8a5 | 555 | gen_jumpi_check_loop_end(dc, 0); |
797d780b MF |
556 | } |
557 | ||
558 | static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s) | |
559 | { | |
f492b82d | 560 | gen_helper_wsr_lend(cpu_env, s); |
3d0be8a5 | 561 | gen_jumpi_check_loop_end(dc, 0); |
797d780b MF |
562 | } |
563 | ||
3580ecad MF |
564 | static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
565 | { | |
566 | tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f); | |
567 | if (dc->sar_m32_5bit) { | |
568 | tcg_gen_discard_i32(dc->sar_m32); | |
569 | } | |
570 | dc->sar_5bit = false; | |
571 | dc->sar_m32_5bit = false; | |
572 | } | |
573 | ||
4dd85b6b MF |
574 | static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
575 | { | |
576 | tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff); | |
577 | } | |
578 | ||
6ad6dbf7 MF |
579 | static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
580 | { | |
581 | tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001); | |
582 | /* This can change tb->flags, so exit tb */ | |
583 | gen_jumpi_check_loop_end(dc, -1); | |
584 | } | |
585 | ||
6825b6c3 MF |
586 | static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
587 | { | |
588 | tcg_gen_ext8s_i32(cpu_SR[sr], s); | |
589 | } | |
590 | ||
553e44f9 MF |
591 | static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
592 | { | |
f492b82d | 593 | gen_helper_wsr_windowbase(cpu_env, v); |
772177c1 MF |
594 | reset_used_window(dc); |
595 | } | |
596 | ||
597 | static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v) | |
598 | { | |
53a72dfd | 599 | tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1); |
772177c1 | 600 | reset_used_window(dc); |
553e44f9 MF |
601 | } |
602 | ||
b67ea0cd MF |
603 | static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
604 | { | |
605 | tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000); | |
606 | } | |
607 | ||
608 | static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v) | |
609 | { | |
f492b82d | 610 | gen_helper_wsr_rasid(cpu_env, v); |
b67ea0cd MF |
611 | /* This can change tb->flags, so exit tb */ |
612 | gen_jumpi_check_loop_end(dc, -1); | |
613 | } | |
614 | ||
615 | static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v) | |
616 | { | |
617 | tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000); | |
618 | } | |
619 | ||
e61dc8f7 MF |
620 | static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
621 | { | |
f492b82d | 622 | gen_helper_wsr_ibreakenable(cpu_env, v); |
e61dc8f7 MF |
623 | gen_jumpi_check_loop_end(dc, 0); |
624 | } | |
625 | ||
fcc803d1 MF |
626 | static void gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
627 | { | |
628 | tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f); | |
629 | } | |
630 | ||
e61dc8f7 MF |
631 | static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
632 | { | |
633 | unsigned id = sr - IBREAKA; | |
634 | ||
635 | if (id < dc->config->nibreak) { | |
636 | TCGv_i32 tmp = tcg_const_i32(id); | |
f492b82d | 637 | gen_helper_wsr_ibreaka(cpu_env, tmp, v); |
e61dc8f7 MF |
638 | tcg_temp_free(tmp); |
639 | gen_jumpi_check_loop_end(dc, 0); | |
640 | } | |
641 | } | |
642 | ||
f14c4b5f MF |
643 | static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
644 | { | |
645 | unsigned id = sr - DBREAKA; | |
646 | ||
647 | if (id < dc->config->ndbreak) { | |
648 | TCGv_i32 tmp = tcg_const_i32(id); | |
f492b82d | 649 | gen_helper_wsr_dbreaka(cpu_env, tmp, v); |
f14c4b5f MF |
650 | tcg_temp_free(tmp); |
651 | } | |
652 | } | |
653 | ||
654 | static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v) | |
655 | { | |
656 | unsigned id = sr - DBREAKC; | |
657 | ||
658 | if (id < dc->config->ndbreak) { | |
659 | TCGv_i32 tmp = tcg_const_i32(id); | |
f492b82d | 660 | gen_helper_wsr_dbreakc(cpu_env, tmp, v); |
f14c4b5f MF |
661 | tcg_temp_free(tmp); |
662 | } | |
663 | } | |
664 | ||
ef04a846 MF |
665 | static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
666 | { | |
667 | tcg_gen_andi_i32(cpu_SR[sr], v, 0xff); | |
668 | /* This can change tb->flags, so exit tb */ | |
669 | gen_jumpi_check_loop_end(dc, -1); | |
670 | } | |
671 | ||
b994e91b MF |
672 | static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
673 | { | |
674 | tcg_gen_andi_i32(cpu_SR[sr], v, | |
675 | dc->config->inttype_mask[INTTYPE_SOFTWARE]); | |
676 | gen_helper_check_interrupts(cpu_env); | |
677 | gen_jumpi_check_loop_end(dc, 0); | |
678 | } | |
679 | ||
680 | static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v) | |
681 | { | |
682 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
683 | ||
684 | tcg_gen_andi_i32(tmp, v, | |
685 | dc->config->inttype_mask[INTTYPE_EDGE] | | |
686 | dc->config->inttype_mask[INTTYPE_NMI] | | |
687 | dc->config->inttype_mask[INTTYPE_SOFTWARE]); | |
688 | tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp); | |
689 | tcg_temp_free(tmp); | |
690 | gen_helper_check_interrupts(cpu_env); | |
691 | } | |
692 | ||
693 | static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) | |
694 | { | |
695 | tcg_gen_mov_i32(cpu_SR[sr], v); | |
696 | gen_helper_check_interrupts(cpu_env); | |
697 | gen_jumpi_check_loop_end(dc, 0); | |
698 | } | |
699 | ||
f0a548b9 MF |
700 | static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
701 | { | |
702 | uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB | | |
703 | PS_UM | PS_EXCM | PS_INTLEVEL; | |
704 | ||
705 | if (option_enabled(dc, XTENSA_OPTION_MMU)) { | |
706 | mask |= PS_RING; | |
707 | } | |
708 | tcg_gen_andi_i32(cpu_SR[sr], v, mask); | |
772177c1 | 709 | reset_used_window(dc); |
b994e91b MF |
710 | gen_helper_check_interrupts(cpu_env); |
711 | /* This can change mmu index and tb->flags, so exit tb */ | |
797d780b | 712 | gen_jumpi_check_loop_end(dc, -1); |
f0a548b9 MF |
713 | } |
714 | ||
35b5c044 MF |
715 | static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
716 | { | |
717 | if (dc->icount) { | |
718 | tcg_gen_mov_i32(dc->next_icount, v); | |
719 | } else { | |
720 | tcg_gen_mov_i32(cpu_SR[sr], v); | |
721 | } | |
722 | } | |
723 | ||
724 | static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v) | |
725 | { | |
726 | tcg_gen_andi_i32(cpu_SR[sr], v, 0xf); | |
727 | /* This can change tb->flags, so exit tb */ | |
728 | gen_jumpi_check_loop_end(dc, -1); | |
729 | } | |
730 | ||
b994e91b MF |
731 | static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v) |
732 | { | |
733 | uint32_t id = sr - CCOMPARE; | |
734 | if (id < dc->config->nccompare) { | |
735 | uint32_t int_bit = 1 << dc->config->timerint[id]; | |
736 | gen_advance_ccount(dc); | |
737 | tcg_gen_mov_i32(cpu_SR[sr], v); | |
738 | tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit); | |
739 | gen_helper_check_interrupts(cpu_env); | |
740 | } | |
741 | } | |
742 | ||
b8132eff MF |
743 | static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s) |
744 | { | |
745 | static void (* const wsr_handler[256])(DisasContext *dc, | |
746 | uint32_t sr, TCGv_i32 v) = { | |
797d780b MF |
747 | [LBEG] = gen_wsr_lbeg, |
748 | [LEND] = gen_wsr_lend, | |
3580ecad | 749 | [SAR] = gen_wsr_sar, |
4dd85b6b | 750 | [BR] = gen_wsr_br, |
6ad6dbf7 | 751 | [LITBASE] = gen_wsr_litbase, |
6825b6c3 | 752 | [ACCHI] = gen_wsr_acchi, |
553e44f9 | 753 | [WINDOW_BASE] = gen_wsr_windowbase, |
772177c1 | 754 | [WINDOW_START] = gen_wsr_windowstart, |
b67ea0cd MF |
755 | [PTEVADDR] = gen_wsr_ptevaddr, |
756 | [RASID] = gen_wsr_rasid, | |
757 | [ITLBCFG] = gen_wsr_tlbcfg, | |
758 | [DTLBCFG] = gen_wsr_tlbcfg, | |
e61dc8f7 | 759 | [IBREAKENABLE] = gen_wsr_ibreakenable, |
fcc803d1 | 760 | [ATOMCTL] = gen_wsr_atomctl, |
e61dc8f7 MF |
761 | [IBREAKA] = gen_wsr_ibreaka, |
762 | [IBREAKA + 1] = gen_wsr_ibreaka, | |
f14c4b5f MF |
763 | [DBREAKA] = gen_wsr_dbreaka, |
764 | [DBREAKA + 1] = gen_wsr_dbreaka, | |
765 | [DBREAKC] = gen_wsr_dbreakc, | |
766 | [DBREAKC + 1] = gen_wsr_dbreakc, | |
ef04a846 | 767 | [CPENABLE] = gen_wsr_cpenable, |
b994e91b MF |
768 | [INTSET] = gen_wsr_intset, |
769 | [INTCLEAR] = gen_wsr_intclear, | |
770 | [INTENABLE] = gen_wsr_intenable, | |
f0a548b9 | 771 | [PS] = gen_wsr_ps, |
35b5c044 MF |
772 | [ICOUNT] = gen_wsr_icount, |
773 | [ICOUNTLEVEL] = gen_wsr_icountlevel, | |
b994e91b MF |
774 | [CCOMPARE] = gen_wsr_ccompare, |
775 | [CCOMPARE + 1] = gen_wsr_ccompare, | |
776 | [CCOMPARE + 2] = gen_wsr_ccompare, | |
b8132eff MF |
777 | }; |
778 | ||
fe0bd475 MF |
779 | if (wsr_handler[sr]) { |
780 | wsr_handler[sr](dc, sr, s); | |
b8132eff | 781 | } else { |
fe0bd475 | 782 | tcg_gen_mov_i32(cpu_SR[sr], s); |
b8132eff MF |
783 | } |
784 | } | |
785 | ||
dd519cbe MF |
786 | static void gen_wur(uint32_t ur, TCGv_i32 s) |
787 | { | |
788 | switch (ur) { | |
789 | case FCR: | |
790 | gen_helper_wur_fcr(cpu_env, s); | |
791 | break; | |
792 | ||
793 | case FSR: | |
794 | tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80); | |
795 | break; | |
796 | ||
797 | default: | |
798 | tcg_gen_mov_i32(cpu_UR[ur], s); | |
799 | break; | |
800 | } | |
801 | } | |
802 | ||
5b4e481b MF |
803 | static void gen_load_store_alignment(DisasContext *dc, int shift, |
804 | TCGv_i32 addr, bool no_hw_alignment) | |
805 | { | |
806 | if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) { | |
807 | tcg_gen_andi_i32(addr, addr, ~0 << shift); | |
808 | } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) && | |
809 | no_hw_alignment) { | |
810 | int label = gen_new_label(); | |
811 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
812 | tcg_gen_andi_i32(tmp, addr, ~(~0 << shift)); | |
813 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label); | |
814 | gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr); | |
815 | gen_set_label(label); | |
816 | tcg_temp_free(tmp); | |
817 | } | |
818 | } | |
819 | ||
b994e91b MF |
820 | static void gen_waiti(DisasContext *dc, uint32_t imm4) |
821 | { | |
822 | TCGv_i32 pc = tcg_const_i32(dc->next_pc); | |
823 | TCGv_i32 intlevel = tcg_const_i32(imm4); | |
824 | gen_advance_ccount(dc); | |
f492b82d | 825 | gen_helper_waiti(cpu_env, pc, intlevel); |
b994e91b MF |
826 | tcg_temp_free(pc); |
827 | tcg_temp_free(intlevel); | |
828 | } | |
829 | ||
772177c1 MF |
830 | static void gen_window_check1(DisasContext *dc, unsigned r1) |
831 | { | |
832 | if (dc->tb->flags & XTENSA_TBFLAG_EXCM) { | |
833 | return; | |
834 | } | |
835 | if (option_enabled(dc, XTENSA_OPTION_WINDOWED_REGISTER) && | |
836 | r1 / 4 > dc->used_window) { | |
908c67fc MF |
837 | int label = gen_new_label(); |
838 | TCGv_i32 ws = tcg_temp_new_i32(); | |
772177c1 MF |
839 | |
840 | dc->used_window = r1 / 4; | |
908c67fc MF |
841 | tcg_gen_deposit_i32(ws, cpu_SR[WINDOW_START], cpu_SR[WINDOW_START], |
842 | dc->config->nareg / 4, dc->config->nareg / 4); | |
843 | tcg_gen_shr_i32(ws, ws, cpu_SR[WINDOW_BASE]); | |
844 | tcg_gen_andi_i32(ws, ws, (2 << (r1 / 4)) - 2); | |
845 | tcg_gen_brcondi_i32(TCG_COND_EQ, ws, 0, label); | |
846 | { | |
847 | TCGv_i32 pc = tcg_const_i32(dc->pc); | |
848 | TCGv_i32 w = tcg_const_i32(r1 / 4); | |
849 | ||
850 | gen_advance_ccount_cond(dc); | |
851 | gen_helper_window_check(cpu_env, pc, w); | |
852 | ||
853 | tcg_temp_free(w); | |
854 | tcg_temp_free(pc); | |
855 | } | |
856 | gen_set_label(label); | |
857 | tcg_temp_free(ws); | |
772177c1 MF |
858 | } |
859 | } | |
860 | ||
861 | static void gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2) | |
862 | { | |
863 | gen_window_check1(dc, r1 > r2 ? r1 : r2); | |
864 | } | |
865 | ||
866 | static void gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2, | |
867 | unsigned r3) | |
868 | { | |
869 | gen_window_check2(dc, r1, r2 > r3 ? r2 : r3); | |
870 | } | |
871 | ||
6825b6c3 MF |
872 | static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned) |
873 | { | |
874 | TCGv_i32 m = tcg_temp_new_i32(); | |
875 | ||
876 | if (hi) { | |
877 | (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16); | |
878 | } else { | |
879 | (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v); | |
880 | } | |
881 | return m; | |
882 | } | |
883 | ||
0c4fabea | 884 | static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) |
dedc5eae | 885 | { |
b67ea0cd MF |
886 | #define HAS_OPTION_BITS(opt) do { \ |
887 | if (!option_bits_enabled(dc, opt)) { \ | |
888 | qemu_log("Option is not enabled %s:%d\n", \ | |
889 | __FILE__, __LINE__); \ | |
dedc5eae MF |
890 | goto invalid_opcode; \ |
891 | } \ | |
892 | } while (0) | |
893 | ||
b67ea0cd MF |
894 | #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt)) |
895 | ||
91a5bb76 MF |
896 | #define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__) |
897 | #define RESERVED() do { \ | |
898 | qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \ | |
899 | dc->pc, b0, b1, b2, __FILE__, __LINE__); \ | |
900 | goto invalid_opcode; \ | |
901 | } while (0) | |
902 | ||
903 | ||
dedc5eae MF |
904 | #ifdef TARGET_WORDS_BIGENDIAN |
905 | #define OP0 (((b0) & 0xf0) >> 4) | |
906 | #define OP1 (((b2) & 0xf0) >> 4) | |
907 | #define OP2 ((b2) & 0xf) | |
908 | #define RRR_R ((b1) & 0xf) | |
909 | #define RRR_S (((b1) & 0xf0) >> 4) | |
910 | #define RRR_T ((b0) & 0xf) | |
911 | #else | |
912 | #define OP0 (((b0) & 0xf)) | |
913 | #define OP1 (((b2) & 0xf)) | |
914 | #define OP2 (((b2) & 0xf0) >> 4) | |
915 | #define RRR_R (((b1) & 0xf0) >> 4) | |
916 | #define RRR_S (((b1) & 0xf)) | |
917 | #define RRR_T (((b0) & 0xf0) >> 4) | |
918 | #endif | |
6825b6c3 MF |
919 | #define RRR_X ((RRR_R & 0x4) >> 2) |
920 | #define RRR_Y ((RRR_T & 0x4) >> 2) | |
921 | #define RRR_W (RRR_R & 0x3) | |
dedc5eae MF |
922 | |
923 | #define RRRN_R RRR_R | |
924 | #define RRRN_S RRR_S | |
925 | #define RRRN_T RRR_T | |
926 | ||
927 | #define RRI8_R RRR_R | |
928 | #define RRI8_S RRR_S | |
929 | #define RRI8_T RRR_T | |
930 | #define RRI8_IMM8 (b2) | |
931 | #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8) | |
932 | ||
933 | #ifdef TARGET_WORDS_BIGENDIAN | |
934 | #define RI16_IMM16 (((b1) << 8) | (b2)) | |
935 | #else | |
936 | #define RI16_IMM16 (((b2) << 8) | (b1)) | |
937 | #endif | |
938 | ||
939 | #ifdef TARGET_WORDS_BIGENDIAN | |
940 | #define CALL_N (((b0) & 0xc) >> 2) | |
941 | #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2)) | |
942 | #else | |
943 | #define CALL_N (((b0) & 0x30) >> 4) | |
944 | #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10)) | |
945 | #endif | |
946 | #define CALL_OFFSET_SE \ | |
947 | (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET) | |
948 | ||
949 | #define CALLX_N CALL_N | |
950 | #ifdef TARGET_WORDS_BIGENDIAN | |
951 | #define CALLX_M ((b0) & 0x3) | |
952 | #else | |
953 | #define CALLX_M (((b0) & 0xc0) >> 6) | |
954 | #endif | |
955 | #define CALLX_S RRR_S | |
956 | ||
957 | #define BRI12_M CALLX_M | |
958 | #define BRI12_S RRR_S | |
959 | #ifdef TARGET_WORDS_BIGENDIAN | |
960 | #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2)) | |
961 | #else | |
962 | #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4)) | |
963 | #endif | |
964 | #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12) | |
965 | ||
966 | #define BRI8_M BRI12_M | |
967 | #define BRI8_R RRI8_R | |
968 | #define BRI8_S RRI8_S | |
969 | #define BRI8_IMM8 RRI8_IMM8 | |
970 | #define BRI8_IMM8_SE RRI8_IMM8_SE | |
971 | ||
972 | #define RSR_SR (b1) | |
973 | ||
0c4fabea BS |
974 | uint8_t b0 = cpu_ldub_code(env, dc->pc); |
975 | uint8_t b1 = cpu_ldub_code(env, dc->pc + 1); | |
a044ec2a | 976 | uint8_t b2 = 0; |
dedc5eae | 977 | |
bd57fb91 MF |
978 | static const uint32_t B4CONST[] = { |
979 | 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256 | |
980 | }; | |
981 | ||
982 | static const uint32_t B4CONSTU[] = { | |
983 | 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256 | |
984 | }; | |
985 | ||
dedc5eae MF |
986 | if (OP0 >= 8) { |
987 | dc->next_pc = dc->pc + 2; | |
988 | HAS_OPTION(XTENSA_OPTION_CODE_DENSITY); | |
989 | } else { | |
990 | dc->next_pc = dc->pc + 3; | |
0c4fabea | 991 | b2 = cpu_ldub_code(env, dc->pc + 2); |
dedc5eae MF |
992 | } |
993 | ||
994 | switch (OP0) { | |
995 | case 0: /*QRST*/ | |
996 | switch (OP1) { | |
997 | case 0: /*RST0*/ | |
998 | switch (OP2) { | |
999 | case 0: /*ST0*/ | |
1000 | if ((RRR_R & 0xc) == 0x8) { | |
1001 | HAS_OPTION(XTENSA_OPTION_BOOLEAN); | |
1002 | } | |
1003 | ||
1004 | switch (RRR_R) { | |
1005 | case 0: /*SNM0*/ | |
5da4a6a8 MF |
1006 | switch (CALLX_M) { |
1007 | case 0: /*ILL*/ | |
40643d7c | 1008 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
5da4a6a8 MF |
1009 | break; |
1010 | ||
1011 | case 1: /*reserved*/ | |
91a5bb76 | 1012 | RESERVED(); |
5da4a6a8 MF |
1013 | break; |
1014 | ||
1015 | case 2: /*JR*/ | |
1016 | switch (CALLX_N) { | |
1017 | case 0: /*RET*/ | |
1018 | case 2: /*JX*/ | |
772177c1 | 1019 | gen_window_check1(dc, CALLX_S); |
5da4a6a8 MF |
1020 | gen_jump(dc, cpu_R[CALLX_S]); |
1021 | break; | |
1022 | ||
1023 | case 1: /*RETWw*/ | |
1024 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
553e44f9 MF |
1025 | { |
1026 | TCGv_i32 tmp = tcg_const_i32(dc->pc); | |
b994e91b | 1027 | gen_advance_ccount(dc); |
f492b82d | 1028 | gen_helper_retw(tmp, cpu_env, tmp); |
553e44f9 MF |
1029 | gen_jump(dc, tmp); |
1030 | tcg_temp_free(tmp); | |
1031 | } | |
5da4a6a8 MF |
1032 | break; |
1033 | ||
1034 | case 3: /*reserved*/ | |
91a5bb76 | 1035 | RESERVED(); |
5da4a6a8 MF |
1036 | break; |
1037 | } | |
1038 | break; | |
1039 | ||
1040 | case 3: /*CALLX*/ | |
772177c1 | 1041 | gen_window_check2(dc, CALLX_S, CALLX_N << 2); |
5da4a6a8 MF |
1042 | switch (CALLX_N) { |
1043 | case 0: /*CALLX0*/ | |
1044 | { | |
1045 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1046 | tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]); | |
1047 | tcg_gen_movi_i32(cpu_R[0], dc->next_pc); | |
1048 | gen_jump(dc, tmp); | |
1049 | tcg_temp_free(tmp); | |
1050 | } | |
1051 | break; | |
1052 | ||
1053 | case 1: /*CALLX4w*/ | |
1054 | case 2: /*CALLX8w*/ | |
1055 | case 3: /*CALLX12w*/ | |
1056 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
553e44f9 MF |
1057 | { |
1058 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1059 | ||
1060 | tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]); | |
1061 | gen_callw(dc, CALLX_N, tmp); | |
1062 | tcg_temp_free(tmp); | |
1063 | } | |
5da4a6a8 MF |
1064 | break; |
1065 | } | |
1066 | break; | |
1067 | } | |
dedc5eae MF |
1068 | break; |
1069 | ||
1070 | case 1: /*MOVSPw*/ | |
1071 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
772177c1 | 1072 | gen_window_check2(dc, RRR_T, RRR_S); |
553e44f9 MF |
1073 | { |
1074 | TCGv_i32 pc = tcg_const_i32(dc->pc); | |
b994e91b | 1075 | gen_advance_ccount(dc); |
f492b82d | 1076 | gen_helper_movsp(cpu_env, pc); |
553e44f9 MF |
1077 | tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]); |
1078 | tcg_temp_free(pc); | |
1079 | } | |
dedc5eae MF |
1080 | break; |
1081 | ||
1082 | case 2: /*SYNC*/ | |
28067b22 MF |
1083 | switch (RRR_T) { |
1084 | case 0: /*ISYNC*/ | |
1085 | break; | |
1086 | ||
1087 | case 1: /*RSYNC*/ | |
1088 | break; | |
1089 | ||
1090 | case 2: /*ESYNC*/ | |
1091 | break; | |
1092 | ||
1093 | case 3: /*DSYNC*/ | |
1094 | break; | |
1095 | ||
1096 | case 8: /*EXCW*/ | |
1097 | HAS_OPTION(XTENSA_OPTION_EXCEPTION); | |
1098 | break; | |
1099 | ||
1100 | case 12: /*MEMW*/ | |
1101 | break; | |
1102 | ||
1103 | case 13: /*EXTW*/ | |
1104 | break; | |
1105 | ||
1106 | case 15: /*NOP*/ | |
1107 | break; | |
1108 | ||
1109 | default: /*reserved*/ | |
1110 | RESERVED(); | |
1111 | break; | |
1112 | } | |
91a5bb76 MF |
1113 | break; |
1114 | ||
1115 | case 3: /*RFEIx*/ | |
40643d7c MF |
1116 | switch (RRR_T) { |
1117 | case 0: /*RFETx*/ | |
1118 | HAS_OPTION(XTENSA_OPTION_EXCEPTION); | |
1119 | switch (RRR_S) { | |
1120 | case 0: /*RFEx*/ | |
1121 | gen_check_privilege(dc); | |
1122 | tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); | |
b994e91b | 1123 | gen_helper_check_interrupts(cpu_env); |
40643d7c MF |
1124 | gen_jump(dc, cpu_SR[EPC1]); |
1125 | break; | |
1126 | ||
1127 | case 1: /*RFUEx*/ | |
1128 | RESERVED(); | |
1129 | break; | |
1130 | ||
1131 | case 2: /*RFDEx*/ | |
1132 | gen_check_privilege(dc); | |
1133 | gen_jump(dc, cpu_SR[ | |
1134 | dc->config->ndepc ? DEPC : EPC1]); | |
1135 | break; | |
1136 | ||
1137 | case 4: /*RFWOw*/ | |
1138 | case 5: /*RFWUw*/ | |
1139 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
553e44f9 MF |
1140 | gen_check_privilege(dc); |
1141 | { | |
1142 | TCGv_i32 tmp = tcg_const_i32(1); | |
1143 | ||
1144 | tcg_gen_andi_i32( | |
1145 | cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); | |
1146 | tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]); | |
1147 | ||
1148 | if (RRR_S == 4) { | |
1149 | tcg_gen_andc_i32(cpu_SR[WINDOW_START], | |
1150 | cpu_SR[WINDOW_START], tmp); | |
1151 | } else { | |
1152 | tcg_gen_or_i32(cpu_SR[WINDOW_START], | |
1153 | cpu_SR[WINDOW_START], tmp); | |
1154 | } | |
1155 | ||
f492b82d | 1156 | gen_helper_restore_owb(cpu_env); |
b994e91b | 1157 | gen_helper_check_interrupts(cpu_env); |
553e44f9 MF |
1158 | gen_jump(dc, cpu_SR[EPC1]); |
1159 | ||
1160 | tcg_temp_free(tmp); | |
1161 | } | |
40643d7c MF |
1162 | break; |
1163 | ||
1164 | default: /*reserved*/ | |
1165 | RESERVED(); | |
1166 | break; | |
1167 | } | |
1168 | break; | |
1169 | ||
1170 | case 1: /*RFIx*/ | |
1171 | HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT); | |
b994e91b MF |
1172 | if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) { |
1173 | gen_check_privilege(dc); | |
1174 | tcg_gen_mov_i32(cpu_SR[PS], | |
1175 | cpu_SR[EPS2 + RRR_S - 2]); | |
1176 | gen_helper_check_interrupts(cpu_env); | |
1177 | gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]); | |
1178 | } else { | |
1179 | qemu_log("RFI %d is illegal\n", RRR_S); | |
1180 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); | |
1181 | } | |
40643d7c MF |
1182 | break; |
1183 | ||
1184 | case 2: /*RFME*/ | |
1185 | TBD(); | |
1186 | break; | |
1187 | ||
1188 | default: /*reserved*/ | |
1189 | RESERVED(); | |
1190 | break; | |
1191 | ||
1192 | } | |
91a5bb76 MF |
1193 | break; |
1194 | ||
1195 | case 4: /*BREAKx*/ | |
e61dc8f7 MF |
1196 | HAS_OPTION(XTENSA_OPTION_DEBUG); |
1197 | if (dc->debug) { | |
1198 | gen_debug_exception(dc, DEBUGCAUSE_BI); | |
1199 | } | |
91a5bb76 MF |
1200 | break; |
1201 | ||
1202 | case 5: /*SYSCALLx*/ | |
1203 | HAS_OPTION(XTENSA_OPTION_EXCEPTION); | |
40643d7c MF |
1204 | switch (RRR_S) { |
1205 | case 0: /*SYSCALLx*/ | |
1206 | gen_exception_cause(dc, SYSCALL_CAUSE); | |
1207 | break; | |
1208 | ||
1209 | case 1: /*SIMCALL*/ | |
1ddeaa5d MF |
1210 | if (semihosting_enabled) { |
1211 | gen_check_privilege(dc); | |
1212 | gen_helper_simcall(cpu_env); | |
1213 | } else { | |
1214 | qemu_log("SIMCALL but semihosting is disabled\n"); | |
1215 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); | |
1216 | } | |
40643d7c MF |
1217 | break; |
1218 | ||
1219 | default: | |
1220 | RESERVED(); | |
1221 | break; | |
1222 | } | |
91a5bb76 MF |
1223 | break; |
1224 | ||
1225 | case 6: /*RSILx*/ | |
1226 | HAS_OPTION(XTENSA_OPTION_INTERRUPT); | |
40643d7c | 1227 | gen_check_privilege(dc); |
772177c1 | 1228 | gen_window_check1(dc, RRR_T); |
40643d7c | 1229 | tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]); |
b994e91b | 1230 | tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); |
40643d7c | 1231 | tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S); |
b994e91b MF |
1232 | gen_helper_check_interrupts(cpu_env); |
1233 | gen_jumpi_check_loop_end(dc, 0); | |
91a5bb76 MF |
1234 | break; |
1235 | ||
1236 | case 7: /*WAITIx*/ | |
1237 | HAS_OPTION(XTENSA_OPTION_INTERRUPT); | |
b994e91b MF |
1238 | gen_check_privilege(dc); |
1239 | gen_waiti(dc, RRR_S); | |
91a5bb76 MF |
1240 | break; |
1241 | ||
1242 | case 8: /*ANY4p*/ | |
91a5bb76 | 1243 | case 9: /*ALL4p*/ |
91a5bb76 | 1244 | case 10: /*ANY8p*/ |
91a5bb76 MF |
1245 | case 11: /*ALL8p*/ |
1246 | HAS_OPTION(XTENSA_OPTION_BOOLEAN); | |
4dd85b6b MF |
1247 | { |
1248 | const unsigned shift = (RRR_R & 2) ? 8 : 4; | |
1249 | TCGv_i32 mask = tcg_const_i32( | |
1250 | ((1 << shift) - 1) << RRR_S); | |
1251 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1252 | ||
1253 | tcg_gen_and_i32(tmp, cpu_SR[BR], mask); | |
1254 | if (RRR_R & 1) { /*ALL*/ | |
1255 | tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S); | |
1256 | } else { /*ANY*/ | |
1257 | tcg_gen_add_i32(tmp, tmp, mask); | |
1258 | } | |
1259 | tcg_gen_shri_i32(tmp, tmp, RRR_S + shift); | |
1260 | tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], | |
1261 | tmp, RRR_T, 1); | |
1262 | tcg_temp_free(mask); | |
1263 | tcg_temp_free(tmp); | |
1264 | } | |
91a5bb76 MF |
1265 | break; |
1266 | ||
1267 | default: /*reserved*/ | |
1268 | RESERVED(); | |
dedc5eae MF |
1269 | break; |
1270 | ||
1271 | } | |
1272 | break; | |
1273 | ||
1274 | case 1: /*AND*/ | |
772177c1 | 1275 | gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
dedc5eae MF |
1276 | tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); |
1277 | break; | |
1278 | ||
1279 | case 2: /*OR*/ | |
772177c1 | 1280 | gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
dedc5eae MF |
1281 | tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); |
1282 | break; | |
1283 | ||
1284 | case 3: /*XOR*/ | |
772177c1 | 1285 | gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
dedc5eae MF |
1286 | tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); |
1287 | break; | |
1288 | ||
1289 | case 4: /*ST1*/ | |
3580ecad MF |
1290 | switch (RRR_R) { |
1291 | case 0: /*SSR*/ | |
772177c1 | 1292 | gen_window_check1(dc, RRR_S); |
3580ecad MF |
1293 | gen_right_shift_sar(dc, cpu_R[RRR_S]); |
1294 | break; | |
1295 | ||
1296 | case 1: /*SSL*/ | |
772177c1 | 1297 | gen_window_check1(dc, RRR_S); |
3580ecad MF |
1298 | gen_left_shift_sar(dc, cpu_R[RRR_S]); |
1299 | break; | |
1300 | ||
1301 | case 2: /*SSA8L*/ | |
772177c1 | 1302 | gen_window_check1(dc, RRR_S); |
3580ecad MF |
1303 | { |
1304 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1305 | tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3); | |
1306 | gen_right_shift_sar(dc, tmp); | |
1307 | tcg_temp_free(tmp); | |
1308 | } | |
1309 | break; | |
1310 | ||
1311 | case 3: /*SSA8B*/ | |
772177c1 | 1312 | gen_window_check1(dc, RRR_S); |
3580ecad MF |
1313 | { |
1314 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1315 | tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3); | |
1316 | gen_left_shift_sar(dc, tmp); | |
1317 | tcg_temp_free(tmp); | |
1318 | } | |
1319 | break; | |
1320 | ||
1321 | case 4: /*SSAI*/ | |
1322 | { | |
1323 | TCGv_i32 tmp = tcg_const_i32( | |
1324 | RRR_S | ((RRR_T & 1) << 4)); | |
1325 | gen_right_shift_sar(dc, tmp); | |
1326 | tcg_temp_free(tmp); | |
1327 | } | |
1328 | break; | |
1329 | ||
1330 | case 6: /*RER*/ | |
91a5bb76 | 1331 | TBD(); |
3580ecad MF |
1332 | break; |
1333 | ||
1334 | case 7: /*WER*/ | |
91a5bb76 | 1335 | TBD(); |
3580ecad MF |
1336 | break; |
1337 | ||
1338 | case 8: /*ROTWw*/ | |
1339 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
553e44f9 MF |
1340 | gen_check_privilege(dc); |
1341 | { | |
1342 | TCGv_i32 tmp = tcg_const_i32( | |
1343 | RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0)); | |
f492b82d | 1344 | gen_helper_rotw(cpu_env, tmp); |
553e44f9 | 1345 | tcg_temp_free(tmp); |
772177c1 | 1346 | reset_used_window(dc); |
553e44f9 | 1347 | } |
3580ecad MF |
1348 | break; |
1349 | ||
1350 | case 14: /*NSAu*/ | |
7f65f4b0 | 1351 | HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA); |
772177c1 | 1352 | gen_window_check2(dc, RRR_S, RRR_T); |
3580ecad MF |
1353 | gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]); |
1354 | break; | |
1355 | ||
1356 | case 15: /*NSAUu*/ | |
7f65f4b0 | 1357 | HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA); |
772177c1 | 1358 | gen_window_check2(dc, RRR_S, RRR_T); |
3580ecad MF |
1359 | gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]); |
1360 | break; | |
1361 | ||
1362 | default: /*reserved*/ | |
91a5bb76 | 1363 | RESERVED(); |
3580ecad MF |
1364 | break; |
1365 | } | |
dedc5eae MF |
1366 | break; |
1367 | ||
1368 | case 5: /*TLB*/ | |
b67ea0cd MF |
1369 | HAS_OPTION_BITS( |
1370 | XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) | | |
1371 | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | | |
1372 | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION)); | |
1373 | gen_check_privilege(dc); | |
1374 | gen_window_check2(dc, RRR_S, RRR_T); | |
1375 | { | |
1376 | TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0); | |
1377 | ||
1378 | switch (RRR_R & 7) { | |
1379 | case 3: /*RITLB0*/ /*RDTLB0*/ | |
f492b82d MF |
1380 | gen_helper_rtlb0(cpu_R[RRR_T], |
1381 | cpu_env, cpu_R[RRR_S], dtlb); | |
b67ea0cd MF |
1382 | break; |
1383 | ||
1384 | case 4: /*IITLB*/ /*IDTLB*/ | |
f492b82d | 1385 | gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb); |
b67ea0cd MF |
1386 | /* This could change memory mapping, so exit tb */ |
1387 | gen_jumpi_check_loop_end(dc, -1); | |
1388 | break; | |
1389 | ||
1390 | case 5: /*PITLB*/ /*PDTLB*/ | |
1391 | tcg_gen_movi_i32(cpu_pc, dc->pc); | |
f492b82d MF |
1392 | gen_helper_ptlb(cpu_R[RRR_T], |
1393 | cpu_env, cpu_R[RRR_S], dtlb); | |
b67ea0cd MF |
1394 | break; |
1395 | ||
1396 | case 6: /*WITLB*/ /*WDTLB*/ | |
f492b82d MF |
1397 | gen_helper_wtlb( |
1398 | cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb); | |
b67ea0cd MF |
1399 | /* This could change memory mapping, so exit tb */ |
1400 | gen_jumpi_check_loop_end(dc, -1); | |
1401 | break; | |
1402 | ||
1403 | case 7: /*RITLB1*/ /*RDTLB1*/ | |
f492b82d MF |
1404 | gen_helper_rtlb1(cpu_R[RRR_T], |
1405 | cpu_env, cpu_R[RRR_S], dtlb); | |
b67ea0cd MF |
1406 | break; |
1407 | ||
1408 | default: | |
1409 | tcg_temp_free(dtlb); | |
1410 | RESERVED(); | |
1411 | break; | |
1412 | } | |
1413 | tcg_temp_free(dtlb); | |
1414 | } | |
dedc5eae MF |
1415 | break; |
1416 | ||
1417 | case 6: /*RT0*/ | |
772177c1 | 1418 | gen_window_check2(dc, RRR_R, RRR_T); |
f331fe5e MF |
1419 | switch (RRR_S) { |
1420 | case 0: /*NEG*/ | |
1421 | tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]); | |
1422 | break; | |
1423 | ||
1424 | case 1: /*ABS*/ | |
1425 | { | |
f877d09e MF |
1426 | TCGv_i32 zero = tcg_const_i32(0); |
1427 | TCGv_i32 neg = tcg_temp_new_i32(); | |
1428 | ||
1429 | tcg_gen_neg_i32(neg, cpu_R[RRR_T]); | |
1430 | tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[RRR_R], | |
1431 | cpu_R[RRR_T], zero, cpu_R[RRR_T], neg); | |
1432 | tcg_temp_free(neg); | |
1433 | tcg_temp_free(zero); | |
f331fe5e MF |
1434 | } |
1435 | break; | |
1436 | ||
1437 | default: /*reserved*/ | |
91a5bb76 | 1438 | RESERVED(); |
f331fe5e MF |
1439 | break; |
1440 | } | |
dedc5eae MF |
1441 | break; |
1442 | ||
1443 | case 7: /*reserved*/ | |
91a5bb76 | 1444 | RESERVED(); |
dedc5eae MF |
1445 | break; |
1446 | ||
1447 | case 8: /*ADD*/ | |
772177c1 | 1448 | gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
dedc5eae MF |
1449 | tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); |
1450 | break; | |
1451 | ||
1452 | case 9: /*ADD**/ | |
1453 | case 10: | |
1454 | case 11: | |
772177c1 | 1455 | gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
dedc5eae MF |
1456 | { |
1457 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1458 | tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8); | |
1459 | tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]); | |
1460 | tcg_temp_free(tmp); | |
1461 | } | |
1462 | break; | |
1463 | ||
1464 | case 12: /*SUB*/ | |
772177c1 | 1465 | gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
dedc5eae MF |
1466 | tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); |
1467 | break; | |
1468 | ||
1469 | case 13: /*SUB**/ | |
1470 | case 14: | |
1471 | case 15: | |
772177c1 | 1472 | gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
dedc5eae MF |
1473 | { |
1474 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1475 | tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12); | |
1476 | tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]); | |
1477 | tcg_temp_free(tmp); | |
1478 | } | |
1479 | break; | |
1480 | } | |
1481 | break; | |
1482 | ||
1483 | case 1: /*RST1*/ | |
3580ecad MF |
1484 | switch (OP2) { |
1485 | case 0: /*SLLI*/ | |
1486 | case 1: | |
772177c1 | 1487 | gen_window_check2(dc, RRR_R, RRR_S); |
3580ecad MF |
1488 | tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S], |
1489 | 32 - (RRR_T | ((OP2 & 1) << 4))); | |
1490 | break; | |
1491 | ||
1492 | case 2: /*SRAI*/ | |
1493 | case 3: | |
772177c1 | 1494 | gen_window_check2(dc, RRR_R, RRR_T); |
3580ecad MF |
1495 | tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T], |
1496 | RRR_S | ((OP2 & 1) << 4)); | |
1497 | break; | |
1498 | ||
1499 | case 4: /*SRLI*/ | |
772177c1 | 1500 | gen_window_check2(dc, RRR_R, RRR_T); |
3580ecad MF |
1501 | tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S); |
1502 | break; | |
1503 | ||
1504 | case 6: /*XSR*/ | |
0857a06e | 1505 | if (gen_check_sr(dc, RSR_SR, SR_X)) { |
3580ecad | 1506 | TCGv_i32 tmp = tcg_temp_new_i32(); |
0857a06e | 1507 | |
40643d7c MF |
1508 | if (RSR_SR >= 64) { |
1509 | gen_check_privilege(dc); | |
1510 | } | |
772177c1 | 1511 | gen_window_check1(dc, RRR_T); |
3580ecad MF |
1512 | tcg_gen_mov_i32(tmp, cpu_R[RRR_T]); |
1513 | gen_rsr(dc, cpu_R[RRR_T], RSR_SR); | |
1514 | gen_wsr(dc, RSR_SR, tmp); | |
1515 | tcg_temp_free(tmp); | |
1516 | } | |
1517 | break; | |
1518 | ||
1519 | /* | |
1520 | * Note: 64 bit ops are used here solely because SAR values | |
1521 | * have range 0..63 | |
1522 | */ | |
1523 | #define gen_shift_reg(cmd, reg) do { \ | |
1524 | TCGv_i64 tmp = tcg_temp_new_i64(); \ | |
1525 | tcg_gen_extu_i32_i64(tmp, reg); \ | |
1526 | tcg_gen_##cmd##_i64(v, v, tmp); \ | |
1527 | tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \ | |
1528 | tcg_temp_free_i64(v); \ | |
1529 | tcg_temp_free_i64(tmp); \ | |
1530 | } while (0) | |
1531 | ||
1532 | #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR]) | |
1533 | ||
1534 | case 8: /*SRC*/ | |
772177c1 | 1535 | gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
3580ecad MF |
1536 | { |
1537 | TCGv_i64 v = tcg_temp_new_i64(); | |
1538 | tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]); | |
1539 | gen_shift(shr); | |
1540 | } | |
1541 | break; | |
1542 | ||
1543 | case 9: /*SRL*/ | |
772177c1 | 1544 | gen_window_check2(dc, RRR_R, RRR_T); |
3580ecad MF |
1545 | if (dc->sar_5bit) { |
1546 | tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]); | |
1547 | } else { | |
1548 | TCGv_i64 v = tcg_temp_new_i64(); | |
1549 | tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]); | |
1550 | gen_shift(shr); | |
1551 | } | |
1552 | break; | |
1553 | ||
1554 | case 10: /*SLL*/ | |
772177c1 | 1555 | gen_window_check2(dc, RRR_R, RRR_S); |
3580ecad MF |
1556 | if (dc->sar_m32_5bit) { |
1557 | tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32); | |
1558 | } else { | |
1559 | TCGv_i64 v = tcg_temp_new_i64(); | |
1560 | TCGv_i32 s = tcg_const_i32(32); | |
1561 | tcg_gen_sub_i32(s, s, cpu_SR[SAR]); | |
1562 | tcg_gen_andi_i32(s, s, 0x3f); | |
1563 | tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]); | |
1564 | gen_shift_reg(shl, s); | |
1565 | tcg_temp_free(s); | |
1566 | } | |
1567 | break; | |
1568 | ||
1569 | case 11: /*SRA*/ | |
772177c1 | 1570 | gen_window_check2(dc, RRR_R, RRR_T); |
3580ecad MF |
1571 | if (dc->sar_5bit) { |
1572 | tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]); | |
1573 | } else { | |
1574 | TCGv_i64 v = tcg_temp_new_i64(); | |
1575 | tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]); | |
1576 | gen_shift(sar); | |
1577 | } | |
1578 | break; | |
1579 | #undef gen_shift | |
1580 | #undef gen_shift_reg | |
1581 | ||
1582 | case 12: /*MUL16U*/ | |
1583 | HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL); | |
772177c1 | 1584 | gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
3580ecad MF |
1585 | { |
1586 | TCGv_i32 v1 = tcg_temp_new_i32(); | |
1587 | TCGv_i32 v2 = tcg_temp_new_i32(); | |
1588 | tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]); | |
1589 | tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]); | |
1590 | tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2); | |
1591 | tcg_temp_free(v2); | |
1592 | tcg_temp_free(v1); | |
1593 | } | |
1594 | break; | |
1595 | ||
1596 | case 13: /*MUL16S*/ | |
1597 | HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL); | |
772177c1 | 1598 | gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
3580ecad MF |
1599 | { |
1600 | TCGv_i32 v1 = tcg_temp_new_i32(); | |
1601 | TCGv_i32 v2 = tcg_temp_new_i32(); | |
1602 | tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]); | |
1603 | tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]); | |
1604 | tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2); | |
1605 | tcg_temp_free(v2); | |
1606 | tcg_temp_free(v1); | |
1607 | } | |
1608 | break; | |
1609 | ||
1610 | default: /*reserved*/ | |
91a5bb76 | 1611 | RESERVED(); |
3580ecad MF |
1612 | break; |
1613 | } | |
dedc5eae MF |
1614 | break; |
1615 | ||
1616 | case 2: /*RST2*/ | |
4dd85b6b MF |
1617 | if (OP2 >= 8) { |
1618 | gen_window_check3(dc, RRR_R, RRR_S, RRR_T); | |
1619 | } | |
772177c1 | 1620 | |
f76ebf55 MF |
1621 | if (OP2 >= 12) { |
1622 | HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV); | |
1623 | int label = gen_new_label(); | |
1624 | tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label); | |
1625 | gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE); | |
1626 | gen_set_label(label); | |
1627 | } | |
1628 | ||
1629 | switch (OP2) { | |
4dd85b6b MF |
1630 | #define BOOLEAN_LOGIC(fn, r, s, t) \ |
1631 | do { \ | |
1632 | HAS_OPTION(XTENSA_OPTION_BOOLEAN); \ | |
1633 | TCGv_i32 tmp1 = tcg_temp_new_i32(); \ | |
1634 | TCGv_i32 tmp2 = tcg_temp_new_i32(); \ | |
1635 | \ | |
1636 | tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \ | |
1637 | tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \ | |
1638 | tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \ | |
1639 | tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \ | |
1640 | tcg_temp_free(tmp1); \ | |
1641 | tcg_temp_free(tmp2); \ | |
1642 | } while (0) | |
1643 | ||
1644 | case 0: /*ANDBp*/ | |
1645 | BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T); | |
1646 | break; | |
1647 | ||
1648 | case 1: /*ANDBCp*/ | |
1649 | BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T); | |
1650 | break; | |
1651 | ||
1652 | case 2: /*ORBp*/ | |
1653 | BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T); | |
1654 | break; | |
1655 | ||
1656 | case 3: /*ORBCp*/ | |
1657 | BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T); | |
1658 | break; | |
1659 | ||
1660 | case 4: /*XORBp*/ | |
1661 | BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T); | |
1662 | break; | |
1663 | ||
1664 | #undef BOOLEAN_LOGIC | |
1665 | ||
f76ebf55 MF |
1666 | case 8: /*MULLi*/ |
1667 | HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL); | |
1668 | tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); | |
1669 | break; | |
1670 | ||
1671 | case 10: /*MULUHi*/ | |
1672 | case 11: /*MULSHi*/ | |
7f65f4b0 | 1673 | HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH); |
f76ebf55 | 1674 | { |
c9cda20b | 1675 | TCGv lo = tcg_temp_new(); |
f76ebf55 MF |
1676 | |
1677 | if (OP2 == 10) { | |
c9cda20b RH |
1678 | tcg_gen_mulu2_i32(lo, cpu_R[RRR_R], |
1679 | cpu_R[RRR_S], cpu_R[RRR_T]); | |
f76ebf55 | 1680 | } else { |
c9cda20b RH |
1681 | tcg_gen_muls2_i32(lo, cpu_R[RRR_R], |
1682 | cpu_R[RRR_S], cpu_R[RRR_T]); | |
f76ebf55 | 1683 | } |
c9cda20b | 1684 | tcg_temp_free(lo); |
f76ebf55 MF |
1685 | } |
1686 | break; | |
1687 | ||
1688 | case 12: /*QUOUi*/ | |
1689 | tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); | |
1690 | break; | |
1691 | ||
1692 | case 13: /*QUOSi*/ | |
1693 | case 15: /*REMSi*/ | |
1694 | { | |
1695 | int label1 = gen_new_label(); | |
1696 | int label2 = gen_new_label(); | |
1697 | ||
1698 | tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000, | |
1699 | label1); | |
1700 | tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff, | |
1701 | label1); | |
1702 | tcg_gen_movi_i32(cpu_R[RRR_R], | |
1703 | OP2 == 13 ? 0x80000000 : 0); | |
1704 | tcg_gen_br(label2); | |
1705 | gen_set_label(label1); | |
1706 | if (OP2 == 13) { | |
1707 | tcg_gen_div_i32(cpu_R[RRR_R], | |
1708 | cpu_R[RRR_S], cpu_R[RRR_T]); | |
1709 | } else { | |
1710 | tcg_gen_rem_i32(cpu_R[RRR_R], | |
1711 | cpu_R[RRR_S], cpu_R[RRR_T]); | |
1712 | } | |
1713 | gen_set_label(label2); | |
1714 | } | |
1715 | break; | |
1716 | ||
1717 | case 14: /*REMUi*/ | |
1718 | tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); | |
1719 | break; | |
1720 | ||
1721 | default: /*reserved*/ | |
1722 | RESERVED(); | |
1723 | break; | |
1724 | } | |
dedc5eae MF |
1725 | break; |
1726 | ||
1727 | case 3: /*RST3*/ | |
b8132eff MF |
1728 | switch (OP2) { |
1729 | case 0: /*RSR*/ | |
0857a06e MF |
1730 | if (gen_check_sr(dc, RSR_SR, SR_R)) { |
1731 | if (RSR_SR >= 64) { | |
1732 | gen_check_privilege(dc); | |
1733 | } | |
1734 | gen_window_check1(dc, RRR_T); | |
1735 | gen_rsr(dc, cpu_R[RRR_T], RSR_SR); | |
40643d7c | 1736 | } |
b8132eff MF |
1737 | break; |
1738 | ||
1739 | case 1: /*WSR*/ | |
0857a06e MF |
1740 | if (gen_check_sr(dc, RSR_SR, SR_W)) { |
1741 | if (RSR_SR >= 64) { | |
1742 | gen_check_privilege(dc); | |
1743 | } | |
1744 | gen_window_check1(dc, RRR_T); | |
1745 | gen_wsr(dc, RSR_SR, cpu_R[RRR_T]); | |
40643d7c | 1746 | } |
b8132eff MF |
1747 | break; |
1748 | ||
1749 | case 2: /*SEXTu*/ | |
7f65f4b0 | 1750 | HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT); |
772177c1 | 1751 | gen_window_check2(dc, RRR_R, RRR_S); |
b8132eff MF |
1752 | { |
1753 | int shift = 24 - RRR_T; | |
1754 | ||
1755 | if (shift == 24) { | |
1756 | tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]); | |
1757 | } else if (shift == 16) { | |
1758 | tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]); | |
1759 | } else { | |
1760 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1761 | tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift); | |
1762 | tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift); | |
1763 | tcg_temp_free(tmp); | |
1764 | } | |
1765 | } | |
1766 | break; | |
1767 | ||
1768 | case 3: /*CLAMPSu*/ | |
7f65f4b0 | 1769 | HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS); |
772177c1 | 1770 | gen_window_check2(dc, RRR_R, RRR_S); |
b8132eff MF |
1771 | { |
1772 | TCGv_i32 tmp1 = tcg_temp_new_i32(); | |
1773 | TCGv_i32 tmp2 = tcg_temp_new_i32(); | |
f877d09e | 1774 | TCGv_i32 zero = tcg_const_i32(0); |
b8132eff MF |
1775 | |
1776 | tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T); | |
1777 | tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]); | |
1778 | tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7)); | |
b8132eff MF |
1779 | |
1780 | tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31); | |
f877d09e | 1781 | tcg_gen_xori_i32(tmp1, tmp1, 0xffffffff >> (25 - RRR_T)); |
b8132eff | 1782 | |
f877d09e MF |
1783 | tcg_gen_movcond_i32(TCG_COND_EQ, cpu_R[RRR_R], tmp2, zero, |
1784 | cpu_R[RRR_S], tmp1); | |
b8132eff MF |
1785 | tcg_temp_free(tmp1); |
1786 | tcg_temp_free(tmp2); | |
f877d09e | 1787 | tcg_temp_free(zero); |
b8132eff MF |
1788 | } |
1789 | break; | |
1790 | ||
1791 | case 4: /*MINu*/ | |
1792 | case 5: /*MAXu*/ | |
1793 | case 6: /*MINUu*/ | |
1794 | case 7: /*MAXUu*/ | |
7f65f4b0 | 1795 | HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX); |
772177c1 | 1796 | gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
b8132eff MF |
1797 | { |
1798 | static const TCGCond cond[] = { | |
1799 | TCG_COND_LE, | |
1800 | TCG_COND_GE, | |
1801 | TCG_COND_LEU, | |
1802 | TCG_COND_GEU | |
1803 | }; | |
f877d09e MF |
1804 | tcg_gen_movcond_i32(cond[OP2 - 4], cpu_R[RRR_R], |
1805 | cpu_R[RRR_S], cpu_R[RRR_T], | |
1806 | cpu_R[RRR_S], cpu_R[RRR_T]); | |
b8132eff MF |
1807 | } |
1808 | break; | |
1809 | ||
1810 | case 8: /*MOVEQZ*/ | |
1811 | case 9: /*MOVNEZ*/ | |
1812 | case 10: /*MOVLTZ*/ | |
1813 | case 11: /*MOVGEZ*/ | |
772177c1 | 1814 | gen_window_check3(dc, RRR_R, RRR_S, RRR_T); |
b8132eff MF |
1815 | { |
1816 | static const TCGCond cond[] = { | |
b8132eff | 1817 | TCG_COND_EQ, |
f877d09e MF |
1818 | TCG_COND_NE, |
1819 | TCG_COND_LT, | |
b8132eff | 1820 | TCG_COND_GE, |
b8132eff | 1821 | }; |
f877d09e MF |
1822 | TCGv_i32 zero = tcg_const_i32(0); |
1823 | ||
1824 | tcg_gen_movcond_i32(cond[OP2 - 8], cpu_R[RRR_R], | |
1825 | cpu_R[RRR_T], zero, cpu_R[RRR_S], cpu_R[RRR_R]); | |
1826 | tcg_temp_free(zero); | |
b8132eff MF |
1827 | } |
1828 | break; | |
1829 | ||
1830 | case 12: /*MOVFp*/ | |
b8132eff MF |
1831 | case 13: /*MOVTp*/ |
1832 | HAS_OPTION(XTENSA_OPTION_BOOLEAN); | |
4dd85b6b MF |
1833 | gen_window_check2(dc, RRR_R, RRR_S); |
1834 | { | |
f877d09e | 1835 | TCGv_i32 zero = tcg_const_i32(0); |
4dd85b6b MF |
1836 | TCGv_i32 tmp = tcg_temp_new_i32(); |
1837 | ||
1838 | tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T); | |
f877d09e MF |
1839 | tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ, |
1840 | cpu_R[RRR_R], tmp, zero, | |
1841 | cpu_R[RRR_S], cpu_R[RRR_R]); | |
1842 | ||
4dd85b6b | 1843 | tcg_temp_free(tmp); |
f877d09e | 1844 | tcg_temp_free(zero); |
4dd85b6b | 1845 | } |
b8132eff MF |
1846 | break; |
1847 | ||
1848 | case 14: /*RUR*/ | |
772177c1 | 1849 | gen_window_check1(dc, RRR_R); |
b8132eff MF |
1850 | { |
1851 | int st = (RRR_S << 4) + RRR_T; | |
fe0bd475 | 1852 | if (uregnames[st].name) { |
b8132eff MF |
1853 | tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]); |
1854 | } else { | |
1855 | qemu_log("RUR %d not implemented, ", st); | |
91a5bb76 | 1856 | TBD(); |
b8132eff MF |
1857 | } |
1858 | } | |
1859 | break; | |
1860 | ||
1861 | case 15: /*WUR*/ | |
772177c1 | 1862 | gen_window_check1(dc, RRR_T); |
fe0bd475 | 1863 | if (uregnames[RSR_SR].name) { |
dd519cbe MF |
1864 | gen_wur(RSR_SR, cpu_R[RRR_T]); |
1865 | } else { | |
1866 | qemu_log("WUR %d not implemented, ", RSR_SR); | |
1867 | TBD(); | |
b8132eff MF |
1868 | } |
1869 | break; | |
1870 | ||
1871 | } | |
dedc5eae MF |
1872 | break; |
1873 | ||
1874 | case 4: /*EXTUI*/ | |
1875 | case 5: | |
772177c1 | 1876 | gen_window_check2(dc, RRR_R, RRR_T); |
3580ecad | 1877 | { |
f9cb5045 | 1878 | int shiftimm = RRR_S | ((OP1 & 1) << 4); |
3580ecad MF |
1879 | int maskimm = (1 << (OP2 + 1)) - 1; |
1880 | ||
1881 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
f783cb22 AJ |
1882 | tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm); |
1883 | tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm); | |
3580ecad MF |
1884 | tcg_temp_free(tmp); |
1885 | } | |
dedc5eae MF |
1886 | break; |
1887 | ||
1888 | case 6: /*CUST0*/ | |
91a5bb76 | 1889 | RESERVED(); |
dedc5eae MF |
1890 | break; |
1891 | ||
1892 | case 7: /*CUST1*/ | |
91a5bb76 | 1893 | RESERVED(); |
dedc5eae MF |
1894 | break; |
1895 | ||
1896 | case 8: /*LSCXp*/ | |
9ed7ae12 MF |
1897 | switch (OP2) { |
1898 | case 0: /*LSXf*/ | |
1899 | case 1: /*LSXUf*/ | |
1900 | case 4: /*SSXf*/ | |
1901 | case 5: /*SSXUf*/ | |
1902 | HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); | |
1903 | gen_window_check2(dc, RRR_S, RRR_T); | |
ef04a846 | 1904 | gen_check_cpenable(dc, 0); |
9ed7ae12 MF |
1905 | { |
1906 | TCGv_i32 addr = tcg_temp_new_i32(); | |
1907 | tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]); | |
1908 | gen_load_store_alignment(dc, 2, addr, false); | |
1909 | if (OP2 & 0x4) { | |
1910 | tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring); | |
1911 | } else { | |
1912 | tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring); | |
1913 | } | |
1914 | if (OP2 & 0x1) { | |
1915 | tcg_gen_mov_i32(cpu_R[RRR_S], addr); | |
1916 | } | |
1917 | tcg_temp_free(addr); | |
1918 | } | |
1919 | break; | |
1920 | ||
1921 | default: /*reserved*/ | |
1922 | RESERVED(); | |
1923 | break; | |
1924 | } | |
dedc5eae MF |
1925 | break; |
1926 | ||
1927 | case 9: /*LSC4*/ | |
772177c1 | 1928 | gen_window_check2(dc, RRR_S, RRR_T); |
553e44f9 MF |
1929 | switch (OP2) { |
1930 | case 0: /*L32E*/ | |
1931 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
1932 | gen_check_privilege(dc); | |
1933 | { | |
1934 | TCGv_i32 addr = tcg_temp_new_i32(); | |
1935 | tcg_gen_addi_i32(addr, cpu_R[RRR_S], | |
1936 | (0xffffffc0 | (RRR_R << 2))); | |
1937 | tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring); | |
1938 | tcg_temp_free(addr); | |
1939 | } | |
1940 | break; | |
1941 | ||
1942 | case 4: /*S32E*/ | |
1943 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
1944 | gen_check_privilege(dc); | |
1945 | { | |
1946 | TCGv_i32 addr = tcg_temp_new_i32(); | |
1947 | tcg_gen_addi_i32(addr, cpu_R[RRR_S], | |
1948 | (0xffffffc0 | (RRR_R << 2))); | |
1949 | tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring); | |
1950 | tcg_temp_free(addr); | |
1951 | } | |
1952 | break; | |
1953 | ||
1954 | default: | |
1955 | RESERVED(); | |
1956 | break; | |
1957 | } | |
dedc5eae MF |
1958 | break; |
1959 | ||
1960 | case 10: /*FP0*/ | |
1961 | HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); | |
0b6df838 MF |
1962 | switch (OP2) { |
1963 | case 0: /*ADD.Sf*/ | |
ef04a846 | 1964 | gen_check_cpenable(dc, 0); |
0b6df838 MF |
1965 | gen_helper_add_s(cpu_FR[RRR_R], cpu_env, |
1966 | cpu_FR[RRR_S], cpu_FR[RRR_T]); | |
1967 | break; | |
1968 | ||
1969 | case 1: /*SUB.Sf*/ | |
ef04a846 | 1970 | gen_check_cpenable(dc, 0); |
0b6df838 MF |
1971 | gen_helper_sub_s(cpu_FR[RRR_R], cpu_env, |
1972 | cpu_FR[RRR_S], cpu_FR[RRR_T]); | |
1973 | break; | |
1974 | ||
1975 | case 2: /*MUL.Sf*/ | |
ef04a846 | 1976 | gen_check_cpenable(dc, 0); |
0b6df838 MF |
1977 | gen_helper_mul_s(cpu_FR[RRR_R], cpu_env, |
1978 | cpu_FR[RRR_S], cpu_FR[RRR_T]); | |
1979 | break; | |
1980 | ||
1981 | case 4: /*MADD.Sf*/ | |
ef04a846 | 1982 | gen_check_cpenable(dc, 0); |
0b6df838 MF |
1983 | gen_helper_madd_s(cpu_FR[RRR_R], cpu_env, |
1984 | cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]); | |
1985 | break; | |
1986 | ||
1987 | case 5: /*MSUB.Sf*/ | |
ef04a846 | 1988 | gen_check_cpenable(dc, 0); |
0b6df838 MF |
1989 | gen_helper_msub_s(cpu_FR[RRR_R], cpu_env, |
1990 | cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]); | |
1991 | break; | |
1992 | ||
b7ee8c6a MF |
1993 | case 8: /*ROUND.Sf*/ |
1994 | case 9: /*TRUNC.Sf*/ | |
1995 | case 10: /*FLOOR.Sf*/ | |
1996 | case 11: /*CEIL.Sf*/ | |
1997 | case 14: /*UTRUNC.Sf*/ | |
1998 | gen_window_check1(dc, RRR_R); | |
ef04a846 | 1999 | gen_check_cpenable(dc, 0); |
b7ee8c6a MF |
2000 | { |
2001 | static const unsigned rounding_mode_const[] = { | |
2002 | float_round_nearest_even, | |
2003 | float_round_to_zero, | |
2004 | float_round_down, | |
2005 | float_round_up, | |
2006 | [6] = float_round_to_zero, | |
2007 | }; | |
2008 | TCGv_i32 rounding_mode = tcg_const_i32( | |
2009 | rounding_mode_const[OP2 & 7]); | |
2010 | TCGv_i32 scale = tcg_const_i32(RRR_T); | |
2011 | ||
2012 | if (OP2 == 14) { | |
2013 | gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S], | |
2014 | rounding_mode, scale); | |
2015 | } else { | |
2016 | gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S], | |
2017 | rounding_mode, scale); | |
2018 | } | |
2019 | ||
2020 | tcg_temp_free(rounding_mode); | |
2021 | tcg_temp_free(scale); | |
2022 | } | |
2023 | break; | |
2024 | ||
2025 | case 12: /*FLOAT.Sf*/ | |
2026 | case 13: /*UFLOAT.Sf*/ | |
2027 | gen_window_check1(dc, RRR_S); | |
ef04a846 | 2028 | gen_check_cpenable(dc, 0); |
b7ee8c6a MF |
2029 | { |
2030 | TCGv_i32 scale = tcg_const_i32(-RRR_T); | |
2031 | ||
2032 | if (OP2 == 13) { | |
2033 | gen_helper_uitof(cpu_FR[RRR_R], cpu_env, | |
2034 | cpu_R[RRR_S], scale); | |
2035 | } else { | |
2036 | gen_helper_itof(cpu_FR[RRR_R], cpu_env, | |
2037 | cpu_R[RRR_S], scale); | |
2038 | } | |
2039 | tcg_temp_free(scale); | |
2040 | } | |
2041 | break; | |
2042 | ||
0b6df838 MF |
2043 | case 15: /*FP1OP*/ |
2044 | switch (RRR_T) { | |
2045 | case 0: /*MOV.Sf*/ | |
ef04a846 | 2046 | gen_check_cpenable(dc, 0); |
0b6df838 MF |
2047 | tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]); |
2048 | break; | |
2049 | ||
2050 | case 1: /*ABS.Sf*/ | |
ef04a846 | 2051 | gen_check_cpenable(dc, 0); |
0b6df838 MF |
2052 | gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]); |
2053 | break; | |
2054 | ||
2055 | case 4: /*RFRf*/ | |
2056 | gen_window_check1(dc, RRR_R); | |
ef04a846 | 2057 | gen_check_cpenable(dc, 0); |
0b6df838 MF |
2058 | tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]); |
2059 | break; | |
2060 | ||
2061 | case 5: /*WFRf*/ | |
2062 | gen_window_check1(dc, RRR_S); | |
ef04a846 | 2063 | gen_check_cpenable(dc, 0); |
0b6df838 MF |
2064 | tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]); |
2065 | break; | |
2066 | ||
2067 | case 6: /*NEG.Sf*/ | |
ef04a846 | 2068 | gen_check_cpenable(dc, 0); |
0b6df838 MF |
2069 | gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]); |
2070 | break; | |
2071 | ||
2072 | default: /*reserved*/ | |
2073 | RESERVED(); | |
2074 | break; | |
2075 | } | |
2076 | break; | |
2077 | ||
2078 | default: /*reserved*/ | |
2079 | RESERVED(); | |
2080 | break; | |
2081 | } | |
dedc5eae MF |
2082 | break; |
2083 | ||
2084 | case 11: /*FP1*/ | |
2085 | HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); | |
4e273869 MF |
2086 | |
2087 | #define gen_compare(rel, br, a, b) \ | |
2088 | do { \ | |
2089 | TCGv_i32 bit = tcg_const_i32(1 << br); \ | |
2090 | \ | |
ef04a846 | 2091 | gen_check_cpenable(dc, 0); \ |
4e273869 MF |
2092 | gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \ |
2093 | tcg_temp_free(bit); \ | |
2094 | } while (0) | |
2095 | ||
2096 | switch (OP2) { | |
2097 | case 1: /*UN.Sf*/ | |
2098 | gen_compare(un_s, RRR_R, RRR_S, RRR_T); | |
2099 | break; | |
2100 | ||
2101 | case 2: /*OEQ.Sf*/ | |
2102 | gen_compare(oeq_s, RRR_R, RRR_S, RRR_T); | |
2103 | break; | |
2104 | ||
2105 | case 3: /*UEQ.Sf*/ | |
2106 | gen_compare(ueq_s, RRR_R, RRR_S, RRR_T); | |
2107 | break; | |
2108 | ||
2109 | case 4: /*OLT.Sf*/ | |
2110 | gen_compare(olt_s, RRR_R, RRR_S, RRR_T); | |
2111 | break; | |
2112 | ||
2113 | case 5: /*ULT.Sf*/ | |
2114 | gen_compare(ult_s, RRR_R, RRR_S, RRR_T); | |
2115 | break; | |
2116 | ||
2117 | case 6: /*OLE.Sf*/ | |
2118 | gen_compare(ole_s, RRR_R, RRR_S, RRR_T); | |
2119 | break; | |
2120 | ||
2121 | case 7: /*ULE.Sf*/ | |
2122 | gen_compare(ule_s, RRR_R, RRR_S, RRR_T); | |
2123 | break; | |
2124 | ||
2125 | #undef gen_compare | |
2126 | ||
2127 | case 8: /*MOVEQZ.Sf*/ | |
2128 | case 9: /*MOVNEZ.Sf*/ | |
2129 | case 10: /*MOVLTZ.Sf*/ | |
2130 | case 11: /*MOVGEZ.Sf*/ | |
2131 | gen_window_check1(dc, RRR_T); | |
ef04a846 | 2132 | gen_check_cpenable(dc, 0); |
4e273869 MF |
2133 | { |
2134 | static const TCGCond cond[] = { | |
4e273869 | 2135 | TCG_COND_EQ, |
f877d09e MF |
2136 | TCG_COND_NE, |
2137 | TCG_COND_LT, | |
4e273869 | 2138 | TCG_COND_GE, |
4e273869 | 2139 | }; |
f877d09e MF |
2140 | TCGv_i32 zero = tcg_const_i32(0); |
2141 | ||
2142 | tcg_gen_movcond_i32(cond[OP2 - 8], cpu_FR[RRR_R], | |
2143 | cpu_R[RRR_T], zero, cpu_FR[RRR_S], cpu_FR[RRR_R]); | |
2144 | tcg_temp_free(zero); | |
4e273869 MF |
2145 | } |
2146 | break; | |
2147 | ||
2148 | case 12: /*MOVF.Sf*/ | |
2149 | case 13: /*MOVT.Sf*/ | |
2150 | HAS_OPTION(XTENSA_OPTION_BOOLEAN); | |
ef04a846 | 2151 | gen_check_cpenable(dc, 0); |
4e273869 | 2152 | { |
f877d09e | 2153 | TCGv_i32 zero = tcg_const_i32(0); |
4e273869 MF |
2154 | TCGv_i32 tmp = tcg_temp_new_i32(); |
2155 | ||
2156 | tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T); | |
f877d09e MF |
2157 | tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ, |
2158 | cpu_FR[RRR_R], tmp, zero, | |
2159 | cpu_FR[RRR_S], cpu_FR[RRR_R]); | |
2160 | ||
4e273869 | 2161 | tcg_temp_free(tmp); |
f877d09e | 2162 | tcg_temp_free(zero); |
4e273869 MF |
2163 | } |
2164 | break; | |
2165 | ||
2166 | default: /*reserved*/ | |
2167 | RESERVED(); | |
2168 | break; | |
2169 | } | |
dedc5eae MF |
2170 | break; |
2171 | ||
2172 | default: /*reserved*/ | |
91a5bb76 | 2173 | RESERVED(); |
dedc5eae MF |
2174 | break; |
2175 | } | |
2176 | break; | |
2177 | ||
2178 | case 1: /*L32R*/ | |
772177c1 | 2179 | gen_window_check1(dc, RRR_T); |
dedc5eae MF |
2180 | { |
2181 | TCGv_i32 tmp = tcg_const_i32( | |
6ad6dbf7 MF |
2182 | ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ? |
2183 | 0 : ((dc->pc + 3) & ~3)) + | |
2184 | (0xfffc0000 | (RI16_IMM16 << 2))); | |
dedc5eae | 2185 | |
6ad6dbf7 MF |
2186 | if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { |
2187 | tcg_gen_add_i32(tmp, tmp, dc->litbase); | |
2188 | } | |
f0a548b9 | 2189 | tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring); |
dedc5eae MF |
2190 | tcg_temp_free(tmp); |
2191 | } | |
2192 | break; | |
2193 | ||
2194 | case 2: /*LSAI*/ | |
809377aa MF |
2195 | #define gen_load_store(type, shift) do { \ |
2196 | TCGv_i32 addr = tcg_temp_new_i32(); \ | |
772177c1 | 2197 | gen_window_check2(dc, RRI8_S, RRI8_T); \ |
809377aa | 2198 | tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \ |
5b4e481b MF |
2199 | if (shift) { \ |
2200 | gen_load_store_alignment(dc, shift, addr, false); \ | |
2201 | } \ | |
f0a548b9 | 2202 | tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \ |
809377aa MF |
2203 | tcg_temp_free(addr); \ |
2204 | } while (0) | |
2205 | ||
2206 | switch (RRI8_R) { | |
2207 | case 0: /*L8UI*/ | |
2208 | gen_load_store(ld8u, 0); | |
2209 | break; | |
2210 | ||
2211 | case 1: /*L16UI*/ | |
2212 | gen_load_store(ld16u, 1); | |
2213 | break; | |
2214 | ||
2215 | case 2: /*L32I*/ | |
2216 | gen_load_store(ld32u, 2); | |
2217 | break; | |
2218 | ||
2219 | case 4: /*S8I*/ | |
2220 | gen_load_store(st8, 0); | |
2221 | break; | |
2222 | ||
2223 | case 5: /*S16I*/ | |
2224 | gen_load_store(st16, 1); | |
2225 | break; | |
2226 | ||
2227 | case 6: /*S32I*/ | |
2228 | gen_load_store(st32, 2); | |
2229 | break; | |
2230 | ||
2231 | case 7: /*CACHEc*/ | |
8ffc2d0d MF |
2232 | if (RRI8_T < 8) { |
2233 | HAS_OPTION(XTENSA_OPTION_DCACHE); | |
2234 | } | |
2235 | ||
2236 | switch (RRI8_T) { | |
2237 | case 0: /*DPFRc*/ | |
2238 | break; | |
2239 | ||
2240 | case 1: /*DPFWc*/ | |
2241 | break; | |
2242 | ||
2243 | case 2: /*DPFROc*/ | |
2244 | break; | |
2245 | ||
2246 | case 3: /*DPFWOc*/ | |
2247 | break; | |
2248 | ||
2249 | case 4: /*DHWBc*/ | |
2250 | break; | |
2251 | ||
2252 | case 5: /*DHWBIc*/ | |
2253 | break; | |
2254 | ||
2255 | case 6: /*DHIc*/ | |
2256 | break; | |
2257 | ||
2258 | case 7: /*DIIc*/ | |
2259 | break; | |
2260 | ||
2261 | case 8: /*DCEc*/ | |
2262 | switch (OP1) { | |
2263 | case 0: /*DPFLl*/ | |
2264 | HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); | |
2265 | break; | |
2266 | ||
2267 | case 2: /*DHUl*/ | |
2268 | HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); | |
2269 | break; | |
2270 | ||
2271 | case 3: /*DIUl*/ | |
2272 | HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); | |
2273 | break; | |
2274 | ||
2275 | case 4: /*DIWBc*/ | |
2276 | HAS_OPTION(XTENSA_OPTION_DCACHE); | |
2277 | break; | |
2278 | ||
2279 | case 5: /*DIWBIc*/ | |
2280 | HAS_OPTION(XTENSA_OPTION_DCACHE); | |
2281 | break; | |
2282 | ||
2283 | default: /*reserved*/ | |
2284 | RESERVED(); | |
2285 | break; | |
2286 | ||
2287 | } | |
2288 | break; | |
2289 | ||
2290 | case 12: /*IPFc*/ | |
2291 | HAS_OPTION(XTENSA_OPTION_ICACHE); | |
2292 | break; | |
2293 | ||
2294 | case 13: /*ICEc*/ | |
2295 | switch (OP1) { | |
2296 | case 0: /*IPFLl*/ | |
2297 | HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); | |
2298 | break; | |
2299 | ||
2300 | case 2: /*IHUl*/ | |
2301 | HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); | |
2302 | break; | |
2303 | ||
2304 | case 3: /*IIUl*/ | |
2305 | HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); | |
2306 | break; | |
2307 | ||
2308 | default: /*reserved*/ | |
2309 | RESERVED(); | |
2310 | break; | |
2311 | } | |
2312 | break; | |
2313 | ||
2314 | case 14: /*IHIc*/ | |
2315 | HAS_OPTION(XTENSA_OPTION_ICACHE); | |
2316 | break; | |
2317 | ||
2318 | case 15: /*IIIc*/ | |
2319 | HAS_OPTION(XTENSA_OPTION_ICACHE); | |
2320 | break; | |
2321 | ||
2322 | default: /*reserved*/ | |
2323 | RESERVED(); | |
2324 | break; | |
2325 | } | |
809377aa MF |
2326 | break; |
2327 | ||
2328 | case 9: /*L16SI*/ | |
2329 | gen_load_store(ld16s, 1); | |
2330 | break; | |
5b4e481b | 2331 | #undef gen_load_store |
809377aa MF |
2332 | |
2333 | case 10: /*MOVI*/ | |
772177c1 | 2334 | gen_window_check1(dc, RRI8_T); |
809377aa MF |
2335 | tcg_gen_movi_i32(cpu_R[RRI8_T], |
2336 | RRI8_IMM8 | (RRI8_S << 8) | | |
2337 | ((RRI8_S & 0x8) ? 0xfffff000 : 0)); | |
2338 | break; | |
2339 | ||
5b4e481b MF |
2340 | #define gen_load_store_no_hw_align(type) do { \ |
2341 | TCGv_i32 addr = tcg_temp_local_new_i32(); \ | |
772177c1 | 2342 | gen_window_check2(dc, RRI8_S, RRI8_T); \ |
5b4e481b MF |
2343 | tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \ |
2344 | gen_load_store_alignment(dc, 2, addr, true); \ | |
2345 | tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \ | |
2346 | tcg_temp_free(addr); \ | |
2347 | } while (0) | |
2348 | ||
809377aa MF |
2349 | case 11: /*L32AIy*/ |
2350 | HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO); | |
5b4e481b | 2351 | gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/ |
809377aa MF |
2352 | break; |
2353 | ||
2354 | case 12: /*ADDI*/ | |
772177c1 | 2355 | gen_window_check2(dc, RRI8_S, RRI8_T); |
809377aa MF |
2356 | tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE); |
2357 | break; | |
2358 | ||
2359 | case 13: /*ADDMI*/ | |
772177c1 | 2360 | gen_window_check2(dc, RRI8_S, RRI8_T); |
809377aa MF |
2361 | tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE << 8); |
2362 | break; | |
2363 | ||
2364 | case 14: /*S32C1Iy*/ | |
7f65f4b0 | 2365 | HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE); |
772177c1 | 2366 | gen_window_check2(dc, RRI8_S, RRI8_T); |
809377aa MF |
2367 | { |
2368 | int label = gen_new_label(); | |
2369 | TCGv_i32 tmp = tcg_temp_local_new_i32(); | |
2370 | TCGv_i32 addr = tcg_temp_local_new_i32(); | |
fcc803d1 | 2371 | TCGv_i32 tpc; |
809377aa MF |
2372 | |
2373 | tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]); | |
2374 | tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); | |
5b4e481b | 2375 | gen_load_store_alignment(dc, 2, addr, true); |
fcc803d1 MF |
2376 | |
2377 | gen_advance_ccount(dc); | |
2378 | tpc = tcg_const_i32(dc->pc); | |
2379 | gen_helper_check_atomctl(cpu_env, tpc, addr); | |
f0a548b9 | 2380 | tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring); |
809377aa MF |
2381 | tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T], |
2382 | cpu_SR[SCOMPARE1], label); | |
2383 | ||
f0a548b9 | 2384 | tcg_gen_qemu_st32(tmp, addr, dc->cring); |
809377aa MF |
2385 | |
2386 | gen_set_label(label); | |
fcc803d1 | 2387 | tcg_temp_free(tpc); |
809377aa MF |
2388 | tcg_temp_free(addr); |
2389 | tcg_temp_free(tmp); | |
2390 | } | |
2391 | break; | |
2392 | ||
2393 | case 15: /*S32RIy*/ | |
2394 | HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO); | |
5b4e481b | 2395 | gen_load_store_no_hw_align(st32); /*TODO release?*/ |
809377aa | 2396 | break; |
5b4e481b | 2397 | #undef gen_load_store_no_hw_align |
809377aa MF |
2398 | |
2399 | default: /*reserved*/ | |
91a5bb76 | 2400 | RESERVED(); |
809377aa MF |
2401 | break; |
2402 | } | |
dedc5eae MF |
2403 | break; |
2404 | ||
2405 | case 3: /*LSCIp*/ | |
9ed7ae12 MF |
2406 | switch (RRI8_R) { |
2407 | case 0: /*LSIf*/ | |
2408 | case 4: /*SSIf*/ | |
2409 | case 8: /*LSIUf*/ | |
2410 | case 12: /*SSIUf*/ | |
2411 | HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); | |
2412 | gen_window_check1(dc, RRI8_S); | |
ef04a846 | 2413 | gen_check_cpenable(dc, 0); |
9ed7ae12 MF |
2414 | { |
2415 | TCGv_i32 addr = tcg_temp_new_i32(); | |
2416 | tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); | |
2417 | gen_load_store_alignment(dc, 2, addr, false); | |
2418 | if (RRI8_R & 0x4) { | |
2419 | tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring); | |
2420 | } else { | |
2421 | tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring); | |
2422 | } | |
2423 | if (RRI8_R & 0x8) { | |
2424 | tcg_gen_mov_i32(cpu_R[RRI8_S], addr); | |
2425 | } | |
2426 | tcg_temp_free(addr); | |
2427 | } | |
2428 | break; | |
2429 | ||
2430 | default: /*reserved*/ | |
2431 | RESERVED(); | |
2432 | break; | |
2433 | } | |
dedc5eae MF |
2434 | break; |
2435 | ||
2436 | case 4: /*MAC16d*/ | |
2437 | HAS_OPTION(XTENSA_OPTION_MAC16); | |
6825b6c3 MF |
2438 | { |
2439 | enum { | |
2440 | MAC16_UMUL = 0x0, | |
2441 | MAC16_MUL = 0x4, | |
2442 | MAC16_MULA = 0x8, | |
2443 | MAC16_MULS = 0xc, | |
2444 | MAC16_NONE = 0xf, | |
2445 | } op = OP1 & 0xc; | |
2446 | bool is_m1_sr = (OP2 & 0x3) == 2; | |
2447 | bool is_m2_sr = (OP2 & 0xc) == 0; | |
2448 | uint32_t ld_offset = 0; | |
2449 | ||
2450 | if (OP2 > 9) { | |
2451 | RESERVED(); | |
2452 | } | |
2453 | ||
2454 | switch (OP2 & 2) { | |
2455 | case 0: /*MACI?/MACC?*/ | |
2456 | is_m1_sr = true; | |
2457 | ld_offset = (OP2 & 1) ? -4 : 4; | |
2458 | ||
2459 | if (OP2 >= 8) { /*MACI/MACC*/ | |
2460 | if (OP1 == 0) { /*LDINC/LDDEC*/ | |
2461 | op = MAC16_NONE; | |
2462 | } else { | |
2463 | RESERVED(); | |
2464 | } | |
2465 | } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/ | |
2466 | RESERVED(); | |
2467 | } | |
2468 | break; | |
2469 | ||
2470 | case 2: /*MACD?/MACA?*/ | |
2471 | if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/ | |
2472 | RESERVED(); | |
2473 | } | |
2474 | break; | |
2475 | } | |
2476 | ||
2477 | if (op != MAC16_NONE) { | |
2478 | if (!is_m1_sr) { | |
2479 | gen_window_check1(dc, RRR_S); | |
2480 | } | |
2481 | if (!is_m2_sr) { | |
2482 | gen_window_check1(dc, RRR_T); | |
2483 | } | |
2484 | } | |
2485 | ||
2486 | { | |
2487 | TCGv_i32 vaddr = tcg_temp_new_i32(); | |
2488 | TCGv_i32 mem32 = tcg_temp_new_i32(); | |
2489 | ||
2490 | if (ld_offset) { | |
2491 | gen_window_check1(dc, RRR_S); | |
2492 | tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset); | |
2493 | gen_load_store_alignment(dc, 2, vaddr, false); | |
2494 | tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring); | |
2495 | } | |
2496 | if (op != MAC16_NONE) { | |
2497 | TCGv_i32 m1 = gen_mac16_m( | |
2498 | is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S], | |
2499 | OP1 & 1, op == MAC16_UMUL); | |
2500 | TCGv_i32 m2 = gen_mac16_m( | |
2501 | is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T], | |
2502 | OP1 & 2, op == MAC16_UMUL); | |
2503 | ||
2504 | if (op == MAC16_MUL || op == MAC16_UMUL) { | |
2505 | tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2); | |
2506 | if (op == MAC16_UMUL) { | |
2507 | tcg_gen_movi_i32(cpu_SR[ACCHI], 0); | |
2508 | } else { | |
2509 | tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31); | |
2510 | } | |
2511 | } else { | |
d2123a07 RH |
2512 | TCGv_i32 lo = tcg_temp_new_i32(); |
2513 | TCGv_i32 hi = tcg_temp_new_i32(); | |
2514 | ||
2515 | tcg_gen_mul_i32(lo, m1, m2); | |
2516 | tcg_gen_sari_i32(hi, lo, 31); | |
6825b6c3 | 2517 | if (op == MAC16_MULA) { |
d2123a07 RH |
2518 | tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], |
2519 | cpu_SR[ACCLO], cpu_SR[ACCHI], | |
2520 | lo, hi); | |
6825b6c3 | 2521 | } else { |
d2123a07 RH |
2522 | tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], |
2523 | cpu_SR[ACCLO], cpu_SR[ACCHI], | |
2524 | lo, hi); | |
6825b6c3 | 2525 | } |
6825b6c3 MF |
2526 | tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); |
2527 | ||
d2123a07 RH |
2528 | tcg_temp_free_i32(lo); |
2529 | tcg_temp_free_i32(hi); | |
6825b6c3 MF |
2530 | } |
2531 | tcg_temp_free(m1); | |
2532 | tcg_temp_free(m2); | |
2533 | } | |
2534 | if (ld_offset) { | |
2535 | tcg_gen_mov_i32(cpu_R[RRR_S], vaddr); | |
2536 | tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32); | |
2537 | } | |
2538 | tcg_temp_free(vaddr); | |
2539 | tcg_temp_free(mem32); | |
2540 | } | |
2541 | } | |
dedc5eae MF |
2542 | break; |
2543 | ||
2544 | case 5: /*CALLN*/ | |
2545 | switch (CALL_N) { | |
2546 | case 0: /*CALL0*/ | |
2547 | tcg_gen_movi_i32(cpu_R[0], dc->next_pc); | |
2548 | gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0); | |
2549 | break; | |
2550 | ||
2551 | case 1: /*CALL4w*/ | |
2552 | case 2: /*CALL8w*/ | |
2553 | case 3: /*CALL12w*/ | |
2554 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
772177c1 | 2555 | gen_window_check1(dc, CALL_N << 2); |
553e44f9 MF |
2556 | gen_callwi(dc, CALL_N, |
2557 | (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0); | |
dedc5eae MF |
2558 | break; |
2559 | } | |
2560 | break; | |
2561 | ||
2562 | case 6: /*SI*/ | |
2563 | switch (CALL_N) { | |
2564 | case 0: /*J*/ | |
2565 | gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0); | |
2566 | break; | |
2567 | ||
bd57fb91 | 2568 | case 1: /*BZ*/ |
772177c1 | 2569 | gen_window_check1(dc, BRI12_S); |
bd57fb91 MF |
2570 | { |
2571 | static const TCGCond cond[] = { | |
2572 | TCG_COND_EQ, /*BEQZ*/ | |
2573 | TCG_COND_NE, /*BNEZ*/ | |
2574 | TCG_COND_LT, /*BLTZ*/ | |
2575 | TCG_COND_GE, /*BGEZ*/ | |
2576 | }; | |
2577 | ||
2578 | gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0, | |
2579 | 4 + BRI12_IMM12_SE); | |
2580 | } | |
2581 | break; | |
2582 | ||
2583 | case 2: /*BI0*/ | |
772177c1 | 2584 | gen_window_check1(dc, BRI8_S); |
bd57fb91 MF |
2585 | { |
2586 | static const TCGCond cond[] = { | |
2587 | TCG_COND_EQ, /*BEQI*/ | |
2588 | TCG_COND_NE, /*BNEI*/ | |
2589 | TCG_COND_LT, /*BLTI*/ | |
2590 | TCG_COND_GE, /*BGEI*/ | |
2591 | }; | |
2592 | ||
2593 | gen_brcondi(dc, cond[BRI8_M & 3], | |
2594 | cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE); | |
2595 | } | |
2596 | break; | |
2597 | ||
2598 | case 3: /*BI1*/ | |
2599 | switch (BRI8_M) { | |
2600 | case 0: /*ENTRYw*/ | |
2601 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); | |
553e44f9 MF |
2602 | { |
2603 | TCGv_i32 pc = tcg_const_i32(dc->pc); | |
2604 | TCGv_i32 s = tcg_const_i32(BRI12_S); | |
2605 | TCGv_i32 imm = tcg_const_i32(BRI12_IMM12); | |
b994e91b | 2606 | gen_advance_ccount(dc); |
f492b82d | 2607 | gen_helper_entry(cpu_env, pc, s, imm); |
553e44f9 MF |
2608 | tcg_temp_free(imm); |
2609 | tcg_temp_free(s); | |
2610 | tcg_temp_free(pc); | |
772177c1 | 2611 | reset_used_window(dc); |
553e44f9 | 2612 | } |
bd57fb91 MF |
2613 | break; |
2614 | ||
2615 | case 1: /*B1*/ | |
2616 | switch (BRI8_R) { | |
2617 | case 0: /*BFp*/ | |
bd57fb91 MF |
2618 | case 1: /*BTp*/ |
2619 | HAS_OPTION(XTENSA_OPTION_BOOLEAN); | |
4dd85b6b MF |
2620 | { |
2621 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
2622 | tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S); | |
2623 | gen_brcondi(dc, | |
2624 | BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ, | |
2625 | tmp, 0, 4 + RRI8_IMM8_SE); | |
2626 | tcg_temp_free(tmp); | |
2627 | } | |
bd57fb91 MF |
2628 | break; |
2629 | ||
2630 | case 8: /*LOOP*/ | |
bd57fb91 | 2631 | case 9: /*LOOPNEZ*/ |
bd57fb91 | 2632 | case 10: /*LOOPGTZ*/ |
797d780b | 2633 | HAS_OPTION(XTENSA_OPTION_LOOP); |
772177c1 | 2634 | gen_window_check1(dc, RRI8_S); |
797d780b MF |
2635 | { |
2636 | uint32_t lend = dc->pc + RRI8_IMM8 + 4; | |
2637 | TCGv_i32 tmp = tcg_const_i32(lend); | |
2638 | ||
2639 | tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1); | |
2640 | tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc); | |
f492b82d | 2641 | gen_helper_wsr_lend(cpu_env, tmp); |
797d780b MF |
2642 | tcg_temp_free(tmp); |
2643 | ||
2644 | if (BRI8_R > 8) { | |
2645 | int label = gen_new_label(); | |
2646 | tcg_gen_brcondi_i32( | |
2647 | BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT, | |
2648 | cpu_R[RRI8_S], 0, label); | |
2649 | gen_jumpi(dc, lend, 1); | |
2650 | gen_set_label(label); | |
2651 | } | |
2652 | ||
2653 | gen_jumpi(dc, dc->next_pc, 0); | |
2654 | } | |
bd57fb91 MF |
2655 | break; |
2656 | ||
2657 | default: /*reserved*/ | |
91a5bb76 | 2658 | RESERVED(); |
bd57fb91 MF |
2659 | break; |
2660 | ||
2661 | } | |
2662 | break; | |
2663 | ||
2664 | case 2: /*BLTUI*/ | |
2665 | case 3: /*BGEUI*/ | |
772177c1 | 2666 | gen_window_check1(dc, BRI8_S); |
bd57fb91 MF |
2667 | gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU, |
2668 | cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE); | |
2669 | break; | |
2670 | } | |
2671 | break; | |
2672 | ||
dedc5eae MF |
2673 | } |
2674 | break; | |
2675 | ||
2676 | case 7: /*B*/ | |
bd57fb91 MF |
2677 | { |
2678 | TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ; | |
2679 | ||
2680 | switch (RRI8_R & 7) { | |
2681 | case 0: /*BNONE*/ /*BANY*/ | |
772177c1 | 2682 | gen_window_check2(dc, RRI8_S, RRI8_T); |
bd57fb91 MF |
2683 | { |
2684 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
2685 | tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]); | |
2686 | gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); | |
2687 | tcg_temp_free(tmp); | |
2688 | } | |
2689 | break; | |
2690 | ||
2691 | case 1: /*BEQ*/ /*BNE*/ | |
2692 | case 2: /*BLT*/ /*BGE*/ | |
2693 | case 3: /*BLTU*/ /*BGEU*/ | |
772177c1 | 2694 | gen_window_check2(dc, RRI8_S, RRI8_T); |
bd57fb91 MF |
2695 | { |
2696 | static const TCGCond cond[] = { | |
2697 | [1] = TCG_COND_EQ, | |
2698 | [2] = TCG_COND_LT, | |
2699 | [3] = TCG_COND_LTU, | |
2700 | [9] = TCG_COND_NE, | |
2701 | [10] = TCG_COND_GE, | |
2702 | [11] = TCG_COND_GEU, | |
2703 | }; | |
2704 | gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T], | |
2705 | 4 + RRI8_IMM8_SE); | |
2706 | } | |
2707 | break; | |
2708 | ||
2709 | case 4: /*BALL*/ /*BNALL*/ | |
772177c1 | 2710 | gen_window_check2(dc, RRI8_S, RRI8_T); |
bd57fb91 MF |
2711 | { |
2712 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
2713 | tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]); | |
2714 | gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T], | |
2715 | 4 + RRI8_IMM8_SE); | |
2716 | tcg_temp_free(tmp); | |
2717 | } | |
2718 | break; | |
2719 | ||
2720 | case 5: /*BBC*/ /*BBS*/ | |
772177c1 | 2721 | gen_window_check2(dc, RRI8_S, RRI8_T); |
bd57fb91 | 2722 | { |
7ff7563f MF |
2723 | #ifdef TARGET_WORDS_BIGENDIAN |
2724 | TCGv_i32 bit = tcg_const_i32(0x80000000); | |
2725 | #else | |
2726 | TCGv_i32 bit = tcg_const_i32(0x00000001); | |
2727 | #endif | |
bd57fb91 MF |
2728 | TCGv_i32 tmp = tcg_temp_new_i32(); |
2729 | tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f); | |
7ff7563f MF |
2730 | #ifdef TARGET_WORDS_BIGENDIAN |
2731 | tcg_gen_shr_i32(bit, bit, tmp); | |
2732 | #else | |
bd57fb91 | 2733 | tcg_gen_shl_i32(bit, bit, tmp); |
7ff7563f | 2734 | #endif |
bd57fb91 MF |
2735 | tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit); |
2736 | gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); | |
2737 | tcg_temp_free(tmp); | |
2738 | tcg_temp_free(bit); | |
2739 | } | |
2740 | break; | |
2741 | ||
2742 | case 6: /*BBCI*/ /*BBSI*/ | |
2743 | case 7: | |
772177c1 | 2744 | gen_window_check1(dc, RRI8_S); |
bd57fb91 MF |
2745 | { |
2746 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
2747 | tcg_gen_andi_i32(tmp, cpu_R[RRI8_S], | |
7ff7563f MF |
2748 | #ifdef TARGET_WORDS_BIGENDIAN |
2749 | 0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T)); | |
2750 | #else | |
2751 | 0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T)); | |
2752 | #endif | |
bd57fb91 MF |
2753 | gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); |
2754 | tcg_temp_free(tmp); | |
2755 | } | |
2756 | break; | |
2757 | ||
2758 | } | |
2759 | } | |
dedc5eae MF |
2760 | break; |
2761 | ||
67882fd1 MF |
2762 | #define gen_narrow_load_store(type) do { \ |
2763 | TCGv_i32 addr = tcg_temp_new_i32(); \ | |
772177c1 | 2764 | gen_window_check2(dc, RRRN_S, RRRN_T); \ |
67882fd1 | 2765 | tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \ |
5b4e481b | 2766 | gen_load_store_alignment(dc, 2, addr, false); \ |
f0a548b9 | 2767 | tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \ |
67882fd1 MF |
2768 | tcg_temp_free(addr); \ |
2769 | } while (0) | |
2770 | ||
dedc5eae | 2771 | case 8: /*L32I.Nn*/ |
67882fd1 | 2772 | gen_narrow_load_store(ld32u); |
dedc5eae MF |
2773 | break; |
2774 | ||
2775 | case 9: /*S32I.Nn*/ | |
67882fd1 | 2776 | gen_narrow_load_store(st32); |
dedc5eae | 2777 | break; |
67882fd1 | 2778 | #undef gen_narrow_load_store |
dedc5eae MF |
2779 | |
2780 | case 10: /*ADD.Nn*/ | |
772177c1 | 2781 | gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T); |
67882fd1 | 2782 | tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]); |
dedc5eae MF |
2783 | break; |
2784 | ||
2785 | case 11: /*ADDI.Nn*/ | |
772177c1 | 2786 | gen_window_check2(dc, RRRN_R, RRRN_S); |
67882fd1 | 2787 | tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1); |
dedc5eae MF |
2788 | break; |
2789 | ||
2790 | case 12: /*ST2n*/ | |
772177c1 | 2791 | gen_window_check1(dc, RRRN_S); |
67882fd1 MF |
2792 | if (RRRN_T < 8) { /*MOVI.Nn*/ |
2793 | tcg_gen_movi_i32(cpu_R[RRRN_S], | |
2794 | RRRN_R | (RRRN_T << 4) | | |
2795 | ((RRRN_T & 6) == 6 ? 0xffffff80 : 0)); | |
2796 | } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/ | |
bd57fb91 MF |
2797 | TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ; |
2798 | ||
2799 | gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0, | |
2800 | 4 + (RRRN_R | ((RRRN_T & 3) << 4))); | |
67882fd1 | 2801 | } |
dedc5eae MF |
2802 | break; |
2803 | ||
2804 | case 13: /*ST3n*/ | |
67882fd1 MF |
2805 | switch (RRRN_R) { |
2806 | case 0: /*MOV.Nn*/ | |
772177c1 | 2807 | gen_window_check2(dc, RRRN_S, RRRN_T); |
67882fd1 MF |
2808 | tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]); |
2809 | break; | |
2810 | ||
2811 | case 15: /*S3*/ | |
2812 | switch (RRRN_T) { | |
2813 | case 0: /*RET.Nn*/ | |
2814 | gen_jump(dc, cpu_R[0]); | |
2815 | break; | |
2816 | ||
2817 | case 1: /*RETW.Nn*/ | |
91a5bb76 | 2818 | HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); |
553e44f9 MF |
2819 | { |
2820 | TCGv_i32 tmp = tcg_const_i32(dc->pc); | |
b994e91b | 2821 | gen_advance_ccount(dc); |
f492b82d | 2822 | gen_helper_retw(tmp, cpu_env, tmp); |
553e44f9 MF |
2823 | gen_jump(dc, tmp); |
2824 | tcg_temp_free(tmp); | |
2825 | } | |
67882fd1 MF |
2826 | break; |
2827 | ||
2828 | case 2: /*BREAK.Nn*/ | |
e61dc8f7 MF |
2829 | HAS_OPTION(XTENSA_OPTION_DEBUG); |
2830 | if (dc->debug) { | |
2831 | gen_debug_exception(dc, DEBUGCAUSE_BN); | |
2832 | } | |
67882fd1 MF |
2833 | break; |
2834 | ||
2835 | case 3: /*NOP.Nn*/ | |
2836 | break; | |
2837 | ||
2838 | case 6: /*ILL.Nn*/ | |
40643d7c | 2839 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
67882fd1 MF |
2840 | break; |
2841 | ||
2842 | default: /*reserved*/ | |
91a5bb76 | 2843 | RESERVED(); |
67882fd1 MF |
2844 | break; |
2845 | } | |
2846 | break; | |
2847 | ||
2848 | default: /*reserved*/ | |
91a5bb76 | 2849 | RESERVED(); |
67882fd1 MF |
2850 | break; |
2851 | } | |
dedc5eae MF |
2852 | break; |
2853 | ||
2854 | default: /*reserved*/ | |
91a5bb76 | 2855 | RESERVED(); |
dedc5eae MF |
2856 | break; |
2857 | } | |
2858 | ||
c26032b2 MF |
2859 | if (dc->is_jmp == DISAS_NEXT) { |
2860 | gen_check_loop_end(dc, 0); | |
2861 | } | |
dedc5eae | 2862 | dc->pc = dc->next_pc; |
797d780b | 2863 | |
dedc5eae MF |
2864 | return; |
2865 | ||
2866 | invalid_opcode: | |
2867 | qemu_log("INVALID(pc = %08x)\n", dc->pc); | |
6b814719 | 2868 | gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); |
dedc5eae MF |
2869 | #undef HAS_OPTION |
2870 | } | |
2871 | ||
97129ac8 | 2872 | static void check_breakpoint(CPUXtensaState *env, DisasContext *dc) |
dedc5eae MF |
2873 | { |
2874 | CPUBreakpoint *bp; | |
2875 | ||
2876 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { | |
2877 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
2878 | if (bp->pc == dc->pc) { | |
2879 | tcg_gen_movi_i32(cpu_pc, dc->pc); | |
b994e91b | 2880 | gen_exception(dc, EXCP_DEBUG); |
dedc5eae MF |
2881 | dc->is_jmp = DISAS_UPDATE; |
2882 | } | |
2883 | } | |
2884 | } | |
2885 | } | |
2886 | ||
97129ac8 | 2887 | static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc) |
e61dc8f7 MF |
2888 | { |
2889 | unsigned i; | |
2890 | ||
2891 | for (i = 0; i < dc->config->nibreak; ++i) { | |
2892 | if ((env->sregs[IBREAKENABLE] & (1 << i)) && | |
2893 | env->sregs[IBREAKA + i] == dc->pc) { | |
2894 | gen_debug_exception(dc, DEBUGCAUSE_IB); | |
2895 | break; | |
2896 | } | |
2897 | } | |
2898 | } | |
2899 | ||
ae06d498 | 2900 | static inline |
90b85b77 AF |
2901 | void gen_intermediate_code_internal(XtensaCPU *cpu, |
2902 | TranslationBlock *tb, bool search_pc) | |
dedc5eae | 2903 | { |
ed2803da | 2904 | CPUState *cs = CPU(cpu); |
90b85b77 | 2905 | CPUXtensaState *env = &cpu->env; |
dedc5eae MF |
2906 | DisasContext dc; |
2907 | int insn_count = 0; | |
2908 | int j, lj = -1; | |
92414b31 | 2909 | uint16_t *gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
dedc5eae MF |
2910 | int max_insns = tb->cflags & CF_COUNT_MASK; |
2911 | uint32_t pc_start = tb->pc; | |
2912 | uint32_t next_page_start = | |
2913 | (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; | |
2914 | ||
2915 | if (max_insns == 0) { | |
2916 | max_insns = CF_COUNT_MASK; | |
2917 | } | |
2918 | ||
2919 | dc.config = env->config; | |
ed2803da | 2920 | dc.singlestep_enabled = cs->singlestep_enabled; |
dedc5eae MF |
2921 | dc.tb = tb; |
2922 | dc.pc = pc_start; | |
f0a548b9 MF |
2923 | dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK; |
2924 | dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring; | |
797d780b MF |
2925 | dc.lbeg = env->sregs[LBEG]; |
2926 | dc.lend = env->sregs[LEND]; | |
dedc5eae | 2927 | dc.is_jmp = DISAS_NEXT; |
b994e91b | 2928 | dc.ccount_delta = 0; |
e61dc8f7 | 2929 | dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG; |
35b5c044 | 2930 | dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT; |
ef04a846 MF |
2931 | dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >> |
2932 | XTENSA_TBFLAG_CPENABLE_SHIFT; | |
dedc5eae | 2933 | |
6ad6dbf7 | 2934 | init_litbase(&dc); |
3580ecad | 2935 | init_sar_tracker(&dc); |
772177c1 | 2936 | reset_used_window(&dc); |
35b5c044 MF |
2937 | if (dc.icount) { |
2938 | dc.next_icount = tcg_temp_local_new_i32(); | |
2939 | } | |
3580ecad | 2940 | |
806f352d | 2941 | gen_tb_start(); |
dedc5eae | 2942 | |
a00817cc | 2943 | if (tb->flags & XTENSA_TBFLAG_EXCEPTION) { |
40643d7c | 2944 | tcg_gen_movi_i32(cpu_pc, dc.pc); |
b994e91b | 2945 | gen_exception(&dc, EXCP_DEBUG); |
40643d7c MF |
2946 | } |
2947 | ||
dedc5eae MF |
2948 | do { |
2949 | check_breakpoint(env, &dc); | |
2950 | ||
2951 | if (search_pc) { | |
92414b31 | 2952 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
dedc5eae MF |
2953 | if (lj < j) { |
2954 | lj++; | |
2955 | while (lj < j) { | |
ab1103de | 2956 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
dedc5eae MF |
2957 | } |
2958 | } | |
25983cad | 2959 | tcg_ctx.gen_opc_pc[lj] = dc.pc; |
ab1103de | 2960 | tcg_ctx.gen_opc_instr_start[lj] = 1; |
c9c99c22 | 2961 | tcg_ctx.gen_opc_icount[lj] = insn_count; |
dedc5eae MF |
2962 | } |
2963 | ||
fdefe51c | 2964 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { |
dedc5eae MF |
2965 | tcg_gen_debug_insn_start(dc.pc); |
2966 | } | |
2967 | ||
b994e91b MF |
2968 | ++dc.ccount_delta; |
2969 | ||
2970 | if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { | |
2971 | gen_io_start(); | |
2972 | } | |
2973 | ||
35b5c044 MF |
2974 | if (dc.icount) { |
2975 | int label = gen_new_label(); | |
2976 | ||
2977 | tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1); | |
2978 | tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label); | |
2979 | tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]); | |
2980 | if (dc.debug) { | |
2981 | gen_debug_exception(&dc, DEBUGCAUSE_IC); | |
2982 | } | |
2983 | gen_set_label(label); | |
2984 | } | |
2985 | ||
e61dc8f7 MF |
2986 | if (dc.debug) { |
2987 | gen_ibreak_check(env, &dc); | |
2988 | } | |
2989 | ||
0c4fabea | 2990 | disas_xtensa_insn(env, &dc); |
dedc5eae | 2991 | ++insn_count; |
35b5c044 MF |
2992 | if (dc.icount) { |
2993 | tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount); | |
2994 | } | |
ed2803da | 2995 | if (cs->singlestep_enabled) { |
dedc5eae | 2996 | tcg_gen_movi_i32(cpu_pc, dc.pc); |
b994e91b | 2997 | gen_exception(&dc, EXCP_DEBUG); |
dedc5eae MF |
2998 | break; |
2999 | } | |
3000 | } while (dc.is_jmp == DISAS_NEXT && | |
3001 | insn_count < max_insns && | |
3002 | dc.pc < next_page_start && | |
efd7f486 | 3003 | tcg_ctx.gen_opc_ptr < gen_opc_end); |
dedc5eae | 3004 | |
6ad6dbf7 | 3005 | reset_litbase(&dc); |
3580ecad | 3006 | reset_sar_tracker(&dc); |
35b5c044 MF |
3007 | if (dc.icount) { |
3008 | tcg_temp_free(dc.next_icount); | |
3009 | } | |
3580ecad | 3010 | |
b994e91b MF |
3011 | if (tb->cflags & CF_LAST_IO) { |
3012 | gen_io_end(); | |
3013 | } | |
3014 | ||
dedc5eae MF |
3015 | if (dc.is_jmp == DISAS_NEXT) { |
3016 | gen_jumpi(&dc, dc.pc, 0); | |
3017 | } | |
806f352d | 3018 | gen_tb_end(tb, insn_count); |
efd7f486 | 3019 | *tcg_ctx.gen_opc_ptr = INDEX_op_end; |
dedc5eae | 3020 | |
36f25d25 MF |
3021 | if (search_pc) { |
3022 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; | |
3023 | memset(tcg_ctx.gen_opc_instr_start + lj + 1, 0, | |
3024 | (j - lj) * sizeof(tcg_ctx.gen_opc_instr_start[0])); | |
3025 | } else { | |
dedc5eae MF |
3026 | tb->size = dc.pc - pc_start; |
3027 | tb->icount = insn_count; | |
3028 | } | |
2328826b MF |
3029 | } |
3030 | ||
97129ac8 | 3031 | void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb) |
2328826b | 3032 | { |
90b85b77 | 3033 | gen_intermediate_code_internal(xtensa_env_get_cpu(env), tb, false); |
2328826b MF |
3034 | } |
3035 | ||
97129ac8 | 3036 | void gen_intermediate_code_pc(CPUXtensaState *env, TranslationBlock *tb) |
2328826b | 3037 | { |
90b85b77 | 3038 | gen_intermediate_code_internal(xtensa_env_get_cpu(env), tb, true); |
2328826b MF |
3039 | } |
3040 | ||
878096ee AF |
3041 | void xtensa_cpu_dump_state(CPUState *cs, FILE *f, |
3042 | fprintf_function cpu_fprintf, int flags) | |
2328826b | 3043 | { |
878096ee AF |
3044 | XtensaCPU *cpu = XTENSA_CPU(cs); |
3045 | CPUXtensaState *env = &cpu->env; | |
2af3da91 MF |
3046 | int i, j; |
3047 | ||
3048 | cpu_fprintf(f, "PC=%08x\n\n", env->pc); | |
3049 | ||
3050 | for (i = j = 0; i < 256; ++i) { | |
fe0bd475 MF |
3051 | if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) { |
3052 | cpu_fprintf(f, "%12s=%08x%c", sregnames[i].name, env->sregs[i], | |
2af3da91 MF |
3053 | (j++ % 4) == 3 ? '\n' : ' '); |
3054 | } | |
3055 | } | |
3056 | ||
3057 | cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n"); | |
3058 | ||
3059 | for (i = j = 0; i < 256; ++i) { | |
fe0bd475 MF |
3060 | if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)) { |
3061 | cpu_fprintf(f, "%s=%08x%c", uregnames[i].name, env->uregs[i], | |
2af3da91 MF |
3062 | (j++ % 4) == 3 ? '\n' : ' '); |
3063 | } | |
3064 | } | |
2328826b | 3065 | |
2af3da91 | 3066 | cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n"); |
2328826b MF |
3067 | |
3068 | for (i = 0; i < 16; ++i) { | |
fe0bd475 | 3069 | cpu_fprintf(f, " A%02d=%08x%c", i, env->regs[i], |
2328826b MF |
3070 | (i % 4) == 3 ? '\n' : ' '); |
3071 | } | |
553e44f9 MF |
3072 | |
3073 | cpu_fprintf(f, "\n"); | |
3074 | ||
3075 | for (i = 0; i < env->config->nareg; ++i) { | |
3076 | cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i], | |
3077 | (i % 4) == 3 ? '\n' : ' '); | |
3078 | } | |
dd519cbe MF |
3079 | |
3080 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) { | |
3081 | cpu_fprintf(f, "\n"); | |
3082 | ||
3083 | for (i = 0; i < 16; ++i) { | |
3084 | cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i, | |
3085 | float32_val(env->fregs[i]), | |
3086 | *(float *)&env->fregs[i], (i % 2) == 1 ? '\n' : ' '); | |
3087 | } | |
3088 | } | |
2328826b MF |
3089 | } |
3090 | ||
97129ac8 | 3091 | void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, int pc_pos) |
2328826b | 3092 | { |
25983cad | 3093 | env->pc = tcg_ctx.gen_opc_pc[pc_pos]; |
2328826b | 3094 | } |