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exec: fix TB invalidation after breakpoint insertion/deletion
[qemu.git] / target-xtensa / translate.c
CommitLineData
2328826b
MF		 1/*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <stdio.h>
32
33#include "cpu.h"
34#include "exec-all.h"
35#include "disas.h"
36#include "tcg-op.h"
37#include "qemu-log.h"
1ddeaa5d 38#include "sysemu.h"
2328826b 39
16c1deae 40#include "helper.h"
dedc5eae 41#define GEN_HELPER 1
16c1deae 42#include "helper.h"
dedc5eae
MF		 43
44typedef struct DisasContext {
45 const XtensaConfig *config;
46 TranslationBlock *tb;
47 uint32_t pc;
48 uint32_t next_pc;
f0a548b9
MF		 49 int cring;
50 int ring;
797d780b
MF		 51 uint32_t lbeg;
52 uint32_t lend;
6ad6dbf7 53 TCGv_i32 litbase;
dedc5eae
MF		 54 int is_jmp;
55 int singlestep_enabled;
3580ecad
MF		 56
57 bool sar_5bit;
58 bool sar_m32_5bit;
59 bool sar_m32_allocated;
60 TCGv_i32 sar_m32;
b994e91b
MF		 61
62 uint32_t ccount_delta;
772177c1 63 unsigned used_window;
e61dc8f7
MF		 64
65 bool debug;
35b5c044
MF		 66 bool icount;
67 TCGv_i32 next_icount;
dedc5eae
MF		 68} DisasContext;
69
70static TCGv_ptr cpu_env;
71static TCGv_i32 cpu_pc;
72static TCGv_i32 cpu_R[16];
2af3da91
MF		 73static TCGv_i32 cpu_SR[256];
74static TCGv_i32 cpu_UR[256];
dedc5eae
MF		 75
76#include "gen-icount.h"
2328826b 77
2af3da91 78static const char * const sregnames[256] = {
797d780b
MF		 79 [LBEG] = "LBEG",
80 [LEND] = "LEND",
81 [LCOUNT] = "LCOUNT",
3580ecad 82 [SAR] = "SAR",
4dd85b6b 83 [BR] = "BR",
6ad6dbf7 84 [LITBASE] = "LITBASE",
809377aa 85 [SCOMPARE1] = "SCOMPARE1",
6825b6c3
MF		 86 [ACCLO] = "ACCLO",
87 [ACCHI] = "ACCHI",
88 [MR] = "MR0",
89 [MR + 1] = "MR1",
90 [MR + 2] = "MR2",
91 [MR + 3] = "MR3",
553e44f9
MF		 92 [WINDOW_BASE] = "WINDOW_BASE",
93 [WINDOW_START] = "WINDOW_START",
b67ea0cd
MF		 94 [PTEVADDR] = "PTEVADDR",
95 [RASID] = "RASID",
96 [ITLBCFG] = "ITLBCFG",
97 [DTLBCFG] = "DTLBCFG",
e61dc8f7
MF		 98 [IBREAKENABLE] = "IBREAKENABLE",
99 [IBREAKA] = "IBREAKA0",
100 [IBREAKA + 1] = "IBREAKA1",
f14c4b5f
MF		 101 [DBREAKA] = "DBREAKA0",
102 [DBREAKA + 1] = "DBREAKA1",
103 [DBREAKC] = "DBREAKC0",
104 [DBREAKC + 1] = "DBREAKC1",
40643d7c 105 [EPC1] = "EPC1",
b994e91b
MF		 106 [EPC1 + 1] = "EPC2",
107 [EPC1 + 2] = "EPC3",
108 [EPC1 + 3] = "EPC4",
109 [EPC1 + 4] = "EPC5",
110 [EPC1 + 5] = "EPC6",
111 [EPC1 + 6] = "EPC7",
40643d7c 112 [DEPC] = "DEPC",
b994e91b
MF		 113 [EPS2] = "EPS2",
114 [EPS2 + 1] = "EPS3",
115 [EPS2 + 2] = "EPS4",
116 [EPS2 + 3] = "EPS5",
117 [EPS2 + 4] = "EPS6",
118 [EPS2 + 5] = "EPS7",
40643d7c 119 [EXCSAVE1] = "EXCSAVE1",
b994e91b
MF		 120 [EXCSAVE1 + 1] = "EXCSAVE2",
121 [EXCSAVE1 + 2] = "EXCSAVE3",
122 [EXCSAVE1 + 3] = "EXCSAVE4",
123 [EXCSAVE1 + 4] = "EXCSAVE5",
124 [EXCSAVE1 + 5] = "EXCSAVE6",
125 [EXCSAVE1 + 6] = "EXCSAVE7",
f3df4c04 126 [CPENABLE] = "CPENABLE",
b994e91b
MF		 127 [INTSET] = "INTSET",
128 [INTCLEAR] = "INTCLEAR",
129 [INTENABLE] = "INTENABLE",
f0a548b9 130 [PS] = "PS",
97836cee 131 [VECBASE] = "VECBASE",
40643d7c 132 [EXCCAUSE] = "EXCCAUSE",
ab58c5b4 133 [DEBUGCAUSE] = "DEBUGCAUSE",
b994e91b 134 [CCOUNT] = "CCOUNT",
f3df4c04 135 [PRID] = "PRID",
35b5c044
MF		 136 [ICOUNT] = "ICOUNT",
137 [ICOUNTLEVEL] = "ICOUNTLEVEL",
40643d7c 138 [EXCVADDR] = "EXCVADDR",
b994e91b
MF		 139 [CCOMPARE] = "CCOMPARE0",
140 [CCOMPARE + 1] = "CCOMPARE1",
141 [CCOMPARE + 2] = "CCOMPARE2",
2af3da91
MF		 142};
143
144static const char * const uregnames[256] = {
145 [THREADPTR] = "THREADPTR",
146 [FCR] = "FCR",
147 [FSR] = "FSR",
148};
149
2328826b
MF		 150void xtensa_translate_init(void)
151{
dedc5eae
MF		 152 static const char * const regnames[] = {
153 "ar0", "ar1", "ar2", "ar3",
154 "ar4", "ar5", "ar6", "ar7",
155 "ar8", "ar9", "ar10", "ar11",
156 "ar12", "ar13", "ar14", "ar15",
157 };
158 int i;
159
160 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
161 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
97129ac8 162 offsetof(CPUXtensaState, pc), "pc");
dedc5eae
MF		 163
164 for (i = 0; i < 16; i++) {
165 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
97129ac8 166 offsetof(CPUXtensaState, regs[i]),
dedc5eae
MF		 167 regnames[i]);
168 }
2af3da91
MF		 169
170 for (i = 0; i < 256; ++i) {
171 if (sregnames[i]) {
172 cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
97129ac8 173 offsetof(CPUXtensaState, sregs[i]),
2af3da91
MF		 174 sregnames[i]);
175 }
176 }
177
178 for (i = 0; i < 256; ++i) {
179 if (uregnames[i]) {
180 cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
97129ac8 181 offsetof(CPUXtensaState, uregs[i]),
2af3da91
MF		 182 uregnames[i]);
183 }
184 }
dedc5eae 185#define GEN_HELPER 2
16c1deae 186#include "helper.h"
dedc5eae
MF		 187}
188
b67ea0cd
MF		 189static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
190{
191 return xtensa_option_bits_enabled(dc->config, opt);
192}
193
dedc5eae
MF		 194static inline bool option_enabled(DisasContext *dc, int opt)
195{
196 return xtensa_option_enabled(dc->config, opt);
197}
198
6ad6dbf7
MF		 199static void init_litbase(DisasContext *dc)
200{
201 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
202 dc->litbase = tcg_temp_local_new_i32();
203 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
204 }
205}
206
207static void reset_litbase(DisasContext *dc)
208{
209 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
210 tcg_temp_free(dc->litbase);
211 }
212}
213
3580ecad
MF		 214static void init_sar_tracker(DisasContext *dc)
215{
216 dc->sar_5bit = false;
217 dc->sar_m32_5bit = false;
218 dc->sar_m32_allocated = false;
219}
220
221static void reset_sar_tracker(DisasContext *dc)
222{
223 if (dc->sar_m32_allocated) {
224 tcg_temp_free(dc->sar_m32);
225 }
226}
227
228static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
229{
230 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
231 if (dc->sar_m32_5bit) {
232 tcg_gen_discard_i32(dc->sar_m32);
233 }
234 dc->sar_5bit = true;
235 dc->sar_m32_5bit = false;
236}
237
238static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
239{
240 TCGv_i32 tmp = tcg_const_i32(32);
241 if (!dc->sar_m32_allocated) {
242 dc->sar_m32 = tcg_temp_local_new_i32();
243 dc->sar_m32_allocated = true;
244 }
245 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
246 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
247 dc->sar_5bit = false;
248 dc->sar_m32_5bit = true;
249 tcg_temp_free(tmp);
250}
251
b994e91b
MF		 252static void gen_advance_ccount(DisasContext *dc)
253{
254 if (dc->ccount_delta > 0) {
255 TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
256 dc->ccount_delta = 0;
257 gen_helper_advance_ccount(tmp);
258 tcg_temp_free(tmp);
259 }
260}
261
772177c1
MF		 262static void reset_used_window(DisasContext *dc)
263{
264 dc->used_window = 0;
265}
266
b994e91b 267static void gen_exception(DisasContext *dc, int excp)
dedc5eae
MF		 268{
269 TCGv_i32 tmp = tcg_const_i32(excp);
b994e91b 270 gen_advance_ccount(dc);
dedc5eae
MF		 271 gen_helper_exception(tmp);
272 tcg_temp_free(tmp);
273}
274
40643d7c
MF		 275static void gen_exception_cause(DisasContext *dc, uint32_t cause)
276{
277 TCGv_i32 tpc = tcg_const_i32(dc->pc);
278 TCGv_i32 tcause = tcg_const_i32(cause);
b994e91b 279 gen_advance_ccount(dc);
40643d7c
MF		 280 gen_helper_exception_cause(tpc, tcause);
281 tcg_temp_free(tpc);
282 tcg_temp_free(tcause);
6b814719
MF		 283 if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
284 cause == SYSCALL_CAUSE) {
285 dc->is_jmp = DISAS_UPDATE;
286 }
40643d7c
MF		 287}
288
5b4e481b
MF		 289static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
290 TCGv_i32 vaddr)
291{
292 TCGv_i32 tpc = tcg_const_i32(dc->pc);
293 TCGv_i32 tcause = tcg_const_i32(cause);
b994e91b 294 gen_advance_ccount(dc);
5b4e481b
MF		 295 gen_helper_exception_cause_vaddr(tpc, tcause, vaddr);
296 tcg_temp_free(tpc);
297 tcg_temp_free(tcause);
298}
299
e61dc8f7
MF		 300static void gen_debug_exception(DisasContext *dc, uint32_t cause)
301{
302 TCGv_i32 tpc = tcg_const_i32(dc->pc);
303 TCGv_i32 tcause = tcg_const_i32(cause);
304 gen_advance_ccount(dc);
305 gen_helper_debug_exception(tpc, tcause);
306 tcg_temp_free(tpc);
307 tcg_temp_free(tcause);
308 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
309 dc->is_jmp = DISAS_UPDATE;
310 }
311}
312
40643d7c
MF		 313static void gen_check_privilege(DisasContext *dc)
314{
315 if (dc->cring) {
316 gen_exception_cause(dc, PRIVILEGED_CAUSE);
6b814719 317 dc->is_jmp = DISAS_UPDATE;
40643d7c
MF		 318 }
319}
320
dedc5eae
MF		 321static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
322{
323 tcg_gen_mov_i32(cpu_pc, dest);
35b5c044
MF		 324 gen_advance_ccount(dc);
325 if (dc->icount) {
326 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
327 }
dedc5eae 328 if (dc->singlestep_enabled) {
b994e91b 329 gen_exception(dc, EXCP_DEBUG);
dedc5eae
MF		 330 } else {
331 if (slot >= 0) {
332 tcg_gen_goto_tb(slot);
333 tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);
334 } else {
335 tcg_gen_exit_tb(0);
336 }
337 }
338 dc->is_jmp = DISAS_UPDATE;
339}
340
67882fd1
MF		 341static void gen_jump(DisasContext *dc, TCGv dest)
342{
343 gen_jump_slot(dc, dest, -1);
344}
345
dedc5eae
MF		 346static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
347{
348 TCGv_i32 tmp = tcg_const_i32(dest);
349 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
350 slot = -1;
351 }
352 gen_jump_slot(dc, tmp, slot);
353 tcg_temp_free(tmp);
354}
355
553e44f9
MF		 356static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
357 int slot)
358{
359 TCGv_i32 tcallinc = tcg_const_i32(callinc);
360
361 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
362 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
363 tcg_temp_free(tcallinc);
364 tcg_gen_movi_i32(cpu_R[callinc << 2],
365 (callinc << 30) | (dc->next_pc & 0x3fffffff));
366 gen_jump_slot(dc, dest, slot);
367}
368
369static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
370{
371 gen_callw_slot(dc, callinc, dest, -1);
372}
373
374static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
375{
376 TCGv_i32 tmp = tcg_const_i32(dest);
377 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
378 slot = -1;
379 }
380 gen_callw_slot(dc, callinc, tmp, slot);
381 tcg_temp_free(tmp);
382}
383
797d780b
MF		 384static bool gen_check_loop_end(DisasContext *dc, int slot)
385{
386 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
387 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
388 dc->next_pc == dc->lend) {
389 int label = gen_new_label();
390
391 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
392 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
393 gen_jumpi(dc, dc->lbeg, slot);
394 gen_set_label(label);
395 gen_jumpi(dc, dc->next_pc, -1);
396 return true;
397 }
398 return false;
399}
400
401static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
402{
403 if (!gen_check_loop_end(dc, slot)) {
404 gen_jumpi(dc, dc->next_pc, slot);
405 }
406}
407
bd57fb91
MF		 408static void gen_brcond(DisasContext *dc, TCGCond cond,
409 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
410{
411 int label = gen_new_label();
412
413 tcg_gen_brcond_i32(cond, t0, t1, label);
797d780b 414 gen_jumpi_check_loop_end(dc, 0);
bd57fb91
MF		 415 gen_set_label(label);
416 gen_jumpi(dc, dc->pc + offset, 1);
417}
418
419static void gen_brcondi(DisasContext *dc, TCGCond cond,
420 TCGv_i32 t0, uint32_t t1, uint32_t offset)
421{
422 TCGv_i32 tmp = tcg_const_i32(t1);
423 gen_brcond(dc, cond, t0, tmp, offset);
424 tcg_temp_free(tmp);
425}
426
b994e91b
MF		 427static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
428{
429 gen_advance_ccount(dc);
430 tcg_gen_mov_i32(d, cpu_SR[sr]);
431}
432
b67ea0cd
MF		 433static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
434{
435 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
436 tcg_gen_or_i32(d, d, cpu_SR[sr]);
437 tcg_gen_andi_i32(d, d, 0xfffffffc);
438}
439
b8132eff
MF		 440static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
441{
442 static void (* const rsr_handler[256])(DisasContext *dc,
443 TCGv_i32 d, uint32_t sr) = {
b994e91b 444 [CCOUNT] = gen_rsr_ccount,
b67ea0cd 445 [PTEVADDR] = gen_rsr_ptevaddr,
b8132eff
MF		 446 };
447
448 if (sregnames[sr]) {
449 if (rsr_handler[sr]) {
450 rsr_handler[sr](dc, d, sr);
451 } else {
452 tcg_gen_mov_i32(d, cpu_SR[sr]);
453 }
454 } else {
455 qemu_log("RSR %d not implemented, ", sr);
456 }
457}
458
797d780b
MF		 459static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
460{
461 gen_helper_wsr_lbeg(s);
3d0be8a5 462 gen_jumpi_check_loop_end(dc, 0);
797d780b
MF		 463}
464
465static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
466{
467 gen_helper_wsr_lend(s);
3d0be8a5 468 gen_jumpi_check_loop_end(dc, 0);
797d780b
MF		 469}
470
3580ecad
MF		 471static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
472{
473 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
474 if (dc->sar_m32_5bit) {
475 tcg_gen_discard_i32(dc->sar_m32);
476 }
477 dc->sar_5bit = false;
478 dc->sar_m32_5bit = false;
479}
480
4dd85b6b
MF		 481static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
482{
483 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
484}
485
6ad6dbf7
MF		 486static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
487{
488 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
489 /* This can change tb->flags, so exit tb */
490 gen_jumpi_check_loop_end(dc, -1);
491}
492
6825b6c3
MF		 493static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
494{
495 tcg_gen_ext8s_i32(cpu_SR[sr], s);
496}
497
553e44f9
MF		 498static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
499{
500 gen_helper_wsr_windowbase(v);
772177c1
MF		 501 reset_used_window(dc);
502}
503
504static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
505{
53a72dfd 506 tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
772177c1 507 reset_used_window(dc);
553e44f9
MF		 508}
509
b67ea0cd
MF		 510static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
511{
512 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
513}
514
515static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
516{
517 gen_helper_wsr_rasid(v);
518 /* This can change tb->flags, so exit tb */
519 gen_jumpi_check_loop_end(dc, -1);
520}
521
522static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
523{
524 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
525}
526
e61dc8f7
MF		 527static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
528{
529 gen_helper_wsr_ibreakenable(v);
530 gen_jumpi_check_loop_end(dc, 0);
531}
532
533static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
534{
535 unsigned id = sr - IBREAKA;
536
537 if (id < dc->config->nibreak) {
538 TCGv_i32 tmp = tcg_const_i32(id);
539 gen_helper_wsr_ibreaka(tmp, v);
540 tcg_temp_free(tmp);
541 gen_jumpi_check_loop_end(dc, 0);
542 }
543}
544
f14c4b5f
MF		 545static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
546{
547 unsigned id = sr - DBREAKA;
548
549 if (id < dc->config->ndbreak) {
550 TCGv_i32 tmp = tcg_const_i32(id);
551 gen_helper_wsr_dbreaka(tmp, v);
552 tcg_temp_free(tmp);
553 }
554}
555
556static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
557{
558 unsigned id = sr - DBREAKC;
559
560 if (id < dc->config->ndbreak) {
561 TCGv_i32 tmp = tcg_const_i32(id);
562 gen_helper_wsr_dbreakc(tmp, v);
563 tcg_temp_free(tmp);
564 }
565}
566
b994e91b
MF		 567static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
568{
569 tcg_gen_andi_i32(cpu_SR[sr], v,
570 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
571 gen_helper_check_interrupts(cpu_env);
572 gen_jumpi_check_loop_end(dc, 0);
573}
574
575static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
576{
577 TCGv_i32 tmp = tcg_temp_new_i32();
578
579 tcg_gen_andi_i32(tmp, v,
580 dc->config->inttype_mask[INTTYPE_EDGE] |
581 dc->config->inttype_mask[INTTYPE_NMI] |
582 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
583 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
584 tcg_temp_free(tmp);
585 gen_helper_check_interrupts(cpu_env);
586}
587
588static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
589{
590 tcg_gen_mov_i32(cpu_SR[sr], v);
591 gen_helper_check_interrupts(cpu_env);
592 gen_jumpi_check_loop_end(dc, 0);
593}
594
f0a548b9
MF		 595static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
596{
597 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
598 PS_UM | PS_EXCM | PS_INTLEVEL;
599
600 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
601 mask |= PS_RING;
602 }
603 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
772177c1 604 reset_used_window(dc);
b994e91b
MF		 605 gen_helper_check_interrupts(cpu_env);
606 /* This can change mmu index and tb->flags, so exit tb */
797d780b 607 gen_jumpi_check_loop_end(dc, -1);
f0a548b9
MF		 608}
609
ab58c5b4
MF		 610static void gen_wsr_debugcause(DisasContext *dc, uint32_t sr, TCGv_i32 v)
611{
612}
613
f3df4c04
MF		 614static void gen_wsr_prid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
615{
616}
617
35b5c044
MF		 618static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
619{
620 if (dc->icount) {
621 tcg_gen_mov_i32(dc->next_icount, v);
622 } else {
623 tcg_gen_mov_i32(cpu_SR[sr], v);
624 }
625}
626
627static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
628{
629 tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
630 /* This can change tb->flags, so exit tb */
631 gen_jumpi_check_loop_end(dc, -1);
632}
633
b994e91b
MF		 634static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
635{
636 uint32_t id = sr - CCOMPARE;
637 if (id < dc->config->nccompare) {
638 uint32_t int_bit = 1 << dc->config->timerint[id];
639 gen_advance_ccount(dc);
640 tcg_gen_mov_i32(cpu_SR[sr], v);
641 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
642 gen_helper_check_interrupts(cpu_env);
643 }
644}
645
b8132eff
MF		 646static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
647{
648 static void (* const wsr_handler[256])(DisasContext *dc,
649 uint32_t sr, TCGv_i32 v) = {
797d780b
MF		 650 [LBEG] = gen_wsr_lbeg,
651 [LEND] = gen_wsr_lend,
3580ecad 652 [SAR] = gen_wsr_sar,
4dd85b6b 653 [BR] = gen_wsr_br,
6ad6dbf7 654 [LITBASE] = gen_wsr_litbase,
6825b6c3 655 [ACCHI] = gen_wsr_acchi,
553e44f9 656 [WINDOW_BASE] = gen_wsr_windowbase,
772177c1 657 [WINDOW_START] = gen_wsr_windowstart,
b67ea0cd
MF		 658 [PTEVADDR] = gen_wsr_ptevaddr,
659 [RASID] = gen_wsr_rasid,
660 [ITLBCFG] = gen_wsr_tlbcfg,
661 [DTLBCFG] = gen_wsr_tlbcfg,
e61dc8f7
MF		 662 [IBREAKENABLE] = gen_wsr_ibreakenable,
663 [IBREAKA] = gen_wsr_ibreaka,
664 [IBREAKA + 1] = gen_wsr_ibreaka,
f14c4b5f
MF		 665 [DBREAKA] = gen_wsr_dbreaka,
666 [DBREAKA + 1] = gen_wsr_dbreaka,
667 [DBREAKC] = gen_wsr_dbreakc,
668 [DBREAKC + 1] = gen_wsr_dbreakc,
b994e91b
MF		 669 [INTSET] = gen_wsr_intset,
670 [INTCLEAR] = gen_wsr_intclear,
671 [INTENABLE] = gen_wsr_intenable,
f0a548b9 672 [PS] = gen_wsr_ps,
ab58c5b4 673 [DEBUGCAUSE] = gen_wsr_debugcause,
f3df4c04 674 [PRID] = gen_wsr_prid,
35b5c044
MF		 675 [ICOUNT] = gen_wsr_icount,
676 [ICOUNTLEVEL] = gen_wsr_icountlevel,
b994e91b
MF		 677 [CCOMPARE] = gen_wsr_ccompare,
678 [CCOMPARE + 1] = gen_wsr_ccompare,
679 [CCOMPARE + 2] = gen_wsr_ccompare,
b8132eff
MF		 680 };
681
682 if (sregnames[sr]) {
683 if (wsr_handler[sr]) {
684 wsr_handler[sr](dc, sr, s);
685 } else {
686 tcg_gen_mov_i32(cpu_SR[sr], s);
687 }
688 } else {
689 qemu_log("WSR %d not implemented, ", sr);
690 }
691}
692
5b4e481b
MF		 693static void gen_load_store_alignment(DisasContext *dc, int shift,
694 TCGv_i32 addr, bool no_hw_alignment)
695{
696 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
697 tcg_gen_andi_i32(addr, addr, ~0 << shift);
698 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
699 no_hw_alignment) {
700 int label = gen_new_label();
701 TCGv_i32 tmp = tcg_temp_new_i32();
702 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
703 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
704 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
705 gen_set_label(label);
706 tcg_temp_free(tmp);
707 }
708}
709
b994e91b
MF		 710static void gen_waiti(DisasContext *dc, uint32_t imm4)
711{
712 TCGv_i32 pc = tcg_const_i32(dc->next_pc);
713 TCGv_i32 intlevel = tcg_const_i32(imm4);
714 gen_advance_ccount(dc);
715 gen_helper_waiti(pc, intlevel);
716 tcg_temp_free(pc);
717 tcg_temp_free(intlevel);
718}
719
772177c1
MF		 720static void gen_window_check1(DisasContext *dc, unsigned r1)
721{
722 if (dc->tb->flags & XTENSA_TBFLAG_EXCM) {
723 return;
724 }
725 if (option_enabled(dc, XTENSA_OPTION_WINDOWED_REGISTER) &&
726 r1 / 4 > dc->used_window) {
727 TCGv_i32 pc = tcg_const_i32(dc->pc);
728 TCGv_i32 w = tcg_const_i32(r1 / 4);
729
730 dc->used_window = r1 / 4;
731 gen_advance_ccount(dc);
732 gen_helper_window_check(pc, w);
733
734 tcg_temp_free(w);
735 tcg_temp_free(pc);
736 }
737}
738
739static void gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
740{
741 gen_window_check1(dc, r1 > r2 ? r1 : r2);
742}
743
744static void gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
745 unsigned r3)
746{
747 gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
748}
749
6825b6c3
MF		 750static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
751{
752 TCGv_i32 m = tcg_temp_new_i32();
753
754 if (hi) {
755 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
756 } else {
757 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
758 }
759 return m;
760}
761
dedc5eae
MF		 762static void disas_xtensa_insn(DisasContext *dc)
763{
b67ea0cd
MF		 764#define HAS_OPTION_BITS(opt) do { \
765 if (!option_bits_enabled(dc, opt)) { \
766 qemu_log("Option is not enabled %s:%d\n", \
767 __FILE__, __LINE__); \
dedc5eae
MF		 768 goto invalid_opcode; \
769 } \
770 } while (0)
771
b67ea0cd
MF		 772#define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
773
91a5bb76
MF		 774#define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
775#define RESERVED() do { \
776 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
777 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
778 goto invalid_opcode; \
779 } while (0)
780
781
dedc5eae
MF		 782#ifdef TARGET_WORDS_BIGENDIAN
783#define OP0 (((b0) & 0xf0) >> 4)
784#define OP1 (((b2) & 0xf0) >> 4)
785#define OP2 ((b2) & 0xf)
786#define RRR_R ((b1) & 0xf)
787#define RRR_S (((b1) & 0xf0) >> 4)
788#define RRR_T ((b0) & 0xf)
789#else
790#define OP0 (((b0) & 0xf))
791#define OP1 (((b2) & 0xf))
792#define OP2 (((b2) & 0xf0) >> 4)
793#define RRR_R (((b1) & 0xf0) >> 4)
794#define RRR_S (((b1) & 0xf))
795#define RRR_T (((b0) & 0xf0) >> 4)
796#endif
6825b6c3
MF		 797#define RRR_X ((RRR_R & 0x4) >> 2)
798#define RRR_Y ((RRR_T & 0x4) >> 2)
799#define RRR_W (RRR_R & 0x3)
dedc5eae
MF		 800
801#define RRRN_R RRR_R
802#define RRRN_S RRR_S
803#define RRRN_T RRR_T
804
805#define RRI8_R RRR_R
806#define RRI8_S RRR_S
807#define RRI8_T RRR_T
808#define RRI8_IMM8 (b2)
809#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
810
811#ifdef TARGET_WORDS_BIGENDIAN
812#define RI16_IMM16 (((b1) << 8) | (b2))
813#else
814#define RI16_IMM16 (((b2) << 8) | (b1))
815#endif
816
817#ifdef TARGET_WORDS_BIGENDIAN
818#define CALL_N (((b0) & 0xc) >> 2)
819#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
820#else
821#define CALL_N (((b0) & 0x30) >> 4)
822#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
823#endif
824#define CALL_OFFSET_SE \
825 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
826
827#define CALLX_N CALL_N
828#ifdef TARGET_WORDS_BIGENDIAN
829#define CALLX_M ((b0) & 0x3)
830#else
831#define CALLX_M (((b0) & 0xc0) >> 6)
832#endif
833#define CALLX_S RRR_S
834
835#define BRI12_M CALLX_M
836#define BRI12_S RRR_S
837#ifdef TARGET_WORDS_BIGENDIAN
838#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
839#else
840#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
841#endif
842#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
843
844#define BRI8_M BRI12_M
845#define BRI8_R RRI8_R
846#define BRI8_S RRI8_S
847#define BRI8_IMM8 RRI8_IMM8
848#define BRI8_IMM8_SE RRI8_IMM8_SE
849
850#define RSR_SR (b1)
851
852 uint8_t b0 = ldub_code(dc->pc);
853 uint8_t b1 = ldub_code(dc->pc + 1);
a044ec2a 854 uint8_t b2 = 0;
dedc5eae 855
bd57fb91
MF		 856 static const uint32_t B4CONST[] = {
857 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
858 };
859
860 static const uint32_t B4CONSTU[] = {
861 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
862 };
863
dedc5eae
MF		 864 if (OP0 >= 8) {
865 dc->next_pc = dc->pc + 2;
866 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
867 } else {
868 dc->next_pc = dc->pc + 3;
a044ec2a 869 b2 = ldub_code(dc->pc + 2);
dedc5eae
MF		 870 }
871
872 switch (OP0) {
873 case 0: /*QRST*/
874 switch (OP1) {
875 case 0: /*RST0*/
876 switch (OP2) {
877 case 0: /*ST0*/
878 if ((RRR_R & 0xc) == 0x8) {
879 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
880 }
881
882 switch (RRR_R) {
883 case 0: /*SNM0*/
5da4a6a8
MF		 884 switch (CALLX_M) {
885 case 0: /*ILL*/
40643d7c 886 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
5da4a6a8
MF		 887 break;
888
889 case 1: /*reserved*/
91a5bb76 890 RESERVED();
5da4a6a8
MF		 891 break;
892
893 case 2: /*JR*/
894 switch (CALLX_N) {
895 case 0: /*RET*/
896 case 2: /*JX*/
772177c1 897 gen_window_check1(dc, CALLX_S);
5da4a6a8
MF		 898 gen_jump(dc, cpu_R[CALLX_S]);
899 break;
900
901 case 1: /*RETWw*/
902 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 903 {
904 TCGv_i32 tmp = tcg_const_i32(dc->pc);
b994e91b 905 gen_advance_ccount(dc);
553e44f9
MF		 906 gen_helper_retw(tmp, tmp);
907 gen_jump(dc, tmp);
908 tcg_temp_free(tmp);
909 }
5da4a6a8
MF		 910 break;
911
912 case 3: /*reserved*/
91a5bb76 913 RESERVED();
5da4a6a8
MF		 914 break;
915 }
916 break;
917
918 case 3: /*CALLX*/
772177c1 919 gen_window_check2(dc, CALLX_S, CALLX_N << 2);
5da4a6a8
MF		 920 switch (CALLX_N) {
921 case 0: /*CALLX0*/
922 {
923 TCGv_i32 tmp = tcg_temp_new_i32();
924 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
925 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
926 gen_jump(dc, tmp);
927 tcg_temp_free(tmp);
928 }
929 break;
930
931 case 1: /*CALLX4w*/
932 case 2: /*CALLX8w*/
933 case 3: /*CALLX12w*/
934 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 935 {
936 TCGv_i32 tmp = tcg_temp_new_i32();
937
938 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
939 gen_callw(dc, CALLX_N, tmp);
940 tcg_temp_free(tmp);
941 }
5da4a6a8
MF		 942 break;
943 }
944 break;
945 }
dedc5eae
MF		 946 break;
947
948 case 1: /*MOVSPw*/
949 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
772177c1 950 gen_window_check2(dc, RRR_T, RRR_S);
553e44f9
MF		 951 {
952 TCGv_i32 pc = tcg_const_i32(dc->pc);
b994e91b 953 gen_advance_ccount(dc);
553e44f9
MF		 954 gen_helper_movsp(pc);
955 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
956 tcg_temp_free(pc);
957 }
dedc5eae
MF		 958 break;
959
960 case 2: /*SYNC*/
28067b22
MF		 961 switch (RRR_T) {
962 case 0: /*ISYNC*/
963 break;
964
965 case 1: /*RSYNC*/
966 break;
967
968 case 2: /*ESYNC*/
969 break;
970
971 case 3: /*DSYNC*/
972 break;
973
974 case 8: /*EXCW*/
975 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
976 break;
977
978 case 12: /*MEMW*/
979 break;
980
981 case 13: /*EXTW*/
982 break;
983
984 case 15: /*NOP*/
985 break;
986
987 default: /*reserved*/
988 RESERVED();
989 break;
990 }
91a5bb76
MF		 991 break;
992
993 case 3: /*RFEIx*/
40643d7c
MF		 994 switch (RRR_T) {
995 case 0: /*RFETx*/
996 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
997 switch (RRR_S) {
998 case 0: /*RFEx*/
999 gen_check_privilege(dc);
1000 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
b994e91b 1001 gen_helper_check_interrupts(cpu_env);
40643d7c
MF		 1002 gen_jump(dc, cpu_SR[EPC1]);
1003 break;
1004
1005 case 1: /*RFUEx*/
1006 RESERVED();
1007 break;
1008
1009 case 2: /*RFDEx*/
1010 gen_check_privilege(dc);
1011 gen_jump(dc, cpu_SR[
1012 dc->config->ndepc ? DEPC : EPC1]);
1013 break;
1014
1015 case 4: /*RFWOw*/
1016 case 5: /*RFWUw*/
1017 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1018 gen_check_privilege(dc);
1019 {
1020 TCGv_i32 tmp = tcg_const_i32(1);
1021
1022 tcg_gen_andi_i32(
1023 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1024 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
1025
1026 if (RRR_S == 4) {
1027 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
1028 cpu_SR[WINDOW_START], tmp);
1029 } else {
1030 tcg_gen_or_i32(cpu_SR[WINDOW_START],
1031 cpu_SR[WINDOW_START], tmp);
1032 }
1033
1034 gen_helper_restore_owb();
b994e91b 1035 gen_helper_check_interrupts(cpu_env);
553e44f9
MF		 1036 gen_jump(dc, cpu_SR[EPC1]);
1037
1038 tcg_temp_free(tmp);
1039 }
40643d7c
MF		 1040 break;
1041
1042 default: /*reserved*/
1043 RESERVED();
1044 break;
1045 }
1046 break;
1047
1048 case 1: /*RFIx*/
1049 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
b994e91b
MF		 1050 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
1051 gen_check_privilege(dc);
1052 tcg_gen_mov_i32(cpu_SR[PS],
1053 cpu_SR[EPS2 + RRR_S - 2]);
1054 gen_helper_check_interrupts(cpu_env);
1055 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
1056 } else {
1057 qemu_log("RFI %d is illegal\n", RRR_S);
1058 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1059 }
40643d7c
MF		 1060 break;
1061
1062 case 2: /*RFME*/
1063 TBD();
1064 break;
1065
1066 default: /*reserved*/
1067 RESERVED();
1068 break;
1069
1070 }
91a5bb76
MF		 1071 break;
1072
1073 case 4: /*BREAKx*/
e61dc8f7
MF		 1074 HAS_OPTION(XTENSA_OPTION_DEBUG);
1075 if (dc->debug) {
1076 gen_debug_exception(dc, DEBUGCAUSE_BI);
1077 }
91a5bb76
MF		 1078 break;
1079
1080 case 5: /*SYSCALLx*/
1081 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
40643d7c
MF		 1082 switch (RRR_S) {
1083 case 0: /*SYSCALLx*/
1084 gen_exception_cause(dc, SYSCALL_CAUSE);
1085 break;
1086
1087 case 1: /*SIMCALL*/
1ddeaa5d
MF		 1088 if (semihosting_enabled) {
1089 gen_check_privilege(dc);
1090 gen_helper_simcall(cpu_env);
1091 } else {
1092 qemu_log("SIMCALL but semihosting is disabled\n");
1093 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1094 }
40643d7c
MF		 1095 break;
1096
1097 default:
1098 RESERVED();
1099 break;
1100 }
91a5bb76
MF		 1101 break;
1102
1103 case 6: /*RSILx*/
1104 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
40643d7c 1105 gen_check_privilege(dc);
772177c1 1106 gen_window_check1(dc, RRR_T);
40643d7c 1107 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
b994e91b 1108 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
40643d7c 1109 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
b994e91b
MF		 1110 gen_helper_check_interrupts(cpu_env);
1111 gen_jumpi_check_loop_end(dc, 0);
91a5bb76
MF		 1112 break;
1113
1114 case 7: /*WAITIx*/
1115 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
b994e91b
MF		 1116 gen_check_privilege(dc);
1117 gen_waiti(dc, RRR_S);
91a5bb76
MF		 1118 break;
1119
1120 case 8: /*ANY4p*/
91a5bb76 1121 case 9: /*ALL4p*/
91a5bb76 1122 case 10: /*ANY8p*/
91a5bb76
MF		 1123 case 11: /*ALL8p*/
1124 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 1125 {
1126 const unsigned shift = (RRR_R & 2) ? 8 : 4;
1127 TCGv_i32 mask = tcg_const_i32(
1128 ((1 << shift) - 1) << RRR_S);
1129 TCGv_i32 tmp = tcg_temp_new_i32();
1130
1131 tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
1132 if (RRR_R & 1) { /*ALL*/
1133 tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
1134 } else { /*ANY*/
1135 tcg_gen_add_i32(tmp, tmp, mask);
1136 }
1137 tcg_gen_shri_i32(tmp, tmp, RRR_S + shift);
1138 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
1139 tmp, RRR_T, 1);
1140 tcg_temp_free(mask);
1141 tcg_temp_free(tmp);
1142 }
91a5bb76
MF		 1143 break;
1144
1145 default: /*reserved*/
1146 RESERVED();
dedc5eae
MF		 1147 break;
1148
1149 }
1150 break;
1151
1152 case 1: /*AND*/
772177c1 1153 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1154 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1155 break;
1156
1157 case 2: /*OR*/
772177c1 1158 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1159 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1160 break;
1161
1162 case 3: /*XOR*/
772177c1 1163 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1164 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1165 break;
1166
1167 case 4: /*ST1*/
3580ecad
MF		 1168 switch (RRR_R) {
1169 case 0: /*SSR*/
772177c1 1170 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1171 gen_right_shift_sar(dc, cpu_R[RRR_S]);
1172 break;
1173
1174 case 1: /*SSL*/
772177c1 1175 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1176 gen_left_shift_sar(dc, cpu_R[RRR_S]);
1177 break;
1178
1179 case 2: /*SSA8L*/
772177c1 1180 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1181 {
1182 TCGv_i32 tmp = tcg_temp_new_i32();
1183 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1184 gen_right_shift_sar(dc, tmp);
1185 tcg_temp_free(tmp);
1186 }
1187 break;
1188
1189 case 3: /*SSA8B*/
772177c1 1190 gen_window_check1(dc, RRR_S);
3580ecad
MF		 1191 {
1192 TCGv_i32 tmp = tcg_temp_new_i32();
1193 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1194 gen_left_shift_sar(dc, tmp);
1195 tcg_temp_free(tmp);
1196 }
1197 break;
1198
1199 case 4: /*SSAI*/
1200 {
1201 TCGv_i32 tmp = tcg_const_i32(
1202 RRR_S | ((RRR_T & 1) << 4));
1203 gen_right_shift_sar(dc, tmp);
1204 tcg_temp_free(tmp);
1205 }
1206 break;
1207
1208 case 6: /*RER*/
91a5bb76 1209 TBD();
3580ecad
MF		 1210 break;
1211
1212 case 7: /*WER*/
91a5bb76 1213 TBD();
3580ecad
MF		 1214 break;
1215
1216 case 8: /*ROTWw*/
1217 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1218 gen_check_privilege(dc);
1219 {
1220 TCGv_i32 tmp = tcg_const_i32(
1221 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
1222 gen_helper_rotw(tmp);
1223 tcg_temp_free(tmp);
772177c1 1224 reset_used_window(dc);
553e44f9 1225 }
3580ecad
MF		 1226 break;
1227
1228 case 14: /*NSAu*/
7f65f4b0 1229 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
772177c1 1230 gen_window_check2(dc, RRR_S, RRR_T);
3580ecad
MF		 1231 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1232 break;
1233
1234 case 15: /*NSAUu*/
7f65f4b0 1235 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
772177c1 1236 gen_window_check2(dc, RRR_S, RRR_T);
3580ecad
MF		 1237 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1238 break;
1239
1240 default: /*reserved*/
91a5bb76 1241 RESERVED();
3580ecad
MF		 1242 break;
1243 }
dedc5eae
MF		 1244 break;
1245
1246 case 5: /*TLB*/
b67ea0cd
MF		 1247 HAS_OPTION_BITS(
1248 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
1249 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1250 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION));
1251 gen_check_privilege(dc);
1252 gen_window_check2(dc, RRR_S, RRR_T);
1253 {
1254 TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0);
1255
1256 switch (RRR_R & 7) {
1257 case 3: /*RITLB0*/ /*RDTLB0*/
1258 gen_helper_rtlb0(cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1259 break;
1260
1261 case 4: /*IITLB*/ /*IDTLB*/
1262 gen_helper_itlb(cpu_R[RRR_S], dtlb);
1263 /* This could change memory mapping, so exit tb */
1264 gen_jumpi_check_loop_end(dc, -1);
1265 break;
1266
1267 case 5: /*PITLB*/ /*PDTLB*/
1268 tcg_gen_movi_i32(cpu_pc, dc->pc);
1269 gen_helper_ptlb(cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1270 break;
1271
1272 case 6: /*WITLB*/ /*WDTLB*/
1273 gen_helper_wtlb(cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1274 /* This could change memory mapping, so exit tb */
1275 gen_jumpi_check_loop_end(dc, -1);
1276 break;
1277
1278 case 7: /*RITLB1*/ /*RDTLB1*/
1279 gen_helper_rtlb1(cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1280 break;
1281
1282 default:
1283 tcg_temp_free(dtlb);
1284 RESERVED();
1285 break;
1286 }
1287 tcg_temp_free(dtlb);
1288 }
dedc5eae
MF		 1289 break;
1290
1291 case 6: /*RT0*/
772177c1 1292 gen_window_check2(dc, RRR_R, RRR_T);
f331fe5e
MF		 1293 switch (RRR_S) {
1294 case 0: /*NEG*/
1295 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1296 break;
1297
1298 case 1: /*ABS*/
1299 {
1300 int label = gen_new_label();
1301 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1302 tcg_gen_brcondi_i32(
1303 TCG_COND_GE, cpu_R[RRR_R], 0, label);
1304 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1305 gen_set_label(label);
1306 }
1307 break;
1308
1309 default: /*reserved*/
91a5bb76 1310 RESERVED();
f331fe5e
MF		 1311 break;
1312 }
dedc5eae
MF		 1313 break;
1314
1315 case 7: /*reserved*/
91a5bb76 1316 RESERVED();
dedc5eae
MF		 1317 break;
1318
1319 case 8: /*ADD*/
772177c1 1320 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1321 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1322 break;
1323
1324 case 9: /*ADD**/
1325 case 10:
1326 case 11:
772177c1 1327 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1328 {
1329 TCGv_i32 tmp = tcg_temp_new_i32();
1330 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1331 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1332 tcg_temp_free(tmp);
1333 }
1334 break;
1335
1336 case 12: /*SUB*/
772177c1 1337 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1338 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1339 break;
1340
1341 case 13: /*SUB**/
1342 case 14:
1343 case 15:
772177c1 1344 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
dedc5eae
MF		 1345 {
1346 TCGv_i32 tmp = tcg_temp_new_i32();
1347 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1348 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1349 tcg_temp_free(tmp);
1350 }
1351 break;
1352 }
1353 break;
1354
1355 case 1: /*RST1*/
3580ecad
MF		 1356 switch (OP2) {
1357 case 0: /*SLLI*/
1358 case 1:
772177c1 1359 gen_window_check2(dc, RRR_R, RRR_S);
3580ecad
MF		 1360 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1361 32 - (RRR_T | ((OP2 & 1) << 4)));
1362 break;
1363
1364 case 2: /*SRAI*/
1365 case 3:
772177c1 1366 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1367 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1368 RRR_S | ((OP2 & 1) << 4));
1369 break;
1370
1371 case 4: /*SRLI*/
772177c1 1372 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1373 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1374 break;
1375
1376 case 6: /*XSR*/
1377 {
1378 TCGv_i32 tmp = tcg_temp_new_i32();
40643d7c
MF		 1379 if (RSR_SR >= 64) {
1380 gen_check_privilege(dc);
1381 }
772177c1 1382 gen_window_check1(dc, RRR_T);
3580ecad
MF		 1383 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1384 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1385 gen_wsr(dc, RSR_SR, tmp);
1386 tcg_temp_free(tmp);
91a5bb76
MF		 1387 if (!sregnames[RSR_SR]) {
1388 TBD();
1389 }
3580ecad
MF		 1390 }
1391 break;
1392
1393 /*
1394 * Note: 64 bit ops are used here solely because SAR values
1395 * have range 0..63
1396 */
1397#define gen_shift_reg(cmd, reg) do { \
1398 TCGv_i64 tmp = tcg_temp_new_i64(); \
1399 tcg_gen_extu_i32_i64(tmp, reg); \
1400 tcg_gen_##cmd##_i64(v, v, tmp); \
1401 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1402 tcg_temp_free_i64(v); \
1403 tcg_temp_free_i64(tmp); \
1404 } while (0)
1405
1406#define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1407
1408 case 8: /*SRC*/
772177c1 1409 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
3580ecad
MF		 1410 {
1411 TCGv_i64 v = tcg_temp_new_i64();
1412 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1413 gen_shift(shr);
1414 }
1415 break;
1416
1417 case 9: /*SRL*/
772177c1 1418 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1419 if (dc->sar_5bit) {
1420 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1421 } else {
1422 TCGv_i64 v = tcg_temp_new_i64();
1423 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1424 gen_shift(shr);
1425 }
1426 break;
1427
1428 case 10: /*SLL*/
772177c1 1429 gen_window_check2(dc, RRR_R, RRR_S);
3580ecad
MF		 1430 if (dc->sar_m32_5bit) {
1431 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1432 } else {
1433 TCGv_i64 v = tcg_temp_new_i64();
1434 TCGv_i32 s = tcg_const_i32(32);
1435 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1436 tcg_gen_andi_i32(s, s, 0x3f);
1437 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1438 gen_shift_reg(shl, s);
1439 tcg_temp_free(s);
1440 }
1441 break;
1442
1443 case 11: /*SRA*/
772177c1 1444 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1445 if (dc->sar_5bit) {
1446 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1447 } else {
1448 TCGv_i64 v = tcg_temp_new_i64();
1449 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1450 gen_shift(sar);
1451 }
1452 break;
1453#undef gen_shift
1454#undef gen_shift_reg
1455
1456 case 12: /*MUL16U*/
1457 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
772177c1 1458 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
3580ecad
MF		 1459 {
1460 TCGv_i32 v1 = tcg_temp_new_i32();
1461 TCGv_i32 v2 = tcg_temp_new_i32();
1462 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1463 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1464 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1465 tcg_temp_free(v2);
1466 tcg_temp_free(v1);
1467 }
1468 break;
1469
1470 case 13: /*MUL16S*/
1471 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
772177c1 1472 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
3580ecad
MF		 1473 {
1474 TCGv_i32 v1 = tcg_temp_new_i32();
1475 TCGv_i32 v2 = tcg_temp_new_i32();
1476 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1477 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1478 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1479 tcg_temp_free(v2);
1480 tcg_temp_free(v1);
1481 }
1482 break;
1483
1484 default: /*reserved*/
91a5bb76 1485 RESERVED();
3580ecad
MF		 1486 break;
1487 }
dedc5eae
MF		 1488 break;
1489
1490 case 2: /*RST2*/
4dd85b6b
MF		 1491 if (OP2 >= 8) {
1492 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1493 }
772177c1 1494
f76ebf55
MF		 1495 if (OP2 >= 12) {
1496 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
1497 int label = gen_new_label();
1498 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1499 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1500 gen_set_label(label);
1501 }
1502
1503 switch (OP2) {
4dd85b6b
MF		 1504#define BOOLEAN_LOGIC(fn, r, s, t) \
1505 do { \
1506 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1507 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1508 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1509 \
1510 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1511 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1512 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1513 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1514 tcg_temp_free(tmp1); \
1515 tcg_temp_free(tmp2); \
1516 } while (0)
1517
1518 case 0: /*ANDBp*/
1519 BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T);
1520 break;
1521
1522 case 1: /*ANDBCp*/
1523 BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T);
1524 break;
1525
1526 case 2: /*ORBp*/
1527 BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T);
1528 break;
1529
1530 case 3: /*ORBCp*/
1531 BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T);
1532 break;
1533
1534 case 4: /*XORBp*/
1535 BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T);
1536 break;
1537
1538#undef BOOLEAN_LOGIC
1539
f76ebf55
MF		 1540 case 8: /*MULLi*/
1541 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1542 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1543 break;
1544
1545 case 10: /*MULUHi*/
1546 case 11: /*MULSHi*/
7f65f4b0 1547 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
f76ebf55
MF		 1548 {
1549 TCGv_i64 r = tcg_temp_new_i64();
1550 TCGv_i64 s = tcg_temp_new_i64();
1551 TCGv_i64 t = tcg_temp_new_i64();
1552
1553 if (OP2 == 10) {
1554 tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]);
1555 tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]);
1556 } else {
1557 tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]);
1558 tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]);
1559 }
1560 tcg_gen_mul_i64(r, s, t);
1561 tcg_gen_shri_i64(r, r, 32);
1562 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r);
1563
1564 tcg_temp_free_i64(r);
1565 tcg_temp_free_i64(s);
1566 tcg_temp_free_i64(t);
1567 }
1568 break;
1569
1570 case 12: /*QUOUi*/
1571 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1572 break;
1573
1574 case 13: /*QUOSi*/
1575 case 15: /*REMSi*/
1576 {
1577 int label1 = gen_new_label();
1578 int label2 = gen_new_label();
1579
1580 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1581 label1);
1582 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1583 label1);
1584 tcg_gen_movi_i32(cpu_R[RRR_R],
1585 OP2 == 13 ? 0x80000000 : 0);
1586 tcg_gen_br(label2);
1587 gen_set_label(label1);
1588 if (OP2 == 13) {
1589 tcg_gen_div_i32(cpu_R[RRR_R],
1590 cpu_R[RRR_S], cpu_R[RRR_T]);
1591 } else {
1592 tcg_gen_rem_i32(cpu_R[RRR_R],
1593 cpu_R[RRR_S], cpu_R[RRR_T]);
1594 }
1595 gen_set_label(label2);
1596 }
1597 break;
1598
1599 case 14: /*REMUi*/
1600 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1601 break;
1602
1603 default: /*reserved*/
1604 RESERVED();
1605 break;
1606 }
dedc5eae
MF		 1607 break;
1608
1609 case 3: /*RST3*/
b8132eff
MF		 1610 switch (OP2) {
1611 case 0: /*RSR*/
40643d7c
MF		 1612 if (RSR_SR >= 64) {
1613 gen_check_privilege(dc);
1614 }
772177c1 1615 gen_window_check1(dc, RRR_T);
b8132eff 1616 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
91a5bb76
MF		 1617 if (!sregnames[RSR_SR]) {
1618 TBD();
1619 }
b8132eff
MF		 1620 break;
1621
1622 case 1: /*WSR*/
40643d7c
MF		 1623 if (RSR_SR >= 64) {
1624 gen_check_privilege(dc);
1625 }
772177c1 1626 gen_window_check1(dc, RRR_T);
b8132eff 1627 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
91a5bb76
MF		 1628 if (!sregnames[RSR_SR]) {
1629 TBD();
1630 }
b8132eff
MF		 1631 break;
1632
1633 case 2: /*SEXTu*/
7f65f4b0 1634 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT);
772177c1 1635 gen_window_check2(dc, RRR_R, RRR_S);
b8132eff
MF		 1636 {
1637 int shift = 24 - RRR_T;
1638
1639 if (shift == 24) {
1640 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1641 } else if (shift == 16) {
1642 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1643 } else {
1644 TCGv_i32 tmp = tcg_temp_new_i32();
1645 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1646 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1647 tcg_temp_free(tmp);
1648 }
1649 }
1650 break;
1651
1652 case 3: /*CLAMPSu*/
7f65f4b0 1653 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS);
772177c1 1654 gen_window_check2(dc, RRR_R, RRR_S);
b8132eff
MF		 1655 {
1656 TCGv_i32 tmp1 = tcg_temp_new_i32();
1657 TCGv_i32 tmp2 = tcg_temp_new_i32();
1658 int label = gen_new_label();
1659
1660 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1661 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1662 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
1663 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1664 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp2, 0, label);
1665
1666 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
1667 tcg_gen_xori_i32(cpu_R[RRR_R], tmp1,
1668 0xffffffff >> (25 - RRR_T));
1669
1670 gen_set_label(label);
1671
1672 tcg_temp_free(tmp1);
1673 tcg_temp_free(tmp2);
1674 }
1675 break;
1676
1677 case 4: /*MINu*/
1678 case 5: /*MAXu*/
1679 case 6: /*MINUu*/
1680 case 7: /*MAXUu*/
7f65f4b0 1681 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX);
772177c1 1682 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
b8132eff
MF		 1683 {
1684 static const TCGCond cond[] = {
1685 TCG_COND_LE,
1686 TCG_COND_GE,
1687 TCG_COND_LEU,
1688 TCG_COND_GEU
1689 };
1690 int label = gen_new_label();
1691
1692 if (RRR_R != RRR_T) {
1693 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1694 tcg_gen_brcond_i32(cond[OP2 - 4],
1695 cpu_R[RRR_S], cpu_R[RRR_T], label);
1696 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1697 } else {
1698 tcg_gen_brcond_i32(cond[OP2 - 4],
1699 cpu_R[RRR_T], cpu_R[RRR_S], label);
1700 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1701 }
1702 gen_set_label(label);
1703 }
1704 break;
1705
1706 case 8: /*MOVEQZ*/
1707 case 9: /*MOVNEZ*/
1708 case 10: /*MOVLTZ*/
1709 case 11: /*MOVGEZ*/
772177c1 1710 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
b8132eff
MF		 1711 {
1712 static const TCGCond cond[] = {
1713 TCG_COND_NE,
1714 TCG_COND_EQ,
1715 TCG_COND_GE,
1716 TCG_COND_LT
1717 };
1718 int label = gen_new_label();
1719 tcg_gen_brcondi_i32(cond[OP2 - 8], cpu_R[RRR_T], 0, label);
1720 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1721 gen_set_label(label);
1722 }
1723 break;
1724
1725 case 12: /*MOVFp*/
b8132eff
MF		 1726 case 13: /*MOVTp*/
1727 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 1728 gen_window_check2(dc, RRR_R, RRR_S);
1729 {
1730 int label = gen_new_label();
1731 TCGv_i32 tmp = tcg_temp_new_i32();
1732
1733 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
1734 tcg_gen_brcondi_i32(
1735 OP2 & 1 ? TCG_COND_EQ : TCG_COND_NE,
1736 tmp, 0, label);
1737 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1738 gen_set_label(label);
1739 tcg_temp_free(tmp);
1740 }
b8132eff
MF		 1741 break;
1742
1743 case 14: /*RUR*/
772177c1 1744 gen_window_check1(dc, RRR_R);
b8132eff
MF		 1745 {
1746 int st = (RRR_S << 4) + RRR_T;
1747 if (uregnames[st]) {
1748 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1749 } else {
1750 qemu_log("RUR %d not implemented, ", st);
91a5bb76 1751 TBD();
b8132eff
MF		 1752 }
1753 }
1754 break;
1755
1756 case 15: /*WUR*/
772177c1 1757 gen_window_check1(dc, RRR_T);
b8132eff
MF		 1758 {
1759 if (uregnames[RSR_SR]) {
1760 tcg_gen_mov_i32(cpu_UR[RSR_SR], cpu_R[RRR_T]);
1761 } else {
1762 qemu_log("WUR %d not implemented, ", RSR_SR);
91a5bb76 1763 TBD();
b8132eff
MF		 1764 }
1765 }
1766 break;
1767
1768 }
dedc5eae
MF		 1769 break;
1770
1771 case 4: /*EXTUI*/
1772 case 5:
772177c1 1773 gen_window_check2(dc, RRR_R, RRR_T);
3580ecad
MF		 1774 {
1775 int shiftimm = RRR_S | (OP1 << 4);
1776 int maskimm = (1 << (OP2 + 1)) - 1;
1777
1778 TCGv_i32 tmp = tcg_temp_new_i32();
1779 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1780 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
1781 tcg_temp_free(tmp);
1782 }
dedc5eae
MF		 1783 break;
1784
1785 case 6: /*CUST0*/
91a5bb76 1786 RESERVED();
dedc5eae
MF		 1787 break;
1788
1789 case 7: /*CUST1*/
91a5bb76 1790 RESERVED();
dedc5eae
MF		 1791 break;
1792
1793 case 8: /*LSCXp*/
1794 HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
91a5bb76 1795 TBD();
dedc5eae
MF		 1796 break;
1797
1798 case 9: /*LSC4*/
772177c1 1799 gen_window_check2(dc, RRR_S, RRR_T);
553e44f9
MF		 1800 switch (OP2) {
1801 case 0: /*L32E*/
1802 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1803 gen_check_privilege(dc);
1804 {
1805 TCGv_i32 addr = tcg_temp_new_i32();
1806 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1807 (0xffffffc0 | (RRR_R << 2)));
1808 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1809 tcg_temp_free(addr);
1810 }
1811 break;
1812
1813 case 4: /*S32E*/
1814 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1815 gen_check_privilege(dc);
1816 {
1817 TCGv_i32 addr = tcg_temp_new_i32();
1818 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1819 (0xffffffc0 | (RRR_R << 2)));
1820 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1821 tcg_temp_free(addr);
1822 }
1823 break;
1824
1825 default:
1826 RESERVED();
1827 break;
1828 }
dedc5eae
MF		 1829 break;
1830
1831 case 10: /*FP0*/
1832 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
91a5bb76 1833 TBD();
dedc5eae
MF		 1834 break;
1835
1836 case 11: /*FP1*/
1837 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
91a5bb76 1838 TBD();
dedc5eae
MF		 1839 break;
1840
1841 default: /*reserved*/
91a5bb76 1842 RESERVED();
dedc5eae
MF		 1843 break;
1844 }
1845 break;
1846
1847 case 1: /*L32R*/
772177c1 1848 gen_window_check1(dc, RRR_T);
dedc5eae
MF		 1849 {
1850 TCGv_i32 tmp = tcg_const_i32(
6ad6dbf7
MF		 1851 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
1852 0 : ((dc->pc + 3) & ~3)) +
1853 (0xfffc0000 | (RI16_IMM16 << 2)));
dedc5eae 1854
6ad6dbf7
MF		 1855 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
1856 tcg_gen_add_i32(tmp, tmp, dc->litbase);
1857 }
f0a548b9 1858 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
dedc5eae
MF		 1859 tcg_temp_free(tmp);
1860 }
1861 break;
1862
1863 case 2: /*LSAI*/
809377aa
MF		 1864#define gen_load_store(type, shift) do { \
1865 TCGv_i32 addr = tcg_temp_new_i32(); \
772177c1 1866 gen_window_check2(dc, RRI8_S, RRI8_T); \
809377aa 1867 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
5b4e481b
MF		 1868 if (shift) { \
1869 gen_load_store_alignment(dc, shift, addr, false); \
1870 } \
f0a548b9 1871 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
809377aa
MF		 1872 tcg_temp_free(addr); \
1873 } while (0)
1874
1875 switch (RRI8_R) {
1876 case 0: /*L8UI*/
1877 gen_load_store(ld8u, 0);
1878 break;
1879
1880 case 1: /*L16UI*/
1881 gen_load_store(ld16u, 1);
1882 break;
1883
1884 case 2: /*L32I*/
1885 gen_load_store(ld32u, 2);
1886 break;
1887
1888 case 4: /*S8I*/
1889 gen_load_store(st8, 0);
1890 break;
1891
1892 case 5: /*S16I*/
1893 gen_load_store(st16, 1);
1894 break;
1895
1896 case 6: /*S32I*/
1897 gen_load_store(st32, 2);
1898 break;
1899
1900 case 7: /*CACHEc*/
8ffc2d0d
MF		 1901 if (RRI8_T < 8) {
1902 HAS_OPTION(XTENSA_OPTION_DCACHE);
1903 }
1904
1905 switch (RRI8_T) {
1906 case 0: /*DPFRc*/
1907 break;
1908
1909 case 1: /*DPFWc*/
1910 break;
1911
1912 case 2: /*DPFROc*/
1913 break;
1914
1915 case 3: /*DPFWOc*/
1916 break;
1917
1918 case 4: /*DHWBc*/
1919 break;
1920
1921 case 5: /*DHWBIc*/
1922 break;
1923
1924 case 6: /*DHIc*/
1925 break;
1926
1927 case 7: /*DIIc*/
1928 break;
1929
1930 case 8: /*DCEc*/
1931 switch (OP1) {
1932 case 0: /*DPFLl*/
1933 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1934 break;
1935
1936 case 2: /*DHUl*/
1937 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1938 break;
1939
1940 case 3: /*DIUl*/
1941 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1942 break;
1943
1944 case 4: /*DIWBc*/
1945 HAS_OPTION(XTENSA_OPTION_DCACHE);
1946 break;
1947
1948 case 5: /*DIWBIc*/
1949 HAS_OPTION(XTENSA_OPTION_DCACHE);
1950 break;
1951
1952 default: /*reserved*/
1953 RESERVED();
1954 break;
1955
1956 }
1957 break;
1958
1959 case 12: /*IPFc*/
1960 HAS_OPTION(XTENSA_OPTION_ICACHE);
1961 break;
1962
1963 case 13: /*ICEc*/
1964 switch (OP1) {
1965 case 0: /*IPFLl*/
1966 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1967 break;
1968
1969 case 2: /*IHUl*/
1970 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1971 break;
1972
1973 case 3: /*IIUl*/
1974 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1975 break;
1976
1977 default: /*reserved*/
1978 RESERVED();
1979 break;
1980 }
1981 break;
1982
1983 case 14: /*IHIc*/
1984 HAS_OPTION(XTENSA_OPTION_ICACHE);
1985 break;
1986
1987 case 15: /*IIIc*/
1988 HAS_OPTION(XTENSA_OPTION_ICACHE);
1989 break;
1990
1991 default: /*reserved*/
1992 RESERVED();
1993 break;
1994 }
809377aa
MF		 1995 break;
1996
1997 case 9: /*L16SI*/
1998 gen_load_store(ld16s, 1);
1999 break;
5b4e481b 2000#undef gen_load_store
809377aa
MF		 2001
2002 case 10: /*MOVI*/
772177c1 2003 gen_window_check1(dc, RRI8_T);
809377aa
MF		 2004 tcg_gen_movi_i32(cpu_R[RRI8_T],
2005 RRI8_IMM8 | (RRI8_S << 8) |
2006 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
2007 break;
2008
5b4e481b
MF		 2009#define gen_load_store_no_hw_align(type) do { \
2010 TCGv_i32 addr = tcg_temp_local_new_i32(); \
772177c1 2011 gen_window_check2(dc, RRI8_S, RRI8_T); \
5b4e481b
MF		 2012 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2013 gen_load_store_alignment(dc, 2, addr, true); \
2014 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2015 tcg_temp_free(addr); \
2016 } while (0)
2017
809377aa
MF		 2018 case 11: /*L32AIy*/
2019 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 2020 gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
809377aa
MF		 2021 break;
2022
2023 case 12: /*ADDI*/
772177c1 2024 gen_window_check2(dc, RRI8_S, RRI8_T);
809377aa
MF		 2025 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
2026 break;
2027
2028 case 13: /*ADDMI*/
772177c1 2029 gen_window_check2(dc, RRI8_S, RRI8_T);
809377aa
MF		 2030 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE << 8);
2031 break;
2032
2033 case 14: /*S32C1Iy*/
7f65f4b0 2034 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
772177c1 2035 gen_window_check2(dc, RRI8_S, RRI8_T);
809377aa
MF		 2036 {
2037 int label = gen_new_label();
2038 TCGv_i32 tmp = tcg_temp_local_new_i32();
2039 TCGv_i32 addr = tcg_temp_local_new_i32();
2040
2041 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
2042 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
5b4e481b 2043 gen_load_store_alignment(dc, 2, addr, true);
f0a548b9 2044 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
809377aa
MF		 2045 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
2046 cpu_SR[SCOMPARE1], label);
2047
f0a548b9 2048 tcg_gen_qemu_st32(tmp, addr, dc->cring);
809377aa
MF		 2049
2050 gen_set_label(label);
2051 tcg_temp_free(addr);
2052 tcg_temp_free(tmp);
2053 }
2054 break;
2055
2056 case 15: /*S32RIy*/
2057 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 2058 gen_load_store_no_hw_align(st32); /*TODO release?*/
809377aa 2059 break;
5b4e481b 2060#undef gen_load_store_no_hw_align
809377aa
MF		 2061
2062 default: /*reserved*/
91a5bb76 2063 RESERVED();
809377aa
MF		 2064 break;
2065 }
dedc5eae
MF		 2066 break;
2067
2068 case 3: /*LSCIp*/
2069 HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
91a5bb76 2070 TBD();
dedc5eae
MF		 2071 break;
2072
2073 case 4: /*MAC16d*/
2074 HAS_OPTION(XTENSA_OPTION_MAC16);
6825b6c3
MF		 2075 {
2076 enum {
2077 MAC16_UMUL = 0x0,
2078 MAC16_MUL = 0x4,
2079 MAC16_MULA = 0x8,
2080 MAC16_MULS = 0xc,
2081 MAC16_NONE = 0xf,
2082 } op = OP1 & 0xc;
2083 bool is_m1_sr = (OP2 & 0x3) == 2;
2084 bool is_m2_sr = (OP2 & 0xc) == 0;
2085 uint32_t ld_offset = 0;
2086
2087 if (OP2 > 9) {
2088 RESERVED();
2089 }
2090
2091 switch (OP2 & 2) {
2092 case 0: /*MACI?/MACC?*/
2093 is_m1_sr = true;
2094 ld_offset = (OP2 & 1) ? -4 : 4;
2095
2096 if (OP2 >= 8) { /*MACI/MACC*/
2097 if (OP1 == 0) { /*LDINC/LDDEC*/
2098 op = MAC16_NONE;
2099 } else {
2100 RESERVED();
2101 }
2102 } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/
2103 RESERVED();
2104 }
2105 break;
2106
2107 case 2: /*MACD?/MACA?*/
2108 if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/
2109 RESERVED();
2110 }
2111 break;
2112 }
2113
2114 if (op != MAC16_NONE) {
2115 if (!is_m1_sr) {
2116 gen_window_check1(dc, RRR_S);
2117 }
2118 if (!is_m2_sr) {
2119 gen_window_check1(dc, RRR_T);
2120 }
2121 }
2122
2123 {
2124 TCGv_i32 vaddr = tcg_temp_new_i32();
2125 TCGv_i32 mem32 = tcg_temp_new_i32();
2126
2127 if (ld_offset) {
2128 gen_window_check1(dc, RRR_S);
2129 tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset);
2130 gen_load_store_alignment(dc, 2, vaddr, false);
2131 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
2132 }
2133 if (op != MAC16_NONE) {
2134 TCGv_i32 m1 = gen_mac16_m(
2135 is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S],
2136 OP1 & 1, op == MAC16_UMUL);
2137 TCGv_i32 m2 = gen_mac16_m(
2138 is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T],
2139 OP1 & 2, op == MAC16_UMUL);
2140
2141 if (op == MAC16_MUL || op == MAC16_UMUL) {
2142 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
2143 if (op == MAC16_UMUL) {
2144 tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
2145 } else {
2146 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
2147 }
2148 } else {
2149 TCGv_i32 res = tcg_temp_new_i32();
2150 TCGv_i64 res64 = tcg_temp_new_i64();
2151 TCGv_i64 tmp = tcg_temp_new_i64();
2152
2153 tcg_gen_mul_i32(res, m1, m2);
2154 tcg_gen_ext_i32_i64(res64, res);
2155 tcg_gen_concat_i32_i64(tmp,
2156 cpu_SR[ACCLO], cpu_SR[ACCHI]);
2157 if (op == MAC16_MULA) {
2158 tcg_gen_add_i64(tmp, tmp, res64);
2159 } else {
2160 tcg_gen_sub_i64(tmp, tmp, res64);
2161 }
2162 tcg_gen_trunc_i64_i32(cpu_SR[ACCLO], tmp);
2163 tcg_gen_shri_i64(tmp, tmp, 32);
2164 tcg_gen_trunc_i64_i32(cpu_SR[ACCHI], tmp);
2165 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
2166
2167 tcg_temp_free(res);
2168 tcg_temp_free_i64(res64);
2169 tcg_temp_free_i64(tmp);
2170 }
2171 tcg_temp_free(m1);
2172 tcg_temp_free(m2);
2173 }
2174 if (ld_offset) {
2175 tcg_gen_mov_i32(cpu_R[RRR_S], vaddr);
2176 tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32);
2177 }
2178 tcg_temp_free(vaddr);
2179 tcg_temp_free(mem32);
2180 }
2181 }
dedc5eae
MF		 2182 break;
2183
2184 case 5: /*CALLN*/
2185 switch (CALL_N) {
2186 case 0: /*CALL0*/
2187 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
2188 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2189 break;
2190
2191 case 1: /*CALL4w*/
2192 case 2: /*CALL8w*/
2193 case 3: /*CALL12w*/
2194 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
772177c1 2195 gen_window_check1(dc, CALL_N << 2);
553e44f9
MF		 2196 gen_callwi(dc, CALL_N,
2197 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
dedc5eae
MF		 2198 break;
2199 }
2200 break;
2201
2202 case 6: /*SI*/
2203 switch (CALL_N) {
2204 case 0: /*J*/
2205 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
2206 break;
2207
bd57fb91 2208 case 1: /*BZ*/
772177c1 2209 gen_window_check1(dc, BRI12_S);
bd57fb91
MF		 2210 {
2211 static const TCGCond cond[] = {
2212 TCG_COND_EQ, /*BEQZ*/
2213 TCG_COND_NE, /*BNEZ*/
2214 TCG_COND_LT, /*BLTZ*/
2215 TCG_COND_GE, /*BGEZ*/
2216 };
2217
2218 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
2219 4 + BRI12_IMM12_SE);
2220 }
2221 break;
2222
2223 case 2: /*BI0*/
772177c1 2224 gen_window_check1(dc, BRI8_S);
bd57fb91
MF		 2225 {
2226 static const TCGCond cond[] = {
2227 TCG_COND_EQ, /*BEQI*/
2228 TCG_COND_NE, /*BNEI*/
2229 TCG_COND_LT, /*BLTI*/
2230 TCG_COND_GE, /*BGEI*/
2231 };
2232
2233 gen_brcondi(dc, cond[BRI8_M & 3],
2234 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
2235 }
2236 break;
2237
2238 case 3: /*BI1*/
2239 switch (BRI8_M) {
2240 case 0: /*ENTRYw*/
2241 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 2242 {
2243 TCGv_i32 pc = tcg_const_i32(dc->pc);
2244 TCGv_i32 s = tcg_const_i32(BRI12_S);
2245 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
b994e91b 2246 gen_advance_ccount(dc);
553e44f9
MF		 2247 gen_helper_entry(pc, s, imm);
2248 tcg_temp_free(imm);
2249 tcg_temp_free(s);
2250 tcg_temp_free(pc);
772177c1 2251 reset_used_window(dc);
553e44f9 2252 }
bd57fb91
MF		 2253 break;
2254
2255 case 1: /*B1*/
2256 switch (BRI8_R) {
2257 case 0: /*BFp*/
bd57fb91
MF		 2258 case 1: /*BTp*/
2259 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 2260 {
2261 TCGv_i32 tmp = tcg_temp_new_i32();
2262 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
2263 gen_brcondi(dc,
2264 BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
2265 tmp, 0, 4 + RRI8_IMM8_SE);
2266 tcg_temp_free(tmp);
2267 }
bd57fb91
MF		 2268 break;
2269
2270 case 8: /*LOOP*/
bd57fb91 2271 case 9: /*LOOPNEZ*/
bd57fb91 2272 case 10: /*LOOPGTZ*/
797d780b 2273 HAS_OPTION(XTENSA_OPTION_LOOP);
772177c1 2274 gen_window_check1(dc, RRI8_S);
797d780b
MF		 2275 {
2276 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
2277 TCGv_i32 tmp = tcg_const_i32(lend);
2278
2279 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
2280 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
b18b37f7 2281 gen_helper_wsr_lend(tmp);
797d780b
MF		 2282 tcg_temp_free(tmp);
2283
2284 if (BRI8_R > 8) {
2285 int label = gen_new_label();
2286 tcg_gen_brcondi_i32(
2287 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
2288 cpu_R[RRI8_S], 0, label);
2289 gen_jumpi(dc, lend, 1);
2290 gen_set_label(label);
2291 }
2292
2293 gen_jumpi(dc, dc->next_pc, 0);
2294 }
bd57fb91
MF		 2295 break;
2296
2297 default: /*reserved*/
91a5bb76 2298 RESERVED();
bd57fb91
MF		 2299 break;
2300
2301 }
2302 break;
2303
2304 case 2: /*BLTUI*/
2305 case 3: /*BGEUI*/
772177c1 2306 gen_window_check1(dc, BRI8_S);
bd57fb91
MF		 2307 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
2308 cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
2309 break;
2310 }
2311 break;
2312
dedc5eae
MF		 2313 }
2314 break;
2315
2316 case 7: /*B*/
bd57fb91
MF		 2317 {
2318 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
2319
2320 switch (RRI8_R & 7) {
2321 case 0: /*BNONE*/ /*BANY*/
772177c1 2322 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2323 {
2324 TCGv_i32 tmp = tcg_temp_new_i32();
2325 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2326 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2327 tcg_temp_free(tmp);
2328 }
2329 break;
2330
2331 case 1: /*BEQ*/ /*BNE*/
2332 case 2: /*BLT*/ /*BGE*/
2333 case 3: /*BLTU*/ /*BGEU*/
772177c1 2334 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2335 {
2336 static const TCGCond cond[] = {
2337 [1] = TCG_COND_EQ,
2338 [2] = TCG_COND_LT,
2339 [3] = TCG_COND_LTU,
2340 [9] = TCG_COND_NE,
2341 [10] = TCG_COND_GE,
2342 [11] = TCG_COND_GEU,
2343 };
2344 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
2345 4 + RRI8_IMM8_SE);
2346 }
2347 break;
2348
2349 case 4: /*BALL*/ /*BNALL*/
772177c1 2350 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2351 {
2352 TCGv_i32 tmp = tcg_temp_new_i32();
2353 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2354 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
2355 4 + RRI8_IMM8_SE);
2356 tcg_temp_free(tmp);
2357 }
2358 break;
2359
2360 case 5: /*BBC*/ /*BBS*/
772177c1 2361 gen_window_check2(dc, RRI8_S, RRI8_T);
bd57fb91
MF		 2362 {
2363 TCGv_i32 bit = tcg_const_i32(1);
2364 TCGv_i32 tmp = tcg_temp_new_i32();
2365 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
2366 tcg_gen_shl_i32(bit, bit, tmp);
2367 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
2368 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2369 tcg_temp_free(tmp);
2370 tcg_temp_free(bit);
2371 }
2372 break;
2373
2374 case 6: /*BBCI*/ /*BBSI*/
2375 case 7:
772177c1 2376 gen_window_check1(dc, RRI8_S);
bd57fb91
MF		 2377 {
2378 TCGv_i32 tmp = tcg_temp_new_i32();
2379 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
2380 1 << (((RRI8_R & 1) << 4) | RRI8_T));
2381 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2382 tcg_temp_free(tmp);
2383 }
2384 break;
2385
2386 }
2387 }
dedc5eae
MF		 2388 break;
2389
67882fd1
MF		 2390#define gen_narrow_load_store(type) do { \
2391 TCGv_i32 addr = tcg_temp_new_i32(); \
772177c1 2392 gen_window_check2(dc, RRRN_S, RRRN_T); \
67882fd1 2393 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
5b4e481b 2394 gen_load_store_alignment(dc, 2, addr, false); \
f0a548b9 2395 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
67882fd1
MF		 2396 tcg_temp_free(addr); \
2397 } while (0)
2398
dedc5eae 2399 case 8: /*L32I.Nn*/
67882fd1 2400 gen_narrow_load_store(ld32u);
dedc5eae
MF		 2401 break;
2402
2403 case 9: /*S32I.Nn*/
67882fd1 2404 gen_narrow_load_store(st32);
dedc5eae 2405 break;
67882fd1 2406#undef gen_narrow_load_store
dedc5eae
MF		 2407
2408 case 10: /*ADD.Nn*/
772177c1 2409 gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T);
67882fd1 2410 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
dedc5eae
MF		 2411 break;
2412
2413 case 11: /*ADDI.Nn*/
772177c1 2414 gen_window_check2(dc, RRRN_R, RRRN_S);
67882fd1 2415 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
dedc5eae
MF		 2416 break;
2417
2418 case 12: /*ST2n*/
772177c1 2419 gen_window_check1(dc, RRRN_S);
67882fd1
MF		 2420 if (RRRN_T < 8) { /*MOVI.Nn*/
2421 tcg_gen_movi_i32(cpu_R[RRRN_S],
2422 RRRN_R | (RRRN_T << 4) |
2423 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
2424 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
bd57fb91
MF		 2425 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
2426
2427 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
2428 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
67882fd1 2429 }
dedc5eae
MF		 2430 break;
2431
2432 case 13: /*ST3n*/
67882fd1
MF		 2433 switch (RRRN_R) {
2434 case 0: /*MOV.Nn*/
772177c1 2435 gen_window_check2(dc, RRRN_S, RRRN_T);
67882fd1
MF		 2436 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
2437 break;
2438
2439 case 15: /*S3*/
2440 switch (RRRN_T) {
2441 case 0: /*RET.Nn*/
2442 gen_jump(dc, cpu_R[0]);
2443 break;
2444
2445 case 1: /*RETW.Nn*/
91a5bb76 2446 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 2447 {
2448 TCGv_i32 tmp = tcg_const_i32(dc->pc);
b994e91b 2449 gen_advance_ccount(dc);
553e44f9
MF		 2450 gen_helper_retw(tmp, tmp);
2451 gen_jump(dc, tmp);
2452 tcg_temp_free(tmp);
2453 }
67882fd1
MF		 2454 break;
2455
2456 case 2: /*BREAK.Nn*/
e61dc8f7
MF		 2457 HAS_OPTION(XTENSA_OPTION_DEBUG);
2458 if (dc->debug) {
2459 gen_debug_exception(dc, DEBUGCAUSE_BN);
2460 }
67882fd1
MF		 2461 break;
2462
2463 case 3: /*NOP.Nn*/
2464 break;
2465
2466 case 6: /*ILL.Nn*/
40643d7c 2467 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
67882fd1
MF		 2468 break;
2469
2470 default: /*reserved*/
91a5bb76 2471 RESERVED();
67882fd1
MF		 2472 break;
2473 }
2474 break;
2475
2476 default: /*reserved*/
91a5bb76 2477 RESERVED();
67882fd1
MF		 2478 break;
2479 }
dedc5eae
MF		 2480 break;
2481
2482 default: /*reserved*/
91a5bb76 2483 RESERVED();
dedc5eae
MF		 2484 break;
2485 }
2486
797d780b 2487 gen_check_loop_end(dc, 0);
dedc5eae 2488 dc->pc = dc->next_pc;
797d780b 2489
dedc5eae
MF		 2490 return;
2491
2492invalid_opcode:
2493 qemu_log("INVALID(pc = %08x)\n", dc->pc);
6b814719 2494 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
dedc5eae
MF		 2495#undef HAS_OPTION
2496}
2497
97129ac8 2498static void check_breakpoint(CPUXtensaState *env, DisasContext *dc)
dedc5eae
MF		 2499{
2500 CPUBreakpoint *bp;
2501
2502 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
2503 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
2504 if (bp->pc == dc->pc) {
2505 tcg_gen_movi_i32(cpu_pc, dc->pc);
b994e91b 2506 gen_exception(dc, EXCP_DEBUG);
dedc5eae
MF		 2507 dc->is_jmp = DISAS_UPDATE;
2508 }
2509 }
2510 }
2511}
2512
97129ac8 2513static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
e61dc8f7
MF		 2514{
2515 unsigned i;
2516
2517 for (i = 0; i < dc->config->nibreak; ++i) {
2518 if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
2519 env->sregs[IBREAKA + i] == dc->pc) {
2520 gen_debug_exception(dc, DEBUGCAUSE_IB);
2521 break;
2522 }
2523 }
2524}
2525
dedc5eae 2526static void gen_intermediate_code_internal(
97129ac8 2527 CPUXtensaState *env, TranslationBlock *tb, int search_pc)
dedc5eae
MF		 2528{
2529 DisasContext dc;
2530 int insn_count = 0;
2531 int j, lj = -1;
2532 uint16_t *gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2533 int max_insns = tb->cflags & CF_COUNT_MASK;
2534 uint32_t pc_start = tb->pc;
2535 uint32_t next_page_start =
2536 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2537
2538 if (max_insns == 0) {
2539 max_insns = CF_COUNT_MASK;
2540 }
2541
2542 dc.config = env->config;
2543 dc.singlestep_enabled = env->singlestep_enabled;
2544 dc.tb = tb;
2545 dc.pc = pc_start;
f0a548b9
MF		 2546 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
2547 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
797d780b
MF		 2548 dc.lbeg = env->sregs[LBEG];
2549 dc.lend = env->sregs[LEND];
dedc5eae 2550 dc.is_jmp = DISAS_NEXT;
b994e91b 2551 dc.ccount_delta = 0;
e61dc8f7 2552 dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG;
35b5c044 2553 dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
dedc5eae 2554
6ad6dbf7 2555 init_litbase(&dc);
3580ecad 2556 init_sar_tracker(&dc);
772177c1 2557 reset_used_window(&dc);
35b5c044
MF		 2558 if (dc.icount) {
2559 dc.next_icount = tcg_temp_local_new_i32();
2560 }
3580ecad 2561
dedc5eae
MF		 2562 gen_icount_start();
2563
40643d7c
MF		 2564 if (env->singlestep_enabled && env->exception_taken) {
2565 env->exception_taken = 0;
2566 tcg_gen_movi_i32(cpu_pc, dc.pc);
b994e91b 2567 gen_exception(&dc, EXCP_DEBUG);
40643d7c
MF		 2568 }
2569
dedc5eae
MF		 2570 do {
2571 check_breakpoint(env, &dc);
2572
2573 if (search_pc) {
2574 j = gen_opc_ptr - gen_opc_buf;
2575 if (lj < j) {
2576 lj++;
2577 while (lj < j) {
2578 gen_opc_instr_start[lj++] = 0;
2579 }
2580 }
2581 gen_opc_pc[lj] = dc.pc;
2582 gen_opc_instr_start[lj] = 1;
2583 gen_opc_icount[lj] = insn_count;
2584 }
2585
2586 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
2587 tcg_gen_debug_insn_start(dc.pc);
2588 }
2589
b994e91b
MF		 2590 ++dc.ccount_delta;
2591
2592 if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
2593 gen_io_start();
2594 }
2595
35b5c044
MF		 2596 if (dc.icount) {
2597 int label = gen_new_label();
2598
2599 tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1);
2600 tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label);
2601 tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]);
2602 if (dc.debug) {
2603 gen_debug_exception(&dc, DEBUGCAUSE_IC);
2604 }
2605 gen_set_label(label);
2606 }
2607
e61dc8f7
MF		 2608 if (dc.debug) {
2609 gen_ibreak_check(env, &dc);
2610 }
2611
dedc5eae
MF		 2612 disas_xtensa_insn(&dc);
2613 ++insn_count;
35b5c044
MF		 2614 if (dc.icount) {
2615 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
2616 }
dedc5eae
MF		 2617 if (env->singlestep_enabled) {
2618 tcg_gen_movi_i32(cpu_pc, dc.pc);
b994e91b 2619 gen_exception(&dc, EXCP_DEBUG);
dedc5eae
MF		 2620 break;
2621 }
2622 } while (dc.is_jmp == DISAS_NEXT &&
2623 insn_count < max_insns &&
2624 dc.pc < next_page_start &&
2625 gen_opc_ptr < gen_opc_end);
2626
6ad6dbf7 2627 reset_litbase(&dc);
3580ecad 2628 reset_sar_tracker(&dc);
35b5c044
MF		 2629 if (dc.icount) {
2630 tcg_temp_free(dc.next_icount);
2631 }
3580ecad 2632
b994e91b
MF		 2633 if (tb->cflags & CF_LAST_IO) {
2634 gen_io_end();
2635 }
2636
dedc5eae
MF		 2637 if (dc.is_jmp == DISAS_NEXT) {
2638 gen_jumpi(&dc, dc.pc, 0);
2639 }
2640 gen_icount_end(tb, insn_count);
2641 *gen_opc_ptr = INDEX_op_end;
2642
2643 if (!search_pc) {
2644 tb->size = dc.pc - pc_start;
2645 tb->icount = insn_count;
2646 }
2328826b
MF		 2647}
2648
97129ac8 2649void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
2328826b 2650{
dedc5eae 2651 gen_intermediate_code_internal(env, tb, 0);
2328826b
MF		 2652}
2653
97129ac8 2654void gen_intermediate_code_pc(CPUXtensaState *env, TranslationBlock *tb)
2328826b 2655{
dedc5eae 2656 gen_intermediate_code_internal(env, tb, 1);
2328826b
MF		 2657}
2658
97129ac8 2659void cpu_dump_state(CPUXtensaState *env, FILE *f, fprintf_function cpu_fprintf,
2328826b
MF		 2660 int flags)
2661{
2af3da91
MF		 2662 int i, j;
2663
2664 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
2665
2666 for (i = j = 0; i < 256; ++i) {
2667 if (sregnames[i]) {
2668 cpu_fprintf(f, "%s=%08x%c", sregnames[i], env->sregs[i],
2669 (j++ % 4) == 3 ? '\n' : ' ');
2670 }
2671 }
2672
2673 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2674
2675 for (i = j = 0; i < 256; ++i) {
2676 if (uregnames[i]) {
2677 cpu_fprintf(f, "%s=%08x%c", uregnames[i], env->uregs[i],
2678 (j++ % 4) == 3 ? '\n' : ' ');
2679 }
2680 }
2328826b 2681
2af3da91 2682 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2328826b
MF		 2683
2684 for (i = 0; i < 16; ++i) {
2685 cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
2686 (i % 4) == 3 ? '\n' : ' ');
2687 }
553e44f9
MF		 2688
2689 cpu_fprintf(f, "\n");
2690
2691 for (i = 0; i < env->config->nareg; ++i) {
2692 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
2693 (i % 4) == 3 ? '\n' : ' ');
2694 }
2328826b
MF		 2695}
2696
97129ac8 2697void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, int pc_pos)
2328826b
MF		 2698{
2699 env->pc = gen_opc_pc[pc_pos];
2700}
Qemu copy for testing